Beruflich Dokumente
Kultur Dokumente
IGT30
Compal confidential
Schematics Document
Mobile Merom uFCPGA with Intel
Crestline_GM/PM+ICH8-M core logic
Security Classification
2006/08/04
Issued Date
2006/10/06
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
Rev
0.1
Date:
Sheet
E
of
47
ZZZ1
Compal confidential
LEDs Board
14W_PCB
Mobile Merom
uFCPGA-478 CPU
LVDS
Connector
Clock Gen.
ICS9LPRS355
page4,5,6
Nvidia N8M
page15
H_A#(3..35)
FSB
H_D#(0..63)
667/800MHz
PCI-E X16
DDR2 -667
PCBGA 1299
LVDS
Connector
BANK 0, 1, 2, 3
MO DEM
Ver 1.5 page
page7,8,9,10,11,12
DMI
page16
page 13,14
Dual Channel
LVDS I/F
page17
DDR2-SO-DIMM X2
28
C-Line
AMP&Audio Jack
page30
AZALIA
PCI Express
Mini card Slot
page28
PCI-E BUS
USB2.0
Intel ICH8-M
Audio Codec
ALC 262H
mBGA-676
3.3V / 33 MHz
page29
SATA
PCI BUS
page19,20,21,22
ATA100
Finger printer
page36
BCM5906 BCM5787
10/100/1G LAN
1394+Card Reader
CMOS Camera
RICOH R5C832
page27
LPC BUS
page26
page36
BlueTooth Conn
page28
1394 Conn
RJ45 CONN
page27
SUB Board
page26
Card reader(XD/SD
MMC/MS/MS-Pro
HD SD)
page26
EC
ENE KB925/KB926
USB conn X4
page31
page33
page32,36
*RJ45 CONN
*RJ11 CONN
*MIC IN JACK
*HP OUT JACK
*LED
*SWITCH
USB 3G
page31
*1394 CONN
*DC JACK
*TVOUT CONN
*USB CONN
*SWITCH
Touch Pad
Int.KBD
page32
BIOS
USB Board
page32
SATA HDD
Connector page23
page34
PATA CDROM
Connector page23
Security Classification
TP Board
2006/08/04
Issued Date
2006/10/06
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
Rev
0.1
Sheet
of
47
Voltage Rails
O MEANS ON
SKU ID Table
X MEANS OFF
power
plane
+B
LDO3
+5VALW
+1.8V
LDO5
+3VALW
+5V
+0.9V
State
+5VS
Vcc
Ra
+3VS
Board ID
+2.5VS
* 0
+1.8VS
1
2
3
4
5
6
7
+1.5VS
CLOCK
+1.25VS
+VGA_CORE
+CPU_CORE
+VCCP
S0
S3
S5 S4/AC
O MEANS ON
3.3V +/- 5%
100K +/- 5%
Rb
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC
BOM Structure
V AD_BID typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V
IDSEL#
AD22
MARK
REQ#/GNT#
0
Interrupts
NC FOR ALL
GIGA@
PIRQG/H
FUNCTION
BCM5787
100@
BCM5906
UMA@
Internal 965GM
VGA@
0
1
2
3
4
5
6
7
8
9
Address
EC SM Bus1 address
Device
V AD_BID max
0 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V
S3 : STR
S4 : STD
S5 : SOFT OFF
X MEANS OFF
Device
V AD_BID min
0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V
EC SM Bus2 address
Address
Device
Address
Smart Battery
0001 011X b
ADM1032
1001 100X b
EEPROM(24C16/02)
1010 000X b
DEVICE
LEFT SIDE
WIRELESS
RIGHT SIDE
CMOS
RIGHT SIDE
NEW CARD
BT(HDL20)
3G
Address
Clock Generator
( ICS954226)
1101 001Xb
DDRII DIMM0
1010 000Xb
DDRII DIMM1
1010 010Xb
Security Classification
2006/08/04
Issued Date
Deciphered Date
2006/10/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
Rev
0.1
Sheet
of
47
+3VS
XDP Reserve
XDP_DBRESET#
XDP_TDI
R158 1
150_0402_1%
R159 1
39_0402_1%
XDP_TDO
R163 1
2 @ 54.9_0402_1%
XDP_BPM#5
R162 1
XDP_HOOK1
R161 1
2 @ 54.9_0402_1%
XDP_TRST#
R155 1
560_0402_5%
XDP_TCK
R156 1
27_0402_5%
20
20
20
20
H_STPCLK#
H_INTR
H_NMI
H_SMI#
H_A20M#
H_FERR#
H_IGNNE#
A6
A5
C4
A20M#
FERR#
IGNNE#
H_STPCLK#
H_INTR
H_NMI
H_SMI#
D5
C6
B4
A3
STPCLK#
LINT0
LINT1
SMI#
M4
N5
T2
V3
B2
C3
D2
D22
D3
F6
RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]
RSVD[10]
H_BR0#
D20
B3
H_IERR#
H_INIT#
LOCK#
H4
H_LOCK#
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
C1
F3
F4
G3
G2
H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
HIT#
HITM#
G6
E4
H_HIT#
H_HITM#
CONTROL
A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#
H_DEFER# 7
H_DRDY# 7
H_DBSY# 7
H_BR0#
H_INIT#
R92
56_0402_5%
2
1
+VCCP
20
H_LOCK# 7
H_RESET# 7
H_RS#0 7
H_RS#1 7
H_RS#2 7
H_TRDY# 7
H_HIT# 7
H_HITM# 7
T17
T6
T13
T15
T12
T14
T7
T9
T16
T11
T5
XDP_DBRESET# 21
+3VS
C535
1
H_PROCHOT#
THERMAL
PROCHOT#
THERMDA
THERMDC
THERMTRIP#
D21
A24
B25
H_THERMDA
H_THERMDC
C7
H_THERMTRIP#
A22
A21
CLK_CPU_BCLK
CLK_CPU_BCLK#
H CLK
BCLK[0]
BCLK[1]
2
R87
1
56_0402_5%
R445
10K_0402_5%
0.1U_0402_16V4Z
U24
H_THERMDA
C536
1
2
33 EC_SMB_CK2
ICH
H_ADSTB#1
H_A20M#
H_FERR#
H_IGNNE#
Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1
F1
IERR#
INIT#
BR0#
ADDR GROUP 1
7
20
20
20
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1
H_DEFER#
H_DRD Y#
H_DBSY#
H_ADS# 7
H_BNR# 7
H_BPRI# 7
REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#
H5
F21
E1
54.9_0402_1%
H_PROCHOT# 45
+VCCP
H_THERMDC
2200P_0402_50V7K
EC_SMB_CK2
EC_SMB_DA2
33 EC_SMB_DA2
D+
D-
SCLK
VDD1
ALERT#
THERM#
GND
SDATA
THERM_SCI#
K3
H2
K2
J3
L1
DEFER#
DRDY#
DBSY#
H_ADS#
H_BNR#
H_BPRI#
2
R442
THERM#
2
10K_0402_5%
1
EC_THERM# 21,33
@ 0_0402_5%
1
+3VS
R448
Check : to sb
G781F_SOP8
Address:100_1100
H_THERMTRIP# 7,20
CLK_CPU_BCLK 15
CLK_CPU_BCLK# 15
FAN1 Conn
+5VS
+5VS
1
C528
2
10U_1206_16V4Z
U23
33
EN_FAN1
1
2
3
4
+VCC_FAN1
EN_FAN1
VEN
VIN
VO
VSET
GND
GND
GND
GND
D17
@ 1SS355_SOD323
8
7
6
5
D18
@ 1N4148_SOT23
1
2
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
ADS#
BNR#
BPRI#
XDP/ITP SIGNALS
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#[17..35]
A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#
H1
E2
G5
RESERVED
H_ADSTB#0
J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1
ADDR GROUP 0
7
7
7
7
7
7
7
JP1A
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0
+VCCP
H_A#[3..16]
1
R157
XDP_TMS
D
2 @ 1K_0402_5%
G993P1UF_SOP8
C532
10U_1206_16V4Z
1
2
+3VS
C529
1000P_0402_50V7K
1
2
+VCCP
R427
10K_0402_5%
R85
2
40mil
@ 56_0402_5%
2 2
H_PROCHOT#
3
1 OCP#
@ Q4
MMBT3904_SOT23
C
OCP#
21
1
2
3
C531
1000P_0402_50V7K
ACES_85205-03001
ME@
2006/08/04
Issued Date
2006/10/06
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
Security Classification
JP61
+VCC_FAN1
33 FAN_SPEED1
Title
Rev
0.1
Sheet
of
47
+CPU_CORE
15
15
15
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
AD26
C23
D25
C24
AF26
AF1
A26
GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
B22
B23
C21
BSEL[0]
BSEL[1]
BSEL[2]
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3
COMP[0]
COMP[1]
COMP[2]
COMP[3]
R26
U26
AA1
Y1
COMP0
COMP1
COMP2
COMP3
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
E5
B5
D24
D6
D7
AE6
H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PW RGOOD
H_CPUSLP#
H_PSI#
DATA GRP 2
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
MISC
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs
CPU_BSEL
CPU_BSEL2
CPU_BSEL1
CPU_BSEL0
166
200
H_DSTBN#2 7
H_DSTBP#2 7
H_DINV#2 7
H_D#[48..63] 7
H_DSTBN#3 7
H_DSTBP#3 7
H_DINV#3 7
H_DPRSTP# 7,20,45
H_DPSLP# 20
H_DPWR# 7
H_PWRGOOD 20
H_CPUSLP# 7
H_PSI#
45
A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18
VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
VCCA[01]
VCCA[02]
B26
C26
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
AD6
AF5
AE5
AF4
AE3
AF3
AE2
VCCSENSE
AF7
VCCSENSE
VCCSENSE 45
VSSSENSE
AE7
VSSSENSE
VSSSENSE 45
0_0402_5%
1
1
0_0402_5%
1
C214
330U_D2E_2.5VM_R7
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
45
45
45
45
45
45
45
+1.5VS
0.01U_0402_16V7K
+CPU_GTLREF
TEST1
2 @ 1K_0402_5%
TEST2
2 @ 1K_0402_5%
TEST3
T4
@ 0.1U_0402_16V4Z
TEST4
2
TEST5
T8
TEST6
T3
1
1
C237
D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2
C231
R94
R93
N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24
Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
R97
27.4_0402_1%
2
1
H_DSTBN#1
H_DSTBP#1
H_DINV#1
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
R96
54.9_0402_1%
2
1
7
7
7
D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
DATA GRP 1
H_DSTBN#0
H_DSTBP#0
H_DINV#0
H_D#[16..31]
E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25
JP1C
R153
27.4_0402_1%
2
1
7
7
7
7
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0
DATA GRP 0
+CPU_CORE
H_D#[32..47] 7
JP1B
R154
54.9_0402_1%
2
1
H_D#[0..15]
DATA GRP 3
10U_0805_10V4Z
C238
+VCCP
R89
1K_0402_1%
2
+CPU_CORE
R483
100_0402_1%
2
VCCSENSE
R486
100_0402_1%
1
2
VSSSENSE
+CPU_GTLREF
R95
2K_0402_1%
Security Classification
2006/08/04
Issued Date
2006/10/06
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
Title
Rev
0.1
Sheet
of
47
+CPU_CORE
D
JP1D
C546
10U_0805_6.3V6M
1
C551
10U_0805_6.3V6M
1
C268
10U_0805_6.3V6M
1
C289
10U_0805_6.3V6M
1
C564
10U_0805_6.3V6M
1
C287
10U_0805_6.3V6M
1
C545
10U_0805_6.3V6M
C322
10U_0805_6.3V6M
+CPU_CORE
1
Place these capacitors on L8
(North side,Secondary Layer)
1
C549
10U_0805_6.3V6M
1
C328
10U_0805_6.3V6M
1
C558
10U_0805_6.3V6M
1
C297
10U_0805_6.3V6M
1
C542
10U_0805_6.3V6M
1
C327
10U_0805_6.3V6M
1
C286
10U_0805_6.3V6M
C559
10U_0805_6.3V6M
+CPU_CORE
1
Place these capacitors on L8
(Sorth side,Secondary Layer)
1
C321
10U_0805_6.3V6M
1
C288
10U_0805_6.3V6M
1
C555
10U_0805_6.3V6M
1
C547
10U_0805_6.3V6M
1
C291
10U_0805_6.3V6M
1
C554
10U_0805_6.3V6M
1
C314
10U_0805_6.3V6M
C295
10U_0805_6.3V6M
+CPU_CORE
C
1
Place these capacitors on L8
(Sorth side,Secondary Layer)
1
C267
10U_0805_6.3V6M
1
C285
10U_0805_6.3V6M
1
C563
10U_0805_6.3V6M
1
C292
10U_0805_6.3V6M
1
C298
10U_0805_6.3V6M
1
C296
10U_0805_6.3V6M
1
C543
10U_0805_6.3V6M
C315
10U_0805_6.3V6M
1
+
2
1
+
2
1
+
2
1
+
2
C562
330U_V_2.5VK_R9
C548
330U_V_2.5VK_R9
C557
330U_V_2.5VK_R9
+CPU_CORE
C313
330U_V_2.5VK_R9
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
C312
330U_V_2.5VK_R9
VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
C561
330U_V_2.5VK_R9
A4
A8
A11
A14
A16
A19
A23
AF2
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3
1
+
+VCCP
1
C229
220U_D2_4VM
+
2
1
C324
0.1U_0402_16V4Z
1
C272
0.1U_0402_16V4Z
1
C273
0.1U_0402_16V4Z
1
C271
0.1U_0402_16V4Z
1
C323
0.1U_0402_16V4Z
C325
0.1U_0402_16V4Z
Security Classification
2006/08/04
Issued Date
2006/10/06
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
Title
Rev
0.1
Sheet
of
47
H_VREF
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
M14
E13
A11
H13
B12
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#_0
H_RS#_1
H_RS#_2
E12
D7
D8
H_RS#0
H_RS#1
H_RS#2
21,33 ICH_POK
21,45
VGATE
18,19,21,23,24,26,27 PLT_RST#
layout note:
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
9
5
5
5
5
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
5
5
5
5
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
4
4
4
4
4
H_RS#0
H_RS#1
H_RS#2
4
4
4
2
R436
2
R438
1
R449
MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2
15 MCH_CLKSEL0
15 MCH_CLKSEL1
15 MCH_CLKSEL2
5
5
5
5
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
9
9
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG16
9
9
CFG18
CFG19
CFG20
9
9
9
CFG5
CFG6
CFG7
CFG9
CFG10
CFG11
CFG12
CFG13
CFG16
CFG18
CFG19
CFG20
1
0_0402_5%
1
@ 0_0402_5%
2
100_0402_5%
PM_POK_R
0309 add
PLT_RST#_R
21 PM_BMBUSY#
5,20,45 H_DPRSTP#
13 PM_EXTTS#0
14 PM_EXTTS#1
4,20 H_THERMTRIP#
21,45 DPRSLPVR
PM_BMBUSY#
G41
H_DPRSTP#
L39
PM_EXTTS#0
L36
PM_EXTTS#1
J36
PM_POK_R
AW49
PLT_RST#_R
AV20
H_THERMTRIP#
N20
DPRSLPVR
G36
+3VS
R57
+1.8V
PM_EXTTS#0
10K_0402_5%
PM_EXTTS#1
2
10K_0402_5%
2
R64
1
R17
2
BG20
BK16
BG16
BE13
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3
BH18
BJ15
BJ14
BE16
M_ODT0
M_ODT1
M_ODT2
M_ODT3
SM_RCOMP
SM_RCOMP#
BL15
BK14
SMRCOMP
SMRCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
BK31
BL31
SMRCOMP_VOH
SMRCOMP_VOL
SM_VREF_0
SM_VREF_1
AR49
AW4
2
1
PM_BM_BUSY#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
DDR
MUXING
CLK_MCH_DREFCLK
CLK_MCH_DREFCLK#
MCH_SSCDREFCLK
MCH_SSCDREFCLK#
PEG_CLK
PEG_CLK#
K44
K45
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
AN47
AJ38
AN42
AN46
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
AM47
AJ39
AN41
AN45
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
AJ46
AJ41
AM40
AM44
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
AJ47
AJ42
AM39
AM43
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VR_EN
+1.8V
20_0402_1%
1
1
20_0402_1%
2
2
CLK_MCH_DREFCLK 15
CLK_MCH_DREFCLK# 15
MCH_SSCDREFCLK 15
MCH_SSCDREFCLK# 15
CLK_MCH_3GPLL 15
CLK_MCH_3GPLL# 15
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
21
21
21
21
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
21
21
21
21
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
21
21
21
21
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
21
21
21
21
+1.25VS
AM49
AK50
AT43
AN49
AM50
CL_CLK0
CL_DATA0
R71
CL_CLK0 21
CL_DATA0 21
M_PWROK 21
CL_RST# 21
CL_RST#
CL_VREF
1K_0402_1%
0.1U_0402_16V4Z 1
R75
392_0402_1%
C167
SDVO_CTRL_CLK
SDVO_CTRL_DATA
CLK_REQ#
ICH_SYNC#
H35
K36
G39
G40
TEST_1
TEST_2
A37
R32
2
CLKREQ_3GPLL#
MCH_ICH_SYNC#
Deciphered Date
CLKREQ_3GPLL# 15
MCH_ICH_SYNC# 21
+3VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Near B3 pin
13
13
14
14
E35
A39
C38
B39
E36
R47
2006/08/04
13
13
14
14
R423
20K_0402_5%
Issued Date
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
+DDR_MCH_REF
CRESTLINE_1p0
Security Classification
13
13
14
14
R22
B42
C42
H48
H47
1K_0402_1%
2
13
13
14
14
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
R23
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
C161
0.1U_0402_16V4Z
R68
BJ51
BK51
BK50
BL50
BL49
BL3
BL2
BK1
BJ1
E1
A5
C51
B50
A50
A49
BK2
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
M_ODT0
M_ODT1
M_ODT2
M_ODT3
0_0402_5%
0.1U_0402_16V4Z
C15
1
5
221_0603_1%
R16
H_SWNG
100_0402_1%
R399
24.9_0402_1%
2
1
C23
1
R411
1K_0402_1%
2
1
R412
2
2K_0402_1%
H_RCOMP
+DDR_MCH_REF
P27
N27
N24
C21
C23
F23
N23
G23
J20
C20
R24
L23
J23
E23
E20
K23
M20
M24
L32
N33
L35
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD36
RSVD37
RSVD38
RSVD39
RSVD40
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45
NC
+VCCP
SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3
CLK
H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4
H_BNR# 4
H_BPRI# 4
H_BR0# 4
H_DEFER# 4
H_DBSY# 4
CLK_MCH_BCLK 15
CLK_MCH_BCLK# 15
H_DPWR# 5
H_DRDY# 4
H_HIT#
4
H_HITM# 4
H_LOCK# 4
H_TRDY# 4
1K_0402_1%
0.1U_0402_16V4Z
H_VREF
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
DMI
1K_0402_1%
R67
+DDR_MCH_REF
BE29
AY32
BD39
BG37
1
2
2
R45
C84
0.01U_0402_25V7K
13 DDR_A_MA14
14 DDR_B_MA14
Layout Note:
V_DDR_MCH_REF
trace width and
spacing is 20/20.
+VCCP
H10
B51
BJ20
BK22
BF19
BH20
BK18
BJ18
BF23
BG23
BC23
BD24
BJ29
BE24
BH39
AW20
BK20
C48
D47
B44
C44
A35
B37
B36
B34
C34
SMRCOMP_VOL
Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces
Layout Note:
H_RCOMP / H_VREF / H_SWNG
trace width and spacing is 10/20
SM_CKE_0
SM_CKE_1
SM_CKE_3
SM_CKE_4
R38
3.01K_0402_1%
NA lead free
H_AVREF
H_DVREF
CRESTLINE_1p0
L7
K2
AC2
AJ10
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
C83
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
2.2U_0603_10V6K
C73
M7
K3
AD2
AH11
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
PM
B9
A9
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
AW30
BA23
AW25
AW23
13
13
14
14
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
SM_CK#_0
SM_CK#_1
SM_CK#_3
SM_CK#_4
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
H_CPURST#
H_CPUSLP#
K5
L2
AD13
AE13
1K_0402_1%
SMRCOMP_VOH
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
B6
E5
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
R31
AV29
BB23
BA25
AV23
H_RESET#
H_CPUSLP#
H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DBSY#
CLK_MCH_BCLK
CLK_MCH_BCLK#
H_DPWR#
H_DRD Y#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
+1.8V
SM_CK_0
SM_CK_1
SM_CK_3
SM_CK_4
H_SCOMP
H_SCOMP#
G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
H_SWING
H_RCOMP
W1
W2
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
P36
P37
R35
N35
AR12
AR13
AM12
AN13
J12
AR37
AM36
AL36
AM37
D20
Title
R63
CLKREQ_3GPLL#2
1
A
10K_0402_5%
B3
C2
H_SCOMP
H_SCOMP#
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
GRAPHICS VID
R15
54.9_0402_1%
2
1
H_RESET#
H_CPUSLP#
H_SWNG
H_RCOMP
J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19
CFG
R18
54.9_0402_1%
2
1
+VCCP
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
ME
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
2.2U_0603_10V6K
C91
E2
G2
G7
M6
H7
H3
G4
F3
N8
H2
M10
N12
N9
H5
P13
K9
M2
W10
Y8
V4
M3
J1
N5
N3
W6
W9
N2
Y7
Y9
P4
W3
N1
AD12
AE3
AD9
AC9
AC7
AC14
AD11
AC11
AB2
AD7
AB1
Y3
AC6
AE2
AC5
AG3
AJ9
AH8
AJ14
AE9
AE11
AH12
AJ5
AH5
AJ6
AE7
AJ7
AJ2
AE5
AJ3
AH2
AH13
RSVD
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
U22B
0.01U_0402_25V7K
U22A
H_D#[0..63]
4
5
H_A#[3..35] 4
HOST
MISC
Rev
0.1
Sheet
of
47
14 DDR_B_D[0..63]
DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2
SA_CAS#
BL17
DDR_A_CAS#
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
AT45
BD44
BD42
AW38
AW13
BG8
AY5
AN6
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
AT46
BE48
BB43
BC37
BB16
BH6
BB2
AP3
AT47
BD47
BC41
BA37
BA16
BH7
BC1
AP2
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
BJ19
BD20
BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28
BC19
BE28
BG30
BJ16
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
SA_RAS#
SA_RCVEN#
BE18
AY20
DDR_A_RAS#
SA_RCVEN#
SA_WE#
BA19
DDR_A_WE#
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
DDR_A_BS#0 13
DDR_A_BS#1 13
DDR_A_BS#2 13
DDR_A_CAS# 13
DDR_A_DM[0..7] 13
DDR_A_DQS[0..7] 13
DDR_A_DQS#[0..7] 13
DDR_A_MA[0..13] 13
DDR_A_RAS# 13
T2
DDR_A_WE# 13
AP49
AR51
AW50
AW51
AN51
AN50
AV50
AV49
BA50
BB50
BA49
BE50
BA51
AY49
BF50
BF49
BJ50
BJ44
BJ43
BL43
BK47
BK49
BK43
BK42
BJ41
BL41
BJ37
BJ36
BK41
BJ40
BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12
BJ10
BL9
BK5
BL5
BK9
BK10
BJ8
BJ6
BF4
BH5
BG1
BC2
BK3
BE4
BD3
BJ2
BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2
CRESTLINE_1p0
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
SB_BS_0
SB_BS_1
SB_BS_2
BB19
BK19
BF29
MEMORY
SA_BS_0
SA_BS_1
SA_BS_2
MEMORY
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
SYSTEM
AR43
AW44
BA45
AY46
AR41
AR45
AT42
AW47
BB45
BF48
BG47
BJ45
BB47
BG50
BH49
BE45
AW43
BE44
BG42
BE40
BF44
BH45
BG40
BF40
AR40
AW40
AT39
AW36
AW41
AY41
AV38
AT38
AV13
AT13
AW11
AV11
AU15
AT11
BA13
BA11
BE10
BD10
BD8
AY9
BG10
AW9
BD7
BB9
BB5
AY7
AT5
AT7
AY6
BB7
AR5
AR8
AR9
AN3
AM8
AN10
AT9
AN9
AM9
AN11
DDR
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
U22E
SYSTEM
U22D
DDR
13 DDR_A_D[0..63]
AY17
BG18
BG36
DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2
SB_CAS#
BE17
DDR_B_CAS#
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
AR50
BD49
BK45
BL39
BH12
BJ7
BF3
AW2
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
AT50
BD50
BK46
BK39
BJ12
BL7
BE2
AV2
AU50
BC50
BL45
BK38
BK12
BK7
BF2
AV3
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
SB_RAS#
SB_RCVEN#
AV16
AY18
DDR_B_RAS#
SB_RCVEN#
SB_WE#
BC17
DDR_B_WE#
DDR_B_BS#0 14
DDR_B_BS#1 14
DDR_B_BS#2 14
DDR_B_CAS# 14
DDR_B_DM[0..7] 14
DDR_B_DQS[0..7] 14
DDR_B_DQS#[0..7] 14
DDR_B_MA[0..13] 14
DDR_B_RAS# 14
T1
DDR_B_WE# 14
CRESTLINE_1p0
Security Classification
2006/08/04
Issued Date
2006/10/06
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
Title
Rev
0.1
Sheet
of
47
R56
2.2K_0402_5%
UMA@
EDID_CLK_LCD
EDID_DAT_LCD
Others = Reserved
U22C
R62
37
37
37
37
LVDSACLVDSAC+
LVDSBCLVDSBC+
L41
L43
N41
N40
D46
C45
D44
E42
LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK
LVDSA0LVDSA1LVDSA2-
G51
E51
F49
LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
1
2.4K_0402_1%
LVDSACLVDSAC+
LVDSBCLVDSBC+
37
37
37
LVDSA0LVDSA1LVDSA2-
37
37
37
LVDSA0+
LVDSA1+
LVDSA2+
37
37
37
LVDSB0LVDSB1LVDSB2-
37
37
37
LVDSB0+
LVDSB1+
LVDSB2+
LVDSA0+
LVDSA1+
LVDSA2+
G50
E50
F48
LVDSB0LVDSB1LVDSB2-
G44
B47
B45
LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2
LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
TV_COMPS
1
UMA@ 150_0603_1%
17
TV_LUMA
1
17
UMA@ 150_0603_1%
17
TV_CRMA
1
UMA@ 150_0603_1%
TV_COMPS
TV_LUMA
TV_CRMA
1
R52
+3VS
R421
R419
2
2
1
UMA@
1
UMA@
1
UMA@
TV_COMPS
TV_LUMA
TV_CRMA
2
2.2K_0402_5%
17
CRT_B
17
CRT_G
17
CRT_R
CRT_B
E27
G27
K27
TVA_DAC
TVB_DAC
TVC_DAC
F27
J27
L27
TVA_RTN
TVB_RTN
TVC_RTN
M35
P33
TV_DCONSEL_0
TV_DCONSEL_1
H32
G32
K29
J29
F29
E29
CRT_G
CRT_R
LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2
CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#
17 CRT_VSYNC
K33
G35
F33
C32
E33
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC
17 CRT_HSYNC
17
3VDDCCL
17
3VDDCDA
CRT_HSYNC 1
R424
CRT_VSYNC 1
R422
3VDDCCL
3VDDCDA
HSYNC_R
2
39_0402_1%
VSYNC_R
2
39_0402_1%
R417
1.3K_0402_1%
VGA
R418
CRT_R
150_0603_1%
CRT_G
150_0603_1%
CRT_B
150_0603_1%
E44
A47
A45
TV
2
R414
2
R415
2
R416
LVDSB0+
LVDSB1+
LVDSB2+
GRAPHICS
16 GMCH_LVDDEN
PCI-EXPRESS
L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN
GMCH_ENBKL
R425 1
2 10K_0402_5%
R429 1
2 10K_0402_5%
EDID_CLK_LCD
EDID_DAT_LCD
GMCH_LVDDEN
16 GMCH_ENBKL
+3VS
LVDS
J40
H39
E39
E40
C37
D35
K40
+VCC_PEG
R66
24.9_0402_1%
1
2
PEG_RXN[0..15] 18
PEG_COMPI
PEG_COMPO
N43
M43
PEGCOMP
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
J51
L51
N47
T45
T50
U40
Y44
Y40
AB51
W49
AD44
AD40
AG46
AH49
AG45
AG41
PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
J50
L50
M47
U44
T49
T41
W45
W41
AB50
Y48
AC45
AC41
AH47
AG49
AH45
AG42
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
N45
U39
U47
N51
R50
T42
Y43
W46
W38
AD39
AC46
AC49
AC42
AH39
AE49
AH44
PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15
C277
C234
C259
C218
C279
C236
C264
C221
C282
C242
C257
C223
C284
C239
C262
C225
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PEG_M_TXN0
PEG_M_TXN1
PEG_M_TXN2
PEG_M_TXN3
PEG_M_TXN4
PEG_M_TXN5
PEG_M_TXN6
PEG_M_TXN7
PEG_M_TXN8
PEG_M_TXN9
PEG_M_TXN10
PEG_M_TXN11
PEG_M_TXN12
PEG_M_TXN13
PEG_M_TXN14
PEG_M_TXN15
M45
T38
T46
N50
R51
U43
W42
Y47
Y39
AC38
AD47
AC50
AD43
AG39
AE50
AH43
PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15
C276
C233
C258
C217
C278
C235
C263
C219
C281
C241
C256
C222
C283
C243
C261
C224
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
VGA@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PEG_M_TXP0
PEG_M_TXP1
PEG_M_TXP2
PEG_M_TXP3
PEG_M_TXP4
PEG_M_TXP5
PEG_M_TXP6
PEG_M_TXP7
PEG_M_TXP8
PEG_M_TXP9
PEG_M_TXP10
PEG_M_TXP11
PEG_M_TXP12
PEG_M_TXP13
PEG_M_TXP14
PEG_M_TXP15
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
0 = DMI x 2
For Crestline:2.4kohm
For Calero: 1.5Kohm
R59
2.2K_0402_5%
UMA@
37 EDID_CLK_LCD
37 EDID_DAT_LCD
+3VS
1 = DMI x 4
Reserved
CFG6
CFG7 (CPU Strap)
0 = Reserved
1 = Mobile CPU
CFG9
1 = Normal Operation
Reserved
CFG[11:10]
00
01
10
11
CFG[13:12] (XOR/ALLZ)
CFG[15:14]
= Reserved
= XOR Mode Enabled
= All Z Mode Enabled
= Normal Operation (Default)
Reserved
0 = Disabled
1 = Enabled
PEG_M_TXN[0..15] 18
0 = Reverse Lane
PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15
0 = Normal mode
PEG_RXP[0..15] 18
CFG[18:17]
Reserved
0 = No SDVO Device Present
SDVO_CTRLDATA
1 = Reverse Lane
0 = Only PCIE or SDVO is operational.
CFG5
R32
1
@ 4.02K_0402_1%
2
CFG7
R33
1
@ 4.02K_0402_1%
2
CFG8
R26
1
@ 4.02K_0402_1%
2
CFG9
R413
1
@ 4.02K_0402_1%
2
CFG12
R25
1
@ 4.02K_0402_1%
2
CFG13
R29
1
@ 4.02K_0402_1%
2
CFG16
R27
1
@ 4.02K_0402_1%
2
CRESTLINE_1p0
For Crestline:1.3kohm
For Calero: 255ohm
PEG_M_TXP[0..15] 18
Security Classification
2006/08/04
Issued Date
2006/10/06
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
Title
CFG19
R55
1
CFG20
R58
1
@ 4.02K_0402_1%
2
@ 4.02K_0402_1%
2
Rev
0.1
Sheet
of
47
U22H
N28
VCCD_QDAC
UMA@
AXD
DMI
C13
0.1U_0402_16V4Z
+VCCP
C24
1
1
C525
10U_0805_10V4Z
+1.25VS_MPLL
R397
2
1
0_0805_5%
2
2
0316 add
1
+
C179
C64
10U_FLC-453232-100K_0.25A_10%
10U_0805_10V4Z
0.1U_0402_16V4Z
C76
0.022U_0402_16V7K
2
1
MBK2012121YZF_0805
+1.25VS
04/10 stuff
C181
CRESTLINE_1p0
220U_D2_4VM
+3VS
R49
+1.25VS
R76
A7
F2
AH1
2
1
0_0603_5%
UMA@
+1.25VS
R398
R431
+VCC_PEG
20mils
C199
+3VS_TVDACC
B
VTTLF1
VTTLF2
VTTLF3
0316 add
220U_D2_4VM
VCCD_LVDS_1
VCCD_LVDS_2
AH50
AH51
0.47U_0603_10V7K
C21
VCCD_PEG_PLL
J41
H42
+1.8V_LVDS
VCC_RXR_DMI_1
VCC_RXR_DMI_2
+VCC_PEG
0.47U_0603_10V7K
C12
+1.25VS_PEGPLL
U48
VCCD_HPLL
AD51
W50
W51
V49
V50
0.47U_0603_10V7K
C14
+1.25VS_HPLL
AN2
D TV/CRT
+1.5VS_QDAC
LVDS
+1.5VS_TVDAC
+1.25VS_HPLL
+3VS_HV
+1.5VS
R41
1
2
0_0805_5%
+1.8V_TXLVDS
VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5
+1.5VS_TVDAC
+1.25VS_DPLLA
VTTLF
VCCD_CRT
VCCD_TVDAC
C40
B40
10U_0805_10V6K
M32
L29
VCC_HV_1
VCC_HV_2
C533
+3VS_TVDACC
VCCA_TVA_DAC_1
VCCA_TVA_DAC_2
VCCA_TVB_DAC_1
VCCA_TVB_DAC_2
VCCA_TVC_DAC_1
VCCA_TVC_DAC_2
VCC_TX_LVDS
A43
+1.25VS
L4
BLM18PG121SN1D_0603
2
1
C163
+3VS_TVDACB
VCCA_SM_CK_1
VCCA_SM_CK_2
C25
B25
C27
B27
B28
A28
+1.8V_SM_CK
+1.25VS_PEGPLL
0.1U_0402_16V4Z
+3VS_TVDACA
BK24
BK23
BJ24
BJ23
C139
BC29
BB29
VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4
+1.25VS
0.1U_0402_16V4Z
C82
0.1U_0402_16V4Z
C77
1U_0603_10V4Z
22U_0805_6.3V4Z
0316 add
C55
C75
1U_0402_6.3V4Z
2
1
0_0603_5%
SM CK
2
1U_0603_10V4Z
+1.25VS_DMI
HV
+1.25VS_A_SM_CK
AJ50
AXF
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
VCCA_SM_10
VCCA_SM_11
VCCA_SM_NCTF_1
VCCA_SM_NCTF_2
C138
VTT
PLL
AT22
AT21
AT19
AT18
AT17
AR17
AR16
C34
VCC_DMI
R28
1
2
0_0805_5%
0.1U_0402_16V4Z
4.7U_0805_6.3V6K
+V1.25VS_AXF
C78
POWER
B23
B21
A21
VCC_AXF_1
VCC_AXF_2
VCC_AXF_3
+1.8V
C79
0.022U_0402_16V7K
22U_0805_6.3V4Z
C29
VCC_AXD_NCTF
C162
VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
10U_0805_10V4Z
R37
C28
VCCA_PEG_PLL
AW18
AV19
AU19
AU18
AU17
AR29
R34
1
2
0_0805_5%
R73
0_0603_5%
C168
1
+
150U_D_6.3VM
U51
1
2
0_0805_5%
+1.25VS
C8
+1.25VS_A_SM
0317 change value
R21
C
+1.25VS_PEGPLL 20 mils
AT23
AU28
AU24
AT29
AT25
AT30
0.1U_0402_16V4Z
C165
VCC_AXD_1
VCC_AXD_2
VCC_AXD_3
VCC_AXD_4
VCC_AXD_5
VCC_AXD_6
PEG
VSSA_PEG_BG
A LVDS
K49
A PEG
0.1U_0402_16V4Z
A SM
VCCA_PEG_BG
10U_0805_10V6K
K50
+3VS_PEG_BG
R72
2
1
0_0603_5%
+3VS
+1.25VS_AXD
C87
VSSA_LVDS
C68
VCCA_LVDS
B41
1U_0603_10V4Z
A41
A CK
1000P_0402_50V7K
1
C154
+1.8V_TXLVDS
C129
VCCA_MPLL
C135
VCCA_HPLL
AM2
CRT
AL2
+1.25VS_MPLL
C43
+1.25VS_HPLL
+1.8V_SM_CK
+1.25VS
0.1U_0402_16V4Z
C49
VCCA_DPLLB
R24
0_0603_5%
C38
UMA@
+1.25VS_DMI
C36
VCCA_DPLLA
H49
0316 add
C47
B49
+1.25VS_DPLLB
0316 add
22U_0805_6.3V4Z
+1.25VS_DPLLA
22U_0805_6.3V4Z
VSSA_DAC_BG
10U_FLC-453232-100K_0.25A_10%
C534
B32
2
2
+1.25VS
0.1U_0402_16V4Z
C166
0.022U_0402_16V7K
C116
1
C117
UMA@
0.1U_0402_16V4Z
R54
1
2
0_0603_5%
UMA@
C164
VCCA_DAC_BG
1
C198
2.2U_0805_16V4Z
A30
+3VS_DAC_BG
+3VS_DAC_CRT
+3VS
330U_D2E_2.5VM_R7
U13
U12
U11
U9
U8
U7
U5
U3
U2
U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
R3
R2
R1
4.7U_0805_10V4Z
VCCA_CRT_DAC_1
VCCA_CRT_DAC_2
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
4.7U_0805_10V4Z
VCCSYNC
A33
B33
0.47U_0603_10V7K
J32
TV
1U_0603_10V4Z
+1.25VS
+V1.25VS_AXF
R433
10U_0805_10V4Z
UMA@
+1.25VS_DPLLB
+3VS_DAC_CRT
D
+VCCP
10U_0805_10V4Z
C94
0.1U_0402_16V4Z
C96
1
C92
4.7U_0805_10V4Z
0.1U_0402_16V4Z
UMA@
R51
2
1
0_0603_5%
0.1U_0402_16V4Z
0.022U_0402_16V7K
C97
1R39
0_0603_5%
UMA@
VCCSYNC
+3VS
+3VS_DAC_BG
+3VS
2
1
MBK2012121YZF_0805
+1.25VS
C11
@ R435
2
1
0_0805_5%
0.1U_0402_16V4Z
C524
10U_0805_10V4Z
04/10 no stuff
+VCCP_D
D16
UMA@
+VCCP
R426
2
1
10_0402_5%
R428
2
1
0_0402_5%
+3VS_HV
CH751H-40PT_SOD323-2
+3VS
+1.5VS_QDAC
+3VS_TVDACA
+1.5VS
R43
+3VS
R35
UMA@
1
C46
UMA@
2
1
0_0603_5%
UMA@
0.1U_0402_16V4Z
C54
C58
0.022U_0402_16V7K
0.1U_0402_16V4Z
C56
0.022U_0402_16V7K
2
1
0_0603_5%
UMA@
40 mils
+1.8V_TXLVDS
R74
1000P_0402_50V7K
UMA@
C158
UMA@
UMA@
2
1
0_0603_5%
UMA@
1
220U_D2_4VM_R15
+ C156
UMA@
U22
C64
C58
C158
C152
PM
0_0402_5%
0_0402_5%
0_0402_5%
0_0603_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
+1.8V
VGA@
VGA@
C54
VGA@
C65
VGA@
C96
VGA@
C117
+1.8V_LVDS
A
+3VS_TVDACB
+3VS
R36
UMA@
C152
1U_0603_10V4Z
C65
R69
C155
10U_0805_10V6K
0.1U_0402_16V4Z
C66
0.022U_0402_16V7K
UMA@
2
1
0_0603_5%
UMA@
2
1
0_0603_5%
UMA@
+1.8V
VGA@
Security Classification
2006/08/04
Issued Date
UMA@
UMA@
2006/10/06
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
Title
VGA@
VGA@
VGA@
Re v
0.1
Sheet
1
10
of
47
+VCCP
+VCCGFX
U22G
VCC AXM
VCC AXM NCTF
VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_5
VCC_AXM_6
VCC_AXM_7
AT33
AT31
AK29
AK24
AK23
AJ26
AJ23
+VCCP
+VCCGFX
10U_0805_10V4Z
0.1U_0402_16V4Z
1
1
C48
C9
C26
1
C27
1U_0603_10V4Z
330U_D2E_2.5VM_R7
1
C51
2
10U_0805_10V4Z
CRESTLINE_1p0
VCC CORE
4.7U_0603_6.3V6K
1 C37
C39
D
0.22U_0402_10V4Z
C159 1U_0603_10V4Z
C145 1U_0603_10V4Z
0.22U_0603_10V7K
C133 0.47U_0402_6.3V6K
C35
0.1U_0402_16V4Z
0.22U_0603_10V7K
C18
AW45 VCCSM_LF1
BC39 VCCSM_LF2
BE39 VCCSM_LF3
BD17 VCCSM_LF4
BD4 VCCSM_LF5
AW8 VCCSM_LF6
AT6 VCCSM_LF7
1
C22
VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7
0.1U_0402_16V4Z
0.1U_0402_16V4Z
VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31
C19
R20
T14
W13
W14
Y12
AA20
AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31
AJ20
AN14
VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83
VCC SM LF
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36
AU32
AU33
AU35
AV33
AW33
AW35
AY35
BA32
BA33
BA35
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35
BF33
BF34
BG32
BG33
BG35
BH32
BH34
BH35
BJ32
BJ33
BJ34
BK32
BK33
BK34
BK35
BL33
AU30
VCC SM
C99
VCC_AXM_NCTF_1
VCC_AXM_NCTF_2
VCC_AXM_NCTF_3
VCC_AXM_NCTF_4
VCC_AXM_NCTF_5
VCC_AXM_NCTF_6
VCC_AXM_NCTF_7
VCC_AXM_NCTF_8
VCC_AXM_NCTF_9
VCC_AXM_NCTF_10
VCC_AXM_NCTF_11
VCC_AXM_NCTF_12
VCC_AXM_NCTF_13
VCC_AXM_NCTF_14
VCC_AXM_NCTF_15
VCC_AXM_NCTF_16
VCC_AXM_NCTF_17
VCC_AXM_NCTF_18
VCC_AXM_NCTF_19
A3
B2
C1
BL1
BL51
A51
VCC_13
VCC GFX
1
C125
0.01U_0402_16V7K
C143
AL24
AL26
AL28
AM26
AM28
AM29
AM31
AM32
AM33
AP29
AP31
AP32
AP33
AL29
AL31
AL32
AR31
AR32
AR33
+1.8V
POWER
VSS_SCB1
VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6
R30
Check : power
POWER
330U_D2E_2.5VM_R7
22U_0805_6.3V4Z
C114
C52
0.1U_0402_16V4Z
C45
C86
0.1U_0402_16V4Z
C53
0.1U_0402_16V4Z
C122
0.22U_0402_10V4Z
C88
0.22U_0402_10V4Z
10U_0805_10V4Z
C126
10U_0805_10V4Z
R53
1
2
0_0603_5%
+VCCP
T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28
22U_0805_6.3V4Z
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS SCB
VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44
VCC_NCTF_45
VCC_NCTF_46
VCC_NCTF_47
VCC_NCTF_48
VCC_NCTF_49
VCC_NCTF_50
VCC NCTF
C17
0.1U_0402_16V4Z
C16
0.22U_0402_10V4Z
C111
0.22U_0402_10V4Z
C151
22U_0805_6.3V4Z
C211
220U_D2_4VM_R15
AB33
AB36
AB37
AC33
AC35
AC36
AD35
AD36
AF33
AF36
AH33
AH35
AH36
AH37
AJ33
AJ35
AK33
AK35
AK36
AK37
AD33
AJ36
AM35
AL33
AL35
AA33
AA35
AA36
AP35
AP36
AR35
AR36
Y32
Y33
Y35
Y36
Y37
T30
T34
T35
U29
U31
U32
U33
U35
U36
V32
V33
V36
V37
VSS NCTF
U22F
VCC_1
VCC_2
VCC_3
VCC_5
VCC_4
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
C33
+VCCP
D
AT35
AT34
AH28
AC32
AC31
AK32
AJ31
AJ28
AH32
AH31
AH29
AF32
CRESTLINE_1p0
Security Classification
2006/08/04
Issued Date
2006/10/06
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
Title
Rev
0.1
Sheet
11
of
47
U22I
A13
A15
A17
A24
AA21
AA24
AA29
AB20
AB23
AB26
AB28
AB31
AC10
AC13
AC3
AC39
AC43
AC47
AD1
AD21
AD26
AD29
AD3
AD41
AD45
AD49
AD5
AD50
AD8
AE10
AE14
AE6
AF20
AF23
AF24
AF31
AG2
AG38
AG43
AG47
AG50
AH3
AH40
AH41
AH7
AH9
AJ11
AJ13
AJ21
AJ24
AJ29
AJ32
AJ43
AJ45
AJ49
AK20
AK21
AK26
AK28
AK31
AK51
AL1
AM11
AM13
AM3
AM4
AM41
AM45
AN1
AN38
AN39
AN43
AN5
AN7
AP4
AP48
AP50
AR11
AR2
AR39
AR44
AR47
AR7
AT10
AT14
AT41
AT49
AU1
AU23
AU29
AU3
AU36
AU49
AU51
AV39
AV48
AW1
AW12
AW16
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41
U22J
C46
C50
C7
D13
D24
D3
D32
D39
D45
D49
E10
E16
E24
E28
E32
E47
F19
F36
F4
F40
F50
G1
G13
G16
G19
G24
G28
G29
G33
G42
G45
G48
G8
H24
H28
H4
H45
J11
J16
J2
J24
J28
J33
J35
J39
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
K12
K47
K8
L1
L17
L20
L24
L28
L3
L33
L49
M28
M42
M46
M49
M5
M50
M9
N11
N14
N17
N29
N32
N36
N39
N44
N49
N7
P19
P2
P23
P3
P50
R49
T39
T43
T47
U41
U45
U50
V2
V3
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29
T29
T31
T33
R28
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50
VSS
CRESTLINE_1p0
CRESTLINE_1p0
A
Security Classification
2006/08/04
Issued Date
2006/10/06
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
Title
Rev
0.1
Sheet
12
of
47
Layout Note:
+DDR_MCH_REF
trace width and
spacing is 20/20.
+1.8V
+DDR_MCH_REF1
DDR_A_DQS#0
DDR_A_DQS0
R113
DDR_A_D2
DDR_A_D3
R112
DDR_A_DQS#1
DDR_A_DQS1
100_0402_1%
2
C254
0.1U_0402_16V4Z
Layout Note:
Place near JP41
DDR_A_D8
DDR_A_D14
+DDR_MCH_REF1
14 +DDR_MCH_REF1
100_0402_1%
D
DDR_A_D9
DDR_A_D15
+1.8V
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
DDR_A_D16
DDR_A_D17
C141
C67
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C98
0.1U_0402_16V4Z
C146
C41
0.1U_0402_16V4Z
C153
2.2U_0805_16V4Z
2.2U_0805_16V4Z
C42
2.2U_0805_16V4Z
C144
2.2U_0805_16V4Z
C148
2.2U_0805_16V4Z
DDR_A_DQS#2
DDR_A_DQS2
1
+
C25
470U_D2_2.5VM_R15
DDR_A_D18
DDR_A_D19
DDR_A_D29
DDR_A_D24
DDR_A_DM3
14,33 EC_TX_P80_DATA
DDR_A_D26
DDR_A_D27
7 DDR_CKE0_DIMMA
14,33 EC_RX_P80_CLK
8
DDR_A_BS#2
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS
DDR_CKE0_DIMMA
DDR_A_BS#2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
8
8
+0.9VS
DDR_A_BS#0
DDR_A_WE#
8 DDR_A_CAS#
7 DDR_CS1_DIMMA#
M_ODT1
DDR_A_CAS#
DDR_CS1_DIMMA#
M_ODT1
DDR_A_D37
DDR_A_D36
DDR_A_DQS#4
DDR_A_DQS4
2
C63
C123
C74
C132
C115
C93
C71
C59
C134
C85
C112
C119
C127
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#
DDR_A_D38
DDR_A_D32
DDR_A_D40
DDR_A_D44
DDR_A_DM5
DDR_A_D41
DDR_A_D46
+0.9VS
RP1
DDR_A_WE#
DDR_A_CAS#
DDR_CS1_DIMMA#
M_ODT1
1
2
3
4
RP2
8
7
6
5
56_0804_8P4R_5%
DDR_A_BS#0
R42
DDR_A_MA10 R46
DDR_A_MA14 R61
2
56_0402_5%
2
56_0402_5%
1
2
56_0402_5%
8
7
6
5
1
2
3
4
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
DDR_A_MA13
Layout Note:
Pla ce these resistor
closely JP41,all
trace length Max=1.5"
DDR_A_D49
DDR_A_D48
14 EC_RX_P80_CLK_R
EC_RX_P80_CLK 1
R19
2
0_0402_5%
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D54
DDR_A_D50
56_0804_8P4R_5%
DDR_A_D61
DDR_A_D60
RP6
5
6
7
8
4
3
2
1
DDR_A_BS#1
DDR_A_MA0
DDR_A_MA2
DDR_A_MA4
DDR_A_DM7
DDR_A_D59
DDR_A_D58
56_0804_8P4R_5%
RP7
DDR_A_MA1
DDR_A_MA3
DDR_A_MA5
DDR_A_MA8
4
3
2
1
RP9
5
6
7
8
56_0804_8P4R_5%
5
6
7
8
4
3
2
1
EC_RX_P80_CLK_R
14,15 CLK_SMBDATA
14,15 CLK_SMBCLK
DDR_A_MA6
DDR_A_MA7
DDR_A_MA11
DDR_CKE1_DIMMA
CLK_SMBDATA
CLK_SMBCLK
+3VS
C6
0.1U_0402_16V4Z
RP11
DDR_A_MA9
DDR_A_MA12
DDR_A_BS#2
DDR_CKE0_DIMMA
4
3
2
1
56_0804_8P4R_5%
5
6
7
8
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SA0
SA1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
FOX_ASOA426-M2RN-7F
ME@
SO-DIMM A
DDR_A_D6
DDR_A_D0
DDR_A_DM0
DDR_A_D5
DDR_A_D7
DDR_A_D13
DDR_A_D12
DDR_A_DM1
M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR0 7
M_CLK_DDR#0 7
DDR_A_D11
DDR_A_D10
DDR_A_D20
DDR_A_D21
PM_EXTTS#0 7
DDR_A_DM2
DDR_A_D23
DDR_A_D22
DDR_A_D28
DDR_A_D25
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D31
DDR_A_D30
DDR_CKE1_DIMMA
DDR_A_MA14
DDR_CKE1_DIMMA 7
DDR_A_MA14 7
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
DDR_A_MA13
DDR_A_BS#1 8
DDR_A_RAS# 8
DDR_CS0_DIMMA# 7
M_ODT0
DDR_A_D33
DDR_A_D39
DDR_A_DM4
DDR_A_D35
DDR_A_D34
DDR_A_D45
DDR_A_D43
B
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D47
DDR_A_D42
DDR_A_D52
DDR_A_D53
M_CLK_DDR1
M_CLK_DDR#1
M_CLK_DDR1 7
M_CLK_DDR#1 7
DDR_A_DM6
DDR_A_D51
DDR_A_D55
DDR_A_D57
DDR_A_D56
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
Top side
Compal Secret Data
Security Classification
56_0804_8P4R_5%
2006/08/04
Issued Date
2006/10/06
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
+DDR_MCH_REF1 14
C251
8 DDR_A_MA[0..13]
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
C253
DDR_A_D4
DDR_A_D1
8 DDR_A_DQS[0..7]
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
0.1U_0402_16V4Z
+1.8V
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2.2U_0805_16V4Z
JP3
8 DDR_A_D[0..63]
8 DDR_A_DM[0..7]
+1.8V
R13
10K_0402_5%
2
1
8 DDR_A_DQS#[0..7]
R14
10K_0402_5%
2
1
Title
Rev
0.1
Sheet
13
of
47
+1.8V
8 DDR_B_DQS#[0..7]
+1.8V
8 DDR_B_D[0..63]
+DDR_MCH_REF1
8 DDR_B_DM[0..7]
DDR_B_D10
DDR_B_D11
+1.8V
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
DDR_B_D17
DDR_B_D20
1
1
C57
C147
0.1U_0402_16V4Z
C128
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C121
0.1U_0402_16V4Z
C31
C157
2.2U_0805_16V4Z
2.2U_0805_16V4Z
C149
2.2U_0805_16V4Z
C32
C44
2.2U_0805_16V4Z
2.2U_0805_16V4Z
C81
470U_D2_2.5VM_R15
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D25
DDR_B_D28
DDR_B_DM3
13,33 EC_TX_P80_DATA
DDR_B_D30
DDR_B_D31
7 DDR_CKE2_DIMMB
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS
13,33 EC_RX_P80_CLK
8
DDR_B_BS#2
DDR_CKE2_DIMMB
DDR_B_BS#2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
+0.9VS
DDR_B_BS#0
DDR_B_WE#
8 DDR_B_CAS#
7 DDR_CS3_DIMMB#
1
M_ODT3
DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#
DDR_B_CAS#
DDR_CS3_DIMMB#
M_ODT3
DDR_B_D32
DDR_B_D33
2
C62
C69
C118
C142
C89
C113
C137
C95
C72
C61
C131
C136
C124
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
8
8
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43
+0.9VS
RP3
DDR_B_CAS#
DDR_B_WE#
DDR_CS3_DIMMB#
M_ODT3
8
7
6
5
RP4
1
2
3
4
56_0804_8P4R_5%
DDR_B_BS#0
R48
1
2
56_0402_5%
1
2
56_0402_5%
1
2
DDR_B_MA10 R44
DDR_B_MA14 R65
4
3
2
1
5
6
7
8
DDR_B_MA13
M_ODT2
DDR_CS2_DIMMB#
DDR_B_RAS#
Layout Note:
Pla ce these resistor
closely JP42,all
trace length Max=1.5"
DDR_B_D56
DDR_B_D61
RP5
5
6
7
8
DDR_B_BS#1
DDR_B_MA0
DDR_B_MA2
DDR_B_MA4
DDR_B_DM7
DDR_B_D58
DDR_B_D59
5
6
7
8
+3VS
DDR_B_MA7
DDR_B_MA11
DDR_B_MA6
DDR_CKE3_DIMMB
C7
0.1U_0402_16V4Z
56_0804_8P4R_5%
DDR_B_DM1
M_CLK_DDR3
M_CLK_DDR#3
M_CLK_DDR3 7
M_CLK_DDR#3 7
DDR_B_D14
DDR_B_D15
DDR_B_D21
DDR_B_D16
PM_EXTTS#1 7
DDR_B_DM2
DDR_B_D22
DDR_B_D23
DDR_B_D26
DDR_B_D24
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D29
DDR_B_D27
DDR_CKE3_DIMMB
DDR_CKE3_DIMMB 7
DDR_B_MA14
DDR_B_MA14 7
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#
DDR_B_BS#1 8
DDR_B_RAS# 8
DDR_CS2_DIMMB# 7
M_ODT2
DDR_B_MA13
M_ODT2
DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D39
DDR_B_D38
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
M_CLK_DDR2
M_CLK_DDR#2
M_CLK_DDR2 7
M_CLK_DDR#2 7
DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D57
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
FOX_AS0A426-MARG-7F
SO-DIMM B
R395
1
R396
56_0804_8P4R_5%
4
3
2
1
CLK_SMBDATA
CLK_SMBCLK
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
10K_0402_5%
13,15 CLK_SMBDATA
13,15 CLK_SMBCLK
RP12
4
3
2
1
EC_RX_P80_CLK_R
DDR_B_DQS#6
DDR_B_DQS6
56_0804_8P4R_5%
4
3
2
1
RP8
5
6
7
8
13 EC_RX_P80_CLK_R
DDR_B_D51
DDR_B_D50
56_0804_8P4R_5%
DDR_B_MA1
DDR_B_MA3
DDR_B_MA5
DDR_B_MA9
DDR_B_D48
DDR_B_D49
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
DDR_B_D12
DDR_B_D13
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D6
DDR_B_D7
+3VS
10K_0402_5%
A
DDR_B_D8
DDR_B_D9
DDR_B_DM0
C249
DDR_B_D2
DDR_B_D3
Layout Note:
Place near JP42
DDR_B_D4
DDR_B_D5
C255
DDR_B_DQS#0
DDR_B_DQS0
D
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
0.1U_0402_16V4Z
DDR_B_D0
DDR_B_D1
8 DDR_B_MA[0..13]
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
2.2U_0805_16V4Z
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
8 DDR_B_DQS[0..7]
+DDR_MCH_REF1 13
JP4
RP13
DDR_CKE2_DIMMB 8
DDR_B_BS#2
7
DDR_B_MA12
6
DDR_B_MA8
5
1
2
3
4
2006/08/04
Issued Date
56_0804_8P4R_5%
Security Classification
2006/10/06
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
Title
Size
Document Number
Rev
0.1
IGT30 LA-3571P
Date:
Sheet
14
of
47
FSLC
FSLB
FSLA
CLKSEL2
CLKSEL1
CLKSEL0
CPU
MHz
SRC
MHz
PCI
MHz
200
100
33.3
+3VS
1
R149
2
0_1206_5% 1
166
100
10U_0805_10V4Z
C335
0.1U_0402_16V4Z
C333
0.1U_0402_16V4Z
C342
0.1U_0402_16V4Z
C344
0.1U_0402_16V4Z
C343
0.1U_0402_16V4Z
+3VS
R165
R940
+1.25VS
R956
No Stuff
R914
R921
R930
Stuff
R959
R930
R914
No Stuff
R919
R940
R956
R949
R943
R921
R943
R949
1
R125
2
0_1206_5%
R954
1
C319
10U_0805_10V4Z
1
C332
0.1U_0402_16V4Z
1
C341
0.1U_0402_16V4Z
1
C326
10U_0805_10V4Z
1
C334
0.1U_0402_16V4Z
R152
2.2K_0402_5%
Q12
2N7002_SOT23
C339
0.1U_0402_16V4Z
CLK_SMBDATA
CLK_SMBCLK
21,26,27 ICH_SMBDATA
2.2K_0402_5%
2
G
*(Default)
+1.25VS_CK505
R919
Stuff
0.1U_0402_16V4Z
CPU Driven
C331
33.3
C329
+3VS_CK505
+3VS
2
G
667MHz
Stuff
800MHz
No Stuff
R959
R930
R921
R919
R940
R956
R949
R943
R914
21,26,27 ICH_SMBCLK
2N7002_SOT23
Q9
+3VS_CK505
+VCCP
@ R472
56_0402_5%
1
R471
0_0402_5%
CPU_BSEL0
MCH_CLKSEL0 7
R468
1K_0402_5%
VDD_PCI
VDD48
VDDPLL3
VDDREF
39
55
VDDSRC
VDDCPU
12
20
26
VDD96_IO
VDDPLL3_IO
VDDSRC_IO
36
49
VDDSRC_IO
VDDCPU_IO
NC
48
SCLK
SDATA
64
63
PCI_STOP#
CPU_STOP#
38
37
CLK_SMBCLK
CLK_SMBDATA
CLK_SMBCLK 13,14
CLK_SMBDATA 13,14
H_STP_PCI# 21
H_STP_CPU# 21
CPU0
CPU0#
54
53
R_CPU_BCLK
R_CPU_BCLK#
CPU1_F
CPU1#_F
51
50
R_MCH_BCLK
R_MCH_BCLK#
SRC8/ITP
SRC8#/ITP#
47
46
R_CPU_XDP
R_CPU_XDP#
SRC10#
SRC10
35
34
R_PCIE_NC1#
R_PCIE_NC1
R179
1
1
R178
R469
R182
1
1
R181
R177
1
1
R176
@ 1K_0402_5%
21 CLKSATAREQ#
2 R124
PCI0/CR#_A
7 CLKREQ_3GPLL#
475_0402_1%1
2 R121
PCI_CLK1 3
PCI1/CR#_B
28 CLK_PCI_1394
33_0402_5% 1
2 R123
PCI2_TME 4
PCI2/TME
33 CLK_PCI_LPC
33_0402_5% 1
2 R122
PCI_CLK3 5
32 CLK_PCI_DB
33_0402_5% 1
2 R139
27_SEL
PCI4/27_Select
19 CLK_PCI_ICH
33_0402_5% 1
2 R138
ITP_EN
PCIF5/ITP_EN
+VCCP
475_0402_1%1
R484
1K_0402_5%
FSB
1
R482
@ 0_0402_5%
CPU_BSEL1
MCH_CLKSEL1 7
R485
1K_0402_5%
2
1
CLK_XTAL_IN
60
X1
CLK_XTAL_OUT
59
X2
0_0402_5%
0_0402_5%
2
2
0_0402_5%
0_0402_5%
2
2
0_0402_5%
0_0402_5%
2
2
0_0402_5%
0_0402_5%
R173
1
1
R172
33_0402_5% 1
2 R137
FSA
10
USB_48MHZ/FSLA
FSB
57
FSLB/TEST MODE
22_0402_5% 1
22_0402_5% 1
2 R168
2 R169
FSC
62
R473
CPU_BSEL2
1
R479
@ 0_0402_5%
21 CLK_14M_ICH
32 CLK_14M_SIO
MCH_CLKSEL2 7
R476
1K_0402_5%
+1.25VS_CK505
R475
0_0402_5%
1
1
SRC9
SRC9#
30
31
R144
R_CLK_PCIE_MCard 1
R_CLK_PCIE_MCard# 1
R143
2
2
1
2
+3VS
R147
10K_0402_5%
0_0402_5%
CLK_PCIE_MCARD 27
0_0402_5%
CLK_PCIE_MCARD# 27
SRC7/CR#_F
SRC7#/CR#_E
44
43
CLKREQ_LAN#R
1
2
R185
@ 10K_0402_5%
475_0402_1%
SRC6
SRC6#
41
40
R_PCIE_LAN
R_PCIE_LAN#
R175
1
1
R174
2
2
0_0402_5%
0_0402_5%
SRC4
SRC4#
27
28
R_MCH_3GPLL
R_MCH_3GPLL#
R127
1
1
R126
2
2
0_0402_5%
0_0402_5%
2
2
0_0402_5%
0_0402_5%
2
2
0_0402_5%
0_0402_5%
2
R184
REF0/FSLC/TEST_SEL
45
VDDSRC_IO
SRC3/CR#_C
SRC3#/CR#_D
24
25
R_PCIE_ICH
R_PCIE_ICH#
R146
1
1
R145
42
GNDSRC
SRC2/SATA
SRC2#/SATA#
21
22
R_PCIE_SATA
R_PCIE_SATA#
R129
1
1
R128
GNDPCI
SRC1/SE1/27MHz_NonSS
SRC1#/SE2/27MHz_SS
17
18
R_SSCDREFCLK R1421
R_SSCDREFCLK#R1411
R132 1
R131 1
R136
R_MCH_DREFCLK
1
R_MCH_DREFCLK# 1
R135
R134
1
R133
1
ITP_EN
GNDCPU
23
GNDSRC
29
GNDSRC
R458
10K_0402_5%
CK_PWRGD/PD#
GNDREF
2
R461
10K_0402_5%
UMA@
13
14
2
10K_0402_5%
CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7
CLK_PCIE_ICH 21
CLK_PCIE_ICH# 21
CLK_PCIE_SATA 20
CLK_PCIE_SATA# 20
MCH_SSCDREFCLK 7
MCH_SSCDREFCLK# 7
CLK_27M_VGA 18
CLK_27M_VGA# 18
2UMA@ 0_0402_5%
2UMA@ 0_0402_5%
CLK_MCH_DREFCLK 7
CLK_MCH_DREFCLK# 7
2VGA@ 0_0402_5%
2VGA@ 0_0402_5%
1
@ 10K_0402_5%
R459
10K_0402_5%
@
CLK_PCIE_VGA 18
CLK_PCIE_VGA# 18
2006/08/04
Issued Date
C345
C317
C346
C299
C311
C318
1 CLK_48M_ICH
@ 5P_0402_50V8C
1 CLK_14M_ICH
@ 4.7P_0402_50V8C
1 CLK_PCI_ICH
@ 4.7P_0402_50V8C
1 CLK_14M_SIO
@ 4.7P_0402_50V8C
1 CLK_PCI_1394
@ 4.7P_0402_50V8C
1 CLK_PCI_LPC
@ 4.7P_0402_50V8C
1 CLK_PCI_DB
@ 4.7P_0402_50V8C
A
ICS9LPRS365/SA00001GT00
2006/10/06
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C316
CK_PWRGD 21
+3VS_CK505
Security Classification
CLK_PCIE_LAN 24
CLK_PCIE_LAN# 24
2UMA@ 0_0402_5%
2UMA@ 0_0402_5%
2VGA@ 0_0402_5%
2VGA@ 0_0402_5%
56
2
R487
+3VS
CLKREQ_LAN# 24
SLG8SP510_TSSOP64
PCI2_TME
SRC0/DOT96
SRC0/DOT96#
58
27_SEL
R462
10K_0402_5%
GND
52
CLK_XTAL_OUT
27P_0402_50V8J
C347
19
+3VS
CLKREQ_NC1# 26
CLKREQ_MCARD# 27
Title
Y1
14.31818MHZ_16PF_DSX840GA
27P_0402_50V8J
GND
+3VS_CK505
R464
10K_0402_5%
VGA@
C348
A
R465
10K_0402_5%
@
CLK_XTAL_IN
+3VS_CK505
2
+3VS_CK505
GND48
15
11
CLK_PCIE_NC1# 26
CLK_PCIE_NC1 26
R167
CLKREQ#_H
2
CLKREQ_MCARD#R 2
R148
@ 1K_0402_5%
1
FSC
R478
2.2K_0402_5%
2
1
CLK_PCIE_MCARD1 27
CLK_PCIE_MCARD1# 27
33
32
21 CLK_48M_ICH
CLK_MCH_BCLK 7
CLK_MCH_BCLK# 7
SRC11/CR#_H
SRC11#/CR#_G
1
R515
+VCCP
CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4
1
2
R166
10K_0402_5%
475_0402_1%
475_0402_1%
PCI3
R481
@ 0_0402_5%
2
2
+1.25VS_CK505
R467
2.2K_0402_5%
FSA 2
1
U3
2
9
16
61
Size
Document Number
Rev
0.1
IGT30 LA-3571P
Date:
Sheet
15
of
47
+LCDVDD
1
+3VS
R886
0_0805_5%
+LCDVDD
1+LCDVDD_R 2
+5VALW
UMA@
1
R849
2
G
S
2
10K_0402_5%
1
2N7002_SOT23
Q27
UMA@
2 R437
1
UMA@ 0_0402_5%
3
AO3413_SOT23
UMA@
1
C213
4.7U_0805_10V4Z
UMA@
C232
4.7U_0805_10V4Z
UMA@
Q28
DTC124EK_SC59
UMA@
C215
0.047U_0402_16V4Z
UMA@
9 GMCH_LVDDEN
R452
100K_0402_5%
UMA@
C212
0.1U_0402_16V4Z
UMA@
R446
100_0402_1%
UMA@
2
G
Q3
R434
100K_0402_5%
UMA@
INVPWR_B+
L14
2 0_0805_5%
@ L13
2 0_0805_5%
0.1U_0603_50V4Z
+3VS
C526
2
B+
R116
2
1
C527
68P_0402_50V8K
33
INVT_PWM
33
DAC_BRIG
INVPWR_B+
DISPOFF#
33
BKOFF#
ENBKL
@
9 GMCH_ENBKL
2 R117
1
UMA@ 0_0402_5%
DISPOFF#
D3
CH751H-40_SC76
1
2
33
1
2
3
4
5
6
7
4.7K_0402_5%
JP40
D2
CH751H-40_SC76
1
2
MOLEX_53780-0790
2 R118
1
VGA@ 0_0402_5%
R669
2.2K_0402_5%
VGA@
R119
100K_0402_5%
UMA@
1
18 G7X_ENBKL
Issued Date
2006/08/04
2006/10/06
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Security Classification
Title
LVDS Connector
Size Document Number
Custom IGT30 LA-3571P
Date:
Rev
0.1
Sheet
16
H
of
47
TV-OUT Conn.
1
0_0402_5%
18 CARD_COMP
TV_LUMA
TV_CRMA
TV_COMPS
2
1
R455 UMA@ 0_0402_5%
2
1
R454 UMA@ 0_0402_5%
2
1
R456 @
0_0402_5%
CRMA
@
COMP
1
@
2
C847
82P_0402_50V8J
2
R98
LUMA
C846
82P_0402_50V8J
1
VGA@ 0_0402_5%
C845
82P_0402_50V8J
2
R86
C850
82P_0402_50V8J
18 CARD_CRMA
L52
1
2
FLM1608081R8K_0603
L53
1
2
FLM1608081R8K_0603
L54
1
2
FLM1608081R8K_0603
C849
82P_0402_50V8J
1
VGA@ 0_0402_5%
C848
82P_0402_50V8J
2
R88
R6
150_0402_1%
2
1
R5
150_0402_1%
2
1
R7
150_0402_1%
2
1
18 CARD_LUMA
S-VIDEO
@
2
JP71
1
2
3
4
5
6
CRMA
LUMA
COMP
CRT Conn.
L55
BK1608LL121-T 0603
1
2
L56
BK1608LL121-T 0603
1
2
L57
BK1608LL121-T 0603
1
2
2
R83
18 CARD_VGA_B
2
R84
1
0_0402_5%
1
0_0402_5%
VGA@
CRT_B
1
C851
C3
@
G2
GREEN
BLUE
+CRT_VCC
DSUB
JP72
+5VS +CRT_VCC
RED
D31
GREEN
22P_0402_50V8J
CRT_G
UMA@
2
1
R447
0_0402_5%
UMA@
2
1
R451
0_0402_5%
UMA@
2
1
R453
0_0402_5%
22P_0402_50V8J
C2
R2
150_0402_1%
2
1
R3
150_0402_1%
2
1
R4
150_0402_1%
2
1
CRT_R
G1
MOLEX_53780-0670
ME@
1
2
3
4
5
6
7
8
9
10
11
12
13
14
BLUE
JVGA_VS
RB751V_SOD323
1
22P_0402_50V8J
C1
VGA@
1
2
3
4
5
6
RED
22P_0402_50V8J
18 CARD_VGA_G
1
0_0402_5%
22P_0402_50V8J
C853
2
R82
22P_0402_50V8J
C852
VGA@
18 CARD_VGA_R
JVGA_HS
MSEMS#
VGA_DDC_DAT
VGA_DDC_CLK
+CRT_VCC +CRT_VCC
C800
0.01U_0402_25V4Z
PIN4
1
C801
1
2
3
4
5
6
7 15
8 16
9
10
11
12
13
14
15
16
ACES_87213-1400
ME@
2 0.1U_0402_16V4Z
Q2
1 2N7002_SOT23
3VDDCCL
2
0_0402_5%
DDCDA
2
0_0402_5%
DDC CL
Q1
1 2N7002_SOT23
VGA_DDC_CLK
R441
3VDDCDA
VGA_DDC_DAT
G
UMA@
9
PIN ASSIGMENT
R77
R79
VGA@1
10_0402_5%
VGA@ 0_0402_5%
2
2
R851
2.2K_0402_5%
1
2
1
R8
2.2K_0402_5%
R12
2.2K_0402_5%
18 CARD_DDCDATA
18 CARD_DDCCLK
R850
2.2K_0402_5%
1
2
+3VS
+3VS
UMA@
1 UMA@ 2
R439
39_0402_5%
CRT_VSYNC
1 UMA@ 2
R443
39_0402_5%
L58
4
CHB1608B121_0603
1
2
R853
1K_0402_5%
U1
Y
JVGA_HS
G
VSYNC
C5
U2
Y
74AHCT1G125GW_SOT353-5
+CRT_VCC
CRT_HSYNC
2
R81
HSYNC
OE#
18 CARD_VSYNC
VGA@
1
0_0402_5%
VGA@
1
0_0402_5%
0.1U_0402_16V4Z
18 CARD_HSYNC
2
R78
R852
1K_0402_5%
R1
1K_0402_5%
C4
5
0.1U_0402_16V4Z
OE#
+CRT_VCC +CRT_VCC
+CRT_VCC
R444
L59
JVGA_VS
CHB1608B121_0603
74AHCT1G125GW_SOT353-5
2006/08/04
2006/10/06
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
FUNCTION
+CRT_VCC
RED
GND
GREEN
GND
BLUE
GND
VSYNC
GND
HSYNC
SENSE
SM_DAT
SM_CLK
PIN4
Security Classification
Issued Date
PIN D-SUB
9
1
1
2
6
3
2
4
7
5
3
6
8
7
14
8
10
9
13
10
11
11
12
12
15
13
4
14
Title
Rev
0.1
Sheet
17
of
47
PEG_M_TXP[0..15] 9
PEG_M_TXN[0..15]
PEG_M_TXN[0..15] 9
PEG_RXP[0..15]
PEG_M_TXP13
PEG_M_TXN13
PEG_M_TXP15
PEG_M_TXN15
+1.5VS
+3VS
+2.5VS
PEG_M_TXP0
PEG_M_TXN0
PEG_RXP3
PEG_RXN3
PEG_M_TXP2
PEG_M_TXN2
PEG_RXP5
PEG_RXN5
PEG_M_TXP4
PEG_M_TXN4
PEG_RXP7
PEG_RXN7
PEG_M_TXP6
PEG_M_TXN6
PEG_RXP9
PEG_RXN9
PEG_M_TXP8
PEG_M_TXN8
PEG_RXP11
PEG_RXN11
PEG_M_TXP10
PEG_M_TXN10
PEG_RXP13
PEG_RXN13
PEG_M_TXP12
PEG_M_TXN12
PEG_RXP15
PEG_RXN15
PEG_M_TXP14
PEG_M_TXN14
+5VS
+1.8VS
15 CLK_PCIE_VGA
15 CLK_PCIE_VGA#
17 CARD_DDCCLK
17 CARD_DDCDATA
B+
17 CARD_VSYNC
17 CARD_HSYNC
17 CARD_VGA_R
17 CARD_VGA_G
17 CARD_VGA_B
ACES_88363-08001
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
PEG_RXN[0..15]
PEG_RXN[0:15] 9
PEG_RXP0
PEG_RXN0
PEG_RXP2
PEG_RXN2
PEG_RXP4
PEG_RXN4
PEG_RXP6
PEG_RXN6
PEG_RXP8
PEG_RXN8
+5VS
PEG_RXP10
PEG_RXN10
PEG_RXP12
PEG_RXN12
PEG_RXP14
PEG_RXN14
SUSP#
G7X_THER_ALERT#
SUSP#
23,26,28,29,33,35,42,43,44
VGA_THER_ALERT# 21
1
VGA@
+2.5VS
VGA@
VGA@
0.1U_0402_16V4Z
C216
PEG_M_TXP11
PEG_M_TXN11
PEG_RXP1
PEG_RXN1
0.1U_0402_16V4Z
C228
PEG_M_TXP9
PEG_M_TXN9
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
0.1U_0402_16V4Z
C248
PEG_M_TXP7
PEG_M_TXN7
C
PEG_RXP[0:15] 9
JP8
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
VGA@
G7X_ENBKL 16
PLT_RST# 7,19,21,23,24,26,27
CLK_27M_VGA 15
CLK_27M_VGA# 15
+3VS
CARD_COMP 17
CARD_LUMA 17
CARD_CRMA 17
ACES_88363-08001
VGA@
C226
0.047U_0402_16V4Z
PEG_M_TXP5
PEG_M_TXN5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
0.1U_0402_16V4Z
C252
PEG_M_TXP3
PEG_M_TXN3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
C227
0.047U_0402_16V4Z
JP7
PEG_M_TXP1
PEG_M_TXN1
VGA@
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
Size
Document Number
Custom IGT30 LA-3571P
Date:
Sheet
18
Rev
0.1
of
47
+3VS
1
R253
1
R254
1
R219
1
R585
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
PCI_DEVSEL#
1
R536
1
R216
1
R233
1
R539
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
PCI_PLOCK#
28 PCI_AD[0..31]
U28B
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI _IRDY#
PCI_SERR#
PCI_PERR#
+3VS
1
R226
1
R532
1
R199
1
R544
1
R217
1
R235
1
R244
1
R524
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
PCI_PIRQA#
1
R528
1
R272
1
R592
1
R549
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
PCI_REQ0#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
D20
E19
D19
A20
D17
A21
A19
C19
A18
B16
A12
E16
A14
G16
A15
B6
C11
A9
D11
B12
C12
D10
C7
F13
E11
E13
E12
D8
A6
E8
D6
A3
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
F9
B5
C5
A10
PIRQA#
PIRQB#
PIRQC#
PIRQD#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
PCI
REQ0#
GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55
A4
D7
E18
C18
B19
F18
A11
C10
PCI_REQ0#
PCI_GNT0#
PCI_REQ1#
PCI_GNT1#
PCI_REQ2#
PCI_GNT2#
PCI_REQ3#
PCI_GNT3#
C/BE0#
C/BE1#
C/BE2#
C/BE3#
C17
E15
F16
E17
PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3
IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#
C8
D9
G6
D16
A7
B7
F10
C16
C9
A17
PCI _IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PLTRST#
PCICLK
PME#
AG24
B10
G7
PCI_PLTRST#
CLK_PCI_ICH
PCI_PME#
@
1
R195
Interrupt I/F
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
F8
G11
F12
B3
PCI_REQ0# 28
PCI_GNT0# 28
PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3
28
28
28
24,28
PCI_IRDY# 28
PCI_PAR 28
PCI_DEVSEL# 28
PCI_PERR# 28
PCI_SERR# 28
PCI_STOP# 28
PCI_TRDY# 28
PCI_FRAME# 28
CLK_PCI_ICH 15
PCI_PME# 33
2
+3VALW
8.2K_0402_5%
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
PCI_PIRQG# 28
PCI_PIRQH# 28
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#
PCI_GNT3#
R234
@
1K_0402_5%
+3V_SB
PCI
2
LPC
R189
0_0402_5%
1
*
1
PCI_RST#
1
PCI_RST# 28,32,33
R188
100K_0402_5%
U11
Y
R225
PCI_PLTRST#
R286
@ 1K_0402_5%
R214
@ 1K_0402_5%
CLK_PCI_ICH
PLT_RST#
PLT_RST# 7,18,21,23,24,26,27
@ TC7SH08FU_SSOP5
R289
0_0402_5%
1
R283
100K_0402_5%
10_0402_5%
1
SB_SPI_CS#1
21 SB_SPI_CS#1
@ TC7SH08FU_SSOP5
+3V_SB
PCI_GNT0#
U5
Y
SPI
PCI_PCIRST#
SPI_CS#1
PCI_GNT0#
C383
@ 8.2P_0402_50V
Security Classification
2006/08/04
Issued Date
2006/10/06
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
Title
Size
Document Number
Rev
0.1
IGT30 LA-3571P
Date:
Sheet
19
of
47
+3VS
R251
GATEA20
10K_0402_5%
ICH_INTVRMEN
R247
KB_RST#
C659
+RTCVCC
15P_0402_50V8J
10K_0402_5%
ICH_RTCX1
Y3
R614
10M_0402_5%
+VCCP
R299
C651
+RTCVCC
1
R576
15P_0402_50V8J
ICH_RTCRST#
2
20K_0402_5%
C623
CLRP1
2MM
RTCX1
RTCX2
AF23
RTCRST#
SM_INTRUDER# AD22
INTRUDER#
ICH_INTVRMEN AF25
LAN100_SLP
AD21
INTVRMEN
LAN100_SLP
1
1
1U_0603_10V4Z
AG25
AF24
B24
GLAN_CLK
D22
LAN_RSTSYNC
C21
B21
C22
LAN_RXD0
LAN_RXD1
LAN_RXD2
D21
E20
C20
LAN_TXD0
LAN_TXD1
LAN_TXD2
AH21
C
R616 1
+1.5VS
2 24.9_0402_1%
GLAN_COMP
D25
C25
GLAN_DOCK#/GPIO13
GLAN_COMPI
GLAN_COMPO
27 HDA_BITCLK_MDC
27 HDA_SYNC_MDC
R565 1
R556 1
2 33_0402_5%
2 33_0402_5%
HDA_BITCLK_R
H DA_SYNC_R
AJ16
AJ15
HDA_BIT_CLK
HDA_SYNC
27 HDA_RST_MDC#
R552 1
2 33_0402_5%
HDA_RST_R#
AE14
HDA_RST#
29 HDA_SDIN0
27 HDA_SDIN1
R547 1
27 HDA_SDOUT_MDC
2 33_0402_5%
27
23
+3VS
10K_0402_5%
1 R227
SATA_LED#
23 PSATA_ITX_DRX_P0
AJ17
AH17
AH15
AD13
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
HDA_SDOUT_R
AE13
HDA_SDOUT
AE10
AG14
HDA_DOCK_EN#/GPIO33
HDA_DOCK_RST#/GPIO34
AF10
SATALED#
AF6
AF5
AH5
AH6
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
AG3
AG4
AJ4
AJ3
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
AF2
AF1
AE4
AE3
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
AB7
AC6
SATA_CLKN
SATA_CLKP
AG1
AG2
SATARBIAS#
SATARBIAS
KILL_MDC#
IDERST_CD#
SATA_LED#
36 SATA_LED#
PSATA_IRX_DTX_N0_C
PSATA_IRX_DTX_P0_C
PSATA_ITX_DRX_N0_C
PSATA_ITX_DRX_P0_C
23 PSATA_IRX_DTX_N0_C
23 PSATA_IRX_DTX_P0_C
23 PSATA_ITX_DRX_N0
ICH_AC_SDIN0
ICH_AC_SDIN1
KILL_MDC#
IDERST_CD#
PSATA_ITX_DRX_N0
1
C582
PSATA_ITX_DRX_N0_C
2
3900P_0402_50V7K
PSATA_ITX_DRX_P0
1
C584
PSATA_ITX_DRX_P0_C
2
3900P_0402_50V7K
15 CLK_PCIE_SATA#
15 CLK_PCIE_SATA
CLK_PCIE_SATA#
CLK_PCIE_SATA
R517
1
H_DPRSTP#
H_DPSLP#
LPC_AD[0..3] 32,33
U28A
ICH_RTCX2
H_FERR#
24.9_0402_1%
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
E5
F5
G8
F6
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
FWH4/LFRAME#
C4
LPC_FRAME#
LDRQ0#
LDRQ1#/GPIO23
G9
E6
LPC_DRQ0#
A20GATE
A20M#
AF13
AG26
GATEA20
H_A20M#
DPRSTP#
DPSLP#
AF26
AE26
H_DPRSTP_R#
FERR#
AD24
H_FERR#
CPUPWRGD/GPIO49
AG29
H_PW RGOOD
IGNNE#
AF27
H_IGNNE#
INIT#
INTR
RCIN#
AE24
AC20
AH14
H_INIT#
H_INTR
KB_RST#
NMI
SMI#
AD23
AG28
H_NMI
H_SMI#
LPC_FRAME# 32,33
56_0402_5%
R331
@
1
56_0402_5%
R324
@
1
56_0402_5%
LPC_DRQ#0 32
GATEA20 33
H_A20M# 4
H_DPRSTP#
1
0_0402_5%
2
R327
H_DPRSTP# 5,7,45
H_DPSLP# 5
H_FERR# 4
H_PWRGOOD 5
H_IGNNE# 4
H_INIT# 4
H_INTR 4
KB_RST# 33
+VCCP
C
OUT
H_NMI 4
H_SMI# 4
STPCLK#
AA24
H_STPCLK#
THRMTRIP#
AE27
THRMTRIP_ICH#
TP8
AA23
R328
56_0402_5%
H_STPCLK# 4
1
R329
IN
NC
NC
RTC
LPC
330K_0402_1%
2 ICH_INTVRMEN
LAN / GLAN
CPU
R319
1
32.768KHZ_12.5P_1TJS125BJ2A251
IHDA
1M_0402_5%
2 SM_INTRUDER#
IDE
R295
1
SATA
330K_0402_1%
2 LAN100_SLP
R287
1
24_0402_1%
H_THERMTRIP# 4,7
PD_D[0..15] 23
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15
V1
U2
V3
T1
V4
T5
AB2
T6
T3
R2
T4
V6
V5
U1
V2
U6
PD_D0
PD_D1
PD_D2
PD_D3
PD_D4
PD_D5
PD_D6
PD_D7
PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15
DA0
DA1
DA2
AA4
AA1
AB3
PD_A0
PD_A1
PD_A2
DCS1#
DCS3#
Y6
Y5
PD_CS#1
PD_CS#3
DIOR#
DIOW#
DDACK#
IDEIRQ
IORDY
DDREQ
W4
W3
Y2
Y3
Y1
W5
PD_IOR#
PD_IOW#
PD_DACK#
PD_IRQ
PD _IORDY
PD_DREQ
+3VS
PD_A0
PD_A1
PD_A2
23
23
23
PD _IORDY
PD_IRQ
R192 1
R196 1
2 4.7K_0402_5%
2 8.2K_0402_5%
B
PD_CS#1 23
PD_CS#3 23
PD_IOR# 23
PD_IOW# 23
PD_DACK# 23
PD_IRQ
23
PD_IORDY 23
PD_DREQ 23
BATT1.1
Close to ICH
+RTCVCC
+3VS
R543
1 HDA_SDOUT_AUDIO
@ 1K_0402_5%
1
R548
29 HDA_SDOUT_AUDIO
2 HDA_SDOUT_R
33_0402_5%
1
R557
29 HDA_SYNC_AUDIO
1
R553
29 HDA_RST_AUDIO#
1
1 R564
29 HDA_BITCLK_AUDIO
R249
1
2 H DA_SYNC_R
33_0402_5%
2 HDA_RST_R#
33_0402_5%
W=20mils
100_0603_1%
C396
D8
1
0.1U_0402_16V4Z
+CHGRTC ML1220T13RE
45@
A
RB751V_SOD323
2 HDA_BITCLK_R
33_0402_5%
@ C394
27P_0402_50V8J
Security Classification
2006/08/04
Issued Date
2006/10/06
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
BATT1
Title
Rev
0.1
Sheet
20
of
47
2ICH_PCIE_WAKE#
1K_0402_5%
1ICH_LOW_BAT#
8.2K_0402_5%
1
45 CLK_ENABLE#
R582
@ 330_0402_5%
1
R588
29
2
TP7
OCP#
AJ8
AJ9
AH9
AE16
AC19
AG8
AH12
AE11
AG10
AH25
AD16
AG13
AF9
AJ11
AD10
TACH1/GPIO1
TACH2/GPIO6
TACH3/GPIO7
GPIO8
GPIO12
TACH0/GPIO17
GPIO18
GPIO20
SCLOCK/GPIO22
QRT_STATE0/GPIO27
QRT_STATE1/GPIO28
SATACLKREQ#/GPIO35
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48
SB_SPKR
SB_SPKR
AD9
SPKR
MCH_ICH_SYNC#AJ13
ICH_RSVD
MCH_SYNC#
AJ21
SATA
GPIO
TP3
ICH8M REV 1.0
AG23
AF21
AD18
SLP_S3#
SLP_S4#
SLP_S5#
S4_STATE#/GPIO26
AH27
PWROK
AE23
2 SB_SPKR
@ 10K_0402_5%
1
R222
DPRSLPVR/GPIO16
AJ14
BATLOW#
AE21
ICH_LOW_BAT#
PWRBTN#
C2
LAN_RST#
AH20
RSMRST#
AG27
PBTN_OUT#
PBTN_OUT# 33
1
2
R277
0_0402_5%
EC_RSMRST#R
E1
CK_PWRGD_R
E3
M_PWROK
PLT_RST# 7,18,19,23,24,26,27
EC_RSMRST#R 1
R325
2 CK_PW RGD
0_0402_5%
1
R511
SLP_M#
AJ25
CL_CLK0
CL_CLK1
F23
AE18
CL_CLK0
CL_DATA0
CL_DATA1
F22
AF19
CL_DATA0
CL_VREF0
CL_VREF1
D24
AH23
CL_VREF0_ICH
CL_VREF1_ICH
CL_RST#
AJ23
CL_RST#
MEM_LED/GPIO24
ME_EC_ALERT/GPIO10
EC_ME_ALERT/GPIO14
WOL_EN/GPIO9
AJ27
AJ24
AF22
AG19
1
2
3
4
USB_OC#6
CPUSB#
USB_OC#2
USB_OC#4
10K_1206_8P4R_5%
RP16
5
6
7
8
M_PWROK 7
CL_CLK0 7
4
3
2
1
USB_OC#5
USB_OC#7
USB_OC#9
USB_OC#0
0.1U_0402_16V7K
0.1U_0402_16V7K
24
24
24
24
PCIE_RXN4
PCIE_RXP4
PCIE_TXN4
PCIE_TXP4
0.1U_0402_16V7K
0.1U_0402_16V7K
31
26
37
USB_OC#0
CPUSB#
USB_OC#2
37
USB_OC#4
M27
M26
L29
L28
PERN2
PERP2
PETN2
PETP2
C676
C677
PCIE_RXN3
PCIE_RXP3
PCIE_C_TXN3
PCIE_C_TXP3
K27
K26
J29
J28
PERN3
PERP3
PETN3
PETP3
C678
C679
PCIE_RXN4
PCIE_RXP4
PCIE_C_TXN4
PCIE_C_TXP4
H27
H26
G29
G28
PERN4
PERP4
PETN4
PETP4
SB_SPI_CS#1
USB_OC#0
CPUSB#
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7
USB_OC#8
USB_OC#9
USB_OC#6
USB_OC#8
1 USB_OC#8
10K_0402_5%
1 USB_OC#3
10K_0402_5%
F27
F26
E29
E28
PERN5
PERP5
PETN5
PETP5
D27
D26
C29
C28
PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP
C23
B23
E22
SPI_CLK
SPI_CS0#
SPI_CS1#
D23
F21
SPI_MOSI
SPI_MISO
AJ19
AG16
AG15
AE15
AF15
AG17
AD12
AJ18
AD14
AH18
OC0#
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
OC8#
OC9#
DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0
V27
V26
U29
U28
CL_RST# 7
33,39
0.1U_0402_16V4Z
1
C644
1
R593
2
@ 3.24K_0402_1%
+3V_SB
R594
453_0402_1%
@
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
Y27
Y26
W29
W28
DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
AB26
AB25
AA29
AA28
DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2
DMI_RXN2 7
DMI_RXP2 7
DMI_TXN2 7
DMI_TXP2 7
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
AD27
AD26
AC29
AC28
DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3
DMI_RXN3 7
DMI_RXP3 7
DMI_TXN3 7
DMI_TXP3 7
DMI_CLKN
DMI_CLKP
T26
T25
CLK_PCIE_ICH#
CLK_PCIE_ICH
DMI_ZCOMP
DMI_IRCOMP
Y23
Y24
DMI_IRCOMP
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
G3
G2
H5
H4
H2
H1
J3
J2
K5
K4
K2
K1
L3
L2
M5
M4
M2
M1
N3
N2
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7
USB20_N8
USB20_P8
USB20_N9
USB20_P9
USBRBIAS#
USBRBIAS
F2
F3
USBRBIAS
USB
RSMRST circuit
DMI_RXN0 7
DMI_RXP0 7
DMI_TXN0 7
DMI_TXP0 7
R621
Q35
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7
USB20_N8
USB20_P8
USB20_N9
USB20_P9
1
R499
33 EC_RSMRST#
R626
@ 2.2K_0402_5%
D23B
R628
@ MMBT3906_SOT23
1
2
R624
@ 4.7K_0402_5%
+1.5VS
31
31
27
27
37
37
36
36
37
37
26
26
PORT
0
1
2
3
4
5
6
7
8
9
27
27
27
27
2
22.6_0402_1%
2006/10/06
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
+3V_SB
D23A
BAV99DW-7_SOT363
@ 2.2K_0402_5%
Security Classification
EC_RSMRST#R
BAV99DW-7_SOT363
CLK_PCIE_ICH# 15
CLK_PCIE_ICH 15
R296 24.9_0402_1%
1
2
0_0402_5%
2
DMI_RXN1 7
DMI_RXP1 7
DMI_TXN1 7
DMI_TXP1 7
2
+3VS
@ 3.24K_0402_1%
R314
453_0402_1%
@
EC_FLASH#
EC_FLASH#
1
2
ACIN
R318
@ 0_0402_5%
WOL_EN
WOL_EN
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
Issued Date
1
R313
PCIE_RXN3
PCIE_RXP3
PCIE_TXN3
PCIE_TXP3
PCIE_RXN2
PCIE_RXP2
PCIE_C_TXN2
PCIE_C_TXP2
C419
@
26
26
26
26
C674
C675
10K_1206_8P4R_5%
2
R248
2
R258
0.1U_0402_16V4Z
CL_DATA0 7
PCI-Express
Direct Media Interface
0.1U_0402_16V7K
0.1U_0402_16V7K
PERN1
PERP1
PETN1
PETP1
2
10K_0402_5%
CK_PWRGD 15
SPI
8
7
6
5
PCIE_RXN2
PCIE_RXP2
PCIE_TXN2
PCIE_TXP2
19 SB_SPI_CS#1
RP14
+3V_SB
27
27
27
27
C672
C673
P27
P26
N29
N28
@ 4.7P_0402_50V8C
ICH_POK
LAN
0.1U_0402_16V7K
0.1U_0402_16V7K
PCIE_RXN1
PCIE_RXP1
PCIE_C_TXN1
PCIE_C_TXP1
C385
NEW CARD
B
PCIE_RXN1
PCIE_RXP1
PCIE_TXN1
PCIE_TXP1
@ 4.7P_0402_50V8C
WLAN
27
27
27
27
C349
SLP_S3# 33
SLP_S4# 33
SLP_S5# 33
U28D
TV TUNER
R884 100_0402_5%
M_PWROK
1
2
ICH_POK 7,33
1
2 R292
DPRSLPVR
10K_0402_5%
DPRSLPVR 7,45
CLPWROK
SLP_S3#
SLP_S4#
SLP_S5#
CK_PWRGD
@ 10_0402_5%
T18 PAD
low-->default
+3VS
AJ22
Q32
@ RHU002N06_SOT323
2
G
SMB
VRMPWRGD
GPIO39
GPIO48
7 MCH_ICH_SYNC#
2 VRMPWRGD
@ 0_0402_5%
AJ20
CLKSATAREQ#
1 ICH_RSVD
1K_0402_5%
2
@
R591
+3VS
2 DPRSLPVR
100K_0402_5%
WAKE#
SERIRQ
THRM#
VRMPWRGD
0_0402_5%
SST_CTL
EC_SMI#
EC_SCI#
EC_SMI#
EC_SCI#
SB_INT_FLASH_SEL#
PAD T24
15 CLKSATAREQ#
18 VGA_THER_ALERT#
R246
OCP#
33
33
CLKRUN#/GPIO32
R228
@ 10_0402_5%
1 2
I CH_RI#
2
10K_0402_5%
1
R589
PAD T31
VGATE
AH11
ICH_PCIE_WAKE# AE17
SIRQ
AF12
EC_THERM#
AC13
R193
7,45
ICH_SUSCLK
CLK_14M_ICH 15
CLK_48M_ICH 15
2XDP_DBRESET#
10K_0402_5%
PCI_CLKRUN#
28,33 PCI_CLKRUN#
24,26,27 ICH_PCIE_WAKE#
28,32,33
SIRQ
4,33 EC_THERM#
CLK_14M_ICH
R291
1
0_0402_5%
SUSCLK
D3
BMBUSY#/GPIO0
AG22
1
2
R323
0_0402_5% SMBALERT#/GPIO11
H_STP_PCI#
AE20 STP_PCI#/GPIO15
R_STP_CPU#
AG18 STP_CPU#/GPIO25
1
CLK_14M_ICH
CLK_48M_ICH
AG9
G5
R271
2CL_RST#
10K_0402_5%
SUS_STAT#/LPCPD#
SYS_RESET#
AG12
CLK14
CLK48
R265
@ R584
RI#
AJ12
AJ10
AF11
AG11
R257
PM_BMBUSY#
7 PM_BMBUSY#
SATA0GP/GPIO21
SATA1GP/GPIO19
SATA2GP/GPIO36
SATA3GP/GPIO37
R432
H_STP_PCI#
H_STP_CPU#
2 LINKALERT#
10K_0402_5%
R284
15
15
GPIO48
2
10K_0402_5%
R232
+3V_SB
GPIO39
2
10K_0402_5%
AF17
F4
XDP_DBRESET# AD15
4 XDP_DBRESET#
@ R278
10K_0402_5%
SMBCLK
SMBDATA
LINKALERT#
SMLINK0
SMLINK1
+3VS
33 EC_LID_OUT#
1
ICH_SMB_CLK
AJ26
ICH_SMB_DATA AD19
LINKALERT#
AG21
ME__EC_CLK1
AC17
ME__EC_DATA1 AE19
I CH_RI#
R583
10K_0402_5%
R542
U28C
2.2K_0402_5%
0320 add
WOL_EN
2
10K_0402_5%
R273
CLK_48M_ICH
R229
+3VS
R236
8.2K_0402_5%
Clocks
OCP#
2
10K_0402_5%
R252
2 CLKSATAREQ#
10K_0402_5%
2.2K_0402_5%
R264
10K_0402_5%
15,26,27 ICH_SMBCLK
15,26,27 ICH_SMBDATA
R274
10K_0402_5%
2 EC_THERM#
8.2K_0402_5%
@ 1
R237
2 VGA_THER_ALERT#
10K_0402_5%
R322
R243
+3V_SB
SYS
GPIO
2 PCI_CLKRUN#
8.2K_0402_5%
Power MGT
+3V_SB
MISC
GPIO
Controller Link
R242
2 SIRQ
10K_0402_5%
R245
+3VS
Title
DEVICE
LEFT SIDE
WIRELESS
RIGHT SIDE
CMOS
RIGHT SIDE
NEW CARD
A
BT(HDL20)
3G
Rev
0.1
Sheet
21
of
47
+RTCVCC
U28E
20 mils
C423
0.1U_0402_16V4Z
C424
0.1U_0402_16V4Z
+VCCP
0.1U_0402_16V7K
U28F
+5VS
C428
C418
C426
+3VS
2.2U_0603_6.3V4Z
10U_0805_6.3V6M
R572
D22
CH751H-40_SC76
20 mils
100_0402_5%
ICH_V5REF_RUN
1
C627
0.1U_0402_16V4Z
D4
C354
0.1U_0402_16V4Z
C358
+1.5VS
C351
1U_0603_10V4Z
C372
1U_0603_10V4Z
+1.5VS
+1.5VS
1
C368
0.1U_0402_16V4Z
2
+1.5VS
C366
0.1U_0402_16V4Z
R615
1
2
+1.5VS
CHB1608U301_0603
1
C655
AC10
AC9
VCC1_5_A[11]
VCC1_5_A[12]
AA5
AA6
VCC1_5_A[13]
VCC1_5_A[14]
G12
G17
H7
VCC1_5_A[15]
VCC1_5_A[16]
VCC1_5_A[17]
AC7
AD7
VCC1_5_A[18]
VCC1_5_A[19]
10U_0805_6.3V6M
D1
VCCUSBPLL
F1
L6
L7
M6
M7
VCC1_5_A[20]
VCC1_5_A[21]
VCC1_5_A[22]
VCC1_5_A[23]
VCC1_5_A[24]
W23
VCC1_5_A[25]
VCCLAN1_05[1]
VCCLAN1_05[2]
F19
G20
VCCLAN3_3[1]
VCCLAN3_3[2]
A24
4.7U_0805_10V4Z
A26
2
A27
1
CHB1608U301_0603
B26
C663
B27
B28
2
VCCGLANPLL
+3VS
AC23
AC24
VCC3_3[01]
AF29
VCC3_3[02]
AD2
VCC3_3[07]
VCC3_3[08]
VCC3_3[09]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]
AA3
U7
V7
W1
W6
W7
Y7
VCC3_3[14]
VCC3_3[15]
VCC3_3[16]
VCC3_3[17]
VCC3_3[18]
VCC3_3[19]
VCC3_3[20]
VCC3_3[21]
VCC3_3[22]
VCC3_3[23]
VCC3_3[24]
A8
B15
B18
B4
B9
C15
D13
D5
E10
E7
F11
VCCHDA
AC12
VCCSUSHDA
AD11
VCCSUS1_05[1]
VCCSUS1_05[2]
J6
AF20
VCCGLAN1_5[1]
VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]
VCCGLAN1_5[5]
B25
VCCSUS3_3[02]
VCCSUS3_3[03]
VCCSUS3_3[04]
VCCSUS3_3[05]
VCCSUS3_3[06]
VCCSUS3_3[07]
VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCCL1_05
0.1U_0402_16V4Z
R332
0.01U_0402_16V7K
C433
1
1
C436
2
+1.5VS
CHB1608U301_0603
10U_0805_6.3V6M
+1.25VS
1
C681
22U_0805_6.3V4Z
2
+VCCP
+3VS
+3VS
1
AC8
AD8
AE8
AF8
VCCSUS1_5[2]
VCC3_3[03]
VCC3_3[04]
VCC3_3[05]
VCC3_3[06]
VCCSUS3_3[01]
R618
1 +1.5VS
V_CPU_IO[1]
V_CPU_IO[2]
VCCSUS1_5[1]
2.2U_0603_10V6K
C653
2
VCC1_5_A[06]
VCC1_5_A[07]
VCC1_5_A[08]
VCC1_5_A[09]
VCC1_5_A[10]
GLAN POWER
AC1
AC2
AC3
AC4
AC5
VCC_LAN1_05_INT_ICH_1 F17
VCC_LAN1_05_INT_ICH_2 G18
T23
T25
+3VS
VCC1_5_A[01]
VCC1_5_A[02]
VCC1_5_A[03]
VCC1_5_A[04]
VCC1_5_A[05]
USB CORE
C359
0.1U_0402_16V4Z
VCCSATAPLL
ATX
+1.5VS
B
AJ6
AE7
AF7
AG7
AH7
AJ7
ARX
C362
CHB1608U301_0603
10U_0805_6.3V6M
+1.5VS
1U_0603_10V4Z
R218
AE28
AE29
C386
+3VS
C357
0.1U_0402_16V4Z
C353
2 0.1U_0402_16V4Z
0.1U_0402_16V4Z
+3VS
(DMI)
C434
(SATA)
C411
20 mils
1
R29
VCC_DMI[1]
VCC_DMI[2]
0.1U_0402_16V4Z
C421
ICH_V5REF_SUS
VCCDMIPLL
C412
0.1U_0402_16V4Z
CH751H-40_SC76
A13
B13
C13
C14
D14
E14
F14
G14
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18
C399
10_0402_5%
VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]
VCC1_05[27]
VCC1_05[28]
4.7U_0603_6.3V6M
R187
C
VCC1_5_B[01]
VCC1_5_B[02]
VCC1_5_B[03]
VCC1_5_B[04]
VCC1_5_B[05]
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]
VCCA3GP
+5VALW +3VALW
AA25
AA26
AA27
AB27
AB28
AB29
D28
D29
E25
E26
E27
F24
F25
G24
H23
H24
J23
J24
K24
K25
L23
L24
L25
M24
M25
N23
N24
N25
P24
P25
R24
R25
R26
R27
T23
T24
T27
T28
T29
U24
U25
V23
V24
V25
W25
Y25
CORE
+
C429
220U_D2_4VM
V5REF_SUS
VCCP_CORE
G4
IDE
40 mils
CHB1608U301_0603
V5REF[1]
V5REF[2]
PCI
+1.5VS
ICH_V5REF_SUS
10U_0805_6.3V6M
VCCRTC
A16
T7
VCCPSUS
R293
D
AD25
VCCPUSB
ICH_V5REF_RUN
+3VS
C352
C367
C376
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+3VS
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
1
+3V_SB
T19
C387
T26
2
AC16 VCCSUS1_5_ICH_1
T22
+3V_SB
VCCSUS1_5_ICH_2
J7
T21
0.1U_0402_16V4Z
C3
1
1
AC18
C416
C414
AC21
0.1U_0402_16V4Z
AC22
2
2
AG20
C395
2
AH28
+3V_SB
P6
P7
C1
N7
P1
P2
P3
P4
P5
R1
R3
R5
R6
G22 VCCCL1_05_ICH
VCCCL1_5
A22
VCCCL3_3[1]
VCCCL3_3[2]
F20
G21
C356
4.7U_0603_6.3V6K
A23
A5
AA2
AA7
A25
AB1
AB24
AC11
AC14
AC25
AC26
AC27
AD17
AD20
AD28
AD29
AD3
AD4
AD6
AE1
AE12
AE2
AE22
AD1
AE25
AE5
AE6
AE9
AF14
AF16
AF18
AF3
AF4
AG5
AG6
AH10
AH13
AH16
AH19
AH2
AF28
AH22
AH24
AH26
AH3
AH4
AH8
AJ5
B11
B14
B17
B2
B20
B22
B8
C24
C26
C27
C6
D12
D15
D18
D2
D4
E21
E24
E4
E9
F15
E23
F28
F29
F7
G1
E2
G10
G13
G19
G23
G25
G26
G27
H25
H28
H29
H3
H6
J1
J25
J26
J27
J4
J5
K23
K28
K29
K3
K6
VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
K7
L1
L13
L15
L26
L27
L4
L5
M12
M13
M14
M15
M16
M17
M23
M28
M29
M3
N1
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
N4
N5
N6
P12
P13
P14
P15
P16
P17
P23
P28
P29
R11
R12
R13
R14
R15
R16
R17
R18
R28
R4
T12
T13
T14
T15
T16
T17
T2
U12
U13
U14
U15
U16
U17
U23
U26
U27
U3
U5
V13
V15
V28
V29
W2
W26
W27
Y28
Y29
Y4
AB4
AB23
AB5
AB6
AD5
U4
W24
VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS_NCTF[05]
VSS_NCTF[06]
VSS_NCTF[07]
VSS_NCTF[08]
VSS_NCTF[09]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]
A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29
T27
1
+3VS
C645
@ 1U_0603_10V4Z
VCCGLAN3_3
ICH8M REV 1.0
Security Classification
2006/08/04
Issued Date
2006/10/06
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
Title
Rev
0.1
Sheet
22
of
47
+3VS
1
1
3900P_0402_50V7K
PSATA_IRX_DTX_P0
+3VS_SATA
1
R341
+3VS
1
2
R355
0_0805_5%
NOSWDJ@
+5VS
+5VS
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
2
@ 0_0805_5%
+5VS_SATA
+5VS_SATA
V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12
PD_CS#1
PLT_RST#
SWDJ@
SN74LVC125APWLE_TSSOP14
G_PCI_RST#
7,18,19,21,24,26,27 PLT_RST#
R782
10K_0402_5%
SWDJ@
U55B
SW_IDE_SDCS1#
SW_IDE_SDCS1#
+5VCD
2
G
S
Q87
2N7002_SOT23
SWDJ@
VCC= +3VALW
20
12
PD_CS#3
R785
10K_0402_5%
SW DJ@
U55D SWDJ@
SW_IDE_SDCS3#
11
SW_IDE_SDCS3#
SN74LVC125APWLE_TSSOP14
NOSWDJ@
1
2
R844
0_0402_5%
R896
10K_0402_5%
SWDJ@
2
14
P
20
C461
0.1U_0402_16V4Z
C462
1000P_0402_50V7K
C467
22U_1206_6.3V6M
+VSB
1
R783
10K_0402_5%
SWDJ@
D
2
C463
0.1U_0402_16V4Z
C472
1U_0603_10V4Z
VCC= +3VALW
ALLTO_C16616-122A3-L_NR
OE#
+3VALW
6
5
2
1
SI3456BDV-T1-E3_TSOP6
1
1
Q90
NOSWDJ@
2
0_0402_5%
1
2
R843
0_0402_5%
NOSWDJ@
+5VCD
SWDJ@
C
SIDE_RST#
2
C435
SIDE_RST#
20 PSATA_IRX_DTX_P0_C
U55ASWDJ@
GND
A+
AGND
BB+
GND
PSATA_IRX_DTX_N0
SN74LVC125APWLE_TSSOP14
1
R837
2
0_0402_5%
1
3900P_0402_50V7K
@
1
R857
2
C432
SWDJ@
R773
10K_0402_5%
1
2
3
4
5
6
7
PSATA_ITX_DRX_P0
PSATA_ITX_DRX_N0
20 PSATA_IRX_DTX_N0_C
TC7SH08FU_SSOP5
JP9
20 PSATA_ITX_DRX_P0
20 PSATA_ITX_DRX_N0
SD_IDERST#
U74
R772
10K_0402_5%
2
@ 1U_0603_10V4Z
PLT_RST#
OE#
IDERST_CD#
13
20
SWDJ@
1
C449
1
C444
PCMRST#
0.1U_0402_16V4Z
2
SWDJ@
PCMRST#
OE#
10K_0402_5%
33
@ 0.1U_0402_16V4Z
1
+5VCD
C839
1
+5VS
R771
C446
0.1U_0402_16V4Z
C445
1000P_0402_50V7K
C441
22U_1206_6.3V6M
+3VS
+3VALW
80 mil
+5VS
CD_PLAY 29,33
+5VALW
+5VCD
SWDJ@
1
Q92
DTC124EK_SC59
SWDJ@
80 mil
2
0_0805_5%
1
R838
NOSWDJ@
Q80
SI2301BDS_SOT23
G
SWDJ@
2
1
1
SWDJ@
C841
10U_0805_10V4Z
2
2
C840
10U_0805_10V4Z
JP10
ODD_LED#
SW_IDE_SDCS1#
ODD_LED#
+5VCD
PRI_CSEL
PD_DREQ 20
ODD_IOR#
PD_DACK# 20
PDIAG#
PD_A2
1
R463
2
1
C553 0.1U_0402_16V4Z
29,33 CD_PLAY
+3VALW
OCTEK_CDR-50DY1G
ME@
PD_IOR#
2006/08/04
Issued Date
2006/10/06
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
CD_PLAY
+3VS
R839
8.2K_0402_5%
NOSWDJ@
R845
SWDJ@
U70
O
ODD_IOR#
33_0402_5%
74LVC1G125GW_SOT3535
SWDJ@
Security Classification
C556
10U_0805_10V4Z
Q86
DTC124EK_SC59
SWDJ@
NOSWDJ@
1
2
R840
0_0402_5%
SN74LVC125APWLE_TSSOP14
PD_A[0..2] 20
20
SWDJ@
U55C
PD_D[0..15] 20
PD_A[0..2]
OE#
10
PD_D[0..15]
C552
1U_0603_10V4Z
SW_IDE_SDCS3#
+5VCD
Q85
DTC124EK_SC59
SWDJ@
2
100K_0402_5% +5VCD
+5VCD
PLAY_MODE
SUSP#
18,26,28,29,33,35,42,43,44 SUSP#
PLAY_MODE 30
1U_0603_10V4Z
SWDJ@
R457
470_0402_5%
C843
1
2
36
PD_DACK#
SWDJ@
1
2
240K_0402_5%
R774
+5VALW
R466
10K_0402_5%
PD_IOW#
PD _IORDY
PD_IRQ
PD_A1
PD_A0
PD_IOW#
PD_IORDY
PD_IRQ
INT_CD_R 29,31
PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15
PD_DREQ
20
20
20
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
+3VS
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
OE#
PD_D7
PD_D6
PD_D5
PD_D4
PD_D3
PD_D2
PD_D1
PD_D0
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
SWDJ@
C844
0.1U_0402_16V4Z
29,31
INT_CD_L
29
CD_AGND
SIDE_RST#
SWDJ@
C842
0.1U_0402_16V4Z
Title
Rev
0.1
Sheet
23
of
47
L23
@
FBM-L11-321611-260-LMT_1206
1
2
1
EN_WOL 2
G
Q93
2N7002_SOT23
EN_WOL
33
15 CLK_PCIE_LAN#
28
PCIE_REFCLK_N
15 CLK_PCIE_LAN
29
PCIE_REFCLK_P
15 CLKREQ_LAN#
11
CLKREQ
C624
4.7U_0805_6.3V6K
R514
+3VS
R567
+3V_LAN
R566
C631
0.1U_0402_16V4Z
21
2
@ 0_0402_5%
2
1K_0402_5%
2
1K_0402_5%
1
1
R537 1
19,28 PCI_CBE#3
VMAIN_PRSNT
54
VAUX_PRSNT
2
@ 0_0402_5%
59
ENERGY_DET
35
GPHY_PLLVDD
32
PCIE_RXD_N
31
PCIE_RXD_P
PCIE_MRX_C_LTX_N4
25
PCIE_TXD_N
PCIE_MRX_C_LTX_P4
26
PCIE_TXD_P
7,18,19,21,23,26,27 PLT_RST#
10
PERST
21,26,27 ICH_PCIE_WAKE#
12
WAKE
58
SMB_CLK
57
SMB_DATA
21
PCIE_TXP4
21
PCIE_RXN4
0.1U_0402_16V7K
21
PCIE_RXP4
0.1U_0402_16V7K
C596
C598
+PCIE_VDD
C617
0.1U_0402_16V4Z
+3V_LAN
+3V_LAN
1
R519
1
R518
2
@ 4.7K_0402_5%
2
@ 4.7K_0402_5%
+3V_LAN
1
R546
1
R551
2
@ 47K_0402_5%
2
@ 47K_0402_5%
1
R513
LAN_WP
2
0_0402_5%
GPIO2
1
R512
2
@ 0_0402_5%
C572
0.1U_0402_16V4Z
C577
0.1U_0402_16V4Z
C597
0.1U_0402_16V4Z
C585
0.1U_0402_16V4Z
C576
0.1U_0402_16V4Z
XTALO
1
200_0603_1%
XTALI
Y2
1
21.5
2
2 25MHZ_16P_XSL025000FK1H 2
LAN_TX0- 25
LAN_TX0+ 25
LAN_RX1- 25
LAN_RX1+ 25
LAN_TX2- 25
LAN_TX2+ 25
LAN_TX3- 25
LAN_TX3+ 25
+3V_LAN
23
6
15
19
56
61
+XTALVDD
+3V_LAN
VDDP
VDDP
17
68
+2.5V_LAN
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
5
13
20
34
55
60
+1.2V_LAN
BIASVDD
PCIE_PLLVDD
PCIE_VDD
PCIE_VDD
36
30
27
33
AVDD
AVDD
AVDD
38
45
52
+LAN_AVDD
AVDDL
AVDDL
AVDDL
AVDDL
39
44
46
51
+AVDDL
GPIO_2
UART_MODE
22
XTALO
16
REG_GND
24
PCIE_GND
100@
Q33
CTL12
C654 1
2 0.1U_0402_16V4Z
C656 1
2 4.7U_0805_10V4Z
MMJT9435T1G_SOT223
+1.2V_LAN
C
CTL12
CTL25
1
1.24K_0402_1%
GIGA@
XTALVDD
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
GPIO_1(SERIAL_DI)
XTALO
LAN_CLK
SI
LAN_DATA
CS#
14
18
37
XTALI
ACTIVITY# 25
REGCTL12
REGCTL25
RDAC
GPIO_0(SERIAL_DO)
21
LINKLED# 25
XTALI
0_0402_5%
2
2 @ 0_0402_5%
2 @ 0_0402_5%
65
63
64
62
SCLK(EECLK)
SI
SO(EEDATA)
CS
GND
2
R538
C581
27P_0402_50V8J
C612
27P_0402_50V8J
C639
10U_0805_10V4Z
0.1U_0402_16V4Z
C642
C641
0.1U_0402_16V4Z
LAN_TX0LAN_TX0+
LAN_RX1LAN_RX1+
LAN_TX2LAN_TX2+
LAN_TX3LAN_TX3+
2 R521 1
1 R522 1
67 R516 1
66
LINKLED
SPD100LED
SPD1000LED
TRAFFICLED
+2.5V_LAN
41
40
42
43
48
47
49
50
TRD0_N
TRD0_P
TRD1_N
TRD1_P
TRD2_N
TRD2_P
TRD3_N
TRD3_P
C613
0.1U_0402_16V4Z
LOW PWR
53
+GPHY_PLLVDD
PCIE_TXN4
+PCIE_PLLVDD
2
1
L21 FBM-L11-160808-601LMT_0603
1
2
C629
4.7U_0805_6.3V6K
+3VS
+GPHY_PLLVDD
2
1
L19 FBM-L11-160808-601LMT_0603
2
2
2
R587
C648
10U_0805_10V4Z
+3V_LAN
Q31
MBT35200MT1G_TSOP6
CTL25
+LAN_BIASVDD
1
2
5
6
C635
4.7U_0805_6.3V6K
C633
0.1U_0402_16V4Z
2
1
L16 FBM-L11-160808-601LMT_0603
2
2
100@
GIGA@
+PCIE_PLLVDD
+PCIE_VDD
B
+2.5V_LAN
69
BCM5787MKML_QFN68 1K_0402_1%
2
4
C636
4.7U_0805_6.3V6K
C619
0.1U_0402_16V4Z
C568
4.7U_0805_6.3V6K
+1.2V_LAN
+AVDDL
+1.2V_LAN
U31
0.1U_0402_16V4Z
2
1
L17 FBM-L11-160808-601LMT_0603
2
2
R587
C877
0.1U_0603_25V7K
+LAN_BIASVDD
1
C628
2
C591
0.1U_0402_16V4Z
C632
C625
C634
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
0.1U_0402_16V4Z
L22
2
1
FBM-L11-160808-601LMT_0603
+LAN_AVDD
2
C583
0.1U_0402_16V4Z
L18
2
1
FBM-L11-160808-601LMT_0603 2
C661
10U_0805_10V4Z
R902
33K_0402_5%
U31
Q34
1
21.5
6
5
2
1
SI3456BDV-T1-E3_TSOP6
+VSB
1
C589
0.1U_0402_16V4Z
+XTALVDD
+3VALW
L15
2
1
FBM-L11-160808-601LMT_0603 2
+2.5V_LAN
C611
0.1U_0402_16V4Z
C575
0.1U_0402_16V4Z
+3V_LAN
R488
4.7K_0402_5%
2
R489
4.7K_0402_5%
C567
0.1U_0402_16V4Z
U27
8
7
6
5
LAN_WP
LAN_CLK
LAN_DATA
VCC
WP
SCL
SDA
A0
A1
NC
GND
1
2
3
4
AT24C02_SO8
A
LAN_CLK
SI
CS#
4.7K_0402_5%
1
GIGA@ 4.7K_0402_5%
2
GIGA@ 4.7K_0402_5%
Security Classification
Issued Date
1
R526
2
R533
1
R534
2006/08/04
2006/10/06
Deciphered Date
Title
BCM5787MKML
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2
Rev
0.1
IGT30 LA-3571P
Sheet
1
24
of
47
RJ11+RJ45 CONN
+2.5V_LAN
JP73
11
VDD
330_0402_5%
12
1
GND
+3V_LAN
220P_0402_25V8J
C882
R523
FBM-L11-160808-601LMT_0603
R910
24
LINKLED#
MDO0+
MDO0MDO1+
U29
MDO2+
C578
C622
2 0.1U_0402_16V4Z
GIGA@
TCT
2 0.1U_0402_16V4Z
GIGA@
C587
C599
2 0.1U_0402_16V4Z
GIGA@
2 0.1U_0402_16V4Z
GIGA@
24
24
LAN_TX3LAN_TX3+
LAN_TX3LAN_TX3+
24
24
LAN_TX2LAN_TX2+
24
24
LAN_RX1LAN_RX1+
24
24
LAN_TX2LAN_TX2+
LAN_RX1LAN_RX1+
LAN_TX0LAN_TX0+
LAN_TX0LAN_TX0+
12
11
10
TD4TD4+
TCT4
MX4MX4+
MCT4
13
14
15
MDO3MDO3+
MCT0
9
8
7
TD3TD3+
TCT3
MX3MX3+
MCT3
16
17
18
MDO2MDO2+
MCT1
6
5
4
TD2TD2+
TCT2
MX2MX2+
MCT2
19
20
21
MDO1MDO1+
22
23
24
MDO0MDO0+
3
2
1
TD1TD1+
TCT1
MX1MX1+
MCT1
MDO22
75_0402_5%
1 R575
RJ45_PR
MDO1MDO3+
2
75_0402_5%
1 R569
2
75_0402_5%
1 R529
GIGA@
+3V_LAN
2
75_0402_5%
1 R525
GIGA@
220P_0402_25V8J
MDO3-
R909
C881
24
U32
2
C571
1 0.01U_0402_16V7K
100@
2
C573
1 0.01U_0402_16V7K
100@
TDTD+
CT
TCT
LAN_TX0LAN_TX0+
3
2
1
CT
RDRD+
RJ45_PR
TXTX+
CT
9
10
11
MDO1MDO1+
MCT0
CT
RXRX+
14
15
16
MCT1
MDO0MDO0+
ACTIVITY#
TX1+
MDO0-
TX1-
MDO1+
RX1+
MDO2+
TX2+
MDO2-
TX2-
MDO1-
RX1-
MDO3+
RX2+
MDO3-
RX2-
13
VDD
330_0402_5%
14
1
GND
R786 FBMA-L11-160808-181LMA15T
RJ_TIP
9
2
1
R J_RING
8
7
6
RJ45
GIGA@ 0.5u_24HST1041A-2
LAN_RX1LAN_RX1+
MDO0+
RJ45_PR
R787
FBMA-L11-160808-181LMA15T
1
2
C803
1000P_1206_2KV7K
1
1
C802
4.7U_0805_10V4Z
C804
RJ11_1
10
RJ11_2
15
16
SGND1
SGND2
RJ11
ALLTO_C100B6-110A4-L
0.1U_0402_16V4Z
NS0013_16P
100@
LAN_TX3- 2
R581
LAN_TX3+ 2
R579
1
@ 49.9_0402_1%
1
@ 49.9_0402_1%
2
1
C637 @ 0.01U_0402_16V7K
LAN_TX22
R568
LAN_TX2+ 2
R558
1
@ 49.9_0402_1%
1
@ 49.9_0402_1%
2
1
C615 @ 0.01U_0402_16V7K
MDC CONN
JP74
LAN_RX1- 2
R545 100@
LAN_RX1+ 2
R541 100@
1
49.9_0402_1%
1
49.9_0402_1%
LAN_TX0- 2
1
R531 100@ 49.9_0402_1%
LAN_TX0+ 2
1
R527 100@ 49.9_0402_1%
RJ_TIP
R J_RING
100@
2
1
C592
0.01U_0402_16V7K
100@
2
1
C579
0.01U_0402_16V7K
Security Classification
2006/08/04
Issued Date
2006/10/06
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
1
2
EDL71_MDC
Title
Rev
0.1
Sheet
25
of
47
+1.5VS_PEC
4.7U_0805_10V4Z
+1.5VS
U8
2
C378
1
0.1U_0402_16V4Z
2
C375
1
0.1U_0402_16V4Z
2
C389
+3VALW
1
0.1U_0402_16V4Z
PLT_RST#
7,18,19,21,23,24,27 PLT_RST#
33,35,42 SYSON
18,23,28,29,33,35,42,43,44 SUSP#
2 R211
+3VALW
21
CPUSB#
+1.5VS_PEC
12
14
1.5Vin
1.5Vin
1.5Vout
1.5Vout
11
13
2
4
3.3Vin
3.3Vin
3.3Vout
3.3Vout
3
5
+3VS
1
C373
0.1U_0402_16V4Z
C365
+3VS_PEC
17
AUX_IN
SYSRST#
20
SHDN#
PERST#
SUSP#
STBY#
NC
10
CPPE#
GND
100K_0402_5%
CPUSB#
CPUSB#
18
RCLKEN
19
OC#
SYSON
+3V_PEC
+3V_PEC
15
AUX_OUT
PERST#
C384
0.1U_0402_16V4Z
16
C392
4.7U_0805_10V4Z
7
+3VS_PEC
4.7U_0805_10V4Z
R5538_QFN20
C371
0.1U_0402_16V4Z
1
C361
JP53
21
21
USB20_N5
USB20_P5
USB20_N5
USB20_P5
0_0402_5%
1
2
1
2
R259
R266
USB5USB5+
CPUSB#
0_0402_5%
ICH_SMBCLK
ICH_SMBDATA
15,21,27 ICH_SMBCLK
15,21,27 ICH_SMBDATA
21,24,27 ICH_PCIE_WAKE#
R315 1
0_0402_5%
+1.5VS_PEC
+1.5VS_PEC
PCIE_PME#_R
+3V_PEC
PERST#
+3VS_PEC
CLKREQ_NC1#
CPUSB#
CLK_PCIE_NC1#
CLK_PCIE_NC1
15 CLKREQ_NC1#
21
CPUSB#
15 CLK_PCIE_NC1#
15 CLK_PCIE_NC1
21
21
21
21
PCIE_RXN3
PCIE_RXP3
PCIE_RXN3
PCIE_RXP3
PCIE_TXN3
PCIE_TXP3
PCIE_TXN3
PCIE_TXP3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
GND
USB_DUSB_D+
CPUSB#
RSV
RSV
SMB_CLK
SMB_DATA
+1.5V
+1.5V
WAKE#
+3.3VAUX
PERST#
+3.3V
+3.3V
CLKREQ#
CPPE#
REFCLKREFCLK+
GND
PERn0
PERp0
GND
PETn0
PETp0
GND
GND
GND
FOX_1CH4110C
Security Classification
2006/08/04
Issued Date
Deciphered Date
2006/10/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
Rev
0.1
Sheet
E
26
of
47
@ 0_0402_5%
@ 0_0402_5%
15 CLKREQ_MCARD#
CLK_PCIE_MCARD#
CLK_PCIE_MCARD
21
21
PCIE_RXN2
PCIE_RXP2
21
21
PCIE_TXN2
PCIE_TXP2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
GND1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
GND2
54
+3VS
2
PLT_RST#
2
R595 2
R598
ICH_SMBCLK
ICH_SMBDATA
+1.5VS
1
RF_OFF# 33
PLT_RST# 7,18,19,21,23,24,26
1
+3VALW
1 0_0402_5% +3VS
@ 0_0402_5%
JP55
BT_AVTIVE
WLAN_AVTIVE
R555 2
R561 2
1@ 0_0402_5%
1@ 0_0402_5%
CLKREQ_MCARD1#
CLK_PCIE_MCARD1#
CLK_PCIE_MCARD1
15 CLK_PCIE_MCARD1#
15 CLK_PCIE_MCARD1
ICH_SMBCLK 15,21,26
ICH_SMBDATA 15,21,26
21
21
PCIE_RXN1
PCIE_RXP1
21
21
PCIE_TXN1
PCIE_TXP1
PCIE_RXN1
PCIE_RXP1
PCIE_TXN1
PCIE_TXP1
USB20_N1 21
USB20_P1 21
R899
2
1
0_0603_5%
+3VS
WIRELESS_LED# 36
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
GND1
FOX_AS0B226-S56N-7F
+5VS
1
3
5
7
9
11
2
4
6
8
10
12
2
4
6
8
10
12
1 2
+3V_SB
3G_LED# 36
RF_OFF2
33
Q13
DTC124EK_SC59
BT_OFF#
+3VS
HDA_BITCLK_MDC 20
Q8
C337
36
BTONLED
BTONLED
JP56
C588
@ 10P_0402_50V8J
21
21
Q11
DTC124EK_SC59
USB20_N7
USB20_P7
1
2
3
4
5
6
7
8
9
10
USB20_N7
USB20_P7
BTON_LED2
BT_AVTIVE
WLAN_AVTIVE
R151
10K_0402_5%
Security Classification
2006/08/04
Issued Date
2006/10/06
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
1
2
3
4
5
6
7
8
GND1
GND2
4
MOLEX_53780-0870
ME@
13
14
15
16
17
18
19
20
13
14
15
16
17
18
19
20
ACES_88012-1207
ME@
+3VS_BT2
1
0.1U_0402_16V4Z
R535
@ 10_0402_5%
ICH_SMBCLK 15,21,26
ICH_SMBDATA 15,21,26
3
DAP202U_SOT323
USB20_N9 21
USB20_P9 21
3
AO3413_SOT23
1
+1.5VS
1U_0805_25V4Z
2
KILL_MDC#
ICH_SMBCLK
ICH_SMBDATA
D21
20
RF_OFF# 33
PLT_RST# 7,18,19,21,23,24,26
+3VALW
PLT_RST#
R497 1
R498 2
1
3
5
7
9
11
AZ _SYNC
2 AZ_SDIN3
133_0402_5%
@ 0_0402_5%
JP17
20 HDA_SYNC_MDC
20 HDA_SDIN1
20 HDA_RST_MDC#
54
R171
10K_0402_1%
C586
1
2
20 HDA_SDOUT_MDC
GND2
+3VS
BT MODULE CONN.
MDC CONN.
R496
10K_0402_1%
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
FOX_AS0B226-S56N-7F
+3VALW
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
15 CLK_PCIE_MCARD#
15 CLK_PCIE_MCARD
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
0.1U_0402_16V4Z
1
1
C683
R635 2
R636 2
0.1U_0402_16V4Z
C684
BT_AVTIVE
WLAN_AVTIVE
0.1U_0402_16V4Z
JP54
21,24,26 ICH_PCIE_WAKE#
C682
0.1U_0402_16V4Z
C669
Title
Rev
0.1
Sheet
E
27
of
47
+3VS
69
66
2
10K_0402_5%
2
@ 0_0402_5%
111
107
103
102
99
97
IEEE1394_TPBIAS0
IEEE1394_TPAP0
IEEE1394_TPAN0
TPBP0
TPBN0
105
104
IEEE1394_TPBP0
IEEE1394_TPBN0
MDIO00
MDIO01
MDIO02
MDIO03
MDIO04
MDIO05
MDIO06
MDIO07
MDIO08
MDIO09
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
MDIO15
MDIO16
MDIO17
MDIO18
MDIO19
80
79
78
77
76
75
74
73
88
84
82
81
93
90
91
89
92
87
85
83
SDCD#_XDCD0#
MSCD#_XDCD1
XD_CE#
SDWP#_XDRB#
SDPWR0_MSPWR_XDPWR
XDWP#
3IN1_LED#
TP_MSEXTCK
SDCMD_MSBS
SDCLK_MSCLK
SDDATA0_MSDATA0
SDDATA1_MSDATA1
SDDATA2_MSDATA2
SDDATA3_MSDATA3
XDD4
XDD5
XDD6
XDD7
XDCLE
XDALE
MSEN
XDEN
58
55
MSEN
XDEN
XI
XO
94
95
R5C832XI
R5C832XO
FIL0
REXT
VREF
INTA#
INTB#
UDIO0/SERIRQ#
UDIO1
UDIO2
UDIO3
UDIO4
UDIO5
HWSPND#
TEST
AGND
AGND
AGND
AGND
AGND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC
C469
10U_0805_4VAM
C448
10U_0805_4VAM
C452
0.01U_0402_16V7K
C455
0.1U_0402_16V4Z
C451
0.01U_0402_16V7K
C447
0.47U_0603_16V4Z
C492
0.47U_0603_16V4Z
C487
0.01U_0402_16V7K
C477
0.01U_0402_16V7K
C657
10U_0805_4VAM
+3V_PHY
SDCD#_XDCD0# 37
MSCD#_XDCD1 37
XD_CE# 37
SDWP#_XDRB# 37
C712
1000P_0402_50V7K
C713
1000P_0402_50V7K
BLM21A601SPT_0805
C711
0.1U_0402_16V4Z
2
C699
0.1U_0402_16V4Z
C714
22U_0805_6.3V6M
+3VS
XDWP# 37
3IN1_LED#
SDCMD_MSBS 37
SDCLK_MSCLK 37
SDDATA0_MSDATA0
SDDATA1_MSDATA1
SDDATA2_MSDATA2
SDDATA3_MSDATA3
XDD4
37
XDD5
37
XDD6
37
XDD7
37
XDCLE 37
XDALE 37
SDPWR0
MDIO05
SDPWR1
MDIO06
MSWR
SDLED#
MMCLED#
MSLED#
MDIO08
SDCCMD
MMCCMD
MSBS
MDIO09
SDCCLK
MMCCLK
MSCCLK
XDRE#
MDIO10
SDCDAT0
MMCDAT
MSCDAT0
XDCDAT0
MDIO11
SDCDAT1
MSCDAT1
XDCDAT1
MDIO12
SDCDAT2
MSCDAT2
XDCDAT2
MDIO13
SDCDAT3
MSCDAT3
XDCDAT3
MSEXTCK
XDCDAT4
MDIO15
XDCDAT5
MDIO16
XDCDAT6
MDIO17
XDCDAT7
MDIO18
XDCLE
MDIO19
XDALE
UDIO4
MSEN
XDEN
Pull-up
Pull-up
Pull-up
Pull-up
C485
1
2
15P_0603_50V8J
MSEN
U DIO3
U DIO4
U DIO5
R343
R347
R342
R344
XDEN
R345 1
X2
1
1
1
1
2
2
2
2
2 10K_0402_5%
R5C832XO
R637 2
1 0_0402_5%
@ Q42
SD_MSDATA1
3 2N7002_SOT23
R629 2
1 0_0402_5%
15P_0603_50V8J
SDDATA2_MSDATA2
2
1
IEEE1394_TPBN0
IEEE1394_TPBP0
IEEE1394_TPAN0
IEEE1394_TPAP0
1
2
3
4
TPBTPB+
TPATPA+
GND
GND
GND
GND
2
G
1
XDCD#
@ Q36
2N7002_SOT23
MSCD#_XDCD1
SDCD#_XDCD0#
5
6
7
8
+VCC_4IN1_XD
2
G
@ Q41
2N7002_SOT23
XDCD#
XDCD#
37
A
DAN202U_SC70
Security Classification
Issued Date
2006/08/04
Deciphered Date
2006/10/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
IEEE1394_TPBIAS0
@ Q38
2N7002_SOT23
SUYIN_020115FB004S512ZL
ME@
C499
0.33U_0603_16V4Z
C494
0.01U_0402_16V7K
2
1
C466
1U_0603_10V6K
R374
56.2_0402_1%
2
1
2
G
C671
0.1U_0402_16V4Z
1
2
R619
150K_0402_5%
SD_MSDATA2 37
D24
CBS_GRST#
R366
56.2_0402_1%
1 @
R367
56.2_0402_1%
1
2
R353
100K_0402_5%
2
A
GND
RT9701CB_SOT25
2
@ 10K_0402_5%
2
@ 10K_0402_5%
SDCD#_XDCD0#
JP13
R375
56.2_0402_1%
C495
R365
4.7P_0402_50V8C10_0402_5%
Z3008
+3VS
+VCC_4IN1
C668
10U_1206_6.3V6M
CLK_PCI_1394
+VCC_4IN1
1
5
C664
1U_0603_10V4Z
C665
0.1U_0402_16V4Z
1
2
R381
5.1K_0402_1%
C496
270P_0402_50V7K
VIN
VOUT
VIN/CE VOUT
1
R627
1
R634
40mil
SD_MSDATA1 37
@ Q39
32N7002_SOT23 SD_MSDATA2
1
2
R631
0_0805_5%
U38
10K_0402_5%
10K_0402_5%
10K_0402_5%
100K_0402_5%
+VCC_4IN1
3
4
Enable
SD,XD,MS,MMC Card
24.576MHz_16P_1BG24576CKIA
C488
1
2
+3VS
Function
R5C832XI
SDDATA1_MSDATA1
SDPWR0_MSPWR_XDPWR
UDIO3
+5VS
XDWE#
MDIO14
R5C832_TQFP128~D
XDLED#
+3VS
SIRQ
21,32,33
PAD
T28
PAD
T29
4
13
22
28
54
62
63
68
118
122
XDWP#
0.01U_0402_16V7K
SIRQ
TP_UDIO1
TP_UDIO2
U DIO3
U DIO4
U DIO5
XDPWR
MMCPWR
37
37
37
37
XDR/B#
MDIO04
MDIO07
L25
96
101
100
72
60
56
65
59
57
1
R349
18,23,26,29,33,35,42,43,44 SUSP#
115
116
113
109
108
1
R351
+3VS
2 0_0402_5%
R5_PME#
PCICLK
PCIRST#
GBRST#
CLKRUN#
PME#
R658 1
33
R5_PME#
19 PCI_PIRQG#
19 PCI_PIRQH#
121
119
71
117
70
CBS_GRST#
2@ 10K_0402_5%
REQ#
GNT#
+3VS
1
+3V_PHY
TPAP0
TPAN0
XDCD1#
2
G
R659 1
21,33 PCI_CLKRUN#
124
123
TPBIAS0
MSCD#
15 CLK_PCI_1394
19,32,33 PCI_RST#
PCI_REQ0#
PCI_GNT0#
SDWP#
PCI_REQ0#
PCI_GNT0#
98
106
110
112
XD Card
PIN Name
XDCD0#
XDCE#
MDIO03
19
19
67
86
MS Card
PIN Name
MDIO02
16
34
64
114
120
VCC_3V
MMC Card
PIN Name
MMCCD#
MDIO01
+3VS
PCI_PERR#
PCI_SERR#
PAR
FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
IDSEL
PERR#
SERR#
19
19
33
23
25
24
29
26
8
30
31
C/BE3#
C/BE2#
C/BE1#
C/BE0#
61
VCC_MD3V
AVCC_PHY3V
AVCC_PHY3V
AVCC_PHY3V
AVCC_PHY3V
R656
10K_0603_1%
PCI_PAR
PCI_FRAME#
PCI_TRDY#
PCI_IRDY#
PCI_STOP#
PCI_DEVSEL#
VCC_ROUT
VCC_ROUT
VCC_ROUT
VCC_ROUT
VCC_ROUT
1
2
R363 100_0402_5%
PCI_PAR
PCI_FRAME#
PCI_TRDY#
PCI_IR DY#
PCI_STOP#
PCI_DEVSEL#
CBS_IDSEL
PCI_PERR#
PCI_SERR#
VCC_RIN
10
20
27
32
41
128
PCI_AD22
19
19
19
19
19
19
PCI_CBE#3
PCI_CBE#2
PCI_CBE#1
PCI_CBE#0
7
21
35
45
R5C832
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
C493
0.01U_0402_16V7K
PCI_CBE#3
PCI_CBE#2
PCI_CBE#1
PCI_CBE#0
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
C481
0.01U_0402_16V7K
125
126
127
1
2
3
5
6
9
11
12
14
15
17
18
19
36
37
38
39
40
42
43
44
46
47
48
49
50
51
52
53
C482
0.01U_0402_16V7K
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
SD Card
PIN Name
SDCD#
MDIO
PIN Name
MDIO00
U18
19 PCI_AD[0..31]
19,24
19
19
19
2
G
Title
R ev
0.1
Sheet
28
of
47
+VDDA
AC97 Codec
28.7K for Module Design (VDDA = 4.702)
+5VS
R642
2MONO_IN1
20K_0402_5%
1
2
Q26
2SC2411K_SC59
2
B
E
560_0402_5%
AMP_LEFT
L26
CHB1608U301_0603
1
2
0.1U_0402_16V4Z
1
AMP_RIGHT
30
HP_L
30
HP_R
C691
30,36 INT_MIC_R
C693
23,31 INT_CD_L
20K_0402_5% CD_R_L
20K_0402_5%
20K_0402_5%
20K_0402_5% CD_R_R
1
1
1
1
CD_GNA
POWER ON PATH
30
14
SWDJ@
+5VALW
C811
0.1U_0402_16V4Z
2
1
SWDJ@
U71C
2
2
2
2
R797
1M_0402_5%
SWDJ@
AMP_LEFT
B
5
1
2
C479
1U_0603_10V4Z
1
2
C484
1U_0603_10V4Z
2
2.2U_0603_6.3V6K
2
2.2U_0603_6.3V6K
1
1
14
MIC1_L
22
MIC1_R
13
SENSE A
R641 1
R639 1
2 0_0402_5%
2 0_0402_5%
PC_BEEP
11
RESET#
EAPD
1
L24
R800 1
10_0402_5%
SPDIF
2
@ CHB1608U301_0603
2
2
9
GPIO2
R644 1
250_SDIN
EC_IDERST
CD_AGND
CD_AGND
R848 2
1
10K_0402_5%
CD_GNA
23
+5VALW
NC
NC
47
SPDIFI/EAPD
48
SPDIFO
4
7
DVSS1
DVSS2
R657 1
2 0_0402_5%
R383 1
2 0_0402_5%
R373 1
2 0_0402_5%
MIC2_VREFO
30
MIC1_VREFO_L
28
VREF
27
MIC1_VREFO_R
32
LINE2_VREFO
DCVOL
SENSE B
GPIO0
GPIO1
31
33
34
43
44
LFILT
AVSS1
AVSS2
40
26
42
10mil
10mil
10mil
R379 1
HDA_SDIN0 20
C458 1
2
@ 22_0402_5%
2
@ 22P_0402_50V8J
+MIC1_VREFO_L
2
C719
1
10U_0805_10V4Z
+AUD_VREF
2 @ 10K_0402_5% +VDDA
R382 2
1
1U_0603_10V4Z
39.2K_0402_1%
2 861@
C813 1
2 861@
JACK_PLUG_CODEC 37
LFE_OUT 31
1U_0603_10V4Z
R364
20K_0402_1%
+MIC2_VREFO
2
1
3
HDA_BITCLK_AUDIO 20
HDA_SDIN0
10mil
+MIC1_VREFO_L
@
C728
@ C733
0.1U_0402_16V4Z
SUSP#
18,23,26,28,33,35,42,43,44
SWDJ@
B
2006/10/06
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
10mil
2G NDA
2
1U_0603_10V4Z
Issued Date
+AUD_VREF
@
C725
@ C511
0.1U_0402_16V4Z
10mil
2G NDA
2
1U_0603_10V4Z
@
C498
0.1U_0402_16V4Z
GNDA
Security Classification
EC_IDERST
2 @
0_0402_5%
HDA_BITCLK_AUDIO
+MIC2_VREFO
C812 1
G NDA
GND
SUSP#
0_0402_5%
2
22_0402_5%
2
33_0402_5%
R643 1
SDATA_OUT
R803
10K_0402_5%
SWDJ@
LINE_OUTR
LFE_OUT 31
1U_0603_10V4Z
29
@ C732
1U_0603_10V4Z
1
R805
LINE_OUTL
LINE1_VREFO
10K_0402_5%
Q81 SWDJ@
2N7002_SOT23
2
1 R804
G
R354 1
ALC262-GR_LQFP48-N
SYNC
45
46
0_0402_5%
R847
BIT_CLK
SDATA_IN
GPIO3
LINE_OUTL
2
1U_0603_10V4Z
LINE_OUTR
2
1U_0603_10V4Z
41
6
CD_L
12
10
EAPD
LINE1_R
21
2
@ 1000P_0402_50V7K
2
@ 1000P_0402_50V7K
DVDD2
24
C_MIC
2
2.2U_0603_6.3V6K
2
2.2U_0603_6.3V6K
2 20K_0402_1%
DVDD1
39
HP_OUT_R
1
C721
1
C722
C807
NOSWDJ@
EC_IDERST
EC_IDERST1
38
HP_OUT_L
LINE1_L
CD_GND
SN74HCT4066PW_TSSOP14
1 R802
2
33
37
MIC2_R
23
19
G
7
R801
1M_0402_5%
SWDJ@
AMP_RIGHT
17
18
1M_0402_5%
37
CD_GNDA
P
8
LINE_OUTR
1
1
+5VAMP
SWDJ@
2
MONO_O
1U_0603_10V4Z
20 HDA_SDOUT_AUDIO
33
MIC2_L
20 HDA_SYNC_AUDIO
SWDJ@
U71D
16
CD_GNA C810 1
+5VALW
R799
C_LINE_OUTR
CD_R
20 HDA_RST_AUDIO#
NOSWDJ@
C_LINE_OUTL
36
20
EAPD
0_0402_5%
35
LINE_OUT_R
SN74HCT4066PW_TSSOP14
1 R798
LINE_OUT_L
LINE2_R
CD_RC_R
MIC
1
C698
1
C715
1
C726
LINE2_L
CD_RC_L
R647
C_LINE_OUTL
C_LINE_OUTR
15
1U_0402_6.3V4Z
37 JACK_PLUG_MIC
C686
0.1U_0402_16V4Z
14
1U_0402_6.3V4Z
C808 1
MONO_IN
1M_0402_5%
SWDJ@
U41
P
4
2
0.1U_0402_16V4Z
LINE_OUTL
1
1
C697
C809 1
MIC
C688
10U_0805_10V4Z
2
2
0.1U_0402_16V4Z
AVDD2
30,36 INT_MIC_L
R792
R793
R794
R795
C687
C727
AMP_RIGHT 30
SN74HCT4066PW_TSSOP14
C717
AVDD1
14
P
12
10
B
C
1
R791
1M_0402_5%
SWDJ@
25
SN74HCT4066PW_TSSOP14
U71B SWDJ@
+3VS
AMP_LEFT 30
11
R638
CHB1608U301_0603
1
2
14
13
23,31 INT_CD_R
+5VAMP
ALC861D
EC_IDERST1
ALC262
Q96
2N7002_SOT23
SWDJ@
+AVDD_AC97
+5VALW
R796
100_0402_5%
2
G
SWDJ@
U71A
+VDDA
SWDJ@
C806
1U_0603_10V4Z
INT_CD_R1
2
EC_IDERST1
R900
C718
10U_0805_10V4Z
31
R654
51K_0603_1%
SWDJ@
P
1
R789
1M_0402_5%
SWDJ@
SWDJ@
C692
10U_0805_10V4Z
+VDDC
1
R788
1M_0402_5%
R790
1M_0402_5%
+5VALW
R655
150K_0603_1%
1
C716
SWDJ@
C805
1U_0603_10V4Z
INT_CD_L1
2
+5VAMP
RB751V_SOD323
SWDJ
SWDJ@
GND
23,33 CD_PLAY
+5VAMP
NOSWDJ@
+5VS
R905
10K_0402_1%
Q43
2N7002_SOT23
D11
CNOISE
+VDDA
4.85V
R356
@ 10K_0402_5%
SD
0.1U_0402_16V4Z
1
1
EAPD 2
G
1U_0603_10V4Z
1 1
ERROR
+5VS
680P_0402_50V7K LINE_OUTR
SB_SPKR
R348
SENSE or ADJ
40mil
680P_0402_50V7K LINE_OUTL
C695
R645
10K_0402_1%
C459
DELAY
2
C694
VOUT
SI9182DH-AD_MSOP8
560_0402_5%
1U_0603_10V4Z
21
R352
1 1
C724
10U_1206_10V4Z
VIN
R648
10K_0402_1%
C453
@ 0.1U_0402_16V4Z
2
R646 20K_0402_5%
10U_0805_10V4Z
C454
2
BEEP#
33
C734
2 470P_0402_50V8J
C689 1U_0603_10V4Z
2
1 MONO_IN
R357
10K_0402_1%
C685
1
+VDDA
1U_0603_10V4Z
U42
60mil
L31 1
2
KC FBM-L11-201209-221LMAT_0805
L29 1
2
KC FBM-L11-201209-221LMAT_0805
1C473
R358
10K_0402_1%
Title
Re v
0.1
Sheet
E
29
of
47
+5VAMP
2
DOS mode
R368
10K_0402_5%
2
0_0402_5%
1
R369
1.5K_0402_1%
NOSWDJ@
C474
C483
4.7U_0805_10V4Z
10
15
VOL_AMP
29
29
AMP_LEFT
R378 1
AMP_RIGHT
VOLMAX
2
0_0402_5%
BTL#
1
R377
NOSWDJ@
1
2
R359
0_0402_5%
R376 1
2 10K_0402_5%
L IN
2 10K_0402_5%
RIN
R914
10K_0402_5%
SWDJ@
JACKCTL
LINRIN-
BYPASS
10K_0402_5%
0_0402_5%
EC_MUTE#
SPKL-
L7
2 0_0603_5% SPKL-O
16
SPKR-
L8
2 0_0603_5% SPKR-O
LOUT+
11
SPKL+
L11
2 0_0603_5% SPKL+O
SPKL+O
31
ROUT+
14
SPKR+
L9
2 0_0603_5% SPKR+O
SPKR+O
31
GND
GND
5
12
SE/BTL#
6
3
2
2
LOUTVOLMAX
13
R371 1
R372 1
ROUT-
VOLUME
MUTE_AMP
AMP_OFF#
1
2
MUTE
SHUTDOWN#
EC_MUTE
12sec
EC_MUTE
12sec
JP20
SPKL+O
SPKL-O
SPKR+O
SPKR-O
APA2068KAI-TRL_SOP16
C491
4.7U_0805_10V4Z
C247
C246
C245
1
2
3
4
5
6
C244
1
2
3
4
G1
G1
E&T_3802-E04N-01R
BTL#
BTL#
@ 47P_0402_50V8J @ 47P_0402_50V8J
@ 47P_0402_50V8J
2
2
2
2
@ 47P_0402_50V8J
31
2
G
3
33
+5VAMP
VDD
VDD
RST
R362
10K_0402_5%
@
U19
Driver initial
ACPI
RST
DOS mode
+3VALW
1
R868
DOS mode
W=40mil
0.1U_0402_16V4Z
NOSWDJ@
1 1
VOLUME
+5VAMP
SWDJ@
31,33
Window mode
Q99
2N7002_SOT23
SWDJ@
+MIC1_VREFO_L
INT MIC
+MIC2_VREFO
+MIC2_VREFO
EXT MIC
INT MIC
+5VAMP
+5VALW
1
29
C865
10U_0805_10V4Z
FBM-11-160808-601-T_0603
EXT_MIC 37
INT_MIC_L 29,36
INT_MIC_R 29,36
2
C866
2
1
10U_0805_10V4Z
PLAY_MODE
MIC
L12
1
R854
3K_0402_5%
R667
3K_0402_5%
6
5
2
1
R664
3K_0402_5%
2
Q89
SI3445DV_TSOP6
C867
0.1U_0402_16V4Z
C497
47P_0402_50V8J
2
GNDA
C723
47P_0402_50V8J
2
GNDA
C856
47P_0402_50V8J
2
GNDA
PLAY_MODE 23
31 HP_L_SWDJ
3
+3VS
1
R361
0_0603_5%
HEADPHONE
HP_OUTL
1
C486
D39
2
RB751V_SOD323
HP_CR+
SHDNR#
18
SHDNL#
HP_OUTR
OUTR
11
HP_OUTR
OUTL
HP_OUTL
R666
1K_0402_5%
2
C1N
SGND
C1P
C696
1U_0603_10V4Z
PGND
1
1
INL
17
INR
13
SVss
15
HP_L
PVss
HP_R
29
29
NC-4
NC-6
NC-8
NC-12
12
NC-16
16
NC-20
20
L27
R665
1
2
FBMA-L11-160808-121LMT_0603
1
C731
47P_0402_50V8J
1K_0402_5%
PR
1
PR
37
C729
47P_0402_50V8J
Security Classification
C478
1U_0603_10V4Z
37
MAX4411ETP+T_TQFN20~N
PL
JACK_PLUG 33,37
47_0402_5%
2
10
19
14
SWDJ@
1
2
FBMA-L11-160808-121LMT_0603
PL
R662
1
L28
EC_MUTE#
U17
SVDD
31,33 EC_MUTE#
HP_CL+
JACK_PLUG
2 NOSWDJ@
0_0402_5%
PVDD
R652 1
R663 47_0402_5%
1
2
2
1U_0603_10V4Z
R653
10K_0402_5%
SWDJ@
31 HP_R_SWDJ
+3VS
2006/08/04
Issued Date
2006/10/06
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
Title
Rev
0.1
Sheet
E
30
of
47
SWDJ
LFE_OUT R808 1
LFE_OUT
1U_0603_10V4Z
+5VAMP
C821 1
8
5
560_0402_5%
560_0402_5%
C820
R869
10K_0402_5%
20mil
+5VAMP
0_0402_5% SWDJ@
1
2
R873
R861
1M_0402_5%
SWDJ@
2 @ 0_0402_5%
14
SWDJ@
U75D
0_0402_5% SWDJ@
1
2
R881
SPKR+O
B
C
6
29
R872
10K_0402_5%
@
1 1
U76
30
VOL_AMP
BTL#
VOLMAX
2
0_0402_5%
BTL#
1
R877
VDD
VDD
MUTE
SHUTDOWN#
1
2
NOSWDJ@
1
2
R878
0_0402_5%
MIX_OUT
R879 1
@
2 10K_0402_5%
W IN1
MIX_OUT
2 0_0402_5%
W IN2
R880 1
VOLUME
VOLMAX
13
6
3
4
SWDJ@
C871
1U_0603_10V4Z
1
2
HP_R_SWDJ 30
LOUT-
ROUT-
16
LOUT+
11
SE/BTL#
ROUT+
14
GND
GND
5
12
LINRINBYPASS
MUTE_AMP_1 R874 1
10K_0402_5%
2
AMP_OFF#1 1
2 EC_MUTE#
EC_MUTE# 30,33
R875
0_0402_5%
WOOF-
L60
2 0_0603_5% W OOFER-
WOFF+
L61
2 0_0603_5% WOOFER+
APA2068KAI-TRL_SOP16
C872
4.7U_0805_10V4Z
SN74HCT4066PW_TSSOP14
2 @ 0_0402_5%
1 R865
R882
0_0402_5%
SubWoofer Conn.
30mil
W OOFERWOOFER+
EC_IDERST1
EC_IDERST1
C869
4.7U_0805_10V4Z
R864
1M_0402_5%
SWDJ@
C868
SWDJ@
1M_0402_5%
+5VAMP
R876
0_0402_5%
+5VALW
L51
L50
1
1
2
2
FBMA-L11-160808-700LMT_0603
WOWO+
FBMA-L11-160808-700LMT_0603
JP75
1
2
1
2
3
4
GND
GND
MOLEX_53780-0270
ME@
+USB_VCCA
1000P_0402_50V7K
1
USB Port
C565
150U_D_6.3VM
+
2
C266
C275
0.1U_0402_16V4Z
+5VALW
ME@
SUYIN_020173MR004S558ZL
+USB_VCCA
U4
GND
IN
IN
EN#
OUT
OUT
OUT
FLG
8
7
6
5
21
21
USB_OC#0 21
D1
@ PSOT24C_SOT23
G545C1P1U_SO8
1
1
2
3
4
5
6
7
8
USB20_N0
USB20_P0
2
1
2
3
USB_ON 4
C338 0.1U_0402_16V4Z
2
1
33,37 USB_ON
C336
@ 1000P_0402_50V7K
For EMI
30
SWDJ@
C864
1U_0603_10V4Z
1
2
R863
+3VALW
10
15
1 R862
R871
1.5K_0402_1%
NOSWDJ@
C870 SWDJ@
1U_0603_10V4Z
1
2
HP_L_SWDJ 30
SN74HCT4066PW_TSSOP14
SWDJ@
2
0_0402_5%
SWDJ@
14
1M_0402_5%
R860 2
+5VAMP
1
R870
VOLUME
W=40mil
0.1U_0402_16V4Z
POWER ON PATH
SPKL+O
0.22U_0603_10V7K
+5VAMP
R811
100K_0402_5%
30,33
30
MIX_OUT
U72B
TLV2462CDR_SO8
14
12
1U_0603_10V4Z
SN74HCT4066PW_TSSOP14
SWDJ@
+5VALW
C862
0.1U_0402_16V4Z
SWDJ@
2
1
U75C
2
2
NOSWDJ@
SWDJ@
C863
1U_0603_10V4Z
1
2
10mil
0.1U_0603_50V4Z
Fc(LPF)= 1.5KHz
C822
10
B
C
C819
O
+AUD_VREF_LF
U75B SWDJ@
P
11
+5VAMP
R810
100K_0402_5%
+5VALW
100P_0402_50V8J
Gain = 3.1dB
EC_IDERST1
2 0.1U_0603_50V4Z
R807
R809
1 100K_0402_5%
100K_0402_5%
2 C818
R806
LFE_OUT 29
C816 1
U72A
TLV2462CDR_SO8
2
0.1U_0402_16V4Z
1
C817
29
SN74HCT4066PW_TSSOP14
13
R859
1M_0402_5%
SWDJ@
SWDJ@
SWDJ@
LFE_OUT
2
1U_0603_10V4Z
2
A
G
R858
1M_0402_5%
SWDJ@
U75A
0_0402_5%
B 2 R9171
C815
1
+5VAMP
1U_0603_10V4Z
+AUD_VREF_LF
2
23,29 INT_CD_R
14
23,29 INT_CD_L
+AUD_VREF_LF +5VAMP
C814
1
+5VALW
SWDJ@
C860
1U_0603_10V4Z
1
2
C861
1U_0603_10V4Z SWDJ@
1
2
1
2
3
4
GND
GND
GND
GND
JP21
Security Classification
Issued Date
2006/08/04
Deciphered Date
2006/10/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Rev
0.1
Sheet
31
of
47
SW2
1
4
6
5
Power BTN
SMT1-05_4P
D
SW1
+3VALW
3
1
2 100P_0402_50V8J
@ C171 1
2 100P_0402_50V8J
KSI4
@ C172 1
2 100P_0402_50V8J
KSI5
@ C183 1
2 100P_0402_50V8J
KSO0
@ C184 1
2 100P_0402_50V8J
KSI2
@ C185 1
2 100P_0402_50V8J
JP26
KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
KSI3
@ C176 1
2 100P_0402_50V8J
KSO5
@ C177 1
2 100P_0402_50V8J
KSO1
@ C178 1
2 100P_0402_50V8J
KSI0
@ C187 1
2 100P_0402_50V8J
KSO2
@ C188 1
2 100P_0402_50V8J
KSO4
@ C189 1
2 100P_0402_50V8J
KSO7
@ C173 1
2 100P_0402_50V8J
KSO8
@ C174 1
2 100P_0402_50V8J
KSO6
@ C175 1
2 100P_0402_50V8J
KSO3
@ C191 1
2 100P_0402_50V8J
KSO12
@ C192 1
2 100P_0402_50V8J
KSO13
@ C193 1
2 100P_0402_50V8J
KSO14
@ C194 1
2 100P_0402_50V8J
KSO11
@ C195 1
2 100P_0402_50V8J
KSO10
@ C196 1
2 100P_0402_50V8J
KSO15
@ C197 1
2 100P_0402_50V8J
D7
36 ON/OFFBTN#
1
+3VALW
ON/OFF# 33
51ON#
51ON#
36,39
DAN202U_SC70
Q18
R256
4.7K_0402_5%
33,40
EC_ON
EC_ON
1
R261
DTC124EK_SC59
D6
RLZ20A_LL34
2 C379
1000P_0402_50V7K
2
2
33K_0402_5%
ACES_85202-2405
ON/OFF
ON/OFFBTN#
@ C169 1
KSO9
KSI6
R255
100K_0402_5%
2
2 100P_0402_50V8J
@ C182 1
4
SMT1-05_4P
KSI7
2 100P_0402_50V8J
KSO[0..15] 33
@ C186 1
KSO[0..15]
KSI1
33,36
KSI[0..7]
6
5
KSI[0..7]
2
G
Q19
2N7002_SOT23
Kill Switch
+3VS
SW3
1
R816
33
KILL_SW#
2
10K_0402_5%
KILL_SW#
1BS003-1211L_3P
B
+3VALW
JP58
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
R888
100_0603_5%
NOTV@
+5VS
+3VS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
R819
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_DRQ#0
PCI_RST#
SIRQ
CLK_14M_SIO 15
LPC_FRAME# 20,33
LPC_DRQ#0 20
PCI_RST# 19,28,33
LPC_AD[0..3]
33
RCIRRX
RCIRRX
LPC_AD[0..3] 20,33
TV@
2
33_0402_5%
C827
22P_0402_50V8J
R622
10K_0402_5%
2
1
1
TV@
2
+5VALW
CLK_PCI_DB 15
SIRQ
21,28,33
TV@
1
R817
1
R818
@
+5VS
IR1
2
100_0603_5%
2
100_0603_5%
1
4.7U_0805_10V4Z
ACES_85201-2005
ME@
C826
Vout
VCC
3
4
GND
GND
IRM-V538/TR1_3P
TV@
CIR
Security Classification
2006/08/04
Issued Date
2006/10/06
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
Title
Rev
0.1
Sheet
32
of
47
+3VALW
L5
1
2
+EC_AVCC
FBM-11-160808-601-T_0603 2
1
C397
C398
0.1U_0402_16V4Z
1000P_0402_50V7K
1 ECAGND 2
1
2
ECAGND
L6 FBM-11-160808-601-T_0603
+3VALW
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
1
2
R312@
C422
@ 22P_0402_50V8J
1
EC_RST#
10_0402_5%
1
+3VALW
R224
2
47K_0402_5%
19,28,32 PCI_RST#
21
EC_SCI#
1
21,28 PCI_CLKRUN#
R223
C377
EC_RST#
EC_SCI#
2
@ 0_0402_5%
36 MODE_LED#
2
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
0.1U_0402_16V4Z
1
2
R231
1
@ 4.7K_0402_5%
KSO3
+3VALW
R279
10K_0402_5%
28
19
R5_PME#
PCI_PME#
1
R298
1
R285
1
R281
EC_PME#
2
@ 0_0402_5%
36
36
2
0_0402_5%
34,46
34,46
4
4
KSO17
2
@ 10K_0402_5%
KSO[0..15]
KSI[0..7]
32,36
KSI[0..7]
+5VALW
EC_SMB_CK1
2
4.7K_0402_5%
EC_SMB_DA1
2
4.7K_0402_5%
1
R276
1
R275
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
21 SLP_S3#
21 SLP_S5#
21
EC_SMI#
36 LID_SWITCH#
18,23,26,28,29,35,42,43,44 SUSP#
21
PBTN_OUT#
EC_PME#
4,21 EC_THERM#
4 FAN_SPEED1
30
JACKCTL
13,14 EC_TX_P80_DATA
13,14 EC_RX_P80_CLK
32
ON/OFF#
36
PWR_LED#
36
NUM_LED#
KSO[0..15]
32
KSO16
KSO17
PM_SLP_S5#
EC_SMI#
LID_SWITCH#
SUSP#
PBTN_OUT#
EC_PME#
EC_THERM#
FAN_SPEED1
EC_TX_P80_DATA
EC_RX_P80_CLK
1
2
3
4
5
7
8
10
12
13
37
20
38
GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC
PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D
77
78
79
80
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
AD
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A
DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F
KB926QFA1_LQFP128
@ 100P_0402_50V8J
68
70
71
72
83
84
85
86
87
88
R898
0_0402_5%
EN_WOL
24
2
2
BATT_TEMP 46
BATT_OVP 40
ADP_I
40
BRD_ID
DAC_BRIG
EN_FAN1
IR EF
DAC_BRIG 16
EN_FAN1 4
IREF
40
VOLUME 30,31
TP_CLK
TP_DATA
0_0402_5%
2 @
1
R294
EC_MUTE# 30,31
EN_WOL
24
USB_ON
31,37
0
1
2
3
4
5
6
7
TP_LOCK_LED# 36
CMOS_OFF# 36
TP_CLK 37
TP_DATA 37
SPI_PULLDOWN R3361
2 4.7K_0402_5%
BT_OFF# 27
CD_PLAY 23,29
MODE#
36
119
120
126
128
FRD#SPI_SO
FWR#SPI_SI
SPI_CLK
FSEL#SPICS#
PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7
110
112
114
115
116
117
118
V18R
124
CHARGE_LED0#
CAPS_LED#
CHARGE_LED1#
SYSON
EC_LID_OUT#
EC_ON
ICH_POK_EC
BKOFF#
JACK_DETECT
0
8.2K
18K
33K
56K
100K
200K
NC
0V
0.25V
0.50V
0.82V
1.19V
1.65V
2.20V
3.30V
C
+3VS
EC_MUTE#
RCIRRX 32
PCMRST# 23
FSTCHG 40
CHARGE_LED0# 36
CAPS_LED# 36
CHARGE_LED1# 36
NOVO_IN# 36
SYSON 26,35,42
VR_ON
45
ACIN
21,39
1
R311
2
@ 10K_0402_5%
+5VS
TP_CLK
1
R317
TP_DATA 1
R321
31,37
EC_RSMRST# 21
EC_LID_OUT# 21
EC_ON
32,40
EC_SWI#
D372 RB751V_SOD323
1
BKOFF#
16
@
1
2
RF_OFF# 27
R893
0_0402_5%
EC_IDERST 29
SCROLL_LED# 36
STB_SB# 35
BATT_IN 46
R578(Rb) Vab
R119(Ra)=100K Ohm
FRD#SPI_SO 34
FWR#SPI_SI 34
SPI_CLK 34
FSEL#SPICS# 34
SLP_S4# 21
ENBKL
16
EAPD
29
KILL_SW# 32
BRD ID
R01 (EVT)
R02 (DVT)
R03 (PVT)
R10A (MP)
R916
10K_0402_5%
VGA@
ID
C HIP_ID
97
98
99
109
100
101
102
103
104
105
106
107
108
GPI
BRD_ID
AGND
C415
BATT_TEMP
BATT_OVP
INVT_PWM 16
BEEP#
29
1
2
ACOFF
39,40
1
R883
2
0_0402_5%
2
4.7K_0402_5%
2
4.7K_0402_5%
1
2
R897 10K_0402_5%
USB_ON
ICH_POK
ICH_POK 7,21
1
2
+3VS
R855 10K_0402_5%
@
JACK_PLUG 37
XCLKO 1 R338
2 XCLKI
@ 20M_0603_5%
69
63
64
65
66
75
76
EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11
XCLK1
XCLK0
GND
GND
GND
GND
GND
122
123
INVT_PWM
BEEP#
ENLAN1
ACOFF
R578
EC_TX_P80_DATA
EC_RX_P80_CLK
1
2
3
4
IN
OUT
1
2
3
4
15P_0402_50V8J
+3VALW
NC
JP59
A
NC
EC DEBUG PORT
C442
15P_0402_50V8J
C443
ECAGND
ECAGND
@ 100P_0402_50V8J
XCLKI
XCLKO
1
BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
PSCLK1/GPIO4A
KSI4/GPIO34
PSDAT1/GPIO4B
KSI5/GPIO35
PSCLK2/GPIO4C
PS2
Interface
KSI6/GPIO36
PSDAT2/GPIO4D
KSI7/GPIO37
TP_CLK/PSCLK3/GPIO4E
KSO0/GPIO20
TP_DATA/PSDAT3/GPIO4F
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
SDICS#/GPXOA00
KSO4/GPIO24
SDICLK/GPXOA01
KSO5/GPIO25 Int. K/B
SDIDO/GPXOA02
KSO6/GPIO26 Matrix
SDIDI/GPXID0
SPI Device Interface
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
SPIDI/RD#
KSO10/GPIO2A
SPIDO/WR#
SPI Flash ROM SPICLK/GPIO58
KSO11/GPIO2B
KSO12/GPIO2C
SPICS#
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
CIR_RX/GPIO40
KSO16/GPIO48
CIR_RLC_TX/GPIO41
KSO17/GPIO49
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
GPIO BATT_LOW_LED#/GPIO54
SCL1/GPIO44
SDA1/GPIO45
SUSP_LED#/GPIO55
SM Bus
SCL2/GPIO46
SYSON/GPIO56
SDA2/GPIO47
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59
11
24
35
94
113
1
R282
1
R288
XCLKI
XCLKO
21
23
26
27
PWM Output
+3VS
EC_SMB_CK2
2
4.7K_0402_5%
EC_SMB_DA2
2
4.7K_0402_5%
C417
INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13
DA Output
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
BATT_TEMP 2
ECAGND
1
C381 0.01U_0402_16V7K
KB_RST#R
C HIP_ID
1
C621
0.1U_0402_16V4Z
GATEA20
21,28,32
SIRQ
20,32 LPC_FRAME#
20,32
LPC_AD3
20,32
LPC_AD2
20,32
LPC_AD1
20,32
LPC_AD0
R915 UMA@
100K_0402_1%
BRD_ID
D9
15 CLK_PCI_LPC
67
U20
56K_0402_5%
RB751V_SOD323
20
2
1
KB_RST#
2
R574
100K_0402_1%
20
+3VALW
+EC_AVCC
AVCC
9
22
33
96
111
125
C413
1000P_0402_50V7K
C425
1000P_0402_50V7K
C439
0.1U_0402_16V4Z
C437
0.1U_0402_16V4Z
C431
0.1U_0402_16V4Z
C382
0.1U_0402_16V4Z
VCC
VCC
VCC
VCC
VCC
VCC
+3VALW
X1
ACES_85205-0400
ME@
32.768KHZ_12.5P_1TJS125BJ2A251
Security Classification
Issued Date
2006/08/04
2006/10/06
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
Title
Rev
0.1
Sheet
1
33
of
47
+3VALW
C658
2
2
0.1U_0402_16V4Z
20mils
U36
33 FSEL#SPICS#
33
SPI_CLK
33
FWR#SPI_SI
FSEL#SPICS# 2
R670
SPI_CLK
2
R617
FWR#SPI_SI 2
R611
VCC
HOLD
VSS
R885
10K_0402_5%
SPI_CS#
1
15_0402_5%
SPI_CLK_R
1
15_0402_5%
SPI_SI
1
15_0402_5%
SPI_SO 2
R613
SPI_CLK_R
1
33_0402_5%
JP11
SPI_CS#
SPI_SO
1
3
5
7
+3VALW
1
3
5
7
2
4
6
8
2
4
6
8
+3VALW
SPI_CLK_R
SPI_SI
E&T_2941-G08N-00E~D
ME@
+5VALW
1
+5VALW
C364
2 0.1U_0402_16V4Z
R215
100K_0402_1%
33,46 EC_SMB_CK1
33,46 EC_SMB_DA1
8
7
6
5
VCC
WP
SCL
SDA
U7
A0
A1
A2
GND
1
2
3
4
AT24C16AN-10SU-2.7_SO8
1
FRD#SPI_SO 33
R221
100K_0402_1%
2
C879
22P_0402_50V8J
R908 2
1
15_0402_5%
SST25LF080A_SO8-200mil
Security Classification
Issued Date
2006/08/04
Deciphered Date
2006/10/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Rev
0.1
Sheet
34
of
47
J
+5VALW
@
J1
PAD-OPEN 3x3m
2
S
S
S
G
1
2
3
4
SI4800DY_SO8
@
C876
1
+VSB
C874
2 0.1U_0402_16V4Z
C465
10U_0805_10V4Z
8
7
6
5
SYSON#
SYSON#
U16
1
2
10U_0805_10V4Z
R903
33K_0402_5%
0.1U_0402_16V4Z
D
D
D
D
S
S
S
G
1
2
3
4
SI4800DY_SO8
R346
22K_0402_5%
Q24
1
1
C468
10U_0805_10V4Z
26,33,42 SYSON
C471
2
DTC124EK_SC59
+5VS
D
D
D
D
+5VALW
8
7
6
5
47K_0402_5%
U77
+VSB
R339
+3V_SB
+3VALW
2
C875
0.1U_0603_25V7K
SUSP 2
G
Q25
2N7002_SOT23
S
@
C457
0.1U_0603_25V7K
+5VALW
RTCVREF
1
2
G
Q94
2N7002_SOT23
STB_SB#
STB_SB#
33
RUNON
R183
R856
@
10K_0402_5%
2
10K_0402_5%
SUSP
SUSP
43
Q14
18,23,26,28,29,33,42,43,44 SUSP#
DTC124EK_SC59
RUNON
2
@ 0_0402_5%
R191
R99
470_0402_5%
470_0402_5%
VGA@
C666
0.1U_0603_25V7K
1 2
2
1
+0.9VS
+5VS
10U_0805_10V4Z
R623 1
R186
D
2 SUSP
G
Q15
2N7002_SOT23
SUSP
2
G
Q37
2N7002_SOT23
C662
470_0402_5%
1 2
SI4800DY_SO8
R625
33K_0402_5%
D
2 SUSP
G
Q5
2N7002_SOT23
VGA@
SUSP
2
G
Q16
2N7002_SOT23
1
2
3
4
C667
10U_0805_10V4Z
S
S
S
G
1 2
+VSB
D
D
D
D
U37
8
7
6
5
R115
47K_0402_5%
VGA@
8
7
6
5
D
D
D
D
S
S
S
G
SI4800DY_SO8
VGA@
C537
VGA@
10U_0805_10V4Z
2 SYSON
G
Q6
2N7002_SOT23
1
470_0402_5%
1 2
1 2
D
2 SUSP
G
Q22
2N7002_SOT23
RUNON
2
@ 0_0402_5%
R333
C269
0.1U_0603_25V7K
VGA@
470_0402_5%
1 2
Security Classification
Issued Date
2006/08/04
Deciphered Date
2006/10/06
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C538
2 SUSP
G
Q29
2N7002_SOT23
+1.25VS
S
1
R114 1
SUSP
2
G
Q7
2N7002_SOT23
VGA@
1
2
3
4
C539
VGA@
10U_0805_10V4Z
VGA@
0.1U_0402_16V4Z
R495
+VSB
470_0402_5%
U25
R326
470_0402_5%
+1.8V
+1.8VS
R111
1 2
+2.5VS
+3VS
+1.8V
2 SUSP
G
Q23
2N7002_SOT23
DC/DC Circuit
Size Document Number
Custom IGT30 LA-3571P
Date:
Rev
0.1
Sheet
35
of
47
+5VS
1 2
2 150_0402_5%
21
21
2
33
27
BTONLED
BTONLED
R821
2 220_0402_5%
0_0402_5%
2
2
0_0402_5%
USB20_N3
USB20_P3
USB20_N3
USB20_P3
Q98
DTC124EK_SC59
CMOS@
HT-297UD/NB_BLUE/AMB_0603
1 R394
1 R393
JP42
1
2
3
4
5
6
7
1
C880
10U_0805_10V4Z
( 1 )
CMOS_OFF#
2
0_0805_5%
LED1
Blue
R820 1
CMOS1
R912
AO3413_SOT23
Q97
CMOS@
R907
10K_0402_1%
CMOS@
D
C523
0.1U_0402_10V6K
1
+5VS
B A
B A
ACES_88266-05001
ME@
Amber
STATUS
AC
Chargin
Low BATT
LED2
R822 1
CHARGE_LED1#
33 CHARGE_LED1#
R823
+5VALW
Blue
BATT_CHG_LED#
CHARGE_LED0#
33 CHARGE_LED0#
BLUE
Blinking Blue
Amber
+3VALW
2 150_0402_5%
2 220_0402_5%
BATT_LOW_LED#
+3VALW
+5VALW
JP76
R904
100K_0402_5%
HT-297UD/NB_BLUE/AMB_0603
Amber
( 2 )
( 3 )
LED3
PWR_LED#
33 PWR_LED#
1
2
3
4
5
GND1
GND2
R824 1
2 150_0402_5%
33
33
32,33
32,33
D38
32,39
51ON#
33
MODE#
DJ_ON
KSO17
KSO16
KSI4
KSI3
R913 1
33 MODE_LED#
DAN202U_SC70
1
2
3
4
5
6
7
2 150_0402_5%8
9
10
11
12
13
14
29,30 INT_MIC_R
29,30 INT_MIC_L
1
2
3
4
5
6
7
8
9
10
11
12
GND
GND
MOLEX_53780-1270
+3VS
LED4
27
2
R661
3G_LED#
1
200_0402_5%
2
+3VS
HT-191NB5-DT_BLUE_0603~D
470_0402_5%
1
2
R827 0_0402_5%
1
2
R828 0_0402_5%
@
Right Switch BD
C830
2
100K_0402_5%
1000P_0402_50V7K
R830
R831
@
Dial Wheel
R836
100K_0402_5%
@
2
33 TP_LOCK_LED#
BLUE
Blinking Blue
Amber
+VCC5_LED
+5VS
+3VS
LED5
+5VALW
STATUS
AC
Chargin
Low BATT
ACES_87151-16071
HT-191NB5-DT_BLUE_0603~D
33
32,33
32,33
33
32,33
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
KSO16
KSI1
KSI0
KSO17
KSO16
KSI1
KSI0
KSO17
KSI2
NOVO_BTN#
Function
32 ON/OFFBTN#
KEY Matrix
KO16
KO17
NOVA_BTN#
KSI0
DW-UP
DW-DOWN
KSI1
DW-ENTER
33 SCROLL_LED#
33
NUM_LED#
33 CAPS_LED#
20 SATA_LED#
D34 1
2
CH751H-40_SC76
23
D35 1
2
CH751H-40_SC76
HDD
CD-ROM
MUTE
ODD_LED#
D26
OUTPUT
1
1
GND
C519
0.1U_0402_16V4Z
U21
2
2
2
2
2
RB751V_SOD323
220_0402_5%
220_0402_5%
220_0402_5%
220_0402_5%
0.1U_0402_16V4Z
18
17
0.1U_0402_16V4Z
1
1
C834 C835
R668
100K_0402_5%
2
VDD
R392
47K_0402_5%
1
1
1
1
+3VALW
LID_SWITCH# 33
C521
10P_0402_25V8K
D36
NOVO_BTN#
R835
100K_0402_5%
NOVO BTN
2
2
+3VALW
2
0_0402_5%
+3VALW
1
R391
R887
R832
R833
R834
16 G18
15 G17
14
13
12
11
10
9
8
7
6
5
4
3
2
1
JP77
NOVO_IN#
NOVO_IN# 33
51ON#
51ON#
32,39
DAN202U_SC70
A3212ELHLT-T_SOT23W-3
Security Classification
2006/08/04
Issued Date
2006/10/06
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
Title
Rev
0.1
Sheet
36
of
47
4 in 1 Card Reader
+VCC_4IN1_XD
+VCC_4IN1
JP12
41
28
28
28
28
D
SDDATA0_MSDATA0
SDDATA1_MSDATA1
SDDATA2_MSDATA2
SDDATA3_MSDATA3
28
XDD4
28
XDD5
28
XDD6
28
XDD7
28 SDCMD_MSBS
28
XDWP#
28
XDALE
28
XDCD#
28 SDWP#_XDRB#
28
28
XD_CE#
XDCLE
33
34
35
36
37
38
39
40
XD-D0
XD-D1
XD-D2
XD-D3
XD-D4
XD-D5
XD-D6
XD-D7
SDCMD_MSBS
XDWP#
XDALE
XDCD#
SDWP#_XDRB#
SDCLK_MSCLK
XD_CE#
XDCLE
30
31
29
23
25
26
27
28
XD-WE
XD-WP
XD-ALE
XD-CD
XD-R/B
XD-RE
XD-CE
XD-CLE
32
24
18
42
XD-GND
XD-GND
N.C.
N.C.
45
46
JP6
(60 MIL)
SD-VCC
MS-VCC
15
9
SD_CLK
SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3
SD-CMD
SD-CD-SW
SD-CD-COM
SD-WP-SW
SD-WP-COM
16
19
20
11
12
13
21
22
43
44
XD-VCC
SDDATA0_MSDATA0
SDDATA1_MSDATA1
SDDATA2_MSDATA2
SDDATA3_MSDATA3
XDD4
XDD5
XDD6
XDD7
4 IN 1 CONN
MS-SCLK
MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3
MS-INS
MS-BS
SD-GND
SD-GND
MS-GND
MS-GND
8
4
3
5
7
6
2
14
17
1
10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
+LCDVDD
R651
22_0402_5%
SDCLK 1
2 SDCLK_MSCLK
SDDATA0_MSDATA0
SDDATA0_MSDATA0 28
SD_MSDATA1
SD_MSDATA1 28
SD_MSDATA2
SD_MSDATA2 28
SDDATA3_MSDATA3
SDDATA3_MSDATA3 28
SDCMD_MSBS
SDCMD_MSBS 28
SDCD#_XDCD0#
SDCD#_XDCD0# 28
SDWP#_XDRB#
SDWP#_XDRB# 28
R649
22_0402_5%
MSCLK 1
2 SDCLK_MSCLK
SDCLK_MSCLK 28
SDDATA0_MSDATA0
SDDATA0_MSDATA0 28
SDDATA1_MSDATA1
SDDATA1_MSDATA1 28
SDDATA2_MSDATA2
SDDATA2_MSDATA2 28
SDDATA3_MSDATA3
SDDATA3_MSDATA3 28
MSCD#_XDCD1
MSCD#_XDCD1 28
SDCMD_MSBS
SDCMD_MSBS 28
9
9
LVDSAC+
LVDSAC-
9
9
LVDSA2+
LVDSA2-
9
9
LVDSA1+
LVDSA1-
9
9
LVDSA0+
LVDSA0-
LVDSAC+
LVDSACLVDSA2+
LVDSA2LVDSA1+
LVDSA1LVDSA0+
LVDSA0-
31
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
GNDGND
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
+3VS
EDID_CLK_LCD
EDID_DAT_LCD
EDID_CLK_LCD 9
EDID_DAT_LCD 9
LVDSBC+
LVDSBC-
LVDSBC+
LVDSBC-
LVDSB2+
LVDSB2-
9
9
D
LVDSB2+ 9
LVDSB2- 9
LVDSB1+
LVDSB1-
LVDSB1+ 9
LVDSB1- 9
LVDSB0+
LVDSB0-
LVDSB0+ 9
LVDSB0- 9
ME@ ACES_88107-30001
Audio Jack/USB
Conn.
+USB_VCCB
SHIELD GND
SHIELD GND
TAITW_R012-210-LR
1
1
+
C836
C837
150U_D_6.3VM
0.1U_0402_16V4Z
2
2
21
21
+3VALW
JP27
C838
1000P_0402_50V7K
USB20_N2
USB20_P2
USB20_N2
USB20_P2
USB20_N4
USB20_P4
21
USB20_N4
R894
21
USB20_P4
SWDJ@
2.2K_0402_5%
30
EXT_MIC
29
SPDIF
29 JACK_PLUG_MIC
EXT_MIC
SPDIF
JACK_PLUG_MIC
29 JACK_PLUG_CODEC
MMBT3906_SOT23
SWDJ@
30
JACK_PLUG
PL
30
PR
PL
PR
@
Q91
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
0.1U_0402_16V7K
C517
T/P Board
ACES_87213-2000
ME@
0.1U_0402_16V7K
1
2
R895
0_0402_5%
NOSWDJ@
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
C518
@
JACK_PLUG
JP70
9
10
1
2
3
9 4
10 5
6
7
8
1
2
3
4
5
6
7
8
+5VS
TP_DATA
TP_CLK
TP_DATA
TP_CLK
33
33
2 C513 SPDIF
470P_0402_50V8J
2 C878 EXT_MIC
470P_0402_50V8J
2 C512 JACK_PLUG_MIC
470P_0402_50V8J
2 C516 PR
470P_0402_50V8J
2 C515 JACK_PLUG
470P_0402_50V8J
2 C514 PL
470P_0402_50V8J
1
1
1
1
ACES_87151-0807G
ME@
+5VALW
+USB_VCCB
U15
C464 0.1U_0402_16V4Z
2
1
31,33 USB_ON
1
2
3
USB_ON 4
GND
IN
IN
EN#
OUT
OUT
OUT
FLG
G545A1P1U_SO8
8
7
6
5
1
USB_OC#2 21
USB_OC#4 21
C476
@ 1000P_0402_50V7K
Security Classification
2006/08/04
Issued Date
2006/10/06
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
Title
Rev
0.1
Sheet
37
of
47
IMVP
NB
VGATE
PWROK
VR_ON
EC
VRMPWRGD
ICH8
PWROK
CK505
CK_PWRGD
ICH_POK
H13
HOLEA
CL1
CLIP
H17
HOLEA
H3
HOLEA
H30
HOLEA
H5
HOLEA
H21
HOLEA
H23
HOLEA
FM9
1
H6
HOLEA
1
H11
HOLEA
H26
HOLEA
FM3
1
H12
HOLEA
H29
HOLEA
FM11
1
H7
HOLEA
H28
HOLEA
FM2
1
H4
HOLEA
FM1
1
H1
HOLEA
FM4
1
H27
HOLEA
FD6
1
H25
HOLEA
1
1
H24
HOLEA
FM5
1
H2
HOLEA
FM6
1
FD4
1
FM7
1
FD5
1
FM8
1
FD2
1
FD3
1
FD1
1
6
M2
HOLEA
H31
HOLEA
H8
HOLEA
H19
HOLEA
H18
HOLEA
H16
HOLEA
H15
HOLEA
H14
HOLEA
H9
HOLEA
Issued Date
2006/08/04
Deciphered Date
2006/10/06
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Security Classification
Hole
Size Document Number
Custom IGT30 LA-3571P
Date:
Rev
0.1
Sheet
38
of
47
ACIN
BATT ONLY
Precharge detector
Min.
typ.
Max.
H-->L 6.138V 6.214V 6.359V
L-->H 7.196V 7.349V 7.505V
Precharge detector
Min.
typ.
Max.
H-->L 13.843V 14.247V 14.636V
L-->H 14.936V 15.381V 15.814V
VIN
PJP1
2
1
PR13
100K_0402_5%
1 2
3
2
1
PR18
499K_0402_1%
1
2
PC191
0.01U_0402_25V7K
PQ5
RHU002N06_SOT323
2
G
PC7
0.01U_0402_25V7K
PACIN 40
PQ6
DTC115EUA_SC70-3
+5VALWP
PR29
47K_0402_5%
1
2
1
PR25
499K_0402_1%
1
PR24
205K_0402_1%
PRG++ 2
PR28
10K_0402_5%
2
1
PU1B
LM393DT_SO8
RTCVREF
PR30
66.5K_0402_1%
1
2
1
2
PR271
200K_0402_1%
2
1
PRECHG
40
PC9
1000P_0402_50V7K
ACON
40
PD6
RB715F_SOT323
2
1
3
41,46 MAINPWON
2
1
PR19
100K_0402_1%
2
1
PR20
68_1206_5%
PR276
68_1206_5%
1
VS
PC12
0.22U_1206_25V7K
PR27
22K_0402_1%
1
2
VS
PC8
0.1U_0603_25V7K
51ON#
PR17
2.2M_0402_5%
2
1
VL
PD4
RLS4148_LLDS2
2
32,36
CHGRTCP
1
PR26
100K_0402_5%
GND
PQ4
TP0610K-T1-E3_SOT23
IN
OUT
PC10
1U_0805_25V4Z
3
PC11
4.7U_0805_6.3V6K
+CHGRTC
PR23
200_0805_5%
2
1
17.011
14.063
PD5
RLS4148_LLDS2
2
1
RTCVREF
PU2
G920AT24U_SOT89
B+
PR15
10K_0402_1%
3.3V
PR22
PR21
560_0603_5%
560_0603_5%
1
2 1
2
PQ3
DTC115EUA_SC70-3
Vin Detector
BATT+
ACOFF
40
PC13
0.1U_0603_25V7K
RTCVREF
PR16
10K_0402_1%
2
1
PACIN
VIN
3.3V
PQ2
DTC115EUA_SC70-3
21,33
33,40
1
ACIN
PACIN
LM393DT_SO8
2
1
PR6
100K_0402_5%
PR8
1K_1206_5%
1
2
2
8
P
PR4
1K_1206_5%
1
2
PU1A
PC6
0.1U_0402_16V7K
PR11
10K_0402_5%
1
2
PD3
RLZ4.3B_LL34
2
1
PR10
82.5K_0402_1%
PR12
215K_0402_1%
1
2
2
1
PR14
24.9K_0402_1%
PC5
0.068U_0603_25V7M
2
1
VS
PQ1
TP0610K-T1-E3_SOT23
PR3
1K_1206_5%
1
2
VIN
1
PR9
10K_0805_5%
PR5
1M_0402_1%
1
2
VIN
VS
PD2
RLS4148_LLDS2
2
1
2
1
PR7
100K_0402_5%
1
PR1
10_1206_5%
1 2
2
PR175
PC131
@ 10K_0402_1% @ 0.01U_0402_25V7K
1
2
1
2
PR2
1K_1206_5%
1
2
PD1
RLZ24B_LL34
PC4
560P_0402_50V7K
2
@ JST_B4B-EH-A(LF)(SN)
PC3
100P_0402_50V8J
ADPIN
PL2
HCB4532KF-800T90_1812
1
2
PC2
100P_0402_50V8J
PF1
12A_65V_451012MRL
2
1
PC1
560P_0402_50V7K
Issued Date
Security Classification
2006/08/04
Deciphered Date
2006/10/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
DCIN/DETECTOR
Size
B
Date:
Document Number
Rev
0.1
Sheet
39
of
47
20
VREF
VH
19
ACIN XACOK
18
-INE1
17
11
SEL
CTL
14
12
-INC1
+INC1
13
PR62
MB39A126
1
PC35
1500P_0603_50V7K
1
2
PC40
10P_0402_50V8J
1
2
1
PR65
0_0402_5%
BATT+
3 2
33K_0402_1%
IREF=0.574~2.56V
1
39
39
2
PR56
0.02_2512_1%
15
PR278
@ 0_0402_5%
16
OUTC1 FB123
+INE1
PL5
16UH_LF919AS-160M=P3_3.7A_20%
1
2
39
PD11
EC31QS04
ACON
PACIN
1
PR273
10K_0402_1%
2
PR50
10K_0402_1%
1
1
3
2
1
LXCHRG
ACON
PR58
56.2K_0402_1%
1
2
-INE3
10
2
G
S
PD10
EC31QS04
RT
PC32
0.1U_0603_25V7K
1
2
PC26
2200P_0402_50V7K
1
2
1
PR49
0_0402_5%
PC243
0.1U_0603_25V7K
BATT+
OUT
2
PRECHG
PC38
10U_1206_25VAK
ACOK
PQ40
DTC115EUA_SC70-3
21
VCC
PQ14
DTC115EUA_SC70-3
PD34
2
1
21SS355TE-17_SOD323-2
PC37
10U_1206_25VAK
-INE2
47K
47K
VIN
CS
PR336
200K_0402_1%
1
2
PQ41
DTA144EUA_SC70
22
1
2
3
CS
33,39
PC36
10U_1206_25VAK
+INE2
PC29
0.22U_0603_16V7K
1
2
PC30
0.1U_0603_25V7K
1
2
2
PC39
0.01U_0402_25V7K
1
2
2
1
PR63
100K_0402_1%
PQ13
AO4407_SO8
5
6
7
8
8
7
6
5
VIN
23
Charger
PR272
100K_0402_1%
1
2
PD23
1SS355TE-17_SOD323-2
ACOFF
1
2
GND
8
7
6
5
1
2
PC33
0.22U_0603_16V7K
PR57
PC34
1K_0402_1% 2200P_0402_50V7K
2
1
2
MB39A1261
PR61
10K_0402_1%
2
1
PR66
3K_0402_1%
1
2
PC25
0.1U_0603_25V7K
2
1
2
OUTC2
1
2
PR337
100K_0402_5%
ACON
1
PR53
10K_0402_1%
2
1
PR54
34.8K_0402_1%
2
1
3
S PQ17
RHU002N06_SOT323
1
1
PR55
150K_0402_1%
PC31
0.01U_0402_25V7K
2
39
65W: PR54=34.8K
90W: PR54=21.0K
PR60
133K_0402_1%
33
1
2
2
G
PACIN
PR52
100K_0402_1%
2
1
PU4
MB39A126PFV-ER_SSOP24
1 -INC2 +INC2 24
PR48
47K_0402_1%
1
2
PR51
PC28
10K_0402_1% 4700P_0402_25V7K
1
2
1
2
1
3
1
3
PQ16
RHU002N06_SOT323
IREF
39
PJ12
PAD-OPEN 3x3m
2
PQ39
AO4407_SO8
1
2
3
CHG_B+
PC24
4.7U_1206_25V6K
1
2
PC133
0.22U_0603_16V7K
PL4
FBMA-L11-322513-201LMA40T_1210
1
2
PR110
10K_0402_5%
A/D
PQ15
DTC115EUA_SC70-3
ADP_I
MB39A126
PR45
2
0.02_2512_1%
P3
33
47K
2
G
PQ11
AO4407_SO8
8
7
6
5
PQ12
DTA144EUA_SC70
47K
2
1
2
3
2
1
PR47
47K_0402_5%
B+
PC23
4.7U_1206_25V6K
2
1
1
2
3
PC27
0.1U_0603_25V7K
2
1
PR46
200K_0402_1%
VIN
PQ10
AO4407_SO8
PQ9
AO4407_SO8
8
7
6
5
Fosc=14100/Rt=14100/47=300KHz
CP mode
65W: 2.8A
90W: 4.0A
P3
P2
PQ49
RHU002N06_SOT323-3
PD25 RB751V-40TE17_SOD323-2
1
2
FSTCHG 33
PD26 RB751V-40TE17_SOD323-2
1
2
EC_ON 32,33
2
33,39
ACOFF
PC41
47P_0402_50V8J
1
2
PQ18
DTC115EUA_SC70-3
LI-3S :13.5V----BATT-OVP=1.5V
BATT-OVP=0.1112*BATT+
CS
1
PQ48
DTC115EUA_SC70-3
PR67
47K_0402_5%
+3VALWP
(100K/(100K+133K))*2.56V=1.0985V
PQ19
DTC115EUA_SC70-3
CC=2.746A
PU12B
LM358DR_SO8
1.116V/(20*0.02)=2.8A
2006/08/04
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Charge voltage
3S CC-CV MODE : 12.6V
SEL is L
Security Classification
Issued Date
PC43
0.01U_0402_25V7K
5V*(10K/(34.8K+10K))=1.116V
0
4
PU12A
LM358DR_SO8
+ 3
2
1
2
1
PR69
PR68
499K_0402_1% 340K_0402_1%
1
1
2
P
A/D
33 BATT_OVP
PR277
10K_0402_1%
2
1
CP Point=2.8A
2
1
PR72
105K_0402_1%
VS
VS
1.098/(20*0.02)=2.746A
BATT+
PC42
0.01U_0402_25V7K
FSTCHG
33
Title
CHARGER
Size
B
Date:
Document Number
Rev
0.1
Sheet
40
of
47
B+
PC46
0.1U_0603_25V7K
1
2
BST3B
BST5B
PC45
0.1U_0603_25V7K
1
2
PL6
FBMA-L11-322513-201LMA40T_1210
VL
1
PQ21
SI4800BDY-T1-E3_SO8
PQ20
SI4800BDY-T1-E3_SO8
4
3
2
1
G
S
S
S
D
D
D
D
5
6
7
8
10U_1206_25VAK
PC48
1
2
1
2
PR93
PR90
0_0402_5% @ 3.57K_0402_1%
10
2
PR92
0_0402_5%
46
PL8
4.7UH_PCMC063T-4R7MN_5.5A_20%
1
2
D
D
D
D
G
S
S
S
4
3
2
1
PR82
0_0402_5%
2
1
7
2
1
+
+3VALWP
PC58
150U_V_6.3VM_R18
PQ30
SI4810BDY-T1-E3_SO8
5
6
7
8
1
2
1
2
PR84
PR81
499K_0402_1% 200K_0402_1%
DH3
1
2
PC60
4.7U_0805_6.3V6K
PC59
0.22U_0603_16V7K
PC47
2200P_0402_50V7K
2
1
2
PR79
0_0402_5%
1
2
1
2
17
1
2
1
2
PR83
PR80
499K_0402_1% 118K_0402_1%
BST3A
28
26
24
27
22
PRO#
VCC
PC53
1U_0603_6.3V6M
11
DL3
SPOK
PC61
@ 0.047U_0603_16V7K
1
2
PC49
0.1U_0402_16V7K
2
1
PR77
4.7_1206_5%
1
2
PR75
47_0402_5%
1 PC55
0.1U_0603_25V7K
2
LD05
TON
LDO3
REF
23
PR89
0_0402_5%
2VREF_87348
PC227
0.047U_0603_25V7M
13
LX5
DL5
ILIM5
OUT5
PU6
FB5
BST3
N.C.MAX8734AEEI+_QSOP28 DH3
DL3
SHDN#
LX3
ON5
OUT3
ON3
FB3
SKIP#
PGOOD
ILIM3
PR323
806K_0603_1%
PR322
0_0402_5%
2
1
18
15
19
21
9
1
V+
DH5
3HG
LX3
VL
20
PC54
4.7U_0805_6.3V6K
2
1
0_0402_5%
1
PR94
@ 47K_0402_5%
1
2
39,46 MAINPWON
BST5
16
12
PR280
2
1
2
PC57
@ 0.047U_0603_16V7K
PZD1
RLZ5.1B_LL34
1
2
PR91
100K_0402_5%
PR88
47K_0402_5%
2 1
2
2VREF_8734
14
6
4
3
PR324
0_0402_5%
MAX8734_B++
VS
MAX8743_B+
GND
PQ29
SI4810BDY-T1-E3_SO8
8
7
6
5
D
D
D
D
S
S
S
G
1
2
3
4
BST5A
2
PR86
@ 0_0402_5%
DL5
PR85
10.2K_0402_1%
PL7
4.7UH_PCMC063T-4R7MN_5.5A_20%
1
2
PC56
150U_V_6.3VM_R18
+5VALWP
PR87
0_0402_5%
VL
MAX8734_B++
PC52
4.7U_1206_25V6K
2
1
DH5
LX5
25
2
PR74
0_0402_5%
PR78
0_0402_5%
2
PR76
4.7_1206_5%
1
5HG
PD13
CHP202UPT_SOT323-3
MAX8743_B+
8
7
6
5
D
D
D
D
S
S
S
G
1
2
3
4
1
2
PC51
10U_1206_25VAK
1
2
MAX8743_B+
PC50
2200P_0402_50V7K
Issued Date
Security Classification
2006/08/04
Deciphered Date
2006/10/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
+5VALWP/+3VALWP
Size Document Number
Custom
Date:
Rev
0.1
Sheet
41
of
47
OZ813_B+
D
+1.8VP
1
2
PR95
51_0402_1%
2
1
2
PC69
22P_0402_50V8J
OZ813_B+
PL11
1UH_PCMB103E-1R0MS_20A_20%
1
2
+
2
PC230
4.7U_0805_6.3V6K
+
2
PC229
220U_D2_4VM_R15
2
1
1
2
1
2
5
6
7
8
PC81
22P_0402_50V8J
PR333
10.5K_0402_1%
3
2
1
DL_1.05V4
1.05VS1N
PC79
10U_1206_25VAK
PR108
PR109
100K_0402_1% @ 300K_0402_1%
1
2 1
2
PC80
4700P_0402_25V7K
1.05VS1P
2
1
+3VALWP
PQ31
IRF7836PBF_SO8
+1.05VSP
PR107
51_0402_1%
1
2
PC156
2.2U_0603_6.3V6K
1
2
PQ24
SI4684DY-T1-E3_SO8
5
6
7
8
4
3
2
1
G
S
S
S
D
D
D
D
+
2
PC70
4700P_0402_25V7K
PQ23
SI4810BDY-T1-E3_SO8
5
6
7
8
D
D
D
D
G
S
S
S
1
2
1.05VS1N
1
PR270
0_0402_5%
1.05VS1P
2
PR263
0_0402_5%
PC132
1U_0402_6.3V6K
1.8VS2N
LX1.05V
PC77
1000P_0402_50V7K
PR98
30K_0402_1%
1
2
PC68
4700P_0402_25V7K
1
2
+5VALWP
2
PD17
RB751V-40TE17_SOD323-2
DH_1.05V_1
1.8VS2P
PC71
1U_0603_6.3V6M
BST_1.05V1
PR179
33K_0402_1%
2
1
PR97
100K_0402_1%
1
2
+5VALWP
DH_1.05V_2
4
3
2
1
1
18
17
16
15
14
13
7
8
9
10
11
12
VSET1
CS1N
CS1P
PGD1
LX1
HDR1
OZ813LN_QFN24
PR172
61.9K_0402_1%
2
1
2
BST2
LDR2
VDDP
GDNP
LDR1
BST1
DL_1.8V
PD16
RB751V-40TE17_SOD323-2
BST_1.8V 1
2
PC76
0.1U_0603_25V7K
1
PC75
0.01U_0402_25V7K
ON/SKIP2
VIN
VREF
TSET
VDDA
ON/SKIP1
PC67
0.1U_0603_25V7K
24
23
22
21
20
19
25
GNDA
VSET2
CS2N
CS2P
PGD2
LX2
HDR2
PR100
1K_0402_1%
1
2
1
2
1
2
3
4
5
6
1.05SET
PR106
150K_0402_1%
1
2
1.8VSET
1
2
PR105
75K_0402_1%
1
2
PR104
100K_0402_1%
PC73
0.1U_0603_25V7K
2
1
PC72
0.022U_0402_16V7K
2
1
PR103
24K_0402_1%
1
2
PR101
0_0402_5%
2
1
PC74
1U_0603_6.3V6M
PR99
22_0402_1%
1
2
PU7
PC65
1000P_0402_50V7K
+5VALWP
PC228
4.7U_0805_6.3V6K
LX_1.8V
1.8VSET
18,23,26,28,29,33,35,43,44 SUSP#
PL10
2.2UH_MPL73-2R2_8A_20%
PC82
4700P_0402_25V7K
PR266
0_0402_5%
2
1
PC184
0.01U_0402_25V7K
26,33,35 SYSON
DH_1.8V_2
PC66
220U_D2_4VM_R15
PR269
0_0402_5%
2
DH_1.8V_1 1
PC78
220U_D2_4VM_R15
+3VALWP
PR262
@ 0_0402_5%
1
2
SI4800BDY-T1-E3_SO8
PQ22
4 G
D 5
3 S
D 6
2 S
D 7
1 S
D 8
1.8VS2N
1.8VS2P
PC63
10U_1206_25VAK
PL9
FBMA-L11-322513-201LMA40T_1210
1
2
B+
Issued Date
Security Classification
2006/08/04
2006/10/06
Deciphered Date
1.05VSP/1.8VP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
Title
Rev
0.1
Sheet
1
42
of
47
PL12
FBMA-L11-322513-201LMA40T_1210
2
B+
D
D
D
D
BST_1.5
1
2
G
S
S
S
4
3
2
1
+1.5VSP
1
+
PQ27
SI4810BDY-T1-E3_SO8
G
S
S
S
2
PC198
1U_0603_6.3V6M
18.2K_0402_1%
DL
PGND
VDDP
PR287
1
10
PC231
4.7U_0805_6.3V6K
ILIM
PL13
3.3UH_MPL73-3R3_6A_20%
DH_1.5A
LX_1.5
5
6
7
8
LX
11
PR285
0_0402_5%
1
2
DH_1.5
D
D
D
D
12
PQ26
SI4800BDY-T1-E3_SO8
PC88
220U_D2_4VM_R15
BST
13
15
NC
7
DH
1
2
TPAD
NC
PGD
14
16
FB
EN/PSV
TON
VCCA
VSSA
17
VOUT
PC200
1U_0603_6.3V6M
PC199
1000P_0402_50V7K
1
2
10.7K_0402_1%
PR288
PR284
21.5K_0402_1%
2
1
PC196
33P_0402_50V8J
2
1
PR286
@ 470K_0402_1%
2
1
1
2
PC197
@ 0.1U_0402_16V7K
PU13
PC195
0.1U_0603_25V7K
4
3
2
1
2
+5VALWP
+1.5VSP
PC193
10U_1206_25VAK
1
2
5
6
7
8
PD21
RB751V-40TE17_SOD323-2
1
2
1
1
PR334
470K_0402_1%
PC194
1U_0402_6.3V6K
PC192
2200P_0402_50V7K
PR283
3K_0402_1%
1
2
18,23,26,28,29,33,35,42,44 SUSP#
PR282
10_0402_5%
PR281
1M_0402_5%
+5VALWP
SC411MLTRT_MLPQ16_4X4
DL_1.5
VFB=0.5V
+1.8VP
+3VS
2
2
PU9
2
4
VOUT
FB
VIN
VCNTL
GND
NC
VREF
NC
VOUT
NC
TP
2
1
1
PC101
0.1U_0402_16V7K
+0.9VSP
PR124
1K_0402_1%
2
G
PQ28
RHU002N06_SOT323
PC103
1U_0402_6.3V6K
PR123
10K_0402_1%
2
1
SUSP
35
0.01U_0402_25V7K
PC95
1U_0603_6.3V6M
G2992F1U_SO8
1
2
2
APL5912-KAC-TRL_SO8
22U_1206_6.3V6M
PC99
PC97
2
PR122
2.15K_0402_1%
+3VALWP
1
PR120
1K_0402_1%
+2.5VSP
1
EN
GND
PR125
1K_0402_1%
PC102
22U_1206_6.3V6M
VIN
VOUT
PC94
22U_1206_6.3V6M
PC96
22U_1206_6.3V6M
PC100
1U_0402_6.3V6K
VIN
8,29,33,35,42,44 SUSP#
PR121
2.2K_0402_1%
1
2
POK
VCNTL
PU10
7
1U_0603_6.3V6M
PJ9
JUMP_43X118
PC93
PJ10
JUMP_43X79
+5VS
Issued Date
Security Classification
2006/08/04
2006/10/06
Deciphered Date
+1.5VSP/+0.9VSP/+2.5VSP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
Title
Rev
0.1
Sheet
1
43
of
47
PL17
FBMA-L11-322513-201LMA40T_1210
1
2
B+
+5VALWP
12.7K_0402_1%
G
S
S
S
SC411MLTRT_MLPQ16_4X4
1
2
PC233
10U_1206_25VAK
+1.25VSP
1
PQ46
SI4810BDY-T1-E3_SO8
5
6
7
8
D
D
D
D
4
3
2
1
PC239
1U_0603_6.3V6M
G
S
S
S
+
2
PR331
PC237
4.7U_0805_6.3V6K
10
DL
4
3
2
1
LX_1.25
11
ILIM
VDDP
PL19
4.7UH_PCMC063T-4R7MN_5.5A_20%
1
2
PC219
220U_D2_4VM_R15
12
DH_1.25A
PQ44
SI4800BDY-T1-E3_SO8
D
D
D
D
1
BST
14
NC
PR329
0_0402_5%
1
2
LX
PC235
0.1U_0603_25V7K
DH_1.25
PGD
TPAD
17
FB
BST_1.25
DH
PGND
16
TON
EN/PSV
VSSA
VCCA
NC
VOUT
5
6
7
8
PD22
RB751V-40TE17_SOD323-2
1
2
1
2
PC241
1U_0603_6.3V6M
1
2
PU16
PC240
1000P_0402_50V7K
10.2K_0402_1%
PR328
2
1
PR332
2
15.4K_0402_1%
+1.25VSP
15
2
PC236
33P_0402_50V8J
2
1
1
2
PR335
470K_0402_1%
13
PC234
@ 0.1U_0402_16V7K
PR327
0_0402_5%
1
18,23,26,28,29,33,35,42,43 SUSP#
PR326
10_0402_5%
PC232
2200P_0402_50V7K
PR325
1M_0402_5%
DL_1.25
VFB=0.5V
+1.5VSP
PJ1
@ PAD-OPEN 3x3m
1
2
+1.5VS
+1.8VP
PJ2
@ PAD-OPEN 3x3m
1
2
+1.8V
PJ4
@ JUMP_43X39
1 1
2 2
+0.9VS
+2.5VS
+5VALWP
PJ3
@ PAD-OPEN 3x3m
1
2
+5VALW
+3VALWP
PJ6
@ PAD-OPEN 3x3m
1
2
+3VALW
+2.5VSP
PJ11
@ JUMP_43X39
1 1
2 2
PJ7
@ PAD-OPEN 3x3m
1
2
+VCCP
+VSBP
PJ8
@ JUMP_43X39
1 1
2 2
+1.05VSP
+0.9VSP
+1.25VSP
PJ19
@ PAD-OPEN 3x3m
1
2
PR313
0_1206_5%
2
1
+1.25VS
+VCCGFX
+VSB
A
+VCCP
PR309
@ 0_1206_5%
2
1
UMA
Discrete
PR313
PR309
Issued Date
Security Classification
2006/08/04
2006/10/06
Deciphered Date
1.25VSP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
Title
Rev
0.1
Sheet
1
44
of
47
+5VS
CPU_B+
B+
DL1__CPU
CPU_VID4
35
D4
PGND1
27
CPU_VID5
36
D5
GND
18
CPU_VID6
D6
CSP1
17
PWRGD
CLKEN
38
PR247
10_0402_5%2
PR253
@ 0_0402_5%
1
2
23
SHDN
CSP2
14
CSP2_CPU
VRHOT
CSN2
15
CSN2__CPU
GNDS
13
POUT
PR251
100_0402_5%
5
PR254
@ 10K_0402_5%
1
2
CPU_POUT
VSSSENSE
PR314
0_0402_5%
1
2
PC181
@ 0.1U_0402_16V7K
@ PR246
3K_0603_1%
PR248
20K_0402_1%
1
1
PR275
0_0402_5%
1
2
PC242
100U_25V_M
2
PR243
100_0402_5%
2
CPU_B+
PQ35
SI7686DP-T1-E3_SO8
PR258
PR259 NTC
3.48K_0402_1% 10KB_0603_5%_ERTJ1VR103J
1
2
1
2
PC183
0.22U_0603_16V7K
1
2
2
A
1
2
PC189
180P_0402_50V8J
PR257
2.1K_0603_1%
1
2
3
2
1
DL2__CPU
PC182
470P_0603_50V7K
PQ36
IRF7836PBF_SO8
PL16
P_0.36H_ETQP4LR36WFC_24A_20%
2
1
PR256
6.8_1206_5%
5
6
7
8
5
6
7
8
3
2
1
PR260
0_0402_5%
PC190
180P_0402_50V8J
2006/08/04
Issued Date
Security Classification
Deciphered Date
2006/10/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
CPU_VCC_SENSE
PC173
470P_0402_50V7K
PQ37
IRF7836PBF_SO8
PC163
2200P_0402_50V7K
2
1
PC162
0.1U_0603_25V7K
2
1
PC161
10U_1206_25VAK
2
1
PC160
10U_1206_25VAK
2
1
1
2
PR245
NTC @ 3K_0603_1%
PR255
10_0402_5%
PC171
@ 0.022U_0402_16V7K
1
2
1
2
PR238
@ 3K_0603_1%
PR242
3.65K_0402_1%
2
PR237
0_0402_5%
PC187
180P_0402_50V8J
A/D
24
+3VS
DL2__CPU
PC188
180P_0402_50V8J
DL2
MAX8770GTL+_TQFN40
4 H_PROCHOT#
LX2_CPU
PGND2
PR249
10_0402_5%2
BST2_CPU
22
VCCSENSE
3
2
1
2
PR241
10K_0402_1%
5
4
1
2
PR240
2K_0402_1%
PR244
0_0402_5%
1
2
20
LX2
PC169
0.22U_0603_16V7K
1
2
BST2
PR230
PR231
3.48K_0402_1% 10KB_0603_5%_ERTJ1VR103J
1
2
1
2
PSI
DPRSTP
40
PR226
2.1K_0603_1%
PC167
470P_0603_50V7K
DH2_CPU
C CI_CPU
21
PC172
4700P_0402_25V7K
10
DH2
PQ34
IRF7836PBF_SO8
3
2
1
CCI
DPRSLPVR
DL1__CPU
REF
3
2
1
11
0.22U_0603_16V7K 39
VR_ON
FB_CPU
5,7,20 H_DPRSTP#
1
2
PR250
10K_0402_5%
33
CSN1_CPU
12
2
1
PR252
56_0402_5%
21 CLK_ENABLE#
16
FB
VGATE
CSN1
CCV
7,21 DPRSLPVR
PR236 0_0402_5%
7,21
TIME
71.5K_0402_1%
1
7
1
PC168
2
CSP1__CPU
37
1
2
PR239
2.2_0402_5%
PQ33
IRF7836PBF_SO8
2
PR235
0_0402_5%
LX1__CPU
26
28
DL1
PR229
10_0402_5%
2
1
LX1
D3
PC180
2200P_0402_50V7K
2
1
D2
34
PC179
0.1U_0603_25V7K
2
1
33
PC178
10U_1206_25VAK
2
1
PC177
10U_1206_25VAK
2
1
CPU_VID3
PL15
P_0.36H_ETQP4LR36WFC_24A_20%
+CPU_CORE
2
1
PC176
10U_1206_25VAK
2
1
CPU_VID2
H_PSI#
+3VS
+
2
+CPU_CORE
29
PR224
6.8_1206_5%
30
DH1
PC170
5
BST1
D1
3
2
1
D0
32
5
6
7
8
31
PQ32
SI7686DP-T1-E3_SO8
5
6
7
8
0_0402_5%
PC159
10U_1206_25VAK
2
1
CPU_VID1
PR2322
PR234
200K_0402_5%
2 PR216 1
CPU_VID0
2
470P_0402_50V7K
1
PR233 499_0402_1%
BSTM2_CPU
PR228 0_0402_5%
PC175
2
1
PR227 0_0402_5%
25
TON
0.22U_0603_16V7K
PR225 0_0402_5%
VDD
THRM
PR223 0_0402_5%
Vcc
0.22U_0603_16V7K
PR220
PC166
2.2_0402_5%
BST1_CPU 1
BSTM1_CPU
2
1
2
PR274
DH1__CPU
10_0402_5%2
PR222 0_0402_5%
19
PR221 0_0402_5%
PU11
V CC
4700P_0402_25V7K
PC174
1
2
PR219 0_0402_5%
2
NTC
100K_0402_5%
PR218
1
2
PC165
1U_0603_6.3V6M
PR217
13K_0402_5%
1
2
PC164
2.2U_0603_6.3V6K
PC157
0.01U_0402_25V7K
0_1206_5%
PR215
10_0402_5%
PL14
FBMA-L11-322513-201LMA40T_1210
2
1
PC158
100U_25V_M
PR214
5VS12
Title
+CPU_CORE
Size Document Number
Custom
Date:
R ev
0.1
Sheet
1
45
of
47
1
PR35
100_0402_1%
1
2
1
2
PL3
HCB4532KF-800T90_1812
1
2
PC15
1000P_0402_50V7K
PC14
1000P_0402_50V7K
+3VALWP
BATT+
VL
VS
ALI/MH#
CPU
PC224
0.1U_0603_25V7K
+3VALWP
PR36
6.49K_0402_1%
1
2
1
PR38
1K_0402_1%
PH1
39,41
1
100K_0603_1%_TH11-4H104FT
MAINPWON
VL
PR315
470K_0402_1%
1
2
PR316
470K_0402_1%
4
2
2
G
LM393DT_SO8
PQ47
RHU002N06_SOT323
PR321
100K_0402_1%
PR320
24.3K_0603_1%
OTP
OTPREF2
PC225
1000P_0402_50V7K
PC226
0.22U_0603_16V7K
VL
1
2
PR319
100K_0402_1%
PU15A
OTPFB2
PR318
215K_0603_1%
1
2
N72
2
PR317
0_0402_5%
EC_SMB_CK1 33,34
EC_SMB_DA1 33,34
BATT_TEMP 33
A/D
N71
2
1
PR31
100_0402_1%
ALI/NIMH#
AB/I
TS_A
EC_SMDA
EC_SMCA
2
3
4
5
6
7
2
3
4
5
6
7
BATT++
PF2
12A_65V_451012MRL
2
1
PR177
PR178
1K_0402_1%
47K_0402_5%
1
2
1
2
BATT_S1
2
1
PR176
1K_0402_1%
@ PJP2
ALLTO_C103D6-10701-L
1 1
PC16
0.01U_0402_25V7K
PQ7
TP0610K-T1-E3_SOT23
+3VALWP
+3VALWP
PC21
0.1U_0603_25V7K
2
2
1
2
PC20
0.22U_1206_25V7K
PR41
100K_0402_5%
O
4
BATT_IN
PU15B
2
G
LM393DT_SO8
33
PQ50
RHU002N06_SOT323
PR340
470K_0402_1%
PC244
@ 1000P_0402_50V7K
2
1
PR339
30K_0402_1%
RTCVREF
8
2
1
PR338
470K_0402_1%
1
33 BATT_TEMP
S PQ8
RHU002N06_SOT323
2
G
PR342
470K_0402_1%
PR341
470K_0402_1%
PR44
0_0402_5%
2
SPOK
41
VS
PC22
0.1U_0402_16V7K
1
2
PR43
100K_0402_5%
PR42
22K_0402_1%
1
2
VL
+VSBP
B+
PC245
1000P_0402_50V7K
Issued Date
Security Classification
2006/08/04
Deciphered Date
2006/10/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
Document Number
Rev
0.1
Sheet
46
of
47
Fixed Issue
Page 1 of 1
Rev.
PG#
Modify List
B.Ver#
Phase
45
40
Delete PR59PR64.
ADD PD19 PD 20.
45
Delete PD12.
ADD PD21 PD22 PR250 PQ50 PC198..
42
3
4
42
2
46
For adjust +1.8VP, Change PR179 to 33k_0402_1% and add PC132 1u_0402_6.3v
For adjust +1.5VSP, Change PR283 to 3k_0402_1% and add PC194 1u_0402_6.3v
2
For adjust +2.5VSP, Change PR121 to 2.2k_0402_1% and add PC100 1u_0402_6.3v
For adjust +0.9VSP, Change PR123 to 10k_0402_1% and add PC103 1u_0402_6.3v
POWER PIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Size
Date:
Document Number
Monday, December 25, 2006
Rev
Sheet
E
47
of
47
Fixed Issue
Page 1 of 1
Rev.
PG#
Modify List
B.Ver#
A2
35
Add C(874~876),R903,J1,Q94,U77
Phase
Add
A2
24
Add C877,R902,Q93
A2
37
A2
36
Add R904
A2
29
Add R905,Q96
A2
27
A2
32 37
Add R908,C878,C879
30
Add D39,Q99,R914
36
Add R912,C880
10
Fixed EMI
25
Add C881,C882
11
Add chipset id
33
12
31
Add R915,R916
Add R917
POWER PIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
Size
Date:
Document Number
Tuesday, December 26, 2006
Rev
Sheet
1
48
of
48