De Lab Manual New

147351 (DIGITAL ELECTRONICS) LAB MANUAL
SYLLABUS
1. Design and implementation of Adders and Subtractors using logic gates. 2. Design and implementation of code converters using logic gates (i) BCD to excess-3 code and voice versa (ii) Binary to gray and vice-versa 3. Design and implementation of 4 bit binary Adder/ Subtractor and BCD adder using IC 7483 4. Design and implementation of 2Bit Magnitude Comparator using logic gates 8 Bit Magnitude Comparator using IC 7485 5. Design and implementation of 16 bit odd/even parity checker /generator using IC74180. 6. Design and implementation of Multiplexer and De-multiplexer using logic gates and study of IC74150 and IC 74154 7. Design and implementation of encoder and decoder using logic gates and study of IC7445 and IC74147 8. Construction and verification of 4 bit ripple counter and Mod-10 / Mod-12 Ripple counters 9. Design and implementation of 3-bit synchronous up/down counter 10. Implementation of SISO, SIPO, PISO and PIPO shift registers using Flip- flops. 11. Design of expts 1, 6,8,10 using Verilog HDL.
II Yr/ECE/147351/DE/LM
Page No.
LIST OF EXPERIMENTS
1. Study of logic gates. 2. Design and implementation of adders and Subtractors using logic gates. 3. Design and implementation of code converters using logic gates. 4. Design and implementation of 4-bit binary adder/Subtractor and BCD adder using IC 7483. 5. Design and implementation of 2-bit magnitude comparator using logic gates, 8-bit magnitude comparator using IC 7485. 6. Design and implementation of 16-bit odd/even parity checker/ generator using IC 74180. 7. Design and implementation of multiplexer and demultiplexer using logic gates and study of IC 74150 and IC 74154. 8. Design and implementation of encoder and decoder using logic gates and study of IC 7445 and IC 74147. 9. Construction and verification of 4-bit ripple counter and Mod10/Mod-12 ripple counter. 10. 11. Design and implementation of 3-bit synchronous up/down counter. Implementation of SISO, SIPO, PISO and PIPO shift registers using flip-flops.
Page No.
EXPT NO. : 1 AND GATE: SYMBOL:
STUDY OF LOGIC GATES

PIN DIAGRAM:
OR GATE:
Page No.
NOT GATE: SYMBOL: PIN DIAGRAM:
X-OR GATE : SYMBOL : PIN DIAGRAM :
Page No.
2-INPUT NAND GATE: SYMBOL: PIN DIAGRAM:
3-INPUT NAND GATE :
Page No.
NOR GATE:
RESULT:
Page No.
EXPT.No: 2
DESIGN OF ADDER AND SUBTRACTOR
LOGIC DIAGRAM: HALF ADDER
TRUTH TABLE: A 0 0 1 1 B 0 1 0 1 CARRY 0 0 0 1 SUM 0 1 1 0
K-Map for SUM:
K-Map for CARRY:
SUM = AB + AB
CARRY = AB
II Yr/ECE/147351/DE/LM Page No. 7
LOGIC DIAGRAM: FULL ADDER USING TWO HALF ADDER
TRUTH TABLE: A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 CARRY 0 0 0 1 0 1 1 1 SUM 0 1 1 0 1 0 0 1
K-Map for SUM:
SUM = ABC + ABC + ABC + ABC
Page No.
K-Map for CARRY:
CARRY = AB + BC + AC LOGIC DIAGRAM: HALF SUBTRACTOR
TRUTH TABLE: A 0 0 1 1 B 0 1 0 1 BORROW DIFFERENCE 0 1 0 0 0 1 1 0
Page No.
K-Map for DIFFERENCE:
DIFFERENCE = AB + AB K-Map for BORROW:
BORROW = AB FULL SUBTRACTOR K-Map for Difference:
Difference = ABC + ABC + ABC + ABC K-Map for Borrow:
Borrow = AB + BC + AC
Page No. 10
LOGIC DIAGRAM: FULL SUBTRACTOR USING TWO HALF SUBTRACTOR:
TRUTH TABLE:
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
BORROW DIFFERENCE 0 1 1 1 0 0 0 1 0 1 1 0 1 0 0 1
RESULT:
Page No. 11
EXPT.No: 3 DESIGN AND IMPLEMENTATION OF CODE CONVERTOR
K-Map for G3:
G3 = B3 K-Map for G2:
Page No. 12
K-Map for G1:
K-Map for G0:
Page No. 13
LOGIC DIAGRAM: BINARY TO GRAY CODE CONVERTOR
TRUTH TABLE: | Binary input |

B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Gray code output
G3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
G2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0
G1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0
G0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
Page No. 14
LOGIC DIAGRAM: GRAY CODE TO BINARY CONVERTOR
TRUTH TABLE: | |
G3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 G2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 G1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 G0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Gray Code
Binary Code
Page No. 15
K-Map for B3:
B3 = G3 K-Map for B2:
Page No. 16
K-Map for B1:
K-Map for B0:
Page No. 17
LOGIC DIAGRAM: BCD TO EXCESS-3 CONVERTOR
TRUTH TABLE: | BCD input |

B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
|
G3 0 0 0 0 0 1 1 1 1 1 x x x x x x
Excess 3 output
G2 0 1 1 1 1 0 0 0 0 1 x x x x x x G1 1 0 0 1 1 0 0 1 1 0 x x x x x x G0 1 0 1 0 1 0 1 0 1 0 x x x x x x
Page No. 18
K-Map for E3:
E3 = B3 + B2 (B0 + B1)
K-Map for E2:
Page No. 19
K-Map for E1:
K-Map for E0:
Page No. 20
LOGIC DIAGRAM: EXCESS-3 TO BCD CONVERTOR
TRUTH TABLE: | | E3 0 0 0 0 0 1 1 1 1 1 Excess 3 Input | BCD Output
E2 0 1 1 1 1 0 0 0 0 1
E1 1 0 0 1 1 0 0 1 1 0
E0 1 0 1 0 1 0 1 0 1 0
B3 0 0 0 0 0 0 0 0 1 1
B2 0 0 0 0 1 1 1 1 0 0
B1 0 0 1 1 0 0 1 1 0 0
B0 0 1 0 1 0 1 0 1 0 1
Page No. 21
K-Map for A:
A = X1 X2 + X3 X4 X1 K-Map for B:
Page No. 22
K-Map for C:
K-Map for D:
RESULT:
Page No. 23
EXPT.No: 4
DESIGN OF 4-BIT ADDER AND SUBTRACTOR
PIN DIAGRAM FOR IC 7483:
LOGIC DIAGRAM: 4-BIT BINARY ADDER
Page No. 24
LOGIC DIAGRAM: 4-BIT BINARY SUBTRACTOR
LOGIC DIAGRAM: 4-BIT BINARY ADDER/SUBTRACTOR
Page No. 25
TURTH TABLE: Input Data A A 4 1 1 0 0 1 1 1 A 3 0 0 0 0 0 1 0 A 2 0 0 1 0 1 1 1 A 1 0 0 0 1 0 0 0 Input Data B B 4 0 1 1 0 1 1 1 B 3 0 0 0 1 0 1 1 B 2 1 0 0 1 1 1 0 B 1 0 0 0 1 1 1 1 C Addition S 4 1 0 1 1 0 1 0 S 3 0 0 0 0 0 0 1 S 2 1 0 1 0 1 1 1 S 1 0 0 0 0 0 0 1 B Subtraction D 4 0 0 1 1 1 1 1 D 3 1 0 0 0 1 1 1 D 2 1 0 1 1 1 1 0 D 1 0 0 0 0 1 1 1
0 1 0 0 1 1 1
1 1 0 0 0 0 0
K MAP
Y = S4 (S3 + S2)
Page No. 26
LOGIC DIAGRAM: BCD ADDER
TRUTH TABLE:
S4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BCD SUM S3 S2 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 S1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CARRY C 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
RESULT:
Page No. 27
EXPT.No: 5 DESIGN AND IMPLEMENTATION OF MAGNITUDE
COMPARATOR
LOGIC DIAGRAM: 2 BIT MAGNITUDE COMPARATOR
Page No. 28
TRUTH TABLE A1 A0 B1 B0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 K MAP for A>B A>B 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0 A=B 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 A<B 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 0
Page No. 29
K MAP for A< B
K MAP for A = B
Page No. 30
LOGIC DIAGRAM: 8 BIT MAGNITUDE COMPARATOR
TRUTH TABLE A B 0000 0000 0000 0000 0001 0001 0000 0000 0000 0000 0001 0001 RESULT:
A>B 0 1 0
A=B 1 0 0
A<B 0 0 1
Page No. 31
EXPT.No: 6 16 BIT ODD/EVEN PARITY CHECKER
/GENERATOR
FUNCTION TABLE: INPUTS Number of High Data Inputs (I0 I7) EVEN ODD EVEN ODD X X
PE 1 1 0 0 1 0
PO 0 0 1 1 1 0
OUTPUTS O E 1 0 0 1 0 1 0 1 1 0 0 1
Page No. 32
LOGIC DIAGRAM: 16 BIT ODD/EVEN PARITY CHECKER
TRUTH TABLE:
I7 I6 I5 I4 I3 I2 I1 I0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0
I7I6I5I4I3I211 I0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0
Active 1 0 1
E 1 1 0
O 0 0 1
Page No. 33
LOGIC DIAGRAM: 16 BIT ODD/EVEN PARITY GENERATOR
TRUTH TABLE: E 1 0 1 O 0 1 0
I7 I6 I5 I4 I3 I2 I1 I0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0
I7 I6 I5 I4 I3 I2 I1 I0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0
Active 1 0 0
RESULT:
Page No. 34
EXPT.No: 7 DESIGN AND IMPLEMENTATION OF
MULTIPLEXER AND DEMULTIPLEXER
BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:
FUNCTION TABLE:
S1 0 0 1 1
S0 0 1 0 1
INPUTS Y D0 D0 S1 S0 D1 D1 S1 S0 D2 D2 S1 S0 D3 D3 S1 S0
Y = D0 S1 S0 + D1 S1 S0 + D2 S1 S0 + D3 S1 S0
Page No. 35
CIRCUIT DIAGRAM FOR MULTIPLEXER:
TRUTH TABLE: S1 0 0 1 1 S0 0 1 0 1 Y = OUTPUT D0 D1 D2 D3
Page No. 36
BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:
FUNCTION TABLE:
S1 0 0 1 1
S0 0 1 0 1
INPUT X D0 = X S1 S0 X D1 = X S1 S0 X D2 = X S1 S0 X D3 = X S1 S0
Y = X S1 S0 + X S1 S0 + X S1 S0 + X S1 S0
Page No. 37
LOGIC DIAGRAM FOR DEMULTIPLEXER:
TRUTH TABLE: INPUT S1 0 0 0 0 1 1 1 1 S0 0 0 1 1 0 0 1 1 I/P 0 1 0 1 0 1 0 1 D0 0 1 0 0 0 0 0 0 OUTPUT D1 0 0 0 1 0 0 0 0 D2 0 0 0 0 0 1 0 0 D3 0 0 0 0 0 0 0 1
Page No. 38
RESULT:
Page No. 39
EXPT.No: 8 DESIGN AND IMPLEMENTATION OF ENCODER
AND DECODER PIN DIAGRAM FOR IC 7445: BCD TO DECIMAL DECODER:
Page No. 40
LOGIC DIAGRAM FOR ENCODER:
TRUTH TABLE: INPUT Y0 1 0 0 0 0 0 0 0 Y1 0 1 0 0 0 0 0 0 Y2 0 0 1 0 0 0 0 0 Y3 0 0 0 1 0 0 0 0 Y4 0 0 0 0 1 0 0 0 Y5 0 0 0 0 0 1 0 0 Y6 0 0 0 0 0 0 1 0 Y7 0 0 0 0 0 0 0 1 A 0 0 0 0 1 1 1 1 OUTPUT B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1
Page No. 41
LOGIC DIAGRAM FOR DECODER
TRUTH TABLE: INPUT E 1 0 0 0 0 RESULT: A 0 0 0 1 1 B 0 0 1 0 1 D0 1 0 1 1 1 OUTPUT D1 1 1 0 1 1 D2 1 1 1 0 1 D3 1 1 1 1 0
Page No. 42
EXPT.No: 9 CONSTRUCTION AND VERIFICATION OF 4 BIT
RIPPLE COUNTER AND MOD 10/MOD 12 RIPPLE COUNTER LOGIC DIAGRAM FOR 4 BIT RIPPLE UP COUNTER:
TRUTH TABLE: CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 QA 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 QB 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 QC 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 QD 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Page No. 43
Page No. 44
LOGIC DIAGRAM FOR 4 BIT RIPPLE DOWN COUNTER:
TRUTH TABLE: CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 QA 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 QB 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 QC 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 QD 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
Page No. 45
LOGIC DIAGRAM FOR MOD - 10 RIPPLE COUNTER:
TRUTH TABLE:
CLK 0 1 2 3 4 5 6 7 8 9 10
QA 0 1 0 1 0 1 0 1 0 1 0
QB 0 0 1 1 0 0 1 1 0 0 0
QC 0 0 0 0 1 1 1 1 0 0 0
QD 0 0 0 0 0 0 0 0 1 1 0
Page No. 46
LOGIC DIAGRAM FOR MOD - 12 RIPPLE COUNTER:
TRUTH TABLE: CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 RESULT: QA 0 1 0 1 0 1 0 1 0 1 0 1 0 QB 0 0 1 1 0 0 1 1 0 0 1 1 0 QC 0 0 0 0 1 1 1 1 0 0 0 0 0 QD 0 0 0 0 0 0 0 0 1 1 1 1 0
Page No. 47
DESIGN AND IMPLEMENTATION OF 3 BIT SYNCHRONOUS UP/DOWN COUNTER K MAP

EXPT.No: 10
STATE DIAGRAM:
Page No. 48
LOGIC DIAGRAM:
QA TRUTH TABLE:
Input 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 QA 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 QB 1 1 0 0 1 1 0 0 0 1 1 0 0 1 1
QB
QC
QC 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Page No. 49
CHARACTERISTICS TABLE: Q 0 0 1 1 Qt+1 0 1 0 1 J 0 1 X X K X X 1 0
RESULT:
Page No. 50
EXPT.No: 11
DESIGN AND IMPLEMENTATION OF SHIFT REGISTER
PIN DIAGRAM:
LOGIC DIAGRAM: SERIAL IN SERIAL OUT:
TRUTH TABLE:
CLK 1 2 3 4 5 6 7 Serial in 1 0 0 1 X X X Serial out 0 0 0 1 0 0 1
Page No. 51
LOGIC DIAGRAM:
SERIAL IN PARALLEL OUT:
TRUTH TABLE:
OUTPUT CLK DATA 0 1 2 3 4 0 1 0 0 1 QA 0 1 0 0 1 QB 0 0 1 0 0 QC 0 0 0 1 0 QD 0 0 0 1 1
Page No. 52
PARALLEL IN SERIAL OUT:
TRUTH TABLE: CLK 0 1 2 3 Q3 1 0 0 0 Q2 0 0 0 0 Q1 0 0 0 0 Q0 1 0 0 0 O/P 1 0 0 1
PARALLEL IN PARALLEL OUT:
TRUTH TABLE: DATA INPUT CLK 1 2 RESULT:

II Yr/ECE/147351/DE/LM Page No. 53
OUTPUT DD 1 0 QA 1 1 QB 0 0 QC 0 1 QD 1 0
DA 1 1
DB 0 0
DC 0 1
VERILOG HDL PROGRAM HALF ADDER module ha(a,b,sum,carry); input a,b; output sum,carry; assign sum=a^b; assign carry=a&b; endmodule FULL ADDER module fa(a,b,cin,sum,cout); input a,b,cin; output sum,cout; assign sum=a^b^cin; assign cout=cin&(a&b)|(a&b); endmodule HALF SUBTRACTOR module hs(a,b,d,bout); input a,b; output d,bout; assign d=a^b; assign bout=~a&b; endmodule FULL SUBTRACTOR module fs(a,b,bin,d,bout); input a,b,bin; output d,bout; assign sum=a^b^bin; assign bout=bin&(~(a&b))|(~a&b); endmodule MULTIPLEXER module mux(s0,s1,d0,d1,d2,d3); input s0,s1; output y; input d0,d1,d2,d3; assign y=(~s0&~s1&d0)|(~s0&s1&d1)|(s0&~s1&d2)|(s0&s1&d3); endmodule
Page No. 54
DEMULTIPLEXER module demux(din,s0,s1,d0,d1,d2.d3); input din,s0,s1; output d0,d1,d2,d3; assign d0=(~s0&~s1&din); assign d1=(~s0&s1&din); assign d2=(s0&~s1&din); assign d3=(s0&s1&din); endmodule
COUNTERS
RIPPLE UP COUNTER module upcounter(clk,clr,q); input clk,clr; output [3:0]q; reg [3:0]q; reg [3:0]count=4b0000; always @(clk) begin if(clk==1b1) if(clr==1b1) count=4b0001; else count=count+4b0001; q=count; end endmodule RIPPLE DOWN COUNTER module upcounter(clk,clr,q); input clk,clr; output [3:0]q; reg [3:0]q; reg [3:0]count=4b1111; always @(clk) begin if(clk==1b1) if(clr==1b1) count=4b1111; else count=count-4b0001; q=count; end endmodule
Page No. 55
RIPPLE MOD-10 COUNTER module mod10(clk,reset,q); input clk,reset; output [3:0]q; reg [3:0]q=4b0000; always @(clk) begin if(reset) q=4b0000; else q=q+4b0001; if(q==4b1010) q<=4b0000; end endmodule RIPPLE MOD-12 COUNTER module mod12(clk,reset,q); input clk,reset; output [3:0]q; reg [3:0]q=4b0000; always @(clk) begin if(reset) q=4b0000; else q=q+4b0001; if(q==4b1100) q<=4b0000; end endmodule
Page No. 56
SHIFT REGISTER
SERIAL IN SERIAL OUT module siso(d,q,clk); input d,clk; output q; wire q1,q2,q0; dff dout(q,q2,clk); dff dff2(q2,q1,clk); dff dff1(q1,q0,clk); dff dff0(q0,d,clk); end module module dff(q,d,clk) input d,clk; output q; reg q; aiways@(posedge clk) q<=d; endmodule SERIAL IN PARALLEL OUT module sipo(clk,rst,din,dout); input clk,rst,din; output [3:0]dout; reg [3:0]dout; reg[2:0]x; always@(posedge(clk) or posedge(rst)) begin if(rst==1b1) dout=1bz; else begin x={x[2:0],din}; dout=x; end end endmodule
Page No. 57
PARALLEL IN SERIAL OUT module piso(clk,rst,din,dout,load); input clk; input rst; input [3:0]din; input load; output dout; reg dout; reg [4:0]x; always@(clk,rst) begin if(rst==1b1) dout=1bz; else begin if(load==1b1) x=din; x={x[3:0],1bz}; dout=x[3]; end end endmodule
PARALLEL IN PARALLEL OUT module pipo(clk,rst,din,dout); input clk,rst; input[3:0],din; output [3:0]dout; reg [3:0]dout; always@(clk,rst,din) begin if(rst==1b1) dout=1bz; else dout=din; end endmodule
Page No. 58

De Lab Manual New

Hochgeladen von

Dokumentinformationen

Originalbeschreibung:

Copyright

Verfügbare Formate

Dieses Dokument teilen

Dokument teilen oder einbetten

Freigabeoptionen

Stufen Sie dieses Dokument als nützlich ein?

Sind diese Inhalte unangemessen?

Copyright:

Verfügbare Formate

De Lab Manual New

Hochgeladen von

Copyright:

Verfügbare Formate

147351 (DIGITAL ELECTRONICS) LAB MANUAL

EXPT NO. : 1 AND GATE: SYMBOL:

STUDY OF LOGIC GATES

NOT GATE: SYMBOL: PIN DIAGRAM:

X-OR GATE : SYMBOL : PIN DIAGRAM :

2-INPUT NAND GATE: SYMBOL: PIN DIAGRAM:

3-INPUT NAND GATE :

DESIGN OF ADDER AND SUBTRACTOR

LOGIC DIAGRAM: HALF ADDER

TRUTH TABLE: A 0 0 1 1 B 0 1 0 1 CARRY 0 0 0 1 SUM 0 1 1 0

K-Map for SUM:

K-Map for CARRY:

LOGIC DIAGRAM: FULL ADDER USING TWO HALF ADDER

TRUTH TABLE: A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 CARRY 0 0 0 1 0 1 1 1 SUM 0 1 1 0 1 0 0 1

K-Map for SUM:

SUM = ABC + ABC + ABC + ABC

K-Map for CARRY:

CARRY = AB + BC + AC LOGIC DIAGRAM: HALF SUBTRACTOR

TRUTH TABLE: A 0 0 1 1 B 0 1 0 1 BORROW DIFFERENCE 0 1 0 0 0 1 1 0

K-Map for DIFFERENCE:

DIFFERENCE = AB + AB K-Map for BORROW:

BORROW = AB FULL SUBTRACTOR K-Map for Difference:

Difference = ABC + ABC + ABC + ABC K-Map for Borrow:

LOGIC DIAGRAM: FULL SUBTRACTOR USING TWO HALF SUBTRACTOR:

EXPT.No: 3 DESIGN AND IMPLEMENTATION OF CODE CONVERTOR

K-Map for G3:

G3 = B3 K-Map for G2:

K-Map for G1:

K-Map for G0:

LOGIC DIAGRAM: BINARY TO GRAY CODE CONVERTOR

TRUTH TABLE: | Binary input |

Gray code output

LOGIC DIAGRAM: GRAY CODE TO BINARY CONVERTOR

K-Map for B3:

B3 = G3 K-Map for B2:

K-Map for B1:

K-Map for B0:

LOGIC DIAGRAM: BCD TO EXCESS-3 CONVERTOR

TRUTH TABLE: | BCD input |

K-Map for E3:

K-Map for E2:

K-Map for E1:

K-Map for E0:

LOGIC DIAGRAM: EXCESS-3 TO BCD CONVERTOR

TRUTH TABLE: | | E3 0 0 0 0 0 1 1 1 1 1 Excess 3 Input | BCD Output

DESIGN OF 4-BIT ADDER AND SUBTRACTOR

PIN DIAGRAM FOR IC 7483:

LOGIC DIAGRAM: 4-BIT BINARY ADDER

LOGIC DIAGRAM: 4-BIT BINARY SUBTRACTOR

LOGIC DIAGRAM: 4-BIT BINARY ADDER/SUBTRACTOR

LOGIC DIAGRAM: BCD ADDER

EXPT.No: 5 DESIGN AND IMPLEMENTATION OF MAGNITUDE

LOGIC DIAGRAM: 2 BIT MAGNITUDE COMPARATOR

TRUTH TABLE A1 A0 B1 B0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 K MAP for A>B A>B 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0 A=B 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 A<B 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 0

K MAP for A< B

PIN DIAGRAM FOR IC 7485:

LOGIC DIAGRAM: 8 BIT MAGNITUDE COMPARATOR

EXPT.No: 6 16 BIT ODD/EVEN PARITY CHECKER

PIN DIAGRAM FOR IC 74180:

LOGIC DIAGRAM: 16 BIT ODD/EVEN PARITY CHECKER

LOGIC DIAGRAM: 16 BIT ODD/EVEN PARITY GENERATOR

EXPT.No: 7 DESIGN AND IMPLEMENTATION OF

MULTIPLEXER AND DEMULTIPLEXER