Section 7.

1 Storage Components

Page 1 of 8

7. Storage Components 7.1 Registers

I3 D3 Clk Q3 I2 D2 Clk Q2 I1 D1 Clk Q1 I0 D0 Clk Q0

Clk Q3 Q2 Q1 Q0

4-bit register
I3 Preset D3
Preset

I2
Preset

I1
Preset

I0
Preset

Q3

D2

Q2

D1

Q1

D0

Q0

Clk
Clear Clear

Clk
Clear Clear

Clk
Clear Clear

Clk
Clear Clear

Clear Clk Q3 Q2 Q1 Q0

4-bit register with preset and clear

I3
1 s 0 y

I2
1 s 0 y

I1
1 s 0 y

I0
1 s 0 y

Load D3 Clk Q3 D2 Clk Q2 D1 Clk Q1 D0 Clk Q0

Clk Q3 Q2 Q1 Q0

4-bit register with parallel load

Section 7.1 Storage Components

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7.2
IL

Shift Registers
1 s 0 y 1 s 0 y 1 s 0 y 1 s 0 y

Shift D3 Clk Q3 D2 Clk Q2 D1 Clk Q1 D0 Clk Q0

Clk Q3 Q2 Q1 Q0

4-bit serial-in / parallel-out shift-right register

I3 IL IR
3 2 1 0 s1 s0 y 3 2 1 0 s1 s0 y 3 2 1 0 s1 s0 y 3 2 1 0 s1 s0 y

I2

I1

I0

S1 S0 D3 Clk Q'0 Clk Q3 Q2 Q1 Q0 Q3 D2 Clk Q'0 Q2 D1 Clk Q'0 Q1 D0 Clk Q'0 Q0

S1 S0 00 01 10 11

Operations no change load input shift left shift right

4-bit shift left/right register with parallel load

7.3
E C4

Counters
C3
HA HA

C2
HA

C1
HA

C0

D3 Clk
Clear

Q3

D2 Clk
Clear

Q2

D3 Clk
Clear

Q3

D0 Clk
Clear

Q0

Qi Ci Ci+1 Di 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0 Half Adder (HA)

Clear Clk Carry Q3 Q2 Q1 Q0

E 0 1

Operations no change count

4-bit binary counter

Section 7.1 Storage Components

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4-bit up/down binary counter E 1 1 1 1 1 1 1 1 D 0 0 0 0 1 1 1 1 Qi Ci Ci+1 Di Comment 0 0 0 0 0 1 0 1 adder: Qi + Ci = Di, and 1 0 0 1 Ci+1 is the carry. 1 1 1 0 0 0 0 0 0 1 1 1 0-1 = borrow 2-1 = 1 1 0 0 1 1 1 0 0 1-1 = 0 with no borrow Half Adder Subtractor (HAS) truth table
Ci +1 = D ' Qi Ci + DQ 'i Ci Di = D ' Q 'i C + D ' Qi C 'i + DQ 'i Ci + DQi C 'i = D ' (Qi C ) + D(Qi C ) = ( D '+ D )(Qi C ) = (Qi C )
D D' C i+ 1 D U Ci

HAS

Subtractor: Qi Ci = Di, and Ci+1 is the borrow.

Di

Q i Q' i

E D

D U

D U

D U

D U

HAS D3 Clk
Clear

HAS Q3 Q'3 D2 Clk

Clear

HAS Q2 Q'2 D1 Clk

Clear

HAS Q1 Q'1 D0 Clk

Clear

Q0 Q'0

Clear Clk Carry Q3 Q2 Q1 Q0

E 0 1 1 4-bit up/down counter with parallel load

I3 D E HAS
1 s 0 y 1 s

D X 0 1

Operations no change count up count down

I2

I1

I0

HAS
0 y 1 s

HAS
0 y 1 s

HAS
0 y

Load D0 Clk Q'0 Clk Carry Q3 Q2 Q1 Q0 Q0 D2 Clk Q'2 Q2 D1 Clk Q'1 Q1 D0 Clk Q'0 Q0

Load 0 0 0 1

E 0 1 1 X

D X 0 1 X

Operations no change count up count down load the input

Section 7.1 Storage Components

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7.4

BCD Counter
"1001" "0" "0" D E Load I3 "0" I2 "0" I1 "0" I0 D E Q0 Load I3 I2 I1 I0 1 "0000" 0

Selector

Up/down counter

Q3

Q2

Q1

Up/down counter

Q3

Q2

Q1

Q0

BCD up counter

BCD up/down counter

7.5

Asynchronous Counter

A counter without using an adder or subtractor. Achieved by toggling each flip-flop at half the frequency of the preceding flip-flop.

E T0 Clk Clear Clear Clk Q3 Q2 Q1 Q0 Q'3 Q3 T0 Clk Q' Clear 2 Q2 T0 Clk Clear Q'1 Q1 T0 Clk Q' Clear 0 Q0

4-bit asynchronous up counter

Section 7.1 Storage Components

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7.6

Register Files
Write Select n WA D0 Clk RFC Q0 Q'0 Read Select Output WE 2n Clk m O I m n RA

Input Clk

RF
x m

RE

Register file cell

I3 0 RFC RFC RFC RFC 0 1 WA1 WA0 2-to-4 read 2 decoder RFC RFC RFC RFC 2 3 RFC RFC RFC RFC 3 RFC RFC RFC RFC 1 I2 I1 I0

Graphic symbol

RA1 2-to-4 read decoder RA0

WE

RE

O3

O2

O1

O0

Register file with one write port and one read port
Write Select

Input Clk RFC

D0 Clk

Q0 Q'0 RS_A RS_B

OutA OutB

Register file cell with two read ports

Section 7.1 Storage Components

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7.7

Random-Access Memory (RAM)

Row select A n -1

Input

D C

Q Q'0

Output

A1 A0

RAM
2n x m O1O0

MC

CS Write I/Om -1

Write enable

Memory cell
0 MC MC MC MC

Graphic symbol

1 A1 A0 2-to-4 read 2 decoder MC MC MC MC MC MC MC MC

3 MC MC MC MC

Write CS

Write enable Read enable IO3 IO2 IO1 IO0

RAM

Section 7.1 Storage Components

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To obtain wider bit widths, we can connect several memory chips in parallel.
Input bus 32

14 A

D 0 - D7 A 0 - A13 CS M3 16K x 8 Write

D 0 - D7 A 0 - A13 CS M3 16K x 8 Write

D 0 - D7 A 0 - A13 CS M3 16K x 8 Write

D 0 - D7 A 0 - A13 CS M3 16K x 8 Write

CS Write

214 = 16384 = 16K = 0000 to 3FFF 16K x 32 RAM obtained by connecting in parallel four 16K x 8 RAMs.

Section 7.1 Storage Components

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To obtain a larger memory, we can connect several memory chips in series.

Data A Write b u s 2 14 12 A 1 2 -A 1 3 2-to-4 decoder 3 2 1 0 0000 - 0FFF 8

212 = 4096 = 4K = 000 to FFF

D 0- D 7 A 0 -A 1 1 CS M0 4K x 8 Write

A0 A11 00

Address 000 FFF

Bytes 4096

214 = 16384 = 16K = 0000 to 3FFF A12 A13 00 01 10 11 Address 0000 0FFF 1000 1FFF 2000 2FFF 3000 3FFF Bytes 4096 8192 12288 16384

D 0- D 7 A 0 -A 1 1 1000 - 1FFF CS M1 4K x 8 Write

D 0- D 7 A 0 -A 1 1 2000 - 2FFF CS M2 4K x 8 Write

D 0- D 7 A 0 -A 1 1 3000 - 3FFF CS M3 4K x 8 Write

16K x 8 RAM obtained by connecting in series four 4K x 8 RAMs.