LATCHUP AND LATCH UP PREVENTION TECHNIQUES

CMOS Structure

Definition
Latchup is defined as the generation of a low impedance path in CMOS chips between power supply rail and the ground rail due to the interaction of parasitic pnp and npn bipolar transistors. These BJTs form a (SCR) with positive feedback and virtually short circuit the power rail to ground, thus causing excessive current flows and even permanent device damage

Formation of SCR from BJT

CMOS - Latch up problem

Latch up triggering
For latch up to occur the parasitic npn-pnp circuit has to be triggered and the holding state has to be maintained. Latchup can be triggered by transient current or voltages that may occur internally to a chip during power-up or externally due to voltages or currents beyond normal operating ranges. Two possible triggering mechanisms are 1)lateral triggering 2)vertical triggering
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Lateral and vertical triggering

Current has to be injected into either the npnor pnp- emitter to initiate latch up. Lateral triggering occurs when a current flows in the emitter of the lateral npn-transistor . Vertical triggering occurs when a sufficient current is injected into the emitter of the vertical- pnp transistor.

Necessary conditions for latch up

Both PNP and NPN bi polars must be biased into the active state. The product of the parasitic bipolar transistor current gains (npn*pnp) is greater than or equal to one The terminal network must be capable of supplying a current greater than the holding current required by the PNPN path
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Latchup prevention techniques

Reducing the value of resistors and reducing the gain of the parasitic transistors are the basis for eliminating latch up. Substrate resistance: It can be reduced by the use of silicon starting- material with a thin epitaxial layer on top of highly doped substrate .

 Well resistance: It can be reduced by having retrograde well structure is also used. This well has a highly doped area at the bottom of the well, whereas the top of the well is more lightly doped.

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I/O latch up prevention

Reducing the gain of parasitic transistors is achieved through the use of guard rings. Guard rings are that p+ diffusions in the p substrate and n+ diffusions in the n-well to collect injected minority carriers

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p+ guard ring

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N+ Guard ring

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THANK YOU

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