Lab Assignment:3 Front end VLSI Design A]washing Machine Controller Using VHDL ---------------------------------------------------------------------------------- Company:Ikonic Edge Techno

Solutions -- Engineer: Navnath Chikhale --- Create Date: 20:19:53 08/02/2012 -- Design Name: -- Module Name: wash_mc - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: ---------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity wash_mc is Port ( clk,rst,start: in STD_LOGIC; s_load,m_load,lg_load : in STD_LOGIC; cold,norm,hot : in STD_LOGIC; cw_v,hw_v,dr_v,htr,fan : out STD_LOGIC; mot : out STD_LOGIC_VECTOR (2 downto 0); --blower,heater : out STD_LOGIC; gentle,normal,heavy,no_heat,low_heat,normal_heat,high_heat: in STD_L OGIC; d_nht,d_lht,d_hht : in STD_LOGIC); end wash_mc; architecture Behavioral of wash_mc is type typ_decl is (s0,load,temp,wait_20,w_cycle,d_cycle,motor,heater); signal state:typ_decl; signal signal signal signal count_20:integer range 0 to 5000000; s_load_sig:std_logic; m_load_sig:std_logic; lg_load_sig:std_logic;

signal gentle_sig:std_logic; signal normal_sig:std_logic; signal heavy_sig:std_logic; signal no_heat_sig:std_logic; signal low_heat_sig:std_logic;

signal normal_heat_sig:std_logic; signal high_heat_sig:std_logic; begin process(clk,rst) begin if(rst='1')then state<=s0; elsif(clk'event and clk='1')then case state is when s0=>if(start='1')then state<=load; else state<=s0; end if; when load=> if s_load='1' then s_load_sig<='1'; state<=temp; elsif(m_load='1')then m_load_sig<='1'; state<=temp; elsif(lg_load='1')then lg_load_sig<='1'; state<=temp; else state<=load; end if; when temp=> if(cold='1')then cw_v<='1'; ----fill with cold water for 20 sec time. state<=wait_20; elsif(norm='1')then cw_v<='1';hw_v<='1';--fi ll with half cold and half hot water. state<=wait_20; elsif(hot='1')then hw_v<='1';--fill with ho t water. state<=wait_20; else state<=temp; end if; when wait_20=> if(count_20=5 and s_load _sig='1')then --fill for small load for 5 sec only. cw_v<='0';hw_v<='0'; count_20<=0; state<=w_cycle; elsif(count_20=10 and m_ load_sig='1')then --fill for medium load for 10 sec only cw_v<='0';hw_v<='0'; count_20<=0; state<=w_cycle; elsif(count_20=20 and lg _load_sig='1')then --fill for larg load for 20 sec only cw_v<='0';hw_v<='0'; count_20<=0; state<=w_cycle;

else count_20<=count_20+1; state<=wait_20; end if; when w_cycle=> if(gentle='1')then gentle_sig<='1'; state<=d_cycle; elsif(normal='1')then normal_sig<='1'; state<=d_cycle; elsif(heavy='1')then heavy_sig<='1'; state<=d_cycle; else state<=w_cycle; end if; when d_cycle=> if(no_heat='1')then no_heat_sig<='1'; state<=motor; elsif(low_heat='1')then low_heat_sig<='1'; state<=motor; elsif(normal_heat='1')th en normal_heat_sig<='1'; state<=motor; elsif(high_heat='1')then high_heat_sig<='1'; state<=motor; else state<=d_cycle; end if; when motor=> if(gentle_sig='1')then mot<="001"; state<=heater; elsif(normal_sig='1')the n mot<="011"; state<=heater; elsif(heavy_sig='1')then mot<="101"; state<=heater; end if; when heater=> if(no_heat_sig='1')then htr<='0'; fan<='1'; state<=s0; elsif(low_heat='1')then htr<='1'; fan<='1'; state<=s0; elsif(normal_heat='1')th en htr<='1'; fan<='1';

state<=s0; elsif(high_heat='1')then htr<='1'; fan<='1'; state<=s0; else state<=d_cycle; end if; end case; end if; end process; end Behavioral;