The AVR Assembler Site

The AVR Assembler Site

HOME Welcome to AVR

RETRO_DAN Assembler Site
ASM FORUM
ASSEMBLY
ASM MATH LANGUAGE:
TUTORIAL #1
The Mnemonic
TUTORIAL #2
Representation of
TUTORIAL #3 Machine Code.
MATH 200
Assembly Language
MATH 200b remains in use
MATH 201 because of its close
relationship to the The AVR is a family of RISC
MATH 202
underlying machine. It microcontrollers from Atmel. The AVR
MATH 32X is used by those who architecture, first conceived by two
need to compress electronic engineering students at the
MATH YX
programs into the Norwegian Institute of Technology
DIV16 XX smallest memory (NTH), has been refined and developed
DIV 24 24 space and have it by Atmel Norway, in a division founded
excecute as fast and by the chip's architects.
DIV 3216 efficiently as possible.
FLOAT 128 It can be a difficult
medium in which to
SQRT16 work. Many can forget
MATH 202 that whether done by
man or compiler, all
MATH 202
computer languages
DEC ASCII must be translated
into machine code
INT ASCII
before they can run in
HX2ASC hardware. The AVR architects, Vergard Wollan and
AVG8 222 Alf-Egil Bogen. Bogen's 1992 NTH thesis
Submit New was titled: High Speed Analog to Digital
FFT7
Routines, Updates, Converters in CMOS.
COPY 102 Bug Reports to
LPM 108 AVR Assembler
Forum at: http://avr.x.
EPROM 100 am
SER EPROM
DFLASH AT45 Most high-level
languages for the AVR
FLASH CARD core accomplish this A RetroDan (HWMNBN) Site
VFX SMIL by translating
programs into
VFX MEM Assembler
SORT 220 Instructions first. The
resultant Assembler
CRC 236
Program is then
XMODEM REC converted to machine-
UART 304 code instructions. The
process may be
UART 305 automated and appear
UART 128 transparent to the
programmer. This is
UART BUFF how the C compilers
USB 232 work.
AVR ISP
THE TWO-PASS
ISP 2313 ASSEMBLER
ISP 1200
Since assembly
AVR SPI
language statements
I2C 300 have a one-to-one
I2C 302 correspondence with
binary instructions it
I2C TWI26 seems only logical to
I2C/TWI 128 simply translate
assembly instructions
I2C/TWI AT8 directly into binary
DALLAS-1W machine code, one-at-
a-time.
DALLAS CRC
ETHNET 8019 This method does not
TEA work due to forward
references and jumps
ADC 128 to lables that have not
ADC 10B been defined yet. This
is the reason most
ADC 400
assemblers are the
ADC 401 two-pass type.
THERM 232
The primary function
IRD 410 of pass-one is to build
LCD HD44 up a symbol table that
contain all the
LCD 2313
constants and labels
LCD44 2313 along with their
KBD 240 values.

MUX 242 The second-pass

KBD PS2 then uses this symbol
table to create the
KBD PC/128
binary machine code.
PS2 EMU
BOOT MG8
BOOT DR8
ALM CLK
CLOCK 8564 Programming the AVR
Microcontrollers in Machine
90 DAYS Language
DELAYS
CALL ID AVR
DTMF 314 << Prev | Ring Hub | Join | Rate| Next
PWM 6CH >>
PWM 10K © WebRing Inc. Search
ENCODE
STH-11
ATMEL CORP
Atmel AVR From Wikipedia, the
AVR free encyclopedia (Redirected
BUTTERFLY
from Avr) Jump to: navigation,
AVR BOOK
search The AVRs are a family of
RISC microcontrollers from Atmel.
Their internal architecture was
conceived by two students: Alf-
Egil Bogen and Vegard Wollan, at
the Norwegian Institute of
Technology (NTH] and further
developed at Atmel Norway, a
subsidiary founded by the two
architects. Atmel recently
released the Atmel AVR32 line of
microcontrollers. These are 32-bit
RISC devices featuring SIMD and
DSP instructions, along with
many additional features for audio
and video processing, intended to
compete with ARM based
processors. Note that the use of
"AVR" in this article refers to the
8-bit RISC line of Atmel AVR
Microcontrollers. The acronym
AVR has been reported to stand
for Advanced Virtual RISC. It's
also rumoured to stand for the
company's founders: Alf and
Vegard, who are evasive when
questioned about it. Contents
[hide] 1 Device Overview 1.1
Program Memory 1.2 Data
Memory and Registers 1.3
EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3
Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official
Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine
Language Development 6.4 C
Language Development 6.5 BASIC
& Other AVR Languages 6.6 AVR
Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The
AVR is a Harvard architecture
machine with programs and data
stored and addressed separately.
Flash, EEPROM, and SRAM are all
integrated onto a single die,
removing the need for external
memory (though still available on
some devices). [edit] Program
Memory Program instructions are
stored in semi-permanent Flash
memory. Each instruction for the
AVR line is either 16 or 32 bits in
length. The Flash memory is
addressed using 16 bit word
sizes. The size of the program
memory is indicated in the
naming of the device itself. For
instance, the ATmega64x line has
64Kbytes of Flash. Almost all AVR
devices are self-programmable.
[edit] Data Memory and Registers
The data address space consists
of the register file, I/O registers,
and SRAM. The AVRs have thirty-
two single-byte registers and are
classified as 8-bit RISC devices.
The working registers are mapped
in as the first thirty-two memory
spaces (000016-001F16) followed
by the 64 I/O registers (002016-
005F16). The actual usable RAM
starts after both these sections
(address 006016). (Note that the I/
O register space may be larger on
some more extensive devices, in
which case memory mapped I/O
registers will occupy a portion of
the SRAM.) Even though there are
separate addressing schemes and
optimized opcodes for register file
and I/O register access, all can
still be addressed and
manipulated as if they were in
SRAM. [edit] EEPROM Almost all
devices have on-die EEPROM.
This is most often used for long-
term parameter storage to be
retrieved even after cycling the
power of the device. [edit]
Program Execution Atmel's AVRs
have a single level pipeline
design. The next machine
instruction is fetched as the
current one is executing. Most
instructions take just one or two
clock cycles, making AVRs
relatively fast among the eight-bit
microcontrollers. The AVR family
of processors were designed for
the efficient execution of
compiled C code. The AVR
instruction set is more orthogonal
than most eight-bit
microcontrollers, however, it is
not completely regular: Pointer
registers X, Y, and Z have
addressing capabilities that are
different from each other. Register
locations R0 to R15 have different
addressing capabilities than
register locations R16 to R31. I/O
ports 0 to 31 have different
addressing capabilities than I/O
ports 32 to 63. CLR affects flags,
while SER does not, even though
they are complementary
instructions. CLR set all bits to
zero and SER sets them to one.
(Note though, that neither CLR
nor SER are native instructions.
Instead CLR is syntactic sugar for
[produces the same machine code
as] EOR R,R while SER is
syntactic sugar for LDI R,$FF.
Math operations such as EOR
modify flags while moves/loads/
stores/branches such as LDI do
not.) [edit] Speed The AVR line
can normally support clock
speeds from 0-16MHz, with some
devices reaching 20MHz. Lower
powered operation usually
requires a reduced clock speed.
All AVRs feature an on-chip
oscillator, removing the need for
external clocks or resonator
circuitry. Because many
operations on the AVR are single
cycle, the AVR can achieve up to
1MIPS per MHz. [edit]
Development AVRs have a large
following due to the free and
inexpensive development tools
available, including reasonably
priced development boards and
free development software. The
AVRs are marketed under various
names that share the same basic
core but with different peripheral
and memory combinations. Some
models (notably, the ATmega
range) have additional
instructions to make arithmetic
faster. Compatibility amongst
chips is fairly good. See external
links for sites relating to AVR
development. [edit] Features
Current AVRs offer a wide range
of features: RISC Core Running
Many Single Cycle Instructions
Multifunction, Bi-directional I/O
Ports with Internal, Configurable
Pull-up Resistors Multiple Internal
Oscillators Internal, Self-
Programmable Instruction Flash
Memory up to 256K In-System
Programmable using ICSP, JTAG,
or High Voltage methods Optional
Boot Code Section with
Independent Lock Bits for
Protection Internal Data EEPROM
up to 4KB Internal SRAM up to 8K
8-Bit and 16-Bit Timers PWM
Channels & dead time generator
Lighting (PWM Specific)
Controller models Dedicated I²C
Compatible Two-Wire Interface
(TWI) Synchronous/
Asynchronous Serial Peripherals
(UART/USART) (As used with RS-
232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN
Controller Support USB Controller
Support Proper High-speed
hardware & Hub controller with
embedded AVR. Also freely
available low-speed (HID)
software emulation Ethernet
Controller Support Universal
Serial Interface (USI) for Two or
Three-Wire Synchronous Data
Transfer Analog Comparators
LCD Controller Support 10-Bit A/D
Converters, with multiplex of up
to 16 channels Brownout
Detection Watchdog Timer (WDT)
Low-voltage Devices Operating
Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower
Devices Atmel AVR assembler
programming language Atmel
AVR machine programming
language Atmel AVR From
Wikipedia, the free encyclopedia
(Redirected from Avr) Jump to:
navigation, search The AVRs are a
family of RISC microcontrollers
from Atmel. Their internal
architecture was conceived by
two students: Alf-Egil Bogen and
Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and
further developed at Atmel
Norway, a subsidiary founded by
the two architects. Atmel recently
released the Atmel AVR32 line of
microcontrollers. These are 32-bit
RISC devices featuring SIMD and
DSP instructions, along with
many additional features for audio
and video processing, intended to
compete with ARM based
processors. Note that the use of
"AVR" in this article refers to the
8-bit RISC line of Atmel AVR
Microcontrollers. The acronym
AVR has been reported to stand
for Advanced Virtual RISC. It's
also rumoured to stand for the
company's founders: Alf and
Vegard, who are evasive when
questioned about it. Contents
[hide] 1 Device Overview 1.1
Program Memory 1.2 Data
Memory and Registers 1.3
EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3
Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official
Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine
Language Development 6.4 C
Language Development 6.5 BASIC
& Other AVR Languages 6.6 AVR
Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The
AVR is a Harvard architecture
machine with programs and data
stored and addressed separately.
Flash, EEPROM, and SRAM are all
integrated onto a single die,
removing the need for external
memory (though still available on
some devices). [edit] Program
Memory Program instructions are
stored in semi-permanent Flash
memory. Each instruction for the
AVR line is either 16 or 32 bits in
length. The Flash memory is
addressed using 16 bit word
sizes. The size of the program
memory is indicated in the
naming of the device itself. For
instance, the ATmega64x line has
64Kbytes of Flash. Almost all AVR
devices are self-programmable.
[edit] Data Memory and Registers
The data address space consists
of the register file, I/O registers,
and SRAM. The AVRs have thirty-
two single-byte registers and are
classified as 8-bit RISC devices.
The working registers are mapped
in as the first thirty-two memory
spaces (000016-001F16) followed
by the 64 I/O registers (002016-
005F16). The actual usable RAM
starts after both these sections
(address 006016). (Note that the I/
O register space may be larger on
some more extensive devices, in
which case memory mapped I/O
registers will occupy a portion of
the SRAM.) Even though there are
separate addressing schemes and
optimized opcodes for register file
and I/O register access, all can
still be addressed and
manipulated as if they were in
SRAM. [edit] EEPROM Almost all
devices have on-die EEPROM.
This is most often used for long-
term parameter storage to be
retrieved even after cycling the
power of the device. [edit]
Program Execution Atmel's AVRs
have a single level pipeline
design. The next machine
instruction is fetched as the
current one is executing. Most
instructions take just one or two
clock cycles, making AVRs
relatively fast among the eight-bit
microcontrollers. The AVR family
of processors were designed for
the efficient execution of
compiled C code. The AVR
instruction set is more orthogonal
than most eight-bit
microcontrollers, however, it is
not completely regular: Pointer
registers X, Y, and Z have
addressing capabilities that are
different from each other. Register
locations R0 to R15 have different
addressing capabilities than
register locations R16 to R31. I/O
ports 0 to 31 have different
addressing capabilities than I/O
ports 32 to 63. CLR affects flags,
while SER does not, even though
they are complementary
instructions. CLR set all bits to
zero and SER sets them to one.
(Note though, that neither CLR
nor SER are native instructions.
Instead CLR is syntactic sugar for
[produces the same machine code
as] EOR R,R while SER is
syntactic sugar for LDI R,$FF.
Math operations such as EOR
modify flags while moves/loads/
stores/branches such as LDI do
not.) [edit] Speed The AVR line
can normally support clock
speeds from 0-16MHz, with some
devices reaching 20MHz. Lower
powered operation usually
requires a reduced clock speed.
All AVRs feature an on-chip
oscillator, removing the need for
external clocks or resonator
circuitry. Because many
operations on the AVR are single
cycle, the AVR can achieve up to
1MIPS per MHz. [edit]
Development AVRs have a large
following due to the free and
inexpensive development tools
available, including reasonably
priced development boards and
free development software. The
AVRs are marketed under various
names that share the same basic
core but with different peripheral
and memory combinations. Some
models (notably, the ATmega
range) have additional
instructions to make arithmetic
faster. Compatibility amongst
chips is fairly good. See external
links for sites relating to AVR
development. [edit] Features
Current AVRs offer a wide range
of features: RISC Core Running
Many Single Cycle Instructions
Multifunction, Bi-directional I/O
Ports with Internal, Configurable
Pull-up Resistors Multiple Internal
Oscillators Internal, Self-
Programmable Instruction Flash
Memory up to 256K In-System
Programmable using ICSP, JTAG,
or High Voltage methods Optional
Boot Code Section with
Independent Lock Bits for
Protection Internal Data EEPROM
up to 4KB Internal SRAM up to 8K
8-Bit and 16-Bit Timers PWM
Channels & dead time generator
Lighting (PWM Specific)
Controller models Dedicated I²C
Compatible Two-Wire Interface
(TWI) Synchronous/
Asynchronous Serial Peripherals
(UART/USART) (As used with RS-
232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN
Controller Support USB Controller
Support Proper High-speed
hardware & Hub controller with
embedded AVR. Also freely
available low-speed (HID)
software emulation Ethernet
Controller Support Universal
Serial Interface (USI) for Two or
Three-Wire Synchronous Data
Transfer Analog Comparators
LCD Controller Support 10-Bit A/D
Converters, with multiplex of up
to 16 channels Brownout
Detection Watchdog Timer (WDT)
Low-voltage Devices Operating
Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower
Devices Atmel AVR assembler
programming language Atmel
AVR machine programming
language Atmel AVR From
Wikipedia, the free encyclopedia
(Redirected from Avr) Jump to:
navigation, search The AVRs are a
family of RISC microcontrollers
from Atmel. Their internal
http://avr-asm.tripod.com/ (1 of 2)1/20/2009 8:32:57 PM
The AVR Assembler Site

architecture was conceived by

two students: Alf-Egil Bogen and
Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and
further developed at Atmel
Norway, a subsidiary founded by
the two architects. Atmel recently
released the Atmel AVR32 line of
microcontrollers. These are 32-bit
RISC devices featuring SIMD and
DSP instructions, along with
many additional features for audio
and video processing, intended to
compete with ARM based
processors. Note that the use of
"AVR" in this article refers to the
8-bit RISC line of Atmel AVR
Microcontrollers. The acronym
AVR has been reported to stand
for Advanced Virtual RISC. It's
also rumoured to stand for the
company's founders: Alf and
Vegard, who are evasive when
questioned about it. Contents
[hide] 1 Device Overview 1.1
Program Memory 1.2 Data
Memory and Registers 1.3
EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3
Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official
Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine
Language Development 6.4 C
Language Development 6.5 BASIC
& Other AVR Languages 6.6 AVR
Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The
AVR is a Harvard architecture
machine with programs and data
stored and addressed separately.
Flash, EEPROM, and SRAM are all
integrated onto a single die,
removing the need for external
memory (though still available on
some devices). [edit] Program
Memory Program instructions are
stored in semi-permanent Flash
memory. Each instruction for the
AVR line is either 16 or 32 bits in
length. The Flash memory is
addressed using 16 bit word
sizes. The size of the program
memory is indicated in the
naming of the device itself. For
instance, the ATmega64x line has
64Kbytes of Flash. Almost all AVR
devices are self-programmable.
[edit] Data Memory and Registers
The data address space consists
of the register file, I/O registers,
and SRAM. The AVRs have thirty-
two single-byte registers and are
classified as 8-bit RISC devices.
The working registers are mapped
in as the first thirty-two memory
spaces (000016-001F16) followed
by the 64 I/O registers (002016-
005F16). The actual usable RAM
starts after both these sections
(address 006016). (Note that the I/
O register space may be larger on
some more extensive devices, in
which case memory mapped I/O
registers will occupy a portion of
the SRAM.) Even though there are
separate addressing schemes and
optimized opcodes for register file
and I/O register access, all can
still be addressed and
manipulated as if they were in
SRAM. [edit] EEPROM Almost all
devices have on-die EEPROM.
This is most often used for long-
term parameter storage to be
retrieved even after cycling the
power of the device. [edit]
Program Execution Atmel's AVRs
have a single level pipeline
design. The next machine
instruction is fetched as the
current one is executing. Most
instructions take just one or two
clock cycles, making AVRs
relatively fast among the eight-bit
microcontrollers. The AVR family
of processors were designed for
the efficient execution of
compiled C code. The AVR
instruction set is more orthogonal
than most eight-bit
microcontrollers, however, it is
not completely regular: Pointer
registers X, Y, and Z have
addressing capabilities that are
different from each other. Register
locations R0 to R15 have different
addressing capabilities than
register locations R16 to R31. I/O
ports 0 to 31 have different
addressing capabilities than I/O
ports 32 to 63. CLR affects flags,
while SER does not, even though
they are complementary
instructions. CLR set all bits to
zero and SER sets them to one.
(Note though, that neither CLR
nor SER are native instructions.
Instead CLR is syntactic sugar for
[produces the same machine code
as] EOR R,R while SER is
syntactic sugar for LDI R,$FF.
Math operations such as EOR
modify flags while moves/loads/
stores/branches such as LDI do
not.) [edit] Speed The AVR line
can normally support clock
speeds from 0-16MHz, with some
devices reaching 20MHz. Lower
powered operation usually
requires a reduced clock speed.
All AVRs feature an on-chip
oscillator, removing the need for
external clocks or resonator
circuitry. Because many
operations on the AVR are single
cycle, the AVR can achieve up to
1MIPS per MHz. [edit]
Development AVRs have a large
following due to the free and
inexpensive development tools
available, including reasonably
priced development boards and
free development software. The
AVRs are marketed under various
names that share the same basic
core but with different peripheral
and memory combinations. Some
models (notably, the ATmega
range) have additional
instructions to make arithmetic
faster. Compatibility amongst
chips is fairly good. See external
links for sites relating to AVR
development. [edit] Features
Current AVRs offer a wide range
of features: RISC Core Running
Many Single Cycle Instructions
Multifunction, Bi-directional I/O
Ports with Internal, Configurable
Pull-up Resistors Multiple Internal
Oscillators Internal, Self-
Programmable Instruction Flash
Memory up to 256K In-System
Programmable using ICSP, JTAG,
or High Voltage methods Optional
Boot Code Section with
Independent Lock Bits for
Protection Internal Data EEPROM
up to 4KB Internal SRAM up to 8K
8-Bit and 16-Bit Timers PWM
Channels & dead time generator
Lighting (PWM Specific)
Controller models Dedicated I²C
Compatible Two-Wire Interface
(TWI) Synchronous/
Asynchronous Serial Peripherals
(UART/USART) (As used with RS-
232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN
Controller Support USB Controller
Support Proper High-speed
hardware & Hub controller with
embedded AVR. Also freely
available low-speed (HID)
software emulation Ethernet
Controller Support Universal
Serial Interface (USI) for Two or
Three-Wire Synchronous Data
Transfer Analog Comparators
LCD Controller Support 10-Bit A/D
Converters, with multiplex of up
to 16 channels Brownout
Detection Watchdog Timer (WDT)
Low-voltage Devices Operating
Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower
Devices Atmel AVR assembler
programming language Atmel
AVR machine programming
language

http://avr-asm.tripod.com/ (2 of 2)1/20/2009 8:32:57 PM

The AVR Assembler Site

The AVR Assembler Site

HOME Welcome to AVR

RETRO_DAN Assembler Site
ASM FORUM
ASSEMBLY
ASM MATH LANGUAGE:
TUTORIAL #1
The Mnemonic
TUTORIAL #2
Representation of
TUTORIAL #3 Machine Code.
MATH 200
Assembly Language
MATH 200b remains in use
MATH 201 because of its close
relationship to the The AVR is a family of RISC
MATH 202
underlying machine. It microcontrollers from Atmel. The AVR
MATH 32X is used by those who architecture, first conceived by two
need to compress electronic engineering students at the
MATH YX
programs into the Norwegian Institute of Technology
DIV16 XX smallest memory (NTH), has been refined and developed
DIV 24 24 space and have it by Atmel Norway, in a division founded
excecute as fast and by the chip's architects.
DIV 3216 efficiently as possible.
FLOAT 128 It can be a difficult
medium in which to
SQRT16 work. Many can forget
MATH 202 that whether done by
man or compiler, all
MATH 202
computer languages
DEC ASCII must be translated
into machine code
INT ASCII
before they can run in
HX2ASC hardware. The AVR architects, Vergard Wollan and
AVG8 222 Alf-Egil Bogen. Bogen's 1992 NTH thesis
Submit New was titled: High Speed Analog to Digital
FFT7
Routines, Updates, Converters in CMOS.
COPY 102 Bug Reports to
LPM 108 AVR Assembler
Forum at: http://avr.x.
EPROM 100 am
SER EPROM
DFLASH AT45 Most high-level
languages for the AVR
FLASH CARD core accomplish this A RetroDan (HWMNBN) Site
VFX SMIL by translating
programs into
VFX MEM Assembler
SORT 220 Instructions first. The
resultant Assembler
CRC 236
Program is then
XMODEM REC converted to machine-
UART 304 code instructions. The
process may be
UART 305 automated and appear
UART 128 transparent to the
programmer. This is
UART BUFF how the C compilers
USB 232 work.
AVR ISP
THE TWO-PASS
ISP 2313 ASSEMBLER
ISP 1200
Since assembly
AVR SPI
language statements
I2C 300 have a one-to-one
I2C 302 correspondence with
binary instructions it
I2C TWI26 seems only logical to
I2C/TWI 128 simply translate
assembly instructions
I2C/TWI AT8 directly into binary
DALLAS-1W machine code, one-at-
a-time.
DALLAS CRC
ETHNET 8019 This method does not
TEA work due to forward
references and jumps
ADC 128 to lables that have not
ADC 10B been defined yet. This
is the reason most
ADC 400
assemblers are the
ADC 401 two-pass type.
THERM 232
The primary function
IRD 410 of pass-one is to build
LCD HD44 up a symbol table that
contain all the
LCD 2313
constants and labels
LCD44 2313 along with their
KBD 240 values.

MUX 242 The second-pass

KBD PS2 then uses this symbol
table to create the
KBD PC/128
binary machine code.
PS2 EMU
BOOT MG8
BOOT DR8
ALM CLK
CLOCK 8564 Programming the AVR
Microcontrollers in Machine
90 DAYS Language
DELAYS
CALL ID AVR
DTMF 314 << Prev | Ring Hub | Join | Rate| Next
PWM 6CH >>
PWM 10K © WebRing Inc. Search
ENCODE
STH-11
ATMEL CORP
Atmel AVR From Wikipedia, the
AVR free encyclopedia (Redirected
BUTTERFLY
from Avr) Jump to: navigation,
AVR BOOK
search The AVRs are a family of
RISC microcontrollers from Atmel.
Their internal architecture was
conceived by two students: Alf-
Egil Bogen and Vegard Wollan, at
the Norwegian Institute of
Technology (NTH] and further
developed at Atmel Norway, a
subsidiary founded by the two
architects. Atmel recently
released the Atmel AVR32 line of
microcontrollers. These are 32-bit
RISC devices featuring SIMD and
DSP instructions, along with
many additional features for audio
and video processing, intended to
compete with ARM based
processors. Note that the use of
"AVR" in this article refers to the
8-bit RISC line of Atmel AVR
Microcontrollers. The acronym
AVR has been reported to stand
for Advanced Virtual RISC. It's
also rumoured to stand for the
company's founders: Alf and
Vegard, who are evasive when
questioned about it. Contents
[hide] 1 Device Overview 1.1
Program Memory 1.2 Data
Memory and Registers 1.3
EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3
Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official
Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine
Language Development 6.4 C
Language Development 6.5 BASIC
& Other AVR Languages 6.6 AVR
Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The
AVR is a Harvard architecture
machine with programs and data
stored and addressed separately.
Flash, EEPROM, and SRAM are all
integrated onto a single die,
removing the need for external
memory (though still available on
some devices). [edit] Program
Memory Program instructions are
stored in semi-permanent Flash
memory. Each instruction for the
AVR line is either 16 or 32 bits in
length. The Flash memory is
addressed using 16 bit word
sizes. The size of the program
memory is indicated in the
naming of the device itself. For
instance, the ATmega64x line has
64Kbytes of Flash. Almost all AVR
devices are self-programmable.
[edit] Data Memory and Registers
The data address space consists
of the register file, I/O registers,
and SRAM. The AVRs have thirty-
two single-byte registers and are
classified as 8-bit RISC devices.
The working registers are mapped
in as the first thirty-two memory
spaces (000016-001F16) followed
by the 64 I/O registers (002016-
005F16). The actual usable RAM
starts after both these sections
(address 006016). (Note that the I/
O register space may be larger on
some more extensive devices, in
which case memory mapped I/O
registers will occupy a portion of
the SRAM.) Even though there are
separate addressing schemes and
optimized opcodes for register file
and I/O register access, all can
still be addressed and
manipulated as if they were in
SRAM. [edit] EEPROM Almost all
devices have on-die EEPROM.
This is most often used for long-
term parameter storage to be
retrieved even after cycling the
power of the device. [edit]
Program Execution Atmel's AVRs
have a single level pipeline
design. The next machine
instruction is fetched as the
current one is executing. Most
instructions take just one or two
clock cycles, making AVRs
relatively fast among the eight-bit
microcontrollers. The AVR family
of processors were designed for
the efficient execution of
compiled C code. The AVR
instruction set is more orthogonal
than most eight-bit
microcontrollers, however, it is
not completely regular: Pointer
registers X, Y, and Z have
addressing capabilities that are
different from each other. Register
locations R0 to R15 have different
addressing capabilities than
register locations R16 to R31. I/O
ports 0 to 31 have different
addressing capabilities than I/O
ports 32 to 63. CLR affects flags,
while SER does not, even though
they are complementary
instructions. CLR set all bits to
zero and SER sets them to one.
(Note though, that neither CLR
nor SER are native instructions.
Instead CLR is syntactic sugar for
[produces the same machine code
as] EOR R,R while SER is
syntactic sugar for LDI R,$FF.
Math operations such as EOR
modify flags while moves/loads/
stores/branches such as LDI do
not.) [edit] Speed The AVR line
can normally support clock
speeds from 0-16MHz, with some
devices reaching 20MHz. Lower
powered operation usually
requires a reduced clock speed.
All AVRs feature an on-chip
oscillator, removing the need for
external clocks or resonator
circuitry. Because many
operations on the AVR are single
cycle, the AVR can achieve up to
1MIPS per MHz. [edit]
Development AVRs have a large
following due to the free and
inexpensive development tools
available, including reasonably
priced development boards and
free development software. The
AVRs are marketed under various
names that share the same basic
core but with different peripheral
and memory combinations. Some
models (notably, the ATmega
range) have additional
instructions to make arithmetic
faster. Compatibility amongst
chips is fairly good. See external
links for sites relating to AVR
development. [edit] Features
Current AVRs offer a wide range
of features: RISC Core Running
Many Single Cycle Instructions
Multifunction, Bi-directional I/O
Ports with Internal, Configurable
Pull-up Resistors Multiple Internal
Oscillators Internal, Self-
Programmable Instruction Flash
Memory up to 256K In-System
Programmable using ICSP, JTAG,
or High Voltage methods Optional
Boot Code Section with
Independent Lock Bits for
Protection Internal Data EEPROM
up to 4KB Internal SRAM up to 8K
8-Bit and 16-Bit Timers PWM
Channels & dead time generator
Lighting (PWM Specific)
Controller models Dedicated I²C
Compatible Two-Wire Interface
(TWI) Synchronous/
Asynchronous Serial Peripherals
(UART/USART) (As used with RS-
232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN
Controller Support USB Controller
Support Proper High-speed
hardware & Hub controller with
embedded AVR. Also freely
available low-speed (HID)
software emulation Ethernet
Controller Support Universal
Serial Interface (USI) for Two or
Three-Wire Synchronous Data
Transfer Analog Comparators
LCD Controller Support 10-Bit A/D
Converters, with multiplex of up
to 16 channels Brownout
Detection Watchdog Timer (WDT)
Low-voltage Devices Operating
Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower
Devices Atmel AVR assembler
programming language Atmel
AVR machine programming
language Atmel AVR From
Wikipedia, the free encyclopedia
(Redirected from Avr) Jump to:
navigation, search The AVRs are a
family of RISC microcontrollers
from Atmel. Their internal
architecture was conceived by
two students: Alf-Egil Bogen and
Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and
further developed at Atmel
Norway, a subsidiary founded by
the two architects. Atmel recently
released the Atmel AVR32 line of
microcontrollers. These are 32-bit
RISC devices featuring SIMD and
DSP instructions, along with
many additional features for audio
and video processing, intended to
compete with ARM based
processors. Note that the use of
"AVR" in this article refers to the
8-bit RISC line of Atmel AVR
Microcontrollers. The acronym
AVR has been reported to stand
for Advanced Virtual RISC. It's
also rumoured to stand for the
company's founders: Alf and
Vegard, who are evasive when
questioned about it. Contents
[hide] 1 Device Overview 1.1
Program Memory 1.2 Data
Memory and Registers 1.3
EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3
Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official
Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine
Language Development 6.4 C
Language Development 6.5 BASIC
& Other AVR Languages 6.6 AVR
Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The
AVR is a Harvard architecture
machine with programs and data
stored and addressed separately.
Flash, EEPROM, and SRAM are all
integrated onto a single die,
removing the need for external
memory (though still available on
some devices). [edit] Program
Memory Program instructions are
stored in semi-permanent Flash
memory. Each instruction for the
AVR line is either 16 or 32 bits in
length. The Flash memory is
addressed using 16 bit word
sizes. The size of the program
memory is indicated in the
naming of the device itself. For
instance, the ATmega64x line has
64Kbytes of Flash. Almost all AVR
devices are self-programmable.
[edit] Data Memory and Registers
The data address space consists
of the register file, I/O registers,
and SRAM. The AVRs have thirty-
two single-byte registers and are
classified as 8-bit RISC devices.
The working registers are mapped
in as the first thirty-two memory
spaces (000016-001F16) followed
by the 64 I/O registers (002016-
005F16). The actual usable RAM
starts after both these sections
(address 006016). (Note that the I/
O register space may be larger on
some more extensive devices, in
which case memory mapped I/O
registers will occupy a portion of
the SRAM.) Even though there are
separate addressing schemes and
optimized opcodes for register file
and I/O register access, all can
still be addressed and
manipulated as if they were in
SRAM. [edit] EEPROM Almost all
devices have on-die EEPROM.
This is most often used for long-
term parameter storage to be
retrieved even after cycling the
power of the device. [edit]
Program Execution Atmel's AVRs
have a single level pipeline
design. The next machine
instruction is fetched as the
current one is executing. Most
instructions take just one or two
clock cycles, making AVRs
relatively fast among the eight-bit
microcontrollers. The AVR family
of processors were designed for
the efficient execution of
compiled C code. The AVR
instruction set is more orthogonal
than most eight-bit
microcontrollers, however, it is
not completely regular: Pointer
registers X, Y, and Z have
addressing capabilities that are
different from each other. Register
locations R0 to R15 have different
addressing capabilities than
register locations R16 to R31. I/O
ports 0 to 31 have different
addressing capabilities than I/O
ports 32 to 63. CLR affects flags,
while SER does not, even though
they are complementary
instructions. CLR set all bits to
zero and SER sets them to one.
(Note though, that neither CLR
nor SER are native instructions.
Instead CLR is syntactic sugar for
[produces the same machine code
as] EOR R,R while SER is
syntactic sugar for LDI R,$FF.
Math operations such as EOR
modify flags while moves/loads/
stores/branches such as LDI do
not.) [edit] Speed The AVR line
can normally support clock
speeds from 0-16MHz, with some
devices reaching 20MHz. Lower
powered operation usually
requires a reduced clock speed.
All AVRs feature an on-chip
oscillator, removing the need for
external clocks or resonator
circuitry. Because many
operations on the AVR are single
cycle, the AVR can achieve up to
1MIPS per MHz. [edit]
Development AVRs have a large
following due to the free and
inexpensive development tools
available, including reasonably
priced development boards and
free development software. The
AVRs are marketed under various
names that share the same basic
core but with different peripheral
and memory combinations. Some
models (notably, the ATmega
range) have additional
instructions to make arithmetic
faster. Compatibility amongst
chips is fairly good. See external
links for sites relating to AVR
development. [edit] Features
Current AVRs offer a wide range
of features: RISC Core Running
Many Single Cycle Instructions
Multifunction, Bi-directional I/O
Ports with Internal, Configurable
Pull-up Resistors Multiple Internal
Oscillators Internal, Self-
Programmable Instruction Flash
Memory up to 256K In-System
Programmable using ICSP, JTAG,
or High Voltage methods Optional
Boot Code Section with
Independent Lock Bits for
Protection Internal Data EEPROM
up to 4KB Internal SRAM up to 8K
8-Bit and 16-Bit Timers PWM
Channels & dead time generator
Lighting (PWM Specific)
Controller models Dedicated I²C
Compatible Two-Wire Interface
(TWI) Synchronous/
Asynchronous Serial Peripherals
(UART/USART) (As used with RS-
232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN
Controller Support USB Controller
Support Proper High-speed
hardware & Hub controller with
embedded AVR. Also freely
available low-speed (HID)
software emulation Ethernet
Controller Support Universal
Serial Interface (USI) for Two or
Three-Wire Synchronous Data
Transfer Analog Comparators
LCD Controller Support 10-Bit A/D
Converters, with multiplex of up
to 16 channels Brownout
Detection Watchdog Timer (WDT)
Low-voltage Devices Operating
Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower
Devices Atmel AVR assembler
programming language Atmel
AVR machine programming
language Atmel AVR From
Wikipedia, the free encyclopedia
(Redirected from Avr) Jump to:
navigation, search The AVRs are a
family of RISC microcontrollers
from Atmel. Their internal
http://avr-asm.tripod.com/index.html (1 of 2)1/20/2009 8:33:30 PM
The AVR Assembler Site

architecture was conceived by

two students: Alf-Egil Bogen and
Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and
further developed at Atmel
Norway, a subsidiary founded by
the two architects. Atmel recently
released the Atmel AVR32 line of
microcontrollers. These are 32-bit
RISC devices featuring SIMD and
DSP instructions, along with
many additional features for audio
and video processing, intended to
compete with ARM based
processors. Note that the use of
"AVR" in this article refers to the
8-bit RISC line of Atmel AVR
Microcontrollers. The acronym
AVR has been reported to stand
for Advanced Virtual RISC. It's
also rumoured to stand for the
company's founders: Alf and
Vegard, who are evasive when
questioned about it. Contents
[hide] 1 Device Overview 1.1
Program Memory 1.2 Data
Memory and Registers 1.3
EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3
Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official
Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine
Language Development 6.4 C
Language Development 6.5 BASIC
& Other AVR Languages 6.6 AVR
Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The
AVR is a Harvard architecture
machine with programs and data
stored and addressed separately.
Flash, EEPROM, and SRAM are all
integrated onto a single die,
removing the need for external
memory (though still available on
some devices). [edit] Program
Memory Program instructions are
stored in semi-permanent Flash
memory. Each instruction for the
AVR line is either 16 or 32 bits in
length. The Flash memory is
addressed using 16 bit word
sizes. The size of the program
memory is indicated in the
naming of the device itself. For
instance, the ATmega64x line has
64Kbytes of Flash. Almost all AVR
devices are self-programmable.
[edit] Data Memory and Registers
The data address space consists
of the register file, I/O registers,
and SRAM. The AVRs have thirty-
two single-byte registers and are
classified as 8-bit RISC devices.
The working registers are mapped
in as the first thirty-two memory
spaces (000016-001F16) followed
by the 64 I/O registers (002016-
005F16). The actual usable RAM
starts after both these sections
(address 006016). (Note that the I/
O register space may be larger on
some more extensive devices, in
which case memory mapped I/O
registers will occupy a portion of
the SRAM.) Even though there are
separate addressing schemes and
optimized opcodes for register file
and I/O register access, all can
still be addressed and
manipulated as if they were in
SRAM. [edit] EEPROM Almost all
devices have on-die EEPROM.
This is most often used for long-
term parameter storage to be
retrieved even after cycling the
power of the device. [edit]
Program Execution Atmel's AVRs
have a single level pipeline
design. The next machine
instruction is fetched as the
current one is executing. Most
instructions take just one or two
clock cycles, making AVRs
relatively fast among the eight-bit
microcontrollers. The AVR family
of processors were designed for
the efficient execution of
compiled C code. The AVR
instruction set is more orthogonal
than most eight-bit
microcontrollers, however, it is
not completely regular: Pointer
registers X, Y, and Z have
addressing capabilities that are
different from each other. Register
locations R0 to R15 have different
addressing capabilities than
register locations R16 to R31. I/O
ports 0 to 31 have different
addressing capabilities than I/O
ports 32 to 63. CLR affects flags,
while SER does not, even though
they are complementary
instructions. CLR set all bits to
zero and SER sets them to one.
(Note though, that neither CLR
nor SER are native instructions.
Instead CLR is syntactic sugar for
[produces the same machine code
as] EOR R,R while SER is
syntactic sugar for LDI R,$FF.
Math operations such as EOR
modify flags while moves/loads/
stores/branches such as LDI do
not.) [edit] Speed The AVR line
can normally support clock
speeds from 0-16MHz, with some
devices reaching 20MHz. Lower
powered operation usually
requires a reduced clock speed.
All AVRs feature an on-chip
oscillator, removing the need for
external clocks or resonator
circuitry. Because many
operations on the AVR are single
cycle, the AVR can achieve up to
1MIPS per MHz. [edit]
Development AVRs have a large
following due to the free and
inexpensive development tools
available, including reasonably
priced development boards and
free development software. The
AVRs are marketed under various
names that share the same basic
core but with different peripheral
and memory combinations. Some
models (notably, the ATmega
range) have additional
instructions to make arithmetic
faster. Compatibility amongst
chips is fairly good. See external
links for sites relating to AVR
development. [edit] Features
Current AVRs offer a wide range
of features: RISC Core Running
Many Single Cycle Instructions
Multifunction, Bi-directional I/O
Ports with Internal, Configurable
Pull-up Resistors Multiple Internal
Oscillators Internal, Self-
Programmable Instruction Flash
Memory up to 256K In-System
Programmable using ICSP, JTAG,
or High Voltage methods Optional
Boot Code Section with
Independent Lock Bits for
Protection Internal Data EEPROM
up to 4KB Internal SRAM up to 8K
8-Bit and 16-Bit Timers PWM
Channels & dead time generator
Lighting (PWM Specific)
Controller models Dedicated I²C
Compatible Two-Wire Interface
(TWI) Synchronous/
Asynchronous Serial Peripherals
(UART/USART) (As used with RS-
232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN
Controller Support USB Controller
Support Proper High-speed
hardware & Hub controller with
embedded AVR. Also freely
available low-speed (HID)
software emulation Ethernet
Controller Support Universal
Serial Interface (USI) for Two or
Three-Wire Synchronous Data
Transfer Analog Comparators
LCD Controller Support 10-Bit A/D
Converters, with multiplex of up
to 16 channels Brownout
Detection Watchdog Timer (WDT)
Low-voltage Devices Operating
Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower
Devices Atmel AVR assembler
programming language Atmel
AVR machine programming
language

http://avr-asm.tripod.com/index.html (2 of 2)1/20/2009 8:33:30 PM

MULTIPLY & DIVIDE (AVR 200)

The AVR Assembler Site

MULTIPLY & DIVIDE (AVR 200)

HOME
RETRO_DAN
;**** A P P L I C A T I O N N O T E A V R 2 0 0
ASM FORUM ************************
ASM MATH ;*
;* Title: Multiply and Divide Routines
TUTORIAL #1
;* Version: 1.1
TUTORIAL #2 ;* Last updated: 97.07.04
TUTORIAL #3 ;* Target: AT90Sxxxx (All AVR Devices)
;*
MATH 200 ;* Support E-mail: avr@atmel.com
MATH 200b ;* ;* DESCRIPTION
;* This Application Note lists subroutines for the following
MATH 201 ;* Muliply/Divide applications:
MATH 202 ;*
;* 8x8 bit unsigned
MATH 32X ;* 8x8 bit signed
MATH YX ;* 16x16 bit unsigned
;* 16x16 bit signed
DIV16 XX
;* 8/8 bit unsigned
DIV 24 24 ;* 8/8 bit signed
DIV 3216 ;* 16/16 bit unsigned
;* 16/16 bit signed
FLOAT 128 ;*
SQRT16 ;* All routines are Code Size optimized implementations
;*;
MATH 202 ***************************************************************************
MATH 202 .include "1200def.inc"
DEC ASCII
rjmp RESET ;reset handle
INT ASCII
HX2ASC
;
AVG8 222 ***************************************************************************
FFT7 ;*
;* "mpy8u" - 8x8 Bit Unsigned Multiplication
COPY 102 ;*
LPM 108 ;* This subroutine multiplies the two register variables mp8u
and mc8u.
EPROM 100 ;* The result is placed in registers m8uH, m8uL
SER EPROM ;*
;* Number of words :9 + return
DFLASH AT45
;* Number of cycles :58 + return
FLASH CARD ;* Low registers used :None
;* High registers used :4 (mp8u,mc8u/m8uL,m8uH,mcnt8u)
VFX SMIL
;*
VFX MEM ;* Note: Result Low byte and the multiplier share the same
SORT 220 register.
;* This causes the multiplier to be overwritten by the result.
CRC 236 ;*
XMODEM REC ;
***************************************************************************
UART 304
UART 305 ;***** Subroutine Register Variables
UART 128
.def mc8u =r16 ;multiplicand
UART BUFF .def mp8u =r17 ;multiplier
.def m8uL =r17 ;result Low byte
USB 232
.def m8uH =r18 ;result High byte
AVR ISP .def mcnt8u =r19 ;loop counter
ISP 2313
;***** Code
ISP 1200
AVR SPI
mpy8u: clr m8uH ;clear result High byte
I2C 300 ldi mcnt8u,8 ;init loop counter
I2C 302 lsr mp8u ;rotate multiplier
I2C TWI26
m8u_1: brcc m8u_2 ;carry set
I2C/TWI 128 add m8uH,mc8u ; add multiplicand to result High
I2C/TWI AT8 byte
m8u_2: ror m8uH ;rotate right result High
DALLAS-1W byte
DALLAS CRC ror m8uL ;rotate right result L byte and
multiplier
ETHNET 8019 dec mcnt8u ;decrement loop counter
TEA brne m8u_1 ;if not done, loop more
ret
ADC 128
ADC 10B
ADC 400
ADC 401 ;
THERM 232 ***************************************************************************
;*
IRD 410 ;* "mpy8s" - 8x8 Bit Signed Multiplication
LCD HD44 ;*
;* This subroutine multiplies signed the two register variables
LCD 2313 mp8s and
LCD44 2313 ;* mc8s. The result is placed in registers m8sH, m8sL
;* The routine is an implementation of Booth's algorithm. If
KBD 240 all 16 bits
MUX 242 ;* in the result are needed, avoid calling the routine with
;* -128 ($80) as multiplicand
KBD PS2
;*
KBD PC/128 ;* Number of words :10 + return
PS2 EMU ;* Number of cycles :73 + return
;* Low registers used :None
BOOT MG8 ;* High registers used :4 (mc8s,mp8s/m8sL,m8sH,mcnt8s)
BOOT DR8 ;*
;
ALM CLK ***************************************************************************
CLOCK 8564
;***** Subroutine Register Variables
90 DAYS
DELAYS .def mc8s =r16 ;multiplicand
.def mp8s =r17 ;multiplier
CALL ID
.def m8sL =r17 ;result Low byte
DTMF 314 .def m8sH =r18 ;result High byte
PWM 6CH .def mcnt8s =r19 ;loop counter

PWM 10K ;***** Code

ENCODE
mpy8s: sub m8sH,m8sH ;clear result High byte and
STH-11 carry
ATMEL CORP ldi mcnt8s,8 ;init loop counter
m8s_1: brcc m8s_2 ;if carry (previous bit) set
AVR
add m8sH,mc8s ; add multiplicand to result
BUTTERFLY High byte
AVR BOOK m8s_2: sbrc mp8s,0 ;if current bit set
sub m8sH,mc8s ; subtract multiplicand from
result High
asr m8sH ;shift right result High byte
ror m8sL ;shift right result L byte and
multiplier
dec mcnt8s ;decrement loop counter
brne m8s_1 ;if not done, loop more
ret

;
***************************************************************************
;*
;* "mpy16u" - 16x16 Bit Unsigned Multiplication
;*
;* This subroutine multiplies the two 16-bit register variables
;* mp16uH:mp16uL and mc16uH:mc16uL.
;* The result is placed in m16u3:m16u2:m16u1:m16u0.
;*
;* Number of words :14 + return
;* Number of cycles :153 + return
;* Low registers used :None
;* High registers used :7 (mp16uL,mp16uH,mc16uL/m16u0,mc16uH/
m16u1,m16u2,
;* m16u3,mcnt16u)
;*
;
***************************************************************************

;***** Subroutine Register Variables

.def mc16uL =r16 ;multiplicand low byte

.def mc16uH =r17 ;multiplicand high byte
.def mp16uL =r18 ;multiplier low byte
.def mp16uH =r19 ;multiplier high byte
.def m16u0 =r18 ;result byte 0 (LSB)
.def m16u1 =r19 ;result byte 1
.def m16u2 =r20 ;result byte 2
.def m16u3 =r21 ;result byte 3 (MSB)
.def mcnt16u =r22 ;loop counter

;***** Code

mpy16u: clr m16u3 ;clear 2 highest bytes of

result
clr m16u2
ldi mcnt16u,16 ;init loop counter
lsr mp16uH
ror mp16uL

m16u_1: brcc noad8 ;if bit 0 of multiplier set

add m16u2,mc16uL ;add multiplicand Low to byte 2 of
res
adc m16u3,mc16uH ;add multiplicand high to byte 3 of
res
noad8: ror m16u3 ;shift right result byte 3
ror m16u2 ;rotate right result byte 2
ror m16u1 ;rotate result byte 1 and
multiplier High
ror m16u0 ;rotate result byte 0 and
multiplier Low
dec mcnt16u ;decrement loop counter
brne m16u_1 ;if not done, loop more
ret

;
***************************************************************************
;*
;* "mpy16s" - 16x16 Bit Signed Multiplication
;*
;* This subroutine multiplies signed the two 16-bit register
variables
;* mp16sH:mp16sL and mc16sH:mc16sL.
;* The result is placed in m16s3:m16s2:m16s1:m16s0.
;* The routine is an implementation of Booth's algorithm. If
all 32 bits
;* in the result are needed, avoid calling the routine with
;* -32768 ($8000) as multiplicand
;*
;* Number of words :16 + return
;* Number of cycles :210/226 (Min/Max) + return
;* Low registers used :None
;* High registers used :7 (mp16sL,mp16sH,mc16sL/m16s0,mc16sH/
m16s1,
;* m16s2,m16s3,mcnt16s)
;*
;
***************************************************************************

;***** Subroutine Register Variables

.def mc16sL =r16 ;multiplicand low byte

.def mc16sH =r17 ;multiplicand high byte
.def mp16sL =r18 ;multiplier low byte
.def mp16sH =r19 ;multiplier high byte
.def m16s0 =r18 ;result byte 0 (LSB)
.def m16s1 =r19 ;result byte 1
.def m16s2 =r20 ;result byte 2
.def m16s3 =r21 ;result byte 3 (MSB)
.def mcnt16s =r22 ;loop counter

;***** Code
mpy16s: clr m16s3 ;clear result byte 3
sub m16s2,m16s2 ;clear result byte 2 and carry
ldi mcnt16s,16 ;init loop counter
m16s_1: brcc m16s_2 ;if carry (previous bit) set
add m16s2,mc16sL ; add multiplicand Low to result
byte 2
adc m16s3,mc16sH ; add multiplicand High to
result byte 3
m16s_2: sbrc mp16sL,0 ;if current bit set
sub m16s2,mc16sL ; sub multiplicand Low from
result byte 2
sbrc mp16sL,0 ;if current bit set
sbc m16s3,mc16sH ; sub multiplicand High from
result byte 3
asr m16s3 ;shift right result and multiplier
ror m16s2
ror m16s1
ror m16s0
dec mcnt16s ;decrement counter
brne m16s_1 ;if not done, loop more
ret

;
***************************************************************************
;*
;* "div8u" - 8/8 Bit Unsigned Division
;*
;* This subroutine divides the two register variables
"dd8u" (dividend) and
;* "dv8u" (divisor). The result is placed in "dres8u" and the
remainder in
;* "drem8u".
;*
;* Number of words :14
;* Number of cycles :97
;* Low registers used :1 (drem8u)
;* High registers used :3 (dres8u/dd8u,dv8u,dcnt8u)
;*
;
***************************************************************************

;***** Subroutine Register Variables

.def drem8u =r15 ;remainder

.def dres8u =r16 ;result
.def dd8u =r16 ;dividend
.def dv8u =r17 ;divisor
.def dcnt8u =r18 ;loop counter

;***** Code

div8u: sub drem8u,drem8u ;clear remainder and carry

ldi dcnt8u,9 ;init loop counter
d8u_1: rol dd8u ;shift left dividend
dec dcnt8u ;decrement counter
brne d8u_2 ;if done
ret ; return
d8u_2: rol drem8u ;shift dividend into
remainder
sub drem8u,dv8u ;remainder = remainder - divisor
brcc d8u_3 ;if result negative
add drem8u,dv8u ; restore remainder
clc ; clear carry to be shifted into
result
rjmp d8u_1 ;else
d8u_3: sec ; set carry to be
shifted into result
rjmp d8u_1

;
***************************************************************************
;*
;* "div8s" - 8/8 Bit Signed Division
;*
;* This subroutine divides the two register variables
"dd8s" (dividend) and
;* "dv8s" (divisor). The result is placed in "dres8s" and the
remainder in
;* "drem8s".
;*
;* Number of words :27
;* Number of cycles :107/108
;* Low registers used :2 (d8s,drem8s)
;* High registers used :3 (dres8s/dd8s,dv8s,dcnt8s)
;*
;
***************************************************************************

;***** Subroutine Register Variables

.def d8s =r14 ;sign register

.def drem8s =r15 ;remainder
.def dres8s =r16 ;result
.def dd8s =r16 ;dividend
.def dv8s =r17 ;divisor
.def dcnt8s =r18 ;loop counter

;***** Code

div8s: mov d8s,dd8s ;move dividend to sign

register
eor d8s,dv8s ;xor sign with divisor

sbrc dv8s,7 ;if MSB of divisor set

neg dv8s ; change sign of divisor
sbrc dd8s,7 ;if MSB of dividend set
neg dd8s ; change sign of divisor
sub drem8s,drem8s ;clear remainder and carry
ldi dcnt8s,9 ;init loop counter
d8s_1: rol dd8s ;shift left dividend
dec dcnt8s ;decrement counter
brne d8s_2 ;if done
sbrc d8s,7 ; if MSB of sign register set
neg dres8s ; change sign of result

ret ; return
d8s_2: rol drem8s ;shift dividend into
remainder
sub drem8u,dv8s ;remainder = remainder - divisor
brcc d8s_3 ;if result negative
add drem8u,dv8s ; restore remainder
clc ; clear carry to be shifted into
result
rjmp d8s_1 ;else
d8s_3: sec ; set carry to be
shifted into result
rjmp d8s_1

;
***************************************************************************
;*
;* "div16u" - 16/16 Bit Unsigned Division
;*
;* This subroutine divides the two 16-bit numbers
;* "dd8uH:dd8uL" (dividend) and "dv16uH:dv16uL" (divisor).
;* The result is placed in "dres16uH:dres16uL" and the
remainder in
;* "drem16uH:drem16uL".
;*
;* Number of words :19
;* Number of cycles :235/251 (Min/Max)
;* Low registers used :2 (drem16uL,drem16uH)
;* High registers used :5 (dres16uL/dd16uL,dres16uH/dd16uH,
dv16uL,dv16uH,
;* dcnt16u)
;*
;
***************************************************************************

;***** Subroutine Register Variables

.def drem16uL=r14
.def drem16uH=r15
.def dres16uL=r16
.def dres16uH=r17
.def dd16uL =r16
.def dd16uH =r17
.def dv16uL =r18
.def dv16uH =r19
.def dcnt16u =r20

;***** Code

div16u: clr drem16uL ;clear remainder Low byte

sub drem16uH,drem16uH;clear remainder High byte and
carry
ldi dcnt16u,17 ;init loop counter
d16u_1: rol dd16uL ;shift left dividend
rol dd16uH
dec dcnt16u ;decrement counter
brne d16u_2 ;if done
ret ; return
d16u_2: rol drem16uL ;shift dividend into
remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_3 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into
result
rjmp d16u_1 ;else
d16u_3: sec ; set carry to be
shifted into result
rjmp d16u_1

;
***************************************************************************
;*
;* "div16s" - 16/16 Bit Signed Division
;*
;* This subroutine divides signed the two 16 bit numbers
;* "dd16sH:dd16sL" (dividend) and "dv16sH:dv16sL" (divisor).
;* The result is placed in "dres16sH:dres16sL" and the
remainder in
;* "drem16sH:drem16sL".
;*
;* Number of words :45
;* Number of cycles :252/268 (Min/Max)
;* Low registers used :3 (d16s,drem16sL,drem16sH)
;* High registers used :7 (dres16sL/dd16sL,dres16sH/dd16sH,
dv16sL,dv16sH,
;*
;
***************************************************************************

;***** Subroutine Register Variables

.def d16s =r13 ;sign register

.def drem16sL=r14 ;remainder low
byte
.def drem16sH=r15 ;remainder high byte
.def dres16sL=r16 ;result low byte
.def dres16sH=r17 ;result high byte
.def dd16sL =r16 ;dividend low byte
.def dd16sH =r17 ;dividend high byte
.def dv16sL =r18 ;divisor low byte
.def dv16sH =r19 ;divisor high byte
.def dcnt16s =r20 ;loop counter

;***** Code

div16s: mov d16s,dd16sH ;move dividend High to sign

register
eor d16s,dv16sH ;xor divisor High with sign register

sbrs dd16sH,7 ;if MSB in dividend set

rjmp d16s_1
com dd16sH ; change sign of dividend
com dd16sL
subi dd16sL,low(-1)
sbci dd16sL,high(-1)
d16s_1: sbrs dv16sH,7 ;if MSB in divisor set
rjmp d16s_2
com dv16sH ; change sign of divisor
com dv16sL
subi dv16sL,low(-1)
sbci dv16sL,high(-1)
d16s_2: clr drem16sL ;clear remainder Low byte
sub drem16sH,drem16sH;clear remainder High byte and
carry
ldi dcnt16s,17 ;init loop counter

d16s_3: rol dd16sL ;shift left dividend

rol dd16sH
dec dcnt16s ;decrement counter
brne d16s_5 ;if done
sbrs d16s,7 ; if MSB in sign register set
rjmp d16s_4
com dres16sH ; change sign of result
com dres16sL
subi dres16sL,low(-1)
sbci dres16sH,high(-1)

d16s_4:
ret ; return
d16s_5: rol drem16sL ;shift dividend into
remainder
rol drem16sH
sub drem16sL,dv16sL ;remainder = remainder - divisor
sbc drem16sH,dv16sH ;
brcc d16s_6 ;if result negative
add drem16sL,dv16sL ; restore remainder
adc drem16sH,dv16sH
clc ; clear carry to be shifted into
result
rjmp d16s_3 ;else
d16s_6: sec ; set carry to be
shifted into result
rjmp d16s_3

;
****************************************************************************
;*
;* Test Program
;*
;* This program calls all the subroutines as an example of
usage and to
;* verify correct verification.
;*
;
****************************************************************************

;***** Main Program Register variables

.def temp =r16 ;temporary storage variable

;***** Code
RESET:
;---------------------------------------------------------------
;Include these lines for devices with SRAM
; ldi temp,low(RAMEND)
; out SPL,temp
; ldi temp,high(RAMEND)
; out SPH,temp ;init Stack Pointer
;---------------------------------------------------------------

;***** Multiply Two Unsigned 8-Bit Numbers (250 * 4)

ldi mc8u,250
ldi mp8u,4
rcall mpy8u ;result: m8uH:m8uL = $03e8 (1000)

;***** Multiply Two Signed 8-Bit Numbers (-99 * 88)

ldi mc8s,-99
ldi mp8s,88
rcall mpy8s ;result: m8sH:m8sL = $ddf8 (-8712)

;***** Multiply Two Unsigned 16-Bit Numbers (5050 * 10,000)

ldi mc16uL,low(5050)
ldi mc16uH,high(5050)
ldi mp16uL,low(10000)
ldi mp16uH,high(10000)
rcall mpy16u ;result: m16u3:m16u2:m16u1:m16u0
;=030291a0 (50,500,000)

;***** Multiply Two Signed 16-Bit Numbers (-12345*(-4321))

ldi mc16sL,low(-12345)
ldi mc16sH,high(-12345)
ldi mp16sL,low(-4321)
ldi mp16sH,high(-4321)
rcall mpy16s ;result: m16s3:m16s2:m16s1:m16s0
;=$032df219 (53,342,745)

;***** Divide Two Unsigned 8-Bit Numbers (100/3)

ldi dd8u,100
ldi dv8u,3
rcall div8u ;result: $21 (33)
;remainder: $01 (1)

;***** Divide Two Signed 8-Bit Numbers (-110/-11)

ldi dd8s,-110
ldi dv8s,-11
rcall div8s ;result: $0a (10)
;remainder $00 (0)

;***** Divide Two Unsigned 16-Bit Numbers (50,000/60,000)

ldi dd16uL,low(50000)
ldi dd16uH,high(50000)
ldi dv16uL,low(60000)
ldi dv16uH,high(60000)
rcall div16u ;result: $0000 (0)
;remainder: $c350 (50,000)

;***** Divide Two Signed 16-Bit Numbers (-22,222/10)

ldi dd16sL,low(-22222)
ldi dd16sH,high(-22222)
ldi dv16sL,low(10)
ldi dv16sH,high(10)
rcall div16s ;result: $f752 (-2222)
;remainder: $0002 (2)

forever:rjmp forever

Programming the AVR Microcontrollers in Machine Language

AVR
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from

Avr) Jump to: navigation, search The AVRs are a family of RISC
microcontrollers from Atmel. Their internal architecture was
conceived by two students: Alf-Egil Bogen and Vegard Wollan, at
the Norwegian Institute of Technology (NTH] and further developed
at Atmel Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers. These
are 32-bit RISC devices featuring SIMD and DSP instructions, along
with many additional features for audio and video processing,
intended to compete with ARM based processors. Note that the use
of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR
Microcontrollers. The acronym AVR has been reported to stand for
Advanced Virtual RISC. It's also rumoured to stand for the
company's founders: Alf and Vegard, who are evasive when
questioned about it. Contents [hide] 1 Device Overview 1.1
Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2
AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other AVR
Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit]
Device Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die, removing
the need for external memory (though still available on some
devices). [edit] Program Memory Program instructions are stored in
semi-permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed using
16 bit word sizes. The size of the program memory is indicated in
the naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data address
space consists of the register file, I/O registers, and SRAM. The
AVRs have thirty-two single-byte registers and are classified as 8-
bit RISC devices. The working registers are mapped in as the first
thirty-two memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after both
these sections (address 006016). (Note that the I/O register space
may be larger on some more extensive devices, in which case
memory mapped I/O registers will occupy a portion of the SRAM.)
Even though there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still be
addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is most
often used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program Execution
Atmel's AVRs have a single level pipeline design. The next machine
instruction is fetched as the current one is executing. Most
instructions take just one or two clock cycles, making AVRs
relatively fast among the eight-bit microcontrollers. The AVR family
of processors were designed for the efficient execution of compiled
C code. The AVR instruction set is more orthogonal than most
eight-bit microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that are
different from each other. Register locations R0 to R15 have
different addressing capabilities than register locations R16 to R31.
I/O ports 0 to 31 have different addressing capabilities than I/O
ports 32 to 63. CLR affects flags, while SER does not, even though
they are complementary instructions. CLR set all bits to zero and
SER sets them to one. (Note though, that neither CLR nor SER are
native instructions. Instead CLR is syntactic sugar for [produces
the same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags while
moves/loads/stores/branches such as LDI do not.) [edit] Speed The
AVR line can normally support clock speeds from 0-16MHz, with
some devices reaching 20MHz. Lower powered operation usually
requires a reduced clock speed. All AVRs feature an on-chip
oscillator, removing the need for external clocks or resonator
circuitry. Because many operations on the AVR are single cycle,
the AVR can achieve up to 1MIPS per MHz. [edit] Development
AVRs have a large following due to the free and inexpensive
development tools available, including reasonably priced
development boards and free development software. The AVRs are
marketed under various names that share the same basic core but
with different peripheral and memory combinations. Some models
(notably, the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good. See
external links for sites relating to AVR development. [edit] Features
Current AVRs offer a wide range of features: RISC Core Running
Many Single Cycle Instructions Multifunction, Bi-directional I/O
Ports with Internal, Configurable Pull-up Resistors Multiple Internal
Oscillators Internal, Self-Programmable Instruction Flash Memory
up to 256K In-System Programmable using ICSP, JTAG, or High
Voltage methods Optional Boot Code Section with Independent
Lock Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time
generator Lighting (PWM Specific) Controller models Dedicated I²C
Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous
Serial Peripherals (UART/USART) (As used with RS-232,RS-485,
and more) Serial Peripheral Interface (SPI) CAN Controller Support
USB Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-speed
(HID) software emulation Ethernet Controller Support Universal
Serial Interface (USI) for Two or Three-Wire Synchronous Data
Transfer Analog Comparators LCD Controller Support 10-Bit A/D
Converters, with multiplex of up to 16 channels Brownout
Detection Watchdog Timer (WDT) Low-voltage Devices Operating
Down to 1.8v Multiple Power-Saving Sleep Modes picoPower
Devices Atmel AVR assembler programming language Atmel AVR
machine programming language Atmel AVR From Wikipedia, the
free encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from Atmel.
Their internal architecture was conceived by two students: Alf-Egil
Bogen and Vegard Wollan, at the Norwegian Institute of
Technology (NTH] and further developed at Atmel Norway, a
subsidiary founded by the two architects. Atmel recently released
the Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with many
additional features for audio and video processing, intended to
compete with ARM based processors. Note that the use of "AVR" in
this article refers to the 8-bit RISC line of Atmel AVR
Microcontrollers. The acronym AVR has been reported to stand for
Advanced Virtual RISC. It's also rumoured to stand for the
company's founders: Alf and Vegard, who are evasive when
questioned about it. Contents [hide] 1 Device Overview 1.1
Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2
AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other AVR
Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit]
Device Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die, removing
the need for external memory (though still available on some
devices). [edit] Program Memory Program instructions are stored in
semi-permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed using
16 bit word sizes. The size of the program memory is indicated in
the naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data address
space consists of the register file, I/O registers, and SRAM. The
AVRs have thirty-two single-byte registers and are classified as 8-
bit RISC devices. The working registers are mapped in as the first
thirty-two memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after both
these sections (address 006016). (Note that the I/O register space
may be larger on some more extensive devices, in which case
memory mapped I/O registers will occupy a portion of the SRAM.)
Even though there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still be
addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is most
often used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program Execution
Atmel's AVRs have a single level pipeline design. The next machine
instruction is fetched as the current one is executing. Most
instructions take just one or two clock cycles, making AVRs
relatively fast among the eight-bit microcontrollers. The AVR family
of processors were designed for the efficient execution of compiled
C code. The AVR instruction set is more orthogonal than most
eight-bit microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that are
different from each other. Register locations R0 to R15 have

http://avr-asm.tripod.com/avr200.html (1 of 2)1/20/2009 8:34:09 PM

MULTIPLY & DIVIDE (AVR 200)

different addressing capabilities than register locations R16 to R31.

I/O ports 0 to 31 have different addressing capabilities than I/O
ports 32 to 63. CLR affects flags, while SER does not, even though
they are complementary instructions. CLR set all bits to zero and
SER sets them to one. (Note though, that neither CLR nor SER are
native instructions. Instead CLR is syntactic sugar for [produces
the same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags while
moves/loads/stores/branches such as LDI do not.) [edit] Speed The
AVR line can normally support clock speeds from 0-16MHz, with
some devices reaching 20MHz. Lower powered operation usually
requires a reduced clock speed. All AVRs feature an on-chip
oscillator, removing the need for external clocks or resonator
circuitry. Because many operations on the AVR are single cycle,
the AVR can achieve up to 1MIPS per MHz. [edit] Development
AVRs have a large following due to the free and inexpensive
development tools available, including reasonably priced
development boards and free development software. The AVRs are
marketed under various names that share the same basic core but
with different peripheral and memory combinations. Some models
(notably, the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good. See
external links for sites relating to AVR development. [edit] Features
Current AVRs offer a wide range of features: RISC Core Running
Many Single Cycle Instructions Multifunction, Bi-directional I/O
Ports with Internal, Configurable Pull-up Resistors Multiple Internal
Oscillators Internal, Self-Programmable Instruction Flash Memory
up to 256K In-System Programmable using ICSP, JTAG, or High
Voltage methods Optional Boot Code Section with Independent
Lock Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time
generator Lighting (PWM Specific) Controller models Dedicated I²C
Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous
Serial Peripherals (UART/USART) (As used with RS-232,RS-485,
and more) Serial Peripheral Interface (SPI) CAN Controller Support
USB Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-speed
(HID) software emulation Ethernet Controller Support Universal
Serial Interface (USI) for Two or Three-Wire Synchronous Data
Transfer Analog Comparators LCD Controller Support 10-Bit A/D
Converters, with multiplex of up to 16 channels Brownout
Detection Watchdog Timer (WDT) Low-voltage Devices Operating
Down to 1.8v Multiple Power-Saving Sleep Modes picoPower
Devices Atmel AVR assembler programming language Atmel AVR
machine programming language Atmel AVR From Wikipedia, the
free encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from Atmel.
Their internal architecture was conceived by two students: Alf-Egil
Bogen and Vegard Wollan, at the Norwegian Institute of
Technology (NTH] and further developed at Atmel Norway, a
subsidiary founded by the two architects. Atmel recently released
the Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with many
additional features for audio and video processing, intended to
compete with ARM based processors. Note that the use of "AVR" in
this article refers to the 8-bit RISC line of Atmel AVR
Microcontrollers. The acronym AVR has been reported to stand for
Advanced Virtual RISC. It's also rumoured to stand for the
company's founders: Alf and Vegard, who are evasive when
questioned about it. Contents [hide] 1 Device Overview 1.1
Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2
AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other AVR
Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit]
Device Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die, removing
the need for external memory (though still available on some
devices). [edit] Program Memory Program instructions are stored in
semi-permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed using
16 bit word sizes. The size of the program memory is indicated in
the naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data address
space consists of the register file, I/O registers, and SRAM. The
AVRs have thirty-two single-byte registers and are classified as 8-
bit RISC devices. The working registers are mapped in as the first
thirty-two memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after both
these sections (address 006016). (Note that the I/O register space
may be larger on some more extensive devices, in which case
memory mapped I/O registers will occupy a portion of the SRAM.)
Even though there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still be
addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is most
often used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program Execution
Atmel's AVRs have a single level pipeline design. The next machine
instruction is fetched as the current one is executing. Most
instructions take just one or two clock cycles, making AVRs
relatively fast among the eight-bit microcontrollers. The AVR family
of processors were designed for the efficient execution of compiled
C code. The AVR instruction set is more orthogonal than most
eight-bit microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that are
different from each other. Register locations R0 to R15 have
different addressing capabilities than register locations R16 to R31.
I/O ports 0 to 31 have different addressing capabilities than I/O
ports 32 to 63. CLR affects flags, while SER does not, even though
they are complementary instructions. CLR set all bits to zero and
SER sets them to one. (Note though, that neither CLR nor SER are
native instructions. Instead CLR is syntactic sugar for [produces
the same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags while
moves/loads/stores/branches such as LDI do not.) [edit] Speed The
AVR line can normally support clock speeds from 0-16MHz, with
some devices reaching 20MHz. Lower powered operation usually
requires a reduced clock speed. All AVRs feature an on-chip
oscillator, removing the need for external clocks or resonator
circuitry. Because many operations on the AVR are single cycle,
the AVR can achieve up to 1MIPS per MHz. [edit] Development
AVRs have a large following due to the free and inexpensive
development tools available, including reasonably priced
development boards and free development software. The AVRs are
marketed under various names that share the same basic core but
with different peripheral and memory combinations. Some models
(notably, the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good. See
external links for sites relating to AVR development. [edit] Features
Current AVRs offer a wide range of features: RISC Core Running
Many Single Cycle Instructions Multifunction, Bi-directional I/O
Ports with Internal, Configurable Pull-up Resistors Multiple Internal
Oscillators Internal, Self-Programmable Instruction Flash Memory
up to 256K In-System Programmable using ICSP, JTAG, or High
Voltage methods Optional Boot Code Section with Independent
Lock Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time
generator Lighting (PWM Specific) Controller models Dedicated I²C
Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous
Serial Peripherals (UART/USART) (As used with RS-232,RS-485,
and more) Serial Peripheral Interface (SPI) CAN Controller Support
USB Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-speed
(HID) software emulation Ethernet Controller Support Universal
Serial Interface (USI) for Two or Three-Wire Synchronous Data
Transfer Analog Comparators LCD Controller Support 10-Bit A/D
Converters, with multiplex of up to 16 channels Brownout
Detection Watchdog Timer (WDT) Low-voltage Devices Operating
Down to 1.8v Multiple Power-Saving Sleep Modes picoPower
Devices Atmel AVR assembler programming language Atmel AVR
machine programming language

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MULTIPLY & DIVIDE (AVR 200)

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;**** A P P L I C A T I O N N O T E A V R 2 0 0 b
ASM FORUM ************************
ASM MATH ;*
;* Title: Multiply and Divide Routines
TUTORIAL #1
;* Version: 1.1
TUTORIAL #2 ;* Last updated: 97.07.04
TUTORIAL #3 ;* Target: AT90Sxxxx (All AVR Devices)
;*
MATH 200 ;* Support E-mail: avr@atmel.com
MATH 200b ;*
;* DESCRIPTION
MATH 201 ;* This Application Note lists subroutines for the following
MATH 202 ;* Muliply/Divide applications. Routines are straight-line
implementations
MATH 32X ;* optimized for speed:
MATH YX ;*
;* 8 x 8 = 16 bit unsigned
DIV16 XX
;* 16 x 16 = 32 bit unsigned
DIV 24 24 ;* 8 / 8 = 8 + 8 bit unsigned
DIV 3216 ;* 16 / 16 = 16 + 16 bit unsigned
;*
FLOAT 128 ;
SQRT16 ***************************************************************************

MATH 202 .include "1200def.inc"

MATH 202
rjmp RESET ;reset handle
DEC ASCII
INT ASCII ;
***************************************************************************
HX2ASC
;*
AVG8 222 ;* "mpy8u" - 8x8 Bit Unsigned Multiplication
FFT7 ;*
;* This subroutine multiplies the two register variables mp8u
COPY 102 and mc8u.
LPM 108 ;* The result is placed in registers m8uH, m8uL
;*
EPROM 100 ;* Number of words :34 + return
SER EPROM ;* Number of cycles :34 + return
;* Low registers used :None
DFLASH AT45
;* High registers used :3 (mc8u,mp8u/m8uL,m8uH)
FLASH CARD ;*
;* Note: Result Low byte and the multiplier share the same
VFX SMIL
register.
VFX MEM ;* This causes the multiplier to be overwritten by the result.
SORT 220 ;*
;
CRC 236 ***************************************************************************
XMODEM REC
;***** Subroutine Register Variables
UART 304
UART 305 .def mc8u =r16 ;multiplicand
.def mp8u =r17 ;multiplier
UART 128
.def m8uL =r17 ;result Low byte
UART BUFF .def m8uH =r18 ;result High byte
USB 232
;***** Code
AVR ISP
ISP 2313 mpy8u: clr m8uH ;clear result High byte
lsr mp8u ;shift multiplier
ISP 1200
AVR SPI brcc noad80 ;if carry set
add m8uH,mc8u ; add multiplicand to result
I2C 300 High byte
I2C 302 noad80: ror m8uH ;shift right result High
byte
I2C TWI26
ror m8uL ;rotate right result L byte and
I2C/TWI 128 multiplier
I2C/TWI AT8
brcc noad81 ;if carry set
DALLAS-1W add m8uH,mc8u ; add multiplicand to result
DALLAS CRC High byte
noad81: ror m8uH ;shift right result High
ETHNET 8019 byte
TEA ror m8uL ;rotate right result L byte and
multiplier
ADC 128
ADC 10B brcc noad82 ;if carry set
add m8uH,mc8u ; add multiplicand to result
ADC 400
High byte
ADC 401 noad82: ror m8uH ;shift right result High
THERM 232 byte
ror m8uL ;rotate right result L byte and
IRD 410 multiplier
LCD HD44
brcc noad83 ;if carry set
LCD 2313 add m8uH,mc8u ; add multiplicand to result
LCD44 2313 High byte
noad83: ror m8uH ;shift right result High
KBD 240 byte
MUX 242 ror m8uL ;rotate right result L byte and
multiplier
KBD PS2
KBD PC/128 brcc noad84 ;if carry set
PS2 EMU add m8uH,mc8u ; add multiplicand to result
High byte
BOOT MG8 noad84: ror m8uH ;shift right result High
BOOT DR8 byte
ror m8uL ;rotate right result L byte and
ALM CLK multiplier
CLOCK 8564
brcc noad85 ;if carry set
90 DAYS
add m8uH,mc8u ; add multiplicand to result
DELAYS High byte
noad85: ror m8uH ;shift right result High
CALL ID
byte
DTMF 314 ror m8uL ;rotate right result L byte and
PWM 6CH multiplier

PWM 10K brcc noad86 ;if carry set

ENCODE add m8uH,mc8u ; add multiplicand to result
High byte
STH-11 noad86: ror m8uH ;shift right result High
ATMEL CORP byte
ror m8uL ;rotate right result L byte and
AVR
multiplier
BUTTERFLY
AVR BOOK brcc noad87 ;if carry set
add m8uH,mc8u ; add multiplicand to result
High byte
noad87: ror m8uH ;shift right result High
byte
ror m8uL ;rotate right result L byte and
multiplier

ret

;
***************************************************************************
;*
;* "mpy16u" - 16x16 Bit Unsigned Multiplication
;*
;* This subroutine multiplies the two 16-bit register variables
;* mp16uH:mp16uL and mc16uH:mc16uL.
;* The result is placed in m16u3:m16u2:m16u1:m16u0.
;*
;* Number of words :105 + return
;* Number of cycles :105 + return
;* Low registers used :None
;* High registers used :6 (mp16uL,mp16uH,mc16uL/m16u0,mc16uH/
m16u1,m16u2,
;* m16u3)
;*
;
***************************************************************************

;***** Subroutine Register Variables

.def mc16uL =r16 ;multiplicand low byte

.def mc16uH =r17 ;multiplicand high byte
.def mp16uL =r18 ;multiplier low byte
.def mp16uH =r19 ;multiplier high byte
.def m16u0 =r18 ;result byte 0 (LSB)
.def m16u1 =r19 ;result byte 1
.def m16u2 =r20 ;result byte 2
.def m16u3 =r21 ;result byte 3 (MSB)

;***** Code

mpy16u: clr m16u3 ;clear 2 highest bytes of

result
clr m16u2
lsr mp16uH ;rotate multiplier Low
ror mp16uL ;rotate multiplier High

brcc noadd0 ;if carry set

add m16u2,mc16uL ; add multiplicand Low to byte 2
of res
adc m16u3,mc16uH ; add multiplicand high to byte
3 of res
noadd0: ror m16u3 ;shift right result byte 3
ror m16u2 ;rotate right result byte 2
ror m16u1 ;rotate result byte 1 and
multiplier High
ror m16u0 ;rotate result byte 0 and
multiplier Low

brcc noadd1 ;if carry set

add m16u2,mc16uL ; add multiplicand Low to byte 2
of res
adc m16u3,mc16uH ; add multiplicand high to byte
3 of res
noadd1: ror m16u3 ;shift right result byte 3
ror m16u2 ;rotate right result byte 2
ror m16u1 ;rotate result byte 1 and
multiplier High
ror m16u0 ;rotate result byte 0 and
multiplier Low

brcc noadd2 ;if carry set

add m16u2,mc16uL ; add multiplicand Low to byte 2
of res
adc m16u3,mc16uH ; add multiplicand high to byte
3 of res
noadd2: ror m16u3 ;shift right result byte 3
ror m16u2 ;rotate right result byte 2
ror m16u1 ;rotate result byte 1 and
multiplier High
ror m16u0 ;rotate result byte 0 and
multiplier Low

brcc noadd3 ;if carry set

add m16u2,mc16uL ; add multiplicand Low to byte 2
of res
adc m16u3,mc16uH ; add multiplicand high to byte
3 of res
noadd3: ror m16u3 ;shift right result byte 3
ror m16u2 ;rotate right result byte 2
ror m16u1 ;rotate result byte 1 and
multiplier High
ror m16u0 ;rotate result byte 0 and
multiplier Low

brcc noadd4 ;if carry set

add m16u2,mc16uL ; add multiplicand Low to byte 2
of res
adc m16u3,mc16uH ; add multiplicand high to byte
3 of res
noadd4: ror m16u3 ;shift right result byte 3
ror m16u2 ;rotate right result byte 2
ror m16u1 ;rotate result byte 1 and
multiplier High
ror m16u0 ;rotate result byte 0 and
multiplier Low

brcc noadd5 ;if carry set

add m16u2,mc16uL ; add multiplicand Low to byte 2
of res
adc m16u3,mc16uH ; add multiplicand high to byte
3 of res
noadd5: ror m16u3 ;shift right result byte 3
ror m16u2 ;rotate right result byte 2
ror m16u1 ;rotate result byte 1 and
multiplier High
ror m16u0 ;rotate result byte 0 and
multiplier Low

brcc noadd6 ;if carry set

add m16u2,mc16uL ; add multiplicand Low to byte 2
of res
adc m16u3,mc16uH ; add multiplicand high to byte
3 of res
noadd6: ror m16u3 ;shift right result byte 3
ror m16u2 ;rotate right result byte 2
ror m16u1 ;rotate result byte 1 and
multiplier High
ror m16u0 ;rotate result byte 0 and
multiplier Low

brcc noadd7 ;if carry sett

add m16u2,mc16uL ; add multiplicand Low to byte 2
of res
adc m16u3,mc16uH ; add multiplicand high to byte
3 of res
noadd7: ror m16u3 ;shift right result byte 3
ror m16u2 ;rotate right result byte 2
ror m16u1 ;rotate result byte 1 and
multiplier High
ror m16u0 ;rotate result byte 0 and
multiplier Low

brcc noadd8 ;if carry set

add m16u2,mc16uL ; add multiplicand Low to byte 2
of res
adc m16u3,mc16uH ; add multiplicand high to byte
3 of res
noadd8: ror m16u3 ;shift right result byte 3
ror m16u2 ;rotate right result byte 2
ror m16u1 ;rotate result byte 1 and
multiplier High
ror m16u0 ;rotate result byte 0 and
multiplier Low

brcc noadd9 ;if carry set

add m16u2,mc16uL ; add multiplicand Low to byte 2
of res
adc m16u3,mc16uH ; add multiplicand high to byte
3 of res
noadd9: ror m16u3 ;shift right result byte 3
ror m16u2 ;rotate right result byte 2
ror m16u1 ;rotate result byte 1 and
multiplier High
ror m16u0 ;rotate result byte 0 and
multiplier Low

brcc noad10 ;if carry set

add m16u2,mc16uL ; add multiplicand Low to byte 2
of res
adc m16u3,mc16uH ; add multiplicand high to byte
3 of res
noad10: ror m16u3 ;shift right result byte 3
ror m16u2 ;rotate right result byte 2
ror m16u1 ;rotate result byte 1 and
multiplier High
ror m16u0 ;rotate result byte 0 and
multiplier Low

brcc noad11 ;if carry set

add m16u2,mc16uL ; add multiplicand Low to byte 2
of res
adc m16u3,mc16uH ; add multiplicand high to byte
3 of res
noad11: ror m16u3 ;shift right result byte 3
ror m16u2 ;rotate right result byte 2
ror m16u1 ;rotate result byte 1 and
multiplier High
ror m16u0 ;rotate result byte 0 and
multiplier Low

brcc noad12 ;if carry set

add m16u2,mc16uL ; add multiplicand Low to byte 2
of res
adc m16u3,mc16uH ; add multiplicand high to byte
3 of res
noad12: ror m16u3 ;shift right result byte 3
ror m16u2 ;rotate right result byte 2
ror m16u1 ;rotate result byte 1 and
multiplier High
ror m16u0 ;rotate result byte 0 and
multiplier Low

brcc noad13 ;if carry set

add m16u2,mc16uL ; add multiplicand Low to byte 2
of res
adc m16u3,mc16uH ; add multiplicand high to byte
3 of res
noad13: ror m16u3 ;shift right result byte 3
ror m16u2 ;rotate right result byte 2
ror m16u1 ;rotate result byte 1 and
multiplier High
ror m16u0 ;rotate result byte 0 and
multiplier Low

brcc noad14 ;if carry set

add m16u2,mc16uL ; add multiplicand Low to byte 2
of res
adc m16u3,mc16uH ; add multiplicand high to byte
3 of res
noad14: ror m16u3 ;shift right result byte 3
ror m16u2 ;rotate right result byte 2
ror m16u1 ;rotate result byte 1 and
multiplier High
ror m16u0 ;rotate result byte 0 and
multiplier Low

brcc noad15 ;if carry set

add m16u2,mc16uL ; add multiplicand Low to byte 2
of res
adc m16u3,mc16uH ; add multiplicand high to byte
3 of res
noad15: ror m16u3 ;shift right result byte 3
ror m16u2 ;rotate right result byte 2
ror m16u1 ;rotate result byte 1 and
multiplier High
ror m16u0 ;rotate result byte 0 and
multiplier Low

ret

;
***************************************************************************
;*
;* "div8u" - 8/8 Bit Unsigned Division
;*
;* This subroutine divides the two register variables
"dd8u" (dividend) and
;* "dv8u" (divisor). The result is placed in "dres8u" and the
remainder in
;* "drem8u".
;*
;* Number of words :66 + return
;* Number of cycles :50/58/66 (Min/Avg/Max) + return
;* Low registers used :1 (drem8u)
;* High registers used :2 (dres8u/dd8u,dv8u)
;*
;
***************************************************************************

;***** Subroutine Register Variables

.def drem8u =r15 ;remainder

.def dres8u =r16 ;result
.def dd8u =r16 ;dividend
.def dv8u =r17 ;divisor

;***** Code

div8u: sub drem8u,drem8u ;clear remainder and carry

rol dd8u ;shift left dividend

rol drem8u ;shift dividend into remainder
sub drem8u,dv8u ;remainder = remainder - divisor
brcc d8u_1 ;if result negative
add drem8u,dv8u ; restore remainder
clc ; clear carry to be shifted into
result
rjmp d8u_2 ;else
d8u_1: sec ; set carry to be
shifted into result

d8u_2: rol dd8u ;shift left dividend

rol drem8u ;shift dividend into remainder
sub drem8u,dv8u ;remainder = remainder - divisor
brcc d8u_3 ;if result negative
add drem8u,dv8u ; restore remainder
clc ; clear carry to be shifted into
result
rjmp d8u_4 ;else
d8u_3: sec ; set carry to be
shifted into result

d8u_4: rol dd8u ;shift left dividend

rol drem8u ;shift dividend into remainder
sub drem8u,dv8u ;remainder = remainder - divisor
brcc d8u_5 ;if result negative
add drem8u,dv8u ; restore remainder
clc ; clear carry to be shifted into
result
rjmp d8u_6 ;else
d8u_5: sec ; set carry to be
shifted into result

d8u_6: rol dd8u ;shift left dividend

rol drem8u ;shift dividend into remainder
sub drem8u,dv8u ;remainder = remainder - divisor
brcc d8u_7 ;if result negative
add drem8u,dv8u ; restore remainder
clc ; clear carry to be shifted into
result
rjmp d8u_8 ;else
d8u_7: sec ; set carry to be
shifted into result

d8u_8: rol dd8u ;shift left dividend

rol drem8u ;shift dividend into remainder
sub drem8u,dv8u ;remainder = remainder - divisor
brcc d8u_9 ;if result negative
add drem8u,dv8u ; restore remainder
clc ; clear carry to be shifted into
result
rjmp d8u_10 ;else
d8u_9: sec ; set carry to be
shifted into result

d8u_10: rol dd8u ;shift left dividend

rol drem8u ;shift dividend into remainder
sub drem8u,dv8u ;remainder = remainder - divisor
brcc d8u_11 ;if result negative
add drem8u,dv8u ; restore remainder
clc ; clear carry to be shifted into
result
rjmp d8u_12 ;else
d8u_11: sec ; set carry to be
shifted into result

d8u_12: rol dd8u ;shift left dividend

rol drem8u ;shift dividend into remainder
sub drem8u,dv8u ;remainder = remainder - divisor
brcc d8u_13 ;if result negative
add drem8u,dv8u ; restore remainder
clc ; clear carry to be shifted into
result
rjmp d8u_14 ;else
d8u_13: sec ; set carry to be
shifted into result

d8u_14: rol dd8u ;shift left dividend

rol drem8u ;shift dividend into remainder
sub drem8u,dv8u ;remainder = remainder - divisor
brcc d8u_15 ;if result negative
add drem8u,dv8u ; restore remainder
clc ; clear carry to be shifted into
result
rjmp d8u_16 ;else
d8u_15: sec ; set carry to be
shifted into result

d8u_16: rol dd8u ;shift left dividend

ret

;
***************************************************************************
;*
;* "div16u" - 16/16 Bit Unsigned Division
;*
;* This subroutine divides the two 16-bit numbers
;* "dd8uH:dd8uL" (dividend) and "dv16uH:dv16uL" (divisor).
;* The result is placed in "dres16uH:dres16uL" and the
remainder in
;* "drem16uH:drem16uL".
;*
;* Number of words :196 + return
;* Number of cycles :148/173/196 (Min/Avg/Max)
;* Low registers used :2 (drem16uL,drem16uH)
;* High registers used :4 (dres16uL/dd16uL,dres16uH/dd16uH,
dv16uL,dv16uH)
;*
;
***************************************************************************

;***** Subroutine Register Variables

.def drem16uL=r14
.def drem16uH=r15
.def dres16uL=r16
.def dres16uH=r17
.def dd16uL =r16
.def dd16uH =r17
.def dv16uL =r18
.def dv16uH =r19

;***** Code

div16u: clr drem16uL ;clear remainder Low byte

sub drem16uH,drem16uH;clear remainder High byte and
carry

rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_1 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into
result
rjmp d16u_2 ;else
d16u_1: sec ; set carry to be
shifted into result

d16u_2: rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_3 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into
result
rjmp d16u_4 ;else
d16u_3: sec ; set carry to be
shifted into result

d16u_4: rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_5 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into
result
rjmp d16u_6 ;else
d16u_5: sec ; set carry to be
shifted into result

d16u_6: rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_7 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into
result
rjmp d16u_8 ;else
d16u_7: sec ; set carry to be
shifted into result

d16u_8: rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_9 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into
result
rjmp d16u_10 ;else
d16u_9: sec ; set carry to be
shifted into result

d16u_10:rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_11 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into
result
rjmp d16u_12 ;else
d16u_11:sec ; set carry to be shifted into
result

d16u_12:rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_13 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into
result
rjmp d16u_14 ;else
d16u_13:sec ; set carry to be shifted into
result

d16u_14:rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_15 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into
result
rjmp d16u_16 ;else
d16u_15:sec ; set carry to be shifted into
result

d16u_16:rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_17 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into
result
rjmp d16u_18 ;else
d16u_17: sec ; set carry to be
shifted into result

d16u_18:rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_19 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into
result
rjmp d16u_20 ;else
d16u_19:sec ; set carry to be shifted into
result

d16u_20:rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_21 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into
result
rjmp d16u_22 ;else
d16u_21:sec ; set carry to be shifted into
result

d16u_22:rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_23 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into
result
rjmp d16u_24 ;else
d16u_23:sec ; set carry to be shifted into
result

d16u_24:rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_25 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into
result
rjmp d16u_26 ;else
d16u_25:sec ; set carry to be shifted into
result

d16u_26:rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_27 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into
result
rjmp d16u_28 ;else
d16u_27:sec ; set carry to be shifted into
result

d16u_28:rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_29 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into
result
rjmp d16u_30 ;else
d16u_29:sec ; set carry to be shifted into
result

d16u_30:rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_31 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into
result
rjmp d16u_32 ;else
d16u_31:sec ; set carry to be shifted into
result

d16u_32:rol dd16uL ;shift left dividend

rol dd16uH
ret

;
****************************************************************************
;*
;* Test Program
;*
;* This program calls all the subroutines as an example of
usage and to
;* verify correct verification.
;*
;
****************************************************************************

;***** Main Program Register variables

.def temp =r16 ;temporary storage variable

;***** Code
RESET:
;---------------------------------------------------------------
;Include these lines for devices with SRAM
; ldi temp,low(RAMEND)
; out SPL,temp
; ldi temp,high(RAMEND)
; out SPH,temp ;init Stack Pointer
;---------------------------------------------------------------

;***** Multiply Two Unsigned 8-Bit Numbers (250 * 4)

ldi mc8u,250
ldi mp8u,4
rcall mpy8u ;result: m8uH:m8uL = $03e8 (1000)

;***** Multiply Two Unsigned 16-Bit Numbers (5050 * 10,000)

ldi mc16uL,low(5050)
ldi mc16uH,high(5050)
ldi mp16uL,low(10000)
ldi mp16uH,high(10000)
rcall mpy16u ;result: m16u3:m16u2:m16u1:m16u0
;=$030291a0 (50,500,000)

;***** Divide Two Unsigned 8-Bit Numbers (100/3)

ldi dd8u,100
ldi dv8u,3
rcall div8u ;result: $21 (33)
;remainder: $01 (1)

;***** Divide Two Unsigned 16-Bit Numbers (50,000/24,995)

ldi dd16uL,low(50000)
ldi dd16uH,high(50000)
ldi dv16uL,low(24995)
ldi dv16uH,high(24995)
rcall div16u ;result: $0002 (2)
;remainder: $000a (10)

forever:rjmp forever

Programming the AVR Microcontrollers in Machine Language

AVR
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© WebRing Inc. Search

Atmel AVR From Wikipedia, the free encyclopedia (Redirected from

Avr) Jump to: navigation, search The AVRs are a family of RISC
microcontrollers from Atmel. Their internal architecture was
conceived by two students: Alf-Egil Bogen and Vegard Wollan, at
the Norwegian Institute of Technology (NTH] and further developed
at Atmel Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers. These
are 32-bit RISC devices featuring SIMD and DSP instructions, along
with many additional features for audio and video processing,
intended to compete with ARM based processors. Note that the use
of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR
Microcontrollers. The acronym AVR has been reported to stand for
Advanced Virtual RISC. It's also rumoured to stand for the
company's founders: Alf and Vegard, who are evasive when
questioned about it. Contents [hide] 1 Device Overview 1.1
Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2
AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other AVR
Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit]
Device Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die, removing
the need for external memory (though still available on some
devices). [edit] Program Memory Program instructions are stored in
semi-permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed using
16 bit word sizes. The size of the program memory is indicated in
the naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data address
space consists of the register file, I/O registers, and SRAM. The

http://avr-asm.tripod.com/avr200b.html (1 of 2)1/20/2009 8:35:39 PM

MULTIPLY & DIVIDE (AVR 200)

AVRs have thirty-two single-byte registers and are classified as 8-

bit RISC devices. The working registers are mapped in as the first
thirty-two memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after both
these sections (address 006016). (Note that the I/O register space
may be larger on some more extensive devices, in which case
memory mapped I/O registers will occupy a portion of the SRAM.)
Even though there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still be
addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is most
often used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program Execution
Atmel's AVRs have a single level pipeline design. The next machine
instruction is fetched as the current one is executing. Most
instructions take just one or two clock cycles, making AVRs
relatively fast among the eight-bit microcontrollers. The AVR family
of processors were designed for the efficient execution of compiled
C code. The AVR instruction set is more orthogonal than most
eight-bit microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that are
different from each other. Register locations R0 to R15 have
different addressing capabilities than register locations R16 to R31.
I/O ports 0 to 31 have different addressing capabilities than I/O
ports 32 to 63. CLR affects flags, while SER does not, even though
they are complementary instructions. CLR set all bits to zero and
SER sets them to one. (Note though, that neither CLR nor SER are
native instructions. Instead CLR is syntactic sugar for [produces
the same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags while
moves/loads/stores/branches such as LDI do not.) [edit] Speed The
AVR line can normally support clock speeds from 0-16MHz, with
some devices reaching 20MHz. Lower powered operation usually
requires a reduced clock speed. All AVRs feature an on-chip
oscillator, removing the need for external clocks or resonator
circuitry. Because many operations on the AVR are single cycle,
the AVR can achieve up to 1MIPS per MHz. [edit] Development
AVRs have a large following due to the free and inexpensive
development tools available, including reasonably priced
development boards and free development software. The AVRs are
marketed under various names that share the same basic core but
with different peripheral and memory combinations. Some models
(notably, the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good. See
external links for sites relating to AVR development. [edit] Features
Current AVRs offer a wide range of features: RISC Core Running
Many Single Cycle Instructions Multifunction, Bi-directional I/O
Ports with Internal, Configurable Pull-up Resistors Multiple Internal
Oscillators Internal, Self-Programmable Instruction Flash Memory
up to 256K In-System Programmable using ICSP, JTAG, or High
Voltage methods Optional Boot Code Section with Independent
Lock Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time
generator Lighting (PWM Specific) Controller models Dedicated I²C
Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous
Serial Peripherals (UART/USART) (As used with RS-232,RS-485,
and more) Serial Peripheral Interface (SPI) CAN Controller Support
USB Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-speed
(HID) software emulation Ethernet Controller Support Universal
Serial Interface (USI) for Two or Three-Wire Synchronous Data
Transfer Analog Comparators LCD Controller Support 10-Bit A/D
Converters, with multiplex of up to 16 channels Brownout
Detection Watchdog Timer (WDT) Low-voltage Devices Operating
Down to 1.8v Multiple Power-Saving Sleep Modes picoPower
Devices Atmel AVR assembler programming language Atmel AVR
machine programming language Atmel AVR From Wikipedia, the
free encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from Atmel.
Their internal architecture was conceived by two students: Alf-Egil
Bogen and Vegard Wollan, at the Norwegian Institute of
Technology (NTH] and further developed at Atmel Norway, a
subsidiary founded by the two architects. Atmel recently released
the Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with many
additional features for audio and video processing, intended to
compete with ARM based processors. Note that the use of "AVR" in
this article refers to the 8-bit RISC line of Atmel AVR
Microcontrollers. The acronym AVR has been reported to stand for
Advanced Virtual RISC. It's also rumoured to stand for the
company's founders: Alf and Vegard, who are evasive when
questioned about it. Contents [hide] 1 Device Overview 1.1
Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2
AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other AVR
Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit]
Device Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die, removing
the need for external memory (though still available on some
devices). [edit] Program Memory Program instructions are stored in
semi-permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed using
16 bit word sizes. The size of the program memory is indicated in
the naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data address
space consists of the register file, I/O registers, and SRAM. The
AVRs have thirty-two single-byte registers and are classified as 8-
bit RISC devices. The working registers are mapped in as the first
thirty-two memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after both
these sections (address 006016). (Note that the I/O register space
may be larger on some more extensive devices, in which case
memory mapped I/O registers will occupy a portion of the SRAM.)
Even though there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still be
addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is most
often used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program Execution
Atmel's AVRs have a single level pipeline design. The next machine
instruction is fetched as the current one is executing. Most
instructions take just one or two clock cycles, making AVRs
relatively fast among the eight-bit microcontrollers. The AVR family
of processors were designed for the efficient execution of compiled
C code. The AVR instruction set is more orthogonal than most
eight-bit microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that are
different from each other. Register locations R0 to R15 have
different addressing capabilities than register locations R16 to R31.
I/O ports 0 to 31 have different addressing capabilities than I/O
ports 32 to 63. CLR affects flags, while SER does not, even though
they are complementary instructions. CLR set all bits to zero and
SER sets them to one. (Note though, that neither CLR nor SER are
native instructions. Instead CLR is syntactic sugar for [produces
the same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags while
moves/loads/stores/branches such as LDI do not.) [edit] Speed The
AVR line can normally support clock speeds from 0-16MHz, with
some devices reaching 20MHz. Lower powered operation usually
requires a reduced clock speed. All AVRs feature an on-chip
oscillator, removing the need for external clocks or resonator
circuitry. Because many operations on the AVR are single cycle,
the AVR can achieve up to 1MIPS per MHz. [edit] Development
AVRs have a large following due to the free and inexpensive
development tools available, including reasonably priced
development boards and free development software. The AVRs are
marketed under various names that share the same basic core but
with different peripheral and memory combinations. Some models
(notably, the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good. See
external links for sites relating to AVR development. [edit] Features
Current AVRs offer a wide range of features: RISC Core Running
Many Single Cycle Instructions Multifunction, Bi-directional I/O
Ports with Internal, Configurable Pull-up Resistors Multiple Internal
Oscillators Internal, Self-Programmable Instruction Flash Memory
up to 256K In-System Programmable using ICSP, JTAG, or High
Voltage methods Optional Boot Code Section with Independent
Lock Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time
generator Lighting (PWM Specific) Controller models Dedicated I²C
Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous
Serial Peripherals (UART/USART) (As used with RS-232,RS-485,
and more) Serial Peripheral Interface (SPI) CAN Controller Support
USB Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-speed
(HID) software emulation Ethernet Controller Support Universal
Serial Interface (USI) for Two or Three-Wire Synchronous Data
Transfer Analog Comparators LCD Controller Support 10-Bit A/D
Converters, with multiplex of up to 16 channels Brownout
Detection Watchdog Timer (WDT) Low-voltage Devices Operating
Down to 1.8v Multiple Power-Saving Sleep Modes picoPower
Devices Atmel AVR assembler programming language Atmel AVR
machine programming language Atmel AVR From Wikipedia, the
free encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from Atmel.
Their internal architecture was conceived by two students: Alf-Egil
Bogen and Vegard Wollan, at the Norwegian Institute of
Technology (NTH] and further developed at Atmel Norway, a
subsidiary founded by the two architects. Atmel recently released
the Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with many
additional features for audio and video processing, intended to
compete with ARM based processors. Note that the use of "AVR" in
this article refers to the 8-bit RISC line of Atmel AVR
Microcontrollers. The acronym AVR has been reported to stand for
Advanced Virtual RISC. It's also rumoured to stand for the
company's founders: Alf and Vegard, who are evasive when
questioned about it. Contents [hide] 1 Device Overview 1.1
Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2
AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other AVR
Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit]
Device Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die, removing
the need for external memory (though still available on some
devices). [edit] Program Memory Program instructions are stored in
semi-permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed using
16 bit word sizes. The size of the program memory is indicated in
the naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data address
space consists of the register file, I/O registers, and SRAM. The
AVRs have thirty-two single-byte registers and are classified as 8-
bit RISC devices. The working registers are mapped in as the first
thirty-two memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after both
these sections (address 006016). (Note that the I/O register space
may be larger on some more extensive devices, in which case
memory mapped I/O registers will occupy a portion of the SRAM.)
Even though there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still be
addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is most
often used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program Execution
Atmel's AVRs have a single level pipeline design. The next machine
instruction is fetched as the current one is executing. Most
instructions take just one or two clock cycles, making AVRs
relatively fast among the eight-bit microcontrollers. The AVR family
of processors were designed for the efficient execution of compiled
C code. The AVR instruction set is more orthogonal than most
eight-bit microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that are
different from each other. Register locations R0 to R15 have
different addressing capabilities than register locations R16 to R31.
I/O ports 0 to 31 have different addressing capabilities than I/O
ports 32 to 63. CLR affects flags, while SER does not, even though
they are complementary instructions. CLR set all bits to zero and
SER sets them to one. (Note though, that neither CLR nor SER are
native instructions. Instead CLR is syntactic sugar for [produces
the same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags while
moves/loads/stores/branches such as LDI do not.) [edit] Speed The
AVR line can normally support clock speeds from 0-16MHz, with
some devices reaching 20MHz. Lower powered operation usually
requires a reduced clock speed. All AVRs feature an on-chip
oscillator, removing the need for external clocks or resonator
circuitry. Because many operations on the AVR are single cycle,
the AVR can achieve up to 1MIPS per MHz. [edit] Development
AVRs have a large following due to the free and inexpensive
development tools available, including reasonably priced
development boards and free development software. The AVRs are
marketed under various names that share the same basic core but
with different peripheral and memory combinations. Some models
(notably, the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good. See
external links for sites relating to AVR development. [edit] Features
Current AVRs offer a wide range of features: RISC Core Running
Many Single Cycle Instructions Multifunction, Bi-directional I/O
Ports with Internal, Configurable Pull-up Resistors Multiple Internal
Oscillators Internal, Self-Programmable Instruction Flash Memory
up to 256K In-System Programmable using ICSP, JTAG, or High
Voltage methods Optional Boot Code Section with Independent
Lock Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time
generator Lighting (PWM Specific) Controller models Dedicated I²C
Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous
Serial Peripherals (UART/USART) (As used with RS-232,RS-485,
and more) Serial Peripheral Interface (SPI) CAN Controller Support
USB Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-speed
(HID) software emulation Ethernet Controller Support Universal
Serial Interface (USI) for Two or Three-Wire Synchronous Data
Transfer Analog Comparators LCD Controller Support 10-Bit A/D
Converters, with multiplex of up to 16 channels Brownout
Detection Watchdog Timer (WDT) Low-voltage Devices Operating
Down to 1.8v Multiple Power-Saving Sleep Modes picoPower
Devices Atmel AVR assembler programming language Atmel AVR
machine programming language

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16 BIT MULTIPLY (AVR 201)

The AVR Assembler Site

16 BIT MULTIPLY (AVR 201)

HOME
RETRO_DAN
; Last change: MWL 21 Jul 99 1:34 pm
ASM FORUM
ASM MATH ;**** A P P L I C A T I O N N O T E A V R 2 0 1
***************************
TUTORIAL #1
;*
TUTORIAL #2 ;* Title : 16bit multiply routines using
TUTORIAL #3 hardware multiplier
;* Version : V1.0
MATH 200 ;* Last updated : 5 Apr, 1999
MATH 200b ;* Target : ATmega83/161/163
;*
MATH 201 ;* Support email : avr@atmel.com
MATH 202 ;*
;* DESCRIPTION
MATH 32X ;* This application note shows a number of examples of
MATH YX how to implement
;* 16bit multiplication using hardware multiplier.
DIV16 XX
Refer to each of the
DIV 24 24 ;* funtions headers for details. The functions
DIV 3216 included in this file
;* are :
FLOAT 128 ;*
SQRT16 ;* mul16x16_16 - Multiply of two 16bits numbers
with 16bits result.
MATH 202 ;* mul16x16_32 - Unsigned multiply of two 16bits
MATH 202 numbers with 32bits
;* result.
DEC ASCII
;* muls16x16_32 - Signed multiply of two 16bits
INT ASCII numbers with 32bits
;* result.
HX2ASC
;* mac16x16_32 - Signed multiply accumulate of two
AVG8 222 16bits numbers
FFT7 ;* with a 32bits result.
;* fmuls16x16_32 - Signed fractional multiply of two
COPY 102 16bits numbers
LPM 108 ;* with 32bits result.
;* fmac16x16_32 - Signed fractional multiply
EPROM 100 accumulate of two 16bits
SER EPROM ;* numbers with a 32bits result.
;*
DFLASH AT45
;
FLASH CARD ******************************************************************************
VFX SMIL
VFX MEM ;
SORT 220 ******************************************************************************
;*
CRC 236 ;* FUNCTION
XMODEM REC ;* mul16x16_16
;* DECRIPTION
UART 304 ;* Multiply of two 16bits numbers with 16bits result.
UART 305 ;* USAGE
;* r17:r16 = r23:r22 * r21:r20
UART 128
;* STATISTICS
UART BUFF ;* Cycles : 9 + ret
;* Words : 6 + ret
USB 232
;* Register usage: r0, r1 and r16 to r23 (8 registers)
AVR ISP ;* NOTE
ISP 2313 ;* Full orthogonality i.e. any register pair can be
used as long as
ISP 1200 ;* the result and the two operands does not share
AVR SPI register pairs.
;* The routine is non-destructive to the operands.
I2C 300 ;*
I2C 302 ;
******************************************************************************
I2C TWI26
I2C/TWI 128 mul16x16_16:
I2C/TWI AT8 mul r22, r20 ; al * bl
movw r17:r16, r1:r0
DALLAS-1W mul r23, r20 ; ah * bl
DALLAS CRC add r17, r0
mul r21, r22 ; bh * al
ETHNET 8019 add r17, r0
TEA ret
ADC 128
ADC 10B ;
******************************************************************************
ADC 400
;*
ADC 401 ;* FUNCTION
THERM 232 ;* mul16x16_32
;* DECRIPTION
IRD 410 ;* Unsigned multiply of two 16bits numbers with 32bits
LCD HD44 result.
;* USAGE
LCD 2313 ;* r19:r18:r17:r16 = r23:r22 * r21:r20
LCD44 2313 ;* STATISTICS
;* Cycles : 17 + ret
KBD 240 ;* Words : 13 + ret
MUX 242 ;* Register usage: r0 to r2 and r16 to r23 (11
registers)
KBD PS2
;* NOTE
KBD PC/128 ;* Full orthogonality i.e. any register pair can be
PS2 EMU used as long as
;* the 32bit result and the two operands does not
BOOT MG8 share register pairs.
BOOT DR8 ;* The routine is non-destructive to the operands.
;*
ALM CLK ;
CLOCK 8564 ******************************************************************************
90 DAYS
mul16x16_32:
DELAYS clr r2
mul r23, r21 ; ah * bh
CALL ID
movw r19:r18, r1:r0
DTMF 314 mul r22, r20 ; al * bl
PWM 6CH movw r17:r16, r1:r0
mul r23, r20 ; ah * bl
PWM 10K add r17, r0
ENCODE adc r18, r1
adc r19, r2
STH-11 mul r21, r22 ; bh * al
ATMEL CORP add r17, r0
adc r18, r1
AVR
adc r19, r2
BUTTERFLY ret
AVR BOOK

;
******************************************************************************
;*
;* FUNCTION
;* muls16x16_32
;* DECRIPTION
;* Signed multiply of two 16bits numbers with 32bits
result.
;* USAGE
;* r19:r18:r17:r16 = r23:r22 * r21:r20
;* STATISTICS
;* Cycles : 19 + ret
;* Words : 15 + ret
;* Register usage: r0 to r2 and r16 to r23 (11
registers)
;* NOTE
;* The routine is non-destructive to the operands.
;*
;
******************************************************************************

muls16x16_32:
clr r2
muls r23, r21 ; (signed)ah *
(signed)bh
movw r19:r18, r1:r0
mul r22, r20 ; al * bl
movw r17:r16, r1:r0
mulsu r23, r20 ; (signed)ah * bl
sbc r19, r2
add r17, r0
adc r18, r1
adc r19, r2
mulsu r21, r22 ; (signed)bh * al
sbc r19, r2
add r17, r0
adc r18, r1
adc r19, r2
ret

;
******************************************************************************
;*
;* FUNCTION
;* mac16x16_32
;* DECRIPTION
;* Signed multiply accumulate of two 16bits numbers
with
;* a 32bits result.
;* USAGE
;* r19:r18:r17:r16 += r23:r22 * r21:r20
;* STATISTICS
;* Cycles : 23 + ret
;* Words : 19 + ret
;* Register usage: r0 to r2 and r16 to r23 (11
registers)
;*
;
******************************************************************************

mac16x16_32:
clr r2

muls r23, r21 ; (signed)ah *

(signed)bh
add r18, r0
adc r19, r1

mul r22, r20 ; al * bl

add r16, r0
adc r17, r1
adc r18, r2
adc r19, r2

mulsu r23, r20 ; (signed)ah * bl

sbc r19, r2
add r17, r0
adc r18, r1
adc r19, r2

mulsu r21, r22 ; (signed)bh * al

sbc r19, r2
add r17, r0
adc r18, r1
adc r19, r2

ret

mac16x16_32_method_B: ; uses two

temporary registers
; (r4,r5), but
reduces cycles/words
; by 1
clr r2

muls r23, r21 ; (signed)ah *

(signed)bh
movw r5:r4,r1:r0

mul r22, r20 ; al * bl

add r16, r0
adc r17, r1
adc r18, r4
adc r19, r5

mulsu r23, r20 ; (signed)ah * bl

sbc r19, r2
add r17, r0
adc r18, r1
adc r19, r2

mulsu r21, r22 ; (signed)bh * al

sbc r19, r2
add r17, r0
adc r18, r1
adc r19, r2

ret

;
******************************************************************************
;*
;* FUNCTION
;* fmuls16x16_32
;* DECRIPTION
;* Signed fractional multiply of two 16bits numbers
with 32bits result.
;* USAGE
;* r19:r18:r17:r16 = ( r23:r22 * r21:r20 ) << 1
;* STATISTICS
;* Cycles : 20 + ret
;* Words : 16 + ret
;* Register usage: r0 to r2 and r16 to r23 (11
registers)
;* NOTE
;* The routine is non-destructive to the operands.
;*
;
******************************************************************************

fmuls16x16_32:
clr r2
fmuls r23, r21 ; ( (signed)ah *
(signed)bh ) << 1
movw r19:r18, r1:r0
fmul r22, r20 ; ( al * bl ) << 1
adc r18, r2
movw r17:r16, r1:r0
fmulsu r23, r20 ; ( (signed)ah *
bl ) << 1
sbc r19, r2
add r17, r0
adc r18, r1
adc r19, r2
fmulsu r21, r22 ; ( (signed)bh *
al ) << 1
sbc r19, r2
add r17, r0
adc r18, r1
adc r19, r2
ret

;
******************************************************************************
;*
;* FUNCTION
;* fmac16x16_32
;* DECRIPTION
;* Signed fractional multiply accumulate of two 16bits
numbers with
;* a 32bits result.
;* USAGE
;* r19:r18:r17:r16 += (r23:r22 * r21:r20) << 1
;* STATISTICS
;* Cycles : 25 + ret
;* Words : 21 + ret
;* Register usage: r0 to r2 and r16 to r23 (11
registers)
;*
;
******************************************************************************

fmac16x16_32:
clr r2

fmuls r23, r21 ; ( (signed)ah *

(signed)bh ) << 1
add r18, r0
adc r19, r1

fmul r22, r20 ; ( al * bl ) << 1

adc r18, r2
adc r19, r2
add r16, r0
adc r17, r1
adc r18, r2
adc r19, r2

fmulsu r23, r20 ; ( (signed)ah *

bl ) << 1
sbc r19, r2
add r17, r0
adc r18, r1
adc r19, r2

fmulsu r21, r22 ; ( (signed)bh *

al ) << 1
sbc r19, r2
add r17, r0
adc r18, r1
adc r19, r2

ret

fmac16x16_32_method_B: ; uses two

temporary registers
; (r4,r5), but
reduces cycles/words
; by 2
clr r2

fmuls r23, r21 ; ( (signed)ah *

(signed)bh ) << 1
movw r5:r4,r1:r0
fmul r22, r20 ; ( al * bl ) << 1
adc r4, r2

add r16, r0
adc r17, r1
adc r18, r4
adc r19, r5

fmulsu r23, r20 ; ( (signed)ah *

bl ) << 1
sbc r19, r2
add r17, r0
adc r18, r1
adc r19, r2
fmulsu r21, r22 ; ( (signed)bh *
al ) << 1
sbc r19, r2
add r17, r0
adc r18, r1
adc r19, r2

ret

;**** End of File ****

Programming the AVR Microcontrollers in Machine Language

AVR
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© WebRing Inc. Search

Atmel AVR From Wikipedia, the free encyclopedia (Redirected

from Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing,
intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still
be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
http://avr-asm.tripod.com/avr201.html (1 of 2)1/20/2009 8:36:15 PM
16 BIT MULTIPLY (AVR 201)

after cycling the power of the device. [edit] Program

Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language

http://avr-asm.tripod.com/avr201.html (2 of 2)1/20/2009 8:36:15 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

16 BIT MATH (AVR 202)

HOME
RETRO_DAN
;**** A P P L I C A T I O N N O T E A V R 2 0 2
ASM FORUM ************************
ASM MATH ;*
;* Title: 16-bit Arithmetics
TUTORIAL #1
;* Version: 1.1
TUTORIAL #2 ;* Last updated: 97.07.04
TUTORIAL #3 ;* Target: AT90Sxxxx (All AVR Devices)
;*
MATH 200 ;* Support E-mail: avr@atmel.com
MATH 200b ;*
;* DESCRIPTION
MATH 201 ;* This application note lists applications for the
MATH 202 following
;* Add/Subtract/Compare operations:
MATH 32X ;*
MATH YX ;* "add16" ADD 16+16
;* "adddi16" ADD 16+Immediate(16)
DIV16 XX
;* "sub16" SUB 16-16
DIV 24 24 ;* "subi16" SUB 16-Immediate(16)
DIV 3216 ;* "cp16" COMPARE 16/16
;* "cpi16" COMPARE 16/Immediate
FLOAT 128 ;* "neg16" NEGATION 16
SQRT16 ;*
;
MATH 202 ***************************************************************************
MATH 202
.cseg
DEC ASCII
ldi r16,0x12 ;Set up some registers to
INT ASCII show usage of
ldi r17,0x34 ;the subroutines below.
HX2ASC
ldi r18,0x56 ;All expected results are
AVG8 222 presented as
FFT7 ldi r19,0x78 ;comments

COPY 102
LPM 108 ;
***************************************************************************
EPROM 100 ;*
SER EPROM ;* "add16" - Adding 16-bit registers
;*
DFLASH AT45
;* This example adds the two pairs of register
FLASH CARD variables (add1l,add1h)
;* and (add2l,add2h) The result is placed in (add1l,
VFX SMIL
add1h).
VFX MEM ;*
SORT 220 ;* Number of words :2
;* Number of cycles :2
CRC 236 ;* Low registers used :None
XMODEM REC ;* High registers used :4
;*
UART 304 ;* Note: The sum and the addend share the same
UART 305 register. This causes the
;* addend to be overwritten by the sum.
UART 128
;*
UART BUFF ;
***************************************************************************
USB 232
AVR ISP ;**** Register Variables
ISP 2313 .def add1l = r16
.def add1h = r17
ISP 1200 .def add2l = r18
AVR SPI .def add2h = r19
I2C 300 ;***** Code
I2C 302 add16: add add1l, add2l ;Add low
bytes
I2C TWI26
adc add1h, add2h ;Add high bytes
I2C/TWI 128 with carry
I2C/TWI AT8 ;Expected result is 0xAC68

DALLAS-1W
DALLAS CRC
;
ETHNET 8019 ***************************************************************************
TEA ;*
;* "addi16" - Adding 16-bit register with immediate
ADC 128 ;*
ADC 10B ;* This example adds a register variable (addi1l,
addi1h) with an
ADC 400
;* immediate 16-bit number defined with .equ-
ADC 401 statement. The result is
THERM 232 ;* placed in (addi1l, addi1h).
;*
IRD 410 ;* Number of words :2
LCD HD44 ;* Number of cycles :2
;* Low registers used :None
LCD 2313 ;* High registers used :2
LCD44 2313 ;*
;* Note: The sum and the addend share the same
KBD 240 register. This causes the
MUX 242 ;* addend to be overwritten by the sum.
;*
KBD PS2
;
KBD PC/128 ***************************************************************************
PS2 EMU
;***** Register Variables
BOOT MG8 .def addi1l = r16
BOOT DR8 .def addi1h = r17

ALM CLK ;***** Immediate 16-bit number

CLOCK 8564 .equ addi2 = 0x1234
90 DAYS
;***** Code
DELAYS addi16: subi add1l, low(-addi2) ;Add low
byte ( x -(-y)) = x + y
CALL ID
sbci add1h, high(-addi2) ;Add high byte with
DTMF 314 carry
PWM 6CH ;Expected result is 0xBE9C

PWM 10K
ENCODE
;
STH-11 ***************************************************************************
ATMEL CORP ;*
;* "sub16" - Subtracting 16-bit registers
AVR
;*
BUTTERFLY ;* This example subtracts two pairs of register
AVR BOOK variables (sub1l,sub1h)
;* from (sub2l, sub2h) The result is stored in
registers sub1l, sub1h.
;*
;* Number of words :2
;* Number of cycles :2
;* Low registers used :None
;* High registers used :4
;*
;* Note: The result and "sub1" share the same
register. This causes "sub1"
;* to be overwritten by the result.
;*
;
***************************************************************************

;***** Register Variables

.def sub1l = r16
.def sub1h = r17
.def sub2l = r18
.def sub2h = r19

;***** Code
sub16: sub sub1l,sub2l ;Subtract
low bytes
sbc sub1h,sub2h ;Add high byte with
carry
;Expected result is 0x4646

;
***************************************************************************
;*
;* "subi16" - Subtracting immediate 16-bit number from
a 16-bit register
;*
;* This example subtracts the immediate 16-bit number
subi2 from the
;* 16-bit register (subi1l,subi1h) The result is
placed in registers
;* subi1l, subi1h.
;*
;* Number of words :2
;* Number of cycles :2
;* Low registers used :None
;* High registers used :2
;*
;* Note: The result and "subi1" share the same
register. This causes
;* "subi1" to be overwritten by the result.
;*
;
***************************************************************************

;***** Register Variables

.def subi1l = r16
.def subi1h = r17

;***** Immediate 16-bit number

.equ subi2 = 0x1234

;***** Code
subi16: subi subi1l,low(subi2) ;Subtract
low bytes
sbci subi1h,high(subi2) ;Subtract high byte
with carry
;Expected result is 0x3412

;
***************************************************************************
;*
;* "cp16" - Comparing two 16-bit numbers
;*
;* This example compares the register pairs (cp1l,cp1h)
with the register
;* pairs (cp2l,cp2h) If they are equal the zero flag
is set(one)
;* otherwise it is cleared(zero)
;*
;* Number of words :2
;* Number of cycles :2
;* Low registers used :None
;* High registers used :4
;*
;* Note: The contents of "cp1" will be overwritten.
;*
;
***************************************************************************

;***** Register Variables

.def cp1l = r16
.def cp1h = r17
.def cp2l = r18
.def cp2h = r19

;***** Code
cp16: cp cp1l,cp2l ;Compare low byte
cpc cp1h,cp2h ;Compare high byte with
carry from
;previous operation
ncp16:
;Expected result is Z=0

;
***************************************************************************
;*
;* "cpi16" - Comparing 16-bit register with 16-bit
immediate
;*
;* This example compares the register pairs (cpi1l,
cpi1h) with the value
;* cpi2. If they are equal the zero flag is set(one),
otherwise it is
;* cleared(zero). This is enabled by the AVR's zero
propagation. Carry is
;* also set if the result is negative. This means that
all conditional
;* branch instructions can be used after the
comparison.
;*
;* Number of words :3
;* Number of cycles :3
;* Low registers used :None
;* High registers used :3
;*
;*
;
***************************************************************************

;***** Register Variables

.def cp1l =r16
.def cp1h =r17
.def c_tmp=r18
.equ cp2 = 0x3412 ;Immediate to compare with

;***** Code
cpi16: cpi cp1l,low(cp2) ;Compare low byte
ldi c_tmp,high(cp2) ;
cpc cp1h,c_tmp ;Compare high byte

;Expected result is Z=1, C=

;
***************************************************************************
;*
;* "neg16" - Negating 16-bit register
;*
;* This example negates the register pair (ng1l,ng1h)
The result will
;* overwrite the register pair.
;*
;* Number of words :4
;* Number of cycles :4
;* Low registers used :None
;* High registers used :2
;*
;
***************************************************************************

;***** Register Variables

.def ng1l = r16
.def ng1h = r17

;***** Code
ng16:
com ng1l ;Invert low byte ;
Calculated by
com ng1h ;Invert high byte ;
incverting all
subi ng1l,low(-1) ;Add 0x0001, low byte ;
bits then adding
sbci ng1h,high(-1) ;Add high byte ;
one (0x0001)
;Expected result is 0xCBEE

;
***************************************************************************
;*
;* End of examples.
;*
;
***************************************************************************

forever:rjmp forever

Programming the AVR Microcontrollers in Machine Language

AVR
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© WebRing Inc. Search

Atmel AVR From Wikipedia, the free encyclopedia (Redirected

from Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing,
intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still
be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
http://avr-asm.tripod.com/avr202.html (1 of 2)1/20/2009 8:37:09 PM
16 BIT MATH (AVR 202)

the ATmega range) have additional instructions to make

arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language

http://avr-asm.tripod.com/avr202.html (2 of 2)1/20/2009 8:37:09 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

32 BIT MATH (AVR XXX)

HOME
RETRO_DAN
;**** A P P L I C A T I O N N O T E A V R ? ? ?
ASM FORUM ************************
ASM MATH ;*
;* Title: 32-bit Arithmetic Routines with
TUTORIAL #1
Macrolibrary
TUTORIAL #2 ;* Project: Math32
TUTORIAL #3 ;* Version: 2.3
;* Last updated: 2003.09.15
MATH 200 ;* Create Date: 1999.10.25
MATH 200b ;* Target MCU: AT90S8515 (as well as
others AVR uC)
MATH 201 ;* (C) ATMEL Corporation (mailto:
MATH 202 avr@atmel.com)
;* Originator: (C) 1999-2003 Andre Birua
MATH 32X
(mailto:birua@hotmail.com)
MATH YX ;* This Application Note absolutely
free in use anybody
DIV16 XX
;* INTERPRETATION
DIV 24 24 ;* This package of assembler subprograms is developed
DIV 3216 for integer arithmetic
;* with tracing of sign bit in 32 bits calculations and
FLOAT 128 data reloads.
SQRT16 ;* It is based on microcontroller register file to the
maximum.
MATH 202 ;* In real users projects available abundant digit
MATH 202 capacity allows to avoid
;* overflow and reduces inaccuracy of rounding errors
DEC ASCII
in chain calculations.
INT ASCII ;* Included macro definitions will increase readability
of assembler source
HX2ASC
;* at bit by bit and multibyte data operations inside
AVG8 222 AVR software model
FFT7 ;*
;* DESCRIPTION
COPY 102 ;* This Application Note lists:
LPM 108 ;* i) Math32 subroutines for the following:
;* Add/Subtract/Multiply/Divide/Complement 32 bits
EPROM 100 operands,
SER EPROM ;* Binary 16 & 24 bits operand to/back BCD conversion,
;* Binary 32 bits operand to BCD conversion,
DFLASH AT45
;* Initialization of data memory on a pattern,
FLASH CARD ;* Load/Store group of registers from/to data space;
;* ii) macro definitions call mathematical and data
VFX SMIL
transfer subroutines;
VFX MEM ;* iii) useful general macroinstructions for the AVR 8-
SORT 220 Bit RISC family
;*
CRC 236 ;* "ADD32" Add without Carry Rd32 = Rd32 +
XMODEM REC Rr32
;* "SUB32" Subtract without Carry Rd32 = Rd32 -
UART 304 Rr32
UART 305 ;* "MUL32" Multiply Unsigned Rd64 = Rd32 *
Rr32
UART 128
;* "DIV32" Divide Unsigned Rd32 = Rd32 /
UART BUFF Rr32 (Rd64)
;* "COM32" One's Complement Rd32 =
USB 232
0xffffffff - Rd32
AVR ISP ;* "NEG32" Two's Complement Rd32 =
ISP 2313 0x00000000 - Rd32
;* "BCD2bin" BCD to Binary 16 Rd16 = Rd24|Rr24
ISP 1200 ;* "BCD3bin" BCD to Binary 24 Rd24 = Rd32|Rr32
AVR SPI ;* "Bin2BCD" Binary 16 to BCD Rd24 = Rd16|Rr16
;* "Bin3BCD" Binary 24 to BCD Rd32 = Rd24|Rr24
I2C 300 ;* "Bin4BCD" Binary 32 to BCD Rd40 = Rd32|
I2C 302 Rr32 || hwrd(Rr32)&Rd16
;* "MathMem" Init Data Memory (MA) = 0x00|0xff
I2C TWI26
;* "MathLoad" Load Registers Rd32|Rr32 = (MA)
I2C/TWI 128 ;* "MathSave" Store Registers (MA) = Rd32|Rd64
I2C/TWI AT8 ;*
;* Rd64: destination registers (8) in the register file
DALLAS-1W ;* Rd32: destination (and source) registers (4) in the
DALLAS CRC register file
;* Rr32: source registers (4) in the register file
ETHNET 8019 ;* (MA): address for access to variable in the internal
TEA memory (SRAM)
;* Note: Math32 use high registers, r0 and lower 512
ADC 128 bytes of data space,
ADC 10B ;* so Rd64=r20:r27, Rd32=r20:r23, Rd24=r20:r22,
Rd16=r20:r21,
ADC 400
;* Rd40=r20:r24, Rr32=r16:r19, Rr24=r16:r18, Rr16=r16:
ADC 401 r17, MA=0:511
THERM 232 ;*
;* Number of words & cycles (Min|Max) c o
IRD 410 m m e n t s
LCD HD44 ;* "ADD32" 6 4|5 Size of Add32sign
;* "SUB32" 16 6|15 Size of Sub32sign
LCD 2313 ;* "MUL32" 24 460|556 Size of Mul32b, based on
LCD44 2313 AVR200 16x16 unsigned
;* "DIV32" 28 528|688 Size of Div32b, based on
KBD 240 AVR200 16/16 unsigned
MUX 242 ;* "COM32" 5 4|4 Part of Sub32
;* "NEG32" 9 8|8 Part of Sub32
KBD PS2
;* "BCD2bin" 26 86|89 Equivalent of AVR204, but
KBD PC/128 smaller & quicker
PS2 EMU ;* "BCD3bin" 43 38|402 Different from BCD2bin
translation algorithm
BOOT MG8 ;* "Bin2BCD" 22 19|177 Equivalent of AVR204, but
BOOT DR8 smaller & much faster
;* "Bin3BCD" 21 36|366 In the form of preamble for
ALM CLK Bin2BCD
CLOCK 8564 ;* "Bin3BCD" 40 36|333 All-sufficient expansion of
Bin2BCD
90 DAYS
;* "Bin4BCD" 37 515|671 Based on AVR204 16-bit Bin
DELAYS to BCD conversion
;* "Bin4BCD" 48 874|878 All-sufficient transform
CALL ID
instead of pre-Bin4BCD
DTMF 314 ;* "MathMem" 10 7|645 Size of MathMemLimit, max
PWM 6CH cycle for 128 bytes
;* "MathLoad" 15 41|46 Size and max cycle for Rr32
PWM 10K load
ENCODE ;* "MathSave" 14 13|78 Size and max cycle for Rd64
save
STH-11 ;* In total: 350 words Usually +7 cycles: rcall &
ATMEL CORP ret
;*
AVR
;* All routines are Code Size` optimized
BUTTERFLY implementations and debugged with
AVR BOOK ;* macrocode for AVR macro assembler version 1.30 (Jan
27 1999 01:30:00) &
;* AVR32 macro assembler version 1.30 (Sep 8
1999 01:30:00).
;* However, AVR32 macro assembler version 1.54 (Nov
14 2001 14:05:48) &
;* AVR32 macro assembler version 1.56 (May 6
2002 14:54:01)
;* generate dummy warnings: Register already defined by
the .DEF directive
;* (command option for disable this kind of warning as
yet is absent...)
;* CheckIt with AVR Studio !
;* NOTE
;* ` Bin4BCD transformations has partial loop
optimization for speed-up
;* While using Math32, it is important to consider the
allocation of the
;* microcontroller resources available for the program.
It is required:
;* - to use r0,r16..r31 with Math32;
;* - to allocate variables used in calculation in the
bottom of the memory;
;* - to use T flag as a sign bit (input, output and
temporary),
;* if you need to operate negative numbers or up-down
overflow error
;*
;* VERSION
;* 1.0 Original version (in use starting with
1999.12.22)
;* 1.1 Fixed precedence bugs if macroparameter is an
assembler expression
;* 1.2 Modify CBF & SBF & IBF macrocalls
;* 1.3 Full modification mathematical and data transfer
macronotation
;* 1.4 Optimaze for speed and code size Mul32 & Div32 &
BCD2bin & Bin2BCD
;* 2.0 Version for publication (added description, note
and demo sections)
;* 2.1 Updated Bin2BCD, added Bin4BCD conversion & XCH
macrocall
;* 2.2 Added functionally closed modifications of
Bin3&4BCD translation
;* 2.3 Added BCD3bin conversion, normalize the comment
of Bin3&4BCD
;*
;* DEMO
;* section below is a sample of macrocalls and not an
ordinary Math32 usage
;*
;
***************************************************************************

.include "8515def.inc"
.listmac ;split Toggle_mode at AVR
Studio
.cseg ;press Step_Over
etceteras of
rjmp Demo ;trace Registers and
Memory

;Words *** general macrocode for the AVR 8-Bit RISC

microcontroller ***
;2 "CLF" CLear bit Flag in register via T flag
;2 "SEF" SEt bit Flag in register via T flag
;2 "CBF" Clear Bit(s) Flag(s) in register via
temporary register
;2 "SBF" Set Bit(s) Flag(s) in register via temporary
register
;2 "IBF" Invert Bit(s) Flag(s) in register via
temporary register
;2 "OUTI" OUT port Immediate via temporary register
;4 "OUTIW" OUT port Immediate Word via temporary
register
;2 "OUTW" OUT port Word from register pair
;2 "INW" IN port Word to register pair
;3 "XCH" data eXCHange between a two registers as
exclusive OR only
;2 "MVW" MoVe register pair as Word
;2 "MVI" MoVe temporary register loaded Immediate
;4 "MOVS" MOVe direct in data Space via temporary
register
;8 "MOVSW" MOVe direct in data Space Word via temporary
register
;3 "STSI" STore direct to data Space Immediate via
temporary register
;4 "STSIW" STore direct to data Space Immediate Word
via temporary register
;4 "LDSW" LoaD direct from data Space Word to register
pair
;4 "STSW" STore direct to data Space Word from
register pair
;2 "LDIW" LoaD Immediate Word to register pair
;2 "LDDW" LoaD indirect with Displacement from data
space Word to register pair
;2 "STDW" STore indirect with Displacement to data
space Word from register pair
;2 "PUSHW" PUSH register pair (Word) on stack
;2 "POPW" POP register pair (Word) from stack

.macro CLF ; Register,Bit#

clt
bld @0,@1
.endmacro
.macro SEF ; Register,Bit#
set
bld @0,@1
.endmacro
.macro CBF ; Register,RegisterH,Bit#[,Bit#][,Bit#][,
Bit#][,Bit#][,Bit#][,Bit#][,Bit#]
ldi @1,~(exp2(@2)|(-@3-1<0)*exp2(@3-0)|
(-@4-1<0)*exp2(@4-0)|(-@5-1<0)*exp2(@5-0)|(-@6-1<0)*exp2(@6-0)|(-@7-1<0)*exp2(@7-0)|(-@8-
1<0)*exp2(@8-0)|(-@9-1<0)*exp2(@9-0))
and @0,@1
.endmacro
.macro SBF ; Register,RegisterH,Bit#[,Bit#][,Bit#][,
Bit#][,Bit#][,Bit#][,Bit#][,Bit#]
ldi @1,exp2(@2)|(-@3-1<0)*exp2(@3-0)|(-
@4-1<0)*exp2(@4-0)|(-@5-1<0)*exp2(@5-0)|(-@6-1<0)*exp2(@6-0)|(-@7-1<0)*exp2(@7-0)|(-@8-1<0)
*exp2(@8-0)|(-@9-1<0)*exp2(@9-0)
or @0,@1
.endmacro
.macro IBF ; Register,RegisterH,Bit#[,Bit#][,Bit#][,
Bit#][,Bit#][,Bit#][,Bit#][,Bit#]
ldi @1,exp2(@2)|(-@3-1<0)*exp2(@3-0)|(-
@4-1<0)*exp2(@4-0)|(-@5-1<0)*exp2(@5-0)|(-@6-1<0)*exp2(@6-0)|(-@7-1<0)*exp2(@7-0)|(-@8-1<0)
*exp2(@8-0)|(-@9-1<0)*exp2(@9-0)
eor @0,@1
.endmacro
.macro OUTI ; Port,RegisterH,ConstantB
ldi @1,@2
out @0,@1
.endmacro
.macro OUTIW ; PortHL,RegisterH,ConstantW
ldi @1,high(@2)
out @0h,@1
ldi @1,low(@2)
out @0l,@1
.endmacro
.macro OUTW ; PortHL,RegisterHL
out @0h,@1h
out @0l,@1l
.endmacro
.macro INW ; RegisterHL,PortHL
in @0l,@1l
in @0h,@1h
.endmacro
.macro XCH ; Register,Register
eor @0,@1
eor @1,@0
eor @0,@1
.endmacro
.macro MVW ; RegisterHL,RegisterHL
mov @0h,@1h
mov @0l,@1l
.endmacro
.macro MVI ; RegisterL,RegisterH,ConstantB
ldi @1,@2
mov @0,@1
.endmacro
.macro MOVS ; Address,Register,Address
lds @1,@2
sts @0,@1
.endmacro
.macro MOVSW ; Address,Register,Address
lds @1,@2
sts @0,@1
lds @1,(@2)+1
sts (@0)+1,@1
.endmacro
.macro STSI ; Address,RegisterH,ConstantB
ldi @1,@2
sts @0,@1
.endmacro
.macro STSIW ; Address,RegisterH,ConstantW
ldi @1,low(@2)
sts @0,@1
ldi @1,high(@2)
sts (@0)+1,@1
.endmacro
.macro LDSW ; RegisterHL,Address
lds @0l,@1
lds @0h,(@1)+1
.endmacro
.macro STSW ; Address,RegisterHL
sts (@0)+1,@1h
sts @0,@1l
.endmacro
.macro LDIW ; RegisterHL,ConstantW
ldi @0l,low(@1)
ldi @0h,high(@1)
.endmacro
.macro LDDW ; RegisterHL,RegisterPair+Displacement
ldd @0l,@1
ldd @0h,@1+1
.endmacro
.macro STDW ; RegisterPair+Displacement,RegisterHL
std @0+1,@1h
std @0,@1l
.endmacro
.macro PUSHW ; RegisterHL
push @0l
push @0h
.endmacro
.macro POPW ; RegisterHL
pop @0h
pop @0l
.endmacro

;Words ***** mathematical and data transfer macrocalls

*****
;3 "INITMEM" INITialize math data space (MEMory
variable) in 0|0xff
;3 "MATHR16" load from MATH data space to Registers r16,
r17,r18,r19
;3 "MATHR20" load from MATH data space to Registers r20,
r21,r22,r23
;3 "OPERAND" load registers as mathematical OPERAND
from math data space
;3 "RESULT2" store registers as mathematical RESULT to
math data space (call)
;3 "RESULT3" store registers as mathematical RESULT to
math data space (jump)
;1 "CNST16B" load immediate CoNSTant to r16 as Byte
;2 "CNST16W" load immediate CoNSTant to r16,r17 as Word
;3 "CNST16T" load immediate CoNSTant to r16,r17,r18 as
Three bytes
;4 "CONST16" load immediate CONSTant to r16,r17,r18,r19
as double word
;4 "CONST20" load immediate CONSTant to r20,r21,r22,r23
as double word

.macro INITMEM ; Address[,Counter(1-128)[,0|1|limit]]

ldi ZL,@0
ldi ZH,@1-1<<1|high(@0)&1
rcall MathMem@2
.endmacro
.macro MATHR16 ; Address[,Bitmap]
ldi ZL,@0
ldi ZH,((-@1-1>0)*ObXXXX|@1-0)<<1|high
(@0)&1
rcall R16MathLoad
.endmacro
.macro MATHR20 ; Address[,Bitmap]
ldi ZL,@0
ldi ZH,((-@1-1>0)*ObXXXX|@1-0)<<1|high
(@0)&1
rcall R20MathLoad
.endmacro
.macro OPERAND ; Address[,[Bitmap][,r16|r20]]
ldi ZL,@0
ldi ZH,((-@1-1>0)*ObXXXX|@1-0)<<1|high
(@0)&1
rcall @2MathLoad
.endmacro
.macro RESULT2 ; Address[,Bitmap]
ldi ZL,@0
ldi ZH,((-@1-1>0)*ObXXXX|@1-0)<<1|high
(@0)&1
rcall MathSave-2*(((-@1-1>0)*ObXXXX|@1-0)
>0x7f)
.endmacro
.macro RESULT3 ; Address[,Bitmap]
ldi ZL,@0
ldi ZH,((-@1-1>0)*ObXXXX|@1-0)<<1|high
(@0)&1
rjmp MathSave-2*(((-@1-1>0)*ObXXXX|@1-0)
>0x7f)
.endmacro
.macro CNST16B ; ConstantB (8 bits)
ldi r16,byte1(@0)
.endmacro
.macro CNST16W ; ConstantW (16 bits)
ldi r16,byte1(@0)
ldi r17,byte2(@0)
.endmacro
.macro CNST16T ; ConstantT (24 bits)
ldi r16,byte1(@0)
ldi r17,byte2(@0)
ldi r18,byte3(@0)
.endmacro
.macro CONST16 ; ConstantD (32 bits)
ldi r16,byte1(@0)
ldi r17,byte2(@0)
ldi r18,byte3(@0)
ldi r19,byte4(@0)
.endmacro
.macro CONST20 ; ConstantD (32 bits)
ldi r20,byte1(@0)
ldi r21,byte2(@0)
ldi r22,byte3(@0)
ldi r23,byte4(@0)
.endmacro

;
***************************************************************************
;# # # # # # # # # Assign Math32 Symbol and
Notation # # # # # # # # #
;
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;*
;* Add32[sign], Sub32[sign], Mul32[b|w|t], Div32[b|w|
t] :
;* operand1
operand2 result
;* r20r21r22r23 +|-|*|/ r16r17r18r19 =
r20r21r22r23[r24r25r26r27]
;*
;* Com32, Neg32 : Bin2BCD20,
BCD2bin20 :
;* operand result
operand result
;* r20r21r22r23 >>> r20r21r22r23 r20r21[r22]
>>> r20r21[r22]
;*
;* BCD3bin, Bin3BCD, Bin4BCD : Bin2BCD16,
BCD2bin16 :
;* operand result
operand result
;* r16...r23 >>> r20r21r22[r23[r24]] r16r17
[r18] >>> r20r21[r22]
;*
;
***************************************************************************
.set ObXXXX=0b1111 ;default load & store memory
variable bitmap upon
;little-endian format of numbers, i.e. abs.address(LSB)
< abs.address(MSB)

;
***************************************************************************
;*
;* Initialize Memory in Math Data Space
;*
;* First 512+127 bytes of data space can be initialize
in 0 or 0xff
;* Limit: if Flag T==1 then EachMemoryByte=0 else
EachMemoryByte=0xff
;*
;
***************************************************************************
.def MathPattern=r28 ;YL
.def MathCounter=r29 ;YH

MathMemLimit: brts MathMem0x0 ;

MathMem0x1: ser MathPattern ;
cpse ZH,ZH ;skip next
instruction
MathMem0x0: clr MathPattern ;
mov MathCounter,ZH ;copy counter
cbr ZH,0xfe ;Z points to math
data space
NextMemByte: st Z+,MathPattern ;
subi MathCounter,2 ;
brcc NextMemByte ;while
MathCounter>=0
ret ;
.equ MathMem=MathMem0x0 ;default initialize memory call

;
***************************************************************************
;*
;* Registers Load from Math Data Space
;*
;* Load: r16r17r18r19r20r21r22r23 from first 512+3
bytes of data space
;* operand2 operand1 (max starting
address: 0x1ff)
;*
;
***************************************************************************
.def MathBmp=r26 ;only XL,XH from high registers
.def MathTmp=r27 ;do not keep useful data or not
used below

R16MathLoad: ldi YL,16 ;Y points

to operand2 LSB
cpse ZH,ZH ;skip next
instruction
R20MathLoad: ldi YL,20 ;Y points
to operand1 LSB
clr YH ;
mov MathBmp,ZH ;copy bitmap
cbr ZH,0xfe ;Z points to math
data space
sbr MathBmp,0xe0 ;it is possible in
each macrocall
MathLoadNext: lsr MathBmp ;
clr MathTmp ;load 0 to temp
register
sbrc MathBmp,0 ;if bit 0 bitmap
not clear
ld MathTmp,Z+ ; load operand
from memory to temp
st Y+,MathTmp ;store temp to math
register
sbrc MathBmp,4 ;
rjmp MathLoadNext ;while bit 4 of
bitmap not clear
ret ;
.equ MathLoad=R20MathLoad ;default registers load call

;
***************************************************************************
;*
;* Registers Save to Math Data Space
;*
;* Save: r20r21r22r23r24r25r26r27 to first 512
+7 bytes of data space
;* result (remainder) (max starting
address: 0x1ff)
;*
;
***************************************************************************
.def MathBmp=r0 ;all high registers keep useful
data or used below

sec ;
cpse ZH,ZH ;skip next
instruction
R20MathSave: clc ;
mov MathBmp,ZH ;copy bitmap
cbr ZH,0xfe ;Z points to math
data space
ror MathBmp ;now bitmap have
all 8 bits
ldi YL,20 ;Y points to result
LSB
MathSaveNext: clr YH ;
ld YH,Y+ ;in order to not
use other registers
sbrc MathBmp,0 ;if bit 0 bitmap
not clear
st Z+,YH ; store
result byte to memory
lsr MathBmp ;
brne MathSaveNext ;while not empty
bitmap
ret ;
.equ MathSave=R20MathSave ;default registers save call

;
***************************************************************************
;*
;* Add32 == 32+32 Bit Unsigned Addition
;*
;* add1L::add1H + add2L::add2H = add1L::add1H
;* item item sum
;* r20r21r22r23 + r16r17r18r19 = r20r21r22r23
;*
;
***************************************************************************
.def add20 = r16 ; item 2 byte 0 (LSB)
.def add21 = r17 ; item 2 byte 1
.def add22 = r18 ; item 2 byte 2
.def add23 = r19 ; item 2 byte 3 (MSB)
.def add10 = r20 ; item 1 byte 0 (LSB)
.def add11 = r21 ; item 1 byte 1
.def add12 = r22 ; item 1 byte 2
.def add13 = r23 ; item 1 byte 3 (MSB)

Add32sign: brts Sub32sign ;

Add32: add add10,add20 ;Add low
bytes
adc add11,add21 ;Add higher bytes
with carry
adc add12,add22 ;
adc add13,add23 ;
ret ;

;
***************************************************************************
;*
;* Sub32 == 32-32 Bit Unsigned Subtraction
;*
;* sub1L::sub1H - sub2L::sub2H = sub1L::sub1H
;* minuend subtrahend difference
;* r20r21r22r23 - r16r17r18r19 = r20r21r22r23
;*
;
***************************************************************************
.def sub20 = r16 ; subtrahend byte 0 (LSB)
.def sub21 = r17 ; subtrahend byte 1
.def sub22 = r18 ; subtrahend byte 2
.def sub23 = r19 ; subtrahend byte 3 (MSB)
.def sub10 = r20 ; minuend byte 0 (LSB)
.def sub11 = r21 ; minuend byte 1
.def sub12 = r22 ; minuend byte 2
.def sub13 = r23 ; minuend byte 3 (MSB)

Sub32sign: clt ;sign +

Sub32: sub sub10,sub20 ;Subtract
low bytes
sbc sub11,sub21 ;Subtract higher
bytes with carry
sbc sub12,sub22 ;
sbc sub13,sub23 ;
brcc Return32u ;return clear carry
if result>=0
set ;sign -
Neg32: subi sub10,1 ;if result<0
sbci sub11,0 ; neg result
sbci sub12,0 ;
sbci sub13,0 ; (dec result)
Com32: com sub10 ; &
com sub11 ; (com result)
com sub12 ;
com sub13 ; return set
carry after com
Return32u: ret ;

;
***************************************************************************
;*
;* Mul32 == 32x32 Bit Unsigned Multiplication
;*
;* mp32uL::mp32uH x mc32uL::mc32uH = m32uL::m32uH
;* multiplier multiplicand result
;* r20r21r22r23 x r16r17r18r19 =
r20r21r22r23r24r25r26r27
;*
;
***************************************************************************
.def mc32u0 =r16 ; multiplicand byte 0 (LSB)
.def mc32u1 =r17 ; multiplicand byte 1
.def mc32u2 =r18 ; multiplicand byte 2
.def mc32u3 =r19 ; multiplicand byte 3 (MSB)
.def mp32u0 =r20 ; multiplier byte 0 (LSB)
.def mp32u1 =r21 ; multiplier byte 1
.def mp32u2 =r22 ; multiplier byte 2
.def mp32u3 =r23 ; multiplier byte 3 (MSB)
.def m32u0 =r20 ; result byte 0 (LSB)
.def m32u1 =r21 ; result byte 1
.def m32u2 =r22 ; result byte 2
.def m32u3 =r23 ; result byte 3
.def m32u4 =r24 ; result byte 4
.def m32u5 =r25 ; result byte 5
.def m32u6 =r26 ; result byte 6
.def m32u7 =r27 ; result byte 7 (MSB)
.def mcnt32u =r28 ; loop counter

Mul32b: clr mc32u1 ;multiplicand is

one byte
Mul32w: clr mc32u2 ;
two bytes
Mul32t: clr mc32u3 ;
three bytes
Mul32: clr m32u7 ;clear 4
highest bytes of result
clr m32u6 ;
clr m32u5 ;
sub m32u4,m32u4 ;and carry
ldi mcnt32u,33 ;init loop counter
m32u_loop: ror m32u3 ;rotate result and
multiplier
ror m32u2 ;
ror m32u1 ;
ror m32u0 ;
dec mcnt32u ;decrement loop
counter
breq Return32u ;if counter zero
return
brcc m32u_skip ;if bit 0 of
multiplier set
add m32u4,mc32u0 ; add
multiplicand to result
adc m32u5,mc32u1 ;
adc m32u6,mc32u2 ;
adc m32u7,mc32u3 ;
m32u_skip: ror m32u7 ;shift right result
byte 7
ror m32u6 ;rotate right result
ror m32u5 ;
ror m32u4 ;
rjmp m32u_loop ;

;
***************************************************************************
;*
;* Div32 == 32/32 Bit Unsigned Division
;*
;* dd32uL::dd32uH / dv32uL::dv32uH = dres32uL::dres32uH
(drem32uL::drem32uH)
;* dividend divisor
result remainder
;* r20r21r22r23 / r16r17r18r19 =
r20r21r22r23 r24r25r26r27
;*
;
***************************************************************************
.def dv32u0 =r16 ; divisor byte 0 (LSB)
.def dv32u1 =r17 ; divisor byte 1
.def dv32u2 =r18 ; divisor byte 2
.def dv32u3 =r19 ; divisor byte 3 (MSB)
.def dres32u0 =r20 ; result byte 0 (LSB)
.def dres32u1 =r21 ; result byte 1
.def dres32u2 =r22 ; result byte 2
.def dres32u3 =r23 ; result byte 3 (MSB)
.def dd32u0 =r20 ; dividend byte 0 (LSB)
.def dd32u1 =r21 ; dividend byte 1
.def dd32u2 =r22 ; dividend byte 2
.def dd32u3 =r23 ; dividend byte 3 (MSB)
.def drem32u0 =r24 ; remainder byte 0 (LSB)
.def drem32u1 =r25 ; remainder byte 1
.def drem32u2 =r26 ; remainder byte 2
.def drem32u3 =r27 ; remainder byte 3 (MSB)
.def dcnt32u =r28 ; loop counter

Div32b: clr dv32u1 ;divisor is one byte

Div32w: clr dv32u2 ; two
bytes
Div32t: clr dv32u3 ; three
bytes
Div32: clr drem32u0 ;clear 4
lower remainde byte
clr drem32u1 ;
clr drem32u2 ;
sub drem32u3,drem32u3;and carry
ldi dcnt32u,33 ;init loop counter
d32u_loop: rol dd32u0 ;shift left dividend
rol dd32u1 ;
rol dd32u2 ;
rol dd32u3 ;
dec dcnt32u ;decrement loop
counter
breq Com32 ;if counter zero
invert result
rol drem32u0 ;shift dividend
into remainder
rol drem32u1 ;
rol drem32u2 ;
rol drem32u3 ;
sub drem32u0,dv32u0 ;remainder =
remainder - divisor
sbc drem32u1,dv32u1 ;
sbc drem32u2,dv32u2 ;
sbc drem32u3,dv32u3 ;
brcc d32u_loop ;clear carry to be
shifted into res
add drem32u0,dv32u0 ;if result negative
adc drem32u1,dv32u1 ; restore
remainder
adc drem32u2,dv32u2 ;
adc drem32u3,dv32u3 ;
rjmp d32u_loop ; set carry to be
shifted into res

;
***************************************************************************
;*
;* BCD2bin == BCD to 16-Bit Binary Conversion
;*
;* fBCD0:fBCD1:fBCD2 >>> tbinL:tbinH
;* dec hex
;* r16r17r18 >>> r20r21
;*
;
***************************************************************************
.def fBCD0 =r16 ; BCD value digits 0 and 1
.def fBCD1 =r17 ; BCD value digits 2 and 3
.def fBCD2 =r18 ; BCD value digit 4 (MSD is
lowermost nibble)
.def mp10L =r20 : Low byte of number to be
multiplied by 10
.def mp10H =r21 ; High byte of number to be
multiplied by 10
.def tbinL =r20 ; Low byte of binary result
(same as mp10L)
.def tbinH =r21 ; High byte of binary
result (same as mp10H)
.def copyL =r22 ; temporary register
.def copyH =r23 ; temporary register

BCD2bin20: mov r16,r20 ;for compatibility

with Math32
mov r17,r21 ;
mov r18,r22 ;
BCD2bin16: cbr fBCD2,0xf0 ;mask away upper
nibble of fBCD2
mov mp10L,fBCD2 ;mp10L:mp10H = MSD
clr mp10H ;
clr fBCD2 ;for adci mp10H,0
below
rcall mul10bcd ;fBCDX = fBCD1
mov fBCD1,fBCD0 ;fBCDX = fBCD0
mul10bcd: ;mp10L:mp10H=10(10*mp10L:mp10H+highnibble
(fBCDX))+lownibble(fBCDX)
rcall mul10add ;10*mp10L:mp10H
+highnibble(fBCDX)
mul10add: ;mp10L:mp10H = 10*mp10L:mp10H+lownibble(fBCDX)
lsl mp10L ;multiply original
by 2
rol mp10H ;
mov copyL,mp10L ;make copy (x2)
mov copyH,mp10H ;
lsl copyL ;multiply copy by 2
(x4)
rol copyH ;
lsl copyL ;multiply copy by 2
(x8)
rol copyH ;
add mp10L,copyL ;add copy to
original (x10)
adc mp10H,copyH ;
swap fBCD1 ;fBCDX
upper<=>lower nibble
mov copyL,fBCD1 ;
andi copyL,0x0f ;mask away upper
nibble
add mp10L,copyL ;add lower nibble
adc mp10H,fBCD2 ;high byte of
result + carry
ret ;
.equ BCD2bin=BCD2bin20 ;default registers BCD to BIN
call

;
***************************************************************************
;*
;* BCD3bin == BCD to 24-Bit Binary Conversion
;*
;* fBCD0:fBCD1:fBCD2:fBCD3 >>> tbin0:tbin1:tbin2
;* dec hex
;* r16r17r18r19 >>> r20r21r22
;*
;
***************************************************************************
.def fBCD0 =r16 ; BCD value digits 0 and 1
.def fBCD1 =r17 ; BCD value digits 2 and 3
.def fBCD2 =r18 ; BCD value digits 4 and 5
.def fBCD3 =r19 ; BCD value digits 6 and 7
(MSD is 0|1)
.def tbin0 =r20 ; binary value byte 0 (LSB)
.def tbin1 =r21 ; binary value byte 1
.def tbin2 =r22 ; binary value byte 2 (MSB)

BCD3bin20: mov r16,r20 ;for compatibility

with Math32
mov r17,r21 ;
mov r18,r22 ;
mov r19,r23 ;
BCD3bin16: ldi tbin0,0xca ;digit-to-
digit presetting
ldi tbin1,0x1b ;-
1111110=0xef0bba
ldi
tbin2,0xff ;0xff1bca=0xef0bba-0xefeff0
sbrc fBCD3,4 ; delete
decimal correction
subi fBCD3,6 ; if
NUMBER<10000000 always
bcdbin_106: subi tbin0,byte1(-1000*1000) ;addit
tbin,10^6
sbci tbin1,byte2(-1000*1000) ;
sbci tbin2,byte3(-1000*1000) ;
subi fBCD3,0x01 ;
brcc bcdbin_106 ;
bcdbin_105: subi tbin0,byte1(-100*1000) ;addit
tbin,10^5
sbci tbin1,byte2(-100*1000) ;
sbci tbin2,byte3(-100*1000) ;
subi fBCD2,0x10 ;
brcc bcdbin_105 ;
bcdbin_104: subi tbin0,byte1(-10*1000) ;addit
tbin,10^4
sbci tbin1,byte2(-10*1000) ;
sbci tbin2,byte3(-10*1000) ;
subi fBCD2,0x01 ;
brhc bcdbin_104 ;
bcdbin_103: subi tbin0,byte1(-1000) ;addit
tbin,10^3
sbci tbin1,byte2(-1000) ;
sbci tbin2,byte3(-1000) ;
subi fBCD1,0x10 ;
brcc bcdbin_103 ;
bcdbin_102: subi tbin0,byte1(-100) ;addit
tbin,10^2
sbci tbin1,byte2(-100) ;
sbci tbin2,byte3(-100) ;
subi fBCD1,0x01 ;
brhc bcdbin_102 ;
bcdbin_101: subi tbin0,byte1(-10) ;addit
tbin,10^1
sbci tbin1,byte2(-10) ;
sbci tbin2,byte3(-10) ;
subi fBCD0,0x10 ;
brcc bcdbin_101 ;addit
tbin,0xefeff0+LSD
add tbin0,fBCD0 ; addend of
tbin1 & tbin2 is
adc tbin1,fBCD1 ;
arbitrarily chosen const
adc tbin2,fBCD2 ; (pre take
off from tbin)
ret

http://avr-asm.tripod.com/math32x.html (1 of 3)1/20/2009 8:37:55 PM

16 BIT MATH (AVR 202)

.equ BCD3bin=BCD3bin20 ;default registers BCD to BIN

call

;
***************************************************************************
;*
;* Bin2BCD == 16-bit Binary to BCD conversion
;*
;* fbinL:fbinH >>> tBCD0:tBCD1:tBCD2
;* hex dec
;* r16r17 >>> r20r21r22
;*
;
***************************************************************************
.def fbinL =r16 ; binary value Low byte
.def fbinH =r17 ; binary value High byte
.def tBCD0 =r20 ; BCD value digits 0 and 1
.def tBCD1 =r21 ; BCD value digits 2 and 3
.def tBCD2 =r22 ; BCD value digit 4 (MSD is
lowermost nibble)

Bin2BCD20: mov r16,r20 ;for compatibility

with Math32
mov r17,r21 ;
Bin2BCD16: ldi tBCD2,0xff ;initialize digit 4
binbcd_4: inc tBCD2 ;
subi fbinL,low(10000);subiw fbin,10000
sbci fbinH,high(10000)
brcc binbcd_4 ;
ldi tBCD1,0x9f ;initialize digits
3 and 2
binbcd_3: subi tBCD1,0x10 ;
subi fbinL,low(-1000);addiw fbin,1000
sbci fbinH,high(-1000)
brcs binbcd_3 ;
binbcd_2: inc tBCD1 ;
subi fbinL,low(100) ;subiw fbin,100
sbci fbinH,high(100) ;
brcc binbcd_2 ;
ldi tBCD0,0xa0 ;initialize digits
1 and 0
binbcd_1: subi tBCD0,0x10 ;
subi fbinL,-10 ;addi fbin,10
brcs binbcd_1 ;
add tBCD0,fbinL ;LSD
binbcd_ret: ret ;
.equ Bin2BCD=Bin2BCD20 ;default registers BIN to BCD
call

;
***************************************************************************
;*
;* Bin4BCD == 32-bit Binary to BCD conversion
[ together with Bin2BCD ]
;*
;* fbin0:fbin1:fbin2:fbin3 >>> tBCD0:tBCD1:tBCD2:
tBCD3:tBCD4
;* hex dec
;* r18r19r20r21 >>> r20r21r22r23r24
;*
;
***************************************************************************
.def fbin0 =r18 ; binary value byte 0 (LSB)
.def fbin1 =r19 ; binary value byte 1
.def fbin2 =r20 ; binary value byte 2
.def fbin3 =r21 ; binary value byte 3 (MSB)
.def tBCD0 =r20 ; BCD value digits 0 and 1
(same as fbin2)
.def tBCD1 =r21 ; BCD value digits 2 and 3
(same as fbin3)
.def tBCD2 =r22 ; BCD value digits 4 and 5
.def tBCD3 =r23 ; BCD value digits 6 and 7
.def tBCD4 =r24 ; BCD value digits 8 and 9
(MSD)

Bin4BCD: rcall Bin2BCD20 ;

clr tBCD3 ;initial highest
bytes of result
ldi tBCD4,0xfe ;
binbcd_loop: subi tBCD0,-0x33 ;add 0x33
to digits 1 and 0
sbrs tBCD0,3 ;if bit 3 clear
subi tBCD0,0x03 ; sub 3
sbrs tBCD0,7 ;if bit 7 clear
subi tBCD0,0x30 ; sub $30
subi tBCD1,-0x33 ;add 0x33 to digits
3 and 2
sbrs tBCD1,3 ;if bit 3 clear
subi tBCD1,0x03 ; sub 3
sbrs tBCD1,7 ;if bit 7 clear
subi tBCD1,0x30 ; sub $30
subi tBCD2,-0x33 ;add 0x33 to digits
5 and 4
sbrs tBCD2,3 ;if bit 3 clear
subi tBCD2,0x03 ; sub 3
sbrs tBCD2,7 ;if bit 7 clear
subi tBCD2,0x30 ; sub $30
lsl fbin0 ;
rol fbin1 ;shift lower word
rol tBCD0 ;through all bytes
rol tBCD1 ;
rol tBCD2 ;
rol tBCD3 ;
rol tBCD4 ;
brmi binbcd_loop ;7 shifts w/o
correction of MSD
rol fbinH ;since Bin2BCD
fbinH = 0xff
brcc binbcd_ret ; so as to do
16_lsl in total
subi tBCD3,-0x33 ;add 0x33 to digits
7 and 6
sbrs tBCD3,3 ;if bit 3 clear
subi tBCD3,0x03 ; sub 3
sbrs tBCD3,7 ;if bit 7 clear
subi tBCD3,0x30 ; sub $30
subi tBCD4,-0x03 ;add 0x03 to digit
8 only
sbrs tBCD4,3 ;if bit 3 clear
subi tBCD4,0x03 ; sub 3
rjmp binbcd_loop ;

;
***************************************************************************
;*
;* Bin4BCD == 32-bit Binary to BCD conversion
;*
;* fbin0:fbin1:fbin2:fbin3 >>> tBCD0:tBCD1:tBCD2:
tBCD3:tBCD4
;* hex dec
;* r16r17r18r19 >>> r20r21r22r23r24
;*
;
***************************************************************************
.def fbin0 =r16 ; binary value byte 0 (LSB)
.def fbin1 =r17 ; binary value byte 1
.def fbin2 =r18 ; binary value byte 2
.def fbin3 =r19 ; binary value byte 3 (MSB)
.def tBCD0 =r20 ; BCD value digits 0 and 1
.def tBCD1 =r21 ; BCD value digits 2 and 3
.def tBCD2 =r22 ; BCD value digits 4 and 5
.def tBCD3 =r23 ; BCD value digits 6 and 7
.def tBCD4 =r24 ; BCD value digits 8 and 9
(MSD)

Bin4BCD20: mov r16,r20 ;for compatibility

with Math32
mov r17,r21 ;
mov r18,r22 ;
mov r19,r23 ;
Bin4BCD16: clr tBCD0 ;initial result (5
bytes)
clr tBCD1 ; & shift
clr tBCD2 ; loop
ldi tBCD3,0xfe ;
counter
ldi
tBCD4,0xff ; too
rjmp binbcd_jump ;for speed-up and
skip of MSD corr
binbcd_876: subi tBCD4,-0x03 ;add 0x03 to digit
8 only
sbrs tBCD4,3 ;if bit 3 clear
subi tBCD4,0x03 ; sub 3
subi tBCD3,-0x33 ;add 0x33 to digits
7 and 6
sbrs tBCD3,3 ;if bit 3 clear
subi tBCD3,0x03 ; sub 3
sbrs tBCD3,7 ;if bit 7 clear
subi tBCD3,0x30 ; sub $30
binbcd_54: subi tBCD2,-0x33 ;add 0x33 to digits
5 and 4
sbrs tBCD2,3 ;if bit 3 clear
subi tBCD2,0x03 ; sub 3
sbrs tBCD2,7 ;if bit 7 clear
subi tBCD2,0x30 ; sub $30
binbcd_3210: subi tBCD1,-0x33 ;add 0x33
to digits 3 and 2
sbrs tBCD1,3 ;if bit 3 clear
subi tBCD1,0x03 ; sub 3
sbrs tBCD1,7 ;if bit 7 clear
subi tBCD1,0x30 ; sub $30
subi tBCD0,-0x33 ;add 0x33 to digits
1 and 0
sbrs tBCD0,3 ;if bit 3 clear
subi tBCD0,0x03 ; sub 3
sbrs tBCD0,7 ;if bit 7 clear
subi tBCD0,0x30 ; sub $30
binbcd_jump: lsl fbin0 ;
rol fbin1 ;
rol fbin2 ;
rol fbin3 ;shift input value
rol tBCD0 ;through all bytes
rol tBCD1 ;
rol tBCD2 ;
rol tBCD3 ;
rol tBCD4 ;
brcs binbcd_3210 ;16_lsl w/o
correction of dig_87654
inc fbin0 ;
brpl binbcd_54 ;+7_lsl w/o
correction of dig_876
sbrs fbin2,0 ;
rjmp binbcd_876 ;32_lsl in total
(fbin = 0x1ffff)
ret ;

;
***************************************************************************
;*
;* Bin3BCD == 24-bit Binary to BCD conversion
[ together with Bin2BCD ]
;*
;* fbin0:fbin1:fbin2 >>> tBCD0:tBCD1:tBCD2:tBCD3
;* hex dec
;* r16r17r18 >>> r20r21r22r23
;*
;
***************************************************************************
.def fbin0 =r16 ; binary value byte 0 (LSB)
.def fbin1 =r17 ; binary value byte 1
.def fbin2 =r18 ; binary value byte 2 (MSB)
.def tBCD0 =r20 ; BCD value digits 0 and 1
.def tBCD1 =r21 ; BCD value digits 2 and 3
.def tBCD2 =r22 ; BCD value digits 4 and 5
.def tBCD3 =r23 ; BCD value digits 6 and 7
(MSD)

Bin3BCD: ldi tBCD3,0xff ;initialize

digits 7 and 6
binbcd_7: inc tBCD3 ;
subi fbin0,byte1(10000*100) ;subit
fbin,1000000
sbci fbin1,byte2(10000*100) ;
sbci fbin2,byte3(10000*100) ;
brcc binbcd_7 ;
subi tBCD3,-6 ; delete
decimal correction
sbrs tBCD3,4 ; if
NUMBER<10000000 always
subi tBCD3,6 ;
ldi tBCD2,0x9f ;initialize
digits 5 and 4
binbcd_6: subi tBCD2,0x10 ;
subi fbin0,byte1(-10000*10) ;addit
fbin,100000
sbci fbin1,byte2(-10000*10) ;
sbci fbin2,byte3(-10000*10) ;
brcs binbcd_6 ;
binbcd_5: inc tBCD2 ;
subi fbin0,byte1(10000) ;subit
fbin,10000
sbci fbin1,byte2(10000) ;
sbci fbin2,byte3(10000) ;
brcc binbcd_5 ;
rjmp binbcd_3-1 ;initialize
digits 3 and 2

;
***************************************************************************
;*
;* Bin3BCD == 24-bit Binary to BCD conversion
;*
;* fbin0:fbin1:fbin2 >>> tBCD0:tBCD1:tBCD2:tBCD3
;* hex dec
;* r16r17r18 >>> r20r21r22r23
;*
;
***************************************************************************
.def fbin0 =r16 ; binary value byte 0 (LSB)
.def fbin1 =r17 ; binary value byte 1
.def fbin2 =r18 ; binary value byte 2 (MSB)
.def tBCD0 =r20 ; BCD value digits 0 and 1
.def tBCD1 =r21 ; BCD value digits 2 and 3
.def tBCD2 =r22 ; BCD value digits 4 and 5
.def tBCD3 =r23 ; BCD value digits 6 and 7
(MSD)

Bin3BCD20: mov r16,r20 ;for compatibility

with Math32
mov r17,r21 ;
mov r18,r22 ;
Bin3BCD16: ldi tBCD3,0xfa ;initialize
digits 7 and 6
binbcd_107: subi tBCD3,-0x10 ;
subi fbin0,byte1(10000*1000) ;subit
fbin,10^7
sbci fbin1,byte2(10000*1000) ;
sbci fbin2,byte3(10000*1000) ;
brcc binbcd_107 ;
binbcd_106: dec tBCD3 ;
subi fbin0,byte1(-10000*100) ;addit
fbin,10^6
sbci fbin1,byte2(-10000*100) ;
sbci fbin2,byte3(-10000*100) ;
brcs binbcd_106 ;
ldi tBCD2,0xfa ;initialize
digits 5 and 4
binbcd_105: subi tBCD2,-0x10 ;
subi fbin0,byte1(10000*10) ;subit
fbin,10^5
sbci fbin1,byte2(10000*10) ;
sbci fbin2,byte3(10000*10) ;
brcc binbcd_105 ;
binbcd_104: dec tBCD2 ;
subi fbin0,byte1(-10000) ;addit
fbin,10^4
sbci fbin1,byte2(-10000) ;
sbci fbin2,byte3(-10000) ;
brcs binbcd_104 ;
ldi tBCD1,0xfa ;initialize
digits 3 and 2
binbcd_103: subi tBCD1,-0x10 ;
subi fbin0,byte1(1000) ;subiw
fbin,10^3
sbci fbin1,byte2(1000) ;
brcc binbcd_103 ;
binbcd_102: dec tBCD1 ;
subi fbin0,byte1(-100) ;addiw
fbin,10^2
sbci fbin1,byte2(-100) ;
brcs binbcd_102 ;
ldi tBCD0,0xfa ;initialize
digits 1 and 0
binbcd_101: subi tBCD0,-0x10 ;
subi fbin0,10 ;subi
fbin,10^1
brcc binbcd_101 ;
add tBCD0,fbin0 ;LSD
ret ;

;
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Demo: ;-)(-:-)(-;-)(-:-)(-;-)(-:-)(-;-)(-:-)(-;-)
(-:-)(-;-)(-:-)(-;-)(-:-)

;
***************************************************************************
;$ $ $ $ $ $ $ $ $ Illustrations with comments
field $ $ $ $ $ $ $ $ $
;
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.dseg
Variable: .byte 4
VarWord1: .byte 2
VarWord2: .byte 2
Result: .byte 8
.equ Address1 =VarWord1
.equ Address2 =VarWord2
.equ Address =Variable
.set Constant =0x4321

.cseg
.def Temp =r16
.def TempL =r16
.def TempH =r17
.def Flags =r15
.equ _Flag1 =1
.equ _Flag2 =2
.equ _Flag3 =3
.equ _signResult=0

;*** OUTI, OUTIW, OUTW, INW

outiw SP,Temp,RAMEND ;initialize 16-bit
Stack Pointer
outi TCNT0,Temp,0 ;clear Timer/
Counter0 (8-bit)
inw Temp,TCNT1 ;read Timer/
Counter1 (16-bit)
outw TCNT1,Temp ;write Timer/
Counter1 (16-bit)

;*** CLF, SEF, CBF, SBF, IBF

clf Flags,_Flag1 ;clear (0)
bit _Flag1
bld Flags,_Flag2 ; and
bit _Flag2
cbf Flags,Temp,_Flag1,_Flag2 ;clear
both at once
sef Flags,_Flag1 ;set (1)
bit _Flag1
bld Flags,_Flag2 ; and
bit _Flag2
sbf Flags,Temp,_Flag1,_Flag2 ;set both
at once
ibf Flags,Temp,_Flag1,_Flag2,_Flag3 ;
invert of 3 flags
ibf TempL,TempH,0,2,4,6 ;invert
only even bits

;*** XCH, MVW, MVI, MOVS, MOVSW

xch TempL,TempH ;swap in Temp
register pair
xch Temp,r0 ;swap bytes r0 &
Temp
mvw X,Y ;copy of Y register pair
into X pair
mvw Z,Temp ;copy of TempL&TempH into Z
register pair
mvi Flags,Temp,exp2(_Flag1)|1<<_Flag2 ;
initialize flags
mvi r0,Temp,Constant ;load to
low register (0-15)
movs Address1,Temp,Address2 ;copy of
one memory byte
movsw Address1,Temp,Address2 ;copy of
two memory bytes

;*** STSI, STSIW, LDSW, STSW

stsi Address,Temp,Constant ;initialize
of one memory byte
stsiw Address,Temp,Constant ;initialize
of two memory bytes
ldsw Temp,Address1 ;copy of two memory
bytes
stsw Address2,Temp ; via Temp
register pair

;*** LDIW, LDDW, STDW

ldiw Temp,Constant ;initialize of
register pair
ldiw Z,Address ;initialize of
address pointer
lddw Temp,Z+(Address1-Address) ;copy of
two memory bytes
stdw Z+(Address2-Address),Temp ; via
Temp register pair

;*** PUSHW, POPW

pushw Y ;copy of Y register
pair
popw X ; into X register
pair
ldiw Temp,Maths
pushw Temp
ret ;equ jmp Maths
Maths:
;***** INITMEM
InitMem Address ;clear 128 bytes
(latest Address+127)
InitMem Address,0 ;equ InitMem Address
InitMem Address,0,0 ;equ InitMem Address
InitMem Address,,1 ;for 128 bytes each:
=0xff
InitMem Address,1 ;clear one byte at
Address
InitMem Address1,Address2-Address1+2,Limit
;limitation: if bit_T=0 then 4_bytes:=0xff
else 4_bytes:=0
ldi MathPattern,0xab
InitMem Address,,+1 ;128_bytes:=0xab
doubly, but possibly

;***** MATHR16, MATHR20, OPERAND

Operand Address ;equ MathR20
Address,obXXXX
MathR20 Address ;equ Operand Address
.set ObXXXX=0b11
MathR16 Address ;equ Operand
Address,0b0011,r16
.set ObXXXX=0b1111 ;default
Operand Address,,r16 ;equ MathR16
Address,obXXXX
Operand Address,,r20 ;equ MathR20
Address,obXXXX
Operand Address,0b11 ;equ MathR20
Address,0b0011
Operand Address,0b11,r16;equ MathR16
Address,0b0011
;load data with displacement (equ *256, *65536,
*16777216)
MathR20 Address,0b0110 ;(data word)
<<8
MathR16 Address,0b1000 ;(data byte)
<<24

;***** CONST20, CONST16, CNST16T

; WARNING: AVRASM ver. 1.30 don't understand 32 bits
constants, but all it
; expressions are internally 32 bits (the higher
versions of assembler
; directly operate on value up to 0xffffffff)
Const20 0x76543210 ;error
v1.30 (0x00003210)
Const20 1985229328 ;error
v1.30 (12816)
Const16 0x7654<<16|0x3210 ;ok
(0x76543210)
Cnst16t 0x7654*1024*1024+0x1234 ;ok
(0x401234)

;***** CNST16B, CNST16W

Cnst16b Constant ;equ Const16 byte1
(Constant)
rcall Div32b ; rcall Div32 ;
but briefly
Cnst16w Constant<<1 ;non-equ Const16
Constant<<1
rcall Mul32w ; rcall
Mul32 ;word overflow

;***** RESULT2, RESULT3

Result2 Address ;equ Result2
Address,obXXXX
;store data with displacement
(equ /256, /65536, /16777216 and more)
Result2 Address,1<<7 ;(byte
result)>>56
Result2 Address,0b111100 ;(double
word result)>>16
Result2 Address,obXXXX<<4 ;(double
word result)>>32
rjmp JointTail+3
JointTail: Result3 Address,0xff ;equ Result2
Address,0b11111111
rcall JointTail ;concluding RET
inside Result call

;******* register pairs

.def AL=r16
.def AH=r17
.def BL=r18
.def BH=r19
.def CL=r20
.def CH=r21
.def DL=r22
.def DH=r23
.def WL=r24
.def WH=r25
ldiw C,0 ;equ
ldiw D,0x7654 ; Const20
0x7654<<16
ldiw A,0x3210 ;equ Cnst16w 0x3210
ldi AL,0x10 ;equ Cnst16b 0x10
mvw A,C ;copy of Const20
mvw B,D ; into Const16
adiw WL,1 ;as well as "adiw" for X,Y,
Z register pairs
sbiw WL,1 ;as well as "sbiw" for X,Y,
Z register pairs

;******* testing calculations

InitMem Variable,4,1 ;
0xffffffff to memory

Operand Variable
Const16 0xffff<<16|0xffff
rcall Mul32 ;
0xffffffff * 0xffffffff
Result2 Result,0b11111111 ;
0xfffffffe00000001

Operand Variable
Const16 0x1010<<16|0x1010
rcall Div32 ;
0xffffffff / 0x10101010
Result2 Result,0b11111111 ; 0xf
(0x0f0f0f0f)

Operand Variable,0b111
Cnst16t 0x00ff<<16|0xffff
rcall Div32t ;
0xffffff / 0xffffff
Result2 Result ; 0x1 (0x0
no rollout)

Operand Variable,0b1100
Cnst16w 0xffff
rcall Div32w ;
0xffff0000 / 0xffff
Result2 Result ; 0x10000
(0x0 no rollout)

;******* data translations 16-bit (overall maximum

65535=0xffff)
;result Rd16|24
Const20 0x2748
rcall BCD2bin ;02748 = 0x0abc
Cnst16t 6<<16|0x5535
rcall BCD2bin16 ;65535 = 0xffff
Result2 Address,0b11
rcall Bin2BCD ;0xffff = 65535
Cnst16w 0xabba
rcall Bin2BCD16 ;0xabba = 43962

;******* data translations 32-bit (overall maximum

655359999=0x270fffff)
;BCD2Bin
stsiw Variable,Temp,0x5432 ;
stsiw Variable+2,Temp,0x9876 ;BCD
98765432 >>>
Operand Variable,0b11
rcall BCD2bin
pushw C ;temporary result
always is 2 bytes
Operand Variable+2,0b11 ;or 0b111 if BCD
have all 5 digits
rcall BCD2bin
ldiw D,0
Cnst16w 10000
rcall Mul32w
popw A ;B pair by this
time =0
rcall Add32
Result2 Result,0b1111 ;>>> HEX
0x05e30a78
;Bin2BCD
stsiw Variable,Temp,0xffff ;
stsiw Variable+2,Temp,0x270f ;HEX
0x270fffff >>>
Operand Variable,0b1111
Cnst16w 10000 ;remainder always
is 2 bytes
rcall Div32w ; as
temporary result
rcall Bin2BCD
Result2 Result+2,0b111
mvw A,W ;W pair do not
changed beyond
rcall Bin2BCD16
Result2 Result,0b11 ;>>> BCD
655359999

;******* 32-bit Bin4BCD conversion (overall maximum

4294967295=0xffffffff)
;result Rd40
ldi YL,18 ;one more dishonest
trick
Operand Variable,0b1111,1+
rcall Bin4BCD ;0x270fffff >>>
655359999
Const20 0x1234<<16|0x5678
Result2 18
rcall Bin4BCD ;0x12345678 >>>
305419896
Const16 0xab98<<16|0xfedc
mvw C,A
rcall Bin4BCD ;0xfedcab98 >>>
4275874712
InitMem Variable,3,1 ; 0xffffff to memory
MathR20 Variable,0b111
MathR16 Variable,0b111
rcall Mul32t ;(0xffffff)^2 =
0xfffffe000001
Result2 18,0b111100 ; /65536 =
0xfffffe00
rcall Bin4BCD ;0xfffffe00 >>>
4294966784

;******* data translations 32-bit (overall maximum

4294967295=0xffffffff)
;Bin4BCD20
Operand Variable,0b1111
rcall Bin4BCD20 ;0x27ffffff >>>
671088639
Const20 0x1234<<16|0x5678
rcall Bin4BCD20 ;0x12345678 >>>
305419896
ldiw D,0
ldiw C,0xab
rcall Bin4BCD20 ; 0xab >>> 171
;Bin4BCD16
rcall Bin4BCD16 ; 0x1ffff >>>
131071
Const16 0xfedc<<16|0xab98
rcall Bin4BCD16 ;0xfedcab98 >>>
4275874712
InitMem Variable,4,1
MathR16 Variable,0b1111
rcall Bin4BCD16 ;0xffffffff >>>
4294967295

;******* data translations 24-bit (overall maximum

16777215=0xffffff)
;BCD3bin
Const20 $1670<<16|$2650
rcall BCD3bin ;16702650 >>>
0xfedcba
ldiw B,0
ldiw A,9
rcall BCD3bin16 ;00000009 >>>
0x000009 (fastest)
ldiw D,0x1599
ldiw C,0x9990
rcall BCD3bin20 ;15999990 >>>
0xf423f6 (slowest)
;Bin3BCD
Const16 0x98<<16|0x967f
rcall Bin3BCD ;0x98967f >>>
09999999
rcall Bin3BCD ;0xffff09 >>>
16776969
Cnst16t $0d00*256+$df22
rcall Bin3BCD ;0x0ddf22 >>>
00909090 (fastest)
Cnst16t $f500*256+$871d
rcall Bin3BCD ;0xf5871d >>>
16090909 (slowest)
;Bin3BCD20
MathR20 Variable,0b111
rcall Bin3BCD20 ;0xffffff >>>
16777215
rcall Bin3BCD20 ;0x777215 >>>
07827989
Const20 $a600*256+$75a2
rcall Bin3BCD20 ;0xa675a2 >>>
10909090 (slowest)
;Bin3BCD16
Cnst16t $8a00*256+$b75d
rcall Bin3BCD16 ;0x8ab75d >>>
09090909 (fastest)
ldi AH,0xff
rcall Bin3BCD16 ; 0xffff >>> 65535
ldi AL,0
rcall Bin3BCD16 ;0x000000 >>>
00000000

;******* formula recalculation: Result=(VarWord1-

0xfff)/7+VarWord2/0x100
;VarWordX>=0
InitMem Variable,16 ;clear
VarWordX & Result
rcall Formula ; -
0x249.0000 as result

ldiw Temp,0xabcd ;these 2

lines are not equ
stsw VarWord1,Temp ;stsiw
VarWord1,Temp,0xabcd
stsw VarWord2,Temp
rcall Formula ; 0x16ed.
cd00 as result

stsiw VarWord1,Temp,0x00ff
stsiw VarWord2,Temp,0xff00
rcall Formula ; -
0x125.9249 as result

stsiw VarWord1,Temp,0x0f0f
stsiw VarWord2,Temp,0xf0f0
rcall Formula ; 0x00ce.
a6dc as result

InitMem VarWord1,4,1 ;
0x2349.2392 at the end
ldiw Temp,Demo
pushw Temp ;getting
into demo loop
Formula:
MathR20 VarWord1,0b1100
Const16 0xfff<<16
rcall Sub32sign
Cnst16b 7
rcall Div32b
Result2 16 ;faster than call
MathR16 20
MathR16 20 ;included for
comparison only
MathR20 VarWord2,0b110
rcall Add32sign
bld Flags,_signResult
Result3 Result
.exit
;
***************************************************************************
;*
;* REMARK
;* Sometimes expression as macroparameter must be
enclosed in parentheses,
;* because they not are always present in above
macrocalls
;* (remember about the priority of AVR assembler
operators).
;* Accommodate oneself to ATmega: MOVW instruction e.
g., etc.
;*
;
***************************************************************************
;Feedback: please, include abbr."Math32" in Your e-mail
subject line (!spam)
;from time to time it is possible mailbox overflow &|
shut-down - I am sorry
;to make mention of http://www.i.com.ua/~birua when
occasion offers - Thanks
;All the best & good luck!

Programming the AVR Microcontrollers in Machine Language

AVR
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© WebRing Inc. Search

Atmel AVR From Wikipedia, the free encyclopedia (Redirected

from Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing,
intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still
be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
http://avr-asm.tripod.com/math32x.html (2 of 3)1/20/2009 8:37:55 PM
16 BIT MATH (AVR 202)

have different addressing capabilities than register locations

R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language

http://avr-asm.tripod.com/math32x.html (3 of 3)1/20/2009 8:37:55 PM

AVR MATH YX

The AVR Assembler Site

MATH YX PACKAGE
HOME
RETRO_DAN
;**** A P P L I C A T I O N N O T E A V R 2 0 2
ASM FORUM ************************
ASM MATH ;*
;* Title: 16-bit Arithmetics
TUTORIAL #1
;* Version: 1.1
TUTORIAL #2 ;* Last updated: 97.07.04
TUTORIAL #3 ;* Target: AT90Sxxxx (All AVR Devices)
;*
MATH 200 ;* Support E-mail: avr@atmel.com
MATH 200b ;*
;* DESCRIPTION
MATH 201 ;* This application note lists applications for the
MATH 202 following
;* Add/Subtract/Compare operations:
MATH 32X
;*
MATH YX ;* "add16" ADD 16+16
;* "adddi16" ADD 16+Immediate(16)
DIV16 XX
;* "sub16" SUB 16-16
DIV 24 24 ;* "subi16" SUB 16-Immediate(16)
DIV 3216 ;* "cp16" COMPARE 16/16
;* "cpi16" COMPARE 16/Immediate
FLOAT 128 ;* "neg16" NEGATION 16
SQRT16 ;*
;
MATH 202 ***************************************************************************
MATH 202
.cseg
DEC ASCII
ldi r16,0x12 ;Set up some registers to
INT ASCII show usage of
ldi r17,0x34 ;the subroutines below.
HX2ASC
ldi r18,0x56 ;All expected results are
AVG8 222 presented as
FFT7 ldi r19,0x78 ;comments

COPY 102
LPM 108 ;
***************************************************************************
EPROM 100 ;*
SER EPROM ;* "add16" - Adding 16-bit registers
;*
DFLASH AT45
;* This example adds the two pairs of register
FLASH CARD variables (add1l,add1h)
;* and (add2l,add2h) The result is placed in (add1l,
VFX SMIL
add1h).
VFX MEM ;*
SORT 220 ;* Number of words :2
;* Number of cycles :2
CRC 236 ;* Low registers used :None
XMODEM REC ;* High registers used :4
;*
UART 304 ;* Note: The sum and the addend share the same
UART 305 register. This causes the
;* addend to be overwritten by the sum.
UART 128
;*
UART BUFF ;
***************************************************************************
USB 232
AVR ISP ;**** Register Variables
ISP 2313 .def add1l = r16
.def add1h = r17
ISP 1200 .def add2l = r18
AVR SPI .def add2h = r19
I2C 300 ;***** Code
I2C 302 add16: add add1l, add2l ;Add low
bytes
I2C TWI26
adc add1h, add2h ;Add high bytes
I2C/TWI 128 with carry
I2C/TWI AT8 ;Expected result is 0xAC68

DALLAS-1W
DALLAS CRC
;
ETHNET 8019 ***************************************************************************
TEA ;*
;* "addi16" - Adding 16-bit register with immediate
ADC 128 ;*
ADC 10B ;* This example adds a register variable (addi1l,
addi1h) with an
ADC 400
;* immediate 16-bit number defined with .equ-
ADC 401 statement. The result is
THERM 232 ;* placed in (addi1l, addi1h).
;*
IRD 410 ;* Number of words :2
LCD HD44 ;* Number of cycles :2
;* Low registers used :None
LCD 2313 ;* High registers used :2
LCD44 2313 ;*
;* Note: The sum and the addend share the same
KBD 240 register. This causes the
MUX 242 ;* addend to be overwritten by the sum.
;*
KBD PS2
;
KBD PC/128 ***************************************************************************
PS2 EMU
;***** Register Variables
BOOT MG8 .def addi1l = r16
BOOT DR8 .def addi1h = r17

ALM CLK ;***** Immediate 16-bit number

CLOCK 8564 .equ addi2 = 0x1234
90 DAYS
;***** Code
DELAYS addi16: subi add1l, low(-addi2) ;Add low
byte ( x -(-y)) = x + y
CALL ID
sbci add1h, high(-addi2) ;Add high byte with
DTMF 314 carry
PWM 6CH ;Expected result is 0xBE9C

PWM 10K
ENCODE
;
STH-11 ***************************************************************************
ATMEL CORP ;*
;* "sub16" - Subtracting 16-bit registers
AVR
;*
BUTTERFLY ;* This example subtracts two pairs of register
AVR BOOK variables (sub1l,sub1h)
;* from (sub2l, sub2h) The result is stored in
registers sub1l, sub1h.
;*
;* Number of words :2
;* Number of cycles :2
;* Low registers used :None
;* High registers used :4
;*
;* Note: The result and "sub1" share the same
register. This causes "sub1"
;* to be overwritten by the result.
;*
;
***************************************************************************

;***** Register Variables

.def sub1l = r16
.def sub1h = r17
.def sub2l = r18
.def sub2h = r19

;***** Code
sub16: sub sub1l,sub2l ;Subtract
low bytes
sbc sub1h,sub2h ;Add high byte with
carry
;Expected result is 0x4646

;
***************************************************************************
;*
;* "subi16" - Subtracting immediate 16-bit number from
a 16-bit register
;*
;* This example subtracts the immediate 16-bit number
subi2 from the
;* 16-bit register (subi1l,subi1h) The result is
placed in registers
;* subi1l, subi1h.
;*
;* Number of words :2
;* Number of cycles :2
;* Low registers used :None
;* High registers used :2
;*
;* Note: The result and "subi1" share the same
register. This causes
;* "subi1" to be overwritten by the result.
;*
;
***************************************************************************

;***** Register Variables

.def subi1l = r16
.def subi1h = r17

;***** Immediate 16-bit number

.equ subi2 = 0x1234

;***** Code
subi16: subi subi1l,low(subi2) ;Subtract
low bytes
sbci subi1h,high(subi2) ;Subtract high byte
with carry
;Expected result is 0x3412

;
***************************************************************************
;*
;* "cp16" - Comparing two 16-bit numbers
;*
;* This example compares the register pairs (cp1l,cp1h)
with the register
;* pairs (cp2l,cp2h) If they are equal the zero flag
is set(one)
;* otherwise it is cleared(zero)
;*
;* Number of words :2
;* Number of cycles :2
;* Low registers used :None
;* High registers used :4
;*
;* Note: The contents of "cp1" will be overwritten.
;*
;
***************************************************************************

;***** Register Variables

.def cp1l = r16
.def cp1h = r17
.def cp2l = r18
.def cp2h = r19

;***** Code
cp16: cp cp1l,cp2l ;Compare low byte
cpc cp1h,cp2h ;Compare high byte with
carry from
;previous operation
ncp16:
;Expected result is Z=0

;
***************************************************************************
;*
;* "cpi16" - Comparing 16-bit register with 16-bit
immediate
;*
;* This example compares the register pairs (cpi1l,
cpi1h) with the value
;* cpi2. If they are equal the zero flag is set(one),
otherwise it is
;* cleared(zero). This is enabled by the AVR's zero
propagation. Carry is
;* also set if the result is negative. This means that
all conditional
;* branch instructions can be used after the
comparison.
;*
;* Number of words :3
;* Number of cycles :3
;* Low registers used :None
;* High registers used :3
;*
;*
;
***************************************************************************

;***** Register Variables

.def cp1l =r16
.def cp1h =r17
.def c_tmp=r18
.equ cp2 = 0x3412 ;Immediate to compare with

;***** Code
cpi16: cpi cp1l,low(cp2) ;Compare low byte
ldi c_tmp,high(cp2) ;
cpc cp1h,c_tmp ;Compare high byte

;Expected result is Z=1, C=

;
***************************************************************************
;*
;* "neg16" - Negating 16-bit register
;*
;* This example negates the register pair (ng1l,ng1h)
The result will
;* overwrite the register pair.
;*
;* Number of words :4
;* Number of cycles :4
;* Low registers used :None
;* High registers used :2
;*
;
***************************************************************************

;***** Register Variables

.def ng1l = r16
.def ng1h = r17

;***** Code
ng16:
com ng1l ;Invert low byte ;
Calculated by
com ng1h ;Invert high byte ;
incverting all
subi ng1l,low(-1) ;Add 0x0001, low byte ;
bits then adding
sbci ng1h,high(-1) ;Add high byte ;
one (0x0001)
;Expected result is 0xCBEE

;
***************************************************************************
;*
;* End of examples.
;*
;
***************************************************************************

forever:rjmp forever

Programming the AVR Microcontrollers in Machine Language

AVR
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© WebRing Inc. Search

Atmel AVR From Wikipedia, the free encyclopedia (Redirected

from Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing,
intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still
be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
http://avr-asm.tripod.com/mathyx.html (1 of 2)1/20/2009 8:38:35 PM
AVR MATH YX

the ATmega range) have additional instructions to make

arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language

http://avr-asm.tripod.com/mathyx.html (2 of 2)1/20/2009 8:38:35 PM

AVR MATH YX

The AVR Assembler Site

DIV16 XX PACKAGE
HOME
RETRO_DAN
ASM FORUM ; DIVISION ROUTINES with scaled reciprocals for constants
ASM MATH ; (all functions optimized for speed, ~ <36 cycles w/o push/pop)
TUTORIAL #1
; Target: AVR MCUs with hardware multiplier ("mul" instruction)
TUTORIAL #2 ; Author: Andreas Lenze (andreas.lenze@t-online.de)
TUTORIAL #3 ; Feb. 2003

MATH 200 ;div. by n: n: scaled reciprocal: shift count:

MATH 200b
;Div16_3 3 1010101010101011 AAAB 17
MATH 201 ;Div16_5 5 1100110011001101 CCCD 18
MATH 202 ;Div16_6 6 1010101010101011 AAAB 18
;Div16_7 7 10010010010010011 19 -> 17 bits req'd,(MSB=1,rest 2493h)
MATH 32X
;Div16_7a 7 1001001001001001 9249 18 -> needs correction for accurate
MATH YX result
;Div16_9 9 1110001110001111 E38F 19
DIV16 XX
;Div16_10 10 1100110011001101 CCCD 19
DIV 24 24 ;Div16_11 11 1011101000101111 BA2F 19
DIV 3216 ;Div16_12 12 1010101010101011 AAAB 19
;Div16_13 13 1001110110001010 9D8A 19
FLOAT 128 ;Div16_14 14 10010010010010011 20 -> 17 bits req'd,(MSB=1,rest 2493h)
SQRT16 ;Div16_15 15 1000100010001001 8889 19
;Div16_17 17 1111000011110001 F0F1 20
MATH 202 ;Div16_18 18 1110001110001111 E38F 20
MATH 202 ;Div16_19 19 0110101111001011 6BCB 19
;Div16_20 20 1100110011001101 CCCD 20
DEC ASCII
;Div16_21 21 1100001100001011 C30B 20 -> needs correction for accurate
INT ASCII result
;Div16_22 22 1011101000101111 BA2F 20
HX2ASC
;Div16_23 23 1011001000010101 B215 20 -> needs correction for accurate
AVG8 222 result
FFT7
;D16_nn(by) 2-23 -> "C-style" function with macro 'Div16by' to perform a
COPY 102 ; constants division with all divisors from 2 to 23. Price
LPM 108 ; tag for the comfort is ~50 cycles / ~50 words overhead

EPROM 100 ; NOTE: Other divisor constants like /24 etc. can easily be created by
SER EPROM ; modifying the shift count in "Q = Q >> x": add 1 shift right for
; 'divisor x 2' (e.g. for "/24" we need a total of 20 instead of
DFLASH AT45
; the 19 shifts needed for "/12")
FLASH CARD
; If the remainder of the division is not needed, the multiply/subtract
VFX SMIL
; operation after the comment
VFX MEM ;
SORT 220 ; r19:r18 now "Q" (= result >> xx)

CRC 236 ; R = A - xx*Q (start removal

XMODEM REC ; ldi r16,xx
; ....
UART 304 ; sbc XH,YH (end removal)
UART 305 ;
; may be omitted to save another 9 cycles / 7 words
UART 128
; (* not applicable for 'Div16_7a' - remainder is always needed *)
UART BUFF ;
; "Div16_7a" and "Div16_21/3" demonstrate and use the 'approximate and
USB 232
correct'
AVR ISP ; technique which may be necessary for some larger divisors (e.g. /21, /23)
ISP 2313
;---------------------------------------------------------------------------
ISP 1200
AVR SPI ;***************************************************************************
;*
I2C 300 ;* Function "Div16_3"
I2C 302 ;* Divides an unsigned 16 bit word (XH:XL) by 3
;* Returns quotient in YH:YL and remainder in XL
I2C TWI26
;*
I2C/TWI 128 ;* Author: Andreas Lenze (andreas.lenze@t-online.de)
I2C/TWI AT8 ;* Equations by D: W. Jones:
;*
DALLAS-1W ;* Reciprocal mul w. extra precision:
DALLAS CRC ;* unsigned int A;
;* unsigned int scaled_reciprocal = 0xAAAB;
ETHNET 8019 ;* unsigned int Q; /* the quotient */
TEA ;*
;* Q = ((A * 0xAAAB) >> 17)
ADC 128 ;*
ADC 10B ;* Uses: high regs: 7 (r17, r18, r19, X, Y)
;* low regs: 3 (r0, r1, r2)
ADC 400
;*
ADC 401 ;* words: 36 (w. push/pop = 10 words)
THERM 232 ;* cycles: 48 (w. push/pop = 16 cycles)
;*
IRD 410 ;* Note: Hardware multiplier required ("mul" instruction)
LCD HD44 ;*
;***************************************************************************
LCD 2313
LCD44 2313 Div16_3:
push r2
KBD 240 push r19
MUX 242 push r18
push r17
KBD PS2
KBD PC/128 ldi YH,0xAA ; scaled reciprocal for /3
PS2 EMU ldi YL,0xAB

BOOT MG8 ; Q = A * 0xAAAB

BOOT DR8 ; (r19:r18:r17[:rXX] = XH:XL * YH:YL)
clr r2
ALM CLK mul XH, YH ; ah * bh
CLOCK 8564 movw r19:r18, r1:r0
mul XL, YL ; al * bl
90 DAYS
mov r17,r1 ; r0 to [rXX] is superfluous
DELAYS mul XH, YL ; ah * bl
add r17, r0
CALL ID
adc r18, r1
DTMF 314 adc r19, r2
PWM 6CH mul YH, XL ; bh * al
add r17, r0
PWM 10K adc r18, r1
ENCODE adc r19, r2
STH-11 ; Q = Q >> 16: use r19:r18 as word
ATMEL CORP ; Q = Q >> 1
lsr r19 ; do the last shift
AVR
ror r18
BUTTERFLY
AVR BOOK ; r19:r18 now "Q" (= result >> 17)
; R = A - 3*Q;
ldi r17,3 ; multiply r19:r18 by 3
mul r18, r17 ; al * bl
sub XL,r0
clr XH
movw YL,r18 ; make copy of Q

; XL holds "R"
; YH:YL holds "Q"
pop r17
pop r18
pop r19
pop r2

ret

;**** End of function Div16_3 ------------------------------------------****

;***************************************************************************
;*
;* Function "Div16_5"
;* Divides an unsigned 16 bit word (XH:XL) by 5
;* Returns quotient in YH:YL and remainder in XL
;*
;* Author: Andreas Lenze (andreas.lenze@t-online.de)
;* Equations by D: W. Jones:
;*
;* Reciprocal mul w. extra precision:
;* unsigned int A;
;* unsigned int scaled_reciprocal = 0xCCCD;
;* unsigned int Q; /* the quotient */
;*
;* Q = ((A * 0xCCCD) >> 18)
;*
;* Uses: high regs: 7 (r17, r18, r19, X, Y)
;* low regs: 3 (r0, r1, r2)
;*
;* words: 38 (w. push/pop = 10 words)
;* cycles: 54 (w. push/pop = 20 cycles)
;*
;* Note: Hardware multiplier required ("mul" instruction)
;*
;***************************************************************************

Div16_5:
push r2
push r19
push r18
push r17

ldi YH,0xCC ; scaled reciprocal for /5

ldi YL,0xCD

; Q = A * 0xCCCD
; (r19:r18:r17[:rXX] = XH:XL * YH:YL)
clr r2
mul XH, YH ; ah * bh
movw r19:r18, r1:r0
mul XL, YL ; al * bl
mov r17,r1 ; r0 to [rXX] is superfluous
mul XH, YL ; ah * bl
add r17, r0
adc r18, r1
adc r19, r2
mul YH, XL ; bh * al
add r17, r0
adc r18, r1
adc r19, r2

; Q = Q >> 16: use r19:r18 as word

; Q = Q >> 2
lsr r19 ; do the last 2 shifts
ror r18
lsr r19
ror r18

; r19:r18 now "Q" (= result >> 18)

; R = A - 5*Q;
ldi r17,5 ; multiply r19:r18 by 5
mul r18, r17 ; al * bl
sub XL,r0
clr XH
movw YL,r18 ; make copy of Q

; XL holds "R"
; YH:YL holds "Q"
pop r17
pop r18
pop r19
pop r2

ret

;**** End of function Div16_5 ------------------------------------------****

;***************************************************************************
;*
;* Function "Div16_6"
;* Divides an unsigned 16 bit word (XH:XL) by 6
;* Returns quotient in YH:YL and remainder in XL
;*
;* Author: Andreas Lenze (andreas.lenze@t-online.de)
;* Equations by D: W. Jones:
;*
;* Reciprocal mul w. extra precision:
;* unsigned int A;
;* unsigned int scaled_reciprocal = 0xAAAB;
;* unsigned int Q; /* the quotient */
;*
;* Q = ((A * 0xAAAB) >> 18)
;*
;* Uses: high regs: 7 (r17, r18, r19, X, Y)
;* low regs: 3 (r0, r1, r2)
;*
;* words: 38 (w. push/pop = 10 words)
;* cycles: 54 (w. push/pop = 20 cycles)
;*
;* Note: Hardware multiplier required ("mul" instruction)
;*
;***************************************************************************

Div16_6:
push r2
push r19
push r18
push r17

ldi YH,0xAA ; scaled reciprocal for /6

ldi YL,0xAB

; Q = A * 0xAAAB
; (r19:r18:r17[:rXX] = XH:XL * YH:YL)
clr r2
mul XH, YH ; ah * bh
movw r19:r18, r1:r0
mul XL, YL ; al * bl
mov r17,r1 ; r0 to [rXX] is superfluous
mul XH, YL ; ah * bl
add r17, r0
adc r18, r1
adc r19, r2
mul YH, XL ; bh * al
add r17, r0
adc r18, r1
adc r19, r2

; Q = Q >> 16: use r19:r18 as word

; Q = Q >> 2
lsr r19 ; do the last 2 shifts
ror r18
lsr r19
ror r18

; r19:r18 now "Q" (= result >> 18)

; R = A - 6*Q;
ldi r17,6 ; multiply r19:r18 by 6
mul r18, r17 ; al * bl
sub XL,r0
clr XH
movw YL,r18 ; make copy of Q

; XL holds "R"
; YH:YL holds "Q"
pop r17
pop r18
pop r19
pop r2

ret

;**** End of function Div16_6 ------------------------------------------****

;***************************************************************************
;*
;* Function "Div16_7"
;* Divides an unsigned 16 bit word (XH:XL) by 7
;* Returns quotient in YH:YL and remainder in XL
;*
;* Author: Andreas Lenze (andreas.lenze@t-online.de)
;* Equations by D: W. Jones:
;*
;* Reciprocal mul w. extra precision:
;* unsigned int A;
;* unsigned int scaled_reciprocal = 0x2493;
;* unsigned int Q; /* the quotient */
;*
;* Q = (((A * 0x2493) >> 16) + A) >> 3 -> 17 bits reciprocal!
;*
;* Uses: high regs: 7 (r17, r18, r19, X, Y)
;* low regs: 3 (r0, r1, r2)
;*
;* words: 38 (w. push/pop = 8 words)
;* cycles: 46 (w. push/pop = 16 cycles)
;*
;* Note: Hardware multiplier required ("mul" instruction)
;*
;***************************************************************************

Div16_7:
push r2
push r19
push r18
push r17

ldi YH,0x24 ; scaled reciprocal for /7

ldi YL,0x93

; Q = A * 0x2493
; (r19:r18:r17[:rXX] = XH:XL * YH:YL)
clr r2
mul XH, YH ; ah * bh
movw r19:r18, r1:r0
mul XL, YL ; al * bl
mov r17,r1 ; r0 to [rXX] is superfluous
mul XH, YL ; ah * bl
add r17, r0
adc r18, r1
adc r19, r2
mul YH, XL ; bh * al
add r17, r0
adc r18, r1
adc r19, r2

; Q = Q >> 16: use r19:r18 as word

; Q = Q + A
add r18,XL
adc r19,XH

; Q = Q >> 3
ror r19 ; do the last 3 shifts, including
ror r18 ; carry (!) from previous addition
lsr r19
ror r18
lsr r19
ror r18

; r19:r18 now "Q" (= result >> 19)

; R = A - 7*Q;
ldi r17,7 ; multiply r19:r18 by 7
mul r18, r17 ; al * bl
sub XL,r0
clr XH
movw YL,r18 ; make copy of Q

; XL holds "R"
; YH:YL holds "Q"
pop r17
pop r18
pop r19
pop r2

ret

;**** End of function Div16_7 ------------------------------------------****

;***************************************************************************
;*
;* Function "Div16_7a"
;* Divides an unsigned 16 bit word (XH:XL) by 7
;* Call with 16 bit number in XH:XL
;* Returns quotient in YH:YL and remainder in XL
;*
;* Author: Andreas Lenze (andreas.lenze@t-online.de)
;* (Equations partly by D. W. Jones)
;*
;* Reciprocal multiplication w. extra precision:
;* (This version uses correction to achieve the required precision)
;* unsigned int R; /* remainder */
;* unsigned int long A; /* dividend */
;* unsigned int long Q; /* quotient */
;*
;* Q = ((A * 0x9249) >> 18)
;*
;* /* Q = A/7 or Q+1 = A/7 for all A <= 65535 */
;* /* correct Q and calculate remainder */
;* R = A - 7*Q
;* if (R >= 7) {
;* R = R - 7;
;* Q = Q + 1;
;* }
;* Uses: high regs: 7 (r17, r18, r19, X, Y)
;* low regs: 3 (r0, r1, r2)
;*
;* words: 36 (w. push/pop = 8 words)
;* cycles: 59 (w. push/pop = 20 cycles)
;*
;* Note: Hardware multiplier required ("mul" instruction)
;*
;***************************************************************************

Div16_7a:
push r2
push r19
push r18 ; Tmp3
push r17 ; Tmp2

ldi YH,0x92 ; scaled reciprocal for /7

ldi YL,0x49 ; (16 bit only, 0/-1 error possible)

; Q = A * 0x9249
; (r19:r18:r17[:rXX] = XH:XL * YH:YL)
clr r2
mul XH, YH ; ah * bh
movw r19:r18, r1:r0
mul XL, YL ; al * bl
mov r17,r1 ; r0 to [rXX] is superfluous
mul XH, YL ; ah * bl
add r17, r0
adc r18, r1
adc r19, r2
mul YH, XL ; bh * al
add r17, r0
adc r18, r1
adc r19, r2

; Q = Q >> 16: use r19:r18 as word

; Q = Q >> 2
lsr r19 ; 2 shifts remaining
ror r18
lsr r19
ror r18

; r19:r18 now "Q" (= result >> 18)

; R = A - 7*Q;
ldi r17,7 ; multiply r19:r18 by 7
mul r18, r17 ; al * bl
sub XL,r0
clr XH
movw YL,r18 ; make copy of current Q

; XH:XL now "R":

; if (R >= 7)
; R = R - 7;
; Q = Q + 1;
cpi XL,0x07
brlo PC+3
subi XL,7
adiw YL,1

; XL holds "R"
; YH:YL holds "Q"
pop r17
pop r18
pop r19
pop r2

ret

;**** End of function Div16_7a -----------------------------------------****

;***************************************************************************
;*
;* Function "Div16_9"
;* Divides an unsigned 16 bit word (XH:XL) by 9
;* Returns quotient in YH:YL and remainder in XL
;*
;* Author: Andreas Lenze (andreas.lenze@t-online.de)
;* Equations by D: W. Jones:
;*
;* Reciprocal mul w. extra precision:
;* unsigned int A;
;* unsigned int scaled_reciprocal = 0xE38F;
;* unsigned int Q; /* the quotient */
;*
;* Q = ((A * 0xE38F) >> 19)
;*
;* Uses: high regs: 7 (r17, r18, r19, X, Y)
;* low regs: 3 (r0, r1, r2)
;*
;* words: 36 (w. push/pop = 8 words)
;* cycles: 46 (w. push/pop = 16 cycles)
;*
;* Note: Hardware multiplier required ("mul" instruction)
;*
;***************************************************************************

Div16_9:
push r2
push r19
push r18
push r17

ldi YH,0xE3 ; scaled reciprocal for /9

ldi YL,0x8F

; Q = A * 0xE38F
; (r19:r18:r17[:rXX] = XH:XL * YH:YL)
clr r2
mul XH, YH ; ah * bh
movw r19:r18, r1:r0
mul XL, YL ; al * bl
mov r17,r1 ; r0 to [rXX] is superfluous
mul XH, YL ; ah * bl
add r17, r0
adc r18, r1
adc r19, r2
mul YH, XL ; bh * al
add r17, r0
adc r18, r1
adc r19, r2

; Q = Q >> 16: use r19:r18 as word

; Q = Q >> 3
lsr r19 ; do the last 3 shifts
ror r18
lsr r19
ror r18
lsr r19
ror r18

; r19:r18 now "Q" (= result >> 19)

; R = A - 9*Q;
ldi r17,9 ; multiply r19:r18 by 9
mul r18, r17 ; al * bl
sub XL,r0
clr XH
movw YL,r18 ; make copy of Q

; XL holds "R"
; YH:YL holds "Q"
pop r17
pop r18
pop r19
pop r2

ret

;**** End of function Div16_9 ------------------------------------------****

;***************************************************************************
;*
;* Function "Div16_10"
;* Divides an unsigned 16 bit word (XH:XL) by 10
;* Returns quotient in YH:YL and remainder in XL
;*
;* Author: Andreas Lenze (andreas.lenze@t-online.de)
;* Equations by D: W. Jones:
;*
;* Reciprocal mul w. extra precision:
;* unsigned int A;
;* unsigned int scaled_reciprocal = 0xCCCD;
;* unsigned int Q; /* the quotient */
;*
;* Q = ((A * 0xCCCD) >> 19)
;*
;* Uses: high regs: 7 (r17, r18, r19, X, Y)
;* low regs: 3 (r0, r1, r2)
;*
;* words: 36 (w. push/pop = 8 words)
;* cycles: 46 (w. push/pop = 16 cycles)
;*
;* Note: Hardware multiplier required ("mul" instruction)
;*
;***************************************************************************

Div16_10:
push r2
push r19
push r18
push r17

ldi YH,0xCC ; scaled reciprocal for /10

ldi YL,0xCD

; Q = A * 0xCCCD
; (r19:r18:r17[:rXX] = XH:XL * YH:YL)
clr r2
mul XH, YH ; ah * bh
movw r19:r18, r1:r0
mul XL, YL ; al * bl
mov r17,r1 ; r0 to [rXX] is superfluous
mul XH, YL ; ah * bl
add r17, r0
adc r18, r1
adc r19, r2
mul YH, XL ; bh * al
add r17, r0
adc r18, r1
adc r19, r2

; Q = Q >> 16: use r19:r18 as word

; Q = Q >> 3
lsr r19 ; do the last 3 shifts
ror r18
lsr r19
ror r18
lsr r19
ror r18

; r19:r18 now "Q" (= result >> 19)

; R = A - 10*Q;
ldi r17,10 ; multiply r19:r18 by 10
mul r18, r17 ; al * bl
sub XL,r0
clr XH
movw YL,r18 ; make copy of Q

; XL holds "R"
; YH:YL holds "Q"
pop r17
pop r18
pop r19
pop r2

ret

;**** End of function Div16_10 -----------------------------------------****

;***************************************************************************
;*
;* Function "Div16_11"
;* Divides an unsigned 16 bit word (XH:XL) by 11
;* Returns quotient in YH:YL and remainder in XL
;*
;* Author: Andreas Lenze (andreas.lenze@t-online.de)
;* Equations by D: W. Jones:
;*
;* Reciprocal mul w. extra precision:
;* unsigned int A;
;* unsigned int scaled_reciprocal = 0xBA2F;
;* unsigned int Q; /* the quotient */
;*
;* Q = ((A * 0xBA2F) >> 19)
;*
;* Uses: high regs: 7 (r17, r18, r19, X, Y)
;* low regs: 3 (r0, r1, r2)
;*
;* words: 36 (w. push/pop = 8 words)
;* cycles: 46 (w. push/pop = 16 cycles)
;*
;* Note: Hardware multiplier required ("mul" instruction)
;*
;***************************************************************************

Div16_11:
push r2
push r19
push r18
push r17

ldi YH,0xBA ; scaled reciprocal for /11

ldi YL,0x2F

; Q = A * 0xBA2F
; (r19:r18:r17[:rXX] = XH:XL * YH:YL)
clr r2
mul XH, YH ; ah * bh
movw r19:r18, r1:r0
mul XL, YL ; al * bl
mov r17,r1 ; r0 to [rXX] is superfluous
mul XH, YL ; ah * bl
add r17, r0
adc r18, r1
adc r19, r2
mul YH, XL ; bh * al
add r17, r0
adc r18, r1
adc r19, r2

; Q = Q >> 16: use r19:r18 as word

; Q = Q >> 3
lsr r19 ; do the last 3 shifts
ror r18
lsr r19
ror r18
lsr r19
ror r18

; r19:r18 now "Q" (= result >> 19)

; R = A - 11*Q;
ldi r17,11 ; multiply r19:r18 by 11
mul r18, r17 ; al * bl
sub XL,r0
clr XH
movw YL,r18 ; make copy of Q

; XL holds "R"
; YH:YL holds "Q"
pop r17
pop r18
pop r19
pop r2

ret

;**** End of function Div16_11 -----------------------------------------****

;***************************************************************************
;*
;* Function "Div16_12"
;* Divides an unsigned 16 bit word (XH:XL) by 12
;* Returns quotient in YH:YL and remainder in XL
;*
;* Author: Andreas Lenze (andreas.lenze@t-online.de)
;* Equations by D: W. Jones:
;*
;* Reciprocal mul w. extra precision:
;* unsigned int A;
;* unsigned int scaled_reciprocal = 0xAAAB;
;* unsigned int Q; /* the quotient */
;*
;* Q = ((A * 0xAAAB) >> 19)
;*
;* Uses: high regs: 7 (r17, r18, r19, X, Y)
;* low regs: 3 (r0, r1, r2)
;*
;* words: 36 (w. push/pop = 8 words)
;* cycles: 46 (w. push/pop = 16 cycles)
;*
;* Note: Hardware multiplier required ("mul" instruction)
;*
;***************************************************************************

Div16_12:
push r2
push r19
push r18
push r17

ldi YH,0xAA ; scaled reciprocal for /12

ldi YL,0xAB

; Q = A * 0xAAAB
; (r19:r18:r17[:rXX] = XH:XL * YH:YL)
clr r2
mul XH, YH ; ah * bh
movw r19:r18, r1:r0
mul XL, YL ; al * bl
mov r17,r1 ; r0 to [rXX] is superfluous
mul XH, YL ; ah * bl
add r17, r0
adc r18, r1
adc r19, r2
mul YH, XL ; bh * al
add r17, r0
adc r18, r1
adc r19, r2

; Q = Q >> 16: use r19:r18 as word

; Q = Q >> 3
lsr r19 ; do the last 3 shifts
ror r18
lsr r19
ror r18
lsr r19
ror r18

; r19:r18 now "Q" (= result >> 19)

; R = A - 12*Q;
ldi r17,12 ; multiply r19:r18 by 12
mul r18, r17 ; al * bl
sub XL,r0
clr XH
movw YL,r18 ; make copy of Q

; XL holds "R"
; YH:YL holds "Q"
pop r17
pop r18
pop r19
pop r2

ret

;**** End of function Div16_12 -----------------------------------------****

;***************************************************************************
;*
;* Function "Div16_13"
;* Divides an unsigned 16 bit word (XH:XL) by 13
;* Returns quotient in YH:YL and remainder in XL
;*
;* Author: Andreas Lenze (andreas.lenze@t-online.de)
;* Equations by D: W. Jones:
;*
;* Reciprocal mul w. extra precision:
;* unsigned int A;
;* unsigned int scaled_reciprocal = 0x9D89;
;* unsigned int Q; /* the quotient */
;*
;* Q = ((A * 0x9D8A) >> 19)
;*
;* Uses: high regs: 7 (r17, r18, r19, X, Y)
;* low regs: 3 (r0, r1, r2)
;*
;* words: 36 (w. push/pop = 8 words)
;* cycles: 46 (w. push/pop = 16 cycles)
;*
;* Note: Hardware multiplier required ("mul" instruction)
;*
;***************************************************************************

Div16_13:
push r2
push r19
push r18
push r17

ldi YH,0x9D ; scaled reciprocal for /13

ldi YL,0x8A

; Q = A * 0x9D8A
; (r19:r18:r17[:rXX] = XH:XL * YH:YL)
clr r2
mul XH, YH ; ah * bh
movw r19:r18, r1:r0
mul XL, YL ; al * bl
mov r17,r1 ; r0 to [rXX] is superfluous
mul XH, YL ; ah * bl
add r17, r0
adc r18, r1
adc r19, r2
mul YH, XL ; bh * al
add r17, r0
adc r18, r1
adc r19, r2

; Q = Q >> 16: use r19:r18 as word

; Q = Q >> 3
lsr r19 ; do the last 3 shifts
ror r18
lsr r19
ror r18
lsr r19
ror r18

; r19:r18 now "Q" (= result >> 19)

; R = A - 13*Q;
ldi r17,13 ; multiply r19:r18 by 13
mul r18, r17 ; al * bl
sub XL,r0
clr XH
movw YL,r18 ; make copy of Q

; XL holds "R"
; YH:YL holds "Q"
pop r17
pop r18
pop r19
pop r2

ret

;**** End of function Div16_13 -----------------------------------------****

;***************************************************************************
;*
;* Function "Div16_14"
;* Divides an unsigned 16 bit word (XH:XL) by 14
;* Returns quotient in YH:YL and remainder in XL
;*
;* Author: Andreas Lenze (andreas.lenze@t-online.de)
;* Equations by D: W. Jones:
;*
;* Reciprocal mul w. extra precision:
;* unsigned int A;
;* unsigned int scaled_reciprocal = 0x2493;
;* unsigned int Q; /* the quotient */
;*
;* Q = (((A * 0x2493) >> 16) + A) >> 4 -> 17 bits reciprocal!
;*
;* Uses: high regs: 7 (r17, r18, r19, X, Y)
;* low regs: 3 (r0, r1, r2)
;*
;* words: 40 (w. push/pop = 8 words)
;* cycles: 44 (w. push/pop = 16 cycles)
;*
;* Note: Hardware multiplier required ("mul" instruction)
;*
;***************************************************************************

Div16_14:
push r2
push r19
push r18
push r17

ldi YH,0x24 ; scaled reciprocal for /7, /14

ldi YL,0x93

; Q = A * 0x2493
; (r19:r18:r17[:rXX] = XH:XL * YH:YL)
clr r2
mul XH, YH ; ah * bh
movw r19:r18, r1:r0

http://avr-asm.tripod.com/div16xx.html (1 of 3)1/20/2009 8:39:37 PM

AVR MATH YX

mul XL, YL ; al * bl
mov r17,r1 ; r0 to [rXX] is superfluous
mul XH, YL ; ah * bl
add r17, r0
adc r18, r1
adc r19, r2
mul YH, XL ; bh * al
add r17, r0
adc r18, r1
adc r19, r2

; Q = Q >> 16: use r19:r18 as word

; Q = Q + A
add r18,XL
adc r19,XH

; Q = Q >> 4
ror r19 ; do the last 4 shifts, including
ror r18 ; carry (!) from previous addition
lsr r19
ror r18
lsr r19
ror r18
lsr r19
ror r18

; r19:r18 now "Q" (= result >> 20)

; R = A - 14*Q;
ldi r17,14 ; multiply r19:r18 by 14
mul r18, r17 ; al * bl
sub XL,r0
clr XH
movw YL,r18 ; make copy of Q

; XL holds "R"
; YH:YL holds "Q"
pop r17
pop r18
pop r19
pop r2

ret

;**** End of function Div16_14 -----------------------------------------****

;***************************************************************************
;*
;* Function "Div16_15"
;* Divides an unsigned 16 bit word (XH:XL) by 15
;* Returns quotient in YH:YL and remainder in XL
;*
;* Author: Andreas Lenze (andreas.lenze@t-online.de)
;* Equations by D: W. Jones:
;*
;* Reciprocal mul w. extra precision:
;* unsigned int A;
;* unsigned int scaled_reciprocal = 0x8889;
;* unsigned int Q; /* the quotient */
;*
;* Q = ((A * 0x8889) >> 19)
;*
;* Uses: high regs: 7 (r17, r18, r19, X, Y)
;* low regs: 3 (r0, r1, r2)
;*
;* words: 36 (w. push/pop = 8 words)
;* cycles: 46 (w. push/pop = 16 cycles)
;*
;* Note: Hardware multiplier required ("mul" instruction)
;*
;***************************************************************************

Div16_15:
push r2
push r19
push r18
push r17

ldi YH,0x88 ; scaled reciprocal for /15

ldi YL,0x89

; Q = A * 0x8889
; (r19:r18:r17[:rXX] = XH:XL * YH:YL)
clr r2
mul XH, YH ; ah * bh
movw r19:r18, r1:r0
mul XL, YL ; al * bl
mov r17,r1 ; r0 to [rXX] is superfluous
mul XH, YL ; ah * bl
add r17, r0
adc r18, r1
adc r19, r2
mul YH, XL ; bh * al
add r17, r0
adc r18, r1
adc r19, r2

; Q = Q >> 16: use r19:r18 as word

; Q = Q >> 3
lsr r19 ; do the last 3 shifts
ror r18
lsr r19
ror r18
lsr r19
ror r18

; r19:r18 now "Q" (= result >> 19)

; R = A - 15*Q;
ldi r17,15 ; multiply r19:r18 by 15
mul r18, r17 ; al * bl
sub XL,r0
clr XH
movw YL,r18 ; make copy of Q

; XL holds "R"
; YH:YL holds "Q"
pop r17
pop r18
pop r19
pop r2

ret

;**** End of function Div16_15 -----------------------------------------****

;***************************************************************************
;*
;* Function "Div16_17"
;* Divides an unsigned 16 bit word (XH:XL) by 17
;* Returns quotient in YH:YL and remainder in XL
;*
;* Author: Andreas Lenze (andreas.lenze@t-online.de)
;* Equations by D: W. Jones:
;*
;* Reciprocal mul w. extra precision:
;* unsigned int A;
;* unsigned int scaled_reciprocal = 0xF0F1;
;* unsigned int Q; /* the quotient */
;*
;* Q = ((A * 0xF0F1) >> 20)
;*
;* Uses: high regs: 7 (r17, r18, r19, X, Y)
;* low regs: 3 (r0, r1, r2)
;*
;* words: 38 (w. push/pop = 10 words)
;* cycles: 44 (w. push/pop = 16 cycles)
;*
;* Note: Hardware multiplier required ("mul" instruction)
;*
;***************************************************************************

Div16_17:
push r2
push r19
push r18
push r17

ldi YH,0xF0 ; scaled reciprocal for /17

ldi YL,0xF1

; Q = A * 0xF0F1
; (r19:r18:r17[:rXX] = XH:XL * YH:YL)
clr r2
mul XH, YH ; ah * bh
movw r19:r18, r1:r0
mul XL, YL ; al * bl
mov r17,r1 ; r0 to [rXX] is superfluous
mul XH, YL ; ah * bl
add r17, r0
adc r18, r1
adc r19, r2
mul YH, XL ; bh * al
add r17, r0
adc r18, r1
adc r19, r2

; Q = Q >> 16: use r19:r18 as word

; Q = Q >> 4
swap r18 ; do the last 4 shifts
swap r19
andi r18,0x0F
eor r18,r19
andi r19,0x0F
eor r18,r19

; r19:r18 now "Q" (= result >> 20)

; R = A - 17*Q;
ldi r17,17 ; multiply r19:r18 by 17
mul r18, r17 ; al * bl
sub XL,r0
clr XH
movw YL,r18 ; make copy of Q

; XL holds "R"
; YH:YL holds "Q"
pop r17
pop r18
pop r19
pop r2

ret

;**** End of function Div16_17 -----------------------------------------****

;***************************************************************************
;*
;* Function "Div16_18"
;* Divides an unsigned 16 bit word (XH:XL) by 18
;* Returns quotient in YH:YL and remainder in XL
;*
;* Author: Andreas Lenze (andreas.lenze@t-online.de)
;* Equations by D: W. Jones:
;*
;* Reciprocal mul w. extra precision:
;* unsigned int A;
;* unsigned int scaled_reciprocal = 0xE38F;
;* unsigned int Q; /* the quotient */
;*
;* Q = ((A * 0xE38F) >> 20)
;*
;* Uses: high regs: 7 (r17, r18, r19, X, Y)
;* low regs: 3 (r0, r1, r2)
;*
;* words: 38 (w. push/pop = 10 words)
;* cycles: 44 (w. push/pop = 16 cycles)
;*
;* Note: Hardware multiplier required ("mul" instruction)
;*
;***************************************************************************

Div16_18:
push r2
push r19
push r18
push r17

ldi YH,0xE3 ; scaled reciprocal for /9 /18

ldi YL,0x8F

; Q = A * 0xE38F
; (r19:r18:r17[:rXX] = XH:XL * YH:YL)
clr r2
mul XH, YH ; ah * bh
movw r19:r18, r1:r0
mul XL, YL ; al * bl
mov r17,r1 ; r0 to [rXX] is superfluous
mul XH, YL ; ah * bl
add r17, r0
adc r18, r1
adc r19, r2
mul YH, XL ; bh * al
add r17, r0
adc r18, r1
adc r19, r2

; Q = Q >> 16: use r19:r18 as word

; Q = Q >> 4
swap r18 ; do the last 4 shifts
swap r19
andi r18,0x0F
eor r18,r19
andi r19,0x0F
eor r18,r19

; r19:r18 now "Q" (= result >> 20)

; R = A - 18*Q;
ldi r17,18 ; multiply r19:r18 by 18
mul r18, r17 ; al * bl
sub XL,r0
clr XH
movw YL,r18 ; make copy of Q

; XL holds "R"
; YH:YL holds "Q"
pop r17
pop r18
pop r19
pop r2

ret

;**** End of function Div16_18 -----------------------------------------****

;***************************************************************************
;*
;* Function "Div16_19"
;* Divides an unsigned 16 bit word (XH:XL) by 19
;* Returns quotient in YH:YL and remainder in XL
;*
;* Author: Andreas Lenze (andreas.lenze@t-online.de)
;* Equations by D: W. Jones:
;*
;* Reciprocal mul w. extra precision:
;* unsigned int A;
;* unsigned int scaled_reciprocal = 0x6BCA;
;* unsigned int Q; /* the quotient */
;*
;* Q = ((A * 0x6BCB) >> 19)
;*
;* Uses: high regs: 7 (r17, r18, r19, X, Y)
;* low regs: 3 (r0, r1, r2)
;*
;* words: 36 (w. push/pop = 8 words)
;* cycles: 46 (w. push/pop = 16 cycles)
;*
;* Note: Hardware multiplier required ("mul" instruction)
;*
;***************************************************************************

Div16_19:
push r2
push r19
push r18
push r17

ldi YH,0x6B ; scaled reciprocal for /19

ldi YL,0xCB

; Q = A * 0x6BCB
; (r19:r18:r17[:rXX] = XH:XL * YH:YL)
clr r2
mul XH, YH ; ah * bh
movw r19:r18, r1:r0
mul XL, YL ; al * bl
mov r17,r1 ; r0 to [rXX] is superfluous
mul XH, YL ; ah * bl
add r17, r0
adc r18, r1
adc r19, r2
mul YH, XL ; bh * al
add r17, r0
adc r18, r1
adc r19, r2

; Q = Q >> 16: use r19:r18 as word

; Q = Q >> 3
lsr r19 ; do the last 3 shifts
ror r18
lsr r19
ror r18
lsr r19
ror r18

; r19:r18 now "Q" (= result >> 19)

; R = A - 19*Q;
ldi r17,18 ; multiply r19:r18 by 18
mul r18, r17 ; al * bl
sub XL,r0
clr XH
movw YL,r18 ; make copy of Q

; XL holds "R"
; YH:YL holds "Q"
pop r17
pop r18
pop r19
pop r2

ret

;**** End of function Div16_19 -----------------------------------------****

;***************************************************************************
;*
;* Function "Div16_20"
;* Divides an unsigned 16 bit word (XH:XL) by 20
;* Returns quotient in YH:YL and remainder in XL
;*
;* Author: Andreas Lenze (andreas.lenze@t-online.de)
;* Equations by D: W. Jones:
;*
;* Reciprocal mul w. extra precision:
;* unsigned int A;
;* unsigned int scaled_reciprocal = 0xCCCD;
;* unsigned int Q; /* the quotient */
;*
;* Q = ((A * 0xCCCD) >> 20)
;*
;* Uses: high regs: 7 (r17, r18, r19, X, Y)
;* low regs: 3 (r0, r1, r2)
;*
;* words: 36 (w. push/pop = 8 words)
;* cycles: 46 (w. push/pop = 16 cycles)
;*
;* Note: Hardware multiplier required ("mul" instruction)
;*
;***************************************************************************

Div16_20:
push r2
push r19
push r18
push r17

ldi YH,0xCC ; scaled reciprocal for /10, /20

ldi YL,0xCD

; Q = A * 0xCCCD
; (r19:r18:r17[:rXX] = XH:XL * YH:YL)
clr r2
mul XH, YH ; ah * bh
movw r19:r18, r1:r0
mul XL, YL ; al * bl
mov r17,r1 ; r0 to [rXX] is superfluous
mul XH, YL ; ah * bl
add r17, r0
adc r18, r1
adc r19, r2
mul YH, XL ; bh * al
add r17, r0
adc r18, r1
adc r19, r2

; Q = Q >> 16: use r19:r18 as word

; Q = Q >> 4
swap r18 ; do the last 4 shifts
swap r19
andi r18,0x0F
eor r18,r19
andi r19,0x0F
eor r18,r19

; r19:r18 now "Q" (= result >> 20)

; R = A - 20*Q;
ldi r17,20 ; multiply r19:r18 by 20
mul r18, r17 ; al * bl
sub XL,r0
clr XH
movw YL,r18 ; make copy of Q

; XL holds "R"
; YH:YL holds "Q"
pop r17
pop r18
pop r19
pop r2

ret

;**** End of function Div16_20 -----------------------------------------****

;***************************************************************************
;*
;* Function "Div16_21"
;* Divides an unsigned 16 bit word (XH:XL) by 21
;* Call with 16 bit number in XH:XL
;* Returns quotient in YH:YL and remainder in XL
;*
;* Author: Andreas Lenze (andreas.lenze@t-online.de)
;* (Equations partly by D. W. Jones)
;*
;* Reciprocal multiplication w. extra precision:
;* (uses correction to achieve the required precision)
;* unsigned int R; /* remainder */
;* unsigned int long A; /* dividend */
;* unsigned int long Q; /* quotient */
;*
;* Q = ((A * 0xC30B) >> 20)
;*
;* /* Q = A/21 or Q+1 = A/21 for all A <= 65535 */
;* /* correct Q and calculate remainder */
;* R = A - 21*Q
;* if (R >= 21) {
;* R = R - 21;
;* Q = Q + 1;
;* }
;* Uses: high regs: 7 (r17, r18, r19, X, Y)
;* low regs: 3 (r0, r1, r2)
;*
;* words: 40 (w. push/pop = 8 words)
;* cycles: 52 (w. push/pop = 16 cycles)
;*
;* Note: Hardware multiplier required ("mul" instruction)
;*
;***************************************************************************

Div16_21:
push r2
push r19
push r18
push r17

ldi YH,0xC3 ; scaled reciprocal for /21

ldi YL,0x0B ; (16 bit only, 0/-1 error possible)

; Q = A * 0xC30B
; (r19:r18:r17[:rXX] = XH:XL * YH:YL)
clr r2
mul XH, YH ; ah * bh
movw r19:r18, r1:r0
mul XL, YL ; al * bl
mov r17,r1 ; r0 to [rXX] is superfluous
mul XH, YL ; ah * bl
add r17, r0
adc r18, r1
adc r19, r2
mul YH, XL ; bh * al
add r17, r0
adc r18, r1
adc r19, r2

; Q = Q >> 16: use r19:r18 as word

; Q = Q >> 4
swap r18 ; do the last 4 shifts
swap r19
andi r18,0x0F
eor r18,r19
andi r19,0x0F
eor r18,r19

; r19:r18 now "Q" (= result >> 20)

; R = A - 21*Q;
ldi r17,21 ; multiply r19:r18 by 21
mul r18, r17 ; al * bl
sub XL,r0
clr XH
movw YL,r18 ; make copy of current Q

; XH:XL now "R":

; if (R >= 21)
; R = R - 21;
; Q = Q + 1;
cpi XL,0x15
brlo PC+3
subi XL,21
adiw YL,1

; XL holds "R"
; YH:YL holds "Q"
pop r17
pop r18
pop r19
pop r2

ret

;**** End of function Div16_21 -----------------------------------------****

;***************************************************************************
;*
;* Function "Div16_22"
;* Divides an unsigned 16 bit word (XH:XL) by 22
;* Returns quotient in YH:YL and remainder in XL
;*
;* Author: Andreas Lenze (andreas.lenze@t-online.de)
;* Equations by D: W. Jones:
;*
;* Reciprocal mul w. extra precision:
;* unsigned int A;
;* unsigned int scaled_reciprocal = 0xBA2F;
;* unsigned int Q; /* the quotient */
;*
;* Q = ((A * 0xBA2F) >> 20)
;*
;* Uses: high regs: 7 (r17, r18, r19, X, Y)
;* low regs: 3 (r0, r1, r2)
;*
;* words: 36 (w. push/pop = 8 words)
;* cycles: 46 (w. push/pop = 16 cycles)
;*
;* Note: Hardware multiplier required ("mul" instruction)
;*
;***************************************************************************

Div16_22:
push r2
push r19
push r18
push r17

ldi YH,0xBA ; scaled reciprocal for /11, /22

ldi YL,0x2F

; Q = A * 0xBA2F
; (r19:r18:r17[:rXX] = XH:XL * YH:YL)
clr r2
mul XH, YH ; ah * bh
movw r19:r18, r1:r0
mul XL, YL ; al * bl
mov r17,r1 ; r0 to [rXX] is superfluous
mul XH, YL ; ah * bl
add r17, r0
adc r18, r1
adc r19, r2
mul YH, XL ; bh * al
add r17, r0
adc r18, r1
adc r19, r2

; Q = Q >> 16: use r19:r18 as word

; Q = Q >> 4
swap r18 ; do the last 4 shifts
swap r19
andi r18,0x0F
eor r18,r19
andi r19,0x0F
eor r18,r19

; r19:r18 now "Q" (= result >> 20)

; R = A - 22*Q;
ldi r17,22 ; multiply r19:r18 by 22
mul r18, r17 ; al * bl
sub XL,r0
clr XH
movw YL,r18 ; make copy of Q

; XL holds "R"
; YH:YL holds "Q"
pop r17
pop r18
pop r19
pop r2

ret

;**** End of function Div16_22 -----------------------------------------****

;***************************************************************************
;*
;* Function "Div16_23"
;* Divides an unsigned 16 bit word (XH:XL) by 23
;* Call with 16 bit number in XH:XL
;* Returns quotient in YH:YL and remainder in XL
;*
;* Author: Andreas Lenze (andreas.lenze@t-online.de)
;* (Equations partly by D. W. Jones)
;*
;* Reciprocal multiplication w. extra precision:
;* (uses correction to achieve the required precision)
;* unsigned int R; /* remainder */
;* unsigned int long A; /* dividend */
;* unsigned int long Q; /* quotient */
;*
;* Q = ((A * 0xB215) >> 20)
;*
;* /* Q = A/23 or Q+1 = A/23 for all A <= 65535 */
;* /* correct Q and calculate remainder */
;* R = A - 1*Q
;* if (R >= 23) {
;* R = R - 23;
;* Q = Q + 1;
;* }
;* Uses: high regs: 7 (r17, r18, r19, X, Y)
;* low regs: 3 (r0, r1, r2)
;*
;* words: 36 (w. push/pop = 8 words)
;* cycles: 59 (w. push/pop = 20 cycles)
;*
;* Note: Hardware multiplier required ("mul" instruction)
;*
;***************************************************************************

Div16_23:
push r2
push r19
push r18
push r17

ldi YH,0xB2 ; scaled reciprocal for /23

ldi YL,0x15 ; (16 bit only, 0/-1 error possible)

; Q = A * 0xB215
; (r19:r18:r17[:rXX] = XH:XL * YH:YL)
clr r2
mul XH, YH ; ah * bh
movw r19:r18, r1:r0
mul XL, YL ; al * bl
mov r17,r1 ; r0 to [rXX] is superfluous
mul XH, YL ; ah * bl
add r17, r0
adc r18, r1
adc r19, r2
mul YH, XL ; bh * al
add r17, r0
adc r18, r1
adc r19, r2

; Q = Q >> 16: use r19:r18 as word

; Q = Q >> 4
swap r18 ; do the last 4 shifts
swap r19
andi r18,0x0F
eor r18,r19
andi r19,0x0F
eor r18,r19

; r19:r18 now "Q" (= result >> 20)

; R = A - 23*Q;
ldi r17,23 ; multiply r19:r18 by 23
mul r18, r17 ; al * bl
sub XL,r0
clr XH
movw YL,r18 ; make copy of currentQ

; XH:XL now "R":

; if (R >= 23)
; R = R - 23;
; Q = Q + 1;
cpi XL,0x17
brlo PC+3
subi XL,23
adiw YL,1

; XL holds "R"
; YH:YL holds "Q"
pop r17
pop r18
pop r19
pop r2

ret

;**** End of function Div16_23 -----------------------------------------****

;***************************************************************************
; macro definition to call/use "division by xx" - module (D16_nn)
macro Div16by
push r20
ldi r20,@0
call D16_nn
pop r20
.endm
;***************************************************************************

;***************************************************************************
;*
;* Function "D16_nn"
;* Divides an unsigned 16 bit word by [2] -> [23]
;* Note: divisor 2, 4, 8, 16 options are provided for remainder calculation
;* and (for ease-of-use) to cover the complete divisors range (2-23)
;*
;* Call with dividend loaded to XH:XL (high/low bytes)
;* Returns quotient in YH:YL and remainder in XL
;*
;* Usage: define the macro "Div16by" prior to using the function,
;* use macro with divisor as parameter, e.g. "Div16by 17" to
;* divide XH:XL by 17 decimal
;*
;* .macro Div16_by
;* push r20
;* ldi r20,@0
;* call D16_nn
;* pop r20
;* .endm
;*
;* Author: Andreas Lenze (andreas.lenze@t-online.de)
;* Feb. 2003
;* Equations mostly by D. W. Jones
;*
;* Reciprocal mul w. extra precision:
;* unsigned int A;
;* unsigned int scaled_reciprocal = xxxx
;* unsigned int Q; /* the quotient */
;*
;* Q = ((A * scaled_reciprocal) >> 16) >> nn
;* or
;* Q = (((A * scaled_reciprocal) >> 16) + A) >> nn -> for /7 and /14
;*
;* /* special case: use correction for Q (e.g. for /21, /23) */
;* if (R >= divisor)
;* R = R - divisor;
;* Q = Q + 1;
;*
;* div. by n: scaled reciprocal: shift count:
;*
;* 2 - 1
;* 3 1010101010101011 AAAB 17
;* 4 - 2
;* 5 1100110011001101 CCCD 18
;* 6 1010101010101011 AAAB 18
;* 7 10010010010010011 19 -> 17 bits req'd,(MSB=1,rest 2493h)
;* 8 - 3
;* 9 1110001110001111 E38F 19
;* 10 1100110011001101 CCCD 19
;* 11 1011101000101111 BA2F 19
;* 12 1010101010101011 AAAB 19
;* 13 1001110110001010 9D8A 19
;* 14 10010010010010011 20 -> 17 bits req'd,(MSB=1,rest 2493h)
;* 15 1000100010001001 8889 19
;* 16 - 4
;* 17 1111000011110001 F0F1 20
;* 18 1110001110001111 E38F 20
;* 19 0110101111001011 6BCB 19
;* 20 1100110011001101 CCCD 20
;* 21 1100001100001011 C30B 20 -> needs correction for accurate
result
;* 22 1011101000101111 BA2F 20
;* 23 1011001000010101 B215 20 -> needs correction for accurate
result
;*
;* Uses: high regs: 11 (r16, r17, r18, r19, r20, X, Y, Z)
;* low regs: 3 (r0, r1, r2)
;* regs 16-20 saved, all others destroyed
;* T-flag destroyed (cleared)
;*
;* words: 97 (incl. 5 words for macro)
;* cycles: 85-111 (w. call/ret & macro), typically 102
;* table bytes: 66
;*
;* Target: AVR MCUs with hardware multiplier ("mul" instruction and
;* "lpm rd,Z/Z+" functionality required)
;*
;***************************************************************************

D16_nT:
; look-up table for D16_nn: 3 bytes per entry, range for divisor "2" to "23"
; data format: 2 bytes scaled reciprocal (word, high/low), 3rd byte
"flags"
.cseg
.db 0x00, 0xFF, 0x01, 0xAA, 0xAB, 0x01, 0x00, 0xFF, 0x02, 0xCC, 0xCD, 0x02,
0xAA, 0xAB
;
by /2 /3 /4 /5 /6

.db 0x02, 0x24, 0x93, 0x13, 0x00, 0xFF, 0x03, 0xE3, 0x8F, 0x03, 0xCC, 0xCD,
0x03, 0xBA
;
by /7 /8 /9 /10 /11

.db 0x2F, 0x03, 0xAA, 0xAB, 0x03, 0x9D, 0x8A, 0x03, 0x24, 0x93, 0x14, 0x88,
0x89, 0x03
;by /12 /13 /14 /15

.db 0x00, 0xFF, 0x04, 0xF0, 0xF1, 0x04, 0xE3, 0x8F, 0x04, 0x6B, 0xCB, 0x03,
0xCC, 0xCD
;
by /16 /17 /18 /19 /20

.db 0x04, 0xC3, 0x0B, 0x04, 0xBA, 0x2F, 0x04, 0xB2, 0x15, 0x04
;by /21 /22 /23

D16_nn:
push r19 ; save scrap regs
push r18
push r17
push r16

clt ; make sure T-flag is cleared

push r20 ; save divisor
cpi r20,24 ; exit if divisor > 23
brsh D16_0
subi r20,2
brmi D16_0 ; exit if divisor <= 1

ldi ZH,high(D16_nT*2)
ldi ZL,low(D16_nT*2)
clr r2
mov r1,r20
lsl r20 ; x2 (3 bytes per entry)
add r20,r1 ; + org value = x3
add ZL,r20 ; point Z to divisor's data table position
adc ZH,r2

lpm YH,Z+ ; scaled reciprocal for /xx

lpm YL,Z+ ; Z now points at flags
cpi YL,0xFF ; low byte "FFh" in the scaled_reciprocal data
; indicates divisor 2, 4, 8, 16 -> no 'mul' req.
brne D16_1 ; != FFh -> mul required
mov r19,XH ; FFh: no div., shifts only: move input
mov r18,XL ; to "result registers" and go to shifts
rjmp D16_2 ; directly (saves ~18 cycles)

D16_0: pop r20 ; clean up stack before exit

rjmp D16_Err ; intermediate label (avoid "out of reach" for
brxx)

; Q = A * scaled_reciprocal
; (r19:r18:r17:r16 = XH:XL * YH:YL)
D16_1: clr r2
mul XH, YH ; ah * bh
movw r19:r18, r1:r0
mul XL, YL ; al * bl
mov r17,r1 ; r0 to r16 is superfluous
mul XH, YL ; ah * bl
add r17, r0
adc r18, r1
adc r19, r2
mul YH, XL ; bh * al
add r17, r0
adc r18, r1
adc r19, r2

; Q = Q >> 16: use r19:r18 as word

; do the remaining shifts
D16_2: lpm r20,Z ; fetch "flag"

cpi r20,3 ; flag = 3 -> 3 normal shifts required

breq D16_6 ; (div. 8, 9, 10, 11, 12, 13, 15, 19)

cpi r20,4 ; flag = 4 -> 4 normal shifts required

breq D16_3 ; (div. 16, 17, 18, 20, 21, 22, 23)

cpi r20,2 ; flag = 2 -> 2 normal shifts required

breq D16_7 ; (div. 4, 5, 6)

cpi r20,1 ; flag = 1 -> 1 normal shift required

breq D16_8 ; (div. 2, 3)

cpi r20,0x14 ; flag = 4spec -> 4 special shifts required

breq D16_5 ; (div. 14, extra addition, 1st shift w. carry)

cpi r20,0x13 ; flag = 3spec -> 3 special shifts required

breq D16_4 ; (div. 7, extra addition, 1st shift w. carry)
rjmp D16_Err ; no valid flags, exit

; Q = Q >> 4
D16_3: swap r18 ; 4 normal shifts
swap r19
andi r18,0x0F
eor r18,r19
andi r19,0x0F
eor r18,r19
rjmp D16_9

http://avr-asm.tripod.com/div16xx.html (2 of 3)1/20/2009 8:39:37 PM

AVR MATH YX

; Q = (Q + A) >> 3-4
D16_4: set
D16_5: add r18,XL ; (Q + A)
adc r19,XH
ror r19 ; 3-4 "special" shifts, include
ror r18 ; carry from previous addition into 1st shift
D16_6: lsr r19
ror r18
D16_7: lsr r19
ror r18
brts D16_9 ; if T-flag set, skip this shift
D16_8: lsr r19
ror r18

; r19:r18 now "Q" (= result >> yy)

; R = A - xx*Q;
D16_9: pop r16 ; multiply r19:r18 by divisor

mul r18, r16 ; al * bl

sub XL,r0
clr XH
movw YL,r18 ; make copy of Q

; XL = "R" (remainder)
; /* use correction - can be omitted if /21, /23 are not used */
; if (R >= divisor)
; R = R - divisor;
; Q = Q + 1;
cp XL,r16
brlo PC+3
sub XL,r16
adiw YL,1

; YH:YL = "Q" (quotient, result)

D16_Err:clt ; make sure T-flag is cleared
pop r16 ; restore regs
pop r17
pop r18
pop r19
ret

;**** End of function D16_nn -------------------------------------------****

Programming the AVR Microcontrollers in Machine Language

AVR
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr)
Jump to: navigation, search The AVRs are a family of RISC
microcontrollers from Atmel. Their internal architecture was conceived by
two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute
of Technology (NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the Atmel AVR32
line of microcontrollers. These are 32-bit RISC devices featuring SIMD and
DSP instructions, along with many additional features for audio and video
processing, intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR
Microcontrollers. The acronym AVR has been reported to stand for
Advanced Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned about it.
Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory
and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2
Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel
Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other AVR
Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with programs and
data stored and addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external memory
(though still available on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory. Each instruction
for the AVR line is either 16 or 32 bits in length. The Flash memory is
addressed using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the ATmega64x
line has 64Kbytes of Flash. Almost all AVR devices are self-programmable.
[edit] Data Memory and Registers The data address space consists of the
register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The working registers
are mapped in as the first thirty-two memory spaces (000016-001F16)
followed by the 64 I/O registers (002016-005F16). The actual usable RAM
starts after both these sections (address 006016). (Note that the I/O register
space may be larger on some more extensive devices, in which case
memory mapped I/O registers will occupy a portion of the SRAM.) Even
though there are separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed and
manipulated as if they were in SRAM. [edit] EEPROM Almost all devices
have on-die EEPROM. This is most often used for long-term parameter
storage to be retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline design. The
next machine instruction is fetched as the current one is executing. Most
instructions take just one or two clock cycles, making AVRs relatively fast
among the eight-bit microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The AVR
instruction set is more orthogonal than most eight-bit microcontrollers,
however, it is not completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other. Register
locations R0 to R15 have different addressing capabilities than register
locations R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not,
even though they are complementary instructions. CLR set all bits to zero
and SER sets them to one. (Note though, that neither CLR nor SER are
native instructions. Instead CLR is syntactic sugar for [produces the same
machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF.
Math operations such as EOR modify flags while moves/loads/stores/
branches such as LDI do not.) [edit] Speed The AVR line can normally
support clock speeds from 0-16MHz, with some devices reaching 20MHz.
Lower powered operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external clocks or
resonator circuitry. Because many operations on the AVR are single cycle,
the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a
large following due to the free and inexpensive development tools
available, including reasonably priced development boards and free
development software. The AVRs are marketed under various names that
share the same basic core but with different peripheral and memory
combinations. Some models (notably, the ATmega range) have additional
instructions to make arithmetic faster. Compatibility amongst chips is fairly
good. See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC Core Running
Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with
Internal, Configurable Pull-up Resistors Multiple Internal Oscillators
Internal, Self-Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage methods
Optional Boot Code Section with Independent Lock Bits for Protection
Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit
Timers PWM Channels & dead time generator Lighting (PWM Specific)
Controller models Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used
with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed hardware &
Hub controller with embedded AVR. Also freely available low-speed (HID)
software emulation Ethernet Controller Support Universal Serial Interface
(USI) for Two or Three-Wire Synchronous Data Transfer Analog
Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex
of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-
voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep
Modes picoPower Devices Atmel AVR assembler programming language
Atmel AVR machine programming language Atmel AVR From Wikipedia,
the free encyclopedia (Redirected from Avr) Jump to: navigation, search
The AVRs are a family of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen and Vegard
Wollan, at the Norwegian Institute of Technology (NTH] and further
developed at Atmel Norway, a subsidiary founded by the two architects.
Atmel recently released the Atmel AVR32 line of microcontrollers. These
are 32-bit RISC devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing, intended to
compete with ARM based processors. Note that the use of "AVR" in this
article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced Virtual RISC. It's
also rumoured to stand for the company's founders: Alf and Vegard, who
are evasive when questioned about it. Contents [hide] 1 Device Overview
1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See
also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion
Groups 6.3 Machine Language Development 6.4 C Language Development
6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other
AVR Links [edit] Device Overview The AVR is a Harvard architecture
machine with programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die, removing the need
for external memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-permanent Flash
memory. Each instruction for the AVR line is either 16 or 32 bits in length.
The Flash memory is addressed using 16 bit word sizes. The size of the
program memory is indicated in the naming of the device itself. For
instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and SRAM. The
AVRs have thirty-two single-byte registers and are classified as 8-bit RISC
devices. The working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O registers (002016-
005F16). The actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on some more
extensive devices, in which case memory mapped I/O registers will occupy
a portion of the SRAM.) Even though there are separate addressing
schemes and optimized opcodes for register file and I/O register access, all
can still be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is most often used
for long-term parameter storage to be retrieved even after cycling the
power of the device. [edit] Program Execution Atmel's AVRs have a single
level pipeline design. The next machine instruction is fetched as the
current one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit microcontrollers.
The AVR family of processors were designed for the efficient execution of
compiled C code. The AVR instruction set is more orthogonal than most
eight-bit microcontrollers, however, it is not completely regular: Pointer
registers X, Y, and Z have addressing capabilities that are different from
each other. Register locations R0 to R15 have different addressing
capabilities than register locations R16 to R31. I/O ports 0 to 31 have
different addressing capabilities than I/O ports 32 to 63. CLR affects flags,
while SER does not, even though they are complementary instructions.
CLR set all bits to zero and SER sets them to one. (Note though, that
neither CLR nor SER are native instructions. Instead CLR is syntactic
sugar for [produces the same machine code as] EOR R,R while SER is
syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit] Speed The
AVR line can normally support clock speeds from 0-16MHz, with some
devices reaching 20MHz. Lower powered operation usually requires a
reduced clock speed. All AVRs feature an on-chip oscillator, removing the
need for external clocks or resonator circuitry. Because many operations
on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz.
[edit] Development AVRs have a large following due to the free and
inexpensive development tools available, including reasonably priced
development boards and free development software. The AVRs are
marketed under various names that share the same basic core but with
different peripheral and memory combinations. Some models (notably, the
ATmega range) have additional instructions to make arithmetic faster.
Compatibility amongst chips is fairly good. See external links for sites
relating to AVR development. [edit] Features Current AVRs offer a wide
range of features: RISC Core Running Many Single Cycle Instructions
Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-Programmable
Instruction Flash Memory up to 256K In-System Programmable using ICSP,
JTAG, or High Voltage methods Optional Boot Code Section with
Independent Lock Bits for Protection Internal Data EEPROM up to 4KB
Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time
generator Lighting (PWM Specific) Controller models Dedicated I²C
Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial
Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB Controller Support
Proper High-speed hardware & Hub controller with embedded AVR. Also
freely available low-speed (HID) software emulation Ethernet Controller
Support Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD Controller Support
10-Bit A/D Converters, with multiplex of up to 16 channels Brownout
Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to
1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine programming
language Atmel AVR From Wikipedia, the free encyclopedia (Redirected
from Avr) Jump to: navigation, search The AVRs are a family of RISC
microcontrollers from Atmel. Their internal architecture was conceived by
two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute
of Technology (NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the Atmel AVR32
line of microcontrollers. These are 32-bit RISC devices featuring SIMD and
DSP instructions, along with many additional features for audio and video
processing, intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR
Microcontrollers. The acronym AVR has been reported to stand for
Advanced Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned about it.
Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory
and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2
Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel
Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other AVR
Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with programs and
data stored and addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external memory
(though still available on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory. Each instruction
for the AVR line is either 16 or 32 bits in length. The Flash memory is
addressed using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the ATmega64x
line has 64Kbytes of Flash. Almost all AVR devices are self-programmable.
[edit] Data Memory and Registers The data address space consists of the
register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The working registers
are mapped in as the first thirty-two memory spaces (000016-001F16)
followed by the 64 I/O registers (002016-005F16). The actual usable RAM
starts after both these sections (address 006016). (Note that the I/O register
space may be larger on some more extensive devices, in which case
memory mapped I/O registers will occupy a portion of the SRAM.) Even
though there are separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed and
manipulated as if they were in SRAM. [edit] EEPROM Almost all devices
have on-die EEPROM. This is most often used for long-term parameter
storage to be retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline design. The
next machine instruction is fetched as the current one is executing. Most
instructions take just one or two clock cycles, making AVRs relatively fast
among the eight-bit microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The AVR
instruction set is more orthogonal than most eight-bit microcontrollers,
however, it is not completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other. Register
locations R0 to R15 have different addressing capabilities than register
locations R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not,
even though they are complementary instructions. CLR set all bits to zero
and SER sets them to one. (Note though, that neither CLR nor SER are
native instructions. Instead CLR is syntactic sugar for [produces the same
machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF.
Math operations such as EOR modify flags while moves/loads/stores/
branches such as LDI do not.) [edit] Speed The AVR line can normally
support clock speeds from 0-16MHz, with some devices reaching 20MHz.
Lower powered operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external clocks or
resonator circuitry. Because many operations on the AVR are single cycle,
the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a
large following due to the free and inexpensive development tools
available, including reasonably priced development boards and free
development software. The AVRs are marketed under various names that
share the same basic core but with different peripheral and memory
combinations. Some models (notably, the ATmega range) have additional
instructions to make arithmetic faster. Compatibility amongst chips is fairly
good. See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC Core Running
Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with
Internal, Configurable Pull-up Resistors Multiple Internal Oscillators
Internal, Self-Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage methods
Optional Boot Code Section with Independent Lock Bits for Protection
Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit
Timers PWM Channels & dead time generator Lighting (PWM Specific)
Controller models Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used
with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed hardware &
Hub controller with embedded AVR. Also freely available low-speed (HID)
software emulation Ethernet Controller Support Universal Serial Interface
(USI) for Two or Three-Wire Synchronous Data Transfer Analog
Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex
of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-
voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep
Modes picoPower Devices Atmel AVR assembler programming language
Atmel AVR machine programming language

http://avr-asm.tripod.com/div16xx.html (3 of 3)1/20/2009 8:39:37 PM

AVR MATH YX

The AVR Assembler Site

24 BIT BY 24 BIT DIVISION ROUTINE

HOME
RETRO_DAN
;******** div24u ***********
ASM FORUM ;*Division 24/24
ASM MATH ;* Dividend(dvd)
;* Result = ---------------
TUTORIAL #1
;* Divisor(dvr)
TUTORIAL #2 ;*
TUTORIAL #3 ;*

MATH 200 .def rem24L =r3

MATH 200b .def rem24M =r4
.def rem24H =r5
MATH 201 .def result24L =r9
MATH 202 .def result24M =r10
.def result24H =r11
MATH 32X
.def dvd24L =r9
MATH YX .def dvd24M =r10
.def dvd24H =r11
DIV16 XX
.def dvr24L =r12
DIV 24 24 .def dvr24M =r13
DIV 3216 .def dvr24H =r14

FLOAT 128 ;*Unsigned* Division 24bit/24bit

SQRT16
div24u: clr rem24L ;clear remainder Low byte
MATH 202 clr rem24M ;clear remainder mid byte
MATH 202 sub rem24H,rem24H ;clear remainder High byte and
carry
DEC ASCII
ldi rLoopCnt1,25 ;init loop counter
INT ASCII
d16u_1: rol dvd24L ;shift left dividend
HX2ASC
rol dvd24M
AVG8 222 rol dvd24H
FFT7 dec rLoopCnt1 ;decrement counter
brne d16u_2 ;if done
COPY 102 ret ; return
LPM 108
d16u_2: rol rem24L ;shift dividend into remainder
EPROM 100 rol rem24M
SER EPROM rol rem24H
sub rem24L,dvr24L ;remainder = remainder - divisor
DFLASH AT45
sbc rem24M,dvr24M ;
FLASH CARD sbc rem24H,dvr24H
brcc d16u_3 ;if result negative
VFX SMIL
add rem24L,dvr24L ; restore remainder
VFX MEM adc rem24M,dvr24M
SORT 220 adc rem24H,dvr24H
clc ; clear carry to be shifted into result
CRC 236 rjmp d16u_1 ;else
XMODEM REC d16u_3: sec ; set carry to be shifted into result
rjmp d16u_1
UART 304
UART 305 ret
UART 128
UART BUFF
USB 232
AVR ISP
ISP 2313
ISP 1200
AVR SPI
I2C 300
I2C 302
I2C TWI26 Programming the AVR Microcontrollers in Machine Language
I2C/TWI 128
I2C/TWI AT8 AVR
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ADC 128
Atmel AVR From Wikipedia, the free encyclopedia
ADC 10B
ADC 400 (Redirected from Avr) Jump to: navigation, search The AVRs
ADC 401 are a family of RISC microcontrollers from Atmel. Their
THERM 232
internal architecture was conceived by two students: Alf-Egil
IRD 410
LCD HD44 Bogen and Vegard Wollan, at the Norwegian Institute of
LCD 2313 Technology (NTH] and further developed at Atmel Norway, a
LCD44 2313
subsidiary founded by the two architects. Atmel recently
KBD 240
MUX 242 released the Atmel AVR32 line of microcontrollers. These are
KBD PS2 32-bit RISC devices featuring SIMD and DSP instructions,
KBD PC/128
along with many additional features for audio and video
PS2 EMU
BOOT MG8 processing, intended to compete with ARM based
BOOT DR8 processors. Note that the use of "AVR" in this article refers
ALM CLK
to the 8-bit RISC line of Atmel AVR Microcontrollers. The
CLOCK 8564
90 DAYS acronym AVR has been reported to stand for Advanced
DELAYS Virtual RISC. It's also rumoured to stand for the company's
CALL ID
founders: Alf and Vegard, who are evasive when questioned
DTMF 314
PWM 6CH
about it. Contents [hide] 1 Device Overview 1.1 Program
PWM 10K Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
ENCODE
Program Execution 1.5 Speed 2 Development 3 Features 4
STH-11
ATMEL CORP
Footnotes 5 See also 6 External Links 6.1 Atmel Official
AVR Links 6.2 AVR Forums & Discussion Groups 6.3 Machine
BUTTERFLY
AVR BOOK
Language Development 6.4 C Language Development 6.5
BASIC & Other AVR Languages 6.6 AVR Butterfly Specific
6.7 Other AVR Links [edit] Device Overview The AVR is a
Harvard architecture machine with programs and data stored
and addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line
is either 16 or 32 bits in length. The Flash memory is
addressed using 16 bit word sizes. The size of the program
memory is indicated in the naming of the device itself. For
instance, the ATmega64x line has 64Kbytes of Flash. Almost
all AVR devices are self-programmable. [edit] Data Memory
and Registers The data address space consists of the
register file, I/O registers, and SRAM. The AVRs have thirty-
two single-byte registers and are classified as 8-bit RISC
devices. The working registers are mapped in as the first
thirty-two memory spaces (000016-001F16) followed by the
64 I/O registers (002016-005F16). The actual usable RAM
starts after both these sections (address 006016). (Note that
the I/O register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities
that are different from each other. Register locations R0 to
R15 have different addressing capabilities than register
locations R16 to R31. I/O ports 0 to 31 have different
addressing capabilities than I/O ports 32 to 63. CLR affects
flags, while SER does not, even though they are
complementary instructions. CLR set all bits to zero and
SER sets them to one. (Note though, that neither CLR nor
SER are native instructions. Instead CLR is syntactic sugar
for [produces the same machine code as] EOR R,R while
SER is syntactic sugar for LDI R,$FF. Math operations such
as EOR modify flags while moves/loads/stores/branches
such as LDI do not.) [edit] Speed The AVR line can normally
support clock speeds from 0-16MHz, with some devices
reaching 20MHz. Lower powered operation usually requires
a reduced clock speed. All AVRs feature an on-chip
oscillator, removing the need for external clocks or
resonator circuitry. Because many operations on the AVR
are single cycle, the AVR can achieve up to 1MIPS per MHz.
[edit] Development AVRs have a large following due to the
free and inexpensive development tools available, including
reasonably priced development boards and free
development software. The AVRs are marketed under
various names that share the same basic core but with
different peripheral and memory combinations. Some
models (notably, the ATmega range) have additional
instructions to make arithmetic faster. Compatibility
amongst chips is fairly good. See external links for sites
relating to AVR development. [edit] Features Current AVRs
offer a wide range of features: RISC Core Running Many
Single Cycle Instructions Multifunction, Bi-directional I/O
Ports with Internal, Configurable Pull-up Resistors Multiple
Internal Oscillators Internal, Self-Programmable Instruction
Flash Memory up to 256K In-System Programmable using
ICSP, JTAG, or High Voltage methods Optional Boot Code
Section with Independent Lock Bits for Protection Internal
Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and
16-Bit Timers PWM Channels & dead time generator Lighting
(PWM Specific) Controller models Dedicated I²C Compatible
Two-Wire Interface (TWI) Synchronous/Asynchronous Serial
Peripherals (UART/USART) (As used with RS-232,RS-485,
and more) Serial Peripheral Interface (SPI) CAN Controller
Support USB Controller Support Proper High-speed
hardware & Hub controller with embedded AVR. Also freely
available low-speed (HID) software emulation Ethernet
Controller Support Universal Serial Interface (USI) for Two or
Three-Wire Synchronous Data Transfer Analog Comparators
LCD Controller Support 10-Bit A/D Converters, with multiplex
of up to 16 channels Brownout Detection Watchdog Timer
(WDT) Low-voltage Devices Operating Down to 1.8v Multiple
Power-Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the
Norwegian Institute of Technology (NTH] and further
developed at Atmel Norway, a subsidiary founded by the two
architects. Atmel recently released the Atmel AVR32 line of
microcontrollers. These are 32-bit RISC devices featuring
SIMD and DSP instructions, along with many additional
features for audio and video processing, intended to
compete with ARM based processors. Note that the use of
"AVR" in this article refers to the 8-bit RISC line of Atmel
AVR Microcontrollers. The acronym AVR has been reported
to stand for Advanced Virtual RISC. It's also rumoured to
stand for the company's founders: Alf and Vegard, who are
evasive when questioned about it. Contents [hide] 1 Device
Overview 1.1 Program Memory 1.2 Data Memory and
Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2
Development 3 Features 4 Footnotes 5 See also 6 External
Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion
Groups 6.3 Machine Language Development 6.4 C Language
Development 6.5 BASIC & Other AVR Languages 6.6 AVR
Butterfly Specific 6.7 Other AVR Links [edit] Device Overview
The AVR is a Harvard architecture machine with programs
and data stored and addressed separately. Flash, EEPROM,
and SRAM are all integrated onto a single die, removing the
need for external memory (though still available on some
devices). [edit] Program Memory Program instructions are
stored in semi-permanent Flash memory. Each instruction
for the AVR line is either 16 or 32 bits in length. The Flash
memory is addressed using 16 bit word sizes. The size of the
program memory is indicated in the naming of the device
itself. For instance, the ATmega64x line has 64Kbytes of
Flash. Almost all AVR devices are self-programmable. [edit]
Data Memory and Registers The data address space
consists of the register file, I/O registers, and SRAM. The
AVRs have thirty-two single-byte registers and are classified
as 8-bit RISC devices. The working registers are mapped in
as the first thirty-two memory spaces (000016-001F16)
followed by the 64 I/O registers (002016-005F16). The actual
usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory
mapped I/O registers will occupy a portion of the SRAM.)
Even though there are separate addressing schemes and
optimized opcodes for register file and I/O register access,
all can still be addressed and manipulated as if they were in
SRAM. [edit] EEPROM Almost all devices have on-die
EEPROM. This is most often used for long-term parameter
storage to be retrieved even after cycling the power of the
device. [edit] Program Execution Atmel's AVRs have a single
level pipeline design. The next machine instruction is
fetched as the current one is executing. Most instructions
take just one or two clock cycles, making AVRs relatively
fast among the eight-bit microcontrollers. The AVR family of
processors were designed for the efficient execution of
compiled C code. The AVR instruction set is more
orthogonal than most eight-bit microcontrollers, however, it
is not completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other.
Register locations R0 to R15 have different addressing
capabilities than register locations R16 to R31. I/O ports 0 to
31 have different addressing capabilities than I/O ports 32 to
63. CLR affects flags, while SER does not, even though they
are complementary instructions. CLR set all bits to zero and
SER sets them to one. (Note though, that neither CLR nor
SER are native instructions. Instead CLR is syntactic sugar
for [produces the same machine code as] EOR R,R while
SER is syntactic sugar for LDI R,$FF. Math operations such
as EOR modify flags while moves/loads/stores/branches
such as LDI do not.) [edit] Speed The AVR line can normally
support clock speeds from 0-16MHz, with some devices
reaching 20MHz. Lower powered operation usually requires
a reduced clock speed. All AVRs feature an on-chip
oscillator, removing the need for external clocks or
resonator circuitry. Because many operations on the AVR
are single cycle, the AVR can achieve up to 1MIPS per MHz.
[edit] Development AVRs have a large following due to the
free and inexpensive development tools available, including
reasonably priced development boards and free
development software. The AVRs are marketed under
various names that share the same basic core but with
different peripheral and memory combinations. Some
models (notably, the ATmega range) have additional
instructions to make arithmetic faster. Compatibility
amongst chips is fairly good. See external links for sites
relating to AVR development. [edit] Features Current AVRs
offer a wide range of features: RISC Core Running Many
Single Cycle Instructions Multifunction, Bi-directional I/O
Ports with Internal, Configurable Pull-up Resistors Multiple
Internal Oscillators Internal, Self-Programmable Instruction
Flash Memory up to 256K In-System Programmable using
ICSP, JTAG, or High Voltage methods Optional Boot Code
Section with Independent Lock Bits for Protection Internal
Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and
16-Bit Timers PWM Channels & dead time generator Lighting
(PWM Specific) Controller models Dedicated I²C Compatible
Two-Wire Interface (TWI) Synchronous/Asynchronous Serial
Peripherals (UART/USART) (As used with RS-232,RS-485,
and more) Serial Peripheral Interface (SPI) CAN Controller
Support USB Controller Support Proper High-speed
hardware & Hub controller with embedded AVR. Also freely
available low-speed (HID) software emulation Ethernet
Controller Support Universal Serial Interface (USI) for Two or
Three-Wire Synchronous Data Transfer Analog Comparators
LCD Controller Support 10-Bit A/D Converters, with multiplex
of up to 16 channels Brownout Detection Watchdog Timer
(WDT) Low-voltage Devices Operating Down to 1.8v Multiple
Power-Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the
Norwegian Institute of Technology (NTH] and further
developed at Atmel Norway, a subsidiary founded by the two
architects. Atmel recently released the Atmel AVR32 line of
microcontrollers. These are 32-bit RISC devices featuring
SIMD and DSP instructions, along with many additional
features for audio and video processing, intended to
compete with ARM based processors. Note that the use of
"AVR" in this article refers to the 8-bit RISC line of Atmel
AVR Microcontrollers. The acronym AVR has been reported
to stand for Advanced Virtual RISC. It's also rumoured to
stand for the company's founders: Alf and Vegard, who are
evasive when questioned about it. Contents [hide] 1 Device
Overview 1.1 Program Memory 1.2 Data Memory and
Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2
Development 3 Features 4 Footnotes 5 See also 6 External
Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion
Groups 6.3 Machine Language Development 6.4 C Language
Development 6.5 BASIC & Other AVR Languages 6.6 AVR
Butterfly Specific 6.7 Other AVR Links [edit] Device Overview
The AVR is a Harvard architecture machine with programs
and data stored and addressed separately. Flash, EEPROM,
and SRAM are all integrated onto a single die, removing the
need for external memory (though still available on some
devices). [edit] Program Memory Program instructions are
stored in semi-permanent Flash memory. Each instruction
for the AVR line is either 16 or 32 bits in length. The Flash
memory is addressed using 16 bit word sizes. The size of the
program memory is indicated in the naming of the device
itself. For instance, the ATmega64x line has 64Kbytes of
Flash. Almost all AVR devices are self-programmable. [edit]
Data Memory and Registers The data address space
consists of the register file, I/O registers, and SRAM. The
AVRs have thirty-two single-byte registers and are classified
as 8-bit RISC devices. The working registers are mapped in
as the first thirty-two memory spaces (000016-001F16)
followed by the 64 I/O registers (002016-005F16). The actual
usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory
mapped I/O registers will occupy a portion of the SRAM.)
Even though there are separate addressing schemes and
optimized opcodes for register file and I/O register access,
all can still be addressed and manipulated as if they were in
SRAM. [edit] EEPROM Almost all devices have on-die
EEPROM. This is most often used for long-term parameter
storage to be retrieved even after cycling the power of the
device. [edit] Program Execution Atmel's AVRs have a single
level pipeline design. The next machine instruction is
fetched as the current one is executing. Most instructions
take just one or two clock cycles, making AVRs relatively
fast among the eight-bit microcontrollers. The AVR family of
processors were designed for the efficient execution of
compiled C code. The AVR instruction set is more
orthogonal than most eight-bit microcontrollers, however, it
is not completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other.
Register locations R0 to R15 have different addressing
capabilities than register locations R16 to R31. I/O ports 0 to
31 have different addressing capabilities than I/O ports 32 to
63. CLR affects flags, while SER does not, even though they
are complementary instructions. CLR set all bits to zero and
SER sets them to one. (Note though, that neither CLR nor
SER are native instructions. Instead CLR is syntactic sugar
for [produces the same machine code as] EOR R,R while
SER is syntactic sugar for LDI R,$FF. Math operations such
as EOR modify flags while moves/loads/stores/branches
such as LDI do not.) [edit] Speed The AVR line can normally
support clock speeds from 0-16MHz, with some devices
reaching 20MHz. Lower powered operation usually requires
a reduced clock speed. All AVRs feature an on-chip
oscillator, removing the need for external clocks or
resonator circuitry. Because many operations on the AVR
are single cycle, the AVR can achieve up to 1MIPS per MHz.
[edit] Development AVRs have a large following due to the
free and inexpensive development tools available, including
reasonably priced development boards and free
development software. The AVRs are marketed under
various names that share the same basic core but with
different peripheral and memory combinations. Some
models (notably, the ATmega range) have additional
instructions to make arithmetic faster. Compatibility
amongst chips is fairly good. See external links for sites
relating to AVR development. [edit] Features Current AVRs
offer a wide range of features: RISC Core Running Many
Single Cycle Instructions Multifunction, Bi-directional I/O
Ports with Internal, Configurable Pull-up Resistors Multiple
Internal Oscillators Internal, Self-Programmable Instruction
Flash Memory up to 256K In-System Programmable using
ICSP, JTAG, or High Voltage methods Optional Boot Code
Section with Independent Lock Bits for Protection Internal
Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and
16-Bit Timers PWM Channels & dead time generator Lighting
(PWM Specific) Controller models Dedicated I²C Compatible
Two-Wire Interface (TWI) Synchronous/Asynchronous Serial
Peripherals (UART/USART) (As used with RS-232,RS-485,
and more) Serial Peripheral Interface (SPI) CAN Controller
Support USB Controller Support Proper High-speed
hardware & Hub controller with embedded AVR. Also freely
available low-speed (HID) software emulation Ethernet
Controller Support Universal Serial Interface (USI) for Two or
Three-Wire Synchronous Data Transfer Analog Comparators
LCD Controller Support 10-Bit A/D Converters, with multiplex
of up to 16 channels Brownout Detection Watchdog Timer
(WDT) Low-voltage Devices Operating Down to 1.8v Multiple
Power-Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language
http://avr-asm.tripod.com/div2424.html (1 of 2)1/20/2009 8:40:09 PM
AVR MATH YX

http://avr-asm.tripod.com/div2424.html (2 of 2)1/20/2009 8:40:09 PM

AVR MATH YX

The AVR Assembler Site

32 BIT BY 16 BIT DIVISION ROUTINE

HOME
RETRO_DAN
;divide r21:r18/refH:refL result in XH:
ASM FORUM XL
ASM MATH __DIVD21U:
CLR XL
TUTORIAL #1
CLR XH
TUTORIAL #2 CLR R0
TUTORIAL #3 CLR R1
LDI R17,32
MATH 200 __DIVD21U1:
MATH 200b LSL R18
ROL R19
MATH 201 ROL R20
MATH 202 ROL R21
ROL XL
MATH 32X
ROL XH
MATH YX ROL R0
ROL R1
DIV16 XX
SUB XL,scaleL
DIV 24 24 SBC XH,scaleH
DIV 3216 SBC R0,zeroreg
SBC R1,zeroreg
FLOAT 128 BRCC __DIVD21U2
SQRT16 ADD XL,scaleL
ADC XH,scaleH
MATH 202 ADC R0,zeroreg
MATH 202 ADC R1,zeroreg
RJMP __DIVD21U3
DEC ASCII
__DIVD21U2:
INT ASCII SBR R18,1
__DIVD21U3:
HX2ASC
DEC R17
AVG8 222 BRNE __DIVD21U1
FFT7 mov XL, r19
mov XH, r18 ; result in X
COPY 102
LPM 108 ret

EPROM 100
SER EPROM
DFLASH AT45
FLASH CARD
VFX SMIL
VFX MEM
SORT 220
CRC 236
XMODEM REC
UART 304 Programming the AVR Microcontrollers in Machine Language
UART 305
UART 128 AVR
UART BUFF << Prev | Ring Hub | Join | Rate| Next
USB 232 >>
© WebRing Inc. Search
AVR ISP
ISP 2313
ISP 1200
Atmel AVR From Wikipedia, the free encyclopedia
AVR SPI
I2C 300
(Redirected from Avr) Jump to: navigation, search
I2C 302 The AVRs are a family of RISC microcontrollers
I2C TWI26
from Atmel. Their internal architecture was
I2C/TWI 128
I2C/TWI AT8
conceived by two students: Alf-Egil Bogen and
DALLAS-1W Vegard Wollan, at the Norwegian Institute of
DALLAS CRC
Technology (NTH] and further developed at Atmel
ETHNET 8019
TEA
Norway, a subsidiary founded by the two architects.
ADC 128 Atmel recently released the Atmel AVR32 line of
ADC 10B
microcontrollers. These are 32-bit RISC devices
ADC 400
ADC 401
featuring SIMD and DSP instructions, along with
THERM 232 many additional features for audio and video
IRD 410
processing, intended to compete with ARM based
LCD HD44
LCD 2313
processors. Note that the use of "AVR" in this
LCD44 2313 article refers to the 8-bit RISC line of Atmel AVR
KBD 240 Microcontrollers. The acronym AVR has been
MUX 242
KBD PS2
reported to stand for Advanced Virtual RISC. It's
KBD PC/128 also rumoured to stand for the company's founders:
PS2 EMU Alf and Vegard, who are evasive when questioned
BOOT MG8
BOOT DR8
about it. Contents [hide] 1 Device Overview 1.1
ALM CLK Program Memory 1.2 Data Memory and Registers
CLOCK 8564 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2
90 DAYS
DELAYS
Development 3 Features 4 Footnotes 5 See also 6
CALL ID External Links 6.1 Atmel Official Links 6.2 AVR
DTMF 314 Forums & Discussion Groups 6.3 Machine
PWM 6CH
PWM 10K
Language Development 6.4 C Language
ENCODE Development 6.5 BASIC & Other AVR Languages 6.6
STH-11 AVR Butterfly Specific 6.7 Other AVR Links [edit]
ATMEL CORP
AVR
Device Overview The AVR is a Harvard architecture
BUTTERFLY machine with programs and data stored and
AVR BOOK
addressed separately. Flash, EEPROM, and SRAM
are all integrated onto a single die, removing the
need for external memory (though still available on
some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash
memory. Each instruction for the AVR line is either
16 or 32 bits in length. The Flash memory is
addressed using 16 bit word sizes. The size of the
program memory is indicated in the naming of the
device itself. For instance, the ATmega64x line has
64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers
The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two
single-byte registers and are classified as 8-bit RISC
devices. The working registers are mapped in as the
first thirty-two memory spaces (000016-001F16)
followed by the 64 I/O registers (002016-005F16).
The actual usable RAM starts after both these
sections (address 006016). (Note that the I/O
register space may be larger on some more
extensive devices, in which case memory mapped I/
O registers will occupy a portion of the SRAM.)
Even though there are separate addressing
schemes and optimized opcodes for register file
and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM.
This is most often used for long-term parameter
storage to be retrieved even after cycling the power
of the device. [edit] Program Execution Atmel's
AVRs have a single level pipeline design. The next
machine instruction is fetched as the current one is
executing. Most instructions take just one or two
clock cycles, making AVRs relatively fast among the
eight-bit microcontrollers. The AVR family of
processors were designed for the efficient
execution of compiled C code. The AVR instruction
set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely
regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each
other. Register locations R0 to R15 have different
addressing capabilities than register locations R16
to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects
flags, while SER does not, even though they are
complementary instructions. CLR set all bits to zero
and SER sets them to one. (Note though, that
neither CLR nor SER are native instructions. Instead
CLR is syntactic sugar for [produces the same
machine code as] EOR R,R while SER is syntactic
sugar for LDI R,$FF. Math operations such as EOR
modify flags while moves/loads/stores/branches
such as LDI do not.) [edit] Speed The AVR line can
normally support clock speeds from 0-16MHz, with
some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed.
All AVRs feature an on-chip oscillator, removing the
need for external clocks or resonator circuitry.
Because many operations on the AVR are single
cycle, the AVR can achieve up to 1MIPS per MHz.
[edit] Development AVRs have a large following due
to the free and inexpensive development tools
available, including reasonably priced development
boards and free development software. The AVRs
are marketed under various names that share the
same basic core but with different peripheral and
memory combinations. Some models (notably, the
ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is
fairly good. See external links for sites relating to
AVR development. [edit] Features Current AVRs
offer a wide range of features: RISC Core Running
Many Single Cycle Instructions Multifunction, Bi-
directional I/O Ports with Internal, Configurable Pull-
up Resistors Multiple Internal Oscillators Internal,
Self-Programmable Instruction Flash Memory up to
256K In-System Programmable using ICSP, JTAG,
or High Voltage methods Optional Boot Code
Section with Independent Lock Bits for Protection
Internal Data EEPROM up to 4KB Internal SRAM up
to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller
models Dedicated I²C Compatible Two-Wire
Interface (TWI) Synchronous/Asynchronous Serial
Peripherals (UART/USART) (As used with RS-232,
RS-485, and more) Serial Peripheral Interface (SPI)
CAN Controller Support USB Controller Support
Proper High-speed hardware & Hub controller with
embedded AVR. Also freely available low-speed
(HID) software emulation Ethernet Controller
Support Universal Serial Interface (USI) for Two or
Three-Wire Synchronous Data Transfer Analog
Comparators LCD Controller Support 10-Bit A/D
Converters, with multiplex of up to 16 channels
Brownout Detection Watchdog Timer (WDT) Low-
voltage Devices Operating Down to 1.8v Multiple
Power-Saving Sleep Modes picoPower Devices
Atmel AVR assembler programming language Atmel
AVR machine programming language Atmel AVR
From Wikipedia, the free encyclopedia (Redirected
from Avr) Jump to: navigation, search The AVRs are
a family of RISC microcontrollers from Atmel. Their
internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the
Norwegian Institute of Technology (NTH] and further
developed at Atmel Norway, a subsidiary founded
by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-
bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for
audio and video processing, intended to compete
with ARM based processors. Note that the use of
"AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has
been reported to stand for Advanced Virtual RISC.
It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when
questioned about it. Contents [hide] 1 Device
Overview 1.1 Program Memory 1.2 Data Memory and
Registers 1.3 EEPROM 1.4 Program Execution 1.5
Speed 2 Development 3 Features 4 Footnotes 5 See
also 6 External Links 6.1 Atmel Official Links 6.2
AVR Forums & Discussion Groups 6.3 Machine
Language Development 6.4 C Language
Development 6.5 BASIC & Other AVR Languages 6.6
AVR Butterfly Specific 6.7 Other AVR Links [edit]
Device Overview The AVR is a Harvard architecture
machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM
are all integrated onto a single die, removing the
need for external memory (though still available on
some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash
memory. Each instruction for the AVR line is either
16 or 32 bits in length. The Flash memory is
addressed using 16 bit word sizes. The size of the
program memory is indicated in the naming of the
device itself. For instance, the ATmega64x line has
64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers
The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two
single-byte registers and are classified as 8-bit RISC
devices. The working registers are mapped in as the
first thirty-two memory spaces (000016-001F16)
followed by the 64 I/O registers (002016-005F16).
The actual usable RAM starts after both these
sections (address 006016). (Note that the I/O
register space may be larger on some more
extensive devices, in which case memory mapped I/
O registers will occupy a portion of the SRAM.)
Even though there are separate addressing
schemes and optimized opcodes for register file
and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM.
This is most often used for long-term parameter
storage to be retrieved even after cycling the power
of the device. [edit] Program Execution Atmel's
AVRs have a single level pipeline design. The next
machine instruction is fetched as the current one is
executing. Most instructions take just one or two
clock cycles, making AVRs relatively fast among the
eight-bit microcontrollers. The AVR family of
processors were designed for the efficient
execution of compiled C code. The AVR instruction
set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely
regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each
other. Register locations R0 to R15 have different
addressing capabilities than register locations R16
to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects
flags, while SER does not, even though they are
complementary instructions. CLR set all bits to zero
and SER sets them to one. (Note though, that
neither CLR nor SER are native instructions. Instead
CLR is syntactic sugar for [produces the same
machine code as] EOR R,R while SER is syntactic
sugar for LDI R,$FF. Math operations such as EOR
modify flags while moves/loads/stores/branches
such as LDI do not.) [edit] Speed The AVR line can
normally support clock speeds from 0-16MHz, with
some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed.
All AVRs feature an on-chip oscillator, removing the
need for external clocks or resonator circuitry.
Because many operations on the AVR are single
cycle, the AVR can achieve up to 1MIPS per MHz.
[edit] Development AVRs have a large following due
to the free and inexpensive development tools
available, including reasonably priced development
boards and free development software. The AVRs
are marketed under various names that share the
same basic core but with different peripheral and
memory combinations. Some models (notably, the
ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is
fairly good. See external links for sites relating to
AVR development. [edit] Features Current AVRs
offer a wide range of features: RISC Core Running
Many Single Cycle Instructions Multifunction, Bi-
directional I/O Ports with Internal, Configurable Pull-
up Resistors Multiple Internal Oscillators Internal,
Self-Programmable Instruction Flash Memory up to
256K In-System Programmable using ICSP, JTAG,
or High Voltage methods Optional Boot Code
Section with Independent Lock Bits for Protection
Internal Data EEPROM up to 4KB Internal SRAM up
to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller
models Dedicated I²C Compatible Two-Wire
Interface (TWI) Synchronous/Asynchronous Serial
Peripherals (UART/USART) (As used with RS-232,
RS-485, and more) Serial Peripheral Interface (SPI)
CAN Controller Support USB Controller Support
Proper High-speed hardware & Hub controller with
embedded AVR. Also freely available low-speed
(HID) software emulation Ethernet Controller
Support Universal Serial Interface (USI) for Two or
Three-Wire Synchronous Data Transfer Analog
Comparators LCD Controller Support 10-Bit A/D
Converters, with multiplex of up to 16 channels
Brownout Detection Watchdog Timer (WDT) Low-
voltage Devices Operating Down to 1.8v Multiple
Power-Saving Sleep Modes picoPower Devices
Atmel AVR assembler programming language Atmel
AVR machine programming language Atmel AVR
From Wikipedia, the free encyclopedia (Redirected
from Avr) Jump to: navigation, search The AVRs are
a family of RISC microcontrollers from Atmel. Their
internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the
Norwegian Institute of Technology (NTH] and further
developed at Atmel Norway, a subsidiary founded
by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-
bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for
audio and video processing, intended to compete
with ARM based processors. Note that the use of
"AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has
been reported to stand for Advanced Virtual RISC.
It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when
questioned about it. Contents [hide] 1 Device
Overview 1.1 Program Memory 1.2 Data Memory and
Registers 1.3 EEPROM 1.4 Program Execution 1.5
Speed 2 Development 3 Features 4 Footnotes 5 See
also 6 External Links 6.1 Atmel Official Links 6.2
AVR Forums & Discussion Groups 6.3 Machine
Language Development 6.4 C Language
Development 6.5 BASIC & Other AVR Languages 6.6
AVR Butterfly Specific 6.7 Other AVR Links [edit]
Device Overview The AVR is a Harvard architecture
machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM
are all integrated onto a single die, removing the
need for external memory (though still available on
some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash
memory. Each instruction for the AVR line is either
16 or 32 bits in length. The Flash memory is
addressed using 16 bit word sizes. The size of the
program memory is indicated in the naming of the
device itself. For instance, the ATmega64x line has
64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers
The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two
single-byte registers and are classified as 8-bit RISC
devices. The working registers are mapped in as the
first thirty-two memory spaces (000016-001F16)
followed by the 64 I/O registers (002016-005F16).
The actual usable RAM starts after both these
sections (address 006016). (Note that the I/O
register space may be larger on some more
extensive devices, in which case memory mapped I/
O registers will occupy a portion of the SRAM.)
Even though there are separate addressing
schemes and optimized opcodes for register file
and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM.
This is most often used for long-term parameter
storage to be retrieved even after cycling the power
of the device. [edit] Program Execution Atmel's
AVRs have a single level pipeline design. The next
machine instruction is fetched as the current one is
executing. Most instructions take just one or two
clock cycles, making AVRs relatively fast among the
eight-bit microcontrollers. The AVR family of
processors were designed for the efficient
execution of compiled C code. The AVR instruction
set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely
regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each
other. Register locations R0 to R15 have different
addressing capabilities than register locations R16
to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects
flags, while SER does not, even though they are
complementary instructions. CLR set all bits to zero
and SER sets them to one. (Note though, that
neither CLR nor SER are native instructions. Instead
CLR is syntactic sugar for [produces the same
machine code as] EOR R,R while SER is syntactic
sugar for LDI R,$FF. Math operations such as EOR
modify flags while moves/loads/stores/branches
such as LDI do not.) [edit] Speed The AVR line can
normally support clock speeds from 0-16MHz, with
some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed.
All AVRs feature an on-chip oscillator, removing the
need for external clocks or resonator circuitry.
Because many operations on the AVR are single
cycle, the AVR can achieve up to 1MIPS per MHz.
[edit] Development AVRs have a large following due
to the free and inexpensive development tools
available, including reasonably priced development
boards and free development software. The AVRs
are marketed under various names that share the
same basic core but with different peripheral and
memory combinations. Some models (notably, the
ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is
fairly good. See external links for sites relating to
AVR development. [edit] Features Current AVRs
offer a wide range of features: RISC Core Running
Many Single Cycle Instructions Multifunction, Bi-
directional I/O Ports with Internal, Configurable Pull-
up Resistors Multiple Internal Oscillators Internal,
Self-Programmable Instruction Flash Memory up to
256K In-System Programmable using ICSP, JTAG,
or High Voltage methods Optional Boot Code
Section with Independent Lock Bits for Protection
Internal Data EEPROM up to 4KB Internal SRAM up
to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller
models Dedicated I²C Compatible Two-Wire
Interface (TWI) Synchronous/Asynchronous Serial
Peripherals (UART/USART) (As used with RS-232,
RS-485, and more) Serial Peripheral Interface (SPI)
CAN Controller Support USB Controller Support
Proper High-speed hardware & Hub controller with
embedded AVR. Also freely available low-speed
(HID) software emulation Ethernet Controller
Support Universal Serial Interface (USI) for Two or
Three-Wire Synchronous Data Transfer Analog
Comparators LCD Controller Support 10-Bit A/D
Converters, with multiplex of up to 16 channels
Brownout Detection Watchdog Timer (WDT) Low-
voltage Devices Operating Down to 1.8v Multiple
Power-Saving Sleep Modes picoPower Devices
Atmel AVR assembler programming language Atmel
AVR machine programming language
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AVR MATH YX

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AVR MATH YX

The AVR Assembler Site

FLOATING POINT MATH

HOME
RETRO_DAN
;***************************************************************************
ASM FORUM ;
ASM MATH ; File Name :'Main.asm"
; Title :Matmatikai rutinok, test verzio
TUTORIAL #1
; Date :2003.07.16.
TUTORIAL #2 ; Version :1.0.0
TUTORIAL #3 ; Support telephone :+36-70-333-4034
; Support fax :
MATH 200 ; Support Email :info@vfx.hu
MATH 200b ; Target MCU :ATmega128
;
MATH 201 ;***************************************************************************
MATH 202 ; D E S C R I P T I O N
;
MATH 32X
;
MATH YX ;***************************************************************************
; M O D I F I C A T I O N H I S T O R Y
DIV16 XX
;
DIV 24 24 ;
DIV 3216 ; rev. date who why
; ---- ---------- --- -----------------------------------
FLOAT 128 ; 0.01 2003.07.16 VFX Creation, mult
SQRT16 ; 0.02 2004.03.30 VFX Add float add & sub
;
MATH 202 ;
MATH 202 ;***************************************************************************
;Hardware
DEC ASCII
;***************************************************************************
INT ASCII ;*
;* f=external 16MHz (t=-.--ns)
HX2ASC
;*
AVG8 222 ;***************************************************************************
FFT7 ;
;
COPY 102 ;
LPM 108 .include "m128def.inc"

EPROM 100 ;***************************************************************************

SER EPROM ;* Const Def
DFLASH AT45
FLASH CARD ;**************************************************************************
;* Hardware Def.
VFX SMIL
;
VFX MEM
SORT 220 ;***************************************************************************
;** VARIABLES
CRC 236 .DSEG
XMODEM REC
;***************************************************************************
UART 304 .ESEG
UART 305
;***************************************************************************
UART 128
;**** I N T E R R U P T S
UART BUFF ;****
;***************************************************************************
USB 232
.CSEG
AVR ISP
ISP 2313 RESET: CLI ;GLOBAL INTERRUP DIS.

ISP 1200 ldi R16, high(RAMEND) ;setup stack

AVR SPI out SPH,R16
ldi R16, low(RAMEND)
I2C 300 out SPL,R16
I2C 302
I2C TWI26
;PI/2 = 81 49 0F DA A2 Sign bit!!!
I2C/TWI 128 ;1,570796326734125614166259765625
I2C/TWI AT8
ldi R24,0x81 ;exponens
DALLAS-1W ldi R23,0xC9 ;mantissa
DALLAS CRC ldi R22,0x0F
ldi R21,0xDA
ETHNET 8019 ldi R20,0xA2
TEA mov R6,R24
mov R5,R23
ADC 128 mov R4,R22
ADC 10B mov R3,R21
mov R2,R20
ADC 400
ADC 401 ; const
THERM 232 ;0,79411764699034392833709716796875

IRD 410 ldi R24,0x80 ;exponens

LCD HD44 ldi R23,0x4b ;mantissa
ldi R22,0x4b
LCD 2313 ldi R21,0x4b
LCD44 2313 ldi R20,0x4b
KBD 240
MUX 242 ; rcall multiply
KBD PS2
rcall addition
KBD PC/128
PS2 EMU veges:
rjmp veges
BOOT MG8
BOOT DR8
; -----------------------------
ALM CLK ; Prepare to multiply or divide
CLOCK 8564 ; -----------------------------
; This routine is called in succession from multiply and divide to prepare
90 DAYS
; two mantissas by setting the leftmost bit that is used for the sign.
DELAYS ; m1: R25, R24:R21
; m2: R6, R5:R2
CALL ID
;
DTMF 314 ; T flag = Sign of result
PWM 6CH ; R6,R24 corrected exponent
; R5,R23 restored sign bit of mantissa
PWM 10K ;
ENCODE ; cycles + (RET) = Cycles
STH-11 PREP_Mul_Div:
ATMEL CORP mov R16,R5
eor R16,R23
AVR
bst R16,7 ;T flag = result sign bit
BUTTERFLY
AVR BOOK ldi R16,0xA0 ;Binary point offset is 0x20 to
integer number
ldi R17,0x80 ;MSB sign bit

tst R24
brne PREP_MD01 ;First number is floating point format
add R24,R16
rjmp PREP_MD02

PREP_MD01:
or R23,R17 ;restore msb bit
PREP_MD02:
tst R6
brne PREP_MD03 ;Second number is floating point format
add R6,R16
rjmp PREP_MD04

PREP_MD03:
or R5,R17 ;restore msb bit
PREP_MD04:
sub R24,R17
sub R6,R17 ;shift zero point by 0x80 (back
to 2's complement)
ret

; ------------------------------
; THE 'MULTIPLICATION' OPERATION
; ------------------------------
; (offset: $04 'multiply')
;
; m1: R6, R5:R2
; m2: R24, R23:R20
; -------------------
; Res: R6, R5:R2
;
; cycles + (RET) = Cycles
;
multiply:
rcall PREP_Mul_Div

mov R0,R2
or R0,R3
or R0,R4
or R0,R5
breq Res_Zero
mov R0,R20
or R0,R21
or R0,R22
or R0,R23
breq Res_Zero

rcall mult32
clr R7
rcall Normalize
sub R6,R16 ;shift exponent by
normalized value
brcs NumberTooBig
add R6,R24 ;2^x *2^y = 2^(x+y)
brvs NumberTooBig
ldi R16,0x80
sub R6,R16 ;set offset by 0x80

rcall Round
brcs NumberTooBig

ldi R17,0xFF
bld R17,7 ;get result sign bit
and R5,R17 ;set result sign bit

clc
ret
NumberTooBig:
sec
ret

Res_Zero:
clr R2
clr R3
movw R4,R2
clr R6
clc
ret

;***************************************************
;* Mutiply 32x32 -> 64 bit
;*
;* R23:R20 x R5:R2 -> R15:R8
;*
;* 86 cycles + 4 (RET) = 90 Cycles
;*
mult32:
clr R16
mul R20,R2
movw R8,R0
clr R10
clr R11
movw R12,R10
movw R14,R10
mul R21,R2
add R9,R0
adc R10,R1
mul R22,R2
add R10,R0
adc R11,R1
mul R23,R2
add R11,R0
adc R12,R1

mul R20,R3
add R9,R0
adc R10,R1
adc R11,R16
adc R12,R16
adc R13,R16
mul R21,R3
add R10,R0
adc R11,R1
adc R12,R16
adc R13,R16
mul R22,R3
add R11,R0
adc R12,R1
adc R13,R16
mul R23,R3
add R12,R0
adc R13,R1

mul R20,R4
add R10,R0
adc R11,R1
adc R12,R16
adc R13,R16
adc R14,R16
mul R21,R4
add R11,R0
adc R12,R1
adc R13,R16
adc R14,R16
mul R22,R4
add R12,R0
adc R13,R1
adc R14,R16
mul R23,R4
add R13,R0
adc R14,R1

mul R20,R5
add R11,R0
adc R12,R1
adc R13,R16
adc R14,R16
adc R15,R16
mul R21,R5
add R12,R0
adc R13,R1
adc R14,R16
adc R15,R16
mul R22,R5
add R13,R0
adc R14,R1
adc R15,R16
mul R23,R5
add R14,R0
adc R15,R1
ret

;**********************************************************
; R15:R8:R7 -> R15:R12
; R16 - 64-exponent
Normalize:
ldi R17,64 ;max 64 bitet kell vegigrotalni
Norm0: tst R15
brne Norm1
mov R15,R14
mov R14,R13
mov R13,R12
mov R12,R11
mov R11,R10
mov R10,R9
mov R9,R8
mov R8,R7
clr R7
subi R17,8
cpi R17,8
brne Norm0
Norm1:
;legnagyobb
helyiertek felrotalasa bit7-ig
sbrc R15,7
rjmp Norm2
lsl R7
rol R8
rol R9
rol R10
rol R11
rol R12
rol R13
rol R14
rol R15
dec R17
brne Norm1
Norm2:
ldi R16,64
sub R16,R17
;R16-ban az
exponens
ret

; -------------------------------
; THE 'PREPARE TO ADD' SUBROUTINE
; -------------------------------
; This routine is called twice by addition to prepare the two numbers.
; The sign bit is tested before being set to the implied state.
; Negative numbers are twos complemented.
;
; m1: R6, R5:R2 -> R6, R7:R5:R2
; m2: R24, R23:R20 -> R24, R25:R23:R20
; R25,R7 -> sign
;
PREP_ADD:
clr R25
clr R7
ldi R16,0x80

tst R24
brne Prep_Add1
mov R24,R16

;ide jon majd a normalas R23:R20

rjmp M1Pos

Prep_Add1:
bst R23,7 ;test the sign bit
or R23,R16 ;set it to implied state
brtc M1Pos ;jump if positive number
NEG_M1:
clr R8
clr R9
movw R10,R8
movw R12,R8 ;clear result regs

sub R8,R20 ;complement

sbc R9,R21 ;add in initial carry
or from prev operation
sbc R10,R22
sbc R11,R23
sbc R12,R13
movw R20,R8
movw R22,R10
mov R25,R12
M1Pos:

tst R6
brne Prep_Add2
mov R6,R16

;ide jon majd a normalas R5:R2

rjmp M2Pos

Prep_Add2:
bst R5,7 ;test the sign bit
or R5,R16 ;set it to implied state
brtc M2Pos ;jump if positive number
NEG_M2:
clr R8
clr R9
movw R10,R8
movw R12,R8 ;clear result regs

sub R8,R2 ;complement

sbc R9,R3 ;add in initial carry
or from prev operation
sbc R10,R4
sbc R11,R5
sbc R12,R13
movw R2,R8
movw R4,R10
mov R7,R12
M2Pos:
ret ;return

; -------------------------
; THE 'SHIFT FP Right' SUBROUTINE
; -------------------------
; In: mantissa R7:R5:R2
; Exponent : R6
; Shift right by R16
;
; Out: R17,R15,R14,R13,R12,R11,R10,R9,R8,R7
; s s s s s m m m m g
SHIFT_FP:
movw R12,R2
movw R14,R4
mov R17,R7
clr R7
clr R8
clr R9
movw R10,R8

tst R16
brne Shift_fp1
ret ;diff
== 0 no rota
Shift_fp1:
cpi R16,0x21 ;diff>33 bit
brcc ADDEND_0 ;we add 0 to 1st param

EIGHT_SHIFT:
cpi R16,8
brcs ONE_SHIFT
mov R7,R8
mov R8,R9
mov R9,R10
mov R10,R11
mov R11,R12
mov R12,R13
mov R13,R14
mov R14,R15
mov R15,R17
bst R17,7 ;negative
number?
clr R17
brtc SHIFT_FP2
ser R17
SHIFT_FP2: subi R16,8
rjmp EIGHT_SHIFT

ONE_SHIFT: bst R17,7 ;store sign bit

lsr R17
ror R15
ror R14
ror R13
ror R12
ror R11
ror R10
ror R9
ror R8
ror R7
bld R17,7 ;set back to
sign bit
dec R16
brne ONE_SHIFT
ret
ADDEND_0:
clr R7
clr R8
clr R9
movw R10,R8
movw R12,R8
movw R14,R8
movw R16,R8
ret

; ---------------------------
; THE 'SUBTRACTION' OPERATION
; ---------------------------
; (offset: $03 'subtract')

; m1: R6, R5:R2

; m2: R24, R23:R20
; -------------------
; Res: R6, R5:R2
;
; Subtraction is done by switching the sign byte/bit of the second
; number and continuing into addition.

subtract:
tst R24
brne Sub_NoZero
mov R0,R20
or R0,R21
or R0,R22
or R0,R23
brne addition
ret ;x - 0 = x
Sub_NoZero:
ori R23,0x80 ;make to negative

; ------------------------
; THE 'ADDITION' OPERATION
; ------------------------
; (offset: $0F 'addition')
;
; m1: R6, R5:R2
; m2: R24, R23:R20
; -------------------
; Res: R6, R5:R2
;
; cycles + (RET) = Cycles
;
addition:
rcall PREP_ADD
cp R24,R6 ;exp.
M1 < M2?
brcc SHIFT_LEN ;to SHIFT_LEN

movw R8,R2 ; exchange M1 &

M2
movw R2,R20
movw R20,R8

movw R8,R4
movw R4,R22
movw R22,R8

movw R8,R6
movw R6,R24
movw R24,R8
SHIFT_LEN:
mov R16,R24
sub R16,
R6 ;length of shift
mov R6,R24
rcall SHIFT_FP

; R17,R15,R14,R13,R12,R11,R10,R9,R8,
R7
; s m m m m m m m m g
; + R25,R23,R22,R21,R20 0 0 0 0
0
;---------------------------------------
; R17,R15,R14,R13,R12,R11,R10,R9,R8,
R7

add R12,R20
adc R13,R21
adc R14,R22
adc R15,R23
adc R17,R25
brlt NoAdd_Overf1

inc R6
brne Add_Rota
rjmp Add_Rep_6
Add_Rota:
ldi R16,1
rcall ONE_SHIFT

NoAdd_Overf1:
mov R20,R17 ;store sign
bst R17,7 ;sign =
positive?
brtc Add_Pos

clr R0 ;negate
clr R1
movw R2,R0
sub R0,R7
mov R7,R0
movw R0,R2

sbc R0,R8
sbc R1,R9
movw R8,R0

movw R0,R2
sbc R0,R10
sbc R1,R11
movw R10,R0

movw R0,R2
sbc R0,R12
sbc R1,R13
movw R12,R0

movw R0,R2
sbc R0,R14
sbc R1,R15
movw R14,R0

mov R0,R2
sbc R0,R17
mov R17,R0

Add_Pos:
tst R17
breq Add_Norm
inc R6
brne Add_Rota1
rjmp Add_Rep_6
Add_Rota1:
ldi R16,1
rcall ONE_SHIFT
rjmp Add_Pos

Add_Norm:
rcall Normalize

bst R15,7
brts Add_Norm1 ;ha 7. =0 ,akkor nincs mit tenni

rjmp Res_Zero

Add_Norm1:
sub R6,R16
breq Add_Rep_6
brcs Add_Rep_6

rcall Round
brcs Add_Rep_6

bst R20,7
brts Add_NegResult
ldi R16,0x7F
and R5,R16 ;make pos sign

Add_NegResult:
clc
ret

Add_Rep_6:
sec ;
overflow error
ret

Round:
movw R4,R14
movw R2,R12

;ide jon majd a kerekites

mov R0,R2
or R0,R3
or R0,R4
or R0,R5
brne Round1
clr R6
Round1:
clc
ret

Programming the AVR Microcontrollers in Machine Language

AVR
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© WebRing Inc. Search

Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr)
Jump to: navigation, search The AVRs are a family of RISC
microcontrollers from Atmel. Their internal architecture was conceived by
two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute
of Technology (NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the Atmel AVR32
line of microcontrollers. These are 32-bit RISC devices featuring SIMD and
DSP instructions, along with many additional features for audio and video
processing, intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR
Microcontrollers. The acronym AVR has been reported to stand for
Advanced Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned about it.
Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory
and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2
Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel
Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other AVR
Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with programs and
data stored and addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external memory
(though still available on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory. Each instruction
for the AVR line is either 16 or 32 bits in length. The Flash memory is
addressed using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the ATmega64x
line has 64Kbytes of Flash. Almost all AVR devices are self-programmable.
[edit] Data Memory and Registers The data address space consists of the
register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The working registers
are mapped in as the first thirty-two memory spaces (000016-001F16)
followed by the 64 I/O registers (002016-005F16). The actual usable RAM
starts after both these sections (address 006016). (Note that the I/O register
space may be larger on some more extensive devices, in which case
memory mapped I/O registers will occupy a portion of the SRAM.) Even
though there are separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed and
manipulated as if they were in SRAM. [edit] EEPROM Almost all devices
have on-die EEPROM. This is most often used for long-term parameter
storage to be retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline design. The
next machine instruction is fetched as the current one is executing. Most
instructions take just one or two clock cycles, making AVRs relatively fast
among the eight-bit microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The AVR
instruction set is more orthogonal than most eight-bit microcontrollers,
however, it is not completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other. Register
locations R0 to R15 have different addressing capabilities than register
locations R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not,
even though they are complementary instructions. CLR set all bits to zero
and SER sets them to one. (Note though, that neither CLR nor SER are
native instructions. Instead CLR is syntactic sugar for [produces the same
machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF.
Math operations such as EOR modify flags while moves/loads/stores/
branches such as LDI do not.) [edit] Speed The AVR line can normally
support clock speeds from 0-16MHz, with some devices reaching 20MHz.
Lower powered operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external clocks or
resonator circuitry. Because many operations on the AVR are single cycle,
the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a
large following due to the free and inexpensive development tools
available, including reasonably priced development boards and free
development software. The AVRs are marketed under various names that
share the same basic core but with different peripheral and memory
combinations. Some models (notably, the ATmega range) have additional
instructions to make arithmetic faster. Compatibility amongst chips is fairly
good. See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC Core Running
Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with
Internal, Configurable Pull-up Resistors Multiple Internal Oscillators
Internal, Self-Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage methods
Optional Boot Code Section with Independent Lock Bits for Protection
Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit
Timers PWM Channels & dead time generator Lighting (PWM Specific)
Controller models Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used
with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed hardware &
Hub controller with embedded AVR. Also freely available low-speed (HID)
software emulation Ethernet Controller Support Universal Serial Interface
(USI) for Two or Three-Wire Synchronous Data Transfer Analog
Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex
of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-
voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep
Modes picoPower Devices Atmel AVR assembler programming language
Atmel AVR machine programming language Atmel AVR From Wikipedia,
the free encyclopedia (Redirected from Avr) Jump to: navigation, search
The AVRs are a family of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen and Vegard
Wollan, at the Norwegian Institute of Technology (NTH] and further
developed at Atmel Norway, a subsidiary founded by the two architects.
Atmel recently released the Atmel AVR32 line of microcontrollers. These
are 32-bit RISC devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing, intended to
compete with ARM based processors. Note that the use of "AVR" in this
article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced Virtual RISC. It's
also rumoured to stand for the company's founders: Alf and Vegard, who
are evasive when questioned about it. Contents [hide] 1 Device Overview
1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See
also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion
Groups 6.3 Machine Language Development 6.4 C Language Development
6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other
AVR Links [edit] Device Overview The AVR is a Harvard architecture
machine with programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die, removing the need
for external memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-permanent Flash
memory. Each instruction for the AVR line is either 16 or 32 bits in length.
The Flash memory is addressed using 16 bit word sizes. The size of the
program memory is indicated in the naming of the device itself. For
instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and Registers The data
http://avr-asm.tripod.com/float128.html (1 of 2)1/20/2009 8:41:21 PM
AVR MATH YX

address space consists of the register file, I/O registers, and SRAM. The
AVRs have thirty-two single-byte registers and are classified as 8-bit RISC
devices. The working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O registers (002016-
005F16). The actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on some more
extensive devices, in which case memory mapped I/O registers will occupy
a portion of the SRAM.) Even though there are separate addressing
schemes and optimized opcodes for register file and I/O register access, all
can still be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is most often used
for long-term parameter storage to be retrieved even after cycling the
power of the device. [edit] Program Execution Atmel's AVRs have a single
level pipeline design. The next machine instruction is fetched as the
current one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit microcontrollers.
The AVR family of processors were designed for the efficient execution of
compiled C code. The AVR instruction set is more orthogonal than most
eight-bit microcontrollers, however, it is not completely regular: Pointer
registers X, Y, and Z have addressing capabilities that are different from
each other. Register locations R0 to R15 have different addressing
capabilities than register locations R16 to R31. I/O ports 0 to 31 have
different addressing capabilities than I/O ports 32 to 63. CLR affects flags,
while SER does not, even though they are complementary instructions.
CLR set all bits to zero and SER sets them to one. (Note though, that
neither CLR nor SER are native instructions. Instead CLR is syntactic
sugar for [produces the same machine code as] EOR R,R while SER is
syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit] Speed The
AVR line can normally support clock speeds from 0-16MHz, with some
devices reaching 20MHz. Lower powered operation usually requires a
reduced clock speed. All AVRs feature an on-chip oscillator, removing the
need for external clocks or resonator circuitry. Because many operations
on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz.
[edit] Development AVRs have a large following due to the free and
inexpensive development tools available, including reasonably priced
development boards and free development software. The AVRs are
marketed under various names that share the same basic core but with
different peripheral and memory combinations. Some models (notably, the
ATmega range) have additional instructions to make arithmetic faster.
Compatibility amongst chips is fairly good. See external links for sites
relating to AVR development. [edit] Features Current AVRs offer a wide
range of features: RISC Core Running Many Single Cycle Instructions
Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-Programmable
Instruction Flash Memory up to 256K In-System Programmable using ICSP,
JTAG, or High Voltage methods Optional Boot Code Section with
Independent Lock Bits for Protection Internal Data EEPROM up to 4KB
Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time
generator Lighting (PWM Specific) Controller models Dedicated I²C
Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial
Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB Controller Support
Proper High-speed hardware & Hub controller with embedded AVR. Also
freely available low-speed (HID) software emulation Ethernet Controller
Support Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD Controller Support
10-Bit A/D Converters, with multiplex of up to 16 channels Brownout
Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to
1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine programming
language Atmel AVR From Wikipedia, the free encyclopedia (Redirected
from Avr) Jump to: navigation, search The AVRs are a family of RISC
microcontrollers from Atmel. Their internal architecture was conceived by
two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute
of Technology (NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the Atmel AVR32
line of microcontrollers. These are 32-bit RISC devices featuring SIMD and
DSP instructions, along with many additional features for audio and video
processing, intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR
Microcontrollers. The acronym AVR has been reported to stand for
Advanced Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned about it.
Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory
and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2
Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel
Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other AVR
Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with programs and
data stored and addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external memory
(though still available on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory. Each instruction
for the AVR line is either 16 or 32 bits in length. The Flash memory is
addressed using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the ATmega64x
line has 64Kbytes of Flash. Almost all AVR devices are self-programmable.
[edit] Data Memory and Registers The data address space consists of the
register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The working registers
are mapped in as the first thirty-two memory spaces (000016-001F16)
followed by the 64 I/O registers (002016-005F16). The actual usable RAM
starts after both these sections (address 006016). (Note that the I/O register
space may be larger on some more extensive devices, in which case
memory mapped I/O registers will occupy a portion of the SRAM.) Even
though there are separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed and
manipulated as if they were in SRAM. [edit] EEPROM Almost all devices
have on-die EEPROM. This is most often used for long-term parameter
storage to be retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline design. The
next machine instruction is fetched as the current one is executing. Most
instructions take just one or two clock cycles, making AVRs relatively fast
among the eight-bit microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The AVR
instruction set is more orthogonal than most eight-bit microcontrollers,
however, it is not completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other. Register
locations R0 to R15 have different addressing capabilities than register
locations R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not,
even though they are complementary instructions. CLR set all bits to zero
and SER sets them to one. (Note though, that neither CLR nor SER are
native instructions. Instead CLR is syntactic sugar for [produces the same
machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF.
Math operations such as EOR modify flags while moves/loads/stores/
branches such as LDI do not.) [edit] Speed The AVR line can normally
support clock speeds from 0-16MHz, with some devices reaching 20MHz.
Lower powered operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external clocks or
resonator circuitry. Because many operations on the AVR are single cycle,
the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a
large following due to the free and inexpensive development tools
available, including reasonably priced development boards and free
development software. The AVRs are marketed under various names that
share the same basic core but with different peripheral and memory
combinations. Some models (notably, the ATmega range) have additional
instructions to make arithmetic faster. Compatibility amongst chips is fairly
good. See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC Core Running
Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with
Internal, Configurable Pull-up Resistors Multiple Internal Oscillators
Internal, Self-Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage methods
Optional Boot Code Section with Independent Lock Bits for Protection
Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit
Timers PWM Channels & dead time generator Lighting (PWM Specific)
Controller models Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used
with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed hardware &
Hub controller with embedded AVR. Also freely available low-speed (HID)
software emulation Ethernet Controller Support Universal Serial Interface
(USI) for Two or Three-Wire Synchronous Data Transfer Analog
Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex
of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-
voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep
Modes picoPower Devices Atmel AVR assembler programming language
Atmel AVR machine programming language

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AVR MATH YX

The AVR Assembler Site

16 SQUARE ROOT ROUTINE

HOME
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;
ASM FORUM *****************************************************************************
ASM MATH ;*
;* sqrt16 V 1.00
TUTORIAL #1
;*
TUTORIAL #2 ;* r16 - SQUARE LOW BYTE
TUTORIAL #3 ;* r17 - SQUARE HIGH BYTE
;*
MATH 200 ;* r18,19 - SQRT, returned in r16
MATH 200b ;*
;* Low registers used : None
MATH 201 ;* High registers used : r16 - r19, r24, r25,
MATH 202 r26
;*
MATH 32X
;
MATH YX *****************************************************************************
.area text
DIV16 XX
_sqrt16::
DIV 24 24 st -y,r18
DIV 3216 st -y,r19
st -y,r24
FLOAT 128 st -y,r25
SQRT16 st -y,r26
ldi r24,0 ; remainder low
MATH 202 ldi r25,0 ; remainder high
MATH 202 ldi r18,0 ; divisor low
ldi r19,0 ; divisor high
DEC ASCII
ldi r26,8 ; loop count
INT ASCII sqrt16loop:
lsl r18 ; divisor <<= 1
HX2ASC
rol r19
AVG8 222 lsl r16 ; shift two msb's into remainder
FFT7 rol r17
rol r24
COPY 102 rol r25
LPM 108 lsl r16
rol r17
EPROM 100 rol r24
SER EPROM rol r25
cp r18,r24 ; divisor < remainder ?
DFLASH AT45
cpc r19,r25
FLASH CARD brcc sqrt16bitdone
inc r18 ; divisor++, lsb = 0
VFX SMIL
sub r24,r18 ; remainder -= divisor
VFX MEM sbc r25,r19
SORT 220 inc r18 ; divisor++, bit_1 = 0
sqrt16bitdone:
CRC 236 dec r26 ; decrement loop count
XMODEM REC brne sqrt16loop ; branch if not done
lsr r19 ; root = divisor / 2
UART 304 ror r18
UART 305 mov r16,r18
ld r26,y+
UART 128
ld r25,y+
UART BUFF ld r24,y+
ld r19,y+
USB 232
ld r18,y+
AVR ISP ret
ISP 2313
ISP 1200
AVR SPI
I2C 300
I2C 302
I2C TWI26
I2C/TWI 128
I2C/TWI AT8
DALLAS-1W
DALLAS CRC
Programming the AVR Microcontrollers in Machine Language
ETHNET 8019
TEA AVR
ADC 128 << Prev | Ring Hub | Join | Rate| Next
ADC 10B >>
ADC 400 © WebRing Inc. Search
ADC 401
THERM 232
IRD 410
Atmel AVR From Wikipedia, the free encyclopedia
LCD HD44 (Redirected from Avr) Jump to: navigation, search The
LCD 2313 AVRs are a family of RISC microcontrollers from Atmel.
LCD44 2313
KBD 240
Their internal architecture was conceived by two students:
MUX 242 Alf-Egil Bogen and Vegard Wollan, at the Norwegian
KBD PS2 Institute of Technology (NTH] and further developed at
KBD PC/128
PS2 EMU
Atmel Norway, a subsidiary founded by the two architects.
BOOT MG8 Atmel recently released the Atmel AVR32 line of
BOOT DR8 microcontrollers. These are 32-bit RISC devices featuring
ALM CLK
CLOCK 8564
SIMD and DSP instructions, along with many additional
90 DAYS features for audio and video processing, intended to
DELAYS compete with ARM based processors. Note that the use of
CALL ID
DTMF 314
"AVR" in this article refers to the 8-bit RISC line of Atmel
PWM 6CH AVR Microcontrollers. The acronym AVR has been
PWM 10K reported to stand for Advanced Virtual RISC. It's also
ENCODE
STH-11
rumoured to stand for the company's founders: Alf and
ATMEL CORP Vegard, who are evasive when questioned about it.
AVR Contents [hide] 1 Device Overview 1.1 Program Memory
BUTTERFLY
AVR BOOK 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program
Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official
Links 6.2 AVR Forums & Discussion Groups 6.3 Machine
Language Development 6.4 C Language Development 6.5
BASIC & Other AVR Languages 6.6 AVR Butterfly Specific
6.7 Other AVR Links [edit] Device Overview The AVR is a
Harvard architecture machine with programs and data
stored and addressed separately. Flash, EEPROM, and
SRAM are all integrated onto a single die, removing the
need for external memory (though still available on some
devices). [edit] Program Memory Program instructions are
stored in semi-permanent Flash memory. Each instruction
for the AVR line is either 16 or 32 bits in length. The Flash
memory is addressed using 16 bit word sizes. The size of
the program memory is indicated in the naming of the
device itself. For instance, the ATmega64x line has
64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers,
and SRAM. The AVRs have thirty-two single-byte registers
and are classified as 8-bit RISC devices. The working
registers are mapped in as the first thirty-two memory
spaces (000016-001F16) followed by the 64 I/O registers
(002016-005F16). The actual usable RAM starts after both
these sections (address 006016). (Note that the I/O register
space may be larger on some more extensive devices, in
which case memory mapped I/O registers will occupy a
portion of the SRAM.) Even though there are separate
addressing schemes and optimized opcodes for register
file and I/O register access, all can still be addressed and
manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most
often used for long-term parameter storage to be retrieved
even after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the
current one is executing. Most instructions take just one or
two clock cycles, making AVRs relatively fast among the
eight-bit microcontrollers. The AVR family of processors
were designed for the efficient execution of compiled C
code. The AVR instruction set is more orthogonal than
most eight-bit microcontrollers, however, it is not
completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other.
Register locations R0 to R15 have different addressing
capabilities than register locations R16 to R31. I/O ports 0
to 31 have different addressing capabilities than I/O ports
32 to 63. CLR affects flags, while SER does not, even
though they are complementary instructions. CLR set all
bits to zero and SER sets them to one. (Note though, that
neither CLR nor SER are native instructions. Instead CLR
is syntactic sugar for [produces the same machine code
as] EOR R,R while SER is syntactic sugar for LDI R,$FF.
Math operations such as EOR modify flags while moves/
loads/stores/branches such as LDI do not.) [edit] Speed
The AVR line can normally support clock speeds from 0-
16MHz, with some devices reaching 20MHz. Lower
powered operation usually requires a reduced clock
speed. All AVRs feature an on-chip oscillator, removing
the need for external clocks or resonator circuitry.
Because many operations on the AVR are single cycle, the
AVR can achieve up to 1MIPS per MHz. [edit] Development
AVRs have a large following due to the free and
inexpensive development tools available, including
reasonably priced development boards and free
development software. The AVRs are marketed under
various names that share the same basic core but with
different peripheral and memory combinations. Some
models (notably, the ATmega range) have additional
instructions to make arithmetic faster. Compatibility
amongst chips is fairly good. See external links for sites
relating to AVR development. [edit] Features Current AVRs
offer a wide range of features: RISC Core Running Many
Single Cycle Instructions Multifunction, Bi-directional I/O
Ports with Internal, Configurable Pull-up Resistors Multiple
Internal Oscillators Internal, Self-Programmable Instruction
Flash Memory up to 256K In-System Programmable using
ICSP, JTAG, or High Voltage methods Optional Boot Code
Section with Independent Lock Bits for Protection Internal
Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and
16-Bit Timers PWM Channels & dead time generator
Lighting (PWM Specific) Controller models Dedicated I²C
Compatible Two-Wire Interface (TWI) Synchronous/
Asynchronous Serial Peripherals (UART/USART) (As used
with RS-232,RS-485, and more) Serial Peripheral Interface
(SPI) CAN Controller Support USB Controller Support
Proper High-speed hardware & Hub controller with
embedded AVR. Also freely available low-speed (HID)
software emulation Ethernet Controller Support Universal
Serial Interface (USI) for Two or Three-Wire Synchronous
Data Transfer Analog Comparators LCD Controller Support
10-Bit A/D Converters, with multiplex of up to 16 channels
Brownout Detection Watchdog Timer (WDT) Low-voltage
Devices Operating Down to 1.8v Multiple Power-Saving
Sleep Modes picoPower Devices Atmel AVR assembler
programming language Atmel AVR machine programming
language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers
from Atmel. Their internal architecture was conceived by
two students: Alf-Egil Bogen and Vegard Wollan, at the
Norwegian Institute of Technology (NTH] and further
developed at Atmel Norway, a subsidiary founded by the
two architects. Atmel recently released the Atmel AVR32
line of microcontrollers. These are 32-bit RISC devices
featuring SIMD and DSP instructions, along with many
additional features for audio and video processing,
intended to compete with ARM based processors. Note
that the use of "AVR" in this article refers to the 8-bit RISC
line of Atmel AVR Microcontrollers. The acronym AVR has
been reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it.
Contents [hide] 1 Device Overview 1.1 Program Memory
1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program
Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official
Links 6.2 AVR Forums & Discussion Groups 6.3 Machine
Language Development 6.4 C Language Development 6.5
BASIC & Other AVR Languages 6.6 AVR Butterfly Specific
6.7 Other AVR Links [edit] Device Overview The AVR is a
Harvard architecture machine with programs and data
stored and addressed separately. Flash, EEPROM, and
SRAM are all integrated onto a single die, removing the
need for external memory (though still available on some
devices). [edit] Program Memory Program instructions are
stored in semi-permanent Flash memory. Each instruction
for the AVR line is either 16 or 32 bits in length. The Flash
memory is addressed using 16 bit word sizes. The size of
the program memory is indicated in the naming of the
device itself. For instance, the ATmega64x line has
64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers,
and SRAM. The AVRs have thirty-two single-byte registers
and are classified as 8-bit RISC devices. The working
registers are mapped in as the first thirty-two memory
spaces (000016-001F16) followed by the 64 I/O registers
(002016-005F16). The actual usable RAM starts after both
these sections (address 006016). (Note that the I/O register
space may be larger on some more extensive devices, in
which case memory mapped I/O registers will occupy a
portion of the SRAM.) Even though there are separate
addressing schemes and optimized opcodes for register
file and I/O register access, all can still be addressed and
manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most
often used for long-term parameter storage to be retrieved
even after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the
current one is executing. Most instructions take just one or
two clock cycles, making AVRs relatively fast among the
eight-bit microcontrollers. The AVR family of processors
were designed for the efficient execution of compiled C
code. The AVR instruction set is more orthogonal than
most eight-bit microcontrollers, however, it is not
completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other.
Register locations R0 to R15 have different addressing
capabilities than register locations R16 to R31. I/O ports 0
to 31 have different addressing capabilities than I/O ports
32 to 63. CLR affects flags, while SER does not, even
though they are complementary instructions. CLR set all
bits to zero and SER sets them to one. (Note though, that
neither CLR nor SER are native instructions. Instead CLR
is syntactic sugar for [produces the same machine code
as] EOR R,R while SER is syntactic sugar for LDI R,$FF.
Math operations such as EOR modify flags while moves/
loads/stores/branches such as LDI do not.) [edit] Speed
The AVR line can normally support clock speeds from 0-
16MHz, with some devices reaching 20MHz. Lower
powered operation usually requires a reduced clock
speed. All AVRs feature an on-chip oscillator, removing
the need for external clocks or resonator circuitry.
Because many operations on the AVR are single cycle, the
AVR can achieve up to 1MIPS per MHz. [edit] Development
AVRs have a large following due to the free and
inexpensive development tools available, including
reasonably priced development boards and free
development software. The AVRs are marketed under
various names that share the same basic core but with
different peripheral and memory combinations. Some
models (notably, the ATmega range) have additional
instructions to make arithmetic faster. Compatibility
amongst chips is fairly good. See external links for sites
relating to AVR development. [edit] Features Current AVRs
offer a wide range of features: RISC Core Running Many
Single Cycle Instructions Multifunction, Bi-directional I/O
Ports with Internal, Configurable Pull-up Resistors Multiple
Internal Oscillators Internal, Self-Programmable Instruction
Flash Memory up to 256K In-System Programmable using
ICSP, JTAG, or High Voltage methods Optional Boot Code
Section with Independent Lock Bits for Protection Internal
Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and
16-Bit Timers PWM Channels & dead time generator
Lighting (PWM Specific) Controller models Dedicated I²C
Compatible Two-Wire Interface (TWI) Synchronous/
Asynchronous Serial Peripherals (UART/USART) (As used
with RS-232,RS-485, and more) Serial Peripheral Interface
(SPI) CAN Controller Support USB Controller Support
Proper High-speed hardware & Hub controller with
embedded AVR. Also freely available low-speed (HID)
software emulation Ethernet Controller Support Universal
Serial Interface (USI) for Two or Three-Wire Synchronous
Data Transfer Analog Comparators LCD Controller Support
10-Bit A/D Converters, with multiplex of up to 16 channels
Brownout Detection Watchdog Timer (WDT) Low-voltage
Devices Operating Down to 1.8v Multiple Power-Saving
Sleep Modes picoPower Devices Atmel AVR assembler
programming language Atmel AVR machine programming
language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers
from Atmel. Their internal architecture was conceived by
two students: Alf-Egil Bogen and Vegard Wollan, at the
Norwegian Institute of Technology (NTH] and further
developed at Atmel Norway, a subsidiary founded by the
two architects. Atmel recently released the Atmel AVR32
line of microcontrollers. These are 32-bit RISC devices
featuring SIMD and DSP instructions, along with many
additional features for audio and video processing,
intended to compete with ARM based processors. Note
that the use of "AVR" in this article refers to the 8-bit RISC
line of Atmel AVR Microcontrollers. The acronym AVR has
been reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it.
Contents [hide] 1 Device Overview 1.1 Program Memory
1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program
Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official
Links 6.2 AVR Forums & Discussion Groups 6.3 Machine
Language Development 6.4 C Language Development 6.5
BASIC & Other AVR Languages 6.6 AVR Butterfly Specific
6.7 Other AVR Links [edit] Device Overview The AVR is a
Harvard architecture machine with programs and data
stored and addressed separately. Flash, EEPROM, and
SRAM are all integrated onto a single die, removing the
need for external memory (though still available on some
devices). [edit] Program Memory Program instructions are
stored in semi-permanent Flash memory. Each instruction
for the AVR line is either 16 or 32 bits in length. The Flash
memory is addressed using 16 bit word sizes. The size of
the program memory is indicated in the naming of the
device itself. For instance, the ATmega64x line has
64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers,
and SRAM. The AVRs have thirty-two single-byte registers
and are classified as 8-bit RISC devices. The working
registers are mapped in as the first thirty-two memory
spaces (000016-001F16) followed by the 64 I/O registers
(002016-005F16). The actual usable RAM starts after both
these sections (address 006016). (Note that the I/O register
space may be larger on some more extensive devices, in
which case memory mapped I/O registers will occupy a
portion of the SRAM.) Even though there are separate
addressing schemes and optimized opcodes for register
file and I/O register access, all can still be addressed and
manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most
often used for long-term parameter storage to be retrieved
even after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the
current one is executing. Most instructions take just one or
two clock cycles, making AVRs relatively fast among the
eight-bit microcontrollers. The AVR family of processors
were designed for the efficient execution of compiled C
code. The AVR instruction set is more orthogonal than
most eight-bit microcontrollers, however, it is not
completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other.
Register locations R0 to R15 have different addressing
capabilities than register locations R16 to R31. I/O ports 0
to 31 have different addressing capabilities than I/O ports
32 to 63. CLR affects flags, while SER does not, even
though they are complementary instructions. CLR set all
bits to zero and SER sets them to one. (Note though, that
neither CLR nor SER are native instructions. Instead CLR
is syntactic sugar for [produces the same machine code
as] EOR R,R while SER is syntactic sugar for LDI R,$FF.
Math operations such as EOR modify flags while moves/
loads/stores/branches such as LDI do not.) [edit] Speed
The AVR line can normally support clock speeds from 0-
16MHz, with some devices reaching 20MHz. Lower
powered operation usually requires a reduced clock
speed. All AVRs feature an on-chip oscillator, removing
the need for external clocks or resonator circuitry.
Because many operations on the AVR are single cycle, the
AVR can achieve up to 1MIPS per MHz. [edit] Development
AVRs have a large following due to the free and
inexpensive development tools available, including
reasonably priced development boards and free
development software. The AVRs are marketed under
various names that share the same basic core but with
different peripheral and memory combinations. Some
models (notably, the ATmega range) have additional
instructions to make arithmetic faster. Compatibility
amongst chips is fairly good. See external links for sites
relating to AVR development. [edit] Features Current AVRs
offer a wide range of features: RISC Core Running Many
Single Cycle Instructions Multifunction, Bi-directional I/O
Ports with Internal, Configurable Pull-up Resistors Multiple
Internal Oscillators Internal, Self-Programmable Instruction
Flash Memory up to 256K In-System Programmable using
ICSP, JTAG, or High Voltage methods Optional Boot Code
Section with Independent Lock Bits for Protection Internal
Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and
16-Bit Timers PWM Channels & dead time generator
Lighting (PWM Specific) Controller models Dedicated I²C
Compatible Two-Wire Interface (TWI) Synchronous/
Asynchronous Serial Peripherals (UART/USART) (As used
with RS-232,RS-485, and more) Serial Peripheral Interface
(SPI) CAN Controller Support USB Controller Support
Proper High-speed hardware & Hub controller with
embedded AVR. Also freely available low-speed (HID)
software emulation Ethernet Controller Support Universal
Serial Interface (USI) for Two or Three-Wire Synchronous
Data Transfer Analog Comparators LCD Controller Support
10-Bit A/D Converters, with multiplex of up to 16 channels
Brownout Detection Watchdog Timer (WDT) Low-voltage
Devices Operating Down to 1.8v Multiple Power-Saving
Sleep Modes picoPower Devices Atmel AVR assembler
programming language Atmel AVR machine programming
language

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AVR MATH YX

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16 BIT MATH (AVR 202)

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BCD MATH (AVR 204)

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;**** A P P L I C A T I O N N O T E A V R 2 0 4 ************************
ASM FORUM ;*
ASM MATH ;* Title: BCD Arithmetics
;* Version: 1.1
TUTORIAL #1
;* Last updated: 97.07.04
TUTORIAL #2 ;* Target: AT90Sxxxx (All AVR Devices)
TUTORIAL #3 ;*
;* Support E-mail: avr@atmel.com
MATH 200 ;*
MATH 200b ;* DESCRIPTION
;* This Application Note lists subroutines for the following Binary Coded
MATH 201 ;* Decimal arithmetic applications:
MATH 202 ;*
;* Binary 16 to BCD Conversion (special considerations for AT90Sxx0x)
MATH 32X
;* Binary 8 to BCD Conversion
MATH YX ;* BCD to Binary 16 Conversion
;* BCD to Binary 8 Conversion
DIV16 XX
;* 2-Digit BCD Addition
DIV 24 24 ;* 2-Digit BCD Subtraction
DIV 3216 ;*
;***************************************************************************
FLOAT 128
SQRT16 .include "8515def.inc"

MATH 202 rjmp RESET ;reset handle

MATH 202
;***************************************************************************
DEC ASCII
;*
INT ASCII ;* "bin2BCD16" - 16-bit Binary to BCD conversion
;*
HX2ASC
;* This subroutine converts a 16-bit number (fbinH:fbinL) to a 5-digit
AVG8 222 ;* packed BCD number represented by 3 bytes (tBCD2:tBCD1:tBCD0).
FFT7 ;* MSD of the 5-digit number is placed in the lowermost nibble of tBCD2.
;*
COPY 102 ;* Number of words :25
LPM 108 ;* Number of cycles :751/768 (Min/Max)
;* Low registers used :3 (tBCD0,tBCD1,tBCD2)
EPROM 100 ;* High registers used :4(fbinL,fbinH,cnt16a,tmp16a)
SER EPROM ;* Pointers used :Z
;*
DFLASH AT45
;***************************************************************************
FLASH CARD
;***** Subroutine Register Variables
VFX SMIL
VFX MEM .equ AtBCD0 =13 ;address of tBCD0
SORT 220 .equ AtBCD2 =15 ;address of tBCD1

CRC 236 .def tBCD0 =r13 ;BCD value digits 1 and 0

XMODEM REC .def tBCD1 =r14 ;BCD value digits 3 and 2
.def tBCD2 =r15 ;BCD value digit 4
UART 304 .def fbinL =r16 ;binary value Low byte
UART 305 .def fbinH =r17 ;binary value High byte
.def cnt16a =r18 ;loop counter
UART 128
.def tmp16a =r19 ;temporary value
UART BUFF
;***** Code
USB 232
AVR ISP bin2BCD16:
ISP 2313 ldi cnt16a,16 ;Init loop counter
clr tBCD2 ;clear result (3 bytes)
ISP 1200 clr tBCD1
AVR SPI clr tBCD0
clr ZH ;clear ZH (not needed for AT90Sxx0x)
I2C 300 bBCDx_1:lsl fbinL ;shift input value
I2C 302 rol fbinH ;through all bytes
rol tBCD0 ;
I2C TWI26
rol tBCD1
I2C/TWI 128 rol tBCD2
I2C/TWI AT8 dec cnt16a ;decrement loop counter
brne bBCDx_2 ;if counter not zero
DALLAS-1W ret ; return
DALLAS CRC
bBCDx_2:ldi r30,AtBCD2+1 ;Z points to result MSB + 1
ETHNET 8019 bBCDx_3:
TEA ld tmp16a,-Z ;get (Z) with pre-decrement
;----------------------------------------------------------------
ADC 128 ;For AT90Sxx0x, substitute the above line with:
ADC 10B ;
; dec ZL
ADC 400
; ld tmp16a,Z
ADC 401 ;
THERM 232 ;----------------------------------------------------------------
subi tmp16a,-$03 ;add 0x03
IRD 410 sbrc tmp16a,3 ;if bit 3 not clear
LCD HD44 st Z,tmp16a ; store back
ld tmp16a,Z ;get (Z)
LCD 2313 subi tmp16a,-$30 ;add 0x30
LCD44 2313 sbrc tmp16a,7 ;if bit 7 not clear
st Z,tmp16a ; store back
KBD 240 cpi ZL,AtBCD0 ;done all three?
MUX 242 brne bBCDx_3 ;loop again if not
rjmp bBCDx_1
KBD PS2
KBD PC/128
PS2 EMU
;***************************************************************************
BOOT MG8 ;*
BOOT DR8 ;* "bin2BCD8" - 8-bit Binary to BCD conversion
;*
ALM CLK ;* This subroutine converts an 8-bit number (fbin) to a 2-digit
CLOCK 8564 ;* BCD number (tBCDH:tBCDL).
;*
90 DAYS
;* Number of words :6 + return
DELAYS ;* Number of cycles :5/50 (Min/Max) + return
;* Low registers used :None
CALL ID
;* High registers used :2 (fbin/tBCDL,tBCDH)
DTMF 314 ;*
PWM 6CH ;* Included in the code are lines to add/replace for packed BCD output.
;*
PWM 10K ;***************************************************************************
ENCODE
;***** Subroutine Register Variables
STH-11
ATMEL CORP .def fbin =r16 ;8-bit binary value
.def tBCDL =r16 ;BCD result MSD
AVR
.def tBCDH =r17 ;BCD result LSD
BUTTERFLY
AVR BOOK ;***** Code

bin2bcd8:
clr tBCDH ;clear result MSD
bBCD8_1:subi fbin,10 ;input = input - 10
brcs bBCD8_2 ;abort if carry set
inc tBCDH ;inc MSD
;---------------------------------------------------------------------------
; ;Replace the above line with this one
; ;for packed BCD output
; subi tBCDH,-$10 ;tBCDH = tBCDH + 10
;---------------------------------------------------------------------------
rjmp bBCD8_1 ;loop again
bBCD8_2:subi fbin,-10 ;compensate extra subtraction
;---------------------------------------------------------------------------
; ;Add this line for packed BCD output
; add fbin,tBCDH
;---------------------------------------------------------------------------
ret

;***************************************************************************
;*
;* "BCD2bin16" - BCD to 16-Bit Binary Conversion
;*
;* This subroutine converts a 5-digit packed BCD number represented by
;* 3 bytes (fBCD2:fBCD1:fBCD0) to a 16-bit number (tbinH:tbinL).
;* MSD of the 5-digit number must be placed in the lowermost nibble of
fBCD2.
;*
;* Let "abcde" denote the 5-digit number. The conversion is done by
;* computing the formula: 10(10(10(10a+b)+c)+d)+e.
;* The subroutine "mul10a"/"mul10b" does the multiply-and-add operation
;* which is repeated four times during the computation.
;*
;* Number of words :30
;* Number of cycles :108
;* Low registers used :4 (copyL,copyH,mp10L/tbinL,mp10H/tbinH)
;* High registers used :4 (fBCD0,fBCD1,fBCD2,adder)
;*
;***************************************************************************

;***** "mul10a"/"mul10b" Subroutine Register Variables

.def copyL =r12 ;temporary register

.def copyH =r13 ;temporary register
.def mp10L =r14 ;Low byte of number to be multiplied by
10
.def mp10H =r15 ;High byte of number to be multiplied
by 10
.def adder =r19 ;value to add after multiplication

;***** Code

mul10a: ;***** multiplies "mp10H:mp10L" with 10 and adds "adder" high

nibble
swap adder
mul10b: ;***** multiplies "mp10H:mp10L" with 10 and adds "adder" low
nibble
mov copyL,mp10L ;make copy
mov copyH,mp10H
lsl mp10L ;multiply original by 2
rol mp10H
lsl copyL ;multiply copy by 2
rol copyH
lsl copyL ;multiply copy by 2 (4)
rol copyH
lsl copyL ;multiply copy by 2 (8)
rol copyH
add mp10L,copyL ;add copy to original
adc mp10H,copyH
andi adder,0x0f ;mask away upper nibble of adder
add mp10L,adder ;add lower nibble of adder
brcc m10_1 ;if carry not cleared
inc mp10H ; inc high byte
m10_1: ret

;***** Main Routine Register Variables

.def tbinL =r14 ;Low byte of binary result (same as

mp10L)
.def tbinH =r15 ;High byte of binary result (same as
mp10H)
.def fBCD0 =r16 ;BCD value digits 1 and 0
.def fBCD1 =r17 ;BCD value digits 2 and 3
.def fBCD2 =r18 ;BCD value digit 5

;***** Code

BCD2bin16:
andi fBCD2,0x0f ;mask away upper nibble of fBCD2
clr mp10H
mov mp10L,fBCD2 ;mp10H:mp10L = a
mov adder,fBCD1
rcall mul10a ;mp10H:mp10L = 10a+b
mov adder,fBCD1
rcall mul10b ;mp10H:mp10L = 10(10a+b)+c
mov adder,fBCD0
rcall mul10a ;mp10H:mp10L = 10(10(10a+b)+c)+d
mov adder,fBCD0
rcall mul10b ;mp10H:mp10L = 10(10(10(10a+b)+c)+d)+e
ret

;***************************************************************************
;*
;* "BCD2bin8" - BCD to 8-bit binary conversion
;*
;* This subroutine converts a 2-digit BCD number (fBCDH:fBCDL) to an
;* 8-bit number (tbin).
;*
;* Number of words :4 + return
;* Number of cycles :3/48 (Min/Max) + return
;* Low registers used :None
;* High registers used :2 (tbin/fBCDL,fBCDH)
;*
;* Modifications to make the routine accept a packed BCD number is indicated
;* as comments in the code. If the modifications are used, fBCDH shall be
;* loaded with the BCD number to convert prior to calling the routine.
;*
;***************************************************************************

;***** Subroutine Register Variables

.def tbin =r16 ;binary result

.def fBCDL =r16 ;lower digit of BCD input
.def fBCDH =r17 ;higher digit of BCD input

;***** Code

BCD2bin8:
;--------------------------------------------------------------------------
;| ;For packed BCD input, add these two lines
;| mov tbin,fBCDH ;copy input to result
;| andi tbin,$0f ;clear higher nibble of result
;--------------------------------------------------------------------------

BCDb8_0:subi fBCDH,1 ;fBCDH = fBCDH - 1

brcs BCDb8_1 ;if carry not set
;--------------------------------------------------------------------------
;| ;For packed BCD input, replace the above
;| ;two lines with these.
;| subi fBCDH,$10 ;MSD = MSD - 1
;| brmi BCDb8_1 ;if Zero flag not set
;--------------------------------------------------------------------------
subi tbin,-10 ; result = result + 10
rjmp BCDb8_0 ; loop again
BCDb8_1:ret ;else return

;***************************************************************************
;*
;* "BCDadd" - 2-digit packed BCD addition
;*
;* This subroutine adds the two unsigned 2-digit BCD numbers
;* "BCD1" and "BCD2". The result is returned in "BCD1", and the overflow
;* carry in "BCD2".
;*
;* Number of words :19
;* Number of cycles :17/20 (Min/Max)
;* Low registers used :None
;* High registers used :3 (BCD1,BCD2,tmpadd)
;*
;***************************************************************************

;***** Subroutine Register Variables

.def BCD1 =r16 ;BCD input value #1

.def BCD2 =r17 ;BCD input value #2
.def tmpadd =r18 ;temporary register

;***** Code

BCDadd:
ldi tmpadd,6 ;value to be added later
add BCD1,BCD2 ;add the numbers binary
clr BCD2 ;clear BCD carry
brcc add_0 ;if carry not clear
ldi BCD2,1 ; set BCD carry
add_0: brhs add_1 ;if half carry not set
add BCD1,tmpadd ; add 6 to LSD
brhs add_2 ; if half carry not set (LSD <= 9)
subi BCD1,6 ; restore value
rjmp add_2 ;else
add_1: add BCD1,tmpadd ; add 6 to LSD
add_2: swap tmpadd
add BCD1,tmpadd ;add 6 to MSD
brcs add_4 ;if carry not set (MSD <= 9)
sbrs BCD2,0 ; if previous carry not set
subi BCD1,$60 ; restore value
add_3: ret ;else
add_4: ldi BCD2,1 ; set BCD carry
ret

;***************************************************************************
;*
;* "BCDsub" - 2-digit packed BCD subtraction
;*
;* This subroutine subtracts the two unsigned 2-digit BCD numbers
;* "BCDa" and "BCDb" (BCDa - BCDb). The result is returned in "BCDa", and
;* the underflow carry in "BCDb".
;*
;* Number of words :13
;* Number of cycles :12/17 (Min/Max)
;* Low registers used :None
;* High registers used :2 (BCDa,BCDb)
;*
;***************************************************************************

;***** Subroutine Register Variables

.def BCDa =r16 ;BCD input value #1

.def BCDb =r17 ;BCD input value #2

;***** Code

BCDsub:
sub BCDa,BCDb ;subtract the numbers binary
clr BCDb
brcc sub_0 ;if carry not clear
ldi BCDb,1 ; store carry in BCDB1, bit 0
sub_0: brhc sub_1 ;if half carry not clear
subi BCDa,$06 ; LSD = LSD - 6
sub_1: sbrs BCDb,0 ;if previous carry not set
ret ; return
subi BCDa,$60 ;subtract 6 from MSD
ldi BCDb,1 ;set underflow carry
brcc sub_2 ;if carry not clear
ldi BCDb,1 ; clear underflow carry
sub_2: ret

;
****************************************************************************
;*
;* Test Program
;*
;* This program calls all the subroutines as an example of usage and to
;* verify correct operation.
;*
;
****************************************************************************

;***** Main Program Register variables

.def temp =r16 ;temporary storage variable

;***** Code

RESET:
ldi temp,low(RAMEND)
out SPL,temp
ldi temp,high(RAMEND)
out SPH,temp ;init Stack Pointer (remove for AT90Sxx0x)

;***** Convert 54,321 to 2.5-byte packed BCD format

ldi fbinL,low(54321)
ldi fbinH,high(54321)
rcall bin2BCD16 ;result: tBCD2:tBCD1:tBCD0 = $054321

;***** Convert 55 to 2-byte BCD

ldi fbin,55
rcall bin2BCD8 ;result: tBCDH:tBCDL = 0505

;***** Convert $065535 to a 16-bit binary number

ldi fBCD2,$06
ldi fBCD1,$55
ldi fBCD0,$35
rcall BCD2bin16 ;result: tbinH:tbinL = $ffff (65,535)

;***** Convert $0403 (43) to an 8-bit binary number

ldi fBCDL,3
ldi fBCDH,4
rcall BCD2bin8 ;result: tbin = $2b (43)

;***** Add BCD numbers 51 and 79

ldi BCD1,$51
ldi BCD2,$79
rcall BCDadd ;result: BCD2:BCD1=$0130

;***** Subtract BCD numbers 72 - 28

ldi BCDa,$72
ldi BCDb,$28
rcall BCDsub ;result: BCDb=$00 (positive result), BCDa=44

;***** Subtract BCD numbers 0 - 90

ldi BCDa,$00
ldi BCDb,$90
rcall BCDsub ;result: BCDb=$01 (negative result), BCDa=10

forever:rjmp forever

Programming the AVR Microcontrollers in Machine Language

AVR
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr)
Jump to: navigation, search The AVRs are a family of RISC
microcontrollers from Atmel. Their internal architecture was conceived by
two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute
of Technology (NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the Atmel AVR32
line of microcontrollers. These are 32-bit RISC devices featuring SIMD and
DSP instructions, along with many additional features for audio and video
processing, intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR
Microcontrollers. The acronym AVR has been reported to stand for
Advanced Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned about it.
Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory
and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2
Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel
Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other AVR
Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with programs and
data stored and addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external memory
(though still available on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory. Each instruction
for the AVR line is either 16 or 32 bits in length. The Flash memory is
addressed using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the ATmega64x
line has 64Kbytes of Flash. Almost all AVR devices are self-programmable.
[edit] Data Memory and Registers The data address space consists of the
register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The working registers
are mapped in as the first thirty-two memory spaces (000016-001F16)
followed by the 64 I/O registers (002016-005F16). The actual usable RAM
starts after both these sections (address 006016). (Note that the I/O register
space may be larger on some more extensive devices, in which case
memory mapped I/O registers will occupy a portion of the SRAM.) Even
though there are separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed and
manipulated as if they were in SRAM. [edit] EEPROM Almost all devices
have on-die EEPROM. This is most often used for long-term parameter
storage to be retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline design. The
next machine instruction is fetched as the current one is executing. Most
instructions take just one or two clock cycles, making AVRs relatively fast
among the eight-bit microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The AVR
instruction set is more orthogonal than most eight-bit microcontrollers,
however, it is not completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other. Register
locations R0 to R15 have different addressing capabilities than register
locations R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not,
even though they are complementary instructions. CLR set all bits to zero
and SER sets them to one. (Note though, that neither CLR nor SER are
native instructions. Instead CLR is syntactic sugar for [produces the same
machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF.
Math operations such as EOR modify flags while moves/loads/stores/
branches such as LDI do not.) [edit] Speed The AVR line can normally
support clock speeds from 0-16MHz, with some devices reaching 20MHz.
Lower powered operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external clocks or
resonator circuitry. Because many operations on the AVR are single cycle,
the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a
large following due to the free and inexpensive development tools
available, including reasonably priced development boards and free
development software. The AVRs are marketed under various names that
share the same basic core but with different peripheral and memory
combinations. Some models (notably, the ATmega range) have additional
instructions to make arithmetic faster. Compatibility amongst chips is fairly
good. See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC Core Running
Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with
Internal, Configurable Pull-up Resistors Multiple Internal Oscillators
Internal, Self-Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage methods
Optional Boot Code Section with Independent Lock Bits for Protection
Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit
Timers PWM Channels & dead time generator Lighting (PWM Specific)
Controller models Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used
with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed hardware &
Hub controller with embedded AVR. Also freely available low-speed (HID)
software emulation Ethernet Controller Support Universal Serial Interface
(USI) for Two or Three-Wire Synchronous Data Transfer Analog
Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex
of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-
voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep
Modes picoPower Devices Atmel AVR assembler programming language
Atmel AVR machine programming language Atmel AVR From Wikipedia,
the free encyclopedia (Redirected from Avr) Jump to: navigation, search
The AVRs are a family of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen and Vegard
Wollan, at the Norwegian Institute of Technology (NTH] and further
developed at Atmel Norway, a subsidiary founded by the two architects.
Atmel recently released the Atmel AVR32 line of microcontrollers. These
are 32-bit RISC devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing, intended to
compete with ARM based processors. Note that the use of "AVR" in this
article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced Virtual RISC. It's
also rumoured to stand for the company's founders: Alf and Vegard, who
are evasive when questioned about it. Contents [hide] 1 Device Overview
1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See
also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion
Groups 6.3 Machine Language Development 6.4 C Language Development
6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other
AVR Links [edit] Device Overview The AVR is a Harvard architecture
machine with programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die, removing the need
for external memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-permanent Flash
memory. Each instruction for the AVR line is either 16 or 32 bits in length.
The Flash memory is addressed using 16 bit word sizes. The size of the
program memory is indicated in the naming of the device itself. For
instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and SRAM. The
AVRs have thirty-two single-byte registers and are classified as 8-bit RISC
devices. The working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O registers (002016-
005F16). The actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on some more
extensive devices, in which case memory mapped I/O registers will occupy
a portion of the SRAM.) Even though there are separate addressing
schemes and optimized opcodes for register file and I/O register access, all
can still be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is most often used
for long-term parameter storage to be retrieved even after cycling the
power of the device. [edit] Program Execution Atmel's AVRs have a single
level pipeline design. The next machine instruction is fetched as the
current one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit microcontrollers.
The AVR family of processors were designed for the efficient execution of
compiled C code. The AVR instruction set is more orthogonal than most
eight-bit microcontrollers, however, it is not completely regular: Pointer
registers X, Y, and Z have addressing capabilities that are different from
each other. Register locations R0 to R15 have different addressing
capabilities than register locations R16 to R31. I/O ports 0 to 31 have
different addressing capabilities than I/O ports 32 to 63. CLR affects flags,
while SER does not, even though they are complementary instructions.
CLR set all bits to zero and SER sets them to one. (Note though, that
neither CLR nor SER are native instructions. Instead CLR is syntactic
sugar for [produces the same machine code as] EOR R,R while SER is
syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit] Speed The
AVR line can normally support clock speeds from 0-16MHz, with some
devices reaching 20MHz. Lower powered operation usually requires a
reduced clock speed. All AVRs feature an on-chip oscillator, removing the
need for external clocks or resonator circuitry. Because many operations
on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz.
[edit] Development AVRs have a large following due to the free and
inexpensive development tools available, including reasonably priced
development boards and free development software. The AVRs are
marketed under various names that share the same basic core but with
different peripheral and memory combinations. Some models (notably, the
ATmega range) have additional instructions to make arithmetic faster.
Compatibility amongst chips is fairly good. See external links for sites
relating to AVR development. [edit] Features Current AVRs offer a wide
range of features: RISC Core Running Many Single Cycle Instructions
Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-Programmable
Instruction Flash Memory up to 256K In-System Programmable using ICSP,
JTAG, or High Voltage methods Optional Boot Code Section with
Independent Lock Bits for Protection Internal Data EEPROM up to 4KB
Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time
generator Lighting (PWM Specific) Controller models Dedicated I²C
Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial
Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB Controller Support
Proper High-speed hardware & Hub controller with embedded AVR. Also
freely available low-speed (HID) software emulation Ethernet Controller
Support Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD Controller Support
10-Bit A/D Converters, with multiplex of up to 16 channels Brownout
Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to
1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine programming
language Atmel AVR From Wikipedia, the free encyclopedia (Redirected
from Avr) Jump to: navigation, search The AVRs are a family of RISC
microcontrollers from Atmel. Their internal architecture was conceived by
two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute
of Technology (NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the Atmel AVR32
line of microcontrollers. These are 32-bit RISC devices featuring SIMD and
DSP instructions, along with many additional features for audio and video
processing, intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR
Microcontrollers. The acronym AVR has been reported to stand for
Advanced Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned about it.
Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory
and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2
Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel
Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other AVR
Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with programs and
data stored and addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external memory
(though still available on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory. Each instruction
for the AVR line is either 16 or 32 bits in length. The Flash memory is
addressed using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the ATmega64x
line has 64Kbytes of Flash. Almost all AVR devices are self-programmable.
[edit] Data Memory and Registers The data address space consists of the
register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The working registers
are mapped in as the first thirty-two memory spaces (000016-001F16)
followed by the 64 I/O registers (002016-005F16). The actual usable RAM
starts after both these sections (address 006016). (Note that the I/O register
space may be larger on some more extensive devices, in which case
memory mapped I/O registers will occupy a portion of the SRAM.) Even
though there are separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed and
manipulated as if they were in SRAM. [edit] EEPROM Almost all devices
have on-die EEPROM. This is most often used for long-term parameter
storage to be retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline design. The
next machine instruction is fetched as the current one is executing. Most
instructions take just one or two clock cycles, making AVRs relatively fast
among the eight-bit microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The AVR
instruction set is more orthogonal than most eight-bit microcontrollers,
however, it is not completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other. Register
locations R0 to R15 have different addressing capabilities than register
locations R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not,
even though they are complementary instructions. CLR set all bits to zero
and SER sets them to one. (Note though, that neither CLR nor SER are
native instructions. Instead CLR is syntactic sugar for [produces the same
machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF.
Math operations such as EOR modify flags while moves/loads/stores/
branches such as LDI do not.) [edit] Speed The AVR line can normally
support clock speeds from 0-16MHz, with some devices reaching 20MHz.
Lower powered operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external clocks or
resonator circuitry. Because many operations on the AVR are single cycle,
the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a
large following due to the free and inexpensive development tools
available, including reasonably priced development boards and free
development software. The AVRs are marketed under various names that
http://avr-asm.tripod.com/avr204.html (1 of 2)1/20/2009 8:42:33 PM
16 BIT MATH (AVR 202)

share the same basic core but with different peripheral and memory
combinations. Some models (notably, the ATmega range) have additional
instructions to make arithmetic faster. Compatibility amongst chips is fairly
good. See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC Core Running
Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with
Internal, Configurable Pull-up Resistors Multiple Internal Oscillators
Internal, Self-Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage methods
Optional Boot Code Section with Independent Lock Bits for Protection
Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit
Timers PWM Channels & dead time generator Lighting (PWM Specific)
Controller models Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used
with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed hardware &
Hub controller with embedded AVR. Also freely available low-speed (HID)
software emulation Ethernet Controller Support Universal Serial Interface
(USI) for Two or Three-Wire Synchronous Data Transfer Analog
Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex
of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-
voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep
Modes picoPower Devices Atmel AVR assembler programming language
Atmel AVR machine programming language

http://avr-asm.tripod.com/avr204.html (2 of 2)1/20/2009 8:42:33 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

BCD MATH (AVR 204)

HOME
RETRO_DAN
;**** A P P L I C A T I O N N O T E A V R 2 0 4 ************************
ASM FORUM ;*
ASM MATH ;* Title: BCD Arithmetics
;* Version: 1.1
TUTORIAL #1
;* Last updated: 97.07.04
TUTORIAL #2 ;* Target: AT90Sxxxx (All AVR Devices)
TUTORIAL #3 ;*
;* Support E-mail: avr@atmel.com
MATH 200 ;*
MATH 200b ;* DESCRIPTION
;* This Application Note lists subroutines for the following Binary Coded
MATH 201 ;* Decimal arithmetic applications:
MATH 202 ;*
;* Binary 16 to BCD Conversion (special considerations for AT90Sxx0x)
MATH 32X
;* Binary 8 to BCD Conversion
MATH YX ;* BCD to Binary 16 Conversion
;* BCD to Binary 8 Conversion
DIV16 XX
;* 2-Digit BCD Addition
DIV 24 24 ;* 2-Digit BCD Subtraction
DIV 3216 ;*
;***************************************************************************
FLOAT 128
SQRT16 .include "8515def.inc"

MATH 202 rjmp RESET ;reset handle

MATH 202
;***************************************************************************
DEC ASCII
;*
INT ASCII ;* "bin2BCD16" - 16-bit Binary to BCD conversion
;*
HX2ASC
;* This subroutine converts a 16-bit number (fbinH:fbinL) to a 5-digit
AVG8 222 ;* packed BCD number represented by 3 bytes (tBCD2:tBCD1:tBCD0).
FFT7 ;* MSD of the 5-digit number is placed in the lowermost nibble of tBCD2.
;*
COPY 102 ;* Number of words :25
LPM 108 ;* Number of cycles :751/768 (Min/Max)
;* Low registers used :3 (tBCD0,tBCD1,tBCD2)
EPROM 100 ;* High registers used :4(fbinL,fbinH,cnt16a,tmp16a)
SER EPROM ;* Pointers used :Z
;*
DFLASH AT45
;***************************************************************************
FLASH CARD
;***** Subroutine Register Variables
VFX SMIL
VFX MEM .equ AtBCD0 =13 ;address of tBCD0
SORT 220 .equ AtBCD2 =15 ;address of tBCD1

CRC 236 .def tBCD0 =r13 ;BCD value digits 1 and 0

XMODEM REC .def tBCD1 =r14 ;BCD value digits 3 and 2
.def tBCD2 =r15 ;BCD value digit 4
UART 304 .def fbinL =r16 ;binary value Low byte
UART 305 .def fbinH =r17 ;binary value High byte
.def cnt16a =r18 ;loop counter
UART 128
.def tmp16a =r19 ;temporary value
UART BUFF
;***** Code
USB 232
AVR ISP bin2BCD16:
ISP 2313 ldi cnt16a,16 ;Init loop counter
clr tBCD2 ;clear result (3 bytes)
ISP 1200 clr tBCD1
AVR SPI clr tBCD0
clr ZH ;clear ZH (not needed for AT90Sxx0x)
I2C 300 bBCDx_1:lsl fbinL ;shift input value
I2C 302 rol fbinH ;through all bytes
rol tBCD0 ;
I2C TWI26
rol tBCD1
I2C/TWI 128 rol tBCD2
I2C/TWI AT8 dec cnt16a ;decrement loop counter
brne bBCDx_2 ;if counter not zero
DALLAS-1W ret ; return
DALLAS CRC
bBCDx_2:ldi r30,AtBCD2+1 ;Z points to result MSB + 1
ETHNET 8019 bBCDx_3:
TEA ld tmp16a,-Z ;get (Z) with pre-decrement
;----------------------------------------------------------------
ADC 128 ;For AT90Sxx0x, substitute the above line with:
ADC 10B ;
; dec ZL
ADC 400
; ld tmp16a,Z
ADC 401 ;
THERM 232 ;----------------------------------------------------------------
subi tmp16a,-$03 ;add 0x03
IRD 410 sbrc tmp16a,3 ;if bit 3 not clear
LCD HD44 st Z,tmp16a ; store back
ld tmp16a,Z ;get (Z)
LCD 2313 subi tmp16a,-$30 ;add 0x30
LCD44 2313 sbrc tmp16a,7 ;if bit 7 not clear
st Z,tmp16a ; store back
KBD 240 cpi ZL,AtBCD0 ;done all three?
MUX 242 brne bBCDx_3 ;loop again if not
rjmp bBCDx_1
KBD PS2
KBD PC/128
PS2 EMU
;***************************************************************************
BOOT MG8 ;*
BOOT DR8 ;* "bin2BCD8" - 8-bit Binary to BCD conversion
;*
ALM CLK ;* This subroutine converts an 8-bit number (fbin) to a 2-digit
CLOCK 8564 ;* BCD number (tBCDH:tBCDL).
;*
90 DAYS
;* Number of words :6 + return
DELAYS ;* Number of cycles :5/50 (Min/Max) + return
;* Low registers used :None
CALL ID
;* High registers used :2 (fbin/tBCDL,tBCDH)
DTMF 314 ;*
PWM 6CH ;* Included in the code are lines to add/replace for packed BCD output.
;*
PWM 10K ;***************************************************************************
ENCODE
;***** Subroutine Register Variables
STH-11
ATMEL CORP .def fbin =r16 ;8-bit binary value
.def tBCDL =r16 ;BCD result MSD
AVR
.def tBCDH =r17 ;BCD result LSD
BUTTERFLY
AVR BOOK ;***** Code

bin2bcd8:
clr tBCDH ;clear result MSD
bBCD8_1:subi fbin,10 ;input = input - 10
brcs bBCD8_2 ;abort if carry set
inc tBCDH ;inc MSD
;---------------------------------------------------------------------------
; ;Replace the above line with this one
; ;for packed BCD output
; subi tBCDH,-$10 ;tBCDH = tBCDH + 10
;---------------------------------------------------------------------------
rjmp bBCD8_1 ;loop again
bBCD8_2:subi fbin,-10 ;compensate extra subtraction
;---------------------------------------------------------------------------
; ;Add this line for packed BCD output
; add fbin,tBCDH
;---------------------------------------------------------------------------
ret

;***************************************************************************
;*
;* "BCD2bin16" - BCD to 16-Bit Binary Conversion
;*
;* This subroutine converts a 5-digit packed BCD number represented by
;* 3 bytes (fBCD2:fBCD1:fBCD0) to a 16-bit number (tbinH:tbinL).
;* MSD of the 5-digit number must be placed in the lowermost nibble of
fBCD2.
;*
;* Let "abcde" denote the 5-digit number. The conversion is done by
;* computing the formula: 10(10(10(10a+b)+c)+d)+e.
;* The subroutine "mul10a"/"mul10b" does the multiply-and-add operation
;* which is repeated four times during the computation.
;*
;* Number of words :30
;* Number of cycles :108
;* Low registers used :4 (copyL,copyH,mp10L/tbinL,mp10H/tbinH)
;* High registers used :4 (fBCD0,fBCD1,fBCD2,adder)
;*
;***************************************************************************

;***** "mul10a"/"mul10b" Subroutine Register Variables

.def copyL =r12 ;temporary register

.def copyH =r13 ;temporary register
.def mp10L =r14 ;Low byte of number to be multiplied by
10
.def mp10H =r15 ;High byte of number to be multiplied
by 10
.def adder =r19 ;value to add after multiplication

;***** Code

mul10a: ;***** multiplies "mp10H:mp10L" with 10 and adds "adder" high

nibble
swap adder
mul10b: ;***** multiplies "mp10H:mp10L" with 10 and adds "adder" low
nibble
mov copyL,mp10L ;make copy
mov copyH,mp10H
lsl mp10L ;multiply original by 2
rol mp10H
lsl copyL ;multiply copy by 2
rol copyH
lsl copyL ;multiply copy by 2 (4)
rol copyH
lsl copyL ;multiply copy by 2 (8)
rol copyH
add mp10L,copyL ;add copy to original
adc mp10H,copyH
andi adder,0x0f ;mask away upper nibble of adder
add mp10L,adder ;add lower nibble of adder
brcc m10_1 ;if carry not cleared
inc mp10H ; inc high byte
m10_1: ret

;***** Main Routine Register Variables

.def tbinL =r14 ;Low byte of binary result (same as

mp10L)
.def tbinH =r15 ;High byte of binary result (same as
mp10H)
.def fBCD0 =r16 ;BCD value digits 1 and 0
.def fBCD1 =r17 ;BCD value digits 2 and 3
.def fBCD2 =r18 ;BCD value digit 5

;***** Code

BCD2bin16:
andi fBCD2,0x0f ;mask away upper nibble of fBCD2
clr mp10H
mov mp10L,fBCD2 ;mp10H:mp10L = a
mov adder,fBCD1
rcall mul10a ;mp10H:mp10L = 10a+b
mov adder,fBCD1
rcall mul10b ;mp10H:mp10L = 10(10a+b)+c
mov adder,fBCD0
rcall mul10a ;mp10H:mp10L = 10(10(10a+b)+c)+d
mov adder,fBCD0
rcall mul10b ;mp10H:mp10L = 10(10(10(10a+b)+c)+d)+e
ret

;***************************************************************************
;*
;* "BCD2bin8" - BCD to 8-bit binary conversion
;*
;* This subroutine converts a 2-digit BCD number (fBCDH:fBCDL) to an
;* 8-bit number (tbin).
;*
;* Number of words :4 + return
;* Number of cycles :3/48 (Min/Max) + return
;* Low registers used :None
;* High registers used :2 (tbin/fBCDL,fBCDH)
;*
;* Modifications to make the routine accept a packed BCD number is indicated
;* as comments in the code. If the modifications are used, fBCDH shall be
;* loaded with the BCD number to convert prior to calling the routine.
;*
;***************************************************************************

;***** Subroutine Register Variables

.def tbin =r16 ;binary result

.def fBCDL =r16 ;lower digit of BCD input
.def fBCDH =r17 ;higher digit of BCD input

;***** Code

BCD2bin8:
;--------------------------------------------------------------------------
;| ;For packed BCD input, add these two lines
;| mov tbin,fBCDH ;copy input to result
;| andi tbin,$0f ;clear higher nibble of result
;--------------------------------------------------------------------------

BCDb8_0:subi fBCDH,1 ;fBCDH = fBCDH - 1

brcs BCDb8_1 ;if carry not set
;--------------------------------------------------------------------------
;| ;For packed BCD input, replace the above
;| ;two lines with these.
;| subi fBCDH,$10 ;MSD = MSD - 1
;| brmi BCDb8_1 ;if Zero flag not set
;--------------------------------------------------------------------------
subi tbin,-10 ; result = result + 10
rjmp BCDb8_0 ; loop again
BCDb8_1:ret ;else return

;***************************************************************************
;*
;* "BCDadd" - 2-digit packed BCD addition
;*
;* This subroutine adds the two unsigned 2-digit BCD numbers
;* "BCD1" and "BCD2". The result is returned in "BCD1", and the overflow
;* carry in "BCD2".
;*
;* Number of words :19
;* Number of cycles :17/20 (Min/Max)
;* Low registers used :None
;* High registers used :3 (BCD1,BCD2,tmpadd)
;*
;***************************************************************************

;***** Subroutine Register Variables

.def BCD1 =r16 ;BCD input value #1

.def BCD2 =r17 ;BCD input value #2
.def tmpadd =r18 ;temporary register

;***** Code

BCDadd:
ldi tmpadd,6 ;value to be added later
add BCD1,BCD2 ;add the numbers binary
clr BCD2 ;clear BCD carry
brcc add_0 ;if carry not clear
ldi BCD2,1 ; set BCD carry
add_0: brhs add_1 ;if half carry not set
add BCD1,tmpadd ; add 6 to LSD
brhs add_2 ; if half carry not set (LSD <= 9)
subi BCD1,6 ; restore value
rjmp add_2 ;else
add_1: add BCD1,tmpadd ; add 6 to LSD
add_2: swap tmpadd
add BCD1,tmpadd ;add 6 to MSD
brcs add_4 ;if carry not set (MSD <= 9)
sbrs BCD2,0 ; if previous carry not set
subi BCD1,$60 ; restore value
add_3: ret ;else
add_4: ldi BCD2,1 ; set BCD carry
ret

;***************************************************************************
;*
;* "BCDsub" - 2-digit packed BCD subtraction
;*
;* This subroutine subtracts the two unsigned 2-digit BCD numbers
;* "BCDa" and "BCDb" (BCDa - BCDb). The result is returned in "BCDa", and
;* the underflow carry in "BCDb".
;*
;* Number of words :13
;* Number of cycles :12/17 (Min/Max)
;* Low registers used :None
;* High registers used :2 (BCDa,BCDb)
;*
;***************************************************************************

;***** Subroutine Register Variables

.def BCDa =r16 ;BCD input value #1

.def BCDb =r17 ;BCD input value #2

;***** Code

BCDsub:
sub BCDa,BCDb ;subtract the numbers binary
clr BCDb
brcc sub_0 ;if carry not clear
ldi BCDb,1 ; store carry in BCDB1, bit 0
sub_0: brhc sub_1 ;if half carry not clear
subi BCDa,$06 ; LSD = LSD - 6
sub_1: sbrs BCDb,0 ;if previous carry not set
ret ; return
subi BCDa,$60 ;subtract 6 from MSD
ldi BCDb,1 ;set underflow carry
brcc sub_2 ;if carry not clear
ldi BCDb,1 ; clear underflow carry
sub_2: ret

;
****************************************************************************
;*
;* Test Program
;*
;* This program calls all the subroutines as an example of usage and to
;* verify correct operation.
;*
;
****************************************************************************

;***** Main Program Register variables

.def temp =r16 ;temporary storage variable

;***** Code

RESET:
ldi temp,low(RAMEND)
out SPL,temp
ldi temp,high(RAMEND)
out SPH,temp ;init Stack Pointer (remove for AT90Sxx0x)

;***** Convert 54,321 to 2.5-byte packed BCD format

ldi fbinL,low(54321)
ldi fbinH,high(54321)
rcall bin2BCD16 ;result: tBCD2:tBCD1:tBCD0 = $054321

;***** Convert 55 to 2-byte BCD

ldi fbin,55
rcall bin2BCD8 ;result: tBCDH:tBCDL = 0505

;***** Convert $065535 to a 16-bit binary number

ldi fBCD2,$06
ldi fBCD1,$55
ldi fBCD0,$35
rcall BCD2bin16 ;result: tbinH:tbinL = $ffff (65,535)

;***** Convert $0403 (43) to an 8-bit binary number

ldi fBCDL,3
ldi fBCDH,4
rcall BCD2bin8 ;result: tbin = $2b (43)

;***** Add BCD numbers 51 and 79

ldi BCD1,$51
ldi BCD2,$79
rcall BCDadd ;result: BCD2:BCD1=$0130

;***** Subtract BCD numbers 72 - 28

ldi BCDa,$72
ldi BCDb,$28
rcall BCDsub ;result: BCDb=$00 (positive result), BCDa=44

;***** Subtract BCD numbers 0 - 90

ldi BCDa,$00
ldi BCDb,$90
rcall BCDsub ;result: BCDb=$01 (negative result), BCDa=10

forever:rjmp forever

Programming the AVR Microcontrollers in Machine Language

AVR
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© WebRing Inc. Search

Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr)
Jump to: navigation, search The AVRs are a family of RISC
microcontrollers from Atmel. Their internal architecture was conceived by
two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute
of Technology (NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the Atmel AVR32
line of microcontrollers. These are 32-bit RISC devices featuring SIMD and
DSP instructions, along with many additional features for audio and video
processing, intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR
Microcontrollers. The acronym AVR has been reported to stand for
Advanced Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned about it.
Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory
and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2
Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel
Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other AVR
Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with programs and
data stored and addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external memory
(though still available on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory. Each instruction
for the AVR line is either 16 or 32 bits in length. The Flash memory is
addressed using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the ATmega64x
line has 64Kbytes of Flash. Almost all AVR devices are self-programmable.
[edit] Data Memory and Registers The data address space consists of the
register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The working registers
are mapped in as the first thirty-two memory spaces (000016-001F16)
followed by the 64 I/O registers (002016-005F16). The actual usable RAM
starts after both these sections (address 006016). (Note that the I/O register
space may be larger on some more extensive devices, in which case
memory mapped I/O registers will occupy a portion of the SRAM.) Even
though there are separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed and
manipulated as if they were in SRAM. [edit] EEPROM Almost all devices
have on-die EEPROM. This is most often used for long-term parameter
storage to be retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline design. The
next machine instruction is fetched as the current one is executing. Most
instructions take just one or two clock cycles, making AVRs relatively fast
among the eight-bit microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The AVR
instruction set is more orthogonal than most eight-bit microcontrollers,
however, it is not completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other. Register
locations R0 to R15 have different addressing capabilities than register
locations R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not,
even though they are complementary instructions. CLR set all bits to zero
and SER sets them to one. (Note though, that neither CLR nor SER are
native instructions. Instead CLR is syntactic sugar for [produces the same
machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF.
Math operations such as EOR modify flags while moves/loads/stores/
branches such as LDI do not.) [edit] Speed The AVR line can normally
support clock speeds from 0-16MHz, with some devices reaching 20MHz.
Lower powered operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external clocks or
resonator circuitry. Because many operations on the AVR are single cycle,
the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a
large following due to the free and inexpensive development tools
available, including reasonably priced development boards and free
development software. The AVRs are marketed under various names that
share the same basic core but with different peripheral and memory
combinations. Some models (notably, the ATmega range) have additional
instructions to make arithmetic faster. Compatibility amongst chips is fairly
good. See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC Core Running
Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with
Internal, Configurable Pull-up Resistors Multiple Internal Oscillators
Internal, Self-Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage methods
Optional Boot Code Section with Independent Lock Bits for Protection
Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit
Timers PWM Channels & dead time generator Lighting (PWM Specific)
Controller models Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used
with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed hardware &
Hub controller with embedded AVR. Also freely available low-speed (HID)
software emulation Ethernet Controller Support Universal Serial Interface
(USI) for Two or Three-Wire Synchronous Data Transfer Analog
Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex
of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-
voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep
Modes picoPower Devices Atmel AVR assembler programming language
Atmel AVR machine programming language Atmel AVR From Wikipedia,
the free encyclopedia (Redirected from Avr) Jump to: navigation, search
The AVRs are a family of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen and Vegard
Wollan, at the Norwegian Institute of Technology (NTH] and further
developed at Atmel Norway, a subsidiary founded by the two architects.
Atmel recently released the Atmel AVR32 line of microcontrollers. These
are 32-bit RISC devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing, intended to
compete with ARM based processors. Note that the use of "AVR" in this
article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced Virtual RISC. It's
also rumoured to stand for the company's founders: Alf and Vegard, who
are evasive when questioned about it. Contents [hide] 1 Device Overview
1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See
also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion
Groups 6.3 Machine Language Development 6.4 C Language Development
6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other
AVR Links [edit] Device Overview The AVR is a Harvard architecture
machine with programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die, removing the need
for external memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-permanent Flash
memory. Each instruction for the AVR line is either 16 or 32 bits in length.
The Flash memory is addressed using 16 bit word sizes. The size of the
program memory is indicated in the naming of the device itself. For
instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and SRAM. The
AVRs have thirty-two single-byte registers and are classified as 8-bit RISC
devices. The working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O registers (002016-
005F16). The actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on some more
extensive devices, in which case memory mapped I/O registers will occupy
a portion of the SRAM.) Even though there are separate addressing
schemes and optimized opcodes for register file and I/O register access, all
can still be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is most often used
for long-term parameter storage to be retrieved even after cycling the
power of the device. [edit] Program Execution Atmel's AVRs have a single
level pipeline design. The next machine instruction is fetched as the
current one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit microcontrollers.
The AVR family of processors were designed for the efficient execution of
compiled C code. The AVR instruction set is more orthogonal than most
eight-bit microcontrollers, however, it is not completely regular: Pointer
registers X, Y, and Z have addressing capabilities that are different from
each other. Register locations R0 to R15 have different addressing
capabilities than register locations R16 to R31. I/O ports 0 to 31 have
different addressing capabilities than I/O ports 32 to 63. CLR affects flags,
while SER does not, even though they are complementary instructions.
CLR set all bits to zero and SER sets them to one. (Note though, that
neither CLR nor SER are native instructions. Instead CLR is syntactic
sugar for [produces the same machine code as] EOR R,R while SER is
syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit] Speed The
AVR line can normally support clock speeds from 0-16MHz, with some
devices reaching 20MHz. Lower powered operation usually requires a
reduced clock speed. All AVRs feature an on-chip oscillator, removing the
need for external clocks or resonator circuitry. Because many operations
on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz.
[edit] Development AVRs have a large following due to the free and
inexpensive development tools available, including reasonably priced
development boards and free development software. The AVRs are
marketed under various names that share the same basic core but with
different peripheral and memory combinations. Some models (notably, the
ATmega range) have additional instructions to make arithmetic faster.
Compatibility amongst chips is fairly good. See external links for sites
relating to AVR development. [edit] Features Current AVRs offer a wide
range of features: RISC Core Running Many Single Cycle Instructions
Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-Programmable
Instruction Flash Memory up to 256K In-System Programmable using ICSP,
JTAG, or High Voltage methods Optional Boot Code Section with
Independent Lock Bits for Protection Internal Data EEPROM up to 4KB
Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time
generator Lighting (PWM Specific) Controller models Dedicated I²C
Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial
Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB Controller Support
Proper High-speed hardware & Hub controller with embedded AVR. Also
freely available low-speed (HID) software emulation Ethernet Controller
Support Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD Controller Support
10-Bit A/D Converters, with multiplex of up to 16 channels Brownout
Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to
1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine programming
language Atmel AVR From Wikipedia, the free encyclopedia (Redirected
from Avr) Jump to: navigation, search The AVRs are a family of RISC
microcontrollers from Atmel. Their internal architecture was conceived by
two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute
of Technology (NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the Atmel AVR32
line of microcontrollers. These are 32-bit RISC devices featuring SIMD and
DSP instructions, along with many additional features for audio and video
processing, intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR
Microcontrollers. The acronym AVR has been reported to stand for
Advanced Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned about it.
Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory
and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2
Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel
Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other AVR
Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with programs and
data stored and addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external memory
(though still available on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory. Each instruction
for the AVR line is either 16 or 32 bits in length. The Flash memory is
addressed using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the ATmega64x
line has 64Kbytes of Flash. Almost all AVR devices are self-programmable.
[edit] Data Memory and Registers The data address space consists of the
register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The working registers
are mapped in as the first thirty-two memory spaces (000016-001F16)
followed by the 64 I/O registers (002016-005F16). The actual usable RAM
starts after both these sections (address 006016). (Note that the I/O register
space may be larger on some more extensive devices, in which case
memory mapped I/O registers will occupy a portion of the SRAM.) Even
though there are separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed and
manipulated as if they were in SRAM. [edit] EEPROM Almost all devices
have on-die EEPROM. This is most often used for long-term parameter
storage to be retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline design. The
next machine instruction is fetched as the current one is executing. Most
instructions take just one or two clock cycles, making AVRs relatively fast
among the eight-bit microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The AVR
instruction set is more orthogonal than most eight-bit microcontrollers,
however, it is not completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other. Register
locations R0 to R15 have different addressing capabilities than register
locations R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not,
even though they are complementary instructions. CLR set all bits to zero
and SER sets them to one. (Note though, that neither CLR nor SER are
native instructions. Instead CLR is syntactic sugar for [produces the same
machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF.
Math operations such as EOR modify flags while moves/loads/stores/
branches such as LDI do not.) [edit] Speed The AVR line can normally
support clock speeds from 0-16MHz, with some devices reaching 20MHz.
Lower powered operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external clocks or
resonator circuitry. Because many operations on the AVR are single cycle,
the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a
large following due to the free and inexpensive development tools
available, including reasonably priced development boards and free
development software. The AVRs are marketed under various names that
http://avr-asm.tripod.com/id77.html (1 of 2)1/20/2009 8:43:13 PM
16 BIT MATH (AVR 202)

share the same basic core but with different peripheral and memory
combinations. Some models (notably, the ATmega range) have additional
instructions to make arithmetic faster. Compatibility amongst chips is fairly
good. See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC Core Running
Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with
Internal, Configurable Pull-up Resistors Multiple Internal Oscillators
Internal, Self-Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage methods
Optional Boot Code Section with Independent Lock Bits for Protection
Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit
Timers PWM Channels & dead time generator Lighting (PWM Specific)
Controller models Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used
with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed hardware &
Hub controller with embedded AVR. Also freely available low-speed (HID)
software emulation Ethernet Controller Support Universal Serial Interface
(USI) for Two or Three-Wire Synchronous Data Transfer Analog
Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex
of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-
voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep
Modes picoPower Devices Atmel AVR assembler programming language
Atmel AVR machine programming language

http://avr-asm.tripod.com/id77.html (2 of 2)1/20/2009 8:43:13 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

DECIMAL TO ASCII ROUTINE

HOME
RETRO_DAN
; universal signed, unsigned decimal number to ASCII
ASM FORUM convert
ASM MATH ; MSB -> LSB = r23:r22 ZH:ZL
_print24bit: ; Print unsigned 24 bit
TUTORIAL #1
values
TUTORIAL #2 clr r23
TUTORIAL #3 rjmp _prnum

MATH 200 _printsdecw: ; Print signed decimal (16

MATH 200b bit)
sbrs zh,7 ; Is the number < 0 ?
MATH 201 rjmp _printdecw ; No, print 0 to 32767
MATH 202 ser r22
ser r23
MATH 32X
rjmp _printsdecdw
MATH YX
_printdecb: ; Print (8 bit) value
DIV16 XX
clr zh
DIV 24 24
DIV 3216 _printdecw: ; Print unsigned decimal
(16 bit)
FLOAT 128 clr r22
SQRT16 clr r23

MATH 202 _printsdecdw: ; Print signed decimal (32

MATH 202 bit)
sbrs r23,7
DEC ASCII
rjmp _printdecdw
INT ASCII com zl
com zh
HX2ASC
com r22
AVG8 222 com r23
FFT7 subi zl,-1
sbci zh,-1
COPY 102 sbci r22,-1
LPM 108 sbci r23,-1
ldi r24,'-'
EPROM 100 rcall _putchar
SER EPROM
_printdecdw: ; Print unsigned decimal
DFLASH AT45
(32 bit)
FLASH CARD _prnum:
push yl
VFX SMIL
push yh
VFX MEM clr r1
SORT 220 clr r2
clr r3
CRC 236 clr r4
XMODEM REC clr r5
ldi r20,32
UART 304 _prnum1:
UART 305 ldi yl,1
clr yh
UART 128
ldi r21,5
UART BUFF _prnum2:
ldi r25,51
USB 232
ld r24,y
AVR ISP add r24,r25
ISP 2313 sbrc r24,7
andi r25,15
ISP 1200 sbrc r24,3
AVR SPI andi r25,240
sub r24,r25
I2C 300 st y+,r24
I2C 302 dec r21
brne _prnum2
I2C TWI26
lsl zl
I2C/TWI 128 rol zh
I2C/TWI AT8 rol r22
rol r23
DALLAS-1W rol r1
DALLAS CRC rol r2
rol r3
ETHNET 8019 rol r4
TEA rol r5
dec r20
ADC 128 brne _prnum1
ADC 10B clt
ldi zl,6
ADC 400
clr zh
ADC 401 _prnum3:
THERM 232 ld r24,-z
rcall _prnum5
IRD 410 cpi zl,2
LCD HD44 brsh _prnum3
brts _prnum4
LCD 2313 set
LCD44 2313 mov r24,r1
rcall _prnum6
KBD 240 _prnum4:
MUX 242 pop yh
pop yl
KBD PS2
ret
KBD PC/128 _prnum5:
PS2 EMU push r24
swap r24
BOOT MG8 rcall _prnum6
BOOT DR8 pop r24
_prnum6:
ALM CLK andi r24,0x0f ; convert to ASCII and
CLOCK 8564 eliminate leading zeros
subi r24,-'0'
90 DAYS
brts _putchar
DELAYS cpi r24,'0'
brne _prnum7
CALL ID
; if you want leading spaces for nice format, add
DTMF 314 here "ldi r24, ' ' rjmp _putchar
PWM 6CH ret
_prnum7:
PWM 10K set
ENCODE _putchar:
rjmp _my_output_char_routine ; RS232, LCD, I2C
STH-11 etc, etc...
ATMEL CORP
AVR
BUTTERFLY
AVR BOOK

Programming the AVR Microcontrollers in Machine Language

AVR
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Atmel AVR From Wikipedia, the free encyclopedia

(Redirected from Avr) Jump to: navigation, search The AVRs
are a family of RISC microcontrollers from Atmel. Their
internal architecture was conceived by two students: Alf-Egil
Bogen and Vegard Wollan, at the Norwegian Institute of
Technology (NTH] and further developed at Atmel Norway, a
subsidiary founded by the two architects. Atmel recently
released the Atmel AVR32 line of microcontrollers. These are
32-bit RISC devices featuring SIMD and DSP instructions,
along with many additional features for audio and video
processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC &
Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other
AVR Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line
is either 16 or 32 bits in length. The Flash memory is
addressed using 16 bit word sizes. The size of the program
memory is indicated in the naming of the device itself. For
instance, the ATmega64x line has 64Kbytes of Flash. Almost
all AVR devices are self-programmable. [edit] Data Memory
and Registers The data address space consists of the
register file, I/O registers, and SRAM. The AVRs have thirty-
two single-byte registers and are classified as 8-bit RISC
devices. The working registers are mapped in as the first
thirty-two memory spaces (000016-001F16) followed by the 64
I/O registers (002016-005F16). The actual usable RAM starts
after both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic
sugar for LDI R,$FF. Math operations such as EOR modify
flags while moves/loads/stores/branches such as LDI do not.)
[edit] Speed The AVR line can normally support clock speeds
from 0-16MHz, with some devices reaching 20MHz. Lower
powered operation usually requires a reduced clock speed.
All AVRs feature an on-chip oscillator, removing the need for
external clocks or resonator circuitry. Because many
operations on the AVR are single cycle, the AVR can achieve
up to 1MIPS per MHz. [edit] Development AVRs have a large
following due to the free and inexpensive development tools
available, including reasonably priced development boards
and free development software. The AVRs are marketed
under various names that share the same basic core but with
different peripheral and memory combinations. Some models
(notably, the ATmega range) have additional instructions to
make arithmetic faster. Compatibility amongst chips is fairly
good. See external links for sites relating to AVR
development. [edit] Features Current AVRs offer a wide range
of features: RISC Core Running Many Single Cycle
Instructions Multifunction, Bi-directional I/O Ports with
Internal, Configurable Pull-up Resistors Multiple Internal
Oscillators Internal, Self-Programmable Instruction Flash
Memory up to 256K In-System Programmable using ICSP,
JTAG, or High Voltage methods Optional Boot Code Section
with Independent Lock Bits for Protection Internal Data
EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit
Timers PWM Channels & dead time generator Lighting (PWM
Specific) Controller models Dedicated I²C Compatible Two-
Wire Interface (TWI) Synchronous/Asynchronous Serial
Peripherals (UART/USART) (As used with RS-232,RS-485, and
more) Serial Peripheral Interface (SPI) CAN Controller
Support USB Controller Support Proper High-speed hardware
& Hub controller with embedded AVR. Also freely available
low-speed (HID) software emulation Ethernet Controller
Support Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of
up to 16 channels Brownout Detection Watchdog Timer
(WDT) Low-voltage Devices Operating Down to 1.8v Multiple
Power-Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the
Norwegian Institute of Technology (NTH] and further
developed at Atmel Norway, a subsidiary founded by the two
architects. Atmel recently released the Atmel AVR32 line of
microcontrollers. These are 32-bit RISC devices featuring
SIMD and DSP instructions, along with many additional
features for audio and video processing, intended to compete
with ARM based processors. Note that the use of "AVR" in
this article refers to the 8-bit RISC line of Atmel AVR
Microcontrollers. The acronym AVR has been reported to
stand for Advanced Virtual RISC. It's also rumoured to stand
for the company's founders: Alf and Vegard, who are evasive
when questioned about it. Contents [hide] 1 Device Overview
1.1 Program Memory 1.2 Data Memory and Registers 1.3
EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3
Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel
Official Links 6.2 AVR Forums & Discussion Groups 6.3
Machine Language Development 6.4 C Language
Development 6.5 BASIC & Other AVR Languages 6.6 AVR
Butterfly Specific 6.7 Other AVR Links [edit] Device Overview
The AVR is a Harvard architecture machine with programs
and data stored and addressed separately. Flash, EEPROM,
and SRAM are all integrated onto a single die, removing the
need for external memory (though still available on some
devices). [edit] Program Memory Program instructions are
stored in semi-permanent Flash memory. Each instruction for
the AVR line is either 16 or 32 bits in length. The Flash
memory is addressed using 16 bit word sizes. The size of the
program memory is indicated in the naming of the device
itself. For instance, the ATmega64x line has 64Kbytes of
Flash. Almost all AVR devices are self-programmable. [edit]
Data Memory and Registers The data address space consists
of the register file, I/O registers, and SRAM. The AVRs have
thirty-two single-byte registers and are classified as 8-bit
RISC devices. The working registers are mapped in as the
first thirty-two memory spaces (000016-001F16) followed by
the 64 I/O registers (002016-005F16). The actual usable RAM
starts after both these sections (address 006016). (Note that
the I/O register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic
sugar for LDI R,$FF. Math operations such as EOR modify
flags while moves/loads/stores/branches such as LDI do not.)
[edit] Speed The AVR line can normally support clock speeds
from 0-16MHz, with some devices reaching 20MHz. Lower
powered operation usually requires a reduced clock speed.
All AVRs feature an on-chip oscillator, removing the need for
external clocks or resonator circuitry. Because many
operations on the AVR are single cycle, the AVR can achieve
up to 1MIPS per MHz. [edit] Development AVRs have a large
following due to the free and inexpensive development tools
available, including reasonably priced development boards
and free development software. The AVRs are marketed
under various names that share the same basic core but with
different peripheral and memory combinations. Some models
(notably, the ATmega range) have additional instructions to
make arithmetic faster. Compatibility amongst chips is fairly
good. See external links for sites relating to AVR
development. [edit] Features Current AVRs offer a wide range
of features: RISC Core Running Many Single Cycle
Instructions Multifunction, Bi-directional I/O Ports with
Internal, Configurable Pull-up Resistors Multiple Internal
Oscillators Internal, Self-Programmable Instruction Flash
Memory up to 256K In-System Programmable using ICSP,
JTAG, or High Voltage methods Optional Boot Code Section
with Independent Lock Bits for Protection Internal Data
EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit
Timers PWM Channels & dead time generator Lighting (PWM
Specific) Controller models Dedicated I²C Compatible Two-
Wire Interface (TWI) Synchronous/Asynchronous Serial
Peripherals (UART/USART) (As used with RS-232,RS-485, and
more) Serial Peripheral Interface (SPI) CAN Controller
Support USB Controller Support Proper High-speed hardware
& Hub controller with embedded AVR. Also freely available
low-speed (HID) software emulation Ethernet Controller
Support Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of
up to 16 channels Brownout Detection Watchdog Timer
(WDT) Low-voltage Devices Operating Down to 1.8v Multiple
Power-Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the
Norwegian Institute of Technology (NTH] and further
developed at Atmel Norway, a subsidiary founded by the two
architects. Atmel recently released the Atmel AVR32 line of
microcontrollers. These are 32-bit RISC devices featuring
SIMD and DSP instructions, along with many additional
features for audio and video processing, intended to compete
with ARM based processors. Note that the use of "AVR" in
this article refers to the 8-bit RISC line of Atmel AVR
Microcontrollers. The acronym AVR has been reported to
stand for Advanced Virtual RISC. It's also rumoured to stand
for the company's founders: Alf and Vegard, who are evasive
when questioned about it. Contents [hide] 1 Device Overview
1.1 Program Memory 1.2 Data Memory and Registers 1.3
EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3
Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel
Official Links 6.2 AVR Forums & Discussion Groups 6.3
Machine Language Development 6.4 C Language
Development 6.5 BASIC & Other AVR Languages 6.6 AVR
Butterfly Specific 6.7 Other AVR Links [edit] Device Overview
The AVR is a Harvard architecture machine with programs
and data stored and addressed separately. Flash, EEPROM,
and SRAM are all integrated onto a single die, removing the
need for external memory (though still available on some
devices). [edit] Program Memory Program instructions are
stored in semi-permanent Flash memory. Each instruction for
the AVR line is either 16 or 32 bits in length. The Flash
memory is addressed using 16 bit word sizes. The size of the
program memory is indicated in the naming of the device
itself. For instance, the ATmega64x line has 64Kbytes of
Flash. Almost all AVR devices are self-programmable. [edit]
Data Memory and Registers The data address space consists
of the register file, I/O registers, and SRAM. The AVRs have
thirty-two single-byte registers and are classified as 8-bit
RISC devices. The working registers are mapped in as the
first thirty-two memory spaces (000016-001F16) followed by
the 64 I/O registers (002016-005F16). The actual usable RAM
starts after both these sections (address 006016). (Note that
the I/O register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic
sugar for LDI R,$FF. Math operations such as EOR modify
flags while moves/loads/stores/branches such as LDI do not.)
[edit] Speed The AVR line can normally support clock speeds
from 0-16MHz, with some devices reaching 20MHz. Lower
powered operation usually requires a reduced clock speed.
All AVRs feature an on-chip oscillator, removing the need for
external clocks or resonator circuitry. Because many
operations on the AVR are single cycle, the AVR can achieve
up to 1MIPS per MHz. [edit] Development AVRs have a large
following due to the free and inexpensive development tools
available, including reasonably priced development boards
and free development software. The AVRs are marketed
under various names that share the same basic core but with
different peripheral and memory combinations. Some models
(notably, the ATmega range) have additional instructions to
make arithmetic faster. Compatibility amongst chips is fairly
good. See external links for sites relating to AVR
development. [edit] Features Current AVRs offer a wide range
of features: RISC Core Running Many Single Cycle
Instructions Multifunction, Bi-directional I/O Ports with
Internal, Configurable Pull-up Resistors Multiple Internal
Oscillators Internal, Self-Programmable Instruction Flash
Memory up to 256K In-System Programmable using ICSP,
JTAG, or High Voltage methods Optional Boot Code Section
with Independent Lock Bits for Protection Internal Data
EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit
Timers PWM Channels & dead time generator Lighting (PWM
Specific) Controller models Dedicated I²C Compatible Two-
Wire Interface (TWI) Synchronous/Asynchronous Serial
Peripherals (UART/USART) (As used with RS-232,RS-485, and
more) Serial Peripheral Interface (SPI) CAN Controller
Support USB Controller Support Proper High-speed hardware
& Hub controller with embedded AVR. Also freely available
low-speed (HID) software emulation Ethernet Controller
Support Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of
up to 16 channels Brownout Detection Watchdog Timer
(WDT) Low-voltage Devices Operating Down to 1.8v Multiple
Power-Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language
http://avr-asm.tripod.com/decascii.html (1 of 2)1/20/2009 8:44:04 PM
16 BIT MATH (AVR 202)

http://avr-asm.tripod.com/decascii.html (2 of 2)1/20/2009 8:44:04 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

INTEGER TO ASCII ROUTINE

HOME
RETRO_DAN
;
ASM FORUM ******************************************************************************
ASM MATH ; Author : Nay Oo
; DESCRIPTION :
TUTORIAL #1
; - This program convert an integer number to ASCII
TUTORIAL #2 ; AVR Newbie Learning program
TUTORIAL #3 ; - The integer Range (0..127)
; - You can use AVRStudio 4 simulator to see the
MATH 200 register
MATH 200b ; contents (recommended)
;
MATH 201 ; uController : AT90S8515
MATH 202 ; Development Board : STK500
;
MATH 32X
;
MATH YX ;
; AUTHOR NOTE:
DIV16 XX
; This file was written by me to educate myself in
DIV 24 24 AVR
DIV 3216 ; Initial ideas was gathered from the http://www.
avrbeginners.net/
FLOAT 128 ; Please do refer to them for more indept
SQRT16 theroritical aspects.
;
MATH 202 ; After the convertion is done, you can send these
MATH 202 ASCII coded
; numbers to UART,USB, LCD interface, etc.
DEC ASCII
;
INT ASCII ; If you have any thing to discuss about this file,
you can contact
HX2ASC
; me via my personal email : nayoo1979@yahoo.com.sg
AVG8 222 ;
FFT7 ;
******************************************************************************
COPY 102
LPM 108 ;* Include Microcontroller Device specific file
.include "8515def.inc"
EPROM 100
SER EPROM ;* Register Variable Declaration Here
.def temp = r16 ; temporary storage
DFLASH AT45
register
FLASH CARD .def intval = r17 ; the variable which
stores the integer value
VFX SMIL
.def HundredCounter = r18 ; eg. 127 = '1'
VFX MEM .def TenthCounter = r19 ; eg. 127 = '2'
SORT 220 .def OneCounter = r20 ; eg. 127 = '7'

CRC 236 ;* Integer Value

XMODEM REC .equ Number=127 ; You can change
any number from 0 to 127
UART 304
UART 305
.org 0x0000
UART 128
rjmp RESET ; program reset vector
UART BUFF
USB 232
;* Integer to ASCII converter subrountine here
AVR ISP IntToASCII:
ISP 2313 cpi intVal,100 ;
brge DivideBy100 ; jump if
ISP 1200 (intVal>=100)
AVR SPI cpi intVal,10
brge DivideBy10 ; jump if
I2C 300 (intVal>=10)
I2C 302 mov OneCounter,IntVal
add HundredCounter,temp ; here, we got
I2C TWI26
there single digits
I2C/TWI 128 add TenthCounter,temp ; from that, we
I2C/TWI AT8 convert them to
add OneCounter,temp ; ASCII values !!!
DALLAS-1W ret
DALLAS CRC
DivideBy100:
ETHNET 8019 subi intVal,100
TEA inc HundredCounter
rjmp IntToASCII
ADC 128
ADC 10B DivideBy10:
subi intVal,10
ADC 400
inc TenthCounter
ADC 401 rjmp IntToASCII
THERM 232
IRD 410 ;* Main Program Starts here
LCD HD44 RESET:
ldi temp,low(RAMEND) ; STACK pointer
LCD 2313 location
LCD44 2313 out SPL,temp ; started
from the
KBD 240 ldi temp,high(RAMEND) ; end of SRAM
MUX 242 out SPH,temp ; RAMEND
is declared in 8515def.inc file
KBD PS2
KBD PC/128 ldi HundredCounter,0 ; set counters
PS2 EMU values to zero
ldi TenthCounter,0 ;
BOOT MG8 ldi OneCounter,0 ;
BOOT DR8 ldi temp,48 ; ASCII =
Number + 48
ALM CLK ;
CLOCK 8564 In ASCII table, we can see that '0' is 48 (0x30)
;
90 DAYS
therefore, need to add 48 to the single digits
DELAYS
ldi intVal,Number
CALL ID
rcall IntToASCII ; subroutine call
DTMF 314 ;
PWM 6CH which convert integer value to
;
PWM 10K ASCII value
ENCODE
forever: rjmp forever ; infinite loop
STH-11
ATMEL CORP
AVR
BUTTERFLY
AVR BOOK

Programming the AVR Microcontrollers in Machine Language

AVR
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr)
Jump to: navigation, search The AVRs are a family of RISC microcontrollers
from Atmel. Their internal architecture was conceived by two students: Alf-
Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary founded by the
two architects. Atmel recently released the Atmel AVR32 line of
microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio and video
processing, intended to compete with ARM based processors. Note that the
use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR
Microcontrollers. The acronym AVR has been reported to stand for
Advanced Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned about it.
Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory
and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development
3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development
6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR
Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a
Harvard architecture machine with programs and data stored and addressed
separately. Flash, EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available on some
devices). [edit] Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is either 16 or 32
bits in length. The Flash memory is addressed using 16 bit word sizes. The
size of the program memory is indicated in the naming of the device itself.
For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and SRAM. The
AVRs have thirty-two single-byte registers and are classified as 8-bit RISC
devices. The working registers are mapped in as the first thirty-two memory
spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16).
The actual usable RAM starts after both these sections (address 006016).
(Note that the I/O register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will occupy a portion of
the SRAM.) Even though there are separate addressing schemes and
optimized opcodes for register file and I/O register access, all can still be
addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost
all devices have on-die EEPROM. This is most often used for long-term
parameter storage to be retrieved even after cycling the power of the device.
[edit] Program Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is executing.
Most instructions take just one or two clock cycles, making AVRs relatively
fast among the eight-bit microcontrollers. The AVR family of processors
were designed for the efficient execution of compiled C code. The AVR
instruction set is more orthogonal than most eight-bit microcontrollers,
however, it is not completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other. Register locations
R0 to R15 have different addressing capabilities than register locations R16
to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports
32 to 63. CLR affects flags, while SER does not, even though they are
complementary instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native instructions. Instead
CLR is syntactic sugar for [produces the same machine code as] EOR R,R
while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR
modify flags while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from 0-16MHz, with
some devices reaching 20MHz. Lower powered operation usually requires a
reduced clock speed. All AVRs feature an on-chip oscillator, removing the
need for external clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit]
Development AVRs have a large following due to the free and inexpensive
development tools available, including reasonably priced development
boards and free development software. The AVRs are marketed under
various names that share the same basic core but with different peripheral
and memory combinations. Some models (notably, the ATmega range) have
additional instructions to make arithmetic faster. Compatibility amongst
chips is fairly good. See external links for sites relating to AVR development.
[edit] Features Current AVRs offer a wide range of features: RISC Core
Running Many Single Cycle Instructions Multifunction, Bi-directional I/O
Ports with Internal, Configurable Pull-up Resistors Multiple Internal
Oscillators Internal, Self-Programmable Instruction Flash Memory up to
256K In-System Programmable using ICSP, JTAG, or High Voltage methods
Optional Boot Code Section with Independent Lock Bits for Protection
Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit
Timers PWM Channels & dead time generator Lighting (PWM Specific)
Controller models Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used
with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed hardware &
Hub controller with embedded AVR. Also freely available low-speed (HID)
software emulation Ethernet Controller Support Universal Serial Interface
(USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators
LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16
channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices
Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower
Devices Atmel AVR assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free encyclopedia
(Redirected from Avr) Jump to: navigation, search The AVRs are a family of
RISC microcontrollers from Atmel. Their internal architecture was conceived
by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel Norway, a
subsidiary founded by the two architects. Atmel recently released the Atmel
AVR32 line of microcontrollers. These are 32-bit RISC devices featuring
SIMD and DSP instructions, along with many additional features for audio
and video processing, intended to compete with ARM based processors.
Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel
AVR Microcontrollers. The acronym AVR has been reported to stand for
Advanced Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned about it.
Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory
and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development
3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development
6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR
Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a
Harvard architecture machine with programs and data stored and addressed
separately. Flash, EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available on some
devices). [edit] Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is either 16 or 32
bits in length. The Flash memory is addressed using 16 bit word sizes. The
size of the program memory is indicated in the naming of the device itself.
For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and SRAM. The
AVRs have thirty-two single-byte registers and are classified as 8-bit RISC
devices. The working registers are mapped in as the first thirty-two memory
spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16).
The actual usable RAM starts after both these sections (address 006016).
(Note that the I/O register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will occupy a portion of
the SRAM.) Even though there are separate addressing schemes and
optimized opcodes for register file and I/O register access, all can still be
addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost
all devices have on-die EEPROM. This is most often used for long-term
parameter storage to be retrieved even after cycling the power of the device.
[edit] Program Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is executing.
Most instructions take just one or two clock cycles, making AVRs relatively
fast among the eight-bit microcontrollers. The AVR family of processors
were designed for the efficient execution of compiled C code. The AVR
instruction set is more orthogonal than most eight-bit microcontrollers,
however, it is not completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other. Register locations
R0 to R15 have different addressing capabilities than register locations R16
to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports
32 to 63. CLR affects flags, while SER does not, even though they are
complementary instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native instructions. Instead
CLR is syntactic sugar for [produces the same machine code as] EOR R,R
while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR
modify flags while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from 0-16MHz, with
some devices reaching 20MHz. Lower powered operation usually requires a
reduced clock speed. All AVRs feature an on-chip oscillator, removing the
need for external clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit]
Development AVRs have a large following due to the free and inexpensive
development tools available, including reasonably priced development
boards and free development software. The AVRs are marketed under
various names that share the same basic core but with different peripheral
and memory combinations. Some models (notably, the ATmega range) have
additional instructions to make arithmetic faster. Compatibility amongst
chips is fairly good. See external links for sites relating to AVR development.
[edit] Features Current AVRs offer a wide range of features: RISC Core
Running Many Single Cycle Instructions Multifunction, Bi-directional I/O
Ports with Internal, Configurable Pull-up Resistors Multiple Internal
Oscillators Internal, Self-Programmable Instruction Flash Memory up to
256K In-System Programmable using ICSP, JTAG, or High Voltage methods
Optional Boot Code Section with Independent Lock Bits for Protection
Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit
Timers PWM Channels & dead time generator Lighting (PWM Specific)
Controller models Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used
with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed hardware &
Hub controller with embedded AVR. Also freely available low-speed (HID)
software emulation Ethernet Controller Support Universal Serial Interface
(USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators
LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16
channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices
Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower
Devices Atmel AVR assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free encyclopedia
(Redirected from Avr) Jump to: navigation, search The AVRs are a family of
RISC microcontrollers from Atmel. Their internal architecture was conceived
by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel Norway, a
subsidiary founded by the two architects. Atmel recently released the Atmel
AVR32 line of microcontrollers. These are 32-bit RISC devices featuring
SIMD and DSP instructions, along with many additional features for audio
and video processing, intended to compete with ARM based processors.
Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel
AVR Microcontrollers. The acronym AVR has been reported to stand for
Advanced Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned about it.
Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory
and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development
3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development
6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR
Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a
Harvard architecture machine with programs and data stored and addressed
separately. Flash, EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available on some
devices). [edit] Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is either 16 or 32
bits in length. The Flash memory is addressed using 16 bit word sizes. The
size of the program memory is indicated in the naming of the device itself.
For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and SRAM. The
AVRs have thirty-two single-byte registers and are classified as 8-bit RISC
devices. The working registers are mapped in as the first thirty-two memory
spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16).
The actual usable RAM starts after both these sections (address 006016).
(Note that the I/O register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will occupy a portion of
the SRAM.) Even though there are separate addressing schemes and
optimized opcodes for register file and I/O register access, all can still be
addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost
all devices have on-die EEPROM. This is most often used for long-term
parameter storage to be retrieved even after cycling the power of the device.
[edit] Program Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is executing.
Most instructions take just one or two clock cycles, making AVRs relatively
fast among the eight-bit microcontrollers. The AVR family of processors
were designed for the efficient execution of compiled C code. The AVR
instruction set is more orthogonal than most eight-bit microcontrollers,
however, it is not completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other. Register locations
R0 to R15 have different addressing capabilities than register locations R16
to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports
32 to 63. CLR affects flags, while SER does not, even though they are
complementary instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native instructions. Instead
CLR is syntactic sugar for [produces the same machine code as] EOR R,R
while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR
modify flags while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from 0-16MHz, with
some devices reaching 20MHz. Lower powered operation usually requires a
reduced clock speed. All AVRs feature an on-chip oscillator, removing the
need for external clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit]
Development AVRs have a large following due to the free and inexpensive
development tools available, including reasonably priced development
boards and free development software. The AVRs are marketed under
various names that share the same basic core but with different peripheral
and memory combinations. Some models (notably, the ATmega range) have
additional instructions to make arithmetic faster. Compatibility amongst
chips is fairly good. See external links for sites relating to AVR development.
[edit] Features Current AVRs offer a wide range of features: RISC Core
Running Many Single Cycle Instructions Multifunction, Bi-directional I/O
Ports with Internal, Configurable Pull-up Resistors Multiple Internal
Oscillators Internal, Self-Programmable Instruction Flash Memory up to
256K In-System Programmable using ICSP, JTAG, or High Voltage methods
Optional Boot Code Section with Independent Lock Bits for Protection
Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit
Timers PWM Channels & dead time generator Lighting (PWM Specific)
Controller models Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used
with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed hardware &
Hub controller with embedded AVR. Also freely available low-speed (HID)
software emulation Ethernet Controller Support Universal Serial Interface
(USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators
LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16
channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices
Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower
Devices Atmel AVR assembler programming language Atmel AVR machine
programming language
http://avr-asm.tripod.com/intascii.html (1 of 2)1/20/2009 8:44:37 PM
16 BIT MATH (AVR 202)

http://avr-asm.tripod.com/intascii.html (2 of 2)1/20/2009 8:44:37 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

TWO HEX TO ASCII ROUTINES

HOME
RETRO_DAN
ASM FORUM ;-----------------------------------------------
ASM MATH ; HEX TO ASCII
;-----------------------------------------------
TUTORIAL #1
;I think, this was the smallest (only 10 words).
TUTORIAL #2
TUTORIAL #3 ;input: R16 = 8 bit value 0 ... 255
;output: R18, R17, R16 = digits
MATH 200 ;bytes: 20
MATH 200b ;
bcd:
MATH 201 ldi r18, -1 + '0'
MATH 202 _bcd1:
inc r18
MATH 32X
subi r16, 100
MATH YX brcc _bcd1
ldi r17, 10 + '0'
DIV16 XX
_bcd2:
DIV 24 24 dec r17
DIV 3216 subi r16, -10
brcs _bcd2
FLOAT 128 sbci r16, -'0'
SQRT16 ret

MATH 202
MATH 202 ;
**********************************************************************************************
DEC ASCII
;E. Seah
INT ASCII ;03/24/01
;HEX-TO-ASCII conversion subroutine
HX2ASC
;"high" registers : 4 (3 if "value" can be "low"
AVG8 222 register)
FFT7 ;"low" registers : 0 (1 if "value" can be "low" register)
;program words : 22+1 (including return)
COPY 102 ;
LPM 108 ;description : convert 0x00<="value"<=0xff to 3 digits of
ASCII in "hundreds","tens" and "ones"
EPROM 100 ;
SER EPROM _h2a: ldi hundreds,200 ;init hundreds for hundreds cp
loop
DFLASH AT45
ldi ones,2 ;init ones for hundreds cp loop
FLASH CARD
a100: cp value,hundreds
VFX SMIL
brlo sub100 ;if value=hundreds
VFX MEM sub value,hundreds ;remove 100s from value
SORT 220 subi ones,-0x30 ;?00<=x<=?99, 1st digit is '?'
mov hundreds,ones
CRC 236 ldi tens,90 ;init tens for tens cp loop
XMODEM REC ldi ones,9 ;init ones for tens cp loop
a10: cp value,tens
UART 304 brlo sub10 ;if value=tens
UART 305 sub value,tens ;remove 10s from value
subi ones,-0x30 ;?0<=x<=?9, 2nd digit is '?'
UART 128
mov tens,ones
UART BUFF
mov ones,value ;3rd digit is the remainder
USB 232
subi ones,-0x30 ;'ones' in ASCII
AVR ISP
ISP 2313 ret

ISP 1200 sub100: subi hundreds,100 ;for compare with value

AVR SPI subi ones,1 ;use ones as temp storage for 1st digit
rjmp a100
I2C 300
I2C 302 sub10: subi tens,10 ;for compare with value
subi ones,1 ;use ones as temp storage for 2nd digit
I2C TWI26
rjmp a10
I2C/TWI 128
I2C/TWI AT8
DALLAS-1W
DALLAS CRC
ETHNET 8019
TEA
ADC 128
ADC 10B
ADC 400
ADC 401
THERM 232 Programming the AVR Microcontrollers in Machine Language
IRD 410
LCD HD44 AVR
LCD 2313 << Prev | Ring Hub | Join | Rate| Next
LCD44 2313 >>
KBD 240 © WebRing Inc. Search
MUX 242
KBD PS2
KBD PC/128
Atmel AVR From Wikipedia, the free encyclopedia (Redirected
PS2 EMU from Avr) Jump to: navigation, search The AVRs are a family of
BOOT MG8 RISC microcontrollers from Atmel. Their internal architecture
BOOT DR8
ALM CLK
was conceived by two students: Alf-Egil Bogen and Vegard
CLOCK 8564 Wollan, at the Norwegian Institute of Technology (NTH] and
90 DAYS further developed at Atmel Norway, a subsidiary founded by
DELAYS
CALL ID
the two architects. Atmel recently released the Atmel AVR32
DTMF 314 line of microcontrollers. These are 32-bit RISC devices
PWM 6CH featuring SIMD and DSP instructions, along with many
PWM 10K
ENCODE
additional features for audio and video processing, intended to
STH-11 compete with ARM based processors. Note that the use of
ATMEL CORP "AVR" in this article refers to the 8-bit RISC line of Atmel AVR
AVR
BUTTERFLY
Microcontrollers. The acronym AVR has been reported to stand
AVR BOOK for Advanced Virtual RISC. It's also rumoured to stand for the
company's founders: Alf and Vegard, who are evasive when
questioned about it. Contents [hide] 1 Device Overview 1.1
Program Memory 1.2 Data Memory and Registers 1.3 EEPROM
1.4 Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links
[edit] Device Overview The AVR is a Harvard architecture
machine with programs and data stored and addressed
separately. Flash, EEPROM, and SRAM are all integrated onto a
single die, removing the need for external memory (though still
available on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory. Each
instruction for the AVR line is either 16 or 32 bits in length. The
Flash memory is addressed using 16 bit word sizes. The size of
the program memory is indicated in the naming of the device
itself. For instance, the ATmega64x line has 64Kbytes of Flash.
Almost all AVR devices are self-programmable. [edit] Data
Memory and Registers The data address space consists of the
register file, I/O registers, and SRAM. The AVRs have thirty-two
single-byte registers and are classified as 8-bit RISC devices.
The working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive devices,
in which case memory mapped I/O registers will occupy a
portion of the SRAM.) Even though there are separate
addressing schemes and optimized opcodes for register file
and I/O register access, all can still be addressed and
manipulated as if they were in SRAM. [edit] EEPROM Almost all
devices have on-die EEPROM. This is most often used for long-
term parameter storage to be retrieved even after cycling the
power of the device. [edit] Program Execution Atmel's AVRs
have a single level pipeline design. The next machine
instruction is fetched as the current one is executing. Most
instructions take just one or two clock cycles, making AVRs
relatively fast among the eight-bit microcontrollers. The AVR
family of processors were designed for the efficient execution
of compiled C code. The AVR instruction set is more
orthogonal than most eight-bit microcontrollers, however, it is
not completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other.
Register locations R0 to R15 have different addressing
capabilities than register locations R16 to R31. I/O ports 0 to 31
have different addressing capabilities than I/O ports 32 to 63.
CLR affects flags, while SER does not, even though they are
complementary instructions. CLR set all bits to zero and SER
sets them to one. (Note though, that neither CLR nor SER are
native instructions. Instead CLR is syntactic sugar for
[produces the same machine code as] EOR R,R while SER is
syntactic sugar for LDI R,$FF. Math operations such as EOR
modify flags while moves/loads/stores/branches such as LDI
do not.) [edit] Speed The AVR line can normally support clock
speeds from 0-16MHz, with some devices reaching 20MHz.
Lower powered operation usually requires a reduced clock
speed. All AVRs feature an on-chip oscillator, removing the
need for external clocks or resonator circuitry. Because many
operations on the AVR are single cycle, the AVR can achieve
up to 1MIPS per MHz. [edit] Development AVRs have a large
following due to the free and inexpensive development tools
available, including reasonably priced development boards and
free development software. The AVRs are marketed under
various names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction, Bi-
directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-System
Programmable using ICSP, JTAG, or High Voltage methods
Optional Boot Code Section with Independent Lock Bits for
Protection Internal Data EEPROM up to 4KB Internal SRAM up
to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time
generator Lighting (PWM Specific) Controller models Dedicated
I²C Compatible Two-Wire Interface (TWI) Synchronous/
Asynchronous Serial Peripherals (UART/USART) (As used with
RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed
hardware & Hub controller with embedded AVR. Also freely
available low-speed (HID) software emulation Ethernet
Controller Support Universal Serial Interface (USI) for Two or
Three-Wire Synchronous Data Transfer Analog Comparators
LCD Controller Support 10-Bit A/D Converters, with multiplex of
up to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR assembler
programming language Atmel AVR machine programming
language Atmel AVR From Wikipedia, the free encyclopedia
(Redirected from Avr) Jump to: navigation, search The AVRs
are a family of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with many
additional features for audio and video processing, intended to
compete with ARM based processors. Note that the use of
"AVR" in this article refers to the 8-bit RISC line of Atmel AVR
Microcontrollers. The acronym AVR has been reported to stand
for Advanced Virtual RISC. It's also rumoured to stand for the
company's founders: Alf and Vegard, who are evasive when
questioned about it. Contents [hide] 1 Device Overview 1.1
Program Memory 1.2 Data Memory and Registers 1.3 EEPROM
1.4 Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links
[edit] Device Overview The AVR is a Harvard architecture
machine with programs and data stored and addressed
separately. Flash, EEPROM, and SRAM are all integrated onto a
single die, removing the need for external memory (though still
available on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory. Each
instruction for the AVR line is either 16 or 32 bits in length. The
Flash memory is addressed using 16 bit word sizes. The size of
the program memory is indicated in the naming of the device
itself. For instance, the ATmega64x line has 64Kbytes of Flash.
Almost all AVR devices are self-programmable. [edit] Data
Memory and Registers The data address space consists of the
register file, I/O registers, and SRAM. The AVRs have thirty-two
single-byte registers and are classified as 8-bit RISC devices.
The working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive devices,
in which case memory mapped I/O registers will occupy a
portion of the SRAM.) Even though there are separate
addressing schemes and optimized opcodes for register file
and I/O register access, all can still be addressed and
manipulated as if they were in SRAM. [edit] EEPROM Almost all
devices have on-die EEPROM. This is most often used for long-
term parameter storage to be retrieved even after cycling the
power of the device. [edit] Program Execution Atmel's AVRs
have a single level pipeline design. The next machine
instruction is fetched as the current one is executing. Most
instructions take just one or two clock cycles, making AVRs
relatively fast among the eight-bit microcontrollers. The AVR
family of processors were designed for the efficient execution
of compiled C code. The AVR instruction set is more
orthogonal than most eight-bit microcontrollers, however, it is
not completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other.
Register locations R0 to R15 have different addressing
capabilities than register locations R16 to R31. I/O ports 0 to 31
have different addressing capabilities than I/O ports 32 to 63.
CLR affects flags, while SER does not, even though they are
complementary instructions. CLR set all bits to zero and SER
sets them to one. (Note though, that neither CLR nor SER are
native instructions. Instead CLR is syntactic sugar for
[produces the same machine code as] EOR R,R while SER is
syntactic sugar for LDI R,$FF. Math operations such as EOR
modify flags while moves/loads/stores/branches such as LDI
do not.) [edit] Speed The AVR line can normally support clock
speeds from 0-16MHz, with some devices reaching 20MHz.
Lower powered operation usually requires a reduced clock
speed. All AVRs feature an on-chip oscillator, removing the
need for external clocks or resonator circuitry. Because many
operations on the AVR are single cycle, the AVR can achieve
up to 1MIPS per MHz. [edit] Development AVRs have a large
following due to the free and inexpensive development tools
available, including reasonably priced development boards and
free development software. The AVRs are marketed under
various names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction, Bi-
directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-System
Programmable using ICSP, JTAG, or High Voltage methods
Optional Boot Code Section with Independent Lock Bits for
Protection Internal Data EEPROM up to 4KB Internal SRAM up
to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time
generator Lighting (PWM Specific) Controller models Dedicated
I²C Compatible Two-Wire Interface (TWI) Synchronous/
Asynchronous Serial Peripherals (UART/USART) (As used with
RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed
hardware & Hub controller with embedded AVR. Also freely
available low-speed (HID) software emulation Ethernet
Controller Support Universal Serial Interface (USI) for Two or
Three-Wire Synchronous Data Transfer Analog Comparators
LCD Controller Support 10-Bit A/D Converters, with multiplex of
up to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR assembler
programming language Atmel AVR machine programming
language Atmel AVR From Wikipedia, the free encyclopedia
(Redirected from Avr) Jump to: navigation, search The AVRs
are a family of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with many
additional features for audio and video processing, intended to
compete with ARM based processors. Note that the use of
"AVR" in this article refers to the 8-bit RISC line of Atmel AVR
Microcontrollers. The acronym AVR has been reported to stand
for Advanced Virtual RISC. It's also rumoured to stand for the
company's founders: Alf and Vegard, who are evasive when
questioned about it. Contents [hide] 1 Device Overview 1.1
Program Memory 1.2 Data Memory and Registers 1.3 EEPROM
1.4 Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links
[edit] Device Overview The AVR is a Harvard architecture
machine with programs and data stored and addressed
separately. Flash, EEPROM, and SRAM are all integrated onto a
single die, removing the need for external memory (though still
available on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory. Each
instruction for the AVR line is either 16 or 32 bits in length. The
Flash memory is addressed using 16 bit word sizes. The size of
the program memory is indicated in the naming of the device
itself. For instance, the ATmega64x line has 64Kbytes of Flash.
Almost all AVR devices are self-programmable. [edit] Data
Memory and Registers The data address space consists of the
register file, I/O registers, and SRAM. The AVRs have thirty-two
single-byte registers and are classified as 8-bit RISC devices.
The working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive devices,
in which case memory mapped I/O registers will occupy a
portion of the SRAM.) Even though there are separate
addressing schemes and optimized opcodes for register file
and I/O register access, all can still be addressed and
manipulated as if they were in SRAM. [edit] EEPROM Almost all
devices have on-die EEPROM. This is most often used for long-
term parameter storage to be retrieved even after cycling the
power of the device. [edit] Program Execution Atmel's AVRs
have a single level pipeline design. The next machine
instruction is fetched as the current one is executing. Most
instructions take just one or two clock cycles, making AVRs
relatively fast among the eight-bit microcontrollers. The AVR
family of processors were designed for the efficient execution
of compiled C code. The AVR instruction set is more
orthogonal than most eight-bit microcontrollers, however, it is
not completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other.
Register locations R0 to R15 have different addressing
capabilities than register locations R16 to R31. I/O ports 0 to 31
have different addressing capabilities than I/O ports 32 to 63.
CLR affects flags, while SER does not, even though they are
complementary instructions. CLR set all bits to zero and SER
sets them to one. (Note though, that neither CLR nor SER are
native instructions. Instead CLR is syntactic sugar for
[produces the same machine code as] EOR R,R while SER is
syntactic sugar for LDI R,$FF. Math operations such as EOR
modify flags while moves/loads/stores/branches such as LDI
do not.) [edit] Speed The AVR line can normally support clock
speeds from 0-16MHz, with some devices reaching 20MHz.
Lower powered operation usually requires a reduced clock
speed. All AVRs feature an on-chip oscillator, removing the
need for external clocks or resonator circuitry. Because many
operations on the AVR are single cycle, the AVR can achieve
up to 1MIPS per MHz. [edit] Development AVRs have a large
following due to the free and inexpensive development tools
available, including reasonably priced development boards and
free development software. The AVRs are marketed under
various names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction, Bi-
directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-System
Programmable using ICSP, JTAG, or High Voltage methods
Optional Boot Code Section with Independent Lock Bits for
Protection Internal Data EEPROM up to 4KB Internal SRAM up
to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time
generator Lighting (PWM Specific) Controller models Dedicated
I²C Compatible Two-Wire Interface (TWI) Synchronous/
Asynchronous Serial Peripherals (UART/USART) (As used with
RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed
hardware & Hub controller with embedded AVR. Also freely
available low-speed (HID) software emulation Ethernet
Controller Support Universal Serial Interface (USI) for Two or
Three-Wire Synchronous Data Transfer Analog Comparators
LCD Controller Support 10-Bit A/D Converters, with multiplex of
up to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR assembler
programming language Atmel AVR machine programming
language
http://avr-asm.tripod.com/hx2asc.html (1 of 2)1/20/2009 8:45:10 PM
16 BIT MATH (AVR 202)

http://avr-asm.tripod.com/hx2asc.html (2 of 2)1/20/2009 8:45:10 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

8 POINT MOVING AVERAGE (AVR 222)

HOME
RETRO_DAN
;**** A P P L I C A T I O N N O T E A V R 2 2 2
ASM FORUM ************************
ASM MATH ;*
;* Title: 8-Point Moving Average Filter
TUTORIAL #1
;* Version: 1.0
TUTORIAL #2 ;* Last updated: 97.07.04
TUTORIAL #3 ;* Target: AT90Sxx1x (Devices with SRAM)
;*
MATH 200 ;* Support E-mail: avr@atmel.com
MATH 200b ;*
;* DESCRIPTION
MATH 201 ;* This Application note shows an implementation of an
MATH 202 8-point Moving
;* Average (MAV) filter. The program filters a data
MATH 32X
array containing SIZE
MATH YX ;* elements starting at T_START. The App. note contains
a test
DIV16 XX
;* program which copies a 60-byte block of data from
DIV 24 24 program memory to
DIV 3216 ;* SRAM and filters the data. Note that the ends of the
data array are not
FLOAT 128 ;* filtered.
SQRT16 ;*
;
MATH 202 ***************************************************************************
MATH 202
.include "8515def.inc"
DEC ASCII
INT ASCII .equ SIZE =60 ;data array size
.equ TABLE_L =$60 ;Low SRAM address
HX2ASC
of first data element
AVG8 222 .equ TABLE_H =$00 ;High SRAM address
FFT7 of first data element

COPY 102 rjmp RESET ;Reset Handle

LPM 108
;
EPROM 100 ***************************************************************************
SER EPROM ;*
;* "mav8"
DFLASH AT45
;*
FLASH CARD ;* This subroutine filters SIZE bytes with the first
element in SRAM
VFX SMIL
;* location T_START. The filter routine uses an 8-byte
VFX MEM ring buffer which
SORT 220 ;* occupies working registers r0-r7. As filtering
progresses, this ring
CRC 236 ;* buffer always contains the 8-byte window to be
XMODEM REC averaged.
;*
UART 304 ;* Number of words :31 + return
UART 305 ;* Number of cycles :59 + (SIZE-7)*75 + return
;* Low registers used :11 (r0-r7,mav_tmp,AL,AH)
UART 128
;* High registers used :1 (t_size)
UART BUFF ;* Pointers used :X,Y,Z
;*
USB 232
;
AVR ISP ***************************************************************************
ISP 2313
;***** Subroutine Register Variables
ISP 1200
AVR SPI .def mav_tmp =r8 ;temprary
storage register
I2C 300 .def AL =r9 ;ring
I2C 302 buffer sum, low byte
.def AH =r10 ;ring
I2C TWI26
buffer sum, high byte
I2C/TWI 128 .def t_size =r16 ;size of
I2C/TWI AT8 table

DALLAS-1W ;***** Code

DALLAS CRC
mav8:
ETHNET 8019 clr YH
TEA clr YL ;init pointers
clr XH
ADC 128 clr XL
ADC 10B
;***** Fill ring buffer with first-8 byte data segment
ADC 400
ADC 401 mav8_1: ld mav_tmp,Z+ ;get SRAM
THERM 232 data
st Y+,mav_tmp ;store in register
IRD 410 cpi YL,8 ;got all?
LCD HD44 brne mav8_1 ;if not, loop more
sbiw ZL,5 ;Z points to first
LCD 2313 value to filter
LCD44 2313
mav8_2:
KBD 240 ;***** Find average
MUX 242 clr AH ;Clear avg High byte
clr AL ;Clear avg Low byte
KBD PS2
clr YL ;init Y-pointer
KBD PC/128 mav8_3: ld mav_tmp,Y+ ;
PS2 EMU add AL,mav_tmp ;add value to AL
adc AH,XH ;add carry to AH
BOOT MG8 (XH is zero)
BOOT DR8 cpi YL,8 ;added all ?
brne mav8_3 ;if not, loop
ALM CLK again
CLOCK 8564 lsr AH ;divide by 8
ror AL ;
90 DAYS
lsr AH ;
DELAYS ror AL ;
lsr AH ;
CALL ID
ror AL ;
DTMF 314 ldd mav_tmp,Z+5 ;get next value to
PWM 6CH buffer
st X+,mav_tmp ;store to buffer
PWM 10K andi XL,$07 ;mask away pointer
ENCODE upper bits
st Z+,AL ;store average
STH-11 dec t_size
ATMEL CORP cpi t_size,4 ;end of array?
brne mav8_2 ;if not, loop
AVR
more
BUTTERFLY ret
AVR BOOK
;
***************************************************************************
;*
;* Test Program
;*
;* This program copies 60 bytes of data from Program
memory to SRAM. It
;* then calls "mav8" to get the data filtered.
;*
;
***************************************************************************

RESET:

;***** Main program Register variables

.def temp =r16

;***** Code

ldi temp,low(RAMEND)
out SPL,temp
ldi temp,high(RAMEND)
out SPH,temp ;init Stack Pointer

;***** Memory fill

clr ZH
ldi ZL,tableend*2+1 ;Z-pointer <- ROM table end
+ 1
ldi YL,low(256*TABLE_H+TABLE_L+SIZE)
ldi YH,high(256*TABLE_H+TABLE_L+SIZE)
;Y pointer <- SRAM table
end + 1
loop: lpm ;get ROM constant
st -Y,r0 ;store in SRAM and
decrement Y-pointer
sbiw ZL,1 ;decrement Z-pointer
cpi YL,TABLE_L ;if not done
brne loop ; loop more
cpi YH,TABLE_H
brne loop

;***** Filter data

ldi ZL,TABLE_L
ldi ZH,TABLE_H
ldi T_size,SIZE
rcall mav8

forever:rjmp forever

;***** 60 ROM Constants

table:
.db 120,196
.db 78,216
.db 78,100
.db 43,39
.db 241,43
.db 62,172
.db 109,69
.db 48,184
.db 215,231
.db 63,133
.db 216,8
.db 121,126
.db 188,98
.db 168,205
.db 157,172
.db 108,233
.db 80,255
.db 252,102
.db 198,0
.db 171,239
.db 107,114
.db 172,170
.db 17,45
.db 42,55
.db 34,174
.db 229,250
.db 12,179
.db 187,243
.db 44,231
tableend:
.db 76,48

Programming the AVR Microcontrollers in Machine Language

AVR
<< Prev | Ring Hub | Join | Rate| Next
>>
© WebRing Inc. Search

Atmel AVR From Wikipedia, the free encyclopedia (Redirected

from Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing,
intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still
be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language
http://avr-asm.tripod.com/avr222.html (1 of 2)1/20/2009 8:45:45 PM
16 BIT MATH (AVR 202)

http://avr-asm.tripod.com/avr222.html (2 of 2)1/20/2009 8:45:45 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

7 BIT FAST FOURIER TRANSFORMATION

HOME
RETRO_DAN
This is an attempt to provide some FFT-math to the AVR
ASM FORUM community. Code has been tested with AVR-Studio4.
ASM MATH Works fine! FFT-Output is about 7 bits accurate.
TUTORIAL #1
******************
TUTORIAL #2 Known limitations and problems:
TUTORIAL #3 The code assumes input Data to be in the range -127
($81)...+127($FF).
MATH 200
MATH 200b Input-data is organized in SRAM as
Data1LowByte,Data1HighByte,
MATH 201 Data2LowByte,Data2HighByte,
MATH 202 Data3LowByte,Data3HighByte,....
MATH 32X
The FFT uses "in-place" operations and produces the
MATH YX following output:
DIV16 XX
Re(f0)LowByte,Re(f0HighByte),
DIV 24 24 Im(f0)LowByte,Im(f0HighByte),
DIV 3216 Re(f1)LowByte,Re(f1HighByte),
Im(f1)LowByte,Im(f1HighByte),....
FLOAT 128
SQRT16 Thus for n=128 data points (at the moment this is the
maximum), we get 64 frequency Data points.
MATH 202 CPU time for different FFT-lengths:
MATH 202 n=32 T=4,05ms
n=64 T=9,3ms
DEC ASCII
n=128 T=20,95ms
INT ASCII
**************************
HX2ASC
Things to do:
AVG8 222 1) I hope to find some inspiration on the scaling issue
FFT7 (to allow greater input range).
2) The loop-counters are still 8bit only, so these
COPY 102 would need to be 16bit to get longer FFTs working.
LPM 108 At the moment 64 frequency bins represent maximum
resolution.
EPROM 100 3) Include amplitude calculation, because most people
SER EPROM just want to know amplitude vs. frequency and nothing more.
DFLASH AT45
FLASH CARD ;
*************************************************************
VFX SMIL
;* FFT-Programm für bis zu 128
VFX MEM Datenpunkte *
SORT 220 ;* reelle Eingangsdaten werden "in place"
transformiert *
CRC 236 ;* 128 Datenpunkte ergeben 64 Real/Imaginär-
XMODEM REC Datenpaare *
;* Programmiert von niels laugwitz für avr-
UART 304 Mikrocontroller *
UART 305 ;
*************************************************************
UART 128
;
UART BUFF ;.device ATmega8
.include "m8def.inc" ;Lade die Registerdefinitionen
USB 232
für AT-Mega8
AVR ISP .DEF temprL = r2
ISP 2313 .def temprH = r3
.DEF tempiL = r4
ISP 1200 .def tempiH = r5
AVR SPI .DEF i1 = r2 ;Benutzt in for_Schleife_i
.def i2 = r3 ;Benutzt in for_Schleife_i
I2C 300 .DEF i3 = r4 ;Benutzt in for_Schleife_i
I2C 302 .def i4 = r5 ;Benutzt in for_Schleife_i
.def sortierzeiger=r0;
I2C TWI26
.def nullwert=r6
I2C/TWI 128 .def jjende=r7
I2C/TWI AT8 .def data1 = R8
.def data2 =R9
DALLAS-1W .def data3 =R10
DALLAS CRC .def data4 =R11
.def wrL=r12
ETHNET 8019 .def wrH=r13
TEA .def wiL=r14
.def wiH=r15
ADC 128 .DEF temp =r16
ADC 10B .DEF ii =r17
.DEF jj =r18
ADC 400
.DEF mmax =r19
ADC 401 .DEF j =r20
THERM 232 .DEF istep=r21
.def i =r22
IRD 410 .DEF m =r23
LCD HD44 .def zaehler=r24
.DEF tmp_lo =r18 ;Benutzt in for_Schleife_i
LCD 2313 .DEF tmp_hi =r19 ;Benutzt in for_Schleife_i
LCD44 2313
.set nn2 =128 ;Anzahl der Datenpunkte (FFT-
KBD 240 Länge)
MUX 242 ;8 =< nn2 =< 128
.equ h1r_lo =$60
KBD PS2
.equ h1r_hi =$61
KBD PC/128 .equ h1i_lo =$62
PS2 EMU .equ h1i_hi =$63
.equ h2r_lo =$64
BOOT MG8 .equ h2r_hi =$65
BOOT DR8 .equ h2i_lo =$66
.equ h2i_hi =$67
ALM CLK .equ sramstart = $0080
CLOCK 8564
.org $0000
90 DAYS
rjmp main ;reset
DELAYS .include "avr201.asm"
CALL ID
schleife_jj_body:
DTMF 314 ;Berechnung der Indexe i und j:
PWM 6CH mov i,m
mul jj,istep ;r0 := jj*istep
PWM 10K mov i,r0
ENCODE add i,m ;i:=m+jj*istep
mov temp,i
STH-11 add temp,mmax
ATMEL CORP mov j,temp ;j:=i+mmax
;Hole data[j] und data[j+1] aus dem SRAM
AVR
ldi XH,0
BUTTERFLY ldi XL,sramstart
AVR BOOK add XL,j
adc XH,nullwert ;da das Array Data als 16bit-Werte
abgespeichert ist,
add XL,j ;muss der Index verdoppelt werden.
adc XH,nullwert
ld data1,X+ ;hole Data[j]low-byte
ld data2,X+ ;hole Data[j]High-byte
ld data3,X+ ;Hole Data[j+1]low-Byte
ld data4,X ;hole Data[j+1]High-Byte
;Berechne tempr und tempi mehrere Multiplikationen
erfordern
;etwas platz in den oberen registern. Im Moment
brauchen wir die
; nicht: Also ab auf den Stack!
push r23
push r22
push r21
push r20
push r19
push r18
push r17
push r16
;Berechne tempr
movw r21:r20,wrh:wrl
movw r23:r22,data2:data1
rcall muls16x16_32 ;tempr:=wr*data[j] (16bit signed)
MOV temprH,r18 ;we take just the middle-result-
bytes
MOV temprL,r17
movw r21:r20,wih:wil
movw r23:r22,data4:data3
rcall muls16x16_32 ;tempi:=wi*data[j+1] (16bit signed)
MOV tempiH,r18 ;we take just the middle-result-
bytes
MOV tempiL,r17
sub temprL,tempiL
sbc temprH,tempiH ;tempr := wr*data[j]-wi*data[j
+1]
;Berechne tempi
push temprL
push temprH
movw r21:r20,wrh:wrl
movw r23:r22,data4:data3
rcall muls16x16_32 ;tempr:=wr*data[j+1] (16bit
signed)
MOV temprH,r18 ;we take just the middle-result-
bytes
MOV temprL,r17
movw r21:r20,wih:wil
movw r23:r22,data2:data1
rcall muls16x16_32 ;tempi:=wi*data[j] (16bit signed)
MOV tempiH,r18 ;we take just the middle-result-
bytes
MOV tempiL,r17
add tempiL,temprL
adc tempiH,temprH ;tempi := wr*data[j+1]+wi*data
[j]
pop temprH
pop temprL
pop r16
pop r17
pop r18
pop r19
pop r20
pop r21
pop r22
pop r23
;multiplikationen beendet, Stack und Register wieder in
Ordnung

;Hole data[i] aus dem SRAM

ldi XH,0
ldi XL,sramstart
add XL,i
adc XH,nullwert
add XL,i
adc XH,nullwert
ld data3,X+ ;hole Data[i]Low-Byte
ld data4,X ;Hole Data[i]high-Byte
;data[j]:=data[i]-tempr
movw data2:data1, data4:data3
sub data1,temprL
sbc data2,temprH
ldi XH,0
ldi XL,sramstart
add XL,j
adc XH,nullwert
add XL,j
adc XH,nullwert
st X+,data1
st X,data2
;Hole data[i+1] aus dem SRAM
ldi XH,0
ldi XL,sramstart
add XL,i
adc XH,nullwert
add XL,i
adc XH,nullwert
adiw XH:XL,2
ld data3,X+ ;hole Data[i+1]low-Byte
ld data4,X ;Hole Data[i+1]high-Byte
;data[j+1]:=data[i+1]-tempi
movw data2:data1, data4:data3
sub data1,tempiL
sbc data2,tempiH
ldi XH,0
ldi XL,sramstart
add XL,j
adc XH,nullwert
add XL,j
adc XH,nullwert
adiw XH:XL,2
st X+,data1
st X,data2
;data[i+1]:=data[i+1]+tempi
add data3,tempiL
adc data4,tempiH
ldi XH,0
ldi XL,sramstart
add XL,i
adc XH,nullwert
add XL,i
adc XH,nullwert
adiw XH:XL,2
st X+,data3
st X,data4
;Hole data[i] aus dem SRAM
ldi XH,0
ldi XL,sramstart
add XL,i
adc XH,nullwert
add XL,i
adc XH,nullwert
ld data3,X+ ;hole Data[i]low-Byte
ld data4,X ;Hole Data[i]high-Byte
;data[i]:=data[i]+tempr
add data3,temprL
adc data4,temprH
ldi XH,0
ldi XL,sramstart
add XL,i
adc XH,nullwert
add XL,i
adc XH,nullwert
st X+,data3
st X,data4
ret ;Rücksprung zur Schleife_jj
;****************************
;****** HAUPTPROGRAMM *******
;****************************
main:
;initialisieren des Stacks
ldi r16,high(RAMEND)
out spH,r16
ldi r16,low(RAMEND)
out spl,r16
sei
;Kopieren der Test-Daten ins SRAM
;Testdaten werden als 16-bit-signed abgespeichert.
;Die FFT ergibt ebenfalls 16-bit Daten,
;davon sind aber nur ca. 7 bit relevant.
ldi ZH,high(2*testdata)
ldi ZL, low(2*testdata)
clr i
blockkopieren: ;Das Kopieren der Werte erspart mir
eine
;butterfly-sort zu programmieren, simple
stupid!
LPM temp,Z+ ;Lade Werte aus der Ursprungstabelle
testdata
push ZH
push ZL
ldi ZH,high(2*speicherorte_128_werte)
ldi ZL, low(2*speicherorte_128_werte)
add ZL,i
adc ZH,nullwert
lpm sortierzeiger,Z
pop ZL
pop ZH
ldi XH,0
ldi XL,sramstart
add XL,sortierzeiger
adc XH,nullwert
add XL,sortierzeiger
adc XH,nullwert
sbrc temp,7 ;wenn temp negativ, dann
dec nullwert ;setze register nullwert ausnahmsweise
auf $FF
st X+,temp ;speichere lower-Byte zuerst
st X,nullwert ;Highbyte (enthält zunächst nur das
Vorzeichen)
;speichere alle Daten umsortiert im SRAM
clr nullwert ;setze Nullwert wieder auf Null!
inc i
cpi i,nn2
brne blockkopieren
;nun sind die daten für die FFT umsortiert und stehen
im SRAM ab
;Adresse (sramstart+2)=$0082. Für Eigene Anwendungen
sollten die Daten
;von Anfang an nach der Sortiertabelle
"speicherorte_XX_werte" geordnet
;werden. Die Werte sind im SRAM abgelegt als 16 bit
signed integer!
;dw = LOW:HIGH = value:sign
;****************************************
;hier beginnt die eigentliche FFT
ldi mmax,2
while_schleife_start:

cpi mmax,nn2 ;nn2=64

brlo while_schleife_body ;while nn2>mmax do
while_schleife_body
rjmp while_schleife_ende ;ende der while-Schleife
erreicht

while_schleife_body:
mov istep,mmax
lsl istep ;istep:=2*mmax
clr ii ;ii:=0
for_schleife_ii_start: ;for ii=1 to (mmax div 2)
inc ii
mov m,ii
lsl m ;m:=2*ii
dec m ;m:=2*ii-1
ldi temp,nn2 ;nn2=64
sub temp,m ;nn2-m
mov dd8u,temp
mov dv8u,istep
rcall div8u ;Divisionsroutine
;.def drem8u =r15 ;remainder
;.def dres8u =r24 ;result
;.def dd8u =r24 ;dividend
;.def dv8u =r25 ;divisor
mov jjende,dres8u ;jjende:=nn2-m div istep
clr jj ;jj:=0 Initialisierung für
Schleife
;Nun holen wir die Cosinuswerte
ldi ZH,high(2*cosinetab)
ldi ZL, low(2*cosinetab)
ldi zaehler,nn2
mov temp,mmax
lsr temp
pp: lsr zaehler
lsr temp
brne pp
mov temp,ii
dec temp
mul temp,zaehler
add ZL,r0
adc ZH,r1
add ZL,r0 ;addition des pointers doppelt wegen
adc ZH,r1 ;2Byte pro Tabelleneintrag
lpm wrL,Z+ ;jetzt haben wir wrL(ow)
lpm wrH,Z ;jetzt haben wir wrH(igh)
;Nun holen wir die Sinuswerte
ldi ZH,high(2*sinetab)
ldi ZL, low(2*sinetab)
ldi zaehler,nn2
mov temp,mmax
lsr temp
pq: lsr zaehler
lsr temp
brne pq
mov temp,ii
dec temp
mul temp,zaehler
add ZL,r0
adc ZH,r1
add ZL,r0 ;Addition des Pointer-Werts doppelt
wegen
adc ZH,r1 ;2Byte pro Tabelleneintrag
lpm wiL,Z+ ;jetzt haben wir wiL(ow)
lpm wiH,Z ;jetzt haben wir wiH(igh)
for_schleife_jj_start:
rcall Schleife_jj_body ;damit die Schleife mit
einer branch-instruktion
;abgeschlossen werden kann,
wird die eigentliche
;Abarbeitungsroutine mit rcall
aufgerufen.
;(Problem ist die
Sprungreichweite von brsh)
inc jj
cp jjende,jj
brsh for_schleife_jj_start
;ende der jj-Schleife
mov temp,mmax
lsr temp ;iiende:=mmax div 2
cp ii,temp
brlo for_schleife_ii_start
;hier ist das ende der for_schleife_ii
mov mmax,istep
rjmp while_schleife_start
While_schleife_ende:
; Die FFTransformation ist geschafft! Jetzt muß nur
noch richtig
; sortiert werden, da Inputdaten reelle Werte waren.
ldi i,1 ;Initialisierung von i
for_schleife_i_anfang:
inc i ;for i:=2 to ((nn2 div 4)+1)
;Berechnung der Indizes i1..i4
mov i1,i
lsl i1
dec i1 ; i1:=i+i-1
mov i2,i1
inc i2 ; i2:= i1+1
ldi temp,nn2
sub temp,i2
subi temp,-3
mov i3,temp ; i3:=nn2-i2+3
mov i4,i3
inc i4 ; i4:=i3+1
;Nun holen wir die wr
ldi ZH,high(2*cosinetab)
ldi ZL, low(2*cosinetab)
mov temp,i
dec temp
lsl temp
add ZL,temp
adc ZH,nullwert
lpm wrL,Z+ ;jetzt haben wir wrL(ow)
lpm wrH,Z ;jetzt haben wir wrH(igh)
;Nun holen wir die wi
ldi ZH,high(2*sinetab)
ldi ZL, low(2*sinetab)
mov temp,i
dec temp
lsl temp
add ZL,temp
adc ZH,nullwert
lpm wiL,Z+ ;jetzt haben wir wiL(ow)
lpm wiH,Z ;jetzt haben wir wiH(igh)
rcall for_schleife_calculus ;auch hier
Unterprogramm, damit die
;Schleife mit brlo enden
kann.
;test ob FOR_Schleife schon fertig
ldi temp,nn2
lsr temp
lsr temp
inc temp
cp i,temp
brlo for_schleife_i_anfang
for_schleife_i_exit: ;Umsortieren ist
geschafft.
nop
;here comes compensation for DC-Value.
; if DC is not important, then just skip the following
routine
rcall DC_compensation
;
***********************************************************
;now the fft is done.
;data contains real-part and imaginary-part as 16bit
values
;arranged in pairs first real, then imaginary
;
***********************************************************
ende: ;Das Werk ist vollbracht!
rjmp ende ;SCHLUSS! ENDE! AUS!

for_schleife_calculus:
;***** Berechnung von h1r und h2i
;hole Data[i1] in reg. data2:data1
ldi XH,0
ldi XL,sramstart
add XL,i1
adc XH,nullwert
add XL,i1
adc XH,nullwert
ld data1,X+ ;lower-Byte zuerst
ld data2,X ;Highbyte
;hole Data[i3] in register-pair data4:data3
ldi XH,0
ldi XL,sramstart
add XL,i3
adc XH,nullwert
add XL,i3
adc XH,nullwert
ld data3,X+ ;lower-Byte zuerst
ld data4,X ;Highbyte
asr data2
ror data1 ;data[i1]:=data[i1]/2
asr data4
ror data3 ;data[i3]:=data[i3]/2
movw tmp_hi:tmp_lo,data2:data1
add tmp_lo,data3
adc tmp_hi,data4 ;h1r:=data[i1]+data[i3]
sts h1r_lo,tmp_lo
sts h1r_hi,tmp_hi ;save h1r to sram-location
movw tmp_hi:tmp_lo,data2:data1
sub tmp_lo,data3
sbc tmp_hi,data4 ;h1r:=-1*(data[i1]-data[i3])
com tmp_lo
com tmp_hi
ldi temp,1
add tmp_lo,temp
adc tmp_hi,nullwert
sts h2i_lo,tmp_lo
sts h2i_hi,tmp_hi ;save h1r to sram-location
;***** Berechnung von h1i und h2r
;hole Data[i2] in reg. data2:data1
ldi XH,0
ldi XL,sramstart
add XL,i2
adc XH,nullwert
add XL,i2
adc XH,nullwert
ld data1,X+ ;lower-Byte zuerst
ld data2,X ;Highbyte
;hole Data[i4] in register-pair data4:data3
ldi XH,0
ldi XL,sramstart
add XL,i4
adc XH,nullwert
add XL,i4
adc XH,nullwert
ld data3,X+ ;lower-Byte zuerst
ld data4,X ;Highbyte
asr data2
ror data1 ;data[i2]:=data[i2]/2
asr data4
ror data3 ;data[i4]:=data[i4]/2
movw tmp_hi:tmp_lo,data2:data1
sub tmp_lo,data3
sbc tmp_hi,data4
sts h1i_lo,tmp_lo
sts h1i_hi,tmp_hi ;save h1i to sram-location
add data1,data3
adc data2,data4
sts h2r_lo,data1
sts h2r_hi,data2 ;save h2r to sram-location
push r23
push r22
push r21
push r20
push r19
push r18
push r17
push r16
; **** Data[i1]:=h1r+wr*h2r-wi*h2i
movw R21:R20,wrh:wrl
lds r23,h2r_hi
lds r22,h2r_lo
rcall muls16x16_32
mov data2,r18
mov data1,r17
movw R21:R20,wih:wil
lds r23,h2i_hi
lds r22,h2i_lo
rcall muls16x16_32
sub data1,r17
sbc data2,r18
lds r18,h1r_hi
lds r17,h1r_lo
add data1,r17
adc data2,r18
ldi XH,0
ldi XL,sramstart
add XL,i1
adc XH,nullwert
add XL,i1
adc XH,nullwert
st X+,data1
st X ,data2
; **** Data[i2]:=h1i+wr*h2i+wi*h2r
movw R21:R20,wrh:wrl
lds r23,h2i_hi
lds r22,h2i_lo
rcall muls16x16_32
mov data2,r18
mov data1,r17
movw R21:R20,wih:wil
lds r23,h2r_hi
lds r22,h2r_lo
rcall muls16x16_32
add data1,r17
adc data2,r18
lds r18,h1i_hi
lds r17,h1i_lo
add data1,r17
adc data2,r18
ldi XH,0
ldi XL,sramstart
add XL,i2
adc XH,nullwert
add XL,i2
adc XH,nullwert
st X+,data1
st X ,data2
; **** Data[i3]:=h1r-wr*h2r+wi*h2i
movw R21:R20,wih:wil
lds r23,h2i_hi
lds r22,h2i_lo
rcall muls16x16_32
mov data2,r18
mov data1,r17
movw R21:R20,wrh:wrl
lds r23,h2r_hi
lds r22,h2r_lo
rcall muls16x16_32
sub data1,r17
sbc data2,r18
lds r18,h1r_hi
lds r17,h1r_lo
add data1,r17
adc data2,r18
ldi XH,0
ldi XL,sramstart
add XL,i3
adc XH,nullwert
add XL,i3
adc XH,nullwert
st X+,data1
st X ,data2
; **** Data[i4]:=-h1i+wr*h2i+wi*h2r
movw R21:R20,wrh:wrl
lds r23,h2i_hi
lds r22,h2i_lo
rcall muls16x16_32
mov data2,r18
mov data1,r17
movw R21:R20,wih:wil
lds r23,h2r_hi
lds r22,h2r_lo
rcall muls16x16_32
add data1,r17
adc data2,r18
lds r18,h1i_hi
lds r17,h1i_lo
sub data1,r17
sbc data2,r18
ldi XH,0
ldi XL,sramstart
add XL,i4
adc XH,nullwert
add XL,i4
adc XH,nullwert
st X+,data1
st X ,data2
pop r16
pop r17
pop r18
pop r19
pop r20
pop r21
pop r22
pop r23
ret ;ende der umfangreichen Berechnungen in
For_schleife_i

DC_compensation:
lds data1,sramstart+2
lds data2,sramstart+3
lds data3,sramstart+4
lds data4,sramstart+5
movw tmp_hi:tmp_lo,data2:data1
add data1,data3
adc data2,data4
sub tmp_lo,data3
sbc tmp_hi,data4
sts sramstart+2,data1
sts sramstart+3,data2
sts sramstart+4,tmp_lo
sts sramstart+5,tmp_hi
ret
;ende DC-kompensation

sinetab: ;Jede Tabelle 128 Werte = Anzahl

Datenpunkte
.dw 0, 13, 25, 38, 50, 62, 74, 86, 98, 109,
121, 132, 142, 152, 162, 172
.dw 181, 190, 198, 206, 213, 220, 226, 231, 237, 241,
245, 248, 251, 253, 255, 256
cosinetab: ;überlappt mit Sinustabelle um
Speicherplatz sparen
.dw 256, 256, 255, 253, 251, 248, 245, 241, 237, 231,
226, 220, 213, 206, 198, 190
.dw 181, 172, 162, 152, 142, 132, 121, 109, 98, 86,
74, 62, 50, 38, 25, 13
.dw 0, -13, -25, -38, -50, -62, -74, -86, -98,-109,-
121,-132,-142,-152,-162,-172
.dw -181,-190,-198,-206,-213,-220,-226,-231,-237,-241,-
245,-248,-251,-253,-255,-256
.dw -256,-256,-255,-253,-251,-248,-245,-241,-237,-231,-
226,-220,-213,-206,-198,-190
.dw -181,-172,-162,-152,-142,-132,-121,-109, -98, -86, -
74, -62, -50, -38, -25, -13
.dw 0, 13, 25, 38, 50, 62, 74, 86, 98, 109,
121, 132, 142, 152, 162, 172
.dw 181, 190, 198, 206, 213, 220, 226, 231, 237, 241,
245, 248, 251, 253, 255, 256

sinetab_64: ;Jede Tabelle 64 Werte = Anzahl

Datenpunkte
.dw 0, 25, 50, 74, 98, 121, 142,162
.dw 181,198,213,226,237,245,251,255
cosinetab_64: ;überlappt mit Sinustabelle um
Speicherplatz sparen
.dw 256, 255, 251, 245, 237, 226, 213, 198
.dw 181, 162, 142, 121, 98, 74, 50, 25
.dw 0, -25, -50, -74, -98,-121,-142,-162
.dw -181,-198,-213,-226,-237,-245,-251,-255
.dw -256,-255,-251,-245,-237,-226,-213,-198
.dw -181,-162,-142,-121, -98, -74, -50, -25
.dw 0, 25, 50, 74, 98, 121, 142,162
.dw 181,198,213,226,237,245,251,255

sinetab_32: ;Jede Tabelle 32 Werte = Anzahl

Datenpunkte
.dw 0, 50, 98, 142
.dw 181, 213, 237, 251
cosinetab_32: ;überlappt mit Sinustabelle um
Speicherplatz sparen
.dw 256, 251, 237, 213
.dw 181, 142, 98, 50
.dw 0, -50, -98,-142
.dw -181,-213,-237,-251
.dw -256,-251,-237,-213
.dw -181,-142, -98, -50
.dw 0, 50, 98, 142
.dw 181, 213, 237, 251

testdata: ;128 Datenpunkte mit 7bit + sign !!

.db 1,2,3,4,5,6,7,8
.db 9,10,11,12,13,14,15,16
.db 17,18,19,20,21,22,23,24
.db 25,25,27,28,29,30,31,32
.db 33,34,35,36,37,38,39,40
.db 41,42,43,44,45,46,47,48
.db 49,50,51,52,53,54,55,56
.db 57,58,59,60,61,62,63,64
.db 65,66,67,68,69,70,71,72
.db 73,74,75,76,77,78,79,80
.db 81,82,83,84,85,86,87,88
.db 89,90,91,92,93,94,95,96
.db 97,98,99,100,101,102,103,104
.db 105,106,107,108,109,110,111,112
.db 113,114,115,116,117,118,119,120
.db 121,122,123,124,125,126,127,0

speicherorte_128_werte:
.db 1,2
.db 65,66
.db 33,34
.db 97,98
.db 17,18
.db 81,82
.db 49,50
.db 113,114
.db 9,10
.db 73,74
.db 41,42
.db 105,106
.db 25,26
.db 89,90
.db 57,58
.db 121,122
.db 5,6
.db 69,70
.db 37,38
.db 101,102
.db 21,22
.db 85,86
.db 53,54
.db 117,118
.db 13,14
.db 77,78
.db 45,46
.db 109,110
.db 29,30
.db 93,94
.db 61,62
.db 125,126
.db 3,4
.db 67,68
.db 35,36
.db 99,100
.db 19,20
.db 83,84
.db 51,52
.db 115,116
.db 11,12
.db 75,76
.db 43,44
.db 107,108
.db 27,28
.db 91,92
.db 59,60
.db 123,124
.db 7,8
.db 71,72
.db 39,40
.db 103,104
.db 23,24
.db 87,88
.db 55,56
.db 119,120
.db 15,16
.db 79,80
.db 47,48
.db 111,112
.db 31,32
.db 95,96
.db 63,64
.db 127,128

speicherorte_64_werte: ;Sortiertabelle für 64

Werte
.db 1, 2, 33, 34
.db 17, 18, 49, 50
.db 9, 10, 41, 42
.db 25, 26, 57, 58
.db 5, 6, 37, 38
.db 21, 22, 53, 54
.db 13, 14, 45, 46
.db 29, 30, 61, 62
.db 3, 4, 35, 36
.db 19, 20, 51, 52
.db 11, 12, 43, 44
.db 27, 28, 59, 60
.db 7, 8, 39, 40
.db 23, 24, 55, 56
.db 15, 16, 47, 48
.db 31, 32, 63, 64
;*********************

speicherorte_32_werte: ;Sortiertabelle für 32

Werte
.db 1, 2, 17, 18
.db 9, 10, 25, 26
.db 5, 6, 21, 22
.db 13, 14, 29, 30
.db 3, 4, 19, 20
.db 11, 12, 27, 28
.db 7, 8, 23, 24
.db 15, 16, 31, 32

;
******************************************************************************
;*
;* FUNCTION
;* muls16x16_32
;* DECRIPTION
;* Signed multiply of two 16bits numbers with 32bits
result.
;* USAGE
;* r19:r18:r17:r16 = r23:r22 * r21:r20
;* STATISTICS
;* Cycles : 19 + ret
;* Words : 15 + ret
;* Register usage: r0:r1 and r6 and r16 to r23 (11
registers)
;* NOTE
;* The routine is non-destructive to the operands.
;*
;
******************************************************************************

muls16x16_32:
; clr r6
muls r23, r21 ; (signed)ah * (signed)bh
movw r19:r18, r1:r0
mul r22, r20 ; al * bl
movw r17:r16, r1:r0
mulsu r23, r20 ; (signed)ah * bl
sbc r19, r6
add r17, r0
adc r18, r1
adc r19, r6
mulsu r21, r22 ; (signed)bh * al
sbc r19, r6
add r17, r0
adc r18, r1
adc r19, r6
ret

;
***************************************************************************
;*
;* "div8u" - 8/8 Bit Unsigned Division
;*
;* This subroutine divides the two register variables
"dd8u" (dividend) and
;* "dv8u" (divisor). The result is placed in "dres8u"
and the remainder in
;* "drem8u".
;*
;* Number of words :66 + return
;* Number of cycles :50/58/66 (Min/Avg/Max) + return
;* Low registers used :1 (drem8u)
;* High registers used :2 (dres8u/dd8u,dv8u)
;*

http://avr-asm.tripod.com/fft7.html (1 of 2)1/20/2009 8:46:26 PM

16 BIT MATH (AVR 202)

;
***************************************************************************

;***** Subroutine Register Variables

.def drem8u =r15 ;remainder

.def dres8u =r24 ;result
.def dd8u =r24 ;dividend
.def dv8u =r25 ;divisor

;***** Code

div8u: sub drem8u,drem8u ;clear remainder and

carry

rol dd8u ;shift left dividend

rol drem8u ;shift dividend into remainder
sub drem8u,dv8u ;remainder = remainder - divisor
brcc d8u_1 ;if result negative
add drem8u,dv8u ; restore remainder
clc ; clear carry to be shifted into
result
rjmp d8u_2 ;else
d8u_1: sec ; set carry to be shifted into
result

d8u_2: rol dd8u ;shift left dividend

rol drem8u ;shift dividend into remainder
sub drem8u,dv8u ;remainder = remainder - divisor
brcc d8u_3 ;if result negative
add drem8u,dv8u ; restore remainder
clc ; clear carry to be shifted into
result
rjmp d8u_4 ;else
d8u_3: sec ; set carry to be shifted into
result

d8u_4: rol dd8u ;shift left dividend

rol drem8u ;shift dividend into remainder
sub drem8u,dv8u ;remainder = remainder - divisor
brcc d8u_5 ;if result negative
add drem8u,dv8u ; restore remainder
clc ; clear carry to be shifted into
result
rjmp d8u_6 ;else
d8u_5: sec ; set carry to be shifted into
result

d8u_6: rol dd8u ;shift left dividend

rol drem8u ;shift dividend into remainder
sub drem8u,dv8u ;remainder = remainder - divisor
brcc d8u_7 ;if result negative
add drem8u,dv8u ; restore remainder
clc ; clear carry to be shifted into
result
rjmp d8u_8 ;else
d8u_7: sec ; set carry to be shifted into
result

d8u_8: rol dd8u ;shift left dividend

rol drem8u ;shift dividend into remainder
sub drem8u,dv8u ;remainder = remainder - divisor
brcc d8u_9 ;if result negative
add drem8u,dv8u ; restore remainder
clc ; clear carry to be shifted into
result
rjmp d8u_10 ;else
d8u_9: sec ; set carry to be shifted into
result

d8u_10: rol dd8u ;shift left dividend

rol drem8u ;shift dividend into remainder
sub drem8u,dv8u ;remainder = remainder - divisor
brcc d8u_11 ;if result negative
add drem8u,dv8u ; restore remainder
clc ; clear carry to be shifted into
result
rjmp d8u_12 ;else
d8u_11: sec ; set carry to be shifted into
result

d8u_12: rol dd8u ;shift left dividend

rol drem8u ;shift dividend into remainder
sub drem8u,dv8u ;remainder = remainder - divisor
brcc d8u_13 ;if result negative
add drem8u,dv8u ; restore remainder
clc ; clear carry to be shifted into
result
rjmp d8u_14 ;else
d8u_13: sec ; set carry to be shifted into
result

d8u_14: rol dd8u ;shift left dividend

rol drem8u ;shift dividend into remainder
sub drem8u,dv8u ;remainder = remainder - divisor
brcc d8u_15 ;if result negative
add drem8u,dv8u ; restore remainder
clc ; clear carry to be shifted into
result
rjmp d8u_16 ;else
d8u_15: sec ; set carry to be shifted into
result

d8u_16: rol dd8u ;shift left dividend

ret

Programming the AVR Microcontrollers in Machine Language

AVR
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected

from Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing,
intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still
be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language

http://avr-asm.tripod.com/fft7.html (2 of 2)1/20/2009 8:46:26 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

BLOCK COPY (AVR 102)

HOME
RETRO_DAN
;**** A P P L I C A T I O N N O T E A V R 1 0 2
ASM FORUM ************************
ASM MATH ;*
;* Title: Block Copy Routines
TUTORIAL #1
;* Version: 1.1
TUTORIAL #2 ;* Last updated: 97.07.04
TUTORIAL #3 ;* Target: AT90Sxx1x (Devices with SRAM)
;*
MATH 200 ;* Support E-mail: avr@atmel.com
MATH 200b ;*
;* DESCRIPTION
MATH 201 ;* This Application Note shows how to copy a block of
MATH 202 data from Program
;* memory to SRAM and from one SRAM area to another
MATH 32X
;*
MATH YX ;
***************************************************************************
DIV16 XX
DIV 24 24 .include "8515def.inc"
DIV 3216
rjmp RESET ;reset handle
FLOAT 128
SQRT16 ;
***************************************************************************
MATH 202 ;*
MATH 202 ;* "flash2ram"
;*
DEC ASCII
;* This subroutine copies a block of data from the
INT ASCII Program memory (Flash)
;* to the internal SRAM. The following parameters must
HX2ASC
be set up prior to
AVG8 222 ;* calling the subroutine:
FFT7 ;* Z-pointer: Flash block start address x 2 (WORD
oriented code segment)
COPY 102 ;* Y-pointer: ram block start address
LPM 108 ;* romsize: block size
;*
EPROM 100 ;* Number of words :5 + return
SER EPROM ;* Number of cycles :10 x block size + return
;* Low Registers used :1 (r0)
DFLASH AT45
;* High Registers used :1 (flashsize)
FLASH CARD ;* Pointers used :Y, Z
;*
VFX SMIL
;
VFX MEM ***************************************************************************
SORT 220
;***** Subroutine Register variables
CRC 236
XMODEM REC .def flashsize=r16 ;size of block to
be copied
UART 304
UART 305 ;***** Code
UART 128
flash2ram:
UART BUFF lpm ;get constant
st Y+,r0 ;store in SRAM and
USB 232
increment Y-pointer
AVR ISP adiw ZL,1 ;increment Z-pointer
ISP 2313 dec flashsize
brne flash2ram ;if not end of table, loop
ISP 1200 more
AVR SPI ret
I2C 300
I2C 302 ;
***************************************************************************
I2C TWI26
;*
I2C/TWI 128 ;* "ram2ram"
I2C/TWI AT8 ;*
;* This subroutine copies one block of data from one
DALLAS-1W SRAM area to another.
DALLAS CRC ;* The following parameters must be set up prior to
calling the subroutine:
ETHNET 8019 ;*
TEA ;* Z-pointer: start of RAM area to copy from
;* Y-pointer: start of RAM area to copy to
ADC 128 ;* ramsize : size of block to copy
ADC 10B ;*
;* Number of words :4 + return
ADC 400
;* Number of cycles :6 x block size + return
ADC 401 ;* Low Registers used :1 (ramtemp)
THERM 232 ;* High Registers used :1 (ramsize)
;* Pointers used :Y, Z
IRD 410 ;*
LCD HD44 ;
***************************************************************************
LCD 2313
LCD44 2313 ;***** Subroutine Register variables
KBD 240 .def ramtemp =r1 ;temporary storage
MUX 242 register
.def ramsize =r16 ;size of block to
KBD PS2
be copied
KBD PC/128
PS2 EMU ;***** Code

BOOT MG8 ram2ram:

BOOT DR8 ld ramtemp,Z+ ;get data from BLOCK1
st Y+,ramtemp ;store data to BLOCK2
ALM CLK dec ramsize ;
CLOCK 8564 brne ram2ram ;if not done, loop more
ret
90 DAYS
DELAYS ;
****************************************************************************
CALL ID
;*
DTMF 314 ;* Test Program
PWM 6CH ;*
;* This program copies 20 bytes of data from the
PWM 10K Program memory to the SRAM
ENCODE ;* area beginning at location BLOCK1. It then makes a
second copy to the
STH-11 ;* area beginning at location BLOCK2.
ATMEL CORP ;*
;
AVR
****************************************************************************
BUTTERFLY
AVR BOOK .equ BLOCK1 =$60 ;start address of
SRAM array #1
.equ BLOCK2 =$80 ;start address of
SRAM array #2

;***** Main Program Register variables

.def temp =r16 ;temporary storage

variable

;***** Code

RESET:
ldi temp,low(RAMEND)
out SPL,temp ;init Stack
Pointer
ldi temp,high(RAMEND)
out SPH,temp

;***** Copy 20 bytes ROM -> RAM

ldi ZH,high(F_TABLE*2)
ldi ZL,low(F_TABLE*2);init Z-pointer
ldi YH,high(BLOCK1)
ldi YL,low(BLOCK1) ;init Y-pointer
ldi flashsize,20
rcall flash2ram ;copy 20 bytes

;***** Copy 20 bytes RAM -> RAM

ldi ZH,high(BLOCK1)
ldi ZL,low(BLOCK1) ;init Z-pointer
ldi YH,high(BLOCK2) ;(not necessary in this
specific case)
ldi YL,low(BLOCK2) ;init Y-pointer
ldi ramsize,20
rcall ram2ram ;copy 20 bytes

forever:rjmp forever ;eternal loop

F_TABLE:
.db 0,1 ;start of table (20 bytes)
.db 2,3
.db 4,5
.db 6,7
.db 8,9
.db 10,11
.db 12,13
.db 14,15
.db 16,17
.db 18,19

Programming the AVR Microcontrollers in Machine Language

AVR
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© WebRing Inc. Search

Atmel AVR From Wikipedia, the free encyclopedia (Redirected

from Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing,
intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still
be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language
http://avr-asm.tripod.com/avr102.html (1 of 2)1/20/2009 8:47:00 PM
16 BIT MATH (AVR 202)

http://avr-asm.tripod.com/avr102.html (2 of 2)1/20/2009 8:47:00 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

LOAD PROGRAM MEMORY (AVR 108)

HOME
RETRO_DAN
;**** A P P L I C A T I O N N O T E A V R 1 0 8
ASM FORUM ************************
ASM MATH ;*
;* Title: Load Program Memory
TUTORIAL #1
;* Version: 1.0
TUTORIAL #2 ;* Last updated: 98.02.27
TUTORIAL #3 ;* Target: AT90Sxx1x and higher (Devices with
SRAM)
MATH 200 ;*
MATH 200b ;* Support E-mail: avr@atmel.com
;*
MATH 201 ;* DESCRIPTION
MATH 202 ;* This Application note shows how to use the Load
Program Memory (LPM)
MATH 32X
;* instruction. The App. note loads the string "Hello
MATH YX World" from
;* program memory byte by byte, and puts it onto port B.
DIV16 XX
;*
DIV 24 24 ;
DIV 3216 ***************************************************************************

FLOAT 128
SQRT16 .include "8515def.inc"

MATH 202 .device AT90S8515 ; Specify device

MATH 202
.def temp =r16 ; Define
DEC ASCII
temporary variable
INT ASCII
HX2ASC
start: ldi temp,low(RAMEND)
AVG8 222 out SPL,temp ; Set stack pointer
FFT7 to last internal RAM location
ldi temp,high(RAMEND)
COPY 102 out SPH,temp
LPM 108
ldi temp,$ff
EPROM 100 out PORTB,temp ; Set all pins at
SER EPROM port B high
out DDRB,temp ; Set port B as
DFLASH AT45
output
FLASH CARD
; Load the address of 'message' into the Z
VFX SMIL
register. Multiplies
VFX MEM ; word address with 2 to achieve the byte address,
SORT 220 and uses the
; functions high() and low() to calculate high and
CRC 236 low address byte.
XMODEM REC
ldi ZH,high(2*message) ; Load high part of
UART 304 byte address into ZH
UART 305 ldi ZL,low(2*message) ; Load low part of
byte address into ZL
UART 128
UART BUFF loadbyte:
lpm ; Load byte from
USB 232
program memory into r0
AVR ISP
ISP 2313 tst r0 ; Check if we've
reached the end of the message
ISP 1200 breq quit ; If so, quit
AVR SPI
out PORTB,r0 ; Put the character
I2C 300 onto Port B
I2C 302
rcall one_sec_delay ; A short delay
I2C TWI26
I2C/TWI 128 adiw ZL,1 ; Increase Z
I2C/TWI AT8 registers
rjmp loadbyte
DALLAS-1W
DALLAS CRC
quit: rjmp quit
ETHNET 8019
TEA
one_sec_delay:
ADC 128 ldi r20, 20
ADC 10B ldi r21, 255
ldi r22, 255
ADC 400
delay: dec r22
ADC 401 brne delay
THERM 232 dec r21
brne delay
IRD 410 dec r20
LCD HD44 brne delay
ret
LCD 2313
LCD44 2313
message:
KBD 240 .db "Hello World"
MUX 242 .db 0
KBD PS2
KBD PC/128
PS2 EMU
BOOT MG8
BOOT DR8
ALM CLK
CLOCK 8564
90 DAYS
DELAYS
CALL ID
DTMF 314
Programming the AVR Microcontrollers in Machine Language
PWM 6CH
PWM 10K
AVR
ENCODE
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STH-11 >>
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AVR
BUTTERFLY
AVR BOOK Atmel AVR From Wikipedia, the free encyclopedia (Redirected
from Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing,
intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still
be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language
http://avr-asm.tripod.com/avr108.html (1 of 2)1/20/2009 8:47:33 PM
16 BIT MATH (AVR 202)

http://avr-asm.tripod.com/avr108.html (2 of 2)1/20/2009 8:47:33 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

EPROM STORAGE (AVR 100)

HOME
RETRO_DAN
;**** A P P L I C A T I O N N O T E A V R 1 0 0
ASM FORUM ************************
ASM MATH ;*
;* Title: Accessing the EEPROM
TUTORIAL #1
;* Version: 2.0
TUTORIAL #2 ;* Last updated: 98.06.15
TUTORIAL #3 ;* Target: AT90Sxxxx (All AVR Devices)
;*
MATH 200 ;* Support E-mail: avr@atmel.com
MATH 200b ;*
;* DESCRIPTION
MATH 201 ;* This Application note shows how to read data from
MATH 202 and write data to the
;* EEPROM. Both random access and sequential access
MATH 32X
routines are listed.
MATH YX ;* The code is written for 8515, to modify for
4414,2313,2323... apply the
DIV16 XX
;* following changes:
DIV 24 24 ;* - Remove all entries to EEARH
DIV 3216 ;* - Rename EEARL to EEAR
;*
FLOAT 128 ;* To modify for 1200, apply the changes above, and
SQRT16 change the code
;* as commented inside the routines
MATH 202 ;*
MATH 202 ;*
;
DEC ASCII
***************************************************************************
INT ASCII .include "8515def.inc"
HX2ASC
rjmp RESET ;Reset Handle
AVG8 222
FFT7 ;
***************************************************************************
COPY 102 ;*
LPM 108 ;* EEWrite
;*
EPROM 100 ;* This subroutine waits until the EEPROM is ready to
SER EPROM be programmed, then
;* programs the EEPROM with register variable "EEdwr"
DFLASH AT45
at address "EEawr:EEawr"
FLASH CARD ;*
;* Number of words :1200 ; 5 + return
VFX SMIL
;* :8515 ; 7 + return
VFX MEM ;* Number of cycles :1200 ; 8 + return (if EEPROM is
SORT 220 ready)
;* :8515 ; 11 + return (if EEPROM is
CRC 236 ready)
XMODEM REC ;* Low Registers used :None
;* High Registers used: ;3 (EEdwr,EEawr,EEawrh)
UART 304 ;*
UART 305 ;
***************************************************************************
UART 128
UART BUFF ;***** Subroutine register variables
USB 232
.def EEdwr =r16 ;data byte to write
AVR ISP to EEPROM
ISP 2313 .def EEawr =r17 ;address low byte
to write to
ISP 1200 .def EEawrh =r18 ;address high byte
AVR SPI to write to
I2C 300 ;***** Code
I2C 302
EEWrite:
I2C TWI26
sbic EECR,EEWE ;if EEWE not clear
I2C/TWI 128 rjmp EEWrite ; wait more
I2C/TWI AT8
; out EEAR,EEawr ;output address for 1200,
DALLAS-1W commented out !
DALLAS CRC
; the two following lines must be replaced with the
ETHNET 8019 line above if 1200 is used
TEA out EEARH,EEawrh ;output address high for
8515
ADC 128 out EEARL,EEawr ;output address low for 8515
ADC 10B
ADC 400
out EEDR,EEdwr ;output data
ADC 401 sbi EECR,EEMWE ;set master write enable,
THERM 232 remove if 1200 is used
sbi EECR,EEWE ;set EEPROM Write strobe
IRD 410 ;This instruction takes 4
LCD HD44 clock cycles since
;it halts the CPU for two
LCD 2313 clock cycles
LCD44 2313 ret
KBD 240 ;
MUX 242 ***************************************************************************
;*
KBD PS2
;* EERead
KBD PC/128 ;*
PS2 EMU ;* This subroutine waits until the EEPROM is ready to
be programmed, then
BOOT MG8 ;* reads the register variable "EEdrd" from address
BOOT DR8 "EEardh:EEard"
;*
ALM CLK ;* Number of words :1200 ; 5 + return
CLOCK 8564 ;* :8515 ; 6 + return
;* Number of cycles :1200 ; 8 + return (if EEPROM is
90 DAYS
ready)
DELAYS ;* :8515 ; 9 + return (if EEPROM is
ready)
CALL ID
;* Low Registers used :1 (EEdrd)
DTMF 314 ;* High Registers used: :2 (EEard,EEardh)
PWM 6CH ;*
;
PWM 10K ***************************************************************************
ENCODE
;***** Subroutine register variables
STH-11
ATMEL CORP .def EEdrd =r0 ;result data byte
.def EEard =r17 ;address low to
AVR
read from
BUTTERFLY .def EEardh =r18 ;address high to
AVR BOOK read from

;***** Code

EERead:
sbic EECR,EEWE ;if EEWE not clear
rjmp EERead ; wait more
; out EEAR,EEard ;output address for 1200,
commented out !

; the two following lines must be replaced with the

line above if 1200 is used
out EEARH,EEardh ;output address high for
8515
out EEARL,EEard ;output address low for 8515

sbi EECR,EERE ;set EEPROM Read strobe

;This instruction takes 4
clock cycles since
;it halts the CPU for two
clock cycles
in EEdrd,EEDR ;get data
ret

;
***************************************************************************
;*
;* EEWrite_seq
;*
;* This subroutine increments the EEPROM address by one
and waits until the
;* EEPROM is ready for programming. It then programs
the EEPROM with
;* register variable "EEdwr_s".

;* Number of words :1200 ; 7 + return

;* :8515 ; 10 + return
;* Number of cycles :1200 ; 10 + return (if EEPROM is
ready)
;* :8515 ; 15 + return (if EEPROM is
ready)
;* Low Registers used :None
;* High Registers used: :3 (EEdwr_s,EEwtmp,EEwtmph)
;*
;
***************************************************************************

;***** Subroutine register variables

.def EEwtmp =r24 ;temporary storage

of address low byte
.def EEwtmph =r25 ;temporary storage
of address high byte
.def EEdwr_s =r18 ;data to write

;***** Code

EEWrite_seq:
sbic EECR,EEWE ;if EEWE not clear
rjmp EEWrite_seq ; wait more

; Write sequence for 1200

; in EEwtmp,EEAR ;get address for 1200,
commented out !
; inc EEwtmp ;increment address 1200,
commented out !
; out EEAR,EEwtmp ;output address 1200

; Write sequence for 8515, must be replaced with the

lines above if 1200 is used
in EEwtmp,EEARL ;get address low 8515
in EEwtmph,EEARH ;get address high 8515
adiw EEwtmp,0x01 ;increment address 8515
out EEARL,EEwtmp ;output address 8515
out EEARH,EEwtmph ;output address 8515

out EEDR,EEdwr_s ;output data

sbi EECR,EEMWE ;set master write enable,
remove if 1200 is used
sbi EECR,EEWE ;set EEPROM Write strobe
;This instruction takes 4
clock cycles since
;it halts the CPU for two
clock cycles
ret

;
***************************************************************************
;*
;* EERead_seq
;*
;* This subroutine increments the address stored in
EEAR and reads the
;* EEPROM into the register variable "EEdrd_s".

;* Number of words :1200 ; 5 + return

;* :8515 ; 7 + return
;* Number of cycles :1200 ; 8 + return (if EEPROM is
ready)
;* :8515 ; 11 + return (if EEPROM is
ready)
;* Low Registers used :1 (EEdrd_s)
;* High Registers used: :2 (EErtmp,EErtmph)
;*
;
***************************************************************************

;***** Subroutine register variables

.def EErtmp =r24 ;temporary storage

of low address
.def EErtmph =r25 ;temporary storage
of high address
.def EEdrd_s =r0 ;result data byte

;***** Code

EERead_seq:
sbic EECR,EEWE ;if EEWE not clear
rjmp EERead_seq ; wait more
; The above sequence for EEWE = 0 can be skipped if no
write is initiated.

; Read sequence for 1200

; in EErtmp,EEAR ;get address for 1200,
commented out !
; inc EErtmp ;increment address 1200,
commented out !
; out EEAR,EErtmp ;output address 1200

; Read sequence for 8515, must be replaced with the

lines above if 1200 is used
in EErtmp,EEARL ;get address low 8515
in EErtmph,EEARH ;get address high 8515
adiw EErtmp,0x01 ;increment address 8515
out EEARL,EErtmp ;output address 8515
out EEARH,EErtmph ;output address 8515

sbi EECR,EERE ;set EEPROM Read strobe

;This instruction takes 4
clock cycles since
;it halts the CPU for two
clock cycles
in EEdrd_s,EEDR ;get data
ret

;
****************************************************************************
;*
;* Test/Example Program
;*
;
****************************************************************************

;***** Main Program Register variables

.def counter =r19

.def temp =r20

;***** Code

RESET:
;***** Initialize stack pointer
;* Initialize stack pointer to highest address in
internal SRAM
;* Comment out for devices without SRAM

ldi r16,high(RAMEND) ;High byte only required

if
out SPH,r16 ;RAM is bigger than 256
Bytes
ldi r16,low(RAMEND)
out SPL,r16

;***** Program a random location

ldi EEdwr,$aa
ldi EEawrh,$00
ldi EEawr,$10
rcall EEWrite ;store $aa in EEPROM
location $0010

;***** Read from a random locations

ldi EEardh,$00
ldi EEard,$10
rcall EERead ;read address $10
out PORTB,EEdrd ;output value to Port B

;***** Fill the EEPROM address 1..64 with bit pattern

$55,$aa,$55,$aa,...

ldi counter,63 ;init loop counter

clr temp
out EEARH,temp ;EEARH <- $00
clr temp
out EEARL,temp ;EEAR <- $00 (start address
- 1)

loop1: ldi EEdwr_s,$55

rcall EEWrite_seq ;program EEPROM with $55
ldi EEdwr_s,$aa
rcall EEWrite_seq ;program EEPROM with $aa
dec counter ;decrement counter
brne loop1 ;and loop more if not done

;***** Copy 10 first bytes of EEPROM to r1-r11

clr temp
out EEARH,temp ;EEARH <- $00
ldi temp,$00
out EEARL,temp ;EEAR <- $00 (start address
- 1)

clr ZH
ldi ZL,1 ;Z-pointer points to r1

loop2: rcall EERead_seq ;get EEPROM data

st Z,EEdrd_s ;store to SRAM
inc ZL
cpi ZL,12 ;reached the end?
brne loop2 ;if not, loop more

forever:rjmp forever ;eternal loop

Programming the AVR Microcontrollers in Machine Language

AVR
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© WebRing Inc. Search

Atmel AVR From Wikipedia, the free encyclopedia (Redirected

from Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing,
intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still
be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
http://avr-asm.tripod.com/avr100.html (1 of 2)1/20/2009 8:48:10 PM
16 BIT MATH (AVR 202)

capabilities than I/O ports 32 to 63. CLR affects flags, while

SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language

http://avr-asm.tripod.com/avr100.html (2 of 2)1/20/2009 8:48:10 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

SERIAL EPROM STORAGE

HOME
RETRO_DAN
;*****read/write spi( in/out temp )
ASM FORUM ;caller is responsible for setting ss_inactive..
ASM MATH ;....after command completion
TUTORIAL #1
rw_spi:
TUTORIAL #2 cli
TUTORIAL #3 cbi portd, nss ;ss-active, just in case
ldi temp2, 8 ;load counter
MATH 200 spi_loop:
MATH 200b cbi portd, sck ;sck_lo
lsl temp ;move 0 into D0, all other bits UP brcc
MATH 201 lo_mosi ;msb into Carry
MATH 202 sbi portd, mosi ;mosi_hi, Carry into output
rjmp mosi_done
MATH 32X
lo_mosi:
MATH YX cbi portd, mosi ;mosi_lo, Carry into output
mosi_done:
DIV16 XX
sbic pinb, miso ;read in SPI bit & put into D0
DIV 24 24 inc temp;we FORCED D0=0, so use INC to set D0.
DIV 3216 sbi portd, sck ;sck_hi
dec temp2 ;count bits
FLOAT 128 brne spi_loop
SQRT16 ret ;end of routine

MATH 202
MATH 202
DEC ASCII
INT ASCII
HX2ASC
AVG8 222
FFT7
COPY 102
LPM 108
EPROM 100 Programming the AVR Microcontrollers in Machine Language
SER EPROM
DFLASH AT45 AVR
FLASH CARD << Prev | Ring Hub | Join | Rate| Next
VFX SMIL >>
© WebRing Inc. Search
VFX MEM
SORT 220
CRC 236
Atmel AVR From Wikipedia, the free encyclopedia
XMODEM REC
UART 304
(Redirected from Avr) Jump to: navigation, search The
UART 305 AVRs are a family of RISC microcontrollers from Atmel.
UART 128
Their internal architecture was conceived by two
UART BUFF
USB 232
students: Alf-Egil Bogen and Vegard Wollan, at the
AVR ISP Norwegian Institute of Technology (NTH] and further
ISP 2313
developed at Atmel Norway, a subsidiary founded by the
ISP 1200
AVR SPI
two architects. Atmel recently released the Atmel AVR32
I2C 300 line of microcontrollers. These are 32-bit RISC devices
I2C 302
featuring SIMD and DSP instructions, along with many
I2C TWI26
I2C/TWI 128
additional features for audio and video processing,
I2C/TWI AT8 intended to compete with ARM based processors. Note
DALLAS-1W that the use of "AVR" in this article refers to the 8-bit
DALLAS CRC
ETHNET 8019
RISC line of Atmel AVR Microcontrollers. The acronym
TEA AVR has been reported to stand for Advanced Virtual
ADC 128 RISC. It's also rumoured to stand for the company's
ADC 10B
ADC 400
founders: Alf and Vegard, who are evasive when
ADC 401 questioned about it. Contents [hide] 1 Device Overview
THERM 232 1.1 Program Memory 1.2 Data Memory and Registers 1.3
IRD 410
LCD HD44
EEPROM 1.4 Program Execution 1.5 Speed 2
LCD 2313 Development 3 Features 4 Footnotes 5 See also 6
LCD44 2313 External Links 6.1 Atmel Official Links 6.2 AVR Forums &
KBD 240
MUX 242
Discussion Groups 6.3 Machine Language Development
KBD PS2 6.4 C Language Development 6.5 BASIC & Other AVR
KBD PC/128 Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
PS2 EMU
BOOT MG8
Links [edit] Device Overview The AVR is a Harvard
BOOT DR8 architecture machine with programs and data stored and
ALM CLK addressed separately. Flash, EEPROM, and SRAM are all
CLOCK 8564
90 DAYS
integrated onto a single die, removing the need for
DELAYS external memory (though still available on some devices).
CALL ID [edit] Program Memory Program instructions are stored
DTMF 314
PWM 6CH
in semi-permanent Flash memory. Each instruction for
PWM 10K the AVR line is either 16 or 32 bits in length. The Flash
ENCODE memory is addressed using 16 bit word sizes. The size of
STH-11
ATMEL CORP
the program memory is indicated in the naming of the
AVR device itself. For instance, the ATmega64x line has
BUTTERFLY
64Kbytes of Flash. Almost all AVR devices are self-
AVR BOOK
programmable. [edit] Data Memory and Registers The
data address space consists of the register file, I/O
registers, and SRAM. The AVRs have thirty-two single-
byte registers and are classified as 8-bit RISC devices.
The working registers are mapped in as the first thirty-
two memory spaces (000016-001F16) followed by the 64 I/
O registers (002016-005F16). The actual usable RAM
starts after both these sections (address 006016). (Note
that the I/O register space may be larger on some more
extensive devices, in which case memory mapped I/O
registers will occupy a portion of the SRAM.) Even
though there are separate addressing schemes and
optimized opcodes for register file and I/O register
access, all can still be addressed and manipulated as if
they were in SRAM. [edit] EEPROM Almost all devices
have on-die EEPROM. This is most often used for long-
term parameter storage to be retrieved even after cycling
the power of the device. [edit] Program Execution Atmel's
AVRs have a single level pipeline design. The next
machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code.
The AVR instruction set is more orthogonal than most
eight-bit microcontrollers, however, it is not completely
regular: Pointer registers X, Y, and Z have addressing
capabilities that are different from each other. Register
locations R0 to R15 have different addressing capabilities
than register locations R16 to R31. I/O ports 0 to 31 have
different addressing capabilities than I/O ports 32 to 63.
CLR affects flags, while SER does not, even though they
are complementary instructions. CLR set all bits to zero
and SER sets them to one. (Note though, that neither CLR
nor SER are native instructions. Instead CLR is syntactic
sugar for [produces the same machine code as] EOR R,R
while SER is syntactic sugar for LDI R,$FF. Math
operations such as EOR modify flags while moves/loads/
stores/branches such as LDI do not.) [edit] Speed The
AVR line can normally support clock speeds from 0-
16MHz, with some devices reaching 20MHz. Lower
powered operation usually requires a reduced clock
speed. All AVRs feature an on-chip oscillator, removing
the need for external clocks or resonator circuitry.
Because many operations on the AVR are single cycle,
the AVR can achieve up to 1MIPS per MHz. [edit]
Development AVRs have a large following due to the free
and inexpensive development tools available, including
reasonably priced development boards and free
development software. The AVRs are marketed under
various names that share the same basic core but with
different peripheral and memory combinations. Some
models (notably, the ATmega range) have additional
instructions to make arithmetic faster. Compatibility
amongst chips is fairly good. See external links for sites
relating to AVR development. [edit] Features Current
AVRs offer a wide range of features: RISC Core Running
Many Single Cycle Instructions Multifunction, Bi-
directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High
Voltage methods Optional Boot Code Section with
Independent Lock Bits for Protection Internal Data
EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-
Bit Timers PWM Channels & dead time generator Lighting
(PWM Specific) Controller models Dedicated I²C
Compatible Two-Wire Interface (TWI) Synchronous/
Asynchronous Serial Peripherals (UART/USART) (As
used with RS-232,RS-485, and more) Serial Peripheral
Interface (SPI) CAN Controller Support USB Controller
Support Proper High-speed hardware & Hub controller
with embedded AVR. Also freely available low-speed
(HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex
of up to 16 channels Brownout Detection Watchdog
Timer (WDT) Low-voltage Devices Operating Down to
1.8v Multiple Power-Saving Sleep Modes picoPower
Devices Atmel AVR assembler programming language
Atmel AVR machine programming language Atmel AVR
From Wikipedia, the free encyclopedia (Redirected from
Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil
Bogen and Vegard Wollan, at the Norwegian Institute of
Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects.
Atmel recently released the Atmel AVR32 line of
microcontrollers. These are 32-bit RISC devices featuring
SIMD and DSP instructions, along with many additional
features for audio and video processing, intended to
compete with ARM based processors. Note that the use
of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it.
Contents [hide] 1 Device Overview 1.1 Program Memory
1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program
Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official
Links 6.2 AVR Forums & Discussion Groups 6.3 Machine
Language Development 6.4 C Language Development 6.5
BASIC & Other AVR Languages 6.6 AVR Butterfly
Specific 6.7 Other AVR Links [edit] Device Overview The
AVR is a Harvard architecture machine with programs
and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still
available on some devices). [edit] Program Memory
Program instructions are stored in semi-permanent Flash
memory. Each instruction for the AVR line is either 16 or
32 bits in length. The Flash memory is addressed using
16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance,
the ATmega64x line has 64Kbytes of Flash. Almost all
AVR devices are self-programmable. [edit] Data Memory
and Registers The data address space consists of the
register file, I/O registers, and SRAM. The AVRs have
thirty-two single-byte registers and are classified as 8-bit
RISC devices. The working registers are mapped in as
the first thirty-two memory spaces (000016-001F16)
followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections
(address 006016). (Note that the I/O register space may
be larger on some more extensive devices, in which case
memory mapped I/O registers will occupy a portion of the
SRAM.) Even though there are separate addressing
schemes and optimized opcodes for register file and I/O
register access, all can still be addressed and
manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most
often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level
pipeline design. The next machine instruction is fetched
as the current one is executing. Most instructions take
just one or two clock cycles, making AVRs relatively fast
among the eight-bit microcontrollers. The AVR family of
processors were designed for the efficient execution of
compiled C code. The AVR instruction set is more
orthogonal than most eight-bit microcontrollers,
however, it is not completely regular: Pointer registers X,
Y, and Z have addressing capabilities that are different
from each other. Register locations R0 to R15 have
different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags,
while SER does not, even though they are
complementary instructions. CLR set all bits to zero and
SER sets them to one. (Note though, that neither CLR nor
SER are native instructions. Instead CLR is syntactic
sugar for [produces the same machine code as] EOR R,R
while SER is syntactic sugar for LDI R,$FF. Math
operations such as EOR modify flags while moves/loads/
stores/branches such as LDI do not.) [edit] Speed The
AVR line can normally support clock speeds from 0-
16MHz, with some devices reaching 20MHz. Lower
powered operation usually requires a reduced clock
speed. All AVRs feature an on-chip oscillator, removing
the need for external clocks or resonator circuitry.
Because many operations on the AVR are single cycle,
the AVR can achieve up to 1MIPS per MHz. [edit]
Development AVRs have a large following due to the free
and inexpensive development tools available, including
reasonably priced development boards and free
development software. The AVRs are marketed under
various names that share the same basic core but with
different peripheral and memory combinations. Some
models (notably, the ATmega range) have additional
instructions to make arithmetic faster. Compatibility
amongst chips is fairly good. See external links for sites
relating to AVR development. [edit] Features Current
AVRs offer a wide range of features: RISC Core Running
Many Single Cycle Instructions Multifunction, Bi-
directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High
Voltage methods Optional Boot Code Section with
Independent Lock Bits for Protection Internal Data
EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-
Bit Timers PWM Channels & dead time generator Lighting
(PWM Specific) Controller models Dedicated I²C
Compatible Two-Wire Interface (TWI) Synchronous/
Asynchronous Serial Peripherals (UART/USART) (As
used with RS-232,RS-485, and more) Serial Peripheral
Interface (SPI) CAN Controller Support USB Controller
Support Proper High-speed hardware & Hub controller
with embedded AVR. Also freely available low-speed
(HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex
of up to 16 channels Brownout Detection Watchdog
Timer (WDT) Low-voltage Devices Operating Down to
1.8v Multiple Power-Saving Sleep Modes picoPower
Devices Atmel AVR assembler programming language
Atmel AVR machine programming language Atmel AVR
From Wikipedia, the free encyclopedia (Redirected from
Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil
Bogen and Vegard Wollan, at the Norwegian Institute of
Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects.
Atmel recently released the Atmel AVR32 line of
microcontrollers. These are 32-bit RISC devices featuring
SIMD and DSP instructions, along with many additional
features for audio and video processing, intended to
compete with ARM based processors. Note that the use
of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it.
Contents [hide] 1 Device Overview 1.1 Program Memory
1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program
Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official
Links 6.2 AVR Forums & Discussion Groups 6.3 Machine
Language Development 6.4 C Language Development 6.5
BASIC & Other AVR Languages 6.6 AVR Butterfly
Specific 6.7 Other AVR Links [edit] Device Overview The
AVR is a Harvard architecture machine with programs
and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still
available on some devices). [edit] Program Memory
Program instructions are stored in semi-permanent Flash
memory. Each instruction for the AVR line is either 16 or
32 bits in length. The Flash memory is addressed using
16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance,
the ATmega64x line has 64Kbytes of Flash. Almost all
AVR devices are self-programmable. [edit] Data Memory
and Registers The data address space consists of the
register file, I/O registers, and SRAM. The AVRs have
thirty-two single-byte registers and are classified as 8-bit
RISC devices. The working registers are mapped in as
the first thirty-two memory spaces (000016-001F16)
followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections
(address 006016). (Note that the I/O register space may
be larger on some more extensive devices, in which case
memory mapped I/O registers will occupy a portion of the
SRAM.) Even though there are separate addressing
schemes and optimized opcodes for register file and I/O
register access, all can still be addressed and
manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most
often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level
pipeline design. The next machine instruction is fetched
as the current one is executing. Most instructions take
just one or two clock cycles, making AVRs relatively fast
among the eight-bit microcontrollers. The AVR family of
processors were designed for the efficient execution of
compiled C code. The AVR instruction set is more
orthogonal than most eight-bit microcontrollers,
however, it is not completely regular: Pointer registers X,
Y, and Z have addressing capabilities that are different
from each other. Register locations R0 to R15 have
different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags,
while SER does not, even though they are
complementary instructions. CLR set all bits to zero and
SER sets them to one. (Note though, that neither CLR nor
SER are native instructions. Instead CLR is syntactic
sugar for [produces the same machine code as] EOR R,R
while SER is syntactic sugar for LDI R,$FF. Math
operations such as EOR modify flags while moves/loads/
stores/branches such as LDI do not.) [edit] Speed The
AVR line can normally support clock speeds from 0-
16MHz, with some devices reaching 20MHz. Lower
powered operation usually requires a reduced clock
speed. All AVRs feature an on-chip oscillator, removing
the need for external clocks or resonator circuitry.
Because many operations on the AVR are single cycle,
the AVR can achieve up to 1MIPS per MHz. [edit]
Development AVRs have a large following due to the free
and inexpensive development tools available, including
reasonably priced development boards and free
development software. The AVRs are marketed under
various names that share the same basic core but with
different peripheral and memory combinations. Some
models (notably, the ATmega range) have additional
instructions to make arithmetic faster. Compatibility
amongst chips is fairly good. See external links for sites
relating to AVR development. [edit] Features Current
AVRs offer a wide range of features: RISC Core Running
Many Single Cycle Instructions Multifunction, Bi-
directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High
Voltage methods Optional Boot Code Section with
Independent Lock Bits for Protection Internal Data
EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-
Bit Timers PWM Channels & dead time generator Lighting
(PWM Specific) Controller models Dedicated I²C
Compatible Two-Wire Interface (TWI) Synchronous/
Asynchronous Serial Peripherals (UART/USART) (As
used with RS-232,RS-485, and more) Serial Peripheral
Interface (SPI) CAN Controller Support USB Controller
Support Proper High-speed hardware & Hub controller
with embedded AVR. Also freely available low-speed
(HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex
of up to 16 channels Brownout Detection Watchdog
Timer (WDT) Low-voltage Devices Operating Down to
1.8v Multiple Power-Saving Sleep Modes picoPower
Devices Atmel AVR assembler programming language
Atmel AVR machine programming language
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16 BIT MATH (AVR 202)

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16 BIT MATH (AVR 202)

The AVR Assembler Site

SPI INTERFACE FOR AT45 SERIAL DATAFLASH

HOME
RETRO_DAN
;
ASM FORUM ***************************************************************************
ASM MATH ;
; File Name :'DFlash.asm"
TUTORIAL #1
; Title :SPI interface to Serial
TUTORIAL #2 DataFlash
TUTORIAL #3 ; Date :2003.06.01.
; Version :1.0.0
MATH 200 ; Support telephone :+36-70-333-4034, old: +36-30-9541-
MATH 200b 658 VFX
; Support fax :
MATH 201 ; Support Email :info@vfx.hu
MATH 202 ; Target MCU :ATmega8
;
MATH 32X
;
MATH YX ***************************************************************************
; D E S C R I P T I O N
DIV16 XX
;
DIV 24 24 ; SPI interface to AT45DBxxx Serial DataFlash
DIV 3216 ;
; Functions to access the Atmel AT45Dxxx dataflash
FLOAT 128 series
SQRT16 ; Supports 1Mbit - 128Mbit
;
MATH 202 ;
MATH 202 ***************************************************************************
; M O D I F I C A T I O N H I S T O R Y
DEC ASCII
;
INT ASCII ;
; rev. date who why
HX2ASC
; ---- ---------- ---
AVG8 222 ------------------------------------
FFT7 ; 0.01 2003.06.01 VFX Creation
;
COPY 102 ;
LPM 108 ***************************************************************************
;Hardware
EPROM 100 ;
SER EPROM ***************************************************************************
;*
DFLASH AT45
;* SYSCLK: f=16.000 MHz (T= 62.5 ns)
FLASH CARD ;*
;
VFX SMIL
***************************************************************************
VFX MEM ;
SORT 220 ; CS - Chip Select
; SCK - Serial Clock
CRC 236 ; SI - Serial Input
XMODEM REC ; SO - Serial Output
; WP - Hardware Page Write Protect Pin
UART 304 ; RESET - Chip Reset
UART 305 ; RDY/BUSY - Ready/Busy
;
UART 128
; To provide optimal flexibility, the memory array of
UART BUFF the AT45DB081B is
;divided into three levels of granularity comprising of
USB 232
sectors, blocks,
AVR ISP ;and pages. All program operations to the DataFlash
ISP 2313 occur on a page-by-page
;basis; however, the optional erase operations can be
ISP 1200 performed at the block
AVR SPI ;or page level.
;
I2C 300 ;
I2C 302 ;The device operation is controlled by instructions
from the host processor.
I2C TWI26
;The list of instructions and their associated opcodes
I2C/TWI 128 are contained in
I2C/TWI AT8 ;Tables 1 through 4. A valid instruction starts with
the falling edge of CS
DALLAS-1W ;followed by the appropriate 8-bit opcode and the
DALLAS CRC desired buffer or main memory
;address location. While the CS pin is low, tog-gling
ETHNET 8019 the SCK pin controls the
TEA ;loading of the opcode and the desired buffer or main
memory address location
ADC 128 ;through the SI (serial input) pin. All instructions,
ADC 10B addresses and data are
;transferred with the most significant bit (MSB) first.
ADC 400
;Buffer addressing is referenced in the datasheet using
ADC 401 the terminology
THERM 232 ;BFA8 - BFA0 to denote the nine address bits required
to designate a byte address
IRD 410 ;within a buffer. Main memory addressing is referenced
LCD HD44 using the terminology
;PA11 - PA0 and BA8 - BA0 where PA11 - PA0 denotes the
LCD 2313 12 address bits required
LCD44 2313 ;to designate a page address and BA8 - BA0 denotes the
nine address bits
KBD 240 ;required to designate a byte address within the page.
MUX 242 ;
;
KBD PS2
;Status Register Format
KBD PC/128 ;Bit 7 6 5 4 3 2 1 0
PS2 EMU ; RDY/BUSY COMP 1 0 0 1 X X 45DB161
;
BOOT MG8 ***************************************************************************
BOOT DR8 ;* Const Def
;
ALM CLK
CLOCK 8564 ;Look-up table for these sizes -> 512k, 1M, 2M, 4M,
8M, 16M, 32M, 64M
90 DAYS
;flash unsigned char DF_pagebits[] ={ 9, 9, 9, 9,
DELAYS 9, 10, 10, 11}; //index of internal page address bits
CALL ID
DTMF 314
PWM 6CH ;Dataflash opcodes
.equ MainMemPageRead = 0x52 ;Main Memory Page
PWM 10K Read Inactive Clk Pol Low or High
ENCODE .equ FlashPageRead = 0x52 ;Main memory page
read
STH-11 .equ FlashToBuf1Transfer= 0x53 ;Main memory page
ATMEL CORP to buffer 1 transfer
.equ Buf1Read = 0x54 ;Buffer 1
AVR
read
BUTTERFLY .equ FlashToBuf2Transfer= 0x55 ;Main memory page
AVR BOOK to buffer 2 transfer
.equ Buf2Read = 0x56 ;Buffer 2
read
.equ StatusReg = 0x57 ;Status
register
.equ StatusRegMode3 = 0xD7 ;Status register
read SPI Mode 0 or 3
.equ AutoPageReWrBuf1 = 0x58 ;Auto page
rewrite through buffer 1
.equ AutoPageReWrBuf2 = 0x59 ;Auto page
rewrite through buffer 2
.equ FlashToBuf1Compare = 0x60 ;Main
memory page to buffer 1 compare
.equ FlashToBuf2Compare = 0x61 ;Main
memory page to buffer 2 compare
.equ ContArrayRead = 0x68 ;Continuous Array
Read (Note : Only A/B-parts supported)
.equ FlashProgBuf1 = 0x82 ;Main memory page
program through buffer 1
.equ Buf1ToFlashWE = 0x83 ;Buffer 1 to main
memory page program with built-in erase
.equ Buf1Write = 0x84 ;Buffer 1
write
.equ FlashProgBuf2 = 0x85 ;Main memory page
program through buffer 2
.equ Buf2ToFlashWE = 0x86 ;Buffer 2 to main
memory page program with built-in erase
.equ Buf2Write = 0x87 ;Buffer 2
write
.equ Buf1ToFlash = 0x88 ;Buffer 1 to main
memory page program without built-in erase
.equ Buf2ToFlash = 0x89 ;Buffer 2 to main
memory page program without built-in erase
.equ MainMemPageReadSPI = 0xD2 ;Main Memory Page
Read SPI Mode 0 or 3
.equ ContArrayReadSPI = 0xE8 ;Continuous Array
Read SPI Mode 0 or 3

;Table 2. Program and Erase Commands

.equ Buffer1Write = 0x84 ;Buffer 1 Write
.equ Buffer2Write = 0x87 ;Buffer 2 Write
.equ Buffer1toMem = 0x88 ;Buffer 1 to Main Memory
Page Program without Built-in Erase
.equ Buffer2toMem = 0x89 ;Buffer 2 to Main Memory
Page Program without Built-in Erase
.equ DFPageErase = 0x81 ;Page Erase
.equ DFBlockErase = 0x50 ;Block Erase
.equ MemPageProgBuff1 = 0x82 ;Main Memory Page
Program through Buffer 1
.equ MemPageProgBuff2 = 0x85 ;Main Memory Page
Program through Buffer 2

;Table 3. Additional Commands

.equ MemPagetoBuff1 = 0x53 ;Main Memory Page to
Buffer 1 Transfer
.equ MemPagetoBuff2 = 0x55 ;Main Memory Page to
Buffer 2 Transfer
.equ MemPagetoBuff1Cmp = 0x60 ;Main Memory Page to
Buffer 1 Compare
.equ MemPagetoBuff2Cmp = 0x61 ;Main Memory Page to
Buffer 2 Compare
.equ PageRewriteBuff1 = 0x58 ;Auto Page Rewrite
through Buffer 1
.equ PageRewriteBuff2 = 0x59 ;Auto Page Rewrite
through Buffer 2

;
**************************************************************************
;* Hardware Def.
;

; RDY/BUSY - Ready/Busy
.equ DFRDY_PORT = PORTD
.equ DFRDY_DIR = DDRD
.equ DFRDY_PIN = PIND
.equ DFRDY = 7

.equ DFRES_PORT = PORTD

.equ DFRES_DIR = DDRD
.equ DFRES = 5

.equ DFCS_PORT = PORTC

.equ DFCS_DIR = DDRC
.equ DFCs = 2

.equ MOSI_DIR = DDRB

.equ MOSI_PORT = PORTB
.equ MOSI = 3

.equ MISO_DIR = DDRB

.equ MISO_PORT = PORTB
.equ MISO_PIN = PINB
.equ MISO = 4

.equ SCLK_DIR = DDRB

.equ SCLK_PORT = PORTB
.equ SCLK = 5

.equ DFSS_DIR = DDRB

.equ DFSS_PORT = PORTB
.equ DFSS = 2

;
***************************************************************************
;**** VARIABLES
.DSEG

DFSize: .byte 1
DFPageSize: .byte 1
DFPageBits: .byte 1

.equ DFBuffer = AppData

;DFBuffer: .byte 128 ;Data buffer

; !!! use AppData buffer from user.asm --> save RAM
Space !!!
; !!! Self update not supported in application !!!

;
***************************************************************************
.ESEG

;
***************************************************************************
;**** CODE SEG
;
***************************************************************************
.CSEG

;p,x,y,z,0
;page bits = p
;page number = x * 256
;page size = y * 256 (264)
;type = z
;
AT45DBxxx: .db 9, 2,1,0b00001100 ;AT45DB011 1Mbit
.db 9, 4,1,0b00010100 ;AT45DB021 2Mbit
.db 9, 8,1,0b00011100 ;AT45DB041 4Mbit
.db 9,16,1,0b00100100 ;AT45DB081 8Mbit
.db 10,16,2,0b00101100 ;AT45DB161 16Mbit
.db 10,32,2,0b00110100 ;AT45DB321 32Mbit
.db 11,32,4,0b00111000 ;AT45DB642 64Mbit
.db 11,64,4,0b00010000 ;AT45DB1282
128Mbit
.dw 0,0

;
****************************************************************************
;*** S P I R U T I N S
;***
;
****************************************************************************
;* SPI_init
;*
;* Initialize our port pins for use as SPI master.
;*
;
***************************************************************************
;
SPI_init:
sbi DFCS_PORT,DFCS ;DFlash CE
pin is output for ATmega
sbi DFCS_DIR,DFCS ;CS=1

sbi DFRES_PORT,DFRES
sbi DFRES_DIR,DFRES ;DFlash
Reset = H

cbi DFRDY_DIR,DFRDY
sbi DFRDY_PORT,DFRDY ;DFlash R/B
pullup input

in R16,PORTB
andi R16,0b11000011
ori R16,0b00101100
out PORTB,R16 ;SS, MOSI,
SCK output; MISO input

in R16,DDRB
andi R16,0b11000011
ori R16,0b00101100
out DDRB,R16

ldi R16,0b01011100
out SPCR,R16 ;[7] - SPIE: SPI
Interrupt Enable
;[6] - SPE: SPI
Enable
;[5] - DORD: Data
Order
;[4] - MSTR: Master/
Slave Select
;[3] - CPOL: Clock
Polarity
;[2] - CPHA: Clock
Phase
;[1:0] - SPR1,SPR0:
SPI Clock Rate Select
; SPI2X SPR1 SPR0
SCK Frequency
; 0 0
0 fosc/4
; 0 0
1 fosc/16
; 0 1
0 fosc/64
; 0 1
1 fosc/128
; 1 0
0 fosc/2
; 1 0
1 fosc/8
; 1 1
0 fosc/32
; 1 1
1 fosc/64

ldi R16,0b00000001
out SPSR,R16 ;[7] - SPIF: SPI
Interrupt Flag
;[6] - WCOL: Write
COLlision flag
;[5:1] - Res:
Reserved Bits
;[0] - SPI2X:
Double SPI Speed Bit
in R16,SPSR
in R16,SPDR ;Clear SPIF & WCOL
bits

cbi DFRES_PORT,DFRES ;DFlash

Reset
;DFlash
Reset>10us
ldi ZL,low(SYSCLK/100000)
ldi ZH,High(SYSCLK/100000)
W10us1: sbiw ZL,1
brne W10us1

sbi DFRES_PORT,DFRES ;DFlash

Reset = 1

ldi R16,50 ;Reset

Recoveri time = 1 us
W10us2: dec R16
brne W10us2

rcall DF_ReadStatus
cbr R16,0b11000011
ldi ZL,low(AT45DBxxx*2) ;ATmega128 -
> set PAMPZ!!
ldi ZH,high(AT45DBxxx*2)
SearchDF: lpm R17,Z+
sts DFPageBits,R17
lpm R18,Z+
sts DFSize,R18
lpm R18,Z+
sts DFPageSize,R18
lpm R2,Z+
cp R16,R2
breq DFHit
tst R17
brne SearchDF
DFHit:
ret

;
*****************************************************************************
;*DF_SPI_RW
;*
;* Read and writes one byte from/to SPI master
;*
;* In: R16 - Byte to be written to SPI data register
;*
;* Out: R16 - Byte read from SPI data register
;*
;
******************************************************************************
;
DF_SPI_RW:
out SPDR,R16
DF_SPI_RW0:
sbis SPSR,spif
rjmp DF_SPI_RW0 ;wait for transfer
complete, poll SPIF-flag
in R16,SPDR
ret

;
*****************************************************************************
;*Read_DF_status
;*
;* Status info concerning the Dataflash is busy or not.
;* Status info concerning compare between buffer and
flash page
;* Status info concerning size of actual device
;*
;* In: -
;*
;* Out: R16 - status byte. Consult Dataflash datasheet
for further decoding info
;*
;
******************************************************************************
;
DF_ReadStatus:
sbi DFCS_PORT,DFCS ;DF CS
inactive
nop
nop
cbi DFCS_PORT,DFCS ;DF CS
Active!
;to reset
dataflash command decoder
ldi R16,StatusRegMode3
rcall DF_SPI_RW ;send
status register read op-code
clr R16
rcall DF_SPI_RW ;dummy
write to get result
ret

;
*****************************************************************************
;* WaitToDF
;*
;* Wait for DataFlash to Ready
;*
;* In: -
;*
;* Out: -
;*
;
******************************************************************************
;
WaitToDF:
rcall DF_ReadStatus
cbr R16,0x7F ;
Csak a Busy Flag marad meg
breq WaitToDF ;
monitor the status register, wait until busy-flag is high
sbi DFCS_PORT,DFCS ;DF CS
inactive
nop
cbi DFCS_PORT,DFCS ;DF CS
Active! , reset dataflash command decoder
ret

;
*****************************************************************************
;Page_To_Buffer
;
; Transfers a page from flash to dataflash SRAM buffer
;
; In: R0 = BufferNo -> R0 = 0 usage Buffer 1
; = non zero usage Buffer 2
; R19:R18 = PageAdr -> Address of page to be
transferred to buffer
;
; Out: -
;
*****************************************************************************
;
DF_PageToBuffer:
rcall WaitToDF
ldi R16,FlashToBuf1Transfer ;transfer
to buffer 1 op-code
tst R0
breq DF_PageToBuff01
ldi R16,FlashToBuf2Transfer ;transfer
to buffer 2 op-code
DF_PageToBuff01:
rcall DF_SPI_RW ;send op-
code
lds R16,DFPageBits
subi R16,8
DF_PageToBuff02:
lsl R18
rol R19
dec R16
brne DF_PageToBuff02

mov R16,R19
rcall DF_SPI_RW ;upper part of page
address
mov R16,R18
rcall DF_SPI_RW ;lower part of page
address
clr R16
rcall DF_SPI_RW

sbi DFCS_PORT,DFCS ;DF CS

inactive
ret

;
*****************************************************************************
;DF_BufferReadByte
;
; Reads one byte from one of the dataflash internal
SRAM buffers
;
; In: R0 = BufferNo -> R0 = 0 usage Buffer 1
; = non zero usage Buffer 2
; R19:R18 = IntPageAdr -> Internal page address
;
; Out: R16 - One read byte (any value)
;
;
*****************************************************************************
;
DF_BufferReadByte:
rcall WaitToDF
ldi R16,Buf1Read ;read byte
from buffer 1
tst R0
breq BufferReadByte01
ldi R16,Buf2Read ;read byte
from buffer 2
BufferReadByte01:
rcall DF_SPI_RW ;send op-
code
clr R16
rcall DF_SPI_RW ;don't cares
mov R16,R19
rcall DF_SPI_RW ;upper part
of page address
mov R16,R18
rcall DF_SPI_RW ;lower part
of page address
clr R16
rcall DF_SPI_RW ;additional
don't cares
clr R16
rcall DF_SPI_RW ;read byte
sbi DFCS_PORT,DFCS ;DF CS
inactive
ret

;
*****************************************************************************
;DF_BufferReadStr
;
; Reads one or more bytes from one of the dataflash
internal SRAM buffers,
; and puts read bytes into buffer pointed to by X
; In: R0: BufferNo -> R0 = 0 usage Buffer 1
; = non zero usage Buffer 2
; R19:R18 -> Internal page address
; R21:R20 -> Number of bytes to be read
; X -> address of buffer to be
used for read bytes
;
; Out: -
;
;
*****************************************************************************
;
DF_BufferReadStr:
rcall WaitToDF
ldi R16,Buf1Read ;read byte
from buffer 1
tst R0
breq DF_BufferReadStr01
ldi R16,Buf2Read ;read byte
from buffer 2
DF_BufferReadStr01:
rcall DF_SPI_RW ;send op-
code
clr R16
rcall DF_SPI_RW ;don't cares
mov R16,R19
rcall DF_SPI_RW ;upper part
of page address
mov R16,R18
rcall DF_SPI_RW ;lower part
of page address
clr R16
rcall DF_SPI_RW ;additional
don't cares
push YL
push YH
movw YL,R20 ;Internal
page address + Number of bytes to be read <= Page Size!!!
DF_BufferReadStr02:
clr R16
rcall DF_SPI_RW
st X+,R16 ;Store DF
data byte
sbiw YL,1
brne DF_BufferReadStr02
pop YH
pop YL
sbi DFCS_PORT,DFCS ;DF CS
inactive
ret

;
*****************************************************************************
; DF_BufferWriteEnable
;
; Enables continous write functionality to one of the
dataflash buffers
; NOTE : User must ensure that CS goes high to
terminate this mode
; before accessing other dataflash functionalities
;
; In: R0: BufferNo -> R0 = 0 usage Buffer 1
; = non zero usage Buffer 2
; R19:R18 -> Internal page address to
start writing from
;
; Out: None
;
;
*****************************************************************************
;
DF_BufferWriteEnable:
rcall WaitToDF
ldi R16,Buf1Write ;buffer 1
write op-code
tst R0
breq DF_BufferWriteEnable01
ldi R16,Buf2Write ;buffer 2
write op-code
DF_BufferWriteEnable01:
rcall DF_SPI_RW ;send op-
code
clr R16
rcall DF_SPI_RW ;don't cares
mov R16,R19
rcall DF_SPI_RW ;upper part
of page address
mov R16,R18
rcall DF_SPI_RW ;lower part
of page address
ret

;
*****************************************************************************
; DF_BufferWriteByte:
;
; Writes one byte to one of the dataflash internal SRAM
buffers
;
; In: R0: BufferNo -> R0 = 0 usage Buffer 1
; = non zero usage Buffer 2
; R19:R18 -> Internal page address to
write byte to
; R16 -> Data byte to be written
;
; Out: None
;
;
*****************************************************************************
;
DF_BufferWriteByte:
push R16
rcall WaitToDF
ldi R16,Buf1Write ;buffer 1
write op-code
tst R0
breq DF_BufferWriteByte01
ldi R16,Buf2Write ;buffer 2
write op-code
DF_BufferWriteByte01:
rcall DF_SPI_RW ;send op-
code
clr R16
rcall DF_SPI_RW ;don't cares
mov R16,R19
rcall DF_SPI_RW ;upper part
of page address
mov R16,R18
rcall DF_SPI_RW ;lower part
of page address
pop R16
rcall DF_SPI_RW ;write data
byte
DF_EndWrite:
sbi DFCS_PORT,DFCS ;DF CS
inactive
ret

;
*****************************************************************************
; DF_BufferWriteStr
;
; Copies one or more bytes to one of the dataflash
internal SRAM buffers
; from AVR SRAM buffer pointed to by X
;
; In: R0: BufferNo -> R0 = 0 usage Buffer 1
; = non zero usage Buffer 2
; R19:R18 -> Internal page address
; R21:R20 -> Number of bytes to be read
; X -> address of buffer to be
used for write bytes
;
; Out: None
;
;
*****************************************************************************
;
DF_BufferWriteStr:
rcall WaitToDF
ldi R16,Buf1Write ;write byte
to buffer 1
tst R0
breq DF_BufferWriteStr01
ldi R16,Buf2Write ;write byte
to buffer 2
DF_BufferWriteStr01:
rcall DF_SPI_RW ;send op-
code
clr R16
rcall DF_SPI_RW ;don't cares
mov R16,R19
rcall DF_SPI_RW ;upper part
of page address
mov R16,R18
rcall DF_SPI_RW ;lower part
of page address
push YL
push YH
movw YL,R20 ;Internal
page address + Number of bytes to be read <= Page Size!!!
DF_BufferWriteStr02:
ld R16,X+ ;Store DF
data byte
rcall DF_SPI_RW
sbiw YL,1
brne DF_BufferWriteStr02
pop YH
pop YL
ret

;
*****************************************************************************
; DF_BufferToPage
; DF_BufferToPageWErase
;
; Transfers a page from dataflash SRAM buffer to flash
;
; In: R0 = BufferNo -> R0 = 0 usage Buffer 1
; = non zero usage Buffer 2
; R19:R18 = PageAdr -> Address of flash page to be
programmed
;
; Out: None
;
;
*****************************************************************************
;
DF_BufferToPage:
rcall WaitToDF
ldi R16,Buffer1toMem ;buffer 1
to flash without erase
tst R0
breq DF_BufferToPage01
ldi R16,Buffer1toMem
rjmp DF_BufferToPage01

DF_BufferToPageWErase:
rcall WaitToDF
ldi R16,Buf1ToFlashWE ;buffer 1
to flash with erase op-code
tst R0
breq DF_BufferToPage01
ldi R16,Buf2ToFlashWE ;buffer 2
to flash with erase op-code
DF_BufferToPage01:
rcall DF_SPI_RW ;send op-
code
lds R16,DFPageBits
subi R16,8
DF_BufferToPage02:
lsl R18
rol R19
dec R16
brne DF_BufferToPage02

mov R16,R19
rcall DF_SPI_RW ;upper part of page
address
mov R16,R18
rcall DF_SPI_RW ;lower part of page
address
clr R16
rcall DF_SPI_RW
nop
sbi DFCS_PORT,DFCS ;DF CS
inactive
ret

;
*****************************************************************************
; DF_PageErase
;
; Erase Flash Page
;
; In: R19:R18 = PageAdr -> Address of flash
page to be erased
;
; Out: None
;
;
*****************************************************************************
;
DF_PageErase:
rcall WaitToDF
ldi R16,DFPageErase
rcall DF_SPI_RW ;send op-
code

lds R16,DFPageBits
subi R16,8
DF_PageErase01:
lsl R18
rol R19
dec R16
brne DF_PageErase01

mov R16,R19
rcall DF_SPI_RW ;upper part
of page address
mov R16,R18
rcall DF_SPI_RW ;lower part
of page address
clr R16
rcall DF_SPI_RW ;dumpy part
of address!!!
nop
sbi DFCS_PORT,DFCS ;DF CS
inactive
ret

;
*****************************************************************************
; DF_CheckErasedPage
;
; Test Erased Flash Page
;
; In: R19:R18 = PageAdr -> Address of flash
page to be tested
; R0 = used buffer 0 = buffer0 other = buffer1
;
; Out: c=0 no error
; c=1 Bad Page! Dont use!!
;
;
*****************************************************************************
;
DF_CheckErasedPage:
rcall WaitToDF
push R0
rcall DF_PageToBuffer

clr XL
ldi R16,8
lds XH,DFPageSize
mul R16,XH
add XL,R0
adc XH,R1 ;X full
lenght of page in byte
pop R0

DF_Check00:
push R0
push XL
push XH
sbiw XL,1
movw R18,XL
rcall DF_BufferReadByte
pop XH
pop XL
pop R0
cpi R16,0xFF

http://avr-asm.tripod.com/dfat45.html (1 of 2)1/20/2009 8:49:19 PM

16 BIT MATH (AVR 202)

brne DF_BadPage
sbiw XL,1
brne DF_Check00
clc
ret ;ok page
cleared well
DF_BadPage:
sec
ret ;Bad Page!

Programming the AVR Microcontrollers in Machine Language

AVR
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© WebRing Inc. Search

Atmel AVR From Wikipedia, the free encyclopedia (Redirected

from Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing,
intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still
be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language

http://avr-asm.tripod.com/dfat45.html (2 of 2)1/20/2009 8:49:19 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

COMPACT FLASH CARD INTERFACE

HOME
RETRO_DAN
;***************************************************************************
ASM FORUM ;
ASM MATH ; File Name :'cf.asm"
; Title :Compact Flash Common Memory Mode Driver
TUTORIAL #1
; Date :2004.05.12.
TUTORIAL #2 ; Version :1.0.0
TUTORIAL #3 ; Support telephone :+36-70-333-4034, old: +36-30-9541-658 VFX
; Support fax :
MATH 200 ; Support Email :info@vfx.hu
MATH 200b ; Target MCU :AVR
;
MATH 201 ;***************************************************************************
MATH 202 ; D E S C R I P T I O N
;
MATH 32X
; Memory Interface to a compact flash card.
MATH YX ; Compact flash card is used in memory mapped mode.
; Registers are located at ADR_CFC in external RAM space of Mega128
DIV16 XX
;
DIV 24 24 ;
DIV 3216 ;***************************************************************************
; M O D I F I C A T I O N H I S T O R Y
FLOAT 128 ;
SQRT16 ;
; rev. date who why
MATH 202 ; ---- ---------- --- ------------------------------------
MATH 202 ; 0.01 2004.05.12 VFX Creation
;
DEC ASCII
;***************************************************************************
INT ASCII ;Hardware
;***************************************************************************
HX2ASC
;*
AVG8 222 ;* SYSCLK: f=16.000 MHz (T= 62.5 ns)
FFT7 ;*
;***************************************************************************
COPY 102 ;
LPM 108 ;
;**************************************************************************
EPROM 100 ;* Hardware Def.
SER EPROM ;
; CompactFlash hardware definitions
DFLASH AT45
; Table 34: Memory Mapped Decoding
FLASH CARD ; -REG A10 A9-A4 A3 A2 A1 A0 Offset -OE=0 -WE=0 Notes
; 1 0 X 0 0 0 0 0 Even RD Data Even WR Data 1, 2
VFX SMIL
; 1 0 X 0 0 0 1 1 Error Features 1, 2
VFX MEM ; 1 0 X 0 0 1 0 2 Sector Count Sector Count
SORT 220 ; 1 0 X 0 0 1 1 3 Sector No. Sector No.
; 1 0 X 0 1 0 0 4 Cylinder Low Cylinder Low
CRC 236 ; 1 0 X 0 1 0 1 5 Cylinder High Cylinder High
XMODEM REC ; 1 0 X 0 1 1 0 6 Select Card/Head Select Card/Head
; 1 0 X 0 1 1 1 7 Status Command
UART 304 ; 1 0 X 1 0 0 0 8 Dup. Even RD Data Dup. Even WR Data 2
UART 305 ; 1 0 X 1 0 0 1 9 Dup. Odd RD Data Dup. Odd WR Data 2
; 1 0 X 1 1 0 1 D Dup. Error Dup. Features 2
UART 128
; 1 0 X 1 1 1 0 E Alt Status Device Ctl
UART BUFF ; 1 0 X 1 1 1 1 F Drive Address Reserved
; 1 1 X X X X 0 8 Even RD Data Even WR Data 3
USB 232
; 1 1 X X X X 1 9 Odd RD Data Odd WR Data 3
AVR ISP
ISP 2313 ;Note: 1) Register 0 is accessed with -CE1 low and -CE2 low as a word register
;on the combined Odd Data Bus and Even Data Bus (D15-D0). This register may
ISP 1200 ;also be accessed by a pair of byte accesses to the offset 0 with -CE1 low and
AVR SPI ;-CE2 high. Note that the address space of this word register overlaps
;the address space of the Error and Feature byte-wide registers that lie at
I2C 300 ;offset 1. When accessed twice as byte register with -CE1 low, the first byte
I2C 302 ;to be accessed is the even byte of the word and the second byte accessed
;is the odd byte of the equivalent word access.
I2C TWI26
;A byte access to address 0 with -CE1 high and -CE2 low accesses the error
I2C/TWI 128 ;(read) or feature (write) register.
I2C/TWI AT8
;2) Registers at offset 8, 9 and D are non-overlapping duplicates of the
DALLAS-1W ;registers at offset 0 and 1. Register 8 is equivalent to register 0,
DALLAS CRC ;while register 9 accesses the odd byte. Therefore, if the registers are byte
;accessed in the order 9 then 8 the data will be transferred odd byte then even
ETHNET 8019 ;byte. Repeated byte accesses to register 8 or 0 will access consecutive
TEA ;(even then odd) bytes from the data buffer. Repeated word accesses to register
;8, 9 or 0 will access consecutive words from the data buffer. Repeated byte
ADC 128 ;accesses to register 9 are not supported. However, repeated alternating byte
ADC 10B ;accesses to registers 8 then 9 will access consecutive (even then odd) bytes
;from the data buffer. Byte accesses to register 9 access only the odd byte of
ADC 400
;the data.
ADC 401
THERM 232 ;3) Accesses to even addresses between 400h and 7FFh access register 8.
;Accesses to odd addresses between 400h and 7FFh access register 9. This
IRD 410 ;1 Kbyte memory window to the data register is provided so that hosts can
LCD HD44 ;perform memory to memory block moves to the data register when the register
;lies in memory space.
LCD 2313 ;
LCD44 2313
;
KBD 240 ;CF register addresses
MUX 242 ;
.equ CF_EvenData = ADR_CFC+0x08 ;Dupl. DAta
KBD PS2
.equ CF_OddData = ADR_CFC+0x09 ;Dupl. Data
KBD PC/128 .equ CF_Error = ADR_CFC+0x0D ;Dupl. Errors / Features
PS2 EMU .equ CF_SECCOUNT = ADR_CFC+0x02 ;Sectorcount
.equ CF_LBA0 = ADR_CFC+0x03 ;LBA 0-7
BOOT MG8 .equ CF_LBA1 = ADR_CFC+0x04 ;LBA 8-15
BOOT DR8 .equ CF_LBA2 = ADR_CFC+0x05 ;LBA 16-23
.equ CF_LBA3 = ADR_CFC+0x06 ;LBA 24-27
ALM CLK .equ CF_STACOM = ADR_CFC+0x07 ;Status / Command
CLOCK 8564 .equ CF_DecCont = ADR_CFC+0x0E ;
90 DAYS
DELAYS
;Class 1
CALL ID
;Upon receipt of a Class 1 command, the CompactFlash Storage Card sets BSY
DTMF 314 ;within 400 nsec.
PWM 6CH
PWM 10K ;Class 2
ENCODE ;Upon receipt of a Class 2 command, the CompactFlash Storage Card sets BSY
;within 400 nsec, sets up the sector buffer for a write operation, sets DRQ
STH-11 ;within 700 usec, and clears BSY within 400 nsec of setting DRQ.
ATMEL CORP
;Class 3
AVR
;Upon receipt of a Class 3 command, the CompactFlash Storage Card sets BSY
BUTTERFLY ;within 400 nsec, sets up the sector buffer for a write operation, sets DRQ
AVR BOOK ;within 20 msec (assuming no re-assignments), and clears BSY within 400 nsec
;of setting DRQ.

;Table 37: CF-ATA Command Set

;
;Class COMMAND Code FR SC SN CY DH LBA
;1 Check Power Mode E5h or 98h - - - - D -
;1 Execute Drive Diagnostic 90h - - - - D -
;1 Erase Sector(s) C0h - Y Y Y Y Y
;1 Flush Cache E7h - - - - D -
;2 Format Track 50h - Y - Y Y Y
;1 Identify Drive ECh - - - - D -
;1 Idle E3h or 97h - Y - - D -
;1 Idle Immediate E1h or 95h - - - - D -
;1 Initialize Drive Parameters 91h - Y - - Y -
;1 Key Management Structure Read B9 Feature 0-127 C C C C D C -
;1 Key Management Read Keying Material B9 Feature 80 C C C C D C -
;2 Key Management Change Key Management Value B9 Feature 81 C C C C D C -
;1 NOP 00h - - - - D -
;1 Read Buffer E4h - - - - D -
;1 Read Long Sector 22h or 23h - - Y Y Y Y
;1 Read Multiple C4h - Y Y Y Y Y
;1 Read Sector(s) 20h or 21h - Y Y Y Y Y
;1 Read Verify Sector(s) 40h or 41h - Y Y Y Y Y
;1 Recalibrate 1Xh - - - - D -
;1 Request Sense 03h - - - - D -
;1 Security Disable Password F6h - - - - D -
;1 Security Erase Prepare F3h - - - - D -
;1 Security Erase Unit F4h - - - - D -
;1 Security Freeze Lock F5h - - - - D -
;1 Security Set Password F1h - - - - D -
;1 Security Unlock F2h - - - - D -
;1 Seek 7Xh - - Y Y Y Y
;1 Set Features EFh Y - - - D -
;1 Set Multiple Mode C6h - Y - - D -
;1 Set Sleep Mode E6h or 99h - - - - D -
;1 Standby E2h or 96h - - - - D -
;1 Standby Immediate E0h or 94h - - - - D -
;1 Translate Sector 87h - Y Y Y Y Y
;1 Wear Level F5h - - - - Y -
;2 Write Buffer E8h - - - - D -
;2 Write Long Sector 32h or 33h - - Y Y Y Y
;3 Write Multiple C5h - Y Y Y Y Y
;3 Write Multiple w/o Erase CDh - Y Y Y Y Y
;2 Write Sector(s) 30h or 31h - Y Y Y Y Y
;2 Write Sector(s) w/o Erase 38h - Y Y Y Y Y
;3 Write Verify 3Ch - Y Y Y Y Y
;
;Definitions:
;FR = Features Register
;SC = Sector Count Register
;SN = Sector Number Register
;CY = Cylinder Registers
;DH = Card/Drive/Head Register
;LBA = Logical Block Address Mode Supported (see command descriptions for use).
;Y - The register contains a valid parameter for this command. For the Drive/Head
Register Y
;means both the CompactFlash Storage Card and head parameters are used; D - only the
;CompactFlash Storage Card parameter is valid and not the head parameter; C - The
register
;contains command specific data (see command descriptions for use).
;

;CF-ATA Command Set

.equ CF_CMD_READ_SEC = 0x20
.equ CF_CMD_WRITE_SEC = 0x30
.equ CF_CMD_IDENTIFY = 0xEC

.equ CFRDY = 2 ;bit 2 = 1 CF ready

.equ CFVS1 = 3 ;bit 3 = 0 CF in slot

;
***************************************************************************************
;*** Definition of the status register bits
;***
;***
Bit7
Bit0
;*** BSY DRDY DWF DSC
DRQ CORR IDX ERR
;
***************************************************************************************
.equ CFC_STATUS_BSY = 0x80 ;Busy flag
.equ CFC_STATUS_DRDY = 0x40 ;Drive ready
.equ CFC_STATUS_DWF = 0x20 ;Drive write fault
.equ CFC_STATUS_DSC = 0x10 ;Drive seek complete
.equ CFC_STATUS_DRQ = 0x08 ;Data request
.equ CFC_STATUS_CORR = 0x04 ;Corrected data
.equ CFC_STATUS_IDX = 0x02 ;Index
.equ CFC_STATUS_ERR = 0x01 ;Error

;
;***************************************************************************
;**** VARIABLES
.DSEG

;***************************************************************************
.ESEG

;***************************************************************************
;**** CODE SEG
;***************************************************************************
.CSEG

;********************************************************
;CFRdy
;
; Wait until CF not busy
;
; Out: c= 0 no error
; 1 error
;
; Alt: R16,R17
;
CFHWRdy:
lds R16,ADR_CFST
bst R16,CFVS1 ;CF inserted?
brtc CFHWRdy0
rjmp CFDrvError
CFHWRdy0:
lds R16,ADR_CFST
bst R16,CFRDY ;CF ready?
brtc CFHWRdy
clc
ret

;********************************************************
;CFWaitDRQ
;
; Wait until Data will available
;
; Out: c= 0 no error
; 1 error
;
; Alt: R16,R17
;
CFWaitDRQ:
rcall CFHWRdy
brcc CFWaitDRQ00
ret
CFWaitDRQ00:
lds R16,CF_STACOM
bst R16,0
brtc CFWaitDRQ0
CFWaitErr:
ldi R16,low(0xFFF0) ;Error in last command
ldi R17,high(0xFFF0) ;ide keresunk egy error kodot!!!
sec
ret

CFWaitDRQ0:
andi R16,0xF8
cpi R16,0x58
brne CFWaitDRQ
clc
ret

;********************************************************
;CFWaitReady
;
; Wait until CF will ready
;
; Out: c= 0 no error
; 1 error
;
; Alt: R16,R17
;
CFWaitReady:
rcall CFHWRdy
brcc CFWaitRdy0
ret
CFWaitRdy0:
lds R16,CF_STACOM
bst R16,0
brts CFWaitErr
CFWaitReady01:
andi R16,0xF0
cpi R16,0x50
brne CFWaitReady
clc
ret

;********************************************************
;CFReadSector
;
; In: R13:R12:R11:R10 - LBA sector number
; Page: Y - Pointer to Data Buffer [512 byte]
; Z - Phis. Drive Descriptor
;
; Out: c= 0 no error
; 1 error
;
CFReadSector:
ldd R0,Z+MaxSector+0
ldd R1,Z+MaxSector+1
ldd R2,Z+MaxSector+2
ldd R3,Z+MaxSector+3
cp R10,R0
cpc R11,R1
cpc R12,R2
cpc R13,R3
brcs CFReadSec00

ldi R16,low(ERROR_SECTOR_NOT_FOUND) ;Sector number too big

ldi R17,high(ERROR_SECTOR_NOT_FOUND)
sec
ret
CFReadSec00:
std Z+CurrentSector+0,R10
std Z+CurrentSector+1,R11
std Z+CurrentSector+2,R12
std Z+CurrentSector+3,R13

rcall CFWaitReady
brcc CFReadSec01
ret ;Error in last command
CFReadSec01:
ldi R16,1
sts CF_SECCOUNT,R16
nop
sts CF_LBA0,R10 ;D7..D0
nop
sts CF_LBA1,R11 ;D15..D8
nop
sts CF_LBA2,R12 ;D23..D16
ldi R16,0x0F
and R16,R13
ori R16,0xE0 ;set LBA mode
sts CF_LBA3,R16 ;D27..D24 + LBA mode + Drive0

ldi R16,CF_CMD_READ_SEC
sts CF_STACOM,R16 ;Set Read Sector Command

ldi XL,0
ldi XH,1 ;if X==0 -> X=256 word;

movw R0,YL ;save Y reg.

rcall CFWaitDrq
brcc CFReadSec02
ret ;Drive error
CFReadSec02:
lds R16,ADR_CFST
bst R16,CFVS1 ;CF inserted?
brts CFDrvError
bst R16,CFRDY ;CF ready?
brtc CFReadSec02

lds R16,CF_EvenData
st Y+,R16
lds R16,CF_OddData
st Y+,R16
sbiw XL,1
brne CFReadSec02

movw YL,R0 ;restore Y reg.

clc
ret

CFDrvError:
ldi R16,low(ERROR_BAD_UNIT)
ldi R17,high(ERROR_BAD_UNIT) ;Drive not present
sec
ret

;********************************************************
;CFWriteSector
;
; In: R13:R12:R11:R10 - LBA sector number
; Page: Y - Pointer to Data Buffer [512 byte]
; Z - Phis. Drive Descriptor
;
; Out: c= 0 no error
; 1 error
;
CFWriteSector:
ldd R0,Z+MaxSector+0
ldd R1,Z+MaxSector+1
ldd R2,Z+MaxSector+2
ldd R3,Z+MaxSector+3
cp R10,R0
cpc R11,R1
cpc R12,R2
cpc R13,R3
brcs CFWriteSec00

ldi R16,low(ERROR_SECTOR_NOT_FOUND) ;Sector number too big

ldi R17,high(ERROR_SECTOR_NOT_FOUND)
sec
ret
CFWriteSec00:
rcall CFWaitReady
brcc CFWriteSec01
ret ;Error in last command
CFWriteSec01:
ldi R16,1
sts CF_SECCOUNT,R16
nop
sts CF_LBA0,R10 ;D7..D0
nop
sts CF_LBA1,R11 ;D15..D8
nop
sts CF_LBA2,R12 ;D23..D16
ldi R16,0x0F
and R16,R13
ori R16,0xE0 ;set LBA mode
sts CF_LBA3,R16 ;D27..D24 + LBA mode + Drive0
ldi R16,CF_CMD_WRITE_SEC
sts CF_STACOM,R16 ;Write sector command

ldi XL,0
ldi XH,1 ;if X==0 -> X=256 word;

movw R0,YL

rcall CFWaitDrq
brcc CFWriteSec02
ret ;Drive error
CFWriteSec02:
lds R16,ADR_CFST
bst R16,CFVS1 ;CF inserted?
brts CFDrvError
bst R16,CFRDY ;CF ready?
brtc CFWriteSec02

ld R16,Y+
sts CF_EvenData,R16
ld R16,Y+
sts CF_OddData,R16
sbiw XL,1
brne CFWriteSec02

movw YL,R0
clc
ret

;********************************************************
;CFResetDevice
;
; In: -
;
; Out: c= 0 no error
; 1 error R17:R16 error code
;
CFResetDevice:
ldi R16,0b00000100 ;Force SW reset
sts ADR_CFC+0x0E,R16 ;Device Control Register
ldi R16,64
CFRes0: dec R17
brne CFRes0
dec R16
brne CFRes0
clr R16
sts ADR_CFC+0x0E,R16 ;Device Control Register
rcall CFWaitReady
ret

;********************************************************
;CFIdentify
;
; In: Z - Phis. Drive Descriptor
; Page: Y - Pointer to temporary Data Buffer [512 byte]
;
; Out: c= 0 no error
; 1 error
;
CFIdentify:
rcall CFWaitReady
brcc CFIdent01
ret ;Error code in R17:R16
CFIdent01:
ldi R16,1
sts CF_SECCOUNT,R16
clr R16
sts CF_LBA0,R16
nop
sts CF_LBA1,R16
nop
sts CF_LBA2,R16
ldi R16,0xE0
sts CF_LBA3,R16
ldi R16,CF_CMD_IDENTIFY
sts CF_STACOM,R16

ldi XL,0 ;read fixed 256 word

ldi XH,1
movw R0,YL

call CFWaitDRQ
brcc CFIdent02
ret ;Drive error
CFIdent02:
lds R16,CF_EvenData
st Y+,R16
nop
lds R16,CF_OddData
st Y+,R16
sbiw XL,1
brne CFIdent02

movw YL,R0

clr R0
ldd R16,Y+0 ;CF IDs: 848Ah
cpi R16,0x8A
brne CFIDs0
ldd R16,Y+1
cpi R16,0x84
brne CFIDs0
inc R0
CFIDs0:
std Z+MediaFlag,R0 ;Store CF ID

ldi R16,RemovableMedia
std Z+MediaType,R16

ldi R16,0x80
std Z+DiskNumber,R16 ;First HDD => HDD0

ldd R16,Y+2 ;Default tracks/cylinders

ldd R17,Y+3
std Z+Cylinders+0,R16
std Z+Cylinders+1,R17

ldd R16,Y+6 ;Default Heads

std Z+Heads,R16

ldd R16,Y+12 ;default Sectors per track

std Z+SectorsPerTrack,R16

ldd R16,Y+14 ;Number of Sectors per Card

std Z+MaxSector+2,R16 ;MSW -LSW !!!
ldd R16,Y+15
std Z+MaxSector+3,R16
ldd R16,Y+16
std Z+MaxSector+0,R16
ldd R16,Y+17
std Z+MaxSector+1,R16

clc
ret

Programming the AVR Microcontrollers in Machine Language

AVR
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump
to: navigation, search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further
developed at Atmel Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers. These are 32-bit
RISC devices featuring SIMD and DSP instructions, along with many additional
features for audio and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line
of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for
Advanced Virtual RISC. It's also rumoured to stand for the company's founders:
Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1
Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3
EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C Language
Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7
Other AVR Links [edit] Device Overview The AVR is a Harvard architecture
machine with programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die, removing the need for
external memory (though still available on some devices). [edit] Program
Memory Program instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in length. The Flash
memory is addressed using 16 bit word sizes. The size of the program memory
is indicated in the naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit]
Data Memory and Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are mapped in as the first
thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers
(002016-005F16). The actual usable RAM starts after both these sections
(address 006016). (Note that the I/O register space may be larger on some more
extensive devices, in which case memory mapped I/O registers will occupy a
portion of the SRAM.) Even though there are separate addressing schemes and
optimized opcodes for register file and I/O register access, all can still be
addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all
devices have on-die EEPROM. This is most often used for long-term parameter
storage to be retrieved even after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design. The next machine
instruction is fetched as the current one is executing. Most instructions take just
one or two clock cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were designed for the efficient
execution of compiled C code. The AVR instruction set is more orthogonal than
most eight-bit microcontrollers, however, it is not completely regular: Pointer
registers X, Y, and Z have addressing capabilities that are different from each
other. Register locations R0 to R15 have different addressing capabilities than
register locations R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even
though they are complementary instructions. CLR set all bits to zero and SER
sets them to one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the same machine
code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations
such as EOR modify flags while moves/loads/stores/branches such as LDI do
not.) [edit] Speed The AVR line can normally support clock speeds from 0-
16MHz, with some devices reaching 20MHz. Lower powered operation usually
requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing
the need for external clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit]
Development AVRs have a large following due to the free and inexpensive
development tools available, including reasonably priced development boards
and free development software. The AVRs are marketed under various names
that share the same basic core but with different peripheral and memory
combinations. Some models (notably, the ATmega range) have additional
instructions to make arithmetic faster. Compatibility amongst chips is fairly
good. See external links for sites relating to AVR development. [edit] Features
Current AVRs offer a wide range of features: RISC Core Running Many Single
Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal,
Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-System Programmable
using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with
Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator
Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire
Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART)
(As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-speed (HID) software
emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or
Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller
Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout
Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v
Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler
programming language Atmel AVR machine programming language Atmel AVR
From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to:
navigation, search The AVRs are a family of RISC microcontrollers from Atmel.
Their internal architecture was conceived by two students: Alf-Egil Bogen and
Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further
developed at Atmel Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers. These are 32-bit
RISC devices featuring SIMD and DSP instructions, along with many additional
features for audio and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line
of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for
Advanced Virtual RISC. It's also rumoured to stand for the company's founders:
Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1
Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3
EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C Language
Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7
Other AVR Links [edit] Device Overview The AVR is a Harvard architecture
machine with programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die, removing the need for
external memory (though still available on some devices). [edit] Program
Memory Program instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in length. The Flash
memory is addressed using 16 bit word sizes. The size of the program memory
is indicated in the naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit]
Data Memory and Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are mapped in as the first
thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers
(002016-005F16). The actual usable RAM starts after both these sections
(address 006016). (Note that the I/O register space may be larger on some more
extensive devices, in which case memory mapped I/O registers will occupy a
portion of the SRAM.) Even though there are separate addressing schemes and
optimized opcodes for register file and I/O register access, all can still be
addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all
devices have on-die EEPROM. This is most often used for long-term parameter
storage to be retrieved even after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design. The next machine
instruction is fetched as the current one is executing. Most instructions take just
one or two clock cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were designed for the efficient
execution of compiled C code. The AVR instruction set is more orthogonal than
most eight-bit microcontrollers, however, it is not completely regular: Pointer
registers X, Y, and Z have addressing capabilities that are different from each
other. Register locations R0 to R15 have different addressing capabilities than
register locations R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even
though they are complementary instructions. CLR set all bits to zero and SER
sets them to one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the same machine
code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations
such as EOR modify flags while moves/loads/stores/branches such as LDI do
not.) [edit] Speed The AVR line can normally support clock speeds from 0-
16MHz, with some devices reaching 20MHz. Lower powered operation usually
requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing
the need for external clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit]
Development AVRs have a large following due to the free and inexpensive
development tools available, including reasonably priced development boards
and free development software. The AVRs are marketed under various names
that share the same basic core but with different peripheral and memory
combinations. Some models (notably, the ATmega range) have additional
instructions to make arithmetic faster. Compatibility amongst chips is fairly
good. See external links for sites relating to AVR development. [edit] Features
Current AVRs offer a wide range of features: RISC Core Running Many Single
Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal,
Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-System Programmable
using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with
Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator
Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire
Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART)
(As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-speed (HID) software
emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or
Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller
Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout
http://avr-asm.tripod.com/flashcard.html (1 of 2)1/20/2009 8:49:58 PM
16 BIT MATH (AVR 202)

Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v

Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler
programming language Atmel AVR machine programming language Atmel AVR
From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to:
navigation, search The AVRs are a family of RISC microcontrollers from Atmel.
Their internal architecture was conceived by two students: Alf-Egil Bogen and
Vegard Wollan, at the Norwegian Institute of Technology (NTH] and further
developed at Atmel Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers. These are 32-bit
RISC devices featuring SIMD and DSP instructions, along with many additional
features for audio and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to the 8-bit RISC line
of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for
Advanced Virtual RISC. It's also rumoured to stand for the company's founders:
Alf and Vegard, who are evasive when questioned about it. Contents [hide] 1
Device Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3
EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C Language
Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7
Other AVR Links [edit] Device Overview The AVR is a Harvard architecture
machine with programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die, removing the need for
external memory (though still available on some devices). [edit] Program
Memory Program instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in length. The Flash
memory is addressed using 16 bit word sizes. The size of the program memory
is indicated in the naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit]
Data Memory and Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are mapped in as the first
thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers
(002016-005F16). The actual usable RAM starts after both these sections
(address 006016). (Note that the I/O register space may be larger on some more
extensive devices, in which case memory mapped I/O registers will occupy a
portion of the SRAM.) Even though there are separate addressing schemes and
optimized opcodes for register file and I/O register access, all can still be
addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all
devices have on-die EEPROM. This is most often used for long-term parameter
storage to be retrieved even after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design. The next machine
instruction is fetched as the current one is executing. Most instructions take just
one or two clock cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were designed for the efficient
execution of compiled C code. The AVR instruction set is more orthogonal than
most eight-bit microcontrollers, however, it is not completely regular: Pointer
registers X, Y, and Z have addressing capabilities that are different from each
other. Register locations R0 to R15 have different addressing capabilities than
register locations R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not, even
though they are complementary instructions. CLR set all bits to zero and SER
sets them to one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the same machine
code as] EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations
such as EOR modify flags while moves/loads/stores/branches such as LDI do
not.) [edit] Speed The AVR line can normally support clock speeds from 0-
16MHz, with some devices reaching 20MHz. Lower powered operation usually
requires a reduced clock speed. All AVRs feature an on-chip oscillator, removing
the need for external clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit]
Development AVRs have a large following due to the free and inexpensive
development tools available, including reasonably priced development boards
and free development software. The AVRs are marketed under various names
that share the same basic core but with different peripheral and memory
combinations. Some models (notably, the ATmega range) have additional
instructions to make arithmetic faster. Compatibility amongst chips is fairly
good. See external links for sites relating to AVR development. [edit] Features
Current AVRs offer a wide range of features: RISC Core Running Many Single
Cycle Instructions Multifunction, Bi-directional I/O Ports with Internal,
Configurable Pull-up Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-System Programmable
using ICSP, JTAG, or High Voltage methods Optional Boot Code Section with
Independent Lock Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator
Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire
Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART)
(As used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-speed (HID) software
emulation Ethernet Controller Support Universal Serial Interface (USI) for Two or
Three-Wire Synchronous Data Transfer Analog Comparators LCD Controller
Support 10-Bit A/D Converters, with multiplex of up to 16 channels Brownout
Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v
Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR assembler
programming language Atmel AVR machine programming language

http://avr-asm.tripod.com/flashcard.html (2 of 2)1/20/2009 8:49:58 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

SMART MEDIA MANAGER FOR SMIL

HOME
RETRO_DAN
;
ASM FORUM ***************************************************************************
ASM MATH ;
; File Name :'SmartM.asm"
TUTORIAL #1
; Title :SmartMedia Driver for
TUTORIAL #2 External SMIL Controller
TUTORIAL #3 ; Date :2003.05.05.
; Version :1.11.0
MATH 200 ; Support telephone :+36-70-333-4034, old: +36-30-9541-
MATH 200b 658 VFX
; Support fax :
MATH 201 ; Support Email :info@vfx.hu
MATH 202 ; Target MCU :ATmega128
;
MATH 32X
;
MATH YX ***************************************************************************
; D E S C R I P T I O N
DIV16 XX
;
DIV 24 24 ; VFX SMIL Smart Media Manager
DIV 3216 ;
;Why is FTL needed?
FLOAT 128 ; • Flash are not 100% perfect . It needs bad block
SQRT16 management.
; • Flash is erased in blocks(typical 16KB) larger
MATH 202 than disk sectors(512Byte)
MATH 202 ; • Flash has a limited number of erase cycles (1M
Cycles). So it needs wear-leveling algorithm.
DEC ASCII
; • Flash is essentially non-writable (must be erased
INT ASCII before it can be written)
;
HX2ASC
; · Converts the sector addresses addressed by the
AVG8 222 host to physical addresses of Flash Memory
FFT7 ; · Converts host requests into the programming/
erasing algorithms of associated Flash technology
COPY 102 ; · Detects the error and replaces the encountered
LPM 108 bad sectors with the good by mapping them out
;
EPROM 100 --------------------------------------------------------------------------------------
SER EPROM ; Linear
address Logical Address
DFLASH AT45
; - Address Map, Address Configuration
FLASH CARD ; I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
;1st Cycle A0 A1 A2 A3 A4 A5 A6
VFX SMIL
A7 CA0 ~ CA7 : column address
VFX MEM ;2nd Cycle A9 A10 A11 A12 A13 A14 A15
SORT 220 A16 PA0 ~ PA7 : page address 1
;3rd Cycle A17 A18 A19 A20 A21 A22 A23
CRC 236 A24 PA8 ~ PA15 : page address 2
XMODEM REC ;4th Cycle A25
A26 PA16 ~ PA23 : page address 3
UART 304 ;
UART 305 ;Model Valid Page Address Fixed Low
;2MB PA0 ~ PA12 PA13 ~ PA15
UART 128
;4MB PA0 ~ PA12 PA13 ~ PA15
UART BUFF ;8MB PA0 ~ PA13 PA14 ~ PA15
;16MB PA0 ~ PA14 PA15
USB 232
;32MB PA0 ~ PA15 -
AVR ISP ;64MB PA0 ~ PA16 PA17 ~ PA23
ISP 2313 ;128MB PA0 ~ PA17 PA18 ~ PA23
;
ISP 1200 ;
AVR SPI --------------------------------------------------------------------------------------
; Considerations for High Density Considerations for
I2C 300 High Density SmartMedia
I2C 302 ; Zone-based block management for 32MB,64MB and 128MB
;
I2C TWI26
;Zone Physical Block Description
I2C/TWI 128 ; 0 0 CIS/Identify Drive
I2C/TWI AT8 Information Area
; 0 1 ~ 1023 Data Area (Logical Block :
DALLAS-1W 0 ~ 999)
DALLAS CRC ; 1 0 ~ 1023 Data Area (Logical
Block :1000 ~1999)
ETHNET 8019 ; ...
TEA ; Last 0 ~ 1023 Data Area (Logical Block :
Zone x 1000 + 999 )
ADC 128 ;
ADC 10B ;* CIS/Identify Drive Information Area ==>Zone 0
; Each zone has 1000 data blocks.
ADC 400
;
ADC 401 --------------------------------------------------------------------------------------
THERM 232 ;
; CIS (Card Information System) Area 1 and CIS (Card
IRD 410 Information System) Area (1 and 2) Physical BLOCK 1
LCD HD44 ;
;Addr Data Contents
LCD 2313 ;
LCD44 2313 ;00 01h Tuple ID(CIS TPL_Device)
;01 03h Link to Next Tuple
KBD 240 ;02 D9h Device Type : I/O, Rate : 250ns
MUX 242 ;03 01h Device Size : 2 K Byte
;04 FFh End of Device ID Tuple
KBD PS2
;05 01h Tuple ID(CIS TPL_JEDEC_C)
KBD PC/128 ;06 20h Link to Next Tuple
PS2 EMU ;07 DFh JEDEC Manufacture ID(PC Card ATA)
;08 18h JEDEC Device ID(VPP not required)
BOOT MG8 ;09 02h Tuple ID(CIS TPL_MANF ID)
BOOT DR8 ;0A 04h Link to Next Tuple
;0B 00h Manufacture Code
ALM CLK ;0C 00h Manufacture Code
CLOCK 8564 ;0D 00h Manufacture Info.
;0E 00h Manufacture Info.
90 DAYS
;0F 21h Tuple ID(CIS TPL_FUNC ID)
DELAYS ;10 02h Link to Next Tuple
;11 04h PL FID_FUNCTION
CALL ID
;12 01h TPL_FID_SYS INIT
DTMF 314 ;13 22h Tuple ID(CIS TPL_FUNCE)
PWM 6CH ;14 02h Link to Next Tuple
;15 01h Disk Device Interface Tuple
PWM 10K ;16 01h PC Card ATA Interface
ENCODE ;17 22h Tuple ID(CIS TPL_FUNCE)
;18 03h Link to Next Tuple
STH-11 ;19 02h PC Card ATA Extension Tuple
ATMEL CORP ;1A 04h ATA Function Byte1
;1B 07h ATA Function Byte2
AVR
;1C 1Ah Tuple ID(CIS TPL_CONFIG)
BUTTERFLY ;1D 05h Link to Next Tuple
AVR BOOK ;1E 01h Field Size Byte
;1F 03h Last Entry in the Card Configuration
Table
;20 00h CCR Base Address(Low-order Byte)
;21 02h CCR Base Address(High-order Byte)
;22 0Fh CCR Present Mask
;23 1Bh Tuple ID(CIS TPL_CFTABLE_ENTRY)
;24 08h Link to Next Tuple
;25 C0h Configuration Table Index Byte
;26 C0h Interface Description Field
;27 A1h Feature Selection Byte
;28 01h Power Parameter Selection Byte
;29 55h Power Voltage(5V)
;2A 08h Memory Space(Low-order byte)
;2B 00h Memory Space(High-order byte)
;2C 20h Miscellaneous (ex: CCSR power down)
;2D 1Bh Tuple ID(CIS TPL_CFTABLE_ENTRY)
;2E 0Ah Link to Next Tuple
;2F C1h Configuration Table Index Byte
;30 41h Interface Description Field
;31 99h Feature Selection Byte
;32 01h Power Parameter Selection Byte
;33 55h Power Voltage(5V)
;34 64h I/O Space Description Byte
;35 F0h Interrupt IRQ Condition Info.
;36 FFh Interrupt IRQs 0 to 7
;37 FFh Interrupt IRQs 8 to 15
;38 20h Miscellaneous (ex: CCSR power down)
;39 1Bh Tuple ID [I/O Primary]
;3A 0Ch Link to Next Tuple
;3B 82h Configuration Table Index Byte
;3C 41h Interface Description Field
;3D 18h Feature Selection Byte
;3E EAh I/O Space Description Byte
;3F 61h I/O Range Description Byte
;40 F0h I/O Address Range(01F0h-01F7h)
;41 01h I/O Address Range(01F0h-01F7h)
;42 07h 8 Bytes
;43 F6h I/O Address Range(03F6h-03F7h)
;44 03h I/O Address Range(03F6h-03F7h)
;45 01h 2 Bytes
;46 EEh IRQ Condition Info. (IRQ14)
;47 1Bh Tuple ID[I/O secondary]
;48 0Ch Link to Next Tuple
;49 83h Configuration Table Index Byte
;4A 41h Interface Description Field
;4B 18h Feature Selection Byte
;4C EAh I/O Space Description Byte
;4D 61h I/O Range Description Byte
;4E 70h I/O Address Range(0170h-0177h)
;4F 01h I/O Address Range(0170h-0177h)
;50 07h 8 Bytes
;51 76h I/O Address Range(0376h-0377h)
;52 03h I/O Address Range(0376h-0377h)
;53 01h 2 Bytes
;54 EEh IRQ Condition Info. (IRQ14)
;55 15h Tuple ID(CIS TPL_VERS_1)
;56 14h Link to Next Tuple
;57 05h Major Version Number[Ver.5]
;58 00h Minor Version Number[Ver.0]
;59 20h Name of Manufacture
;5A 20h Name of Manufacture
;5B 20h Name of Manufacture
;5C 20h Name of Manufacture
;5D 20h Name of Manufacture
;5E 20h Name of Manufacture
;5F 20h Name of Manufacture
;60 00h End of Manufacture Name
;61 20h Name of Product
;62 20h Name of Product
;63 20h Name of Product
;64 20h Name of Product
;65 00h End of Product Name
;66 30h Product Version “0”
;67 2Eh Product Version "."
;68 30h Product Version "0"
;69 00h End of Product Version
;6A FFh End of Product Info. Tuple
;6B 14h CIS TPL_NO_LINK
;6C 00h Link to Next Tuple
;6D FFh CIS TPL_END
;6E-7F 00h Null-Tuple
;
;
--------------------------------------------------------------------------------------
;
; Logical Format Parameter
;
; 1 MB 2 MB 4 MB 8 MB 16
MB 32 MB 64 MB 128 MB
;NumCylinder 125 125 250
250 500 500 500 500
;NumHead 4 4 4 4
4 8 8 16
;NumSector 4 8 8 16
16 16 32 32
;SumSector 2,000 4,000 8,000 16,000
32,000 64,000 128,000 256,000
;SectorSize 512 512 512 512
512 512 512 512
;Logical Block Size 4k 4k 8k 8k
16k 16k 16k 16k
;Unformatted 1MB 2MB 4MB
8MB 16MB 32MB 64MB 128MB
;Formatted 0.977MB 1.953MB 3.906MB
7.813MB 16.63MB 31.25MB 62.5MB 125MB
;
; Physical Format Parameter
;
;Page Size (byte) 256+8 256+8 512+16 512
+16 512+16 512+16 512+16 512+16 (byte/sectror)
;Number of page/block ? 16 16
16 32 32 32 32 (sectror/Cluster)
;Number of block/device ? 512 512
1024 1024 2048 4096 8192 (Cluster)

;
--------------------------------------------------------------------------------------
; Sector Data Structure
; [1 Sector = 1 Page]
; 0-255 Data Area-1
; 256-511 Data Area-2
;
; Spare Area Information (4 ~ 128 MB)
; 512-515 Reserved Area
; 516 Data/User Status Flag/Area
; 517 Block Status Flag/Area
; 518-519 Block Address Area-1
; 520-522 ECC Area-2
; 523-524 Block Address Area-2
; 525-527 ECC Area-1
;
;
--------------------------------------------------------------------------------------
; Block Address Area Information
; [Block Address Configuration]
;D7 D6 D5 D4 D3 D2 D1 D0 1,2 MB
SM 4,8,16 MB and above SM
;
;0 0 0 1 0 BA9 BA8 BA7 262 bytes(even)
518, 523 bytes
; 259 bytes(odd)
;
;BA6 BA5 BA4 BA3 BA2 BA1 BA0 P 263 bytes(even)
519, 524 bytes
; 260 bytes(odd)
;
;BA9 ~ BA0 : Block Address (values=0 through n,where n
= maximum logical block count - 1)
;P : Even Parity bit
;
;
--------------------------------------------------------------------------------------
; Block_a Parameter Definition
; - Used Valid Block is block_a[ Physical block number]
= bl_addr(Block Address value)
; - Invalid Block is block_a[Physical block number] =
0xffee(Invalid Mark is defined as ‘ 0xffee’ )
; - CIS Block is block_a[Physical block number] = 0
(Actual Block Addess Value is ‘ 0x0000’ .)
; - Unused Valid Block[Physical block number] = 0xffff
;
;
--------------------------------------------------------------------------------------
;
; Support Devices
; K9S2808V0M-SSB0 16M x 8 bit SmartMedia Card - tested
; [32768 rows(pages), 528 columns]
;
;
; Command Latch Enable(CLE)
; The CLE input controls the path activation for
commands sent to the
; command register. When active high, commands are
latched into the
; command register through the I/O ports on the
rising edge of the
; WE signal.
;
; Address Latch Enable(ALE)
; The ALE input controls the activating path for
address to the internal
; address registers. Addresses are latched on the
rising edge of WE with
; ALE high.
;
; Chip Enable(CE)
; The CE input is the device selection control. When
CE goes high during
; a read operation the device is returned to standby
mode.
; However, when the device is in the busy state
during program or erase,
; CE high is ignored, and does not return the device
to standby mode.
;
; Write Enable(WE)
; The WE input controls writes to the I/O port.
Commands, address and data
; are latched on the rising edge of the WE pulse.
;
; Read Enable(RE)
; The RE input is the serial data-out control, and
when active drives the
; data onto the I/O bus. Data is valid tREA after the
falling edge of RE
; which also increments the internal column address
counter by one.
;
; I/O Port : I/O 0 ~ I/O 7
; The I/O pins are used to input command, address and
data, and to output
; data during read operations. The I/O pins float to
high-z when the chip
; is deselected or when the outputs are disabled.
;
; Write Protect(WP)
; The WP pin provides inadvertent write/erase
protection during power
; transitions. The internal high voltage generator is
reset when the
; WP pin is active low.
;
; Ready/Busy(R/B)
; The R/B output indicates the status of the device
operation. When low,
; it indicates that a program, erase or random read
operation is
; in process and returns to high state upon
completion. It is an open
; drain output and does not float to high-z condition
when the chip
; is deselected or when outputs are disabled.
;
;
;
***************************************************************************
; M O D I F I C A T I O N H I S T O R Y
;
;
; rev. date who why
; ---- ---------- ---
------------------------------------
; 0.01 2002.07.19 VFX Creation
; 1.10 2003.02.02 VFX Redesign all
functions
; 1.11 2003.05.05 VFX Remove IO pin and
change to XMEM mode
;
;
***************************************************************************
;Hardware
;
***************************************************************************
;*
;* SYSCLK: f=16.000 MHz (T= 62.5 ns)
;*
;
***************************************************************************
;
;

;
***************************************************************************
;* Const Def

;SmartMedia Commands
.EQU SM_ReadLowHalf =
0x00h ;Page read A
.EQU SM_ReadHiHalf = 0x01h
.EQU SM_ReadEnd =
0x50h ;Page read C
.EQU SM_ReadID =
0x90h ;Read ID
.EQU SM_ReadUnique =
0x91h ;Read Unique 128 bit
.EQU SM_Reset =
0xFFh ;Device reset
.EQU SM_PageProgram =
0x80h ;Ready to write, Serial Data Input
.EQU SM_PageProgramTrue =
0x10h ;Start to write page, auto program (Toshiba)
.EQU SM_PageProgramDumy =
0x11h ;
.EQU SM_PageProgramMultiBlk =
0x15h ;
.EQU SM_BlockErase =
0x60h ;Erase block (block#)
.EQU SM_BlockErase2nd =
0xD0h ;Erase block (start)
.EQU SM_ReadStatus =
0x70h ;Read status
.EQU SM_ReadMultiPlaneStatus =
0x71h ;

;SMIL Commands

.equ SMIL_Standby = 0x00h ;Standby

Mode

.equ SMIL_RM_ReadData = 0x14h ;Data

Read ( SmartMedia Data Read )
.equ SMIL_RM_WriteCmd = 0x15h ;Command
Write ( SmartMedia Data Read )
.equ SMIL_RM_WriteAddr = 0x16h ;Address
Write ( SmartMedia Data Read )
.equ SMIL_RM_WriteData = 0x14h ;Data
Write ( SmartMedia Data Read )

.equ SMIL_WM_ReadData = 0x94h ;Data

Read ( SmartMedia Data Write)
.equ SMIL_WM_WriteCmd = 0x95h ;Command
Write ( SmartMedia Data Write)
.equ SMIL_WM_WriteAddr = 0x96h ;Address
Write ( SmartMedia Data Write)
.equ SMIL_WM_WriteData = 0x94h ;Data
Write ( SmartMedia Data Write)

.equ SMIL_ResetECCLogic = 0b01100000

.equ SMIL_RWwithECC = 0b00100000
.equ SMIL_RWwithoutECC = 0b00000000

;SM Manufacturer ID
.equ MakerSamsung = 0xEC
.equ MakerToshiba = 0x98

;SM IDs, only 3.3V or 2.7-3.6V devices

.equ Sign05 = 0xA4 ;0.5 Mb
.equ Sign1 = 0x6E ;1 Mb
.equ Sign2 = 0xEA ;2 Mb Samsung
.equ Sign2a = 0x64 ;2 Mb Toshiba
.equ Sign4 = 0xE3 ;4 MB Samsung
.equ Sign4a = 0xE5 ;4 MB Toshiba
.equ Sign8 = 0xE6 ;8 Mb
.equ Sign16 = 0x73 ;16 MB
.equ Sign32 = 0x75 ;32 Mb
.equ Sign64 = 0x76 ;64 Mb
.equ Sign128 = 0x79 ;128 Mb

.EQU SM_UniqueIDcode = 0xA5

.EQU SM_MultiplaneSupportCode = 0xC0
.equ ExtendedID = 0x21

.equ SM_Protected =
7 ;bit = 1, media write protect
.equ SM_Busy =
6 ;bit = 1, media ready
.equ SM_Fail =
0 ;bit = 1, Fail

;SmFlags
.EQU SM_UniqueID = 7
.EQU SM_MultiplaneSupport = 6
.EQU SM_DeviceTooSmall =
5 ;Device < 16 MB
.EQU SM_DeviceUnkown =
4 ;Device Unknown

.equ W500us = SYSCLK/8000 ;Delay 500us units

of SYSCLK
.equ W10us = SYSCLK/160 ;Delay 10us

;
**************************************************************************
;* Hardware Def.
;

; External Controller Address def. by main.asm

;.equ ADR_SMDATA = 0x3F00 ;SmartMedia
Data Register
;.equ ADR_SMMODE = 0x3F01 ;SmartMedia
Mode Register
;.equ ADR_SMSTAT = 0x3F01 ;SmartMedia
Mode Register

;
***************************************************************************
;**** VARIABLES
.DSEG

;-Memory Card-----------Egymas utan kell aljanak --

Struct
;dont remove or insert any line here!!
SmManufacturerID: .byte 1 ; SM Manufacturer
code
SmDeviceCode: .byte 1 ; SM Device
Code
SmFlags: .byte 1 ; 7 bit = 1
UniqueID Supported
; 6 bit = 1
MultiPlane Supported
SmPages: .byte 3 ; Number of pages
(physical sectors)
SmPPB: .byte 1 ; Pages per
block
SmBlocks: .byte 2 ; Blocks per Devices

;end struct

SMDataBuffer: .byte 512 ;I/O Data

buffer

;
***************************************************************************
.ESEG

;
***************************************************************************
;**** CODE SEG
;
***************************************************************************
.CSEG

Init_SMedia:
ldi R16, SMIL_Standby
sts ADR_SMMODE,R16 ;SmartMedia
Controller is StandBy

clr R16
sts SmManufacturerID,R16 ;No valid
Card in socket
sts SmDeviceCode,R16
sts SmFlags,R16

rcall SM_ResetDevice ;Reset

SmartMedia

PrintSMType:
rcall SM_GetType ;Get
SmartMedia Type

lds R18,SmFlags
andi R18,(1<

Programming the AVR Microcontrollers in Machine Language

AVR
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© WebRing Inc. Search

Atmel AVR From Wikipedia, the free encyclopedia (Redirected

from Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing,
intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still
be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
http://avr-asm.tripod.com/vfxsmil.html (1 of 2)1/20/2009 8:50:36 PM
16 BIT MATH (AVR 202)

are different from each other. Register locations R0 to R15

have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language

http://avr-asm.tripod.com/vfxsmil.html (2 of 2)1/20/2009 8:50:36 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

VFX MEMORY MANAGER

HOME
RETRO_DAN
;
ASM FORUM ***************************************************************************
ASM MATH ;
; File Name :'memory.asm"
TUTORIAL #1
; Title :Memory Manager for VFX's
TUTORIAL #2 DataLog
TUTORIAL #3 ; Date :2003.08.03.
; Version :1.0.0
MATH 200 ; Support telephone :+36-70-333-4034, old: +36-30-9541-
MATH 200b 658 VFX
; Support fax :
MATH 201 ; Support Email :info@vfx.hu
MATH 202 ; Target MCU :ATmega128
;
MATH 32X
;
MATH YX ***************************************************************************
; D E S C R I P T I O N
DIV16 XX
;
DIV 24 24 ;
DIV 3216 ; MCB
; 0. byte - Type/Flag
FLOAT 128 ; 7. =1 last block
SQRT16 ; 6. =1 first block
; 5. =1 used block
MATH 202 ; 4. = nc
MATH 202 ; 3:0 = process number Hi part
; 1. byte - process number low part
DEC ASCII
; 2. word - low part of length
INT ASCII ; 4. byte - hi part of length
; 5. word - low part offset of prev. MCB
HX2ASC
; 7. byte - hi part offset of prev. MCB
AVG8 222 ;
FFT7 ;
***************************************************************************
COPY 102 ; M O D I F I C A T I O N H I S T O R Y
LPM 108 ;
;
EPROM 100 ; rev. date who why
SER EPROM ; ---- ---------- ---
------------------------------------
DFLASH AT45
; 0.01 2003.08.03 VFX Creation
FLASH CARD ;
;
VFX SMIL
***************************************************************************
VFX MEM ;Hardware
SORT 220 ;
***************************************************************************
CRC 236 ;*
XMODEM REC ;* SYSCLK: f=16.000 MHz (T= 62.5 ns)
;*
UART 304 ;
UART 305 ***************************************************************************
UART 128
.equ MCB_Type = 0
UART BUFF .equ MCB_Proc = 1
.equ MCB_LenL = 2
USB 232
.equ MCB_LenH = 4
AVR ISP .equ MCB_PrevL = 5
ISP 2313 .equ MCB_PrevH = 7
.equ MCB_Size = 8
ISP 1200
AVR SPI
.equ MCBLast = 7
I2C 300 .equ MCBFirst = 6
I2C 302 .equ MCBUsed = 5
.equ ProcMask = 0x0F
I2C TWI26
.equ NonProcMask = 0xF0
I2C/TWI 128
I2C/TWI AT8
.equ MMAP0 = 0x0000
DALLAS-1W .equ MMAP1 = 0x4000
DALLAS CRC .equ MMAP2 = 0x8000
.equ MMAP3 = 0xC000
ETHNET 8019
TEA
.equ MaxMemoryLW = 0x0000
ADC 128 .equ MaxMemoryHW = 0x0002 ;max memory
ADC 10B 0x00020000 == 128kb
ADC 400
;
ADC 401 ;
THERM 232 **************************************************************************
;* Hardware Def.
IRD 410 ;
LCD HD44 ;
***************************************************************************
LCD 2313 ;**** VARIABLES
LCD44 2313 .DSEG
KBD 240
MUX 242 LargeMCB: .byte 3 ;Egybefuggo nagy blokkok
>4kb
KBD PS2
SmallMCB: .byte 3 ;kicsi blokkok <4kb
KBD PC/128 kezdopozicioja
PS2 EMU
BOOT MG8
BOOT DR8 ;
***************************************************************************
ALM CLK .ESEG
CLOCK 8564
90 DAYS
;
DELAYS ***************************************************************************
;**** CODE SEG
CALL ID
;
DTMF 314 ***************************************************************************
PWM 6CH .CSEG

PWM 10K ExtSRAMTest:

ENCODE ldi R20,SRAMBASE ;External
SRAM Base Address
STH-11 ldi R18,8 ;8x16k page
ATMEL CORP = 128k
ldi R21,0x5A ;test byte
AVR
SRT0: sts ADR_EXHH,R20 ;
BUTTERFLY Upper memory to SRAM Banks
AVR BOOK ldi ZL,0
ldi ZH,192 ;Z point to
upper memory
ldi XL,low(16384)
ldi XH,high(16384) ;Count of
test byte

srt1: st Z+,R21
sbiw XL,1
brne srt1 ;fill bank
inc R20
dec R18
brne SRT0

ldi R20,SRAMBASE
ldi R18,8
ldi R21,0x5A ;test byte
SRT2: sts ADR_EXHH,R20
ldi ZL,0
ldi ZH,192 ;Z point to
upper memory
ldi XL,low(16384)
ldi XH,high(16384) ;Count of
test byte

srt3: ld R3,Z+
cp R21,R3
brne SRAMERR
sbiw XL,1
brne srt3 ;check bank
inc R20
dec R18
brne srt2

clc
ret

SRAMERR: sec
ret

;******************************************************
; Convert Phisycal address to Logical Address
; In: R18:R17:R16 Phisycal address
; Out R18 - page,
; R17:R16 - offset address (must add MMAP1,2,3)
;
MmTranslatePhysicalAddress:
push R17
rol R17
rol R18
rol R17
rol R18
pop R17
andi R17,0b00111111
ret

;******************************************************
; Set Page at R18:R16
; In: R18:R17:R16 Phisycal address
; Out R18 - page+1,
; R17:R16 - offset address on MMAP2
; Z - mapped address on MMAP2
;
MmSetPage:
rcall MmTranslatePhysicalAddress
MmSetPageMap:
ori R17,high(MMAP2)
sts ADR_EXHL,R18
inc R18
sts ADR_EXHH,R18 ;2 page ->
no page border fault
movw ZL,R16 ;Z - offset
at first page
RET

;******************************************************
; Initialize Memory & setup MCBs
;
Mem_Init:
ldi R16,S1D_DISPLAY_HEIGHT
ldi R17,S1D_DISPLAY_SCANLINE_BYTES
mul R16,R17
inc R1 ;skip Video
RAM + 256 byte
clr R2

sts LargeMCB+0,R0
sts LargeMCB+1,R1
sts LargeMCB+2,R2 ;First MCB
movw R16,R0
mov R18,R2
rcall MmSetPage

ldi R16,(1<= old delta

movw R12,R16
mov R14,R18 ;delta
movw R8,R0
mov R10,R2 ;best pointer
rjmp MMVanMeg

MMTeljesenJo:
movw R8,R0
mov R10,R2 ;pointer
clr R12
clr R13
clr R14 ;delta=0
rjmp MMLastInChain

MMVanMeg:
ldd R16,Z+MCB_Type
sbrc R16,MCBLast
rjmp MMLastInChain

ldd R18,Z+MCB_LenH
ldd R17,Z+MCB_LenL+1
ldd R16,Z+MCB_LenL+0
add R16,R21
adc R17,R15
adc R18,R15
add R0,R16
adc R1,R17
adc R2,R18
rjmp MmNextMCB01

MMLastInChain:
mov R0,R8
or R0,R9
or R0,R10
brne mmMoreM00
rjmp mmNoMoreMemory
mmMoreM00:
;Memory block
Allocation/sharing
;Alloc = delta < 40
byte (32+8)
;share = delta =>
40 byte
ldi R16,40
clr R17
cp R12,R16
cpc R13,R17
cpc R14,R17
brsh MMShare

mmAllocAll:
movw R0,R8
mov R2,R10
movw R16,R8
mov R18,R10
rcall MmSetPage

ldd R16,Z+MCB_Type ;set

MCBUsed & Process
ori R16,(1< Proc

mmMakeFree:
ldd R16,Z+MCB_Type
cbr R16,(1<

Programming the AVR Microcontrollers in Machine Language

AVR
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected

from Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing,
intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still
be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
http://avr-asm.tripod.com/vfxmem.html (1 of 2)1/20/2009 8:51:14 PM
16 BIT MATH (AVR 202)

USART) (As used with RS-232,RS-485, and more) Serial

Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language

http://avr-asm.tripod.com/vfxmem.html (2 of 2)1/20/2009 8:51:14 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

BUBBLE SORT (AVR 220)

HOME
RETRO_DAN
;**** A P P L I C A T I O N N O T E A V R 2 2 0
ASM FORUM ************************
ASM MATH ;*
;* Title: Bubble Sort Algorithm
TUTORIAL #1
;* Version: 1.0
TUTORIAL #2 ;* Last updated: 97.07.04
TUTORIAL #3 ;* Target: AT90Sxx1x (Devices with SRAM)
;*
MATH 200 ;* Support E-mail: avr@atmel.com
MATH 200b ;*
;* DESCRIPTION
MATH 201 ;* This Application note shows how to sort a block of
MATH 202 data in SRAM using
;* the code efficient Bubble Sort Algorithm. The App.
MATH 32X
note contains a test
MATH YX ;* program which copies a 60-byte block of data from
program memory to
DIV16 XX
;* SRAM and sorts the data.
DIV 24 24 ;*
DIV 3216 ;
***************************************************************************
FLOAT 128
SQRT16 .include "8515def.inc"

MATH 202 .equ SIZE =60 ;data block size

MATH 202 .equ TABLE_L =$60 ;Low SRAM address
of first data element
DEC ASCII
.equ TABLE_H =$00 ;High SRAM address
INT ASCII of first data element
HX2ASC
rjmp RESET ;Reset Handle
AVG8 222
FFT7 ;
***************************************************************************
COPY 102 ;*
LPM 108 ;* "bubble"
;*
EPROM 100 ;* This subroutine bubble sorts the number of bytes
SER EPROM found in "cnt1" + 1
;* with the last element in SRAM at location "last".
DFLASH AT45
;* This implementation sorts the data with the highest
FLASH CARD element at the
;* lowest SRAM address. The sort order can be reversed
VFX SMIL
by changing the
VFX MEM ;* "brlo" statement to "brsh". Signed sort can be
SORT 220 obtained by using "brlt"
;* or "brge"
CRC 236 ;*
XMODEM REC ;* Number of words :13 + return
;* Number of cycles :6*(SIZE-1)+10*(SIZE(SIZE-1))
UART 304 +return (Min)
UART 305 ;* 6*(SIZE-1)+13*(SIZE(SIZE-1))
+return (Max)
UART 128
;* Low registers used :3 (A,B,cnt2)
UART BUFF ;* High registers used :3 (cnt1,endL,endH)
;* Pointers used :Z
USB 232
;*
AVR ISP ;
ISP 2313 ***************************************************************************

ISP 1200 ;***** Subroutine Register Variables

AVR SPI
.def A =r13 ;first value to be
I2C 300 compared
I2C 302 .def B =r14 ;second value to be
compared
I2C TWI26
.def cnt2 =r15 ;inner loop counter
I2C/TWI 128 .def cnt1 =r16 ;outer loop counter
I2C/TWI AT8 .def endL =r17 ;end of data array
low address
DALLAS-1W .def endH =r18 ;end of data array
DALLAS CRC high address

ETHNET 8019 ;***** Code

TEA
bubble:
ADC 128 mov ZL,endL
ADC 10B mov ZH,endH ;init Z pointer
mov cnt2,cnt1 ;counter2 <- counter1
ADC 400
i_loop: ld A,Z ;get first byte, A
ADC 401 (n)
THERM 232 ld B,-Z ;decrement Z and get second
byte, B (n-1)
IRD 410 cp A,B ;compare A with B
LCD HD44 brlo L1 ;if A not lower
st Z,A ; store swapped
LCD 2313 std Z+1,B
LCD44 2313 L1: dec cnt2
brne i_loop ;end inner loop
KBD 240 dec cnt1
MUX 242 brne bubble ;end outer loop
ret
KBD PS2
KBD PC/128
PS2 EMU ;
***************************************************************************
BOOT MG8 ;*
BOOT DR8 ;* Test Program
;*
ALM CLK ;* This program copies 60 bytes of data from Program
CLOCK 8564 memory to SRAM. It
;* then calls "bubble" to get the data sorted.
90 DAYS
;*
DELAYS ;
***************************************************************************
CALL ID
DTMF 314 RESET:
PWM 6CH
;***** Main program Register variables
PWM 10K
ENCODE .def temp =r16
STH-11 ;***** Code
ATMEL CORP
ldi temp,low(RAMEND)
AVR
out SPL,temp
BUTTERFLY ldi temp,high(RAMEND)
AVR BOOK out SPH,temp ;init Stack Pointer

;***** Memory fill

clr ZH
ldi ZL,tableend*2+1 ;Z-pointer <- ROM table end
+ 1
ldi YL,low(256*TABLE_H+TABLE_L+SIZE)
ldi YH,high(256*TABLE_H+TABLE_L+SIZE)
;Y pointer <- SRAM table
end + 1
loop: lpm ;get ROM constant
st -Y,r0 ;store in SRAM and
decrement Y-pointer
sbiw ZL,1 ;decrement Z-pointer
cpi YL,TABLE_L ;if not done
brne loop ; loop more
cpi YH,TABLE_H
brne loop

;***** Sort data

sort: ldi endL,low(TABLE_H*256+TABLE_L+SIZE-1)

ldi endH,high(TABLE_H*256+TABLE_L+SIZE-1)
;Z <- end of array address
ldi cnt1,SIZE-1 ;cnt1 <- size of array - 1
rcall bubble

forever:rjmp forever

;***** 60 ROM Constants

table:
.db 120,196
.db 78,216
.db 78,100
.db 43,39
.db 241,43
.db 62,172
.db 109,69
.db 48,184
.db 215,231
.db 63,133
.db 216,8
.db 121,126
.db 188,98
.db 168,205
.db 157,172
.db 108,233
.db 80,255
.db 252,102
.db 198,0
.db 171,239
.db 107,114
.db 172,170
.db 17,45
.db 42,55
.db 34,174
.db 229,250
.db 12,179
.db 187,243
.db 44,231
tableend:
.db 76,48

Programming the AVR Microcontrollers in Machine Language

AVR
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected

from Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing,
intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still
be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language
http://avr-asm.tripod.com/avr220.html (1 of 2)1/20/2009 8:51:49 PM
16 BIT MATH (AVR 202)

http://avr-asm.tripod.com/avr220.html (2 of 2)1/20/2009 8:51:49 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

CIRCULAR REDUNDANCY CHECK (AVR 236)

HOME
RETRO_DAN
;**** A P P L I C A T I O N N O T E A V R 236
ASM FORUM ************************
ASM MATH ;*
;* Title: CRC check of program memory
TUTORIAL #1
;* Version: 1.3
TUTORIAL #2 ;* Last updated: 11.11.2004
TUTORIAL #3 ;* Target: AT90Sxxx, ATtinyxxx, ATmegaxxx
;* (All AVR Devices with LPM
MATH 200 instr, not AT90S1200)
MATH 200b ;*
;* Support E-mail: avr@atmel.com
MATH 201 ;*
MATH 202 ;* NOTE: Always check out Atmels web site, www.atmel.
com for the latest and updated
MATH 32X
;* version of the software.
MATH YX ;*
;* DESCRIPTION
DIV16 XX
;* This application note describes how to perform CRC
DIV 24 24 computation
DIV 3216 ;* of code memory contents using a simple algoritm.
;* To generate CRC checksum load the register "status"
FLOAT 128 with 00 and call the routine
SQRT16 ;* "crc_gen". The resulting checksum is placed in the
registers
MATH 202 ;* byte_2(low byte) and byte_3(high byte).
MATH 202 ;*
;* To check the CRC checksum load the register "status"
DEC ASCII
with FF and call the routine
INT ASCII ;* "crc_gen". The resulting checksum is placed in the
registers
HX2ASC
;* byte_2(low byte) and byte_3(high byte). If the
AVG8 222 checksum is 00 the program code is
FFT7 ;* correct, if the checksum is non-zero an error has
been introduced in the program code
COPY 102 ;
LPM 108 **************************************************************************
EPROM 100
SER EPROM .include "8515def.inc"
DFLASH AT45
;***** Constants
FLASH CARD
.equ LAST_PROG_ADDR = 0x1FFF ;
VFX SMIL
Last program memory address(byte address)
VFX MEM .equ CR = 0x8005 ; CRC
SORT 220 divisor value

CRC 236 ;
XMODEM REC **************************************************************************
;*
UART 304 ;* PROGRAM START - EXECUTION STARTS HERE
UART 305 ;*
;
UART 128
**************************************************************************
UART BUFF
; .cseg
USB 232
AVR ISP .org $0000
ISP 2313 rjmp RESET ;Reset handle

ISP 1200
AVR SPI ;
***************************************************************************
I2C 300 ;*
I2C 302 ;* "crc_gen" - Generation and checking of CRC checksum
;*
I2C TWI26
;* This subroutine generates the checksum for the
I2C/TWI 128 program code.
I2C/TWI AT8 ;* 32 bits are loaded into 4 register, the upper 16
bits are XORed
DALLAS-1W ;* with the divisor value each time a 1 is shifted into
DALLAS CRC the carry flag
;* from the MSB.
ETHNET 8019 ;*
TEA ;* If the status byte is 0x00,the routine will generate
new checksum:
ADC 128 ;* After the computing the code 16 zeros are
ADC 10B ;* appended to the code and the checksum is calculated.
;*
ADC 400
;* If the status byte is different from 0X00, the
ADC 401 routine will check if the current checksum is valid.
THERM 232 ;* After the computing the code the original checksum
are
IRD 410 ;* appended to the code and calculated. The result is
LCD HD44 zero if no errors occurs
;* The result is placed in registers byte_2 and byte_3
LCD 2313 ;*
LCD44 2313 ;* Number of words :44 + return
;* Number of cycles :program memory size(word) * 175
KBD 240 (depending on memory contens)
MUX 242 ;* Low registers used :6 (byte_0,byte_1,byte_2,
byte_3)
KBD PS2
;* High registers used :7 (sizel,sizeh,crdivl,crdivh,
KBD PC/128 count,status,zl,zh)
PS2 EMU ;*
;
BOOT MG8 ***************************************************************************
BOOT DR8
;***** Subroutine Register Variables
ALM CLK
CLOCK 8564 .def byte_0 = r0 ; Lower byte of
lower word
90 DAYS
.def byte_1 = r1 ; Upper byte of
DELAYS lower word
.def byte_2 = r2 ; Lower byte of
CALL ID
upper word
DTMF 314 .def byte_3 = r3 ; Upper byte of
PWM 6CH upper word
.def crc = r4 ; CRC
PWM 10K checksum low byte
ENCODE .def crch = r5 ; CRC
checksum high byte
STH-11 .def sizel = r17 ; Program code size register
ATMEL CORP .def sizeh = r18
.def crdivl = r19 ; CRC divisor register
AVR
.def crdivh = r20
BUTTERFLY .def count = r21 ; Bit counter
AVR BOOK .def status = r22 ; Status byte: generate(0)
or check(1)

crc_gen:
ldi sizel,low(LAST_PROG_ADDR) ;Load last
program memory address
ldi sizeh,high(LAST_PROG_ADDR)
clr zl ;Clear Z pointer
clr zh
ldi crdivh,high(CR);Load divisor value
ldi crdivl,low(CR)
lpm ;Load first memory
location
mov byte_3,byte_0 ;Move to highest byte
adiw zl,0x01 ;Increment Z pointer
lpm ;Load second memory
location
mov byte_2,byte_0

next_byte:
cp zl,sizel ;Loop starts here
cpc zh,sizeh ;Check for end of
code
brge end ;Jump if end of code
adiw zl,0x01
lpm ;Load high byte
mov byte_1,byte_0 ;Move to upper byte
adiw zl,0x01 ;Increment Z pointer
lpm ;Load program
memory location
rcall rot_word ;Call the rotate routine
rjmp next_byte

end:
;ret ;uncomment this line if checksum is stored
in last flash memory address.
ldi count,0x11
cpi status,0x00
brne check
clr byte_0 ;Append 16 bits(0x0000) to
clr byte_1 ;the end of the code for
CRC generation
rjmp gen
check:
mov byte_0,crc ;Append the
original checksum to
mov byte_1,crch ;the end of the code for
CRC checking
gen:
rcall rot_word ;Call the rotate routine
mov crc,byte_2
mov crch,byte_3
ret ;Return to main prog

rot_word:
ldi count,0x11
rot_loop:
dec count ;Decrement bit counter
breq stop ;Break if bit
counter = 0
lsl byte_0 ;Shift zero into lowest bit
rol byte_1 ;Shift in carry from
previous byte
rol byte_2 ;Preceede shift
rol byte_3
brcc rot_loop ;Loop if MSB =
0
eor byte_2,crdivl
eor byte_3,crdivh ;XOR high word if MSB = 1
rjmp rot_loop
stop:
ret

;
***************************************************************************
;*
;* EERead_seq
;*
;* This routine reads the
;* EEPROM into the global register variable "temp".
;*
;* Number of words :4+ return
;* Number of cycles :8 + return
;* High Registers used :4 (temp,eeadr,eeadrh,
eedata)
;*
;
***************************************************************************

.def temp = r16

.def eeadr = r23
.def eeadrh = r24
.def eedata = r25

;***** Code

eeread:
out EEARH,eeadrh ;output address high byte
out EEARL,eeadr ;output address low byte
sbi EECR,EERE ;set EEPROM Read
strobe
in eedata,EEDR ;get data
ret

;
***************************************************************************
;*
;* EEWrite
;*
;* This subroutine waits until the EEPROM is ready to
be programmed, then
;* programs the EEPROM with register variable "EEdwr"
at address "EEawr"
;*
;* Number of words :7 + return
;* Number of cycles :13 + return (if EEPROM is ready)
;* Low Registers used :None
;* High Registers used: ;4 (temp,eeadr,eeadr,eedata)
;*
;
***************************************************************************

.def temp = r16

.def eeadr = r23
.def eeadrh = r24
.def eedata = r25

eewrite:
sbic EECR,EEWE ;If EEWE not clear
rjmp EEWrite ; Wait more
out EEARH,eeadrh ;Output address high byte
out EEARL,eeadr ;Output address low byte
out EEDR,eedata ;Output data
sbi EECR,EEMWE
sbi EECR,EEWE ;Set EEPROM Write
strobe
ret

;
************************************************************************
;*
;* Start Of Main Program
;*
.cseg
.def crc = r4 ;Low byte
of checksum to be returned
.def crch = r5 ;High byte
of checksum to be returned
.def temp = r16
.def status = r22 ;Status byte: generate(0)
or check(1)
.def eeadr = r23
.def eeadrh = r24
.def eedata = r25

RESET:
ldi r16,high(RAMEND) ;Initialize stack
pointer
out SPH,r16 ;High byte only
required if
ldi r16,low(RAMEND) ;RAM is bigger than 256
Bytes
out SPL,r16

ldi temp,0xff
out DDRB,temp ;Set PORTB as output
out PORTB,temp ;Write 0xFF to PORTB
clr status ;Clear status register,
prepare for CRC generation
rcall crc_gen

ldi eeadr,0x01 ;Set address low byte for

EEPROM write
ldi eeadrh,0x00 ;Set address high byte for
EEPROM write
mov eedata,crc ;Set CRC low byte in EEPROM
data
rcall eewrite ;Write EEPROM

ldi eeadr,0x02 ;Set address low byte for

EEPROM write
ldi eeadrh,0x00 ;Set address high byte for
EEPROM write
mov eedata,crch ;Set CRC high byte in
EEPROM data
rcall eewrite ;Write EEPROM

out PORTB,crc ;Output CRC low value to

PORTB

mainloop:
sbic EECR,EEWE ;If EEWE not clear
rjmp mainloop ; Wait more

;********** Insert program code here *************

ldi eeadr,0x01 ;Set address low byte for

EEPROM read
ldi eeadrh,0x00 ;Set address high byte for
EEPROM read
rcall eeread ;Read EEPROM
mov crc,eedata ;Read CRC low byte from
EEPROM

ldi eeadr,0x02 ;Set address low byte for

EEPROM read
ldi eeadrh,0x00 ;Set address high byte for
EEPROM read
rcall eeread ;Read EEPROM
mov crch,eedata ;Read CRC low byte from
EEPROM

ser status ;Set status register,

prepare for CRC checking
rcall crc_gen

loop:
out PORTB,crc ;Output CRC low value to
PORTB
rjmp loop

.exit

Programming the AVR Microcontrollers in Machine Language

AVR
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© WebRing Inc. Search

Atmel AVR From Wikipedia, the free encyclopedia (Redirected

from Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing,
intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still
be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
http://avr-asm.tripod.com/arv236.html (1 of 2)1/20/2009 8:52:28 PM
16 BIT MATH (AVR 202)

same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language

http://avr-asm.tripod.com/arv236.html (2 of 2)1/20/2009 8:52:28 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

XMODEM RECEIVE ROUTINE

HOME
RETRO_DAN
;
ASM FORUM ***************************************************************************
ASM MATH ;
; File Name :'xmodem.asm"
TUTORIAL #1
; Title :XMODEM only receive
TUTORIAL #2 ; Date :2002.07.03.
TUTORIAL #3 ; Version :1.0.0
; Support telephone :+36-70-333-4034, Old: +36-30-9541-
MATH 200 658
MATH 200b ; Support fax :
; Support Email :info@vfx.hu
MATH 201 ; Target MCU :AT90S8515
MATH 202 ;
;
MATH 32X
***************************************************************************
MATH YX ; D E S C R I P T I O N
;
DIV16 XX
;
DIV 24 24 ;
DIV 3216 ;
***************************************************************************
FLOAT 128 ; M O D I F I C A T I O N H I S T O R Y
SQRT16 ;
;
MATH 202 ; rev. date who why
MATH 202 ; ---- ---------- ---
--------------------------------------------
DEC ASCII
; 0.01 2002.07.03 VFX Creation
INT ASCII ;
;
HX2ASC
;
AVG8 222 ***************************************************************************
FFT7 ;Hardware
;
COPY 102 ***************************************************************************
LPM 108 ;*
;* Kvarc: f=7.3728 MHz (T=135.63368 ns)
EPROM 100 ;*
SER EPROM ;
***************************************************************************
DFLASH AT45
;
FLASH CARD ;
;
VFX SMIL
VFX MEM ;
SORT 220 ***************************************************************************
;* Const Def
CRC 236
XMODEM REC .EQU Xmodem_Sync = 0 ;
szinkronizalasi fazis
UART 304 .EQU Xmodem_SOH = 1 ;SOH byte-
UART 305 ra var
.EQU Xmodem_Fill = 2 ;SOH byte
UART 128
megjott, block init megvolt
UART BUFF .EQU Xmodem_Err = 3 ;megszakadt
az atvitel, NAK kuldese 3 masodpercenkent
USB 232
AVR ISP
ISP 2313 .EQU SyncTiming = 300 ;ket
karakter elkuldese kozott
ISP 1200 ;eltelt ido szinc.
AVR SPI uzemmodban 3sec @100Hz
I2C 300
I2C 302 ;
**************************************************************************
I2C TWI26
;* Hardware Def.
I2C/TWI 128 ;
I2C/TWI AT8
DALLAS-1W ;
DALLAS CRC ***************************************************************************
;**** VARIABLES
ETHNET 8019 .DSEG
TEA
ADC 128 CRC: .BYTE 2 ; CRC for
ADC 10B XMODEM
XmodemFlag: .BYTE 1 ;Xmodem Flag
ADC 400
;[2:0] = 000
ADC 401 sending 'c' Phase 1: syncronize
THERM 232
Xm_BlkCounter: .BYTE 1 ;Xmodem
IRD 410 Block Counter [00-FF]
LCD HD44 XmodemPTR: .BYTE 1 ;Xmodem Buffer
pointer
LCD 2313 XmodemBuf: .BYTE 133 ;XMODEM RxBuffer
LCD44 2313 FileLength: .byte 4 ;File hossz 32 bites
LastPocketSize: .byte 1 ;utolso
KBD 240 pocket merete byte-ban [0...128]
MUX 242 XmodemMode: .byte 1 ;Mode0 - Nul modem
letolti de nem csinal semmit
KBD PS2
;Mode1 - DSP Boot
KBD PC/128 Xm_ErrorCNT: .byte 1 ;Xmodem
PS2 EMU Time to Abort counter

BOOT MG8 ;
BOOT DR8 ***************************************************************************
.ESEG
ALM CLK
CLOCK 8564
;
90 DAYS
***************************************************************************
DELAYS .CSEG
CALL ID
DTMF 314 ;
PWM 6CH ***************************************************************************
;** Init Xmodem File Receive
PWM 10K ;**
ENCODE
Init_Xmodem: ldi R16,128
STH-11 sts LastPocketSize,R16
ATMEL CORP clr R0
sts FileLength+0,R0
AVR
sts FileLength+1,R0
BUTTERFLY sts FileLength+2,R0
AVR BOOK sts FileLength+3,R0
sts Xm_ErrorCNT,R0
sts XmodemFlag,R0
sts Xm_BlkCounter,R0
Init_XmNextBl: clr R0
sts CRC+0,R0
sts CRC+1,R0
sts XmodemPTR,R0
STS SCNT2+0,R0
STS SCNT2+1,R0
ret

;
***************************************************************************
;** Calc & Update XMODEM CRC
;*
;* In: R0 - data byte

UpdateCRC: lds R17,CRC+1

mov R15,R17
swap R17
mov R16,R17

eor R17,R15
andi R17,0xF0
andi R16,0x0F
eor R15,R16

mov R14,R17
lsl R14
rol R16

eor R15, R14

eor R17,R16

lds R14,CRC+0
eor R15,R0
eor R17,R14

sts CRC+0,R15
sts CRC+1,R17
ret

;
***************************************************************************
;** XMODEM Receive File & Block
;*
;*
Xmodem_Rec: lds R16,XmodemFlag
cpi R16,Xmodem_Sync
breq Xm_Sync

cpi R16,Xmodem_Fill
brne Xmodem_Rec1
rjmp Xm_Fill

Xmodem_Rec1: cpi R16,Xmodem_SOH

breq Xm_SOH

cpi R16,Xmodem_Err
breq Xm_Sync

rjmp Xmodem_Cancel

Xm_Sync: call Rs232GetByte

brcs Xm_valamijott
;itt meg
mindig nem jott semmi
lds R16,SCNT2+0
lds R17,SCNT2+1
or R16,R17 ;Timer
lejart?
breq Xm_Sync1
ret

Xm_Sync1: ldi R16,NAK ;akkor, ha

hiba van NAK megy 3 masodpercenkent
lds R17,XmodemFlag
cpi R17,Xmodem_Err
breq Xm_Sync2

;mivel meg
mindig nem jott semmi kuldunk egy
;CRC -
karaktert 3 masodpercenkent

lds R16,Xm_ErrorCNT ;ha 20 'C'

ideig nem jon semmi akkor abort!!!
inc R16
sts Xm_ErrorCNT,R16
cpi R16,20
brne Xm_Sync25
rjmp Xm_Abort

Xm_Sync25: ldi R16,'C'

Xm_Sync2: call SendChrW

ldi R16,Low(SyncTiming) ;Timer=3sec
@100Hz
sts SCNT2+0,R16
ldi R17,High(SyncTiming)
sts SCNT2+1,R17
ret

Xm_SOH: call Rs232GetByte

brcs Xm_valamijott
ret

Xm_valamijott: mov R16,R0

cpi R16,CAN
breq Xmodem_Cancel
cpi R16,SOH
breq Xmodem_StartOfH
cpi R16,EOT
breq Xmodem_EndOfT
rjmp Xmodem_Rec

Xm_ByteStr: .db " Bytes received ",CR,0

;End of
Trans == Canacel
Xmodem_EndOfT:
ldi R16,ACK
call SendChrW ;Pozitiv
nyugta

Xm_Abort: ldi R16,CR

call SendChrW ;soremeles

lds R16,FileLength+0 ;ACC1 LSByte

lds R17,FileLength+1
lds R18,FileLength+2
lds R19,FileLength+3
call ULTOA ;Print
FileLength

ldi XL,low(ASCIIBuf) ;Ascii

Buffer Ptr
ldi XH,high(ASCIIBuf)
;ldi
R22,12
call PrintASCII ;rcall
DumpASCII

ldi R16,Low(Xm_ByteStr)
ldi R17,High(Xm_ByteStr)
call SendStrW

Xmodem_Cancel: lds R16,Term_Stat ;

End of Xmodem receiving
cbr R16,Term_Rec_Xmodem ;Normal
Terminal Mode
sts Term_Stat,R16

lds R17,XmodemMode
cpi R17,1
brne Xm_CancelEnd
;itt lesz
vege a FALSH update-nak

Xm_CancelEnd: clr R17

sts Updating,R17 ;Ezel
jelzzuk keszen vagyunk
sts XmodemMode,R17 ;barmi volt
is, most null modem
jmp CMDOk

Xmodem_StartOfH:
ldi R16,Xmodem_Fill
sts XmodemFlag,R16
rcall Init_XmNextBl
ldi ZL,Low(SyncTiming) ;Timer=3sec
@100Hz
sts SCNT2+0,ZL ;he nem jon
ujjab byte, akkor baj van!!
ldi ZL,High(SyncTiming)
sts SCNT2+1,ZL
rjmp Xmodem_Rec

Xm_Fill: call Rs232GetByte ;itt

beolvasunk 132 byte-ot
brcs Xm_data ; blk
counter,255-blk counter [2 byte]
; adatblok
[128 byte]
; CRC [2
byte]
;total 132
byte

lds R16,SCNT2+0 ;he nem jon

ujjab byte, akkor baj van!!
lds R17,SCNT2+1
or R16,R17
brne Xm_vanido

ldi R16,Xmodem_Err
sts XmodemFlag,R16 ;Time Out,
Ismetles kell

Xm_vanido: ret

Xm_data:
ldi ZL,Low(SyncTiming) ;Timer=3sec
@100Hz
sts SCNT2+0,ZL ;he nem jon
ujjab byte, akkor baj van!!
ldi ZL,High(SyncTiming)
sts SCNT2+1,ZL

ldi ZL,Low(XmodemBuf)
ldi ZH,High(XmodemBuf)
clr R1
lds R16,XmodemPTR
add ZL,R16
adc ZH,R1 ;ZL:ZH ->
Xmodem Actualis Pos.
st Z,R0 ;Char
eltarolasa
inc R16
sts XmodemPTR,R16
cpi R16,3 ;3

Programming the AVR Microcontrollers in Machine Language

AVR
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© WebRing Inc. Search

Atmel AVR From Wikipedia, the free encyclopedia (Redirected

from Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing,
intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still
be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations

http://avr-asm.tripod.com/xmodemrec.html (1 of 2)1/20/2009 8:53:11 PM

16 BIT MATH (AVR 202)

R16 to R31. I/O ports 0 to 31 have different addressing

capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language

http://avr-asm.tripod.com/xmodemrec.html (2 of 2)1/20/2009 8:53:11 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

HALF DUPLEX SOFTWARE UART (AVR 304)

HOME
RETRO_DAN
;**** A P P L I C A T I O N N O T E A V R 3 0 4
ASM FORUM ************************
ASM MATH ;*
;* Title: Half Duplex Interrupt Driven
TUTORIAL #1
Software UART
TUTORIAL #2 ;* Version: 1.0
TUTORIAL #3 ;* Last updated: 97.07.18
;* Target: AT90Sxxxx (All AVR Devices)
MATH 200 ;*
MATH 200b ;* Support E-mail: avr@atmel.com
;*
MATH 201 ;* Code Size :72 words
MATH 202 ;* Low Register Usage :2
;* High Register Usage :5
MATH 32X
;* Interrupt Usage :External Interrupt,
MATH YX ;* Timer/Counter0 overflow interrupt
;*
DIV16 XX
;* DESCRIPTION
DIV 24 24 ;*
DIV 3216 ;* This application note describes how to make a half
duplex software UART
FLOAT 128 ;* on any AVR device with the 8-bit Timer/Counter0 and
SQRT16 External Interrupt.
;* As a lot of control applications communicate in one
MATH 202 direction at a time
MATH 202 ;* only, a half duplex UART will limit the usage of MCU
resources.
DEC ASCII
;*
INT ASCII ;* The constants N and R determine the data rate. R
selects clock frequency
HX2ASC
;* as described in the T/C Prescaler in the AVR
AVG8 222 databook. If the T/C pre-
FFT7 ;* scaling factor is denoted C, the following
expression yields the data rate:
COPY 102 ;*
LPM 108 ;* XTAL
;* BAUD = ------ min. N*C = 17
EPROM 100 ;* N*C max. N = 170
SER EPROM ;*
;* Absolute minimum value for N*C is 17 (which causes
DFLASH AT45
the interrupt flag to be
FLASH CARD ;* set again before the interrupt is finished).
Absolute maximum is 170.
VFX SMIL
;* (Caused by the 1.5bit-lenght that is necessary to
VFX MEM receive bits correctly.)
SORT 220 ;*
;* The UART uses PD2 as receive pin because it utilizes
CRC 236 the external interrupt.
XMODEM REC ;* The transmit-pin is PD4 in this example, but it can
be any other pins.
UART 304 ;*
UART 305 ;* Since the UART is half duplex, it can either send or
recieve data. It can't
UART 128
;* do both simoutaneausly. When idle it will
UART BUFF automatically recieve incoming
;* data, but if it is transmitting data while incoming
USB 232
data arrives, it will
AVR ISP ;* ignore it. Also, if u_transmit is called without
ISP 2313 waiting for the 'READY' bit
;* in the 'u_status' register to become cleared, it
ISP 1200 will abort any pending
AVR SPI ;* reception or transmittal.
;*
I2C 300 ;*
I2C 302 ;* *** Initialization
;*
I2C TWI26
;* 1. Call uart_init
I2C/TWI 128 ;* 2. Enable global interrupts (with 'sei')
I2C/TWI AT8 ;*
;* *** Receive
DALLAS-1W ;*
DALLAS CRC ;* 1. Wait until RDR in 'u_status' becomes set
;* 2. Read 'u_buffer'
ETHNET 8019 ;*
TEA ;* *** Transmit
;*
ADC 128 ;* (0. Initialize the UART by executing uart_init and
ADC 10B sei)
;* 1. Wait until READY in 'u_status' becomes clear
ADC 400
;* 2. Set 'u_buffer'
ADC 401 ;* 3. Call 'u_transmit'
THERM 232 ;*
;
IRD 410 **************************************************************************
LCD HD44
.include "1200def.inc"
LCD 2313
LCD44 2313 ;***** BAUD-rate settings
KBD 240 ;BAUD-RATES @1MHz XTAL AND
MUX 242 R=1
;.equ N=104 ; 9600
KBD PS2
;.equ N=52 ;19200
KBD PC/128 .equ N=26 ;38400
PS2 EMU .equ C=1 ;Divisor
.equ R=1 ;R=1 when C=1
BOOT MG8
BOOT DR8
;***** UART Global Registers
ALM CLK
CLOCK 8564 .def u_buffer =r14 ;Serial buffer
.def u_sr =r15 ;Status-register
90 DAYS
storage
DELAYS .def u_tmp =r16 ;Scratchregister
.def u_bit_cnt =r17 ;Bit counter
CALL ID
.def u_status =r18 ;Status buffer
DTMF 314 .def u_reload =r19 ;Reload-register
PWM 6CH (internal - do not use)
.def u_transmit =r20 ;Data to transmit
PWM 10K
ENCODE
;***** Bit positions in the Status-register
STH-11
ATMEL CORP .equ RDR=0 ;Receive data ready
bit
AVR
.equ TD=6 ;Transmitting data
BUTTERFLY (internal - read-only)
AVR BOOK .equ BUSY=7 ;Busy-flag
(internal - read-only)

;
**************************************************************************
;*
;* PROGRAM START - EXECUTION STARTS HERE
;*
;
**************************************************************************
.cseg

.org $0000
rjmp start ;Reset handler

.org INT0addr
rjmp ext_int0 ;External interrupt
handler

.org OVF0addr
rjmp tim0_ovf ;Timer0 overflow
handler

.org ACIaddr
reti ;Analog comparator
handler (Not Used)

;
**************************************************************************
;*
;* EXT_INT0 - External Interrupt Routine 0
;*
;*
;* DESCRIPTION
;* This routine is executed when a negative edge on the
incoming serial
;* signal is detected. It disables further external
interrupts and enables
;* timer interrupts (bit-timer) because the UART must
now receive the
;* incoming data.
;*
;* This routine sets bits in the GIMSK, TIFR and TIMSK
registers. In this
;* code when the bits are set, it overwrites all other
bits. This is done
;* because of the lack of available cycles when it
operates at low clock
;* rate and high baudrates.
;*
;*
;* Total number of words : 12
;* Total number of cycles : 15 (incl. reti)
;* Low register usage : 1 (u_sr)
;* High register usage : 4 (u_bit_cnt,
u_tmp,u_status,u_reload)
;*
;
**************************************************************************
ext_int0:
in u_sr,SREG ;Store Status
Register

ldi u_status,1<7) is set

rjmp tim0_stopb ; jump to stop-
bit-part

sbrc u_buffer,0 ;if LSB in buffer

is 1
sbi PORTD,PD4 ; Set transmit
to 1
sbrs u_buffer,0 ;if LSB in buffer
is 0
cbi PORTD,PD4 ; Set transmit
to 0
lsr u_buffer ;Shift buffer right

out SREG,u_sr ;Restore SREG

reti

tim0_stopb:
sbi PORTD,PD4 ;Generate stop-bit

sbrs u_bit_cnt,0 ;if u_bit_cnt==8

(stop-bit)
rjmp tim0_ret ; jump to exit

tim0_complete:
ldi u_tmp,1<' is sent back. The character is
also
;* presented on port B.
;*
;
**************************************************************************

.def tmp=r21 ;Temp.

register
.def buffer=r22 ;Recieved
byte
.def adr=r23 ;EEPROM
Address

start: ser tmp ;Initialize

out PORTD,tmp ;Set port D as
input with pullups
sbi DDRD,DDD4 ; except PD4 ->
output with 1's
out DDRB,tmp ;Set port B as
output with 1's (LED-off)
out PORTB,tmp

rcall uart_init ;Init UART

sei ;Enable interrupts

idle: sbrs u_status,RDR ;Wait for

Character
rjmp idle
mov buffer,u_buffer ;Get recieved
character
out PORTB,u_buffer ;Output the byte on
port B
ldi adr,example_data ;Set/Restore
pointer to EEPROM data

loop: out EEAR,adr ;Set the

EEPROM's address
sbi EECR,EERE ;Send the Read
strobe
in u_transmit,EEDR ;Put the data in
the transmit register
rcall uart_transmit ;And transmit the
data

wait: sbrc u_status,TD ;Wait until

data is sent
rjmp wait

inc adr ;Increase pointer

cpi adr,example_data+12 ;Reached byte 12?
(End?)
breq idle ; Yes, wait for
new char.

cpi adr,example_data+10 ;Reached byte 10?

brne loop ; No, jump back

mov u_transmit,buffer ;Put data in

transmit register
rcall uart_transmit ;And transmit it

wait2: sbrc u_status,TD ;Wait until

data is sent
rjmp wait2

rjmp loop ;Continue sendig

chars

;
**************************************************************************
;*
;* Test/Example program data.
;*
;* This is the data that will be sent back when a
character is recieved.
;*
;
**************************************************************************
.eseg
example_data:
.db 89 ;'Y'
.db 111 ;'o'
.db 117 ;'u'
.db 32 ;' '
.db 116 ;'t'
.db 121 ;'y'
.db 112 ;'p'
.db 101 ;'e'
.db 100 ;'d'
.db 32 ;' '
.db 13 ;
.db 10 ;

Programming the AVR Microcontrollers in Machine Language

AVR
<< Prev | Ring Hub | Join | Rate| Next
>>
© WebRing Inc. Search

Atmel AVR From Wikipedia, the free encyclopedia (Redirected

from Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing,
intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still
be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
http://avr-asm.tripod.com/avr304.html (1 of 2)1/20/2009 8:53:46 PM
16 BIT MATH (AVR 202)

Core Running Many Single Cycle Instructions Multifunction,

Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language

http://avr-asm.tripod.com/avr304.html (2 of 2)1/20/2009 8:53:46 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

HALF DUPLEX SOFTWARE UART (AVR 305)

HOME
RETRO_DAN
;**** A P P L I C A T I O N N O T E A V R 3 0 5
ASM FORUM ************************
ASM MATH ;*
;* Title : Half Duplex Interrupt Driven
TUTORIAL #1
Software UART
TUTORIAL #2 ;* Version : 1.1
TUTORIAL #3 ;* Last updated : 97.08.27
;* Target : AT90Sxxxx (All AVR Device)
MATH 200 ;*
MATH 200b ;* Support email : avr@atmel.com
;*
MATH 201 ;* Code Size : 32 Words
MATH 202 ;* Low Register Usage : 0
;* High Register Usage : 4
MATH 32X
;* Interrupt Usage : None
MATH YX ;*
;* DESCRIPTION
DIV16 XX
;* This Application note contains a very code efficient
DIV 24 24 software UART.
DIV 3216 ;* The example program receives one character and
echoes it back.
FLOAT 128 ;
SQRT16 ***************************************************************************

MATH 202 .include "1200def.inc"

MATH 202
;***** Pin definitions
DEC ASCII
INT ASCII .equ RxD =0 ;Receive
pin is PD0
HX2ASC
.equ TxD =1 ;Transmit
AVG8 222 pin is PD1
FFT7
;***** Global register variables
COPY 102
LPM 108 .def bitcnt =R16 ;bit counter
.def temp =R17 ;temporary
EPROM 100 storage register
SER EPROM
.def Txbyte =R18 ;Data to be
DFLASH AT45
transmitted
FLASH CARD .def RXbyte =R19 ;Received
data
VFX SMIL
VFX MEM .cseg
SORT 220 .org 0

CRC 236 ;
XMODEM REC ***************************************************************************
;*
UART 304 ;* "putchar"
UART 305 ;*
;* This subroutine transmits the byte stored in the
UART 128
"Txbyte" register
UART BUFF ;* The number of stop bits used is set with the sb
constant
USB 232
;*
AVR ISP ;* Number of words :14 including return
ISP 2313 ;* Number of cycles :Depens on bit rate
;* Low registers used :None
ISP 1200 ;* High registers used :2 (bitcnt,Txbyte)
AVR SPI ;* Pointers used :None
;*
I2C 300 ;
I2C 302 ***************************************************************************
.equ sb =1 ;Number of
I2C TWI26
stop bits (1, 2, ...)
I2C/TWI 128
I2C/TWI AT8 putchar: ldi bitcnt,9+sb ;1+8+sb (sb is # of
stop bits)
DALLAS-1W com Txbyte ;Inverte everything
DALLAS CRC sec ;Start bit

ETHNET 8019 putchar0: brcc putchar1 ;If carry set

TEA cbi PORTD,TxD ; send a '0'
rjmp putchar2 ;else
ADC 128
ADC 10B putchar1: sbi PORTD,TxD ; send a '1'
nop
ADC 400
ADC 401 putchar2: rcall UART_delay ;One bit delay
THERM 232 rcall UART_delay

IRD 410 lsr Txbyte ;Get next bit

LCD HD44 dec bitcnt ;If not all bit sent
brne putchar0 ; send next
LCD 2313 ;else
LCD44 2313 ret ; return
KBD 240
MUX 242 ;
***************************************************************************
KBD PS2
;*
KBD PC/128 ;* "getchar"
PS2 EMU ;*
;* This subroutine receives one byte and returns it in
BOOT MG8 the "Rxbyte" register
BOOT DR8 ;*
;* Number of words :14 including return
ALM CLK ;* Number of cycles :Depens on when data arrives
CLOCK 8564 ;* Low registers used :None
;* High registers used :2 (bitcnt,Rxbyte)
90 DAYS
;* Pointers used :None
DELAYS ;*
;
CALL ID
***************************************************************************
DTMF 314
PWM 6CH getchar: ldi bitcnt,9 ;8 data bit + 1
stop bit
PWM 10K
ENCODE getchar1: sbic PIND,RxD ;Wait for start bit
rjmp getchar1
STH-11
ATMEL CORP rcall UART_delay ;0.5 bit delay
AVR
getchar2: rcall UART_delay ;1 bit delay
BUTTERFLY rcall UART_delay
AVR BOOK
clc ;clear carry
sbic PIND,RxD ;if RX pin high
sec ;

dec bitcnt ;If bit is stop bit

breq getchar3 ; return
;else
ror Rxbyte ; shift bit into
Rxbyte
rjmp getchar2 ; go get next

getchar3: ret

;
***************************************************************************
;*
;* "UART_delay"
;*
;* This delay subroutine generates the required delay
between the bits when
;* transmitting and receiving bytes. The total
execution time is set by the
;* constant "b":
;*
;* 3·b + 7 cycles (including rcall and ret)
;*
;* Number of words :4 including return
;* Low registers used :None
;* High registers used :1 (temp)
;* Pointers used :None
;*
;
***************************************************************************
; Some b values: (See also table in Appnote
documentation)
;
; 1 MHz crystal:
; 9600 bps - b=14
; 19200 bps - b=5
; 28800 bps - b=2
;
; 2 MHz crystal:
; 19200 bps - b=14
; 28800 bps - b=8
; 57600 bps - b=2

; 4 MHz crystal:
; 19200 bps - b=31
; 28800 bps - b=19
; 57600 bps - b=8
; 115200 bps - b=2

.equ b =31 ;19200 bps @ 4 MHz crystal

UART_delay: ldi temp,b

UART_delay1: dec temp
brne UART_delay1

ret

;***** Program Execution Starts Here

;***** Test program

reset: sbi PORTD,TxD ;Init port

pins
sbi DDRD,TxD

ldi Txbyte,12 ;Clear terminal

rcall putchar

forever: rcall getchar

mov Txbyte,Rxbyte
rcall putchar ;Echo received char
rjmp forever

Programming the AVR Microcontrollers in Machine Language

AVR
<< Prev | Ring Hub | Join | Rate| Next
>>
© WebRing Inc. Search

Atmel AVR From Wikipedia, the free encyclopedia (Redirected

from Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing,
intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still
be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language

http://avr-asm.tripod.com/avr305.html (1 of 2)1/20/2009 8:54:26 PM

16 BIT MATH (AVR 202)

http://avr-asm.tripod.com/avr305.html (2 of 2)1/20/2009 8:54:26 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

UART ROUTINES FOR ATMEGA128

HOME
RETRO_DAN
;
ASM FORUM ***************************************************************************
ASM MATH ;
; File Name :'M_rs232.asm"
TUTORIAL #1
; Title : ATmega128 UART, RS-232
TUTORIAL #2 komunikacios rutinok
TUTORIAL #3 ; Date :2003.02.08. Lastmod.:
[2003.02.08.]
MATH 200 ; Version :1.0.0
MATH 200b ; Support telephone :+36-70-333-4034, Old: +36-30-9541-
658 VFX
MATH 201 ; Support fax :
MATH 202 ; Support Email :info@vfx.hu
; Target MCU :ATmaga128
MATH 32X
;
MATH YX ;
***************************************************************************
DIV16 XX
; D E S C R I P T I O N
DIV 24 24 ;
DIV 3216 ; Universal Synchronous and Asynchronous serial
Receiver and Transmitter (USART)
FLOAT 128 ;
SQRT16 ;Circular serial I/O buffers, with handshake handling
for hardware.
MATH 202 ;Interupt driven, thus 'transparent' to User functions
MATH 202 ;
;You have a head and tail pointer, a constant that
DEC ASCII
tells the size of the array
INT ASCII ;
;One thing to note, is that the buffer store routine is
HX2ASC
only concerned with the
AVG8 222 ;tail pointer, and the recall routine is only concerned
FFT7 with the head pointer.
;Only the buffer init routine is concerned with both
COPY 102 pointers!
LPM 108 ;
;
EPROM 100 ;
SER EPROM ***************************************************************************
; M O D I F I C A T I O N H I S T O R Y
DFLASH AT45
;
FLASH CARD ;
; rev. date who why
VFX SMIL
; ---- ---------- ---
VFX MEM --------------------------------------------
SORT 220 ; 0.01 2001.07.21 VFX Creation (Base on
8515)
CRC 236 ; 1.00 2003.02.08 VFX Redesign for
XMODEM REC Atmega128
;
UART 304 ;
UART 305 ***************************************************************************
;
UART 128
; Init_UART
UART BUFF ; SendChr
; SendStr
USB 232
;
AVR ISP ;
ISP 2313 ;Hardware
;
ISP 1200 ***************************************************************************
AVR SPI ;*
;RTS pin , Adas keres DSUB9
I2C 300 7.
I2C 302 .equ SER_HSO_PORT=PORTD ;Hardware Handshake
output port
I2C TWI26
.equ SER_HSO_DIR=DDRD ;Hardware Handshake
I2C/TWI 128 output control
I2C/TWI AT8 .equ SER_HSO=7 ;Hardware Handshake
Output bit
DALLAS-1W
DALLAS CRC ;CTS pin , Vetelkezseg
nyugtazo DSUB9 8.
ETHNET 8019 .equ SER_HSI_PORT=PIND ;Hardware Handshake
TEA input port
.equ SER_HSI_DIR=DDRD ;Hardware Handshake
ADC 128 input control
ADC 10B .equ SER_HSI=5 ;Hardware Handshake
Input bit
ADC 400
ADC 401
THERM 232 .MACRO HS_Enabled
cbi SER_HSO_PORT,SER_HSO ;
IRD 410 Set low, HS to off
LCD HD44 .endm

LCD 2313 .MACRO HS_Disabled

LCD44 2313 sbi SER_HSO_PORT,SER_HSO ;
Set Hi for Dis
KBD 240 .endm
MUX 242
KBD PS2
;
KBD PC/128 **************************************************************************
PS2 EMU ;* Const Def

BOOT MG8
BOOT DR8 ;
********************************************************************
ALM CLK ;
CLOCK 8564 ;ASCII Equivalents
;
90 DAYS
.equ NUL=0x00 ;Null
DELAYS .equ SOH=0x01 ;Start of Header
.equ STX=0x02 ;Start of Text
CALL ID
.equ ETX=0x03 ;End of Text
DTMF 314 .equ EOT=0x04 ;End of Transmission
PWM 6CH .equ ENQ=0x05 ;Enquiry
.equ ACK=0x06 ;Acknowlege
PWM 10K .equ BEL=0x07 ;Bell
ENCODE .equ BS=0x08 ;Backspace
.equ HT=0x09 ;Horizontal Tab
STH-11 .equ LF=0x0A ;Line Feed
ATMEL CORP .equ VT=0x0B ;Vertical Tab
.equ FF=0x0C ;Form Feed
AVR
.equ CR=0x0D ;Carriage Return
BUTTERFLY .equ SO=0x0E ;
AVR BOOK .equ SI=0x0F ;

.equ DLE=0x10 ;Delete

.equ XON=0x11 ;AKA DC1
.equ XOFF=0x12 ;AKA DC2
.equ DC3=0x13 ;
.equ DC4=0x14 ;
.equ NAK=0x15 ;Negative Acknowlege
.equ SYN=0x16 ;Sync
.equ ETB=0x17 ;
.equ CAN=0x18 ;Cancel
.equ EM=0x19 ;
.equ SUB=0x1A ;End of File
.equ ESC=0x1B ;
.equ FS=0x1C ;Field Separator
.equ GS=0x1D ;Group Separator
.equ RS=0x1E ;Record Separator
.equ US=0x1F ;

;From the data sheet:BAUD = XTAL/(16*(UBRR+1))

;Rearranging you get:UBRR = XTAL/(16*BAUD) - 1
;
;This would work except that any fraction will be
truncated.
;For least error we want to round off the result.
;So we add 1/2 as follows: UBRR = XTAL/(16*BAUD) - 1 +
0.5
;Combining the -1 and the +0.5 we can rewrite this as
follows:
;
;UBRR = INT(XTAL/(16*BAUD) - 0.5)

.equ Rx_Buffer_Length = 24
.equ Tx_Buffer_Length = 32

.equ SendROMTXT = 0x02 ;RS232 Tx

func. Send ROM text to RS232

.equ FlSending = 0b00000001 ;Tx Send

running
.equ FlSendROM = 0b00000010 ;Tx Send
ROM TXT Flag

;
***************************************************************************
.DSEG

Rx_Buffer:
Rx_Head: .byte 1
Rx_Tail: .byte 1
Rx_Data: .byte Rx_Buffer_Length

Tx_Buffer:
Tx_Head: .byte 1
Tx_Tail: .byte 1
Tx_Data: .byte Tx_Buffer_Length

UARTFlg: .byte 1 ;UART Flags

ROMTXT: .byte 3 ;ROM TXT
kuldeskor az aktualis ROM pozicio cime

;
*************************************************************************
;* Text Const
;*
.CSEG

;
************************************************************************
;** Init_UART1
;** Set up the inital states for the buffers, and make
sure the handshake
;** is turned on (Not the Shaddap state), so we can
talk.
;**
;**
;
************************************************************************
Init_UART1: ldi R16,0
sts Tx_Tail,R16
sts Tx_Head,R16
sts Rx_Tail,R16
sts Rx_Head,R16
sts UARTFlg,R16

sts CMD_Len,R16
sts CMD_Pos,R16

;Set up
Hardware HS I/O bits
sbi SER_HSO_DIR,SER_HSO ;Set as
output
HS_Enabled

cbi SER_HSI_PORT,SER_HSI ;Set as

input, Pull-up
cbi SER_HSI_DIR,SER_HSI

ldi R16,High(SYSCLK/(16*BaudSpeed1)-1)
sts UBRR1H,R16
ldi R16,Low(SYSCLK/(16*BaudSpeed1)-1)
sts UBRR1L,R16 ;BaudRate
Gen.

ldi R16,0b00000000 ;RXCn,

TXCn, UDREn, FEn, DORn, UPEn, U2Xn, MPCMn
sts UCSR1A,R16

ldi R16,0b11011000 ;RXCIE,

TXCIE,UDRIE,RXEN,TXEN,UCSZn2,RXB8,TXB8
sts UCSR1B,R16

ldi R16,0b00000110 ;–, UMSELn,

UPMn1, UPMn0, USBSn, UCSZn1, UCSZn0, UCPOLn
sts UCSR1C,R16
ret

ECopyr: .DB "(C) 2003 VFX ATmega128 Service

Terminal [2003.02.08.]",CR
.DB "Firmware version ",MAJOR_REV,".",
MINOR_REV,MINOR_REVB," "
.DB "Latest Upd.: 2003.05.01.",CR,0

;***********************************************
;* Megnezi, hogy kell-e ujrainditani a Tx muveletet

TxRunning: lds ZL,Tx_Head

lds ZH,Tx_Tail
cp ZL,ZH ;ha
azonosak akkor nincs mit tenni
breq TxRun1
lds ZL,UARTFlg
andi ZL,FlSending ;Tx
folyamatban?
brne TxRun1 ;ha igen
nincs mit tenni
rjmp USART1_TXC
TxRun1: ret

;
***************************************************************************
;
***************************************************************************
;
***************************************************************************
;** UART TX Functions
;
***************************************************************************
; kod Bufferbe
Osszesen
; 0x02 - send ROM TXT -> 0xE0, 0x02, low addr, hi
addr ; 4 byte
; 0xE0 - send 0xE0 -> 0xE0,
0xE0 ; 2 byte

;
************************************************************************
;** Calc Tx Buffer Free Space
; In: -
; Out: R18 - Tx_Tail
; R19 - Tx_Head
; R20 - Free Space in Tx Buffer
; Alt: R21
;
; Tail < Head -> Free= LEN+Tail-Head-1
; Tail = Head -> Free= LEN
; Tail > Head -> Free= Tail-Head-1
;
FreeInTxBuff: lds R19,Tx_Head
lds R18,Tx_Tail
ldi R20,Tx_Buffer_Length
mov R21,R18
sub R21,R19
breq FreeInTx1 ;T=H, Free=
Tx_Buffer_Length
brcs FreeInTx2
clr R20
FreeInTx2: add R20,R21
dec R20
FreeInTx1: ret

;************************************************
;* The RS232 Tx FIFO manager ROM TEXT *
;* In: (R16, R17) address word of text (L,
H) *
;* Out: c=1 hiba *
;************************************************
SendStr: rcall FreeInTxBuff ;R18,R19-t
is beallitja
cpi R20,4
brcs ExitwError ;ha <4
nincs eleg hely! Hiba!

clr R18 ;R18=0

ldi ZL,low(Tx_Data) ;Z to the
addr of txbuffer (FIFO)
ldi ZH,high(Tx_Data)
add ZL,R19
adc ZH,R18 ;add
address offset... z = @Buf[Tx_head]
push R16
ldi R16,0xE0 ;
Alternative function indicator

cli

rcall StoreChar
ldi R16,SendROMTXT ;Buf
[Tx_head]=SendROMTXT indicate Send ROM TXT
rcall StoreChar
pop R16
rcall StoreChar ;Buf
[Tx_head]=RomTXT low address

sei

mov R16,R17 ;Store

RomTXT high address
rcall StoreChar
sts Tx_Head,R19 ;Store new
pointer

rcall TxRunning

clc ;Nincs hiba

ret

ExitwError: sec ;Return

with error
ret

SendStrW: rcall SendStr

brcs SendStrW
ret

;************************************************
;* The RS232 Tx FIFO manager Send CHAR *
;* in: R16 char *
;* out c=1 hiba *
;************************************************
SendChr: rcall FreeInTxBuff ;R18,R19-t
is beallitja
cpi R20,2
brcs ExitwError ;ha <1
nincs elg hely! Hiba!

clr R18 ;R18=0

ldi ZL,low(Tx_Data) ;Pointer to
the txbuffer (FIFO)
ldi ZH,high(Tx_Data)
add ZL,R19
adc ZH,R18 ;add
address offset... z = @Buf[txhead]

cpi R16,0xE0 ;
Alternative kod?
brne only1char ;ha igen
akkor ketszer kell atkuldeni!!
rcall StoreChar
only1char: rcall StoreChar
sts Tx_Head,R19

rcall TxRunning

clc ; Nincs hiba

ret

SendChrW: push ZL
push ZH
rcall SendChr
pop ZH
pop ZL
brcs SendChrW
ret

;***********************************************
; Subrutin for SendROMTXT & SendChar

StoreChar: st Z+,R16 ;Store char

inc R19
cpi R19,Tx_Buffer_Length
brcs StoreC1 ;TxHead

Programming the AVR Microcontrollers in Machine Language

AVR
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected

from Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing,
intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still
be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
http://avr-asm.tripod.com/uart128.html (1 of 2)1/20/2009 8:55:05 PM
16 BIT MATH (AVR 202)

either 16 or 32 bits in length. The Flash memory is addressed

using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language

http://avr-asm.tripod.com/uart128.html (2 of 2)1/20/2009 8:55:05 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

UART RING BUFFER

HOME
RETRO_DAN
;--------------------------------------------------------
ASM FORUM ; A UART RING BUFFER
ASM MATH ;--------------------------------------------------------
.equ rxfifo_length = 0x40 ; length or size
TUTORIAL #1
of RX fifo buffer (64 bytes)
TUTORIAL #2 .equ txfifo_length = 0x40 ; length or size
TUTORIAL #3 of TX fifo buffer (64 bytes)

MATH 200 ; Arrays

MATH 200b .DSEG
.org 0x00C0
MATH 201
MATH 202 ; UART ring buffers
MATH 32X
rxfifo_n:
MATH YX .byte 1 ; number of
bytes currently stored in buffer (init: 0)
DIV16 XX
DIV 24 24 rxfifo_in:
DIV 3216 .byte 2 ; pointer to
address in buffer written to (init: rxfifo_base)
FLOAT 128
SQRT16 rxfifo_out:
.byte 2 ; pointer to
MATH 202 address in buffer read from (init: rxfifo_base)
MATH 202
rxfifo_base:
DEC ASCII
.byte rxfifo_length ; reserves
INT ASCII fifo_length bytes for the
; buffer and is
HX2ASC
used as the buffer’s base address
AVG8 222
FFT7
txfifo_n:
COPY 102 .byte 1 ; number of
LPM 108 bytes currently stored in buffer (init: 0)
EPROM 100 txfifo_in:
SER EPROM .byte 2 ; pointer to
address in buffer written to (init: txfifo_base)
DFLASH AT45
FLASH CARD txfifo_out:
.byte 2 ; pointer to
VFX SMIL
address in buffer read from (init: txfifo_base)
VFX MEM
SORT 220 txfifo_base:
.byte txfifo_length ; reserves
CRC 236 fifo_length bytes for the
XMODEM REC ; buffer and is
used as the buffer’s base address
UART 304
UART 305 ;---------------
UART 128
;
UART BUFF ***************************************************************************
;*
USB 232
;* "USART_UDRE" interrupt handler
AVR ISP ;* Transmits data pending in TX buffer in predefined
ISP 2313 baud rate & 8n1
;* (RTS handshake via pin PB0, CTS_in; single- or multi-
ISP 1200 byte transfers)
AVR SPI ;*
;* All regs saved
I2C 300 ;*
I2C 302 ;
***************************************************************************
I2C TWI26
I2C/TWI 128 USART_UDRE:
I2C/TWI AT8 sbic UCSRA,RXC ; if receiving (RXC
"1"),
DALLAS-1W rjmp U_Tx5 ; exit immediately
DALLAS CRC
push Flags_tmp
ETHNET 8019 in Flags_tmp,SREG ; flags may be changed
TEA by arithmetics,
push Flags_tmp ; so save the
ADC 128 status register
ADC 10B push Tmp1
push Tmp2
ADC 400
ADC 401 U_Tx1:
THERM 232 sbrs B_Flags4,2 ; set: use HW handshake
rjmp Get_txfifo ; don't use handshake
IRD 410 sbic PINB,0 ; check CTS_in (low =
LCD HD44 pardner ready for receive)
rjmp U_Tx3 ; pardner not ready, try
LCD 2313 later (exit), else
LCD44 2313
KBD 240 Get_txfifo: ; fetch a byte from TX buffer and
MUX 242 transmit it
lds Tmp1,txfifo_n
KBD PS2
tst Tmp1 ; buffer empty?
KBD PC/128 breq U_Tx3
PS2 EMU sts save_Y,YL
sts save_Y + 1,YH
BOOT MG8 lds YL,txfifo_out
BOOT DR8 lds YH,txfifo_out + 1
ld Tmp2,Y+ ; ** data_out **
ALM CLK out UDR,Tmp2 ; to UART transmit
CLOCK 8564 dec Tmp1
sts txfifo_n,Tmp1
90 DAYS
brne tx_notclr ; buffer not yet empty!
DELAYS cbr B_Flags3,0x40 ; else: clear TX data
pending flag
CALL ID
cbi UCSRB,UDRIE ; and disable UDRE int
DTMF 314
PWM 6CH tx_notclr:
ldi Tmp2,high(txfifo_base + txfifo_length)
PWM 10K cpi YL,low(txfifo_base + txfifo_length)
ENCODE cpc YH,Tmp2
brne end_get_txfifo
STH-11 ldi YL,low(txfifo_base)
ATMEL CORP ldi YH,high(txfifo_base)
AVR
end_get_txfifo:
BUTTERFLY sts txfifo_out,YL
AVR BOOK sts txfifo_out + 1,YH
lds YL,save_Y
lds YH,save_Y + 1

exit_get_txfifo:
rjmp U_Tx4 ; (remove this for multi-
byte transmits)
;rjmp U_Tx1 ; (loop until all bytes
are sent -
; remove this for a one
byte transmit)
U_Tx3:
cbi UCSRB,UDRIE ; disable UDRE int to
avoid ADC lock-up if
; HW handshake is active
U_Tx4:
pop Tmp2
pop Tmp1
pop Flags_tmp
out SREG,Flags_tmp ; restore the status
register
pop Flags_tmp

U_Tx5:
reti

;**** End of USART_UDRE interrupt handler

**********************************

;
***************************************************************************
;*
;* "USART_Rx" interrupt handler
;*
;* Stores received bytes to fifo ring buffer
("Add_txfifo")
;* Checks for errors, skips byte if error
;*
;* All regs saved
;*
;
***************************************************************************

USART_RXC:
push Flags_tmp
in Flags_tmp,SREG ; flags may be changed
by arithmetics,
push Flags_tmp ; so save the
status register
push Tmp1
push Tmp3

U_R1:
in Tmp1,UCSRA ; get status
ldi Tmp3,0b00011100
and Tmp1,Tmp3 ; isolate bits 4-2
tst Tmp1 ; if not zero, we have
an error
breq U_R_cont ; no error

in Tmp1,UDR ; fetch defective byte,

clear its error bits
;call Init_rxbuf ; (flush rx fifo buffer,
too)
;**call error handler
rjmp U_R2 ; continue -> test fifo
for another byte

U_R_cont:
in Tmp1,UDR ; get data from UDR ...

; Add_rxfifo - routine ; ... and store it to RX

buffer
lds Tmp3,rxfifo_n ; check if
buffer full

cpi Tmp3,rxfifo_length - 3 ; if buffer

almost full, push RTS_out high
brsh stop_rx ; (-> HW
handshake, "stop", used if no rollover)

add_rxfifo_HWoff:
cpi Tmp3,rxfifo_length ; check if
buffer full
breq full_rxfifo_n ; if so, deal
with that

add_rxfifo_cont:
sts save_Y,YL ; save Y reg
pair
sts save_Y + 1,YH
lds YL,rxfifo_in ; setup FIFO_in
lds YH,rxfifo_in + 1
st Y+,Tmp1 ; ** store data
from Tmp1 **

sbr B_Flags4,0x02 ; set bit 1: rx

data received and pending
inc Tmp3 ; inc FIFO_n
sts rxfifo_n,Tmp3

; 16-bit cpi with FIFO_base + FIFO_length

ldi Tmp3,high(rxfifo_base + rxfifo_length)
cpi YL,low(rxfifo_base + rxfifo_length)
cpc YH,Tmp3
brne end_add_rxfifo ; if end of
buffer ram reached,
ldi YL,low(rxfifo_base) ; rollover: load
FIFO_in with
ldi YH,high(rxfifo_base) ; FIFO_base

end_add_rxfifo:
sts rxfifo_in,YL ; store FIFO_in
sts rxfifo_in + 1,YH
lds YL,save_Y ; restore Y reg
pair
lds YH,save_Y + 1

exit_add_rxfifo:
rjmp U_R2 ; return (Exit
Add_rxfifo routine)

full_rxfifo_n: ; buffer is full: either

; overwrite older data in buffer (buffer
rollover)
;sbr B_Flags4,0x02 ; clear bit 1,
no more rx data pending
;rjmp add_rxfifo_cont

; or, alternative: call error handler

and end
;**call rxfifo_err
rjmp exit_add_rxfifo

stop_rx: ; alternative if no buffer rollover

RTS_high ; HW handshake,
"stop"
rjmp add_rxfifo_HWoff

U_R2:
sbic UCSRA,RXC ; another byte pending
in fifo?
rjmp U_R1 ; yes, loop

U_R_exit:

pop Tmp3
pop Tmp1
pop Flags_tmp
out SREG,Flags_tmp ; restore the status
register
pop Flags_tmp
reti

;**** End of USART_RCX interrupt handler

-------------------------------****

;
***************************************************************************
;*
;* UART ring buffer functions
;*
;* ("Add_rxfifo": store a byte from IO_Source (UDR) to
buffer, -> ISR)
;* "Get_rxfifo": return 1 byte from rx ring buffer in
Tmp2
;*
;* "Add_txfifo": store a byte to transmit buffer
;* ("Get_txfifo": transmits the bytes stored in
transmit buffer -> ISR)
;*
;* "Init_rx/txbuf": initialize/clear fifo ring buffers
(RX / TX)
;*
;
***************************************************************************

;
**************************************************************************

Get_rxfifo: ; returns a byte from RX buffer in Tmp2

; (all regs saved, comments cf.
add_rxFIFO)
push Tmp1
push Tmp3
lds Tmp1,rxfifo_n
cpi Tmp1,rxfifo_length - 8 ; if buffer no
longer almost full,
brlo start_rx ; set RTS_out
low again (ready to receive)

get_rxfifo_cont:
tst Tmp1
breq exit_get_rxfifo
sts save_Y,YL
sts save_Y + 1,YH
lds YL,rxfifo_out
lds YH,rxfifo_out + 1
ld Tmp2,Y+ ; ** data_out to
Tmp2 **
dec Tmp1
sts rxfifo_n,Tmp1
brne rx_notclr
cbr B_Flags4,0x02 ; rx buffer
empty: clear "data pending" bit

rx_notclr:
ldi Tmp3,high(rxfifo_base + rxfifo_length)
cpi YL,low(rxfifo_base + rxfifo_length)
cpc YH,Tmp3
brne end_get_rxfifo
ldi YL,low(rxfifo_base)
ldi YH,high(rxfifo_base)

end_get_rxfifo:
sts rxfifo_out,YL
sts rxfifo_out + 1,YH
lds YL,save_Y
lds YH,save_Y + 1

exit_get_rxfifo:
pop Tmp3
pop Tmp1
ret ; EXIT function

start_rx: ; switch receive

on again
RTS_low
rjmp get_rxfifo_cont

;
**************************************************************************
;
**************************************************************************

Add_txfifo: ; stores a byte to TX buffer / all regs

saved
; entry with data to-be-stored in Tmp2
push Tmp1
push Tmp3

lds Tmp3,txfifo_n ; load # of

chars pending

cpi Tmp3,txfifo_length ; check if

buffer full
breq full_txfifo_n ; if so, deal
with that

add_txfifo_cont:
sbr B_Flags3,0x40 ; set TX data
pending flag
;sbi UCSRB,UDRIE ; (enable UDRE
int to start transmit!)
sts save_Y,YL ; save Y reg
pair
sts save_Y + 1,YH
lds YL,txfifo_in ; setup FIFO_in
lds YH,txfifo_in + 1
st Y+,Tmp2 ; ** store data
from Tmp2 **
inc Tmp3 ; inc FIFO_n
sts txfifo_n,Tmp3

; 16-bit cpi with FIFO_base + FIFO_length

ldi Tmp3,high(txfifo_base + txfifo_length)
cpi YL,low(txfifo_base + txfifo_length)
cpc YH,Tmp3
brne end_add_txfifo ; if end of
buffer ram reached,
ldi YL,low(txfifo_base) ; rollover: load
FIFO_in with
ldi YH,high(txfifo_base) ; FIFO_base

end_add_txfifo:
sts txfifo_in,YL ; store FIFO_in
sts txfifo_in + 1,YH
lds YL,save_Y ; restore Y reg
pair
lds YH,save_Y + 1

exit_add_txfifo:
pop Tmp3
pop Tmp1
ret ; return

full_txfifo_n: ; buffer is full: either

; overwrite older data in buffer (buffer
rollover)
;rjmp add_txfifo_cont

; or, alternative: call error handler

and end
;call txfifo_err
rjmp exit_add_txfifo

;
**************************************************************************
;
**************************************************************************

; routines to initialize the RX / TX buffers

; All regs saved

Init_rxbuf:
push YH
push YL
push Tmp1

; init rx buffer
clr YL
sts rxfifo_n,YL
ldi YL,low(rxfifo_base)
ldi YH,high(rxfifo_base)
sts rxfifo_in,YL
sts rxfifo_in + 1,YH
sts rxfifo_out,YL
sts rxfifo_out + 1,YH

cbr B_Flags4,0x02 ; clear "rx data

pending" bit
clr Tmp1 ; reset FIFO_n
sts rxfifo_n,Tmp1

pop Tmp1
pop YL
pop YH
ret

Init_txbuf:
push YH
push YL
push Tmp1

; init tx buffer
clr YL
sts txfifo_n,YL
ldi YL,low(txfifo_base)
ldi YH,high(txfifo_base)
sts txfifo_in,YL
sts txfifo_in + 1,YH
sts txfifo_out,YL
sts txfifo_out + 1,YH

cbr B_Flags3,0x40 ; clear "tx data

pending" bit
clr Tmp1 ; reset FIFO_n
sts txfifo_n,Tmp1

pop Tmp1
pop YL
pop YH
ret

;**** End of UART buffer functions -----

Programming the AVR Microcontrollers in Machine Language

AVR
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected

from Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with many
additional features for audio and video processing, intended to
compete with ARM based processors. Note that the use of
"AVR" in this article refers to the 8-bit RISC line of Atmel AVR
Microcontrollers. The acronym AVR has been reported to
stand for Advanced Virtual RISC. It's also rumoured to stand
for the company's founders: Alf and Vegard, who are evasive
when questioned about it. Contents [hide] 1 Device Overview
1.1 Program Memory 1.2 Data Memory and Registers 1.3
EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3
Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel
Official Links 6.2 AVR Forums & Discussion Groups 6.3
Machine Language Development 6.4 C Language Development
6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific
6.7 Other AVR Links [edit] Device Overview The AVR is a
Harvard architecture machine with programs and data stored
and addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The working
registers are mapped in as the first thirty-two memory spaces
(000016-001F16) followed by the 64 I/O registers (002016-
005F16). The actual usable RAM starts after both these
sections (address 006016). (Note that the I/O register space
may be larger on some more extensive devices, in which case
memory mapped I/O registers will occupy a portion of the
SRAM.) Even though there are separate addressing schemes
and optimized opcodes for register file and I/O register access,
all can still be addressed and manipulated as if they were in
SRAM. [edit] EEPROM Almost all devices have on-die
EEPROM. This is most often used for long-term parameter
storage to be retrieved even after cycling the power of the
device. [edit] Program Execution Atmel's AVRs have a single
level pipeline design. The next machine instruction is fetched
as the current one is executing. Most instructions take just
one or two clock cycles, making AVRs relatively fast among
the eight-bit microcontrollers. The AVR family of processors
were designed for the efficient execution of compiled C code.
The AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular: Pointer
registers X, Y, and Z have addressing capabilities that are
different from each other. Register locations R0 to R15 have
different addressing capabilities than register locations R16 to
R31. I/O ports 0 to 31 have different addressing capabilities
than I/O ports 32 to 63. CLR affects flags, while SER does not,
even though they are complementary instructions. CLR set all
bits to zero and SER sets them to one. (Note though, that
neither CLR nor SER are native instructions. Instead CLR is
syntactic sugar for [produces the same machine code as] EOR
R,R while SER is syntactic sugar for LDI R,$FF. Math
operations such as EOR modify flags while moves/loads/
stores/branches such as LDI do not.) [edit] Speed The AVR
line can normally support clock speeds from 0-16MHz, with
some devices reaching 20MHz. Lower powered operation
usually requires a reduced clock speed. All AVRs feature an
on-chip oscillator, removing the need for external clocks or
resonator circuitry. Because many operations on the AVR are
single cycle, the AVR can achieve up to 1MIPS per MHz. [edit]
Development AVRs have a large following due to the free and
inexpensive development tools available, including reasonably
priced development boards and free development software.
The AVRs are marketed under various names that share the
same basic core but with different peripheral and memory
combinations. Some models (notably, the ATmega range) have
additional instructions to make arithmetic faster. Compatibility
amongst chips is fairly good. See external links for sites
relating to AVR development. [edit] Features Current AVRs
offer a wide range of features: RISC Core Running Many Single
Cycle Instructions Multifunction, Bi-directional I/O Ports with
Internal, Configurable Pull-up Resistors Multiple Internal
Oscillators Internal, Self-Programmable Instruction Flash
Memory up to 256K In-System Programmable using ICSP,
JTAG, or High Voltage methods Optional Boot Code Section
with Independent Lock Bits for Protection Internal Data
EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit
Timers PWM Channels & dead time generator Lighting (PWM
Specific) Controller models Dedicated I²C Compatible Two-
Wire Interface (TWI) Synchronous/Asynchronous Serial
Peripherals (UART/USART) (As used with RS-232,RS-485, and
more) Serial Peripheral Interface (SPI) CAN Controller Support
USB Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-speed
(HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR assembler
programming language Atmel AVR machine programming
language Atmel AVR From Wikipedia, the free encyclopedia
(Redirected from Avr) Jump to: navigation, search The AVRs
are a family of RISC microcontrollers from Atmel. Their
internal architecture was conceived by two students: Alf-Egil
Bogen and Vegard Wollan, at the Norwegian Institute of
Technology (NTH] and further developed at Atmel Norway, a
subsidiary founded by the two architects. Atmel recently
released the Atmel AVR32 line of microcontrollers. These are
32-bit RISC devices featuring SIMD and DSP instructions,
along with many additional features for audio and video
processing, intended to compete with ARM based processors.
Note that the use of "AVR" in this article refers to the 8-bit
RISC line of Atmel AVR Microcontrollers. The acronym AVR
has been reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5
Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages 6.6
AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still be
addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were designed
for the efficient execution of compiled C code. The AVR
instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular: Pointer
registers X, Y, and Z have addressing capabilities that are
different from each other. Register locations R0 to R15 have
different addressing capabilities than register locations R16 to
R31. I/O ports 0 to 31 have different addressing capabilities
than I/O ports 32 to 63. CLR affects flags, while SER does not,
even though they are complementary instructions. CLR set all
bits to zero and SER sets them to one. (Note though, that
neither CLR nor SER are native instructions. Instead CLR is
syntactic sugar for [produces the same machine code as] EOR
R,R while SER is syntactic sugar for LDI R,$FF. Math
operations such as EOR modify flags while moves/loads/
stores/branches such as LDI do not.) [edit] Speed The AVR
line can normally support clock speeds from 0-16MHz, with
some devices reaching 20MHz. Lower powered operation
usually requires a reduced clock speed. All AVRs feature an
on-chip oscillator, removing the need for external clocks or
resonator circuitry. Because many operations on the AVR are
single cycle, the AVR can achieve up to 1MIPS per MHz. [edit]
Development AVRs have a large following due to the free and
inexpensive development tools available, including reasonably
priced development boards and free development software.
The AVRs are marketed under various names that share the
same basic core but with different peripheral and memory
combinations. Some models (notably, the ATmega range) have
additional instructions to make arithmetic faster. Compatibility
amongst chips is fairly good. See external links for sites
relating to AVR development. [edit] Features Current AVRs
offer a wide range of features: RISC Core Running Many Single
Cycle Instructions Multifunction, Bi-directional I/O Ports with
Internal, Configurable Pull-up Resistors Multiple Internal
Oscillators Internal, Self-Programmable Instruction Flash
Memory up to 256K In-System Programmable using ICSP,
JTAG, or High Voltage methods Optional Boot Code Section
with Independent Lock Bits for Protection Internal Data
EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit
Timers PWM Channels & dead time generator Lighting (PWM
Specific) Controller models Dedicated I²C Compatible Two-
Wire Interface (TWI) Synchronous/Asynchronous Serial
Peripherals (UART/USART) (As used with RS-232,RS-485, and
more) Serial Peripheral Interface (SPI) CAN Controller Support
USB Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-speed
(HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR assembler

http://avr-asm.tripod.com/uartbuff.html (1 of 2)1/20/2009 8:55:41 PM

16 BIT MATH (AVR 202)

programming language Atmel AVR machine programming

language Atmel AVR From Wikipedia, the free encyclopedia
(Redirected from Avr) Jump to: navigation, search The AVRs
are a family of RISC microcontrollers from Atmel. Their
internal architecture was conceived by two students: Alf-Egil
Bogen and Vegard Wollan, at the Norwegian Institute of
Technology (NTH] and further developed at Atmel Norway, a
subsidiary founded by the two architects. Atmel recently
released the Atmel AVR32 line of microcontrollers. These are
32-bit RISC devices featuring SIMD and DSP instructions,
along with many additional features for audio and video
processing, intended to compete with ARM based processors.
Note that the use of "AVR" in this article refers to the 8-bit
RISC line of Atmel AVR Microcontrollers. The acronym AVR
has been reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5
Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages 6.6
AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still be
addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were designed
for the efficient execution of compiled C code. The AVR
instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular: Pointer
registers X, Y, and Z have addressing capabilities that are
different from each other. Register locations R0 to R15 have
different addressing capabilities than register locations R16 to
R31. I/O ports 0 to 31 have different addressing capabilities
than I/O ports 32 to 63. CLR affects flags, while SER does not,
even though they are complementary instructions. CLR set all
bits to zero and SER sets them to one. (Note though, that
neither CLR nor SER are native instructions. Instead CLR is
syntactic sugar for [produces the same machine code as] EOR
R,R while SER is syntactic sugar for LDI R,$FF. Math
operations such as EOR modify flags while moves/loads/
stores/branches such as LDI do not.) [edit] Speed The AVR
line can normally support clock speeds from 0-16MHz, with
some devices reaching 20MHz. Lower powered operation
usually requires a reduced clock speed. All AVRs feature an
on-chip oscillator, removing the need for external clocks or
resonator circuitry. Because many operations on the AVR are
single cycle, the AVR can achieve up to 1MIPS per MHz. [edit]
Development AVRs have a large following due to the free and
inexpensive development tools available, including reasonably
priced development boards and free development software.
The AVRs are marketed under various names that share the
same basic core but with different peripheral and memory
combinations. Some models (notably, the ATmega range) have
additional instructions to make arithmetic faster. Compatibility
amongst chips is fairly good. See external links for sites
relating to AVR development. [edit] Features Current AVRs
offer a wide range of features: RISC Core Running Many Single
Cycle Instructions Multifunction, Bi-directional I/O Ports with
Internal, Configurable Pull-up Resistors Multiple Internal
Oscillators Internal, Self-Programmable Instruction Flash
Memory up to 256K In-System Programmable using ICSP,
JTAG, or High Voltage methods Optional Boot Code Section
with Independent Lock Bits for Protection Internal Data
EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit
Timers PWM Channels & dead time generator Lighting (PWM
Specific) Controller models Dedicated I²C Compatible Two-
Wire Interface (TWI) Synchronous/Asynchronous Serial
Peripherals (UART/USART) (As used with RS-232,RS-485, and
more) Serial Peripheral Interface (SPI) CAN Controller Support
USB Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-speed
(HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR assembler
programming language Atmel AVR machine programming
language

http://avr-asm.tripod.com/uartbuff.html (2 of 2)1/20/2009 8:55:41 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

UNIVERSAL SERIAL BUS TO RS232

HOME
RETRO_DAN
;***************************************************************************
ASM FORUM ;* U S B S T A C K F O R T H E A V R F A M I L Y
ASM MATH ;*
;* File Name :"USBtoRS232.asm"
TUTORIAL #1
;* Title :USB stack: USB to RS232 converter + USB to 8-bit I/O pins
TUTORIAL #2 converter + USB to EEPROM recorder
TUTORIAL #3 ;* Date :15.09.2003
;* Version :2.4
MATH 200 ;* Target MCU :ATmega8
MATH 200b ;* AUTHOR :Ing. Igor Cesko
;* Slovakia
MATH 201 ;* cesko@internet.sk
MATH 202 ;* http://www.cesko.host.sk
;*
MATH 32X
;* DESCRIPTION:
MATH YX ;* USB protocol implementation into MCU with noUSB interface:
;* Device:
DIV16 XX
;* Universal USB interface (3x8-bit I/O port + RS232 serial line + EEPROM)
DIV 24 24 ;* + added RS232 FIFO buffer
DIV 3216 ;*
;* The timing is adapted for 12 MHz crystal
FLOAT 128 ;*
SQRT16 ;* Copyright (c) Ing. Igor Cesko 2002-2003
;* All rights reserved
MATH 202 ;*
MATH 202 ;* to add your own functions - see section: TEMPLATE OF YOUR FUNCTION
;*
DEC ASCII
;***************************************************************************
INT ASCII .include "m8def.inc"
;comment for AT90S2313
HX2ASC
.equ UCR =UCSRB
AVG8 222 .equ UBRR =UBRRL
FFT7 .equ EEAR =EEARL
.equ USR =UCSRA
COPY 102 .equ E2END =127
LPM 108 .equ RAMEND128 =96+127
EPROM 100 .equ inputport =PINB
SER EPROM .equ outputport =PORTB
.equ USBdirection =DDRB
DFLASH AT45
.equ DATAplus =1 ;signal D+ na PB1 ;ENG;signal D+
FLASH CARD on PB1
.equ DATAminus =0 ;signal D- na PB0 - treba dat na tento
VFX SMIL
pin pull-up 1.5kOhm ;ENG;signal D- on PB0 - give on this pin pull-up
VFX MEM 1.5kOhm
SORT 220 .equ USBpinmask =0b11111100 ;mask low 2 bits (D+,D-) on PB ;ENG;
mask low 2 bit (D+,D-) on PB
CRC 236 .equ USBpinmaskDplus =~(1<<DATAplus) ;mask D+ bit on PB ;ENG;mask D+
XMODEM REC bit on PB
.equ USBpinmaskDminus =~(1<<DATAminus);mask D- bit on PB ;ENG;mask D-
UART 304 bit on PB
UART 305
.equ TSOPPort =PINB
UART 128
.equ TSOPpullupPort =PORTB
UART BUFF .equ TSOPPin =2 ;signal OUT z IR senzora TSOP1738 na
USB 232 PB2 ;ENG;signal OUT from IR sensor TSOP1738 on PB2

AVR ISP ;.equ LEDPortLSB =PORTD ;pripojenie LED diod LSB ;ENG;
ISP 2313 connecting LED diode LSB
;.equ LEDPinLSB =PIND ;pripojenie LED diod LSB
ISP 1200 (vstup) ;ENG;connecting LED diode LSB (input)
AVR SPI ;.equ LEDdirectionLSB =DDRD ;vstup/vystup LED LSB ;ENG;input/
output LED LSB
I2C 300 ;.equ LEDPortMSB =PORTB ;pripojenie LED diod MSB ;ENG;
I2C 302 connecting LED diode MSB
;.equ LEDPinMSB =PINB ;pripojenie LED diod MSB
I2C TWI26
(vstup) ;ENG;connecting LED diode MSB (input)
I2C/TWI 128 ;.equ LEDdirectionMSB =DDRB ;vstup/vystup LED MSB ;ENG;input/
I2C/TWI AT8 output LED MSB
;.equ LEDlsb0 =3 ;LED0 na pin PD3 ;ENG;LED0 on
DALLAS-1W pin PD3
DALLAS CRC ;.equ LEDlsb1 =5 ;LED1 na pin PD5 ;ENG;LED1 on
pin PD5
ETHNET 8019 ;.equ LEDlsb2 =6 ;LED2 na pin PD6 ;ENG;LED2 on
TEA pin PD6
;.equ LEDmsb3 =3 ;LED3 na pin PB3 ;ENG;LED3 on
ADC 128 pin PB3
ADC 10B ;.equ LEDmsb4 =4 ;LED4 na pin PB4 ;ENG;LED4 on
pin PB4
ADC 400
;.equ LEDmsb5 =5 ;LED5 na pin PB5 ;ENG;LED5 on
ADC 401 pin PB5
THERM 232 ;.equ LEDmsb6 =6 ;LED6 na pin PB6 ;ENG;LED6 on
pin PB6
IRD 410 ;.equ LEDmsb7 =7 ;LED7 na pin PB7 ;ENG;LED7 on
LCD HD44 pin PB7

LCD 2313 .equ SOPbyte =0b10000000 ;Start of Packet byte ;ENG;Start of

LCD44 2313 Packet byte
.equ DATA0PID =0b11000011 ;PID pre DATA0 pole ;ENG;PID for
KBD 240 DATA0 field
MUX 242 .equ DATA1PID =0b01001011 ;PID pre DATA1 pole ;ENG;PID for
DATA1 field
KBD PS2
.equ OUTPID =0b11100001 ;PID pre OUT pole ;ENG;PID for
KBD PC/128 OUT field
PS2 EMU .equ INPID =0b01101001 ;PID pre IN pole ;ENG;PID for
IN field
BOOT MG8 .equ SOFPID =0b10100101 ;PID pre SOF pole ;ENG;PID for
BOOT DR8 SOF field
.equ SETUPPID =0b00101101 ;PID pre SETUP pole ;ENG;PID for
ALM CLK SETUP field
CLOCK 8564 .equ ACKPID =0b11010010 ;PID pre ACK pole ;ENG;PID for
ACK field
90 DAYS
.equ NAKPID =0b01011010 ;PID pre NAK pole ;ENG;PID for
DELAYS NAK field
.equ STALLPID =0b00011110 ;PID pre STALL pole ;ENG;PID for
CALL ID
STALL field
DTMF 314 .equ PREPID =0b00111100 ;PID pre PRE pole ;ENG;PID for
PWM 6CH FOR field

PWM 10K .equ nSOPbyte =0b00000001 ;Start of Packet byte - opacne

ENCODE poradie ;ENG;Start of Packet byte - reverse order
.equ nDATA0PID =0b11000011 ;PID pre DATA0 pole - opacne
STH-11 poradie ;ENG;PID for DATA0 field - reverse order
ATMEL CORP .equ nDATA1PID =0b11010010 ;PID pre DATA1 pole - opacne
poradie ;ENG;PID for DATA1 field - reverse order
AVR
.equ nOUTPID =0b10000111 ;PID pre OUT pole - opacne
BUTTERFLY poradie ;ENG;PID for OUT field - reverse order
AVR BOOK .equ nINPID =0b10010110 ;PID pre IN pole - opacne
poradie ;ENG;PID for IN field - reverse order
.equ nSOFPID =0b10100101 ;PID pre SOF pole - opacne
poradie ;ENG;PID for SOF field - reverse order
.equ nSETUPPID =0b10110100 ;PID pre SETUP pole - opacne
poradie ;ENG;PID for SETUP field - reverse order
.equ nACKPID =0b01001011 ;PID pre ACK pole - opacne
poradie ;ENG;PID for ACK field - reverse order
.equ nNAKPID =0b01011010 ;PID pre NAK pole - opacne
poradie ;ENG;PID for NAK field - reverse order
.equ nSTALLPID =0b01111000 ;PID pre STALL pole - opacne
poradie ;ENG;PID for STALL field - reverse order
.equ nPREPID =0b00111100 ;PID pre PRE pole - opacne
poradie ;ENG;PID for FOR field - reverse order

.equ nNRZITokenPID =~0b10000000 ;PID maska pre Token paket (IN,OUT,SOF,

SETUP) - opacne poradie NRZI ;ENG;PID mask for Token
packet (IN,OUT,SOF,SETUP) - reverse order NRZI
.equ nNRZISOPbyte =~0b10101011 ;Start of Packet byte - opacne poradie
NRZI ;ENG;Start of Packet byte - reverse order NRZI
.equ nNRZIDATA0PID =~0b11010111 ;PID pre DATA0 pole - opacne poradie
NRZI ;ENG;PID for DATA0 field - reverse order NRZI
.equ nNRZIDATA1PID =~0b11001001 ;PID pre DATA1 pole - opacne poradie
NRZI ;ENG;PID for DATA1 field - reverse order NRZI
.equ nNRZIOUTPID =~0b10101111 ;PID pre OUT pole - opacne poradie
NRZI ;ENG;PID for OUT field - reverse order NRZI
.equ nNRZIINPID =~0b10110001 ;PID pre IN pole - opacne poradie
NRZI ;ENG;PID for IN field - reverse order NRZI
.equ nNRZISOFPID =~0b10010011 ;PID pre SOF pole - opacne poradie
NRZI ;ENG;PID for SOF field - reverse order NRZI
.equ nNRZISETUPPID =~0b10001101 ;PID pre SETUP pole - opacne poradie
NRZI ;ENG;PID for SETUP field - reverse order NRZI
.equ nNRZIACKPID =~0b00100111 ;PID pre ACK pole - opacne poradie
NRZI ;ENG;PID for ACK field - reverse order NRZI
.equ nNRZINAKPID =~0b00111001 ;PID pre NAK pole - opacne poradie
NRZI ;ENG;PID for NAK field - reverse order NRZI
.equ nNRZISTALLPID =~0b00000111 ;PID pre STALL pole - opacne poradie
NRZI ;ENG;PID for STALL field - reverse order NRZI
.equ nNRZIPREPID =~0b01111101 ;PID pre PRE pole - opacne poradie
NRZI ;ENG;PID for FOR field - reverse order NRZI
.equ nNRZIADDR0 =~0b01010101 ;Adresa = 0 - opacne poradie
NRZI ;ENG;Address = 0 - reverse order NRZI

;stavove byty - State ;ENG;status bytes -

State
.equ BaseState =0 ;
.equ SetupState =1 ;
.equ InState =2 ;
.equ OutState =3 ;
.equ SOFState =4 ;
.equ DataState =5 ;

;Flagy pozadovanej akcie ;ENG;Flags of

action
.equ DoNone =0
.equ DoReceiveOutData =1
.equ DoReceiveSetupData =2
.equ DoPrepareOutContinuousBuffer =3
.equ DoReadySendAnswer =4

.equ CRC5poly =0b00101 ;CRC5 polynom ;ENG;CRC5

polynomial
.equ CRC5zvysok =0b01100 ;CRC5 zvysok po uspesnom
CRC5 ;ENG;CRC5 remainder after successful CRC5
.equ CRC16poly =0b1000000000000101 ;CRC16 polynom ;ENG;CRC16
polynomial
.equ CRC16zvysok =0b1000000000001101 ;CRC16 zvysok po uspesnom
CRC16 ;ENG;CRC16 remainder after successful CRC16

.equ MAXUSBBYTES =14 ;maximum bytes in USB input

message ;ENG;maximum bytes in USB input message
.equ NumberOfFirstBits =10 ;kolko prvych bitov moze byt
dlhsich ;ENG;how many first bits allowed be longer
.equ NoFirstBitsTimerOffset =256-12800*12/1024 ;Timeout 12.8ms (12800us) na
ukoncenie prijmu po uvodnych bitoch (12Mhz:clock,
1024:timer predivider, 256:timer overflow value) ;ENG;Timeout 12.8ms (12800us) to
terminate after firsts bits
.equ InitBaudRate =12000000/16/57600-1 ;nastavit vysielaciu rychlost
UART-u na 57600 (pre 12MHz=12000000Hz) ;ENG;UART on
57600 (for 12MHz=12000000Hz)

.equ InputBufferBegin =RAMEND128-127 ;zaciatok

prijimacieho shift buffera ;ENG;compare of receiving shift buffer
.equ InputShiftBufferBegin =InputBufferBegin+MAXUSBBYTES ;zaciatok
prijimacieho buffera ;ENG;compare of receiving buffera

.equ OutputBufferBegin =RAMEND128-MAXUSBBYTES-2 ;zaciatok vysielacieho

buffera ;ENG;compare of transmitting buffer
.equ AckBufferBegin =OutputBufferBegin-3 ;zaciatok vysielacieho buffera
Ack ;ENG;compare of transmitting buffer Ack
.equ NakBufferBegin =AckBufferBegin-3 ;zaciatok vysielacieho buffera
Nak ;ENG;compare of transmitting buffer Nak
.equ ConfigByte =NakBufferBegin-1 ;0=unconfigured state ;
ENG;0=unconfigured state
.equ AnswerArray =ConfigByte-8 ;8 byte answer array ;ENG;8
byte answer array
.equ StackBegin =AnswerArray-1 ;spodok zasobnika (stack je
velky cca 68 bytov) ;ENG;low reservoir (stack is big cca 68 byte)

.equ MAXRS232LENGTH =RAMEND-RAMEND128-10 ;maximalna dlzka RS232

kodu ;ENG;maximum length RS232 code
.equ RS232BufferBegin =RAMEND128+1 ;zaciatok buffera pre RS232
prijem ;ENG;compare of buffer for RS232 - receiving
.equ RS232BufferEnd =RS232BufferBegin+MAXRS232LENGTH
.equ RS232ReadPosPtr =RS232BufferBegin+0
.equ RS232WritePosPtr =RS232BufferBegin+2
.equ RS232LengthPosPtr =RS232BufferBegin+4
.equ RS232Reserved =RS232BufferBegin+6
.equ RS232FIFOBegin =RS232BufferBegin+8

.def RS232BufferFull =R1 ;priznak plneho RS232 buffera ;ENG;

flag of full RS232 buffer
.def backupbitcount =R2 ;zaloha bitcount registra v INT0
preruseni ;ENG;backup bitcount register in INT0 disconnected
.def RAMread =R3 ;ci sa ma citat zo SRAM-ky ;ENG;
if reading from SRAM
.def backupSREGTimer =R4 ;zaloha Flag registra v Timer
interrupte ;ENG;backup Flag register in Timer interrupt
.def backupSREG =R5 ;zaloha Flag registra v INT0
preruseni ;ENG;backup Flag register in INT0 interrupt
.def ACC =R6 ;accumulator ;ENG;accumulator
.def lastBitstufNumber =R7 ;pozicia bitstuffingu ;ENG;position
in bitstuffing
.def OutBitStuffNumber =R8 ;kolko bitov sa ma este odvysielat z
posledneho bytu - bitstuffing ;ENG;how many bits to send
last byte - bitstuffing
.def BitStuffInOut =R9 ;ci sa ma vkladat alebo mazat
bitstuffing ;ENG;if insertion or deleting of bitstuffing
.def TotalBytesToSend =R10 ;kolko sa ma poslat bytov ;ENG;
how many bytes to send
.def TransmitPart =R11 ;poradove cislo vysielacej
casti ;ENG;order number of transmitting part
.def InputBufferLength =R12 ;dlzka pripravena vo vstupnom USB
bufferi ;ENG;length prepared in input USB buffer
.def OutputBufferLength =R13 ;dlzka odpovede pripravena v USB
bufferi ;ENG;length answers prepared in USB buffer
.def MyUpdatedAddress =R14 ;moja USB adresa na update ;ENG;
my USB address for update
.def MyAddress =R15 ;moja USB adresa ;ENG;my USB
address

.def ActionFlag =R16 ;co sa ma urobit v hlavnej slucke

programu ;ENG;what to do in main program loop
.def temp3 =R17 ;temporary register ;ENG;temporary
register
.def temp2 =R18 ;temporary register ;ENG;temporary
register
.def temp1 =R19 ;temporary register ;ENG;temporary
register
.def temp0 =R20 ;temporary register ;ENG;temporary
register
.def bitcount =R21 ;counter of bits in byte ;ENG;
counter of bits in byte
.def ByteCount =R22 ;pocitadlo maximalneho poctu prijatych
bajtov ;ENG;counter of maximum number of received bytes
.def inputbuf =R23 ;prijimaci register ;ENG;receiver
register
.def shiftbuf =R24 ;posuvny prijimaci register ;ENG;
shift receiving register
.def State =R25 ;byte stavu stavoveho stroja ;ENG;
state byte of status of state machine
.def RS232BufptrX =R26 ;XL register - pointer do buffera
prijatych IR kodov ;ENG;XL register - pointer to buffer of received
IR codes
.def RS232BufptrXH =R27
.def USBBufptrY =R28 ;YL register - pointer do USB buffera
input/output ;ENG;YL register - pointer to USB buffer input/output
.def ROMBufptrZ =R30 ;ZL register - pointer do buffera ROM
dat ;ENG;ZL register - pointer to buffer of ROM data

;poziadavky na deskriptory ;ENG;requirements on descriptors

.equ GET_STATUS =0
.equ CLEAR_FEATURE =1
.equ SET_FEATURE =3
.equ SET_ADDRESS =5
.equ GET_DESCRIPTOR =6
.equ SET_DESCRIPTOR =7
.equ GET_CONFIGURATION =8
.equ SET_CONFIGURATION =9
.equ GET_INTERFACE =10
.equ SET_INTERFACE =11
.equ SYNCH_FRAME =12

;typy deskriptorov ;ENG;descriptor types

.equ DEVICE =1
.equ CONFIGURATION =2
.equ STRING =3
.equ INTERFACE =4
.equ ENDPOINT =5

;databits ;ENG;databits
.equ DataBits5 =0
.equ DataBits6 =1
.equ DataBits7 =2
.equ DataBits8 =3

;parity ;ENG;parity
.equ ParityNone =0
.equ ParityOdd =1
.equ ParityEven =2
.equ ParityMark =3
.equ ParitySpace =4

;stopbits ;ENG;stopbits
.equ StopBit1 =0
.equ StopBit2 =1

;user function start number

.equ USER_FNC_NUMBER =100

;------------------------------------------------------------------------------------------
;********************************************************************
;* Interrupt table ;ENG;* Interrupt table
;********************************************************************
.cseg
;------------------------------------------------------------------------------------------
.org 0 ;po resete ;ENG;after reset
rjmp reset
;------------------------------------------------------------------------------------------
.org INT0addr ;externe prerusenie INT0 ;ENG;
external interrupt INT0
rjmp INT0handler
;------------------------------------------------------------------------------------------
.org URXCaddr ;prijem zo seriovej linky ;ENG;
receiving from serial line
push temp0
cbi UCR,RXCIE ;zakazat interrupt od prijimania
UART ;ENG;disable interrupt from UART receiving
sei ;povol interrupty na obsluhu
USB ;ENG;enable interrupts to service USB
in temp0,UDR ;nacitaj do temp0 prijate data z UART-
u ;ENG;put to temp0 received data from UART
in backupSREGTimer,SREG ;zaloha SREG ;ENG;backup SREG
push temp2
push temp3
lds temp2,RS232LengthPosPtr
lds temp3,RS232LengthPosPtr+1 ;zisti dlzku buffera RS232
kodu ;ENG;determine length of RS232 code buffer
cpi temp3,HIGH(RS232BufferEnd-RS232FIFOBegin-1) ;ci by mal pretiect
buffer ;ENG;if the buffer would overflow
brlo FIFOBufferNoOverflow ;ak nepretecie, tak zapis do
FIFO ;ENG;if not overflow then write to FIFO
brne NoIncRS232BufferFull ;ak by mal pretiect, tak
zabran prepisaniu ;ENG;if buffer would overflow, then prevent of overwriting
;inak (pri rovnosti) este
porovnaj Lo byty ;ENG;otherwise (if equall) still compare Lo bytes
cpi temp2,LOW(RS232BufferEnd-RS232FIFOBegin-1) ;ak by mal pretiect
buffer (Lo byte) ;ENG;if buffer would overflow (Lo byte)
brcc NoIncRS232BufferFull ;tak zabran prepisaniu ;ENG;
then prevent of overwriting
FIFOBufferNoOverflow:
push RS232BufptrX
push RS232BufptrXH
lds RS232BufptrX,RS232WritePosPtr ;nastavenie sa na zaciatok
buffera zapisu RS232 kodu ;ENG;set position to begin of buffer
write RS232 code
lds RS232BufptrXH,RS232WritePosPtr+1 ;nastavenie sa na zaciatok
buffera zapisu RS232 kodu ;ENG;set position to begin of
buffer write RS232 code

st X+,temp0 ;a uloz ho do buffera ;ENG;

and save it to buffer
cpi RS232BufptrXH,HIGH(RS232BufferEnd+1) ;ak sa nedosiahol maximum
RS232 buffera ;ENG;if not reached maximum of RS232 buffer
brlo NoUARTBufferOverflow ;tak pokracuj ;ENG;then
continue
brne UARTBufferOverflow ;skontroluj aj LSB ;ENG;
check althen LSB
cpi RS232BufptrX,LOW(RS232BufferEnd+1) ;ak sa nedosiahol maximum
RS232 buffera ;ENG;if not reached maximum of RS232 buffer
brlo NoUARTBufferOverflow ;tak pokracuj ;ENG;then
continue
UARTBufferOverflow:
ldi RS232BufptrX,LOW(RS232FIFOBegin) ;inak sa nastav na zaciatok
buffera ;ENG;otherwise set position to buffer begin
ldi RS232BufptrXH,HIGH(RS232FIFOBegin) ;inak sa nastav na zaciatok
buffera ;ENG;otherwise set position to buffer begin
NoUARTBufferOverflow:
sts RS232WritePosPtr,RS232BufptrX ;ulozenie noveho offsetu
buffera zapisu RS232 kodu ;ENG;save new offset of buffer write
RS232 code
sts RS232WritePosPtr+1,RS232BufptrXH ;ulozenie noveho offsetu
buffera zapisu RS232 kodu ;ENG;save new offset of buffer write
RS232 code
ldi temp0,1 ;zvys dlzku RS232
buffera ;ENG;increment length of RS232 buffer
add temp2,temp0
ldi temp0,0
adc temp3,temp0
sts RS232LengthPosPtr,temp2 ;uloz dlzku buffera RS232
kodu ;ENG;save length of buffer RS232 code
sts RS232LengthPosPtr+1,temp3 ;uloz dlzku buffera RS232
kodu ;ENG;save length of buffer RS232 code
pop RS232BufptrXH
pop RS232BufptrX
NoIncRS232BufferFull:
pop temp3
pop temp2
pop temp0
out SREG,backupSREGTimer ;obnova SREG ;ENG;restore SREG
cli ;zakazat interrupt kvoli
zacykleniu ;ENG;disable interrupt because to prevent reentrant interrupt call
sbi UCR,RXCIE ;povolit interrupt od prijimania
UART ;ENG;enable interrupt from receiving of UART
reti
;------------------------------------------------------------------------------------------
;********************************************************************
;* Init program ;ENG;* Init program
;********************************************************************
;------------------------------------------------------------------------------------------
reset: ;inicializacia procesora a premennych na spravne
hodnoty ;ENG;initialization of processor and variables to right
values
ldi temp0,StackBegin ;inicializacia stacku ;ENG;initialization of
stack
out SPL,temp0

clr XH ;RS232 pointer ;ENG;RS232 pointer

clr YH ;USB pointer ;ENG;USB pointer
clr ZH ;ROM pointer ;ENG;ROM pointer
ldi temp0,LOW(RS232FIFOBegin) ;nastav na zaciatok buffera Low ;ENG;
set Low to begin of buffer
sts RS232ReadPosPtr,temp0 ;znuluj ukazovatel citania ;ENG;
zero index of reading
sts RS232WritePosPtr,temp0 ;znuluj ukazovatel zapisu ;ENG;
zero index of writing
ldi temp0,HIGH(RS232FIFOBegin) ;nastav na zaciatok buffera
High ;ENG;set High to begin of buffer
sts RS232ReadPosPtr+1,temp0 ;znuluj ukazovatel citania ;ENG;
zero index of reading
sts RS232WritePosPtr+1,temp0 ;znuluj ukazovatel zapisu ;ENG;
zero index of writing
sts RS232LengthPosPtr,YH ;znuluj ukazovatel dlzky ;ENG;
zero index of length
sts RS232LengthPosPtr+1,YH ;znuluj ukazovatel dlzky ;ENG;
zero index of length
clr RS232BufferFull

clr MyUpdatedAddress ;nova adresa USB - nedekodovana ;ENG;

new address USB - non-decoded
rcall InitACKBufffer ;inicializacia ACK buffera ;ENG;
initialization of ACK buffer
rcall InitNAKBufffer ;inicializacia NAK buffera ;ENG;
initialization of NAK buffer

rcall USBReset ;inicializacia USB adresy ;ENG;

initialization of USB addresses

ldi temp0,0b00111100 ;nahodit pull-up na PORTB ;ENG;set pull-

up on PORTB
out PORTB,temp0
ldi temp0,0b11111111 ;nahodit pull-up na PORTC ;ENG;set pull-
up on PORTC
out PORTC,temp0
ldi temp0,0b11111011 ;nahodit pull-up na PORTD ;ENG;set pull-
up on PORTD
out PORTD,temp0

clr temp0 ;
out UBRRH,temp0 ;nastavit vysielaciu rychlost UART-u
High ;ENG;set UART speed High
out EEARH,temp0 ;znulovat EEPROM ukazovatel ;ENG;zero
EEPROM index

ldi temp0,1<<U2X ;nastavit mod X2 na UART-e ;ENG;set mode

X2 on UART
out USR,temp0
ldi temp0,InitBaudRate ;nastavit vysielaciu rychlost UART-u ;ENG;
set UART speed
out UBRR,temp0
sbi UCR,TXEN ;povolit vysielanie UART-u ;ENG;enable
transmiting of UART
sbi UCR,RXEN ;povolit prijimanie UART-u ;ENG;enable
receiving of UART
sbi UCR,RXCIE ;povolit interrupt od prijimania UART ;ENG;
enable interrupt from receiving of UART

ldi temp0,0x0F ;INT0 - reagovanie na nabeznu hranu ;ENG;

INT0 - respond to leading edge
out MCUCR,temp0 ;
ldi temp0,1<<INT0 ;povolit externy interrupt INT0 ;ENG;enable
external interrupt INT0
out GIMSK,temp0
;------------------------------------------------------------------------------------------

;********************************************************************
;* Main program ;ENG;* Main program
;********************************************************************
sei ;povolit interrupty globalne ;ENG;
enable interrupts globally
Main:
sbis inputport,DATAminus ;cakanie az sa zmeni D- na 0 ;ENG;waiting
till change D- to 0
rjmp CheckUSBReset ;a skontroluj, ci to nie je USB reset ;ENG;
and check, if isn't USB reset

cpi ActionFlag,DoReceiveSetupData
breq ProcReceiveSetupData
cpi ActionFlag,DoPrepareOutContinuousBuffer
breq ProcPrepareOutContinuousBuffer
rjmp Main

CheckUSBReset:
ldi temp0,255 ;pocitadlo trvania reset-u (podla normy je to
cca 10ms - tu je to cca 100us) ;ENG;counter duration of reset
(according to specification is that cca 10ms - here is cca 100us)
WaitForUSBReset:
sbic inputport,DATAminus ;cakanie az sa zmeni D+ na 0 ;ENG;waiting
till change D+ to 0
rjmp Main
dec temp0
brne WaitForUSBReset
rcall USBReset
rjmp Main

ProcPrepareOutContinuousBuffer:
rcall PrepareOutContinuousBuffer ;priprav pokracovanie odpovede do
buffera ;ENG;prepare next sequence of answer to buffer
ldi ActionFlag,DoReadySendAnswer
rjmp Main
ProcReceiveSetupData:
ldi USBBufptrY,InputBufferBegin ;pointer na zaciatok prijimacieho
buffera ;ENG;pointer to begin of receiving buffer
mov ByteCount,InputBufferLength ;dlzka vstupneho buffera ;ENG;
length of input buffer
rcall DecodeNRZI ;prevod kodovania NRZI na bity ;ENG;transfer
NRZI coding to bits
rcall MirrorInBufferBytes ;prehodit poradie bitov v bajtoch ;ENG;
invert bits order in bytes
rcall BitStuff ;odstranenie bit stuffing ;ENG;removal
of bitstuffing
;rcall CheckCRCIn ;kontrola CRC ;ENG;rcall
CheckCRCIn ;check CRC
rcall PrepareUSBOutAnswer ;pripravenie odpovede do vysielacieho
buffera ;ENG;prepare answers to transmitting buffer
ldi ActionFlag,DoReadySendAnswer
rjmp Main
;********************************************************************
;* Main program END ;ENG;* Main program END
;********************************************************************
;------------------------------------------------------------------------------------------
;********************************************************************
;* Interrupt0 interrupt handler ;ENG;* Interrupt0 interrupt handler
;********************************************************************
INT0Handler: ;prerusenie INT0 ;ENG;interrupt
INT0
in backupSREG,SREG
push temp0
push temp1

ldi temp0,3 ;pocitadlo trvania log0 ;ENG;counter of

duration log0
ldi temp1,2 ;pocitadlo trvania log1 ;ENG;counter of
duration log1
;cakanie na zaciatok paketu ;ENG;waiting for begin packet
CheckchangeMinus:
sbis inputport,DATAminus ;cakanie az sa zmeni D- na 1 ;ENG;waiting
till change D- to 1
rjmp CheckchangeMinus
CheckchangePlus:
sbis inputport,DATAplus ;cakanie az sa zmeni D+ na 1 ;ENG;waiting
till change D+ to 1
rjmp CheckchangePlus
DetectSOPEnd:
sbis inputport,DATAplus
rjmp Increment0 ;D+ =0 ;ENG;D+ =0
Increment1:
ldi temp0,3 ;pocitadlo trvania log0 ;ENG;counter of
duration log0
dec temp1 ;kolko cyklov trvala log1 ;ENG;how many
cycles takes log1
nop
breq USBBeginPacket ;ak je to koniec SOP - prijimaj paket ;ENG;
if this is end of SOP - receive packet
rjmp DetectSOPEnd
Increment0:
ldi temp1,2 ;pocitadlo trvania log1 ;ENG;counter of
duration log1
dec temp0 ;kolko cyklov trvala log0 ;ENG;how many
cycles take log0
nop
brne DetectSOPEnd ;ak nenastal SOF - pokracuj ;ENG;if there
isn't SOF - continue
rjmp EndInt0HandlerPOP2
EndInt0Handler:
pop ACC
pop RS232BufptrX
pop temp3
pop temp2
EndInt0HandlerPOP:
pop USBBufptrY
pop ByteCount
mov bitcount,backupbitcount ;obnova bitcount registra ;ENG;restore
bitcount register
EndInt0HandlerPOP2:
pop temp1
pop temp0
out SREG,backupSREG
ldi shiftbuf,1<<INTF0 ;znulovat flag interruptu INTF0 ;ENG;zero
interruptu flag INTF0
out GIFR,shiftbuf
reti ;inak skonci (bol iba SOF - kazdu
milisekundu) ;ENG;otherwise finish (was only SOF - every millisecond)

USBBeginPacket:
mov backupbitcount,bitcount ;zaloha bitcount registra ;ENG;backup
bitcount register
in shiftbuf,inputport ;ak ano nacitaj ho ako nulty bit priamo do
shift registra ;ENG;if yes load it as zero bit directly
to shift register
USBloopBegin:
push ByteCount ;dalsia zaloha registrov (setrenie
casu) ;ENG;additional backup of registers (save of time)
push USBBufptrY
ldi bitcount,6 ;inicializacia pocitadla bitov v bajte ;ENG;
initialization of bits counter in byte
ldi ByteCount,MAXUSBBYTES ;inicializacia max poctu prijatych bajtov v
pakete ;ENG;initialization of max number of received
bytes in packet
ldi USBBufptrY,InputShiftBufferBegin ;nastav vstupny buffera ;ENG;
set the input buffer
USBloop1_6:
in inputbuf,inputport
cbr inputbuf,USBpinmask ;odmaskovat spodne 2 bity ;ENG;unmask
low 2 bits
breq USBloopEnd ;ak su nulove - koniec USB packetu ;ENG;
if they are zeros - end of USB packet
ror inputbuf ;presun Data+ do shift registra ;ENG;transfer
Data+ to shift register
rol shiftbuf
dec bitcount ;zmensi pocitadlo bitov ;ENG;decrement bits
counter
brne USBloop1_6 ;ak nie je nulove - opakuj naplnanie shift
registra ;ENG;if it isn't zero - repeat filling of shift register
nop ;inak bude nutne skopirovat shift register bo
buffera ;ENG;otherwise is necessary copy shift register to buffer
USBloop7:
in inputbuf,inputport
cbr inputbuf,USBpinmask ;odmaskovat spodne 2 bity ;ENG;unmask
low 2 bits
breq USBloopEnd ;ak su nulove - koniec USB packetu ;ENG;
if they are zeros - end of USB packet
ror inputbuf ;presun Data+ do shift registra ;ENG;transfer
Data+ to shift register
rol shiftbuf
ldi bitcount,7 ;inicializacia pocitadla bitov v bajte ;ENG;
initialization of bits counter in byte
st Y+,shiftbuf ;skopiruj shift register bo buffera a zvys
pointer do buffera ;ENG;copy shift register into buffer and increment
pointer to buffer
USBloop0: ;a zacni prijimat dalsi bajt ;ENG;and start
receiving next byte
in shiftbuf,inputport ;nulty bit priamo do shift registra ;ENG;
zero bit directly to shift register
cbr shiftbuf,USBpinmask ;odmaskovat spodne 2 bity ;ENG;unmask
low 2 bits
breq USBloopEnd ;ak su nulove - koniec USB packetu ;ENG;
if they are zeros - end of USB packet
dec bitcount ;zmensi pocitadlo bitov ;ENG;decrement bits
counter
nop ;
dec ByteCount ;ak sa nedosiahol maximum buffera ;ENG;
if not reached maximum buffer
brne USBloop1_6 ;tak prijimaj dalej ;ENG;then receive next

rjmp EndInt0HandlerPOP ;inak opakuj od zaciatku ;ENG;otherwise

repeat back from begin

USBloopEnd:
cpi USBBufptrY,InputShiftBufferBegin+3 ;ak sa neprijali aspon 3
byte ;ENG;if at least 3 byte not received
brcs EndInt0HandlerPOP ;tak skonci ;ENG;then finish
lds temp0,InputShiftBufferBegin+0 ;identifikator paketu do temp0 ;ENG;
identifier of packet to temp0
lds temp1,InputShiftBufferBegin+1 ;adresa do temp1 ;ENG;address
to temp1
brne TestDataPacket ;ak je dlzka ina ako 3 - tak to moze byt iba
DataPaket ;ENG;if is length different from 3 - then this
can be only DataPaket
TestIOPacket:
cp temp1,MyAddress ;ak to nie je urcene (adresa) pre mna ;ENG;
if this isn't assigned (address) for me
brne TestDataPacket ;tak to moze byt este Data Packet ;ENG;
then this can be still DataPacket
TestSetupPacket:;test na SETUP paket ;ENG;test to SETUP packet
cpi temp0,nNRZISETUPPID
brne TestOutPacket ;ak nie je Setup PID - dekoduj iny
paket ;ENG;if this isn't Setup PID - decode other packet
ldi State,SetupState
rjmp EndInt0HandlerPOP ;ak je Setup PID - prijimaj nasledny Data
paket ;ENG;if this is Setup PID - receive consecutive Data
packet
TestOutPacket: ;test na OUT paket ;ENG;test for OUT packet
cpi temp0,nNRZIOUTPID
brne TestInPacket ;ak nie je Out PID - dekoduj iny paket ;ENG;
if this isn't Out PID - decode other packet
ldi State,OutState
rjmp EndInt0HandlerPOP ;ak je Out PID - prijimaj nasledny Data
paket ;ENG;if this is Out PID - receive consecutive Data
packet
TestInPacket: ;test na IN paket ;ENG;test on IN packet
cpi temp0,nNRZIINPID
brne TestDataPacket ;ak nie je In PID - dekoduj iny paket ;ENG;
if this isn't In PID - decode other packet
rjmp AnswerToInRequest
TestDataPacket: ;test na DATA0 a DATA1 paket ;ENG;test for DATA0 and DATA1 packet
cpi temp0,nNRZIDATA0PID
breq Data0Packet ;ak nie je Data0 PID - dekoduj iny
paket ;ENG;if this isn't Data0 PID - decode other packet
cpi temp0,nNRZIDATA1PID
brne NoMyPacked ;ak nie je Data1 PID - dekoduj iny
paket ;ENG;if this isn't Data1 PID - decode other packet
Data0Packet:
cpi State,SetupState ;ak bol stav Setup ;ENG;if was state Setup
breq ReceiveSetupData ;prijmi ho ;ENG;receive it
cpi State,OutState ;ak bol stav Out ;ENG;if was state Out
breq ReceiveOutData ;prijmi ho ;ENG;receive it
NoMyPacked:
ldi State,BaseState ;znuluj stav ;ENG;zero state
rjmp EndInt0HandlerPOP ;a prijimaj nasledny Data paket ;ENG;and
receive consecutive Data packet

AnswerToInRequest:
push temp2 ;zazalohuj dalsie registre a pokracuj ;ENG;
backup next registers and continue
push temp3
push RS232BufptrX
push ACC
cpi ActionFlag,DoReadySendAnswer ;ak nie je pripravena odpoved ;ENG;
if isn't prepared answer
brne NoReadySend ;tak posli NAK ;ENG;then send NAK
rcall SendPreparedUSBAnswer ;poslanie odpovede naspat ;ENG;
transmitting answer back
and MyUpdatedAddress,MyUpdatedAddress ;ak je MyUpdatedAddress
nenulova ;ENG;if is MyUpdatedAddress nonzero
brne SetMyNewUSBAddress ;tak treba zmenit USB adresu ;ENG;then is
necessary to change USB address
ldi State,InState
ldi ActionFlag,DoPrepareOutContinuousBuffer
rjmp EndInt0Handler ;a opakuj - cakaj na dalsiu odozvu z
USB ;ENG;and repeat - wait for next response from USB
ReceiveSetupData:
push temp2 ;zazalohuj dalsie registre a pokracuj ;ENG;
backup next registers and continue
push temp3
push RS232BufptrX
push ACC
rcall SendACK ;akceptovanie Setup Data paketu ;ENG;accept
Setup Data packet
rcall FinishReceiving ;ukonci prijem ;ENG;finish receiving
ldi ActionFlag,DoReceiveSetupData
rjmp EndInt0Handler
ReceiveOutData:
push temp2 ;zazalohuj dalsie registre a pokracuj ;ENG;
backup next registers and continue
push temp3
push RS232BufptrX
push ACC
cpi ActionFlag,DoReceiveSetupData ;ak sa prave spracovava prikaz
Setup ;ENG;if is currently in process command Setup
breq NoReadySend ;tak posli NAK ;ENG;then send NAK
rcall SendACK ;akceptovanie Out paketu ;ENG;accept
Out packet
clr ActionFlag
rjmp EndInt0Handler
NoReadySend:
rcall SendNAK ;este nie som pripraveny s odpovedou ;ENG;
still I am not ready to answer
rjmp EndInt0Handler ;a opakuj - cakaj na dalsiu odozvu z
USB ;ENG;and repeat - wait for next response from USB
;------------------------------------------------------------------------------------------
SetMyNewUSBAddress: ;nastavi novu USB adresu v NRZI kodovani ;ENG;set new
USB address in NRZI coded
clr MyAddress ;vychodzi stav odpovede - mojej nNRZI USB
adresy ;ENG;original answer state - of my nNRZI USB address
ldi temp2,0b00000001 ;maska na xorovanie ;ENG;mask for xoring
ldi temp3,8 ;pocitadlo bitov ;ENG;bits counter
SetMyNewUSBAddressLoop:
mov temp0,MyAddress ;zapamatat si koncovu odpoved ;ENG;remember
final answer
ror MyUpdatedAddress ;do carry vysielany bit LSB (v smere naskor
LSB a potom MSB) ;ENG;to carry transmitting bit LSB (in
direction firstly LSB then MSB)
brcs NoXORBit ;ak je jedna - nemen stav ;ENG;if one -
don't change state
eor temp0,temp2 ;inak sa bude stav menit podla posledneho bitu
odpovede ;ENG;otherwise state will be changed according
to last bit of answer
NoXORBit:
ror temp0 ;posledny bit zmenenej odpovede do
carry ;ENG;last bit of changed answer to carry
rol MyAddress ;a z carry do koncovej odpovede na miesto LSB
(a sucasne prehodenie LSB a MSB poradia) ;ENG;and from carry
to final answer to the LSB place (and reverse LSB and MSB order)
dec temp3 ;zmensi pocitadlo bitov ;ENG;decrement bits
counter
brne SetMyNewUSBAddressLoop ;ak pocitadlo bitov nie je nulove opakuj
vysielanie s dalsim bitom ;ENG;if bits counter isn't
zero repeat transmitting with next bit
clr MyUpdatedAddress ;znulovanie adresy ako priznak jej buduceho
nemenenia ;ENG;zero addresses as flag of its next unchanging
rjmp EndInt0Handler
;------------------------------------------------------------------------------------------
FinishReceiving: ;korekcne akcie na ukoncenie prijmu ;ENG;corrective
actions for receive termination
cpi bitcount,7 ;prenes do buffera aj posledny necely
byte ;ENG;transfer to buffer also last not completed byte
breq NoRemainingBits ;ak boli vsetky byty prenesene, tak neprenasaj
nic ;ENG;if were all bytes transfered, then nothing
transfer
inc bitcount
ShiftRemainingBits:
rol shiftbuf ;posun ostavajuce necele bity na spravnu
poziciu ;ENG;shift remaining not completed bits on right position
dec bitcount
brne ShiftRemainingBits
st Y+,shiftbuf ;a skopiruj shift register bo buffera - necely
byte ;ENG;and copy shift register bo buffer - not completed
byte
NoRemainingBits:
mov ByteCount,USBBufptrY
subi ByteCount,InputShiftBufferBegin-1 ;v ByteCount je pocet
prijatych byte (vratane necelych byte) ;ENG;in ByteCount is
number of received bytes (including not completed bytes)

mov InputBufferLength,ByteCount ;a uchovat pre pouzitie v

hlavnom programe ;ENG;and save for use in main program
ldi USBBufptrY,InputShiftBufferBegin ;pointer na zaciatok
prijimacieho shift buffera ;ENG;pointer to begin of receiving
shift buffer
ldi RS232BufptrX,InputBufferBegin+1 ;data buffer (vynechat
SOP) ;ENG;data buffer (leave out SOP)
push XH ;uschova RS232BufptrX Hi
ukazovatela ;ENG;save RS232BufptrX Hi index
clr XH
MoveDataBuffer:
ld temp0,Y+
st X+,temp0
dec ByteCount
brne MoveDataBuffer

pop XH ;obnova RS232BufptrX Hi

ukazovatela ;ENG;restore RS232BufptrX Hi index
ldi ByteCount,nNRZISOPbyte
sts InputBufferBegin,ByteCount ;ako keby sa prijal SOP -
nekopiruje sa zo shift buffera ;ENG;like received SOP - it is
not copied from shift buffer
ret
;------------------------------------------------------------------------------------------

;********************************************************************
;* Other procedures ;ENG;* Other procedures
;********************************************************************
;------------------------------------------------------------------------------------------
USBReset: ;inicializacia USB stavoveho stroja ;ENG;initialization of USB
state engine
ldi temp0,nNRZIADDR0 ;inicializacia USB adresy ;ENG;
initialization of USB address
mov MyAddress,temp0
clr State ;inicializacia stavoveho stroja ;ENG;
initialization of state engine
clr BitStuffInOut
clr OutBitStuffNumber
clr ActionFlag
clr RAMread ;bude sa vycitavat z ROM-ky ;ENG;will be
reading from ROM
sts ConfigByte,RAMread ;nenakonfiguravany stav ;ENG;unconfigured state
ret
;------------------------------------------------------------------------------------------
SendPreparedUSBAnswer: ;poslanie kodovanim NRZI OUT buffera s dlzkou
OutputBufferLength do USB ;ENG;transmitting by NRZI coding
OUT buffer with length OutputBufferLength to USB
mov ByteCount,OutputBufferLength ;dlzka odpovede ;ENG;length of
answer
SendUSBAnswer: ;poslanie kodovanim NRZI OUT buffera do USB ;ENG;transmitting by
NRZI coding OUT buffer to USB
ldi USBBufptrY,OutputBufferBegin ;pointer na zaciatok
vysielacieho buffera ;ENG;pointer to begin of transmitting buffer
SendUSBBuffer: ;poslanie kodovanim NRZI dany buffer do USB ;ENG;transmitting by
NRZI coding given buffer to USB
ldi temp1,0 ;zvysovanie pointera (pomocna premenna) ;ENG;
incrementing pointer (temporary variable)
mov temp3,ByteCount ;pocitadlo bytov: temp3 = ByteCount ;ENG;
byte counter: temp3 = ByteCount
ldi temp2,0b00000011 ;maska na xorovanie ;ENG;mask for xoring
ld inputbuf,Y+ ;nacitanie prveho bytu do inputbuf a zvys

http://avr-asm.tripod.com/usb232.html (1 of 4)1/20/2009 8:56:38 PM

16 BIT MATH (AVR 202)

pointer do buffera ;ENG;load first byte to inputbuf and increment

pointer to buffer
;USB ako vystup: ;ENG;USB as output:
cbi outputport,DATAplus ;zhodenie DATAplus : kludovy stav portu
USB ;ENG;down DATAPLUS : idle state of USB port
sbi outputport,DATAminus ;nahodenie DATAminus : kludovy stav portu
USB ;ENG;set DATAMINUS : idle state of USB port
sbi USBdirection,DATAplus ;DATAplus ako vystupny ;ENG;DATAPLUS as output
sbi USBdirection,DATAminus ;DATAminus ako vystupny ;ENG;DATAMINUS as
output

in temp0,outputport ;kludovy stav portu USB do temp0 ;ENG;

idle state of USB port to temp0
SendUSBAnswerLoop:
ldi bitcount,7 ;pocitadlo bitov ;ENG;bits counter
SendUSBAnswerByteLoop:
nop ;oneskorenie kvoli casovaniu ;ENG;delay
because timing
ror inputbuf ;do carry vysielany bit (v smere naskor LSB a
potom MSB) ;ENG;to carry transmiting bit (in direction first
LSB then MSB)
brcs NoXORSend ;ak je jedna - nemen stav na USB ;ENG;
if that it is one - don't change USB state
eor temp0,temp2 ;inak sa bude stav menit ;ENG;otherwise
state will be changed
NoXORSend:
out outputport,temp0 ;vysli von na USB ;ENG;send out to USB
dec bitcount ;zmensi pocitadlo bitov - podla carry
flagu ;ENG;decrement bits counter - according to carry flag
brne SendUSBAnswerByteLoop ;ak pocitadlo bitov nie je nulove - opakuj
vysielanie s dalsim bitom ;ENG;if bits counter isn't
zero - repeat transmiting with next bit
sbrs inputbuf,0 ;ak je vysielany bit jedna - nemen stav na
USB ;ENG;if is transmiting bit one - don't change USB state
eor temp0,temp2 ;inak sa bude stav menit ;ENG;otherwise
state will be changed
NoXORSendLSB:
dec temp3 ;zniz pocitadlo bytov ;ENG;decrement bytes
counter
ld inputbuf,Y+ ;nacitanie dalsieho bytu a zvys pointer do
buffera ;ENG;load next byte and increment pointer to buffer
out outputport,temp0 ;vysli von na USB ;ENG;transmit to USB
brne SendUSBAnswerLoop ;opakuj pre cely buffer (pokial
temp3=0) ;ENG;repeat for all buffer (till temp3=0)

mov bitcount,OutBitStuffNumber ;pocitadlo bitov pre bitstuff ;ENG;

bits counter for bitstuff
cpi bitcount,0 ;ak nie je potrebny bitstuff ;ENG;if not be
needed bitstuff
breq ZeroBitStuf
SendUSBAnswerBitstuffLoop:
ror inputbuf ;do carry vysielany bit (v smere naskor LSB a
potom MSB) ;ENG;to carry transmiting bit (in direction first
LSB then MSB)
brcs NoXORBitstuffSend ;ak je jedna - nemen stav na USB ;ENG;
if is one - don't change state on USB
eor temp0,temp2 ;inak sa bude stav menit ;ENG;otherwise
state will be changed
NoXORBitstuffSend:
out outputport,temp0 ;vysli von na USB ;ENG;transmit to USB
nop ;oneskorenie kvoli casovaniu ;ENG;delay
because of timing
dec bitcount ;zmensi pocitadlo bitov - podla carry
flagu ;ENG;decrement bits counter - according to carry flag
brne SendUSBAnswerBitstuffLoop ;ak pocitadlo bitov nie je nulove -
opakuj vysielanie s dalsim bitom ;ENG;if bits counter
isn't zero - repeat transmiting with next bit
ld inputbuf,Y ;oneskorenie 2 cykly ;ENG;delay 2 cycle
ZeroBitStuf:
nop ;oneskorenie 1 cyklus ;ENG;delay 1 cycle
cbr temp0,3
out outputport,temp0 ;vysli EOP na USB ;ENG;transmit EOP on
USB

ldi bitcount,5 ;pocitadlo oneskorenia: EOP ma trvat 2 bity

(16 cyklov pri 12MHz) ;ENG;delay counter: EOP shouls exists
2 bits (16 cycle at 12MHz)
SendUSBWaitEOP:
dec bitcount
brne SendUSBWaitEOP

sbi outputport,DATAminus ;nahodenie DATAminus : kludovy stav na port

USB ;ENG;set DATAMINUS : idle state on USB port
sbi outputport,DATAminus ;oneskorenie 2 cykly: Idle ma trvat 1 bit (8
cyklov pri 12MHz) ;ENG;delay 2 cycle: Idle should
exists 1 bit (8 cycle at 12MHz)
cbi USBdirection,DATAplus ;DATAplus ako vstupny ;ENG;DATAPLUS as input
cbi USBdirection,DATAminus ;DATAminus ako vstupny ;ENG;DATAMINUS as input
cbi outputport,DATAminus ;zhodenie DATAminus : treti stav na port
USB ;ENG;reset DATAMINUS : the third state on USB port
ret
;------------------------------------------------------------------------------------------
ToggleDATAPID:
lds temp0,OutputBufferBegin+1 ;nahraj posledne PID ;ENG;load last
PID
cpi temp0,DATA1PID ;ak bolo posledne DATA1PID byte ;ENG;
if last was DATA1PID byte
ldi temp0,DATA0PID
breq SendData0PID ;tak posli nulovu odpoved s
DATA0PID ;ENG;then send zero answer with DATA0PID
ldi temp0,DATA1PID ;inak posli nulovu odpoved s
DATA1PID ;ENG;otherwise send zero answer with DATA1PID
SendData0PID:
sts OutputBufferBegin+1,temp0 ;DATA0PID byte ;ENG;DATA0PID byte
ret
;------------------------------------------------------------------------------------------
ComposeZeroDATA1PIDAnswer:
ldi temp0,DATA0PID ;DATA0 PID - v skutocnosti sa
stoggluje na DATA1PID v nahrati deskriptora ;ENG;DATA0 PID - in the next
will be toggled to DATA1PID in load descriptor
sts OutputBufferBegin+1,temp0 ;nahraj do vyst buffera ;ENG;load to
output buffer
ComposeZeroAnswer:
ldi temp0,SOPbyte
sts OutputBufferBegin+0,temp0 ;SOP byte ;ENG;SOP byte
rcall ToggleDATAPID ;zmen DATAPID ;ENG;change DATAPID
ldi temp0,0x00
sts OutputBufferBegin+2,temp0 ;CRC byte ;ENG;CRC byte
sts OutputBufferBegin+3,temp0 ;CRC byte ;ENG;CRC byte
ldi ByteCount,2+2 ;dlzka vystupneho buffera (SOP a PID +
CRC16) ;ENG;length of output buffer (SOP and PID + CRC16)
ret
;------------------------------------------------------------------------------------------
InitACKBufffer:
ldi temp0,SOPbyte
sts ACKBufferBegin+0,temp0 ;SOP byte ;ENG;SOP byte
ldi temp0,ACKPID
sts ACKBufferBegin+1,temp0 ;ACKPID byte ;ENG;ACKPID byte
ret
;------------------------------------------------------------------------------------------
SendACK:
push USBBufptrY
push bitcount
push OutBitStuffNumber
ldi USBBufptrY,ACKBufferBegin ;pointer na zaciatok ACK
buffera ;ENG;pointer to begin of ACK buffer
ldi ByteCount,2 ;pocet vyslanych bytov (iba SOP a
ACKPID) ;ENG;number of transmit bytes (only SOP and ACKPID)
clr OutBitStuffNumber
rcall SendUSBBuffer
pop OutBitStuffNumber
pop bitcount
pop USBBufptrY
ret
;------------------------------------------------------------------------------------------
InitNAKBufffer:
ldi temp0,SOPbyte
sts NAKBufferBegin+0,temp0 ;SOP byte ;ENG;SOP byte
ldi temp0,NAKPID
sts NAKBufferBegin+1,temp0 ;NAKPID byte ;ENG;NAKPID byte
ret
;------------------------------------------------------------------------------------------
SendNAK:
push OutBitStuffNumber
ldi USBBufptrY,NAKBufferBegin ;pointer na zaciatok ACK
buffera ;ENG;pointer to begin of ACK buffer
ldi ByteCount,2 ;pocet vyslanych bytov (iba SOP a
NAKPID) ;ENG;number of transmited bytes (only SOP and NAKPID)
clr OutBitStuffNumber
rcall SendUSBBuffer
pop OutBitStuffNumber
ret
;------------------------------------------------------------------------------------------
ComposeSTALL:
ldi temp0,SOPbyte
sts OutputBufferBegin+0,temp0 ;SOP byte ;ENG;SOP byte
ldi temp0,STALLPID
sts OutputBufferBegin+1,temp0 ;STALLPID byte ;ENG;STALLPID byte
ldi ByteCount,2 ;dlzka vystupneho buffera (SOP a
PID) ;ENG;length of output buffer (SOP and PID)
ret
;------------------------------------------------------------------------------------------
DecodeNRZI: ;enkodovanie buffera z NRZI kodu do binarneho ;ENG;encoding of buffer from
NRZI code to binary
push USBBufptrY ;zalohuj pointer do buffera ;ENG;back up
pointer to buffer
push ByteCount ;zalohuj dlzku buffera ;ENG;back up length of
buffer
add ByteCount,USBBufptrY ;koniec buffera do ByteCount ;ENG;end of
buffer to ByteCount
ser temp0 ;na zabezpecenie jednotkoveho carry (v
nasledujucej rotacii) ;ENG;to ensure unit carry (in the next rotation)
NRZIloop:
ror temp0 ;naplnenie carry z predchadzajuceho
byte ;ENG;filling carry from previous byte
ld temp0,Y ;nahraj prijaty byte z buffera ;ENG;load
received byte from buffer
mov temp2,temp0 ;posunuty register o jeden bit vpravo a XOR na
funkciu NRZI dekodovania ;ENG;shifted register to one bit
to the right and XOR for function of NRZI decoding
ror temp2 ;carry do najvyssieho bitu a sucasne
posuv ;ENG;carry to most significant digit bit and shift
eor temp2,temp0 ;samotne dekodovanie NRZI ;ENG;NRZI
decoding
com temp2 ;negovanie ;ENG;negate
st Y+,temp2 ;ulozenie spat ako dekodovany byte a zvys
pointer do buffera ;ENG;save back as decoded byte and increment pointer
to buffer
cp USBBufptrY,ByteCount ;ak este neboli vsetky ;ENG;if not all bytes
brne NRZIloop ;tak opakuj ;ENG;then repeat
pop ByteCount ;obnov dlzku buffera ;ENG;restore buffer
length
pop USBBufptrY ;obnov pointer do buffera ;ENG;restore
pointer to buffer
ret ;inak skonci ;ENG;otherwise finish
;------------------------------------------------------------------------------------------
BitStuff: ;odstranenie bit-stuffingu v buffri ;ENG;removal of bitstuffing in buffer
clr temp3 ;pocitadlo vynechanych bitov ;ENG;counter
of omitted bits
clr lastBitstufNumber ;0xFF do lastBitstufNumber ;ENG;0xFF to
lastBitstufNumber
dec lastBitstufNumber
BitStuffRepeat:
push USBBufptrY ;zalohuj pointer do buffera ;ENG;back up
pointer to buffer
push ByteCount ;zalohuj dlzku buffera ;ENG;back up buffer
length
mov temp1,temp3 ;pocitadlo vsetkych bitov ;ENG;counter
of all bits
ldi temp0,8 ;spocitat vsetky bity v bufferi ;ENG;sum all
bits in buffer
SumAllBits:
add temp1,temp0
dec ByteCount
brne SumAllBits
ldi temp2,6 ;inicializuj pocitadlo jednotiek ;ENG;
initialize counter of ones
pop ByteCount ;obnov dlzku buffera ;ENG;restore buffer
length
push ByteCount ;zalohuj dlzku buffera ;ENG;back up buffer
length
add ByteCount,USBBufptrY ;koniec buffera do ByteCount ;ENG;end of
buffer to ByteCount
inc ByteCount ;a pre istotu ho zvys o 2 (kvoli
posuvaniu) ;ENG;and for safety increment it with 2 (because of shifting)
inc ByteCount
BitStuffLoop:
ld temp0,Y ;nahraj prijaty byte z buffera ;ENG;load
received byte from buffer
ldi bitcount,8 ;pocitadlo bitov v byte ;ENG;bits counter in
byte
BitStuffByteLoop:
ror temp0 ;naplnenie carry z LSB ;ENG;filling carry
from LSB
brcs IncrementBitstuff ;ak LSB=0 ;ENG;if that LSB=0
ldi temp2,7 ;inicializuj pocitadlo jednotiek +1 (ak bola
nula) ;ENG;initialize counter of ones +1 (if was zero)
IncrementBitstuff:
dec temp2 ;zniz pocitadlo jednotiek (predpoklad
jednotkoveho bitu) ;ENG;decrement counter of ones (assumption of one bit)
brne NeposunBuffer ;ak este nebolo 6 jednotiek za sebou - neposun
buffer ;ENG;if there was not 6 ones together - don't
shift buffer
cp temp1,lastBitstufNumber ;
ldi temp2,6 ;inicializuj pocitadlo jednotiek (ak by sa
nerobil bitstuffing tak sa musi zacat odznova) ;ENG;initialize
counter of ones (if no bitstuffing will be made then must be started again)
brcc NeposunBuffer ;ak sa tu uz robil bitstuffing - neposun
buffer ;ENG;if already was made bitstuffing - don't shift buffer

dec temp1 ;
mov lastBitstufNumber,temp1 ;zapamataj si poslednu poziciu
bitstuffingu ;ENG;remember last position of bitstuffing
cpi bitcount,1 ;aby sa ukazovalo na 7 bit (ktory sa ma
vymazat alebo kde sa ma vlozit nula) ;ENG;for pointing to 7-th bit
(which must be deleted or where to insert zero)
brne NoBitcountCorrect
ldi bitcount,9 ;
inc USBBufptrY ;zvys pointer do buffera ENG;increment
pointer to buffer
NoBitcountCorrect:
dec bitcount
bst BitStuffInOut,0
brts CorrectOutBuffer ;ak je Out buffer - zvys dlzku buffera ;ENG;
if this is Out buffer - increment buffer length
rcall ShiftDeleteBuffer ;posun In buffer ;ENG;shift In buffer
dec temp3 ;zniz pocitadlo vynechani ;ENG;decrement
counter of omission
rjmp CorrectBufferEnd
CorrectOutBuffer:
rcall ShiftInsertBuffer ;posun Out buffer ;ENG;shift Out buffer
inc temp3 ;zvys pocitadlo vynechani ;ENG;increment
counter of omission
CorrectBufferEnd:
pop ByteCount ;obnov dlzku buffera ;ENG;restore buffer
length
pop USBBufptrY ;obnov pointer do buffera ;ENG;restore
pointer to buffer
rjmp BitStuffRepeat ;a restartni od zaciatku ;ENG;and
restart from begin
NeposunBuffer:
dec temp1 ;ak uz boli vsetky bity ;ENG;if already were
all bits
breq EndBitStuff ;ukonci cyklus ;ENG;finish cycle
dec bitcount ;zniz pocitadlo bitov v byte ;ENG;decrement
bits counter in byte
brne BitStuffByteLoop ;ak este neboli vsetky bity v byte - chod na
dalsi bit ;ENG;if not yet been all bits in byte - go
to next bit
;inak nahraj dalsi byte ;ENG;otherwise load
next byte
inc USBBufptrY ;zvys pointer do buffera ;ENG;increment
pointer to buffer
rjmp BitStuffLoop ;a opakuj ;ENG;and repeat
EndBitStuff:
pop ByteCount ;obnov dlzku buffera ;ENG;restore buffer
length
pop USBBufptrY ;obnov pointer do buffera ;ENG;restore
pointer to buffer
bst BitStuffInOut,0
brts IncrementLength ;ak je Out buffer - zvys dlzku Out
buffera ;ENG;if this is Out buffer - increment length of Out buffer
DecrementLength: ;ak je In buffer - zniz dlzku In
buffera ;ENG;if this is In buffer - decrement length of In buffer
cpi temp3,0 ;bolo aspon jedno znizenie ;ENG;was at
least one decrement
breq NoChangeByteCount ;ak nie - nemen dlzku buffera ;ENG;if no -
don't change buffer length
dec ByteCount ;ak je In buffer - zniz dlzku buffera ;ENG;
if this is In buffer - decrement buffer length
subi temp3,256-8 ;ak nebolo viac ako 8 bitov naviac ;ENG;
if there wasn't above 8 bits over
brcc NoChangeByteCount ;tak skonci ;ENG;then finish
dec ByteCount ;inak este zniz dlzku buffera ;ENG;otherwise
next decrement buffer length
ret ;a skonci ;ENG;and finish
IncrementLength:
mov OutBitStuffNumber,temp3 ;zapamataj si pocet bitov naviac ;ENG;
remember number of bits over
subi temp3,8 ;ak nebolo viac ako 8 bitov naviac ;ENG;
if there wasn't above 8 bits over
brcs NoChangeByteCount ;tak skonci ;ENG;then finish
inc ByteCount ;inak zvys dlzku buffera ;ENG;otherwise
increment buffer length
mov OutBitStuffNumber,temp3 ;a zapamataj si pocet bitov naviac (znizene o
8) ;ENG;and remember number of bits over (decremented
by 8)
NoChangeByteCount:
ret ;skonci ;ENG;finish
;------------------------------------------------------------------------------------------
ShiftInsertBuffer: ;posuv buffer o jeden bit vpravo od konca az po poziciu: byte-
USBBufptrY a bit-bitcount ;ENG;shift buffer
by one bit to right from end till to position: byte-USBBufptrY and bit-bitcount
mov temp0,bitcount ;vypocet: bitcount= 9-bitcount ;ENG;
calculation: bitcount= 9-bitcount
ldi bitcount,9
sub bitcount,temp0 ;do bitcount poloha bitu, ktory treba
nulovat ;ENG;to bitcount bit position, which is necessary to clear

ld temp1,Y ;nahraj byte ktory este treba posunut od

pozicie bitcount ;ENG;load byte which still must be shifted from position
bitcount
rol temp1 ;a posun vlavo cez Carry (prenos z vyssieho
byte a LSB do Carry) ;ENG;and shift to the left through Carry (transmission
from higher byte and LSB to Carry)
ser temp2 ;FF do masky - temp2 ;ENG;FF to mask - temp2
HalfInsertPosuvMask:
lsl temp2 ;nula do dalsieho spodneho bitu masky ;ENG;
zero to the next low bit of mask
dec bitcount ;az pokial sa nedosiahne hranica posuvania v
byte ;ENG;till not reached boundary of shifting in byte
brne HalfInsertPosuvMask

and temp1,temp2 ;odmaskuj aby zostali iba vrchne posunute bity

v temp1 ;ENG;unmask that remains only high shifted bits
in temp1
com temp2 ;invertuj masku ;ENG;invert mask
lsr temp2 ;posun masku vpravo - na vlozenie nuloveho
bitu ;ENG;shift mask to the right - for insertion of zero bit
ld temp0,Y ;nahraj byte ktory este treba posunut od
pozicie bitcount do temp0 ;ENG;load byte which must be shifted from
position bitcount to temp0
and temp0,temp2 ;odmaskuj aby zostali iba spodne neposunute
bity v temp0 ;ENG;unmask to remains only low non-shifted bits
in temp0
or temp1,temp0 ;a zluc posunutu a neposunutu cast ;ENG;
and put together shifted and nonshifted part

ld temp0,Y ;nahraj byte ktory este treba posunut od

pozicie bitcount ;ENG;load byte which must be shifted from position
bitcount
rol temp0 ;a posun ho vlavo cez Carry (aby sa nastavilo
spravne Carry pre dalsie prenosy) ;ENG;and shift it to the left
through Carry (to set right Carry for further carry)
st Y+,temp1 ;a nahraj spat upraveny byte ;ENG;and load
back modified byte
ShiftInsertBufferLoop:
cpse USBBufptrY,ByteCount ;ak nie su vsetky cele byty ;ENG;if are
not all entire bytes
rjmp NoEndShiftInsertBuffer ;tak pokracuj ;ENG;then continue
ret ;inak skonci ;ENG;otherwise finish
NoEndShiftInsertBuffer:
ld temp1,Y ;nahraj byte ;ENG;load byte
rol temp1 ;a posun vlavo cez Carry (prenos z nizsieho
byte a LSB do Carry) ;ENG;and shift to the left through Carry (carry
from low byte and LSB to Carry)
st Y+,temp1 ;a nahraj spat ;ENG;and store back
rjmp ShiftInsertBufferLoop ;a pokracuj ;ENG;and continue
;------------------------------------------------------------------------------------------
ShiftDeleteBuffer: ;posuv buffera o jeden bit vlavo od konca az po poziciu: byte-
USBBufptrY a bit-bitcount ;ENG;shift buffer
one bit to the left from end to position: byte-USBBufptrY and bit-bitcount
mov temp0,bitcount ;vypocet: bitcount= 9-bitcount ;ENG;
calculation: bitcount= 9-bitcount
ldi bitcount,9
sub bitcount,temp0 ;do bitcount poloha bitu, ktory este treba
posunut ;ENG;to bitcount bit position, which must be shifted
mov temp0,USBBufptrY ;uschovanie pointera do buffera ;ENG;backup
pointera to buffer
inc temp0 ;pozicia celych bytov do temp0 ;ENG;position
of completed bytes to temp0
mov USBBufptrY,ByteCount ;maximalna pozicia do pointera ;ENG;maximum
position to pointer
ShiftDeleteBufferLoop:
ld temp1,-Y ;zniz buffer a nahraj byte ;ENG;decrement
buffer and load byte
ror temp1 ;a posun vpravo cez Carry (prenos z vyssieho
byte a LSB do Carry) ;ENG;and right shift through Carry (carry
from higher byte and LSB to Carry)
st Y,temp1 ;a nahraj spat ;ENG;and store back
cpse USBBufptrY,temp0 ;ak nie su vsetky cele byty ;ENG;if there
are not all entire bytes
rjmp ShiftDeleteBufferLoop ;tak pokracuj ;ENG;then continue

ld temp1,-Y ;zniz buffer a nahraj byte ktory este treba

posunut od pozicie bitcount ;ENG;decrement buffer and load byte
which must be shifted from position bitcount
ror temp1 ;a posun vpravo cez Carry (prenos z vyssieho
byte a LSB do Carry) ;ENG;and right shift through Carry (carry
from higher byte and LSB to Carry)
ser temp2 ;FF do masky - temp2 ;ENG;FF to mask - temp2
HalfDeletePosuvMask:
dec bitcount ;az pokial sa nedosiahne hranica posuvania v
byte ;ENG;till not reached boundary of shifting in byte
breq DoneMask
lsl temp2 ;nula do dalsieho spodneho bitu masky ;ENG;
zero to the next low bit of mask
rjmp HalfDeletePosuvMask
DoneMask:
and temp1,temp2 ;odmaskuj aby zostali iba vrchne posunute bity
v temp1 ;ENG;unmask to remain only high shifted bits in
temp1
com temp2 ;invertuj masku ;ENG;invert mask
ld temp0,Y ;nahraj byte ktory este treba posunut od
pozicie bitcount do temp0 ;ENG;load byte which must be shifted from
position bitcount to temp0
and temp0,temp2 ;odmaskuj aby zostali iba spodne neposunute
bity v temp0 ;ENG;unmask to remain only low nonshifted bits
in temp0
or temp1,temp0 ;a zluc posunutu a neposunutu cast ;ENG;
and put together shifted and nonshifted part
st Y,temp1 ;a nahraj spat ;ENG;and store back
ret ;a skonci ;ENG;and finish
;------------------------------------------------------------------------------------------
MirrorInBufferBytes:
push USBBufptrY
push ByteCount
ldi USBBufptrY,InputBufferBegin
rcall MirrorBufferBytes
pop ByteCount
pop USBBufptrY
ret
;------------------------------------------------------------------------------------------
MirrorBufferBytes:
add ByteCount,USBBufptrY ;ByteCount ukazuje na koniec spravy ;ENG;
ByteCount shows to the end of message
MirrorBufferloop:
ld temp0,Y ;nahraj prijaty byte z buffera ;ENG;load
received byte from buffer
ldi temp1,8 ;pocitadlo bitov ;ENG;bits counter
MirrorBufferByteLoop:
ror temp0 ;do carry dalsi najnizsi bit ;ENG;to carry
next least bit
rol temp2 ;z carry dalsi bit na obratene poradie ;ENG;
from carry next bit to reverse order
dec temp1 ;bol uz cely byte ;ENG;was already
entire byte
brne MirrorBufferByteLoop ;ak nie tak opakuj dalsi najnizsi bit ;ENG;
if no then repeat next least bit
st Y+,temp2 ;ulozenie spat ako obrateny byte a zvys
pointer do buffera ;ENG;save back as reversed byte and increment
pointer to buffer
cp USBBufptrY,ByteCount ;ak este neboli vsetky ;ENG;if not yet been
all
brne MirrorBufferloop ;tak opakuj ;ENG;then repeat
ret ;inak skonci ;ENG;otherwise finish
;------------------------------------------------------------------------------------------
;CheckCRCIn: ;ENG;CheckCRCIn:
; push USBBufptrY ;ENG; kiss USBBUFPTRY
; push ByteCount ;ENG; kiss ByteCount
; ldi USBBufptrY,InputBuffercompare ;ENG; ldi USBBUFPTRY,
InputBuffercompare
; rcall CheckCRC ;ENG; rcall CheckCRC
; pop ByteCount ;ENG; pope ByteCount
; pop USBBufptrY ;ENG; pope USBBUFPTRY
; ret ;ENG; lip
;------------------------------------------------------------------------------------------
AddCRCOut:
push USBBufptrY
push ByteCount
ldi USBBufptrY,OutputBufferBegin
rcall CheckCRC
com temp0 ;negacia CRC ;ENG;negation of CRC
com temp1
st Y+,temp1 ;ulozenie CRC na koniec buffera (najskor
MSB) ;ENG;save CRC to the end of buffer (at first MSB)
st Y,temp0 ;ulozenie CRC na koniec buffera (potom
LSB) ;ENG;save CRC to the end of buffer (then LSB)
dec USBBufptrY ;pointer na poziciu CRC ;ENG;pointer to CRC
position
ldi ByteCount,2 ;otocit 2 byty CRC ;ENG;reverse bits
order in 2 bytes CRC
rcall MirrorBufferBytes ;opacne poradie bitov CRC (pri vysielani CRC
sa posiela naskor MSB) ;ENG;reverse bits order in CRC
(transmiting CRC - MSB first)
pop ByteCount
pop USBBufptrY
ret
;------------------------------------------------------------------------------------------
CheckCRC: ;vstup: USBBufptrY = zaciatok spravy ,ByteCount = dlzka spravy ;ENG;
input: USBBufptrY = begin of message ,ByteCount
= length of message
add ByteCount,USBBufptrY ;ByteCount ukazuje na koniec spravy ;ENG;
ByteCount points to the end of message
inc USBBufptrY ;nastav pointer na zaciatok spravy - vynechat
SOP ;ENG;set the pointer to message start - omit SOP
ld temp0,Y+ ;nahraj PID do temp0 ;ENG;load PID to temp0
;a nastav pointer na zaciatok spravy -
vynechat aj PID ;ENG;and set the pointer to start of message - omit also PID
cpi temp0,DATA0PID ;ci je DATA0 pole ;ENG;if is DATA0 field
breq ComputeDATACRC ;pocitaj CRC16 ;ENG;compute CRC16
cpi temp0,DATA1PID ;ci je DATA1 pole ;ENG;if is DATA1 field
brne CRC16End ;ak nie tak skonci ;ENG;if no then finish
ComputeDATACRC:
ser temp0 ;inicializacia zvysku LSB na 0xff ;ENG;
initialization of remaider LSB to 0xff
ser temp1 ;inicializacia zvysku MSB na
0xff ;ENG;initialization of remaider MSB to 0xff
CRC16Loop:
ld temp2,Y+ ;nahraj spravu do temp2 a zvys pointer do
buffera ;ENG;load message to temp2 and increment pointer to buffer
ldi temp3,8 ;pocitadlo bitov v byte - temp3 ;ENG;bits
counter in byte - temp3
CRC16LoopByte:
bst temp1,7 ;do T uloz MSB zvysku (zvysok je iba 16 bitovy
- 8 bit vyssieho byte) ;ENG;to T save MSB of remainder (remainder
is only 16 bits - 8 bit of higher byte)
bld bitcount,0 ;do bitcount LSB uloz T - MSB zvysku ;ENG;
to bitcount LSB save T - of MSB remainder
eor bitcount,temp2 ;XOR bitu spravy a bitu zvysku - v LSB
bitcount ;ENG;XOR of bit message and bit remainder - in LSB bitcount
rol temp0 ;posun zvysok dolava - nizsi byte (dva byty -
cez carry) ;ENG;shift remainder to the left - low byte (two bytes
- through carry)
rol temp1 ;posun zvysok dolava - vyssi byte (dva byty -
cez carry) ;ENG;shift remainder to the left - high byte (two bytes
- through carry)
cbr temp0,1 ;znuluj LSB zvysku ;ENG;znuluj LSB remains
lsr temp2 ;posun spravu doprava ;ENG;shift message to
right
ror bitcount ;vysledok XOR-u bitov z LSB do carry ;ENG;
result of XOR bits from LSB to carry
brcc CRC16NoXOR ;ak je XOR bitu spravy a MSB zvysku = 0 , tak
nerob XOR ;ENG;if is XOR bitmessage and MSB of remainder
= 0 , then no XOR
ldi bitcount,CRC16poly>>8 ;do bitcount CRC polynom - vrchny byte ;ENG;
to bitcount CRC polynomial - high byte
eor temp1,bitcount ;a urob XOR zo zvyskom a CRC polynomom -
vrchny byte ;ENG;and make XOR from remains and CRC polynomial
- high byte
ldi bitcount,CRC16poly ;do bitcount CRC polynom - spodny byte ;ENG;
to bitcount CRC polynomial - low byte
eor temp0,bitcount ;a urob XOR zo zvyskom a CRC polynomom -
spodny byte ;ENG;and make XOR of remainder and CRC polynomial
- low byte
CRC16NoXOR:
dec temp3 ;boli uz vsetky bity v byte ;ENG;were
already all bits in byte
brne CRC16LoopByte ;ak nie, tak chod na dalsi bit ;ENG;unless,
then go to next bit
cp USBBufptrY,ByteCount ;bol uz koniec spravy ;ENG;was already end-
of-message
brne CRC16Loop ;ak nie tak opakuj ;ENG;unless then repeat
CRC16End:
ret ;inak skonci (v temp0 a temp1 je
vysledok) ;ENG;otherwise finish (in temp0 and temp1 is result)
;------------------------------------------------------------------------------------------
LoadDescriptorFromROM:
lpm ;nahraj z pozicie ROM pointera do R0 ;ENG;
load from ROM position pointer to R0
st Y+,R0 ;R0 uloz do buffera a zvys buffer ;ENG;
R0 save to buffer and increment buffer
adiw ZH:ZL,1 ;zvys ukazovatel do ROM ;ENG;increment index
to ROM
dec ByteCount ;pokial nie su vsetky byty ;ENG;till are
not all bytes
brne LoadDescriptorFromROM ;tak nahravaj dalej ;ENG;then load next
rjmp EndFromRAMROM ;inak skonci ;ENG;otherwise finish
;------------------------------------------------------------------------------------------
LoadDescriptorFromROMZeroInsert:
lpm ;nahraj z pozicie ROM pointerra do R0 ;ENG;
load from ROM position pointer to R0
st Y+,R0 ;R0 uloz do buffera a zvys buffer ;ENG;
R0 save to buffer and increment buffer

bst RAMread,3 ;ak je 3 bit jednotkovy - nebude sa vkladat

nula ;ENG;if bit 3 is one - don't insert zero
brtc InsertingZero ;inak sa bude vkladat nula ;ENG;otherwise
zero will be inserted
adiw ZH:ZL,1 ;zvys ukazovatel do ROM ;ENG;increment index
to ROM
lpm ;nahraj z pozicie ROM pointerra do R0 ;ENG;
load from ROM position pointer to R0
st Y+,R0 ;R0 uloz do buffera a zvys buffer ;ENG;
R0 save to buffer and increment buffer
clt ;a znuluj ;ENG;and clear
bld RAMread,3 ;treti bit v RAMread - aby sa v dalsom
vkladali nuly ;ENG;the third bit in RAMread - for to the next zero
insertion will be made
rjmp InsertingZeroEnd ;a pokracuj ;ENG;and continue
InsertingZero:
clr R0 ;na vkladanie nul ;ENG;for insertion of
zero
st Y+,R0 ;nulu uloz do buffera a zvys buffer ;ENG;
zero save to buffer and increment buffer
InsertingZeroEnd:
adiw ZH:ZL,1 ;zvys ukazovatel do ROM ;ENG;increment index
to ROM
subi ByteCount,2 ;pokial nie su vsetky byty ;ENG;till are
not all bytes
brne LoadDescriptorFromROMZeroInsert ;tak nahravaj dalej ;ENG;then load
next
rjmp EndFromRAMROM ;inak skonci ;ENG;otherwise finish
;------------------------------------------------------------------------------------------
LoadDescriptorFromSRAM:
ld R0,Z ;nahraj z pozicie RAM pointerra do R0 ;ENG;
load from position RAM pointer to R0
st Y+,R0 ;R0 uloz do buffera a zvys buffer ;ENG;
R0 save to buffer and increment buffer
adiw ZH:ZL,1 ;zvys ukazovatel do RAM ;ENG;increment index
to RAM
dec ByteCount ;pokial nie su vsetky byty ;ENG;till are
not all bytes
brne LoadDescriptorFromSRAM ;tak nahravaj dalej ;ENG;then load next
rjmp EndFromRAMROM ;inak skonci ;ENG;otherwise finish
;------------------------------------------------------------------------------------------
LoadDescriptorFromEEPROM:
out EEARL,ZL ;nastav adresu EEPROM Lo ;ENG;set the
address EEPROM Lo
out EEARH,ZH ;nastav adresu EEPROM Hi ;ENG;set the
address EEPROM Hi
sbi EECR,EERE ;vycitaj EEPROM do registra EEDR ;ENG;
read EEPROM to register EEDR
in R0,EEDR ;nahraj z EEDR do R0 ;ENG;load from EEDR to
R0
st Y+,R0 ;R0 uloz do buffera a zvys buffer ;ENG;
R0 save to buffer and increment buffer
adiw ZH:ZL,1 ;zvys ukazovatel do EEPROM ;ENG;increment
index to EEPROM
dec ByteCount ;pokial nie su vsetky byty ;ENG;till are
not all bytes
brne LoadDescriptorFromEEPROM;tak nahravaj dalej ;ENG;then load next
rjmp EndFromRAMROM ;inak skonci ;ENG;otherwise finish
;------------------------------------------------------------------------------------------
LoadXXXDescriptor:
ldi temp0,SOPbyte ;SOP byte ;ENG;SOP byte
sts OutputBufferBegin,temp0 ;na zaciatok vysielacieho buffera dat
SOP ;ENG;to begin of tramsmiting buffer store SOP
ldi ByteCount,8 ;8 bytov nahrat ;ENG;8 byte store
ldi USBBufptrY,OutputBufferBegin+2 ;do vysielacieho buffera ;ENG;
to transmitting buffer

and RAMread,RAMread ;ci sa bude citat z RAM alebo ROM-ky

alebo EEPROM-ky ;ENG;if will be reading from RAM or ROM or EEPROM
brne FromRAMorEEPROM ;0=ROM,1=RAM,2=EEPROM,4=ROM s
vkladanim nuly ;ENG;0=ROM,1=RAM,2=EEPROM,4=ROM with zero insertion
(string)
FromROM:
rjmp LoadDescriptorFromROM ;nahrat descriptor z ROM-ky ;ENG;
load descriptor from ROM
FromRAMorEEPROM:
sbrc RAMread,2 ;ak RAMread=4 ;ENG;if RAMREAD=4
rjmp LoadDescriptorFromROMZeroInsert ;citaj z ROM s vkladanim nuly ;ENG;
read from ROM with zero insertion
sbrc RAMread,0 ;ak RAMread=1 ;ENG;if RAMREAD=1
rjmp LoadDescriptorFromSRAM ;nahraj data zo SRAM-ky ;ENG;load data
from SRAM
rjmp LoadDescriptorFromEEPROM ;inak citaj z EEPROM ;ENG;otherwise
read from EEPROM
EndFromRAMROM:
sbrc RAMread,7 ;ak je najvyssi bit v premennej
RAMread=1 ;ENG;if is most significant bit in variable RAMread=1
clr RAMread ;znuluj RAMread ;ENG;clear RAMread
rcall ToggleDATAPID ;zmenit DATAPID ;ENG;change DATAPID
ldi USBBufptrY,OutputBufferBegin+1 ;do vysielacieho buffera - pozicia
DATA PID ;ENG;to transmitting buffer - position of
DATA PID
ret
;------------------------------------------------------------------------------------------
PrepareUSBOutAnswer: ;pripravenie odpovede do buffera ;ENG;prepare answer to
buffer
rcall PrepareUSBAnswer ;pripravenie odpovede do
buffera ;ENG;prepare answer to buffer
MakeOutBitStuff:
inc BitStuffInOut ;vysielaci buffer - vkladanie bitstuff
bitov ;ENG;transmitting buffer - insertion of bitstuff bits
ldi USBBufptrY,OutputBufferBegin ;do vysielacieho buffera ;ENG;
to transmitting buffer
rcall BitStuff
mov OutputBufferLength,ByteCount ;dlzku odpovede zapamatat pre
vysielanie ;ENG;length of answer store for transmiting
clr BitStuffInOut ;prijimaci buffer - mazanie bitstuff
bitov ;ENG;receiving buffer - deletion of bitstuff bits
ret
;------------------------------------------------------------------------------------------
PrepareUSBAnswer: ;pripravenie odpovede do buffera ;ENG;prepare answer to buffer
clr RAMread ;nulu do RAMread premennej - cita sa z
ROM-ky ;ENG;zero to RAMread variable - reading from ROM
lds temp0,InputBufferBegin+2 ;bmRequestType do temp0 ;ENG;
bmRequestType to temp0
lds temp1,InputBufferBegin+3 ;bRequest do temp1 ;ENG;bRequest
to temp1
cbr temp0,0b10011111 ;ak je 5 a 6 bit nulovy ;ENG;if is 5
and 6 bit zero
brne VendorRequest ;tak to nie je Vendor Request ;ENG;
then this isn't Vendor Request
rjmp StandardRequest ;ale je to standardny request ;ENG;
but this is standard Request
;--------------------------
VendorRequest:
clr ZH ;pre citanie z RAM alebo EEPROM ;ENG;
for reading from RAM or EEPROM

cpi temp1,1 ;
brne NoDoSetInfraBufferEmpty ;
rjmp DoSetInfraBufferEmpty ;restartne infra prijimanie (ak bolo
zastavene citanim z RAM-ky) ;ENG;restart infra receiving
(if it was stopped by reading from RAM)
NoDoSetInfraBufferEmpty:
cpi temp1,2 ;
brne NoDoGetInfraCode
rjmp DoGetInfraCode ;vysle prijaty infra kod (ak je v
bufferi) ;ENG;transmit received infra code (if it is in buffer)
NoDoGetInfraCode:
cpi temp1,3 ;
brne NoDoSetDataPortDirection
rjmp DoSetDataPortDirection ;nastavi smer toku datovych
bitov ;ENG;set flow direction of datal bits
NoDoSetDataPortDirection:
cpi temp1,4 ;
brne NoDoGetDataPortDirection
rjmp DoGetDataPortDirection ;zisti smer toku datovych bitov ;ENG;
detect of flow direction of data bits
NoDoGetDataPortDirection:
cpi temp1,5 ;
brne NoDoSetOutDataPort
rjmp DoSetOutDataPort ;nastavi datove bity (ak su vstupne,
tak ich pull-up) ;ENG;set data bits (if they are inputs, then
pull-ups)
NoDoSetOutDataPort:
cpi temp1,6 ;
brne NoDoGetOutDataPort
rjmp DoGetOutDataPort ;zisti nastavenie datovych out bitov
(ak su vstupne, tak ich pull-up) ;ENG;detect settings of data
out bits (if they are input, then pull-ups)
NoDoGetOutDataPort:
cpi temp1,7 ;
brne NoDoGetInDataPort
rjmp DoGetInDataPort ;vrati hodnotu datoveho vstupneho
portu ;ENG;return value of input data port
NoDoGetInDataPort:
cpi temp1,8 ;
brne NoDoEEPROMRead
rjmp DoEEPROMRead ;vrati obsah EEPROM od urcitej
adresy ;ENG;return contents of EEPROM from given address
NoDoEEPROMRead:
cpi temp1,9 ;
brne NoDoEEPROMWrite
rjmp DoEEPROMWrite ;zapise EEPROM na urcitu adresu urcite
data ;ENG;write to EEPROM to given address given data
NoDoEEPROMWrite:
cpi temp1,10 ;
brne NoDoRS232Send
rjmp DoRS232Send ;vysle byte na seriovy linku ;ENG;
transmit byte to serial line
NoDoRS232Send:
cpi temp1,11 ;
brne NoDoRS232Read
rjmp DoRS232Read ;vrati prijaty byte zo seriovej linky
(ak sa nejaky prijal) ;ENG;returns received byte from serial line
NoDoRS232Read:
cpi temp1,12 ;
brne NoDoSetRS232Baud
rjmp DoSetRS232Baud ;nastavi prenosovu rychlost seriovej
linky ;ENG;set line speed of of serial line
NoDoSetRS232Baud:
cpi temp1,13 ;
brne NoDoGetRS232Baud
rjmp DoGetRS232Baud ;vrati prenosovu rychlost seriovej
linky ;ENG;return line speed of serial line
NoDoGetRS232Baud:
cpi temp1,14 ;
brne NoDoGetRS232Buffer
rjmp DoGetRS232Buffer ;vrati prenosovu rychlost seriovej
linky ;ENG;return line speed of serial line
NoDoGetRS232Buffer:
cpi temp1,15 ;
brne NoDoSetRS232DataBits
rjmp DoSetRS232DataBits ;nastavi prenosovu rychlost seriovej
linky ;ENG;set line speed of serial line
NoDoSetRS232DataBits:
cpi temp1,16 ;
brne NoDoGetRS232DataBits
rjmp DoGetRS232DataBits ;vrati prenosovu rychlost seriovej
linky ;ENG;return line speed of serial line
NoDoGetRS232DataBits:
cpi temp1,17 ;
brne NoDoSetRS232Parity
rjmp DoSetRS232Parity ;nastavi prenosovu rychlost seriovej
linky ;ENG;set line speed of serial line
NoDoSetRS232Parity:
cpi temp1,18 ;
brne NoDoGetRS232Parity
rjmp DoGetRS232Parity ;vrati prenosovu rychlost seriovej
linky ;ENG;return line speed of serial line
NoDoGetRS232Parity:
cpi temp1,19 ;
brne NoDoSetRS232StopBits
rjmp DoSetRS232StopBits ;nastavi prenosovu rychlost seriovej
linky ;ENG;set line speed of serial line
NoDoSetRS232StopBits:
cpi temp1,20 ;
brne NoDoGetRS232StopBits
rjmp DoGetRS232StopBits ;vrati prenosovu rychlost seriovej
linky ;ENG;return line speed of serial line
NoDoGetRS232StopBits:

cpi temp1,USER_FNC_NUMBER+0 ;
brne NoDoUserFunction0
rjmp DoUserFunction0 ;vykona uzivatelsku rutinu0 ;ENG;
execute of user function0
NoDoUserFunction0:
cpi temp1,USER_FNC_NUMBER+1 ;
brne NoDoUserFunction1
rjmp DoUserFunction1 ;vykona uzivatelsku rutinu1 ;ENG;
execute of user function1
NoDoUserFunction1:
cpi temp1,USER_FNC_NUMBER+2 ;
brne NoDoUserFunction2
rjmp DoUserFunction2 ;vykona uzivatelsku rutinu2 ;ENG;
execute of user function1
NoDoUserFunction2:

rjmp ZeroDATA1Answer ;ak to bolo nieco nezname, tak priprav

nulovu odpoved ;ENG;if that it was something unknown, then
prepare zero answer

;----------------------------- USER FUNCTIONS --------------------------------------

;------------------------------TEMPLATE OF YOUR FUNCTION----------------------------

;------------------ BEGIN: This is template how to write own function --------------

;free of use are registers:

;temp0,temp1,temp2,temp3,ACC,ZH,ZL
;registers are destroyed after execution (use push/pop to save content)

;at the end of routine you must correctly set registers:

;RAMread - 0=reading from ROM, 1=reading from RAM, 2=reading from EEPROM
;temp0 - number of transmitted data bytes
;ZH,ZL - pointer to buffer of transmitted data (pointer to ROM/RAM/EEPROM)

;to transmit data (preparing data to buffer) :

;to transmit data you must jump to "ComposeEndXXXDescriptor"
;to transmit one zero byte you can jump to "OneZeroAnswer" (commonly used as
confirmation of correct processing)
;to transmit two zero byte you can jump to "TwoZeroAnswer" (commonly used as
confirmation of error in processing)
;for small size (up to 8 bytes) ansver use buffer AnswerArray (see function
DoGetOutDataPort:)

DoUserFunctionX:
DoUserFunction0: ;send byte(s) of RAM starting at position given by first parameter in
function
lds temp0,InputBufferBegin+4 ;first parameter Lo into temp0
lds temp1,InputBufferBegin+5 ;first parameter Hi into temp1
;lds temp2,InputBufferBegin+6 ;second parameter Lo into temp2
;lds temp3,InputBufferBegin+7 ;second parameter Hi into temp3
;lds ACC,InputBufferBegin+8 ;number of requested bytes from USB
host (computer) into ACC

;Here add your own code:

;-------------------------------------------------------------------
nop ;example of code - nothing to do
nop
nop
nop
nop
;-------------------------------------------------------------------

mov ZL,temp0 ;will be sending value of RAM - from

address stored in temp0 (first parameter Lo of function)
mov ZH,temp1 ;will be sending value of RAM - from
address stored in temp1 (first parameter Hi of function)
inc RAMread ;RAMread=1 - reading from RAM
ldi temp0,255 ;send max number of bytes - 255 bytes
are maximum
rjmp ComposeEndXXXDescriptor ;a prepare data
DoUserFunction1:
rjmp OneZeroAnswer ;only confirm receiving by one zero
byte answer
DoUserFunction2:
rjmp TwoZeroAnswer ;only confirm receiving by two zero
bytes answer
;------------------ END: This is template how to write own function ----------------

;----------------------------- USER FUNCTIONS --------------------------------------

;--------------------------
DoSetInfraBufferEmpty:
rjmp OneZeroAnswer ;potvrd prijem jednou nulou ;ENG;
acknowledge reception with single zero
;--------------------------
DoGetInfraCode:

http://avr-asm.tripod.com/usb232.html (2 of 4)1/20/2009 8:56:38 PM

16 BIT MATH (AVR 202)

rjmp OneZeroAnswer ;potvrd prijem jednou nulou ;ENG;

acknowledge reception with single zero
;--------------------------
DoSetDataPortDirection:
lds temp1,InputBufferBegin+7 ;stvrty parameter - bitova maska ktore
porty menit ;ENG;fourth parameter - bit mask - which
port(s) to change

lds temp0,InputBufferBegin+4 ;prvy parameter - smer datovych bitov

DDRB ;ENG;first parameter - direction of data bits DDRB
andi temp0,0b00111100 ;zamaskovat nepouzite piny ;ENG;
mask unused pins
sbrc temp1,0 ;ak je bit0 nulovy - nemen port ;ENG;
if bit0 is zero - don't change port state
out DDRB,temp0 ;a update smeru datoveho portu ;ENG;
and update direction of data port

lds temp0,InputBufferBegin+5 ;druhy parameter - smer datovych bitov

DDRC ;ENG;second parameter - direction of data bits
DDRC
sbrc temp1,1 ;ak je bit1 nulovy - nemen port ;ENG;
if bit1 is zero - don't change port state
out DDRC,temp0 ;a update smeru datoveho portu ;ENG;
and update direction of data port

lds temp0,InputBufferBegin+6 ;treti parameter - smer datovych bitov

DDRD ;ENG;third parameter - direction of data bits DDRD
andi temp0,0b11111000 ;zamaskovat nepouzite piny ;ENG;
mask unused pins
ori temp0,0b00000010 ;zamaskovat nepouzite piny ;ENG;
mask unused pins
sbrc temp1,2 ;ak je bit2 nulovy - nemen port ;ENG;
if bit2 is zero - don't change port state
out DDRD,temp0 ;a update smeru datoveho portu ;ENG;
and update direction of data port

rjmp OneZeroAnswer ;potvrd prijem jednou nulou ;ENG;

acknowledge reception with single zero
;--------------------------
DoGetDataPortDirection:
in temp0,DDRB ;nacitaj stav smeru DDRB ;ENG;
read direction of DDRB
sts AnswerArray,temp0 ;do pola AnswerArray ;ENG;to array
AnswerArray
in temp0,DDRC ;nacitaj stav smeru DDRC ;ENG;
read direction of DDRC
sts AnswerArray+1,temp0 ;do pola AnswerArray ;ENG;to array
AnswerArray
in temp0,DDRD ;nacitaj stav smeru DDRD ;ENG;
read direction of DDRD
sts AnswerArray+2,temp0 ;do pola AnswerArray ;ENG;to array
AnswerArray
ldi ZL,AnswerArray ;posiela sa hodnota z
AnswerArray ;ENG;sending is value from AnswerArray
ldi temp0,0x81 ;RAMread=1 - cita sa z RAM-ky ;ENG;
RAMREAD=1 - reading from RAM
mov RAMread,temp0 ;(najvyssi bit na 1 - aby sa hned
premenna RAMread znulovala) ;ENG;(highest bit set to 1 - to zero RAMread
immediatelly)
ldi temp0,3 ;posielaju sa tri byty ;ENG;sending
are three bytes
rjmp ComposeEndXXXDescriptor ;a priprav data ;ENG;and prepare data
;--------------------------
DoSetOutDataPort:
lds temp1,InputBufferBegin+7 ;stvrty parameter - bitova maska ktore
porty menit ;ENG;fourth parameter - bit mask - which
port(s) to change

lds temp0,InputBufferBegin+4 ;prvy parameter - hodnota datovych

bitov PORTB ;ENG;first parameter - value of data bits PORTB
andi temp0,0b00111100 ;zamaskovat nepouzite piny ;ENG;
mask unused pins
sbrc temp1,0 ;ak je bit0 nulovy - nemen port ;ENG;
if bit0 is zero - don't change port state
out PORTB,temp0 ;a update datoveho portu ;ENG;
and update data port

lds temp0,InputBufferBegin+5 ;druhy parameter - hodnota datovych

bitov PORTC ;ENG;second parameter - value of data bits
PORTC
sbrc temp1,1 ;ak je bit1 nulovy - nemen port ;ENG;
if bit1 is zero - don't change port state
out PORTC,temp0 ;a update datoveho portu ;ENG;
and update data port

lds temp0,InputBufferBegin+6 ;treti parameter - hodnota datovych

bitov PORTD ;ENG;third parameter - value of data bits PORTD
andi temp0,0b11111000 ;zamaskovat nepouzite piny ;ENG;
mask unused pins
ori temp0,0b00000011 ;zamaskovat nepouzite piny ;ENG;
mask unused pins
sbrc temp1,2 ;ak je bit2 nulovy - nemen port ;ENG;
if bit2 is zero - don't change port state
out PORTD,temp0 ;a update datoveho portu ;ENG;
and update data port

rjmp OneZeroAnswer ;potvrd prijem jednou nulou ;ENG;

acknowledge reception with single zero
;--------------------------
DoGetOutDataPort:
in temp0,PORTB ;nacitaj stav PORTB ;ENG;read PORTB
sts AnswerArray,temp0 ;do pola AnswerArray ;ENG;to array
AnswerArray
in temp0,PORTC ;nacitaj stav PORTC ;ENG;read PORTC
sts AnswerArray+1,temp0 ;do pola AnswerArray ;ENG;to array
AnswerArray
in temp0,PORTD ;nacitaj stav PORTD ;ENG;read PORTD
sts AnswerArray+2,temp0 ;do pola AnswerArray ;ENG;to array
AnswerArray
ldi ZL,AnswerArray ;posiela sa hodnota z
AnswerArray ;ENG;sending is value from AnswerArray
ldi temp0,0x81 ;RAMread=1 - cita sa z RAM-ky ;ENG;
RAMREAD=1 - reading from RAM
mov RAMread,temp0 ;(najvyssi bit na 1 - aby sa hned
premenna RAMread znulovala) ;ENG;(highest bit set to 1 - to zero RAMread
immediatelly)
ldi temp0,3 ;posielaju sa tri byty ;ENG;sending
are three bytes
rjmp ComposeEndXXXDescriptor ;a priprav data ;ENG;and prepare data
;--------------------------
DoGetInDataPort:
in temp0,PINB ;nacitaj stav PINB ;ENG;read PINB
sts AnswerArray,temp0 ;do pola AnswerArray ;ENG;to array
AnswerArray
in temp0,PINC ;nacitaj stav PINC ;ENG;read PINC
sts AnswerArray+1,temp0 ;do pola AnswerArray ;ENG;to array
AnswerArray
in temp0,PIND ;nacitaj stav PIND ;ENG;read PIND
sts AnswerArray+2,temp0 ;do pola AnswerArray ;ENG;to array
AnswerArray
ldi ZL,AnswerArray ;posiela sa hodnota z
AnswerArray ;ENG;sending is value from AnswerArray
ldi temp0,0x81 ;RAMread=1 - cita sa z RAM-ky ;ENG;
RAMREAD=1 - reading from RAM
mov RAMread,temp0 ;(najvyssi bit na 1 - aby sa hned
premenna RAMread znulovala) ;ENG;(highest bit set to 1 - to zero RAMread
immediatelly)
ldi temp0,3 ;posielaju sa tri byty ;ENG;sending
are three bytes
rjmp ComposeEndXXXDescriptor ;a priprav data ;ENG;and prepare data
;------------------------------------------------------------------------------------------
DoGetIn:
ldi ZL,0 ;posiela sa hodnota v R0 ;ENG;
sending value in R0
ldi temp0,0x81 ;RAMread=1 - cita sa z RAM-ky ;ENG;
RAMread=1 - reading from RAM
mov RAMread,temp0 ;(najvyssi bit na 1 - aby sa hned
premenna RAMread znulovala) ;ENG;(highest bit set to 1 - to zero RAMread
immediatelly)
ldi temp0,1 ;posli iba jeden byte ;ENG;send only
single byte
rjmp ComposeEndXXXDescriptor ;a priprav data ;ENG;and prepare data
;------------------------------------------------------------------------------------------
DoEEPROMRead:
lds ZL,InputBufferBegin+4 ;prvy parameter - offset v EEPROM-
ke ;ENG;first parameter - offset in EEPROM
lds ZH,InputBufferBegin+5
ldi temp0,2
mov RAMread,temp0 ;RAMread=2 - cita sa z EEPROM-
ky ;ENG;RAMREAD=2 - reading from EEPROM
ldi temp0,E2END+1 ;pocet mojich bytovych odpovedi do
temp0 - cela dlzka EEPROM ;ENG;number my byte answers to temp0 -
entire length of EEPROM
rjmp ComposeEndXXXDescriptor ;inak priprav data ;ENG;otherwise
prepare data
;--------------------------
DoEEPROMWrite:
lds ZL,InputBufferBegin+4 ;prvy parameter - offset v EEPROM-ke
(adresa) ;ENG;first parameter - offset in EEPROM (address)
lds ZH,InputBufferBegin+5
lds R0,InputBufferBegin+6 ;druhy parameter - data, ktore sa maju
zapisat do EEPROM-ky (data) ;ENG;second parameter - data
to store to EEPROM (data)
out EEAR,ZL ;nastav adresu EEPROM ;ENG;set the
address of EEPROM
out EEARH,ZH
out EEDR,R0 ;nastav data do EEPROM ;ENG;set the
data to EEPROM
cli ;zakaz prerusenie ;ENG;disable
interrupt
sbi EECR,EEMWE ;nastav master write enable ;ENG;
set the master write enable
sei ;povol prerusenie (este sa vykona
nasledujuca instrukcia) ;ENG;enable interrupt (next instruction is performed)
sbi EECR,EEWE ;samotny zapis ;ENG;write
WaitForEEPROMReady:
sbic EECR,EEWE ;pockaj si na koniec zapisu ;ENG;
wait to the end of write
rjmp WaitForEEPROMReady ;v slucke (max cca 4ms) (kvoli
naslednemu citaniu/zapisu) ;ENG;in loop (max cca 4ms) (because of
possible next reading/writing)
rjmp OneZeroAnswer ;potvrd prijem jednou nulou ;ENG;
acknowledge reception with single zero
;--------------------------
DoRS232Send:
lds temp0,InputBufferBegin+4 ;prvy parameter - hodnota vysielana na
RS232 ;ENG;first parameter - value transmitted to RS232
out UDR,temp0 ;vysli data na UART ;ENG;transmit
data to UART
WaitForRS232Send:
sbis UCR,TXEN ;ak nie je povoleny UART
vysielac ;ENG;if disabled UART transmitter
rjmp OneZeroAnswer ;tak skonci - ochrana kvoli zacykleniu
v AT90S2323/2343 ;ENG;then finish - protection because loop
lock in AT90S2323/2343
sbis USR,TXC ;pockat na dovysielanie bytu ;ENG;
wait for transmition finish
rjmp WaitForRS232Send
rjmp OneZeroAnswer ;potvrd prijem jednou nulou ;ENG;
acknowledge reception with single zero
;--------------------------
DoRS232Read:
rjmp TwoZeroAnswer ;iba potvrd prijem dvoma nulami ;ENG;
only acknowledge reception with two zero
;--------------------------
DoSetRS232Baud:
lds temp0,InputBufferBegin+4 ;prvy parameter - hodnota baudrate na
RS232 ;ENG;first parameter - value of baudrate of RS232
lds temp1,InputBufferBegin+6 ;druhy parameter - hodnota baudrate na
RS232 - high byte ;ENG;second parameter - baudrate of
RS232 - high byte
cbr temp1,1<<URSEL ;zapisovat sa bude baudrate high byte
(nie UCSRC) ;ENG;writing will be baudrate high byte (no
UCSRC)
out UBRRH,temp1 ;nastav rychlost UART-u high
byte ;ENG;set the speed of UART high byte
out UBRR,temp0 ;nastav rychlost UART-u low
byte ;ENG;set the speed of UART low byte
rjmp OneZeroAnswer ;potvrd prijem jednou nulou ;ENG;
acknowledge reception with single zero
;--------------------------
DoGetRS232Baud:
in temp0,UBRR ;vrat rychlost UART-u Lo ;ENG;
return speed of UART Lo
sts AnswerArray,temp0
in temp0,UBRRH ;vrat rychlost UART-u Hi ;ENG;
return speed of UART Hi
sts AnswerArray+1,temp0 ;do pola AnswerArray ;ENG;to array
AnswerArray
ldi ZL,AnswerArray ;posiela sa hodnota z
AnswerArray ;ENG;sending is value from AnswerArray
ldi temp0,0x81 ;RAMread=1 - cita sa z RAM-ky ;ENG;
RAMREAD=1 - reading from RAM
mov RAMread,temp0 ;(najvyssi bit na 1 - aby sa hned
premenna RAMread znulovala) ;ENG;(highest bit set to 1 - to zero RAMread
immediatelly)
ldi temp0,2 ;posielaju sa dva byty ;ENG;sending
are two bytes
rjmp ComposeEndXXXDescriptor ;a priprav data ;ENG;and prepare data
;--------------------------
DoGetRS232Buffer:
cbi UCR,RXCIE ;zakazat interrupt od prijimania
UART ;ENG;disable interrupt from UART receiving
nop
lds temp0,RS232LengthPosPtr
lds temp1,RS232LengthPosPtr+1 ;zisti dlzku buffera RS232
kodu ;ENG;obtain buffer length of RS232 code
sbi UCR,RXCIE ;povolit interrupt od prijimania
UART ;ENG;enable interrupt from UART receiving

cpi temp0,0 ;ak nie je RS232 Buffer prazdny ;ENG;

if this isn't RS232 Buffer empty
brne SomeRS232Send ;tak ho posli ;ENG;then send it
cpi temp1,0 ;ak nie je RS232 Buffer prazdny ;ENG;
if this isn't RS232 Buffer empty
brne SomeRS232Send ;tak ho posli ;ENG;then send it
rjmp OneZeroAnswer ;inak nic neposli a potvrd prijem
jednou nulou ;ENG;otherwise nothing send and acknowledge reception
with single zero
SomeRS232Send:
lds ACC,InputBufferBegin+8 ;pocet pozadovanych bytov do
ACC ;ENG;number of requiring bytes to ACC
ldi temp2,2 ;pocet moznych dodanych bajtov (plus
word dlzky buffera) ;ENG;number of possible bytes (plus word of buffer
length)
add temp0,temp2
ldi temp2,0
adc temp1,temp2
cpi temp1,0 ;ak je MSB>0 ;ENG;if is MSB>0
brne AsRequiredGetRS232Buffer ;vysli tolko kolko sa ziada ;ENG;
transmit as many as requested
cp ACC,temp0 ;ak sa neziada viac ako mozem
dodat ;ENG;if no requested more that I can send
brcc NoShortGetRS232Buffer ;vysli tolko kolko sa ziada ;ENG;
transmit as many as requested
AsRequiredGetRS232Buffer:
mov temp0,ACC
ldi temp1,0
NoShortGetRS232Buffer:
subi temp0,2 ;uber word dlzky ;ENG;substract
word length
sbci temp1,0
lds temp2,RS232ReadPosPtr ;zisti ukazovatel citania buffera
RS232 kodu ;ENG;obtain index of reading of buffer of RS232
code
lds temp3,RS232ReadPosPtr+1
add temp2,temp0 ;zisti kde je koniec ;ENG;obtain
where is end
adc temp3,temp1
cpi temp3,HIGH(RS232BufferEnd+1) ;ci by mal pretiect ;ENG;if it
would overflow
brlo ReadNoOverflow ;
brne ReadOverflow ;ak ano - skoc na pretecenie ;ENG;
if yes - skip to overflow

cpi temp2,LOW(RS232BufferEnd+1) ;inak porovnaj LSB ;ENG;otherwise

compare LSB
brlo ReadNoOverflow ;a urob to iste ;ENG;and do the same
ReadOverflow:
subi temp2,LOW(RS232BufferEnd+1) ;vypocitaj kolko sa neprenesie ;ENG;
caculate how many not transfered
sbci temp3,HIGH(RS232BufferEnd+1) ;vypocitaj kolko sa neprenesie ;ENG;
caculate how many not transfered
sub temp0,temp2 ;a o to skrat dlzku citania ;ENG;
and with this short length of reading
sbc temp1,temp3 ;a o to skrat dlzku citania ;ENG;
and with this short length of reading
ldi temp2,LOW(RS232FIFOBegin) ;a zacni od nuly ;ENG;and start
from zero
ldi temp3,HIGH(RS232FIFOBegin) ;a zacni od nuly ;ENG;and start
from zero
ReadNoOverflow:
lds ZL,RS232ReadPosPtr ;zisti ukazovatel citania buffera
RS232 kodu ;ENG;obtain index of reading of buffer of RS232 code
lds ZH,RS232ReadPosPtr+1 ;zisti ukazovatel citania buffera
RS232 kodu ;ENG;obtain index of reading of buffer of RS232 code

sts RS232ReadPosPtr,temp2 ;zapis novy ukazovatel citania buffera

RS232 kodu ;ENG;write new index of reading of buffer of
RS232 code
sts RS232ReadPosPtr+1,temp3 ;zapis novy ukazovatel citania buffera
RS232 kodu ;ENG;write new index of reading of buffer
of RS232 code
sbiw ZL,2 ;priestor pre udaj dlzky - prenasa sa
ako prvy word ;ENG;space for length data - transmitted as first word

cbi UCR,RXCIE ;zakazat interrupt od prijimania

UART ;ENG;disable interrupt from UART receiving
inc RAMread ;RAMread=1 - cita sa z RAM-ky ;ENG;
RAMread=1 reading from RAM
lds temp2,RS232LengthPosPtr
lds temp3,RS232LengthPosPtr+1 ;zisti dlzku buffera RS232
kodu ;ENG;obtain buffer length of RS232 code
sub temp2,temp0 ;zniz dlzku buffera ;ENG;decrement
buffer length
sbc temp3,temp1
sts RS232LengthPosPtr,temp2 ;zapis novu dlzku buffera RS232
kodu ;ENG;write new buffer length of RS232 code
sts RS232LengthPosPtr+1,temp3
sbi UCR,RXCIE ;povolit interrupt od prijimania
UART ;ENG;enable interrupt from UART receiving

st Z+,temp2 ;a uloz skutocnu dlzku do

paketu ;ENG;and save real length to packet
st Z,temp3 ;a uloz skutocnu dlzku do
paketu ;ENG;and save real length to packet
sbiw ZL,1 ;a nastav sa na zaciatok ;ENG;
and set to begin
inc temp0 ;a o tento jeden word zvys pocet
prenasanych bajtov (dlzka buffer) ;ENG;and about this word increment number
of transmited bytes (buffer length)
inc temp0
rjmp ComposeEndXXXDescriptor ;a priprav data ;ENG;and prepare data
;------------------------------------------------------------------------------------------
DoSetRS232DataBits:
lds temp0,InputBufferBegin+4 ;prvy parameter - data bits 0=5db,
1=6db, 2=7db, 3=8db ;ENG;first parameter - data bits 0=5db,
1=6db, 2=7db, 3=8db
cpi temp0,DataBits8 ;ak sa ma nastavit 8-bitova
komunikacia ;ENG;if to set 8-bits communication
breq Databits8or9Set ;tak nemen 8/9 bitovu
komunikaciu ;ENG;then don't change 8/9 bit communication
in temp1,UCSRB ;inak nacitaj UCSRB ;ENG;otherwise
load UCSRB
cbr temp1,(1<<UCSZ2) ;vymaz 9-bitovu komunikaciu ;ENG;
clear 9-bit communication
out UCSRB,temp1 ;a zapis spat ;ENG;and write back
Databits8or9Set:
rcall RS232DataBitsLocal
rjmp OneZeroAnswer ;potvrd prijem jednou nulou ;ENG;
acknowledge reception with single zero
RS232DataBitsLocal:
rcall GetUCSRCtotemp1
bst temp0,0 ;nastav UCSZ0 ;ENG;set the UCSZ0
bld temp1,UCSZ0
bst temp0,1 ;nastav UCSZ1 ;ENG;set the UCSZ1
bld temp1,UCSZ1
rcall Settemp1toUCSRC
ret
GetUCSRCtotemp1:
cli ;zisti UCSRC ;ENG;obtain UCSRC
in temp1,UBRRH
in temp1,UCSRC ;do temp1 ;ENG;to temp1
sei
nop ;aby sa mohlo vykonat prerusenie pred
ret istrukciou (ret trva dlho) ;ENG;for to enable possible interrupt waiting
before ret instruction (ret has long duration)
ret
Settemp1toUCSRC:
sbr temp1,(1<<URSEL) ;bude sa zapisovat do UCSRC ;ENG;
will be writing to UCSRC
out UCSRC,temp1 ;a zapis spat do registra s novymi
UCSZ0 a UCSZ1 ;ENG;and write back to register with new UCSZ0 and UCSZ1
ret
;------------------------------------------------------------------------------------------
DoGetRS232DataBits:
rcall GetUCSRCtotemp1
clr temp0 ;znuluj odpoved ;ENG;clear answer
bst temp1,UCSZ0 ;zisti UCSZ0 ;ENG;obtain UCSZ0
bld temp0,0 ;a uloz do bitu 0 ;ENG;and save
to bit 0
bst temp1,UCSZ1 ;zisti UCSZ1 ;ENG;obtain UCSZ1
bld temp0,1 ;a uloz do bitu 1 ;ENG;and save
to bit 1
mov R0,temp0 ;vrat pocet databitov v R0 ;ENG;
return number of databits in R0
rjmp DoGetIn ;a ukonci ;ENG;and finish
;------------------------------------------------------------------------------------------
DoSetRS232Parity:
lds temp0,InputBufferBegin+4 ;prvy parameter - parity: 0=none,
1=odd, 2=even, 3=mark, 4=space ;ENG;first parameter - parity:
0=none, 1=odd, 2=even, 3=mark, 4=space
cpi temp0,3
brcc StableParity
rcall GetUCSRCtotemp1
cbr temp1,(1<<UPM1)|(1<<UPM0) ;znuluj paritne bity ;ENG;clear
parity bits
cpi temp0,ParityNone ;ci ma byt none ;ENG;if none
breq SetParityOut
sbr temp1,(1<<UPM1)
cpi temp0,ParityEven ;ci ma byt even ;ENG;if even
breq SetParityOut
sbr temp1,(1<<UPM0)
cpi temp0,ParityOdd ;ci ma byt odd ;ENG;if odd
brne ParityErrorAnswer
SetParityOut:
rcall Settemp1toUCSRC
in temp1,UCSRB ;nacitaj UCSRB ;ENG;load UCSRB
cbr temp1,(1<<UCSZ2) ;ak je 9-bitova komunikacia tak ju
zmen na menej ako 9 bitovu ;ENG;if is 9-bits communication
then change it under 9 bits
out UCSRB,temp1 ;a zapis spat ;ENG;and write back
rjmp OneZeroAnswer ;potvrd prijem jednou nulou ;ENG;
acknowledge reception with single zero
StableParity:
in temp1,UCSRB ;zmen vysielany paritny bit
TXB8 ;ENG;change transmiting parity bit TXB8
bst temp0,0 ;nacitaj najnizsi bit ;ENG;load
lowest bit
bld temp1,TXB8 ;a uloz ho na miesto TXB8 ;ENG;
and save to its place TXB8
sbr temp1,(1<<UCSZ2) ;nastav UCSZ2 bit - 9 bitova
komunikacia ;ENG;set the UCSZ2 bit - 9 bits communication
out UCSRB,temp1 ;upravene TXB8 a UCSZ2 zapisat do
UCSRB ;ENG;changed TXB8 and UCSZ2 write to UCSRB

ldi temp0,3 ;nastav 9-databit ;ENG;set the 9-

databit
rcall RS232DataBitsLocal ;a sucasne vrat v temp1 obsah
UCSRC ;ENG;and return in temp1 contents UCSRC
cbr temp1,(1<<UPM1)|(1<<UPM0) ;zakaz paritu ;ENG;disable parity
rcall Settemp1toUCSRC
rjmp OneZeroAnswer ;potvrd prijem jednou nulou ;ENG;
acknowledge reception with single zero
ParityErrorAnswer:
rjmp TwoZeroAnswer ;potvrd prijem dvoma nulami ;ENG;
acknowledge reception with two zero
;------------------------------------------------------------------------------------------
DoGetRS232Parity:
in temp1,UCSRB ;nacitaj UCSRB ;ENG;load UCSRB
sbrc temp1,UCSZ2 ;ak je 9-bitova komunikacia ;ENG;
if is 9-bits communication
rjmp ParityIsStable ;tak je parita space alebo mark ;ENG;
then parity is space or mark

rcall GetUCSRCtotemp1
cbr temp1,~((1<<UPM0)|(1<<UPM1)) ;a nechaj nenulove iba paritne
bity ;ENG;and let nonzero only parity bits

cpi temp1,(1<<UPM0)|(1<<UPM1) ;ak su obidva nastavene ;ENG;if are

both set
ldi temp0,ParityOdd ;je to odd parita ;ENG;this is
odd parity
breq RetGetParity ;a skonci ;ENG;and finish
cpi temp1,(1<<UPM1) ;ak je nastaveny UPM1 ;ENG;if is
UPM1 set
ldi temp0,ParityEven ;je to even parita ;ENG;this is
even parity
breq RetGetParity ;a skonci ;ENG;and finish
ldi temp0,ParityNone ;inak je to none parita ;ENG;otherwise
is that none parity
rjmp RetGetParity ;a skonci ;ENG;and finish
ParityIsStable:
bst temp1,TXB8 ;zisti ake je 9.-ty bit ;ENG;obtain
what is 9-th bit
ldi temp0,ParityMark ;priprav si mark odpoved ;ENG;
prepare mark answer
brts RetGetParity ;ak je 1 potom vrat mark ;ENG;
if is 1 then return mark
ldi temp0,ParitySpace ;inak vrat space ;ENG;otherwise
return space
RetGetParity:
mov R0,temp0 ;odpoved daj z temp0 do R0 ;ENG;
answer move from temp0 to R0
rjmp DoGetIn ;a ukonci ;ENG;and finish
;------------------------------------------------------------------------------------------
DoSetRS232StopBits:
lds temp0,InputBufferBegin+4 ;prvy parameter - stop bits 0=1stopbit
1=2stopbits ;ENG;first parameter - stop bit 0=1stopbit
1=2stopbits
rcall GetUCSRCtotemp1
bst temp0,0 ;a najnizsi bit z parametra ;ENG;
and lowest bit from parameter
bld temp1,USBS ;uloz ako stopbit ;ENG;save as
stopbit
rcall Settemp1toUCSRC
rjmp OneZeroAnswer ;potvrd prijem jednou nulou ;ENG;
acknowledge reception with single zero
;------------------------------------------------------------------------------------------
DoGetRS232StopBits:
rcall GetUCSRCtotemp1
clr R0 ;znuluj odpoved ;ENG;clear answer
bst temp1,USBS ;a bit USBS ;ENG;and bit USBS
bld R0,0 ;zapis do odpovede ;ENG;write to
answer
rjmp DoGetIn ;a ukonci ;ENG;and finish
;------------------------------------------------------------------------------------------
;----------------------------- END USER FUNCTIONS -------------------------------------
END USER FUNCTIONS ------------------------------

OneZeroAnswer: ;posle jednu nulu ;ENG;send single zero

ldi temp0,1 ;pocet mojich bytovych odpovedi do
temp0 ;ENG;number of my bytes answers to temp0
rjmp ComposeGET_STATUS2
;----------------------------- STANDARD USB REQUESTS ----------------------------------
STANDARD USB REQUESTS ------------------------------
StandardRequest:
cpi temp1,GET_STATUS ;
breq ComposeGET_STATUS ;

cpi temp1,CLEAR_FEATURE ;
breq ComposeCLEAR_FEATURE ;

cpi temp1,SET_FEATURE ;
breq ComposeSET_FEATURE ;

cpi temp1,SET_ADDRESS ;ak sa ma nastavit adresa ;ENG;

if to set address
breq ComposeSET_ADDRESS ;nastav adresu ;ENG;set the address

cpi temp1,GET_DESCRIPTOR ;ak sa ziada descriptor ;ENG;if

requested descriptor
breq ComposeGET_DESCRIPTOR ;vygeneruj ho ;ENG;generate it

cpi temp1,SET_DESCRIPTOR ;
breq ComposeSET_DESCRIPTOR ;

cpi temp1,GET_CONFIGURATION ;
breq ComposeGET_CONFIGURATION ;

cpi temp1,SET_CONFIGURATION ;
breq ComposeSET_CONFIGURATION ;

cpi temp1,GET_INTERFACE ;
breq ComposeGET_INTERFACE ;

cpi temp1,SET_INTERFACE ;
breq ComposeSET_INTERFACE ;

cpi temp1,SYNCH_FRAME ;
breq ComposeSYNCH_FRAME ;
;ak sa nenasla znama poziadavka ;ENG;
if not found known request
rjmp ZeroDATA1Answer ;ak to bolo nieco nezname, tak priprav
nulovu odpoved ;ENG;if that was something unknown, then prepare
zero answer

ComposeSET_ADDRESS:
lds MyUpdatedAddress,InputBufferBegin+4 ;nova adresa do
MyUpdatedAddress ;ENG;new address to MyUpdatedAddress
rjmp ZeroDATA1Answer ;posli nulovu odpoved ;ENG;send zero
answer

ComposeSET_CONFIGURATION:
lds temp0,InputBufferBegin+4 ;cislo konfiguracie do premennej
ConfigByte ;ENG;number of configuration to variable ConfigByte
sts ConfigByte,temp0 ;
ComposeCLEAR_FEATURE:
ComposeSET_FEATURE:
ComposeSET_INTERFACE:
ZeroStringAnswer:
rjmp ZeroDATA1Answer ;posli nulovu odpoved ;ENG;send zero
answer
ComposeGET_STATUS:
TwoZeroAnswer:
ldi temp0,2 ;pocet mojich bytovych odpovedi do
temp0 ;ENG;number of my bytes answers to temp0
ComposeGET_STATUS2:
ldi ZH, high(StatusAnswer<<1) ;ROMpointer na odpoved ;ENG;
ROMpointer to answer
ldi ZL, low(StatusAnswer<<1)
rjmp ComposeEndXXXDescriptor ;a dokonci ;ENG;and complete
ComposeGET_CONFIGURATION:
lds temp0,ConfigByte
and temp0,temp0 ;ak som nenakonfigurovany ;ENG;
if I am unconfigured
breq OneZeroAnswer ;tak posli jednu nulu - inak posli
moju konfiguraciu ;ENG;then send single zero - otherwise send my
configuration
ldi temp0,1 ;pocet mojich bytovych odpovedi do
temp0 ;ENG;number of my bytes answers to temp0
ldi ZH, high(ConfigAnswerMinus1<<1) ;ROMpointer na odpoved ;ENG;
ROMpointer to answer
ldi ZL, low(ConfigAnswerMinus1<<1)+1
rjmp ComposeEndXXXDescriptor ;a dokonci ;ENG;and complete
ComposeGET_INTERFACE:
ldi ZH, high(InterfaceAnswer<<1) ;ROMpointer na odpoved ;ENG;
ROMpointer to answer
ldi ZL, low(InterfaceAnswer<<1)
ldi temp0,1 ;pocet mojich bytovych odpovedi do
temp0 ;ENG;number of my bytes answers to temp0
rjmp ComposeEndXXXDescriptor ;a dokonci ;ENG;and complete
ComposeSYNCH_FRAME:
ComposeSET_DESCRIPTOR:
rcall ComposeSTALL
ret
ComposeGET_DESCRIPTOR:
lds temp1,InputBufferBegin+5 ;DescriptorType do temp1 ;ENG;
DescriptorType to temp1
cpi temp1,DEVICE ;DeviceDescriptor ;ENG;
DeviceDescriptor
breq ComposeDeviceDescriptor ;
cpi temp1,CONFIGURATION ;ConfigurationDescriptor ;ENG;
ConfigurationDescriptor
breq ComposeConfigDescriptor ;
cpi temp1,STRING ;StringDeviceDescriptor ;ENG;
StringDeviceDescriptor
breq ComposeStringDescriptor ;
ret
ComposeDeviceDescriptor:
ldi ZH, high(DeviceDescriptor<<1) ;ROMpointer na descriptor ;ENG;
ROMpointer to descriptor
ldi ZL, low(DeviceDescriptor<<1)
ldi temp0,0x12 ;pocet mojich bytovych odpovedi do
temp0 ;ENG;number of my bytes answers to temp0
rjmp ComposeEndXXXDescriptor ;a dokonci ;ENG;and complete
ComposeConfigDescriptor:
ldi ZH, high(ConfigDescriptor<<1) ;ROMpointer na descriptor ;ENG;
ROMpointer to descriptor
ldi ZL, low(ConfigDescriptor<<1)
ldi temp0,9+9+7 ;pocet mojich bytovych odpovedi do
temp0 ;ENG;number of my bytes answers to temp0
ComposeEndXXXDescriptor:
lds TotalBytesToSend,InputBufferBegin+8 ;pocet pozadovanych bytov do
TotalBytesToSend ;ENG;number of requested bytes to
TotalBytesToSend
cp TotalBytesToSend,temp0 ;ak sa neziada viac ako mozem
dodat ;ENG;if not requested more than I can send
brcs HostConfigLength ;vysli tolko kolko sa ziada ;ENG;
transmit the requested number
mov TotalBytesToSend,temp0 ;inak posli pocet mojich
odpovedi ;ENG;otherwise send number of my answers
HostConfigLength:
mov temp0,TotalBytesToSend ;
clr TransmitPart ;nuluj pocet 8 bytovych
odpovedi ;ENG;zero the number of 8 bytes answers
andi temp0,0b00000111 ;ak je dlzka delitelna 8-mimi ;ENG;
if is length divisible by 8
breq Length8Multiply ;tak nezapocitaj jednu necelu odpoved
(pod 8 bytov) ;ENG;then not count one answer (under 8 byte)
inc TransmitPart ;inak ju zapocitaj ;ENG;otherwise
count it
Length8Multiply:
mov temp0,TotalBytesToSend ;
lsr temp0 ;dlzka 8 bytovych odpovedi sa
dosiahne ;ENG;length of 8 bytes answers will reach
lsr temp0 ;delenie celociselne 8-mimi ;ENG;
integer division by 8
lsr temp0
add TransmitPart,temp0 ;a pripocitanim k poslednej necelej 8-
mici do premennej TransmitPart ;ENG;and by addition to last
non entire 8-bytes to variable TransmitPart
ldi temp0,DATA0PID ;DATA0 PID - v skutocnosti sa
stoggluje na DATA1PID v nahrati deskriptora ;ENG;DATA0 PID - in the next
will be toggled to DATA1PID in load descriptor
sts OutputBufferBegin+1,temp0 ;nahraj do vyst buffera ;ENG;store to
output buffer
rjmp ComposeNextAnswerPart
ComposeStringDescriptor:
ldi temp1,4+8 ;ak RAMread=4(vkladaj nuly z ROM-
koveho citania) + 8(za prvy byte nevkldadaj nulu) ;ENG;if RAMread=4(insert
zeros from ROM reading) + 8(behind first byte no load zero)
mov RAMread,temp1
lds temp1,InputBufferBegin+4 ;DescriptorIndex do temp1 ;ENG;
DescriptorIndex to temp1
cpi temp1,0 ;LANGID String ;ENG;LANGID String
breq ComposeLangIDString ;
cpi temp1,2 ;DevNameString ;ENG;DevNameString
breq ComposeDevNameString ;
brcc ZeroStringAnswer ;ak je DescriptorIndex vyssi nez 2 -
posli nulovu odpoved ;ENG;if is DescriptorIndex higher than
2 - send zero answer
;inak to bude VendorString ;ENG;
otherwise is VendorString
ComposeVendorString:
ldi ZH, high(VendorStringDescriptor<<1) ;ROMpointer na
descriptor ;ENG;ROMpointer to descriptor
ldi ZL, low(VendorStringDescriptor<<1)
ldi temp0,(VendorStringDescriptorEnd-VendorStringDescriptor)*4-2 ;pocet
mojich bytovych odpovedi do temp0 ;ENG;number of
my bytes answers to temp0
rjmp ComposeEndXXXDescriptor ;a dokonci ;ENG;and complete
ComposeDevNameString:
ldi ZH, high(DevNameStringDescriptor<<1) ;ROMpointer na
descriptor ;ENG;ROMpointer to descriptor
ldi ZL, low(DevNameStringDescriptor<<1)
ldi temp0,(DevNameStringDescriptorEnd-DevNameStringDescriptor)*4-2 ;pocet
mojich bytovych odpovedi do temp0 ;ENG;number
of my bytes answers to temp0
rjmp ComposeEndXXXDescriptor ;a dokonci ;ENG;and complete
ComposeLangIDString:
clr RAMread
ldi ZH, high(LangIDStringDescriptor<<1) ;ROMpointer na
descriptor ;ENG;ROMpointer to descriptor
ldi ZL, low(LangIDStringDescriptor<<1)
ldi temp0,(LangIDStringDescriptorEnd-LangIDStringDescriptor)*2;pocet
mojich bytovych odpovedi do temp0 ;ENG;number of my
bytes answers to temp0
rjmp ComposeEndXXXDescriptor ;a dokonci ;ENG;and complete
;------------------------------------------------------------------------------------------
ZeroDATA1Answer:
rcall ComposeZeroDATA1PIDAnswer
ret
;----------------------------- END positionARD USB REQUESTS
------------------------------------- END DATA ENCRYPTION USB
REQUESTS ------------------------------

PrepareOutContinuousBuffer:
rcall PrepareContinuousBuffer
rcall MakeOutBitStuff
ret
;------------------------------------------------------------------------------------------
PrepareContinuousBuffer:
mov temp0,TransmitPart
cpi temp0,1
brne NextAnswerInBuffer ;ak uz je buffer prazdny ;ENG;
if buffer empty
rcall ComposeZeroAnswer ;priprav nulovu odpoved ;ENG;prepare
zero answer
ret
NextAnswerInBuffer:
dec TransmitPart ;znizit celkovu dlzku odpovede ;ENG;
decrement general length of answer
ComposeNextAnswerPart:
mov temp1,TotalBytesToSend ;zniz pocet bytov na vyslanie ;ENG;decrement
number of bytes to transmit
subi temp1,8 ;ci je este treba poslat viac ako 8
bytov ;ENG;is is necessary to send more as 8 byte
ldi temp3,8 ;ak ano - posli iba 8 bytov ;ENG;if yes -
send only 8 byte
brcc Nad8Bytov
mov temp3,TotalBytesToSend ;inak posli iba dany pocet bytov ;ENG;
otherwise send only given number of bytes
clr TransmitPart
inc TransmitPart ;a bude to posledna odpoved ;ENG;and this
will be last answer
Nad8Bytov:
mov TotalBytesToSend,temp1 ;znizeny pocet bytov do
TotalBytesToSend ;ENG;decremented number of bytes to TotalBytesToSend
rcall LoadXXXDescriptor
ldi ByteCount,2 ;dlzka vystupneho buffera (iba SOP a
PID) ;ENG;length of output buffer (only SOP and PID)
add ByteCount,temp3 ;+ pocet bytov ;ENG;+ number of bytes
rcall AddCRCOut ;pridanie CRC do buffera ;ENG;addition
of CRC to buffer
inc ByteCount ;dlzka vystupneho buffera + CRC16 ;ENG;
length of output buffer + CRC16
inc ByteCount
ret ;skonci ;ENG;finish
;------------------------------------------------------------------------------------------
.equ USBversion =0x0100 ;pre aku verziu USB je to
(1.00) ;ENG;for what version USB is that (1.00)
.equ VendorUSBID =0x03EB ;identifikator dodavatela
(Atmel=0x03EB) ;ENG; vendor identifier (Atmel=0x03EB)
.equ DeviceUSBID =0x0004 ;identifikator vyrobku (USB to RS232
converter ATmega8=0x0004) ;ENG;product identifier (USB to
RS232 converter ATmega8=0x0004)
.equ DeviceVersion =0x0003 ;cislo verzie vyrobku
(verzia=0.03) ;ENG;version number of product (version=0.03)
;(0.01=AT90S2313 Infra buffer) ;ENG;
(0.01=AT90S2313 Infra buffer)
;(0.02=AT90S2313 RS232 buffer 32bytes) ;ENG;
(0.02=AT90S2313 RS232 buffer 32bytes)
;(0.03=ATmega8 RS232 buffer 800bytes) ;ENG;
(0.03=ATmega8 RS232 buffer 800bytes)
.equ MaxUSBCurrent =50 ;prudovy odber z USB (50mA) - rezerva
na MAX232 ;ENG;current consumption from USB (50mA) - together
with MAX232
;------------------------------------------------------------------------------------------
DeviceDescriptor:
.db 0x12,0x01 ;0 byte - velkost deskriptora v bytoch ;ENG;0
byte - size of descriptor in byte
;1 byte - typ deskriptora: Deskriptor
zariadenia ;ENG;1 byte - descriptor type: Device descriptor
.dw USBversion ;2,3 byte - verzia USB LSB (1.00) ;
ENG;2,3 byte - version USB LSB (1.00)
.db 0x00,0x00 ;4 byte - trieda zariadenia ;ENG;4 byte -
device class
;5 byte - podtrieda zariadenia ;ENG;5 byte -
subclass
.db 0x00,0x08 ;6 byte - kod protokolu ;ENG;6 byte - protocol
code
;7 byte - velkost FIFO v bytoch ;ENG;7 byte -
FIFO size in bytes
.dw VendorUSBID ;8,9 byte - identifikator dodavatela
(Cypress=0x04B4) ;ENG;8,9 byte - vendor identifier (Cypress=0x04B4)
.dw DeviceUSBID ;10,11 byte - identifikator vyrobku
(teplomer=0x0002) ;ENG;10,11 byte - product identifier (teplomer=0x0002)
.dw DeviceVersion ;12,13 byte - cislo verzie vyrobku
(verzia=0.01) ;ENG;12,13 byte - product version number (verzia=0.01)
.db 0x01,0x02 ;14 byte - index stringu "vyrobca" ;
ENG;14 byte - index of string "vendor"
;15 byte - index stringu "vyrobok" ;
ENG;15 byte - index of string "product"
.db 0x00,0x01 ;16 byte - index stringu "seriove
cislo" ;ENG;16 byte - index of string "serial number"
;17 byte - pocet moznych konfiguracii ;
ENG;17 byte - number of possible configurations
DeviceDescriptorEnd:
;------------------------------------------------------------------------------------------
ConfigDescriptor:
.db 0x9,0x02 ;dlzka,typ deskriptoru ;ENG;length,
descriptor type
ConfigDescriptorLength:
.dw 9+9+7 ;celkova dlzka vsetkych deskriptorov ;ENG;
entire length of all descriptors
ConfigAnswerMinus1: ;pre poslanie cisla congiguration number
(pozor je treba este pricitat 1) ;ENG;for sending the number
- congiguration number (attention - addition of 1 required)
.db 1,1 ;numInterfaces,congiguration number ;ENG;
numInterfaces, congiguration number
.db 0,0x80 ;popisny index stringu, atributy;bus
powered ;ENG;string index, attributes; bus powered
.db MaxUSBCurrent/2,0x09 ;prudovy odber, interface descriptor
length ;ENG;current consumption, interface descriptor length
.db 0x04,0 ;interface descriptor; cislo interface ;ENG;
interface descriptor; number of interface
InterfaceAnswer: ;pre poslanie cisla alternativneho
interface ;ENG;for sending number of alternatively interface
.db 0,1 ;alternativne nastavenie interface; pocet
koncovych bodov okrem EP0 ;ENG;alternatively interface; number of endpoints
except EP0
StatusAnswer: ;2 nulove odpovede (na usetrenie
miestom) ;ENG;2 zero answers (saving ROM place)
.db 0,0 ;trieda rozhrania; podtrieda rozhrania ;ENG;
interface class; interface subclass
.db 0,0 ;kod protokolu; index popisneho stringu ;ENG;
protocol code; string index
.db 0x07,0x5 ;dlzka,typ deskriptoru - endpoint ;ENG;
length, descriptor type - endpoint
.db 0x81,0 ;endpoint address; transfer type ;ENG;
endpoint address; transfer type
.dw 0x08 ;max packet size ;ENG;max packet size
.db 10,0 ;polling interval [ms]; dummy byte (pre
vyplnenie) ;ENG;polling interval [ms]; dummy byte (for filling)
ConfigDescriptorEnd:
;------------------------------------------------------------------------------------------
LangIDStringDescriptor:
.db (LangIDStringDescriptorEnd-LangIDStringDescriptor)*2,3 ;dlzka, typ:
string deskriptor ;ENG;length, type: string descriptor
.dw 0x0409 ;English ;ENG;English
LangIDStringDescriptorEnd:
;------------------------------------------------------------------------------------------
VendorStringDescriptor:
.db (VendorStringDescriptorEnd-VendorStringDescriptor)*4-2,3 ;
dlzka, typ: string deskriptor ;ENG;length, type: string descriptor
CopyRight:
.db "Ing. Igor Cesko, Copyright(c) 2003"
CopyRightEnd:
VendorStringDescriptorEnd:
;------------------------------------------------------------------------------------------
DevNameStringDescriptor:
.db (DevNameStringDescriptorEnd-DevNameStringDescriptor)*4-2,3;dlzka, typ:
string deskriptor ;ENG;length, type: string descriptor
.db "Igor Atmel-AVR device: Advanced USB to RS232 converter + I/O pins
control + EEPROM scratch pad"
DevNameStringDescriptorEnd:
;------------------------------------------------------------------------------------------
;********************************************************************
;* End of Program ;ENG;* End of program
;********************************************************************
;------------------------------------------------------------------------------------------
;********************************************************************
;* EEPROM contents ;ENG;* EEPROM contents
;********************************************************************
;------------------------------------------------------------------------------------------
.eseg ;data v EEPROM-ke (vo finalnej verzii zapoznamkovat) ;ENG;data in
EEPROM (at final version comment)
;.org 0x400 ;pre naplnenie EEPROM dat na spravne adresy - hned za kod programu (vo
finalnej verzii odpoznamkovat) ;ENG;.org 0x400 ;for
filling EEPROM give on right addresses - behind the program code (at final version
uncomment)
EEData:
.db "This device was developed by Ing. Igor Cesko: cesko@internet.sk "
.db "For more information see: http://www.cesko.host.sk. "
.db "S/N:00000001"
;------------------------------------------------------------------------------------------
;********************************************************************
;* End of file ;ENG;* End of file
;********************************************************************

http://avr-asm.tripod.com/usb232.html (3 of 4)1/20/2009 8:56:38 PM

16 BIT MATH (AVR 202)

Programming the AVR Microcontrollers in Machine Language

AVR
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr) Jump to:
navigation, search The AVRs are a family of RISC microcontrollers from Atmel. Their
internal architecture was conceived by two students: Alf-Egil Bogen and Vegard
Wollan, at the Norwegian Institute of Technology (NTH] and further developed at
Atmel Norway, a subsidiary founded by the two architects. Atmel recently released
the Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices featuring
SIMD and DSP instructions, along with many additional features for audio and video
processing, intended to compete with ARM based processors. Note that the use of
"AVR" in this article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and Vegard, who are evasive
when questioned about it. Contents [hide] 1 Device Overview 1.1 Program Memory
1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2
Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official
Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development 6.4
C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly
Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and addressed separately.
Flash, EEPROM, and SRAM are all integrated onto a single die, removing the need for
external memory (though still available on some devices). [edit] Program Memory
Program instructions are stored in semi-permanent Flash memory. Each instruction
for the AVR line is either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is indicated in the naming
of the device itself. For instance, the ATmega64x line has 64Kbytes of Flash. Almost
all AVR devices are self-programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and SRAM. The AVRs have
thirty-two single-byte registers and are classified as 8-bit RISC devices. The working
registers are mapped in as the first thirty-two memory spaces (000016-001F16)
followed by the 64 I/O registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O register space may be larger
on some more extensive devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are separate addressing schemes
and optimized opcodes for register file and I/O register access, all can still be
addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost all
devices have on-die EEPROM. This is most often used for long-term parameter
storage to be retrieved even after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design. The next machine
instruction is fetched as the current one is executing. Most instructions take just one
or two clock cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were designed for the efficient
execution of compiled C code. The AVR instruction set is more orthogonal than most
eight-bit microcontrollers, however, it is not completely regular: Pointer registers X,
Y, and Z have addressing capabilities that are different from each other. Register
locations R0 to R15 have different addressing capabilities than register locations R16
to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports 32 to 63.
CLR affects flags, while SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to one. (Note though, that
neither CLR nor SER are native instructions. Instead CLR is syntactic sugar for
[produces the same machine code as] EOR R,R while SER is syntactic sugar for LDI
R,$FF. Math operations such as EOR modify flags while moves/loads/stores/
branches such as LDI do not.) [edit] Speed The AVR line can normally support clock
speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered operation
usually requires a reduced clock speed. All AVRs feature an on-chip oscillator,
removing the need for external clocks or resonator circuitry. Because many
operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz.
[edit] Development AVRs have a large following due to the free and inexpensive
development tools available, including reasonably priced development boards and
free development software. The AVRs are marketed under various names that share
the same basic core but with different peripheral and memory combinations. Some
models (notably, the ATmega range) have additional instructions to make arithmetic
faster. Compatibility amongst chips is fairly good. See external links for sites relating
to AVR development. [edit] Features Current AVRs offer a wide range of features:
RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O
Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators
Internal, Self-Programmable Instruction Flash Memory up to 256K In-System
Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code
Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB
Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator
Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire
Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As
used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller
Support USB Controller Support Proper High-speed hardware & Hub controller with
embedded AVR. Also freely available low-speed (HID) software emulation Ethernet
Controller Support Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D
Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer
(WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep
Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR
machine programming language Atmel AVR From Wikipedia, the free encyclopedia
(Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC
microcontrollers from Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of
Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by
the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many
additional features for audio and video processing, intended to compete with ARM
based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC
line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for
Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf
and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device
Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3
Machine Language Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with programs and data stored
and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single
die, removing the need for external memory (though still available on some devices).
[edit] Program Memory Program instructions are stored in semi-permanent Flash
memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash
memory is addressed using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the ATmega64x line has
64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data
Memory and Registers The data address space consists of the register file, I/O
registers, and SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are mapped in as the first
thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-
005F16). The actual usable RAM starts after both these sections (address 006016).
(Note that the I/O register space may be larger on some more extensive devices, in
which case memory mapped I/O registers will occupy a portion of the SRAM.) Even
though there are separate addressing schemes and optimized opcodes for register
file and I/O register access, all can still be addressed and manipulated as if they were
in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even after cycling the power of
the device. [edit] Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current one is executing. Most
instructions take just one or two clock cycles, making AVRs relatively fast among the
eight-bit microcontrollers. The AVR family of processors were designed for the
efficient execution of compiled C code. The AVR instruction set is more orthogonal
than most eight-bit microcontrollers, however, it is not completely regular: Pointer
registers X, Y, and Z have addressing capabilities that are different from each other.
Register locations R0 to R15 have different addressing capabilities than register
locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O
ports 32 to 63. CLR affects flags, while SER does not, even though they are
complementary instructions. CLR set all bits to zero and SER sets them to one. (Note
though, that neither CLR nor SER are native instructions. Instead CLR is syntactic
sugar for [produces the same machine code as] EOR R,R while SER is syntactic
sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/
stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support
clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs feature an on-chip
oscillator, removing the need for external clocks or resonator circuitry. Because
many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per
MHz. [edit] Development AVRs have a large following due to the free and inexpensive
development tools available, including reasonably priced development boards and
free development software. The AVRs are marketed under various names that share
the same basic core but with different peripheral and memory combinations. Some
models (notably, the ATmega range) have additional instructions to make arithmetic
faster. Compatibility amongst chips is fairly good. See external links for sites relating
to AVR development. [edit] Features Current AVRs offer a wide range of features:
RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O
Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators
Internal, Self-Programmable Instruction Flash Memory up to 256K In-System
Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code
Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB
Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator
Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire
Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As
used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller
Support USB Controller Support Proper High-speed hardware & Hub controller with
embedded AVR. Also freely available low-speed (HID) software emulation Ethernet
Controller Support Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D
Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer
(WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep
Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR
machine programming language Atmel AVR From Wikipedia, the free encyclopedia
(Redirected from Avr) Jump to: navigation, search The AVRs are a family of RISC
microcontrollers from Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute of
Technology (NTH] and further developed at Atmel Norway, a subsidiary founded by
the two architects. Atmel recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP instructions, along with many
additional features for audio and video processing, intended to compete with ARM
based processors. Note that the use of "AVR" in this article refers to the 8-bit RISC
line of Atmel AVR Microcontrollers. The acronym AVR has been reported to stand for
Advanced Virtual RISC. It's also rumoured to stand for the company's founders: Alf
and Vegard, who are evasive when questioned about it. Contents [hide] 1 Device
Overview 1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3
Machine Language Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with programs and data stored
and addressed separately. Flash, EEPROM, and SRAM are all integrated onto a single
die, removing the need for external memory (though still available on some devices).
[edit] Program Memory Program instructions are stored in semi-permanent Flash
memory. Each instruction for the AVR line is either 16 or 32 bits in length. The Flash
memory is addressed using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the ATmega64x line has
64Kbytes of Flash. Almost all AVR devices are self-programmable. [edit] Data
Memory and Registers The data address space consists of the register file, I/O
registers, and SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are mapped in as the first
thirty-two memory spaces (000016-001F16) followed by the 64 I/O registers (002016-
005F16). The actual usable RAM starts after both these sections (address 006016).
(Note that the I/O register space may be larger on some more extensive devices, in
which case memory mapped I/O registers will occupy a portion of the SRAM.) Even
though there are separate addressing schemes and optimized opcodes for register
file and I/O register access, all can still be addressed and manipulated as if they were
in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even after cycling the power of
the device. [edit] Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current one is executing. Most
instructions take just one or two clock cycles, making AVRs relatively fast among the
eight-bit microcontrollers. The AVR family of processors were designed for the
efficient execution of compiled C code. The AVR instruction set is more orthogonal
than most eight-bit microcontrollers, however, it is not completely regular: Pointer
registers X, Y, and Z have addressing capabilities that are different from each other.
Register locations R0 to R15 have different addressing capabilities than register
locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities than I/O
ports 32 to 63. CLR affects flags, while SER does not, even though they are
complementary instructions. CLR set all bits to zero and SER sets them to one. (Note
though, that neither CLR nor SER are native instructions. Instead CLR is syntactic
sugar for [produces the same machine code as] EOR R,R while SER is syntactic
sugar for LDI R,$FF. Math operations such as EOR modify flags while moves/loads/
stores/branches such as LDI do not.) [edit] Speed The AVR line can normally support
clock speeds from 0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs feature an on-chip
oscillator, removing the need for external clocks or resonator circuitry. Because
many operations on the AVR are single cycle, the AVR can achieve up to 1MIPS per
MHz. [edit] Development AVRs have a large following due to the free and inexpensive
development tools available, including reasonably priced development boards and
free development software. The AVRs are marketed under various names that share
the same basic core but with different peripheral and memory combinations. Some
models (notably, the ATmega range) have additional instructions to make arithmetic
faster. Compatibility amongst chips is fairly good. See external links for sites relating
to AVR development. [edit] Features Current AVRs offer a wide range of features:
RISC Core Running Many Single Cycle Instructions Multifunction, Bi-directional I/O
Ports with Internal, Configurable Pull-up Resistors Multiple Internal Oscillators
Internal, Self-Programmable Instruction Flash Memory up to 256K In-System
Programmable using ICSP, JTAG, or High Voltage methods Optional Boot Code
Section with Independent Lock Bits for Protection Internal Data EEPROM up to 4KB
Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time generator
Lighting (PWM Specific) Controller models Dedicated I²C Compatible Two-Wire
Interface (TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As
used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN Controller
Support USB Controller Support Proper High-speed hardware & Hub controller with
embedded AVR. Also freely available low-speed (HID) software emulation Ethernet
Controller Support Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D
Converters, with multiplex of up to 16 channels Brownout Detection Watchdog Timer
(WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep
Modes picoPower Devices Atmel AVR assembler programming language Atmel AVR
machine programming language

http://avr-asm.tripod.com/usb232.html (4 of 4)1/20/2009 8:56:38 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

AVR ISP PROTOCOL

HOME
RETRO_DAN
;
ASM FORUM ***************************************************************************
ASM MATH ;*
;* Title : AVR ISP (Auto adr inc, 19200bps)
TUTORIAL #1
;* Version : 2.0
TUTORIAL #2 ;* Last updated : 1998.01.06 (mlund)
TUTORIAL #3 ;* Target : AT90S1200
;* File : ispprog.asm
MATH 200 ;* Author : Atmel Norway
MATH 200b ;*
;* DESCRIPTION
MATH 201 ;* The firmware on all programmers now support a
MATH 202 unified protocol for
;* program and data memory programming. The host
MATH 32X
computer do not need
MATH YX ;* to know if the programmer operates in serial or
parallel mode.
DIV16 XX
;*
DIV 24 24 ;* The following commands are supported. All commands
DIV 3216 start with a
;* single letter. The programmer returns 13d (carriage
FLOAT 128 return) or the
SQRT16 ;* data read after the command is finished.
;*
MATH 202 ;* +-------------
MATH 202 +------------+------+
;* Commands | Host writes |
DEC ASCII
Host reads | |
INT ASCII ;* -------- +-----+-------
+------+-----+ |
HX2ASC
;* | ID | data |
AVG8 222 data | | Note |
FFT7 ;* +-----------------------------------+-----+-------
+------+-----+------+
COPY 102 ;* | Enter programming mode | 'P' |
LPM 108 | | 13d | 1 |
;* | Set address | 'A' | ah al
EPROM 100 | | 13d | 2 |
SER EPROM ;* | Write program memory, low byte | 'c' | dd
| | 13d | 3 |
DFLASH AT45
;* | Write program memory, high byte | 'C' | dd
FLASH CARD | | 13d | 3 |
;* | Issue Page Write | 'm' |
VFX SMIL
| | 13d | |
VFX MEM ;* | Read program memory | 'R' | |dd
SORT 220 (dd)| | 4 |
;* | Write data memory | 'D' | dd
CRC 236 | | 13d | |
XMODEM REC ;* | Read data memory | 'd' |
| dd | | |
UART 304 ;* | Chip erase | 'e' |
UART 305 | | 13d | |
;* | Write lock bits | 'l' | dd
UART 128
| | 13d | |
UART BUFF ;* | Write fuse bits | 'f' | dd
USB 232 | | 13d | 11 |
;* | Read fuse and lock bits | 'F' |
AVR ISP | dd | | 11 |
ISP 2313 ;* | Leave programming mode | 'L' |
| | 13d | 5 |
ISP 1200 ;* | Select device type | 'T' | dd
AVR SPI | | 13d | 6 |
;* | Read signature bytes | 's' | |
I2C 300 3*dd | | |
I2C 302 ;* | Return supported device codes | 't' | |
n*dd | 00d | 7 |
I2C TWI26
;* | Return software identifier | 'S' | | s
I2C/TWI 128 [7] | | 8 |
I2C/TWI AT8 ;* | Return sofware version | 'V' | |
dd dd | | 9 |
DALLAS-1W ;* | Return hardware version | 'v' | |
DALLAS CRC dd dd | | 9 |
;* | Return programmer type | 'p' |
ETHNET 8019 | dd | | 10 |
TEA ;* | Set LED | 'x' | dd
| | 13d | 12 |
ADC 128 ;* | Clear LED | 'y' | dd
ADC 10B | | 13d | 12 |
;* | Universial command | ':' | 3*dd
ADC 400
| dd | 13d | |
ADC 401 ;* +-----------------------------------+-----+-------
THERM 232 +------+-----+------+
;*
IRD 410 ;* NOTE 1
LCD HD44 ;* The Enter programming mode command MUST be sent one
time prior to
LCD 2313 ;* the other commands, with the exception of the 't',
LCD44 2313 'S', 'V', 'v'
;* and 'T' commands. The 'T' command must be sent
KBD 240 before this command
MUX 242 ;* (see note 6).
;*
KBD PS2
;* For programmers supporting both parallel and serial
KBD PC/128 programming
PS2 EMU ;* mode this command enters parallel programming mode.
For programmers
BOOT MG8 ;* supporting only serial programming mode, this
BOOT DR8 command enters serial
;* programming mode.
ALM CLK ;*
CLOCK 8564 ;* NOTE 2
;* The ah and al are the high and low order bytes of
90 DAYS
the address. For
DELAYS ;* parallel programmers this command issues the Load
Address Low/High
CALL ID
;* Byte command. For serial programmers the address
DTMF 314 byte is stored for
PWM 6CH ;* use by the Read/Write commands.
;*
PWM 10K ;* NOTE 3
ENCODE ;* For parallel programmers this command issues the
Program Flash
STH-11 ;* command. For serial programmers this command
ATMEL CORP iussues the Write
;* Program Memory Command. For devices with byte-wide
AVR
program memories
BUTTERFLY ;* only the low byte command should be used.
AVR BOOK ;*
;* NOTE 4
;* The contents of the program memory at the address
given by the 'A'
;* command are written to the serial port in binary
form. For byte
;* wide memories one byte is written. For 16 bit
memories two bytes
;* are written,MSB first.
;*
;* NOTE 5
;* This command must be executed after the programming
is finished.
;*
;* NOTE 6
;* The select device type command must be sent before
the enter
;* programming command
;*
;* NOTE 7
;* The supported device codes are returned in binary
form terminated
;* by 0x00.
;*
;* NOTE 8
;* This return a 7 character ASCII string identifying
the programmer.
;* For the in-system programmer it is "AVR ISP".
;*
;* NOTE 9
;* The software/hardware version are returned as two
ASCII numbers.
;*
;* NOTE 10
;* This command should be used to identify the
programmer type. The
;* return value is 'S' for serial (or SPI) programmers
or 'P' for
;* parallel programmers.
;*
;* NOTE 11
;* The write fuse bits command are available only on
parallel
;* programmers and only for AVR devices (device code <
0x80). The host
;* should use the return programmer type command to
determine the
;* programmer type, do not use the "AVR PPR"
idenifier because other
;* programmers may be available in the future.
;*
;* NOTE 12
;* Currently only the AVR development board has LEDs.
The other boards
;* must implement this commands as NOPs.
;*
;* NOTE 13
;* Devices using Page Mode Programming write one
page of flash memory
;* before issuing a Page Mode Write Pulse.
;
***************************************************************************

;**** includes ****

.include "1200def.inc"

;
***************************************************************************
;*
;* CONSTANTS
;* device codes
;*
;* DESCRIPTION
;* The following device codes must be used by the host
computer. Note
;* that the device codes are arbitrary selected, they
do not have any
;* thing in common with the signature bytes stored in
the device.
;*
;* The following devices are supported (make a new
table for each
;* software release):
;*
;* SW_MAJOR=1, SW_MINOR=5
;* AT90S1200 rev. C (abbreviated S1200C)
;* AT90S1200 rev. D (abbreviated S1200D)
;* AT90S8515 rev. A (abbreviated S8515A)
;* AT89S8252 (abbreviated S8252)
;*
;* SW_MAJOR=1, SW_MINOR=6
;* AT90S1200 rev. C (abbreviated S1200C)
;* AT90S1200 rev. D (abbreviated S1200D)
;* AT90S8515 rev. A (abbreviated S8515A)
;* AT89S8252 (abbreviated S8252)
;* ATmega103 rev. A (abbreviated S01838A)
;*
;
***************************************************************************

.equ S1200C = 0x12

.equ S1200D = 0x13
.equ S2313A = 0x20
.equ S4414A = 0x28
.equ S8515A = 0x38
.equ S8252 = 0x86
.equ S2323A = 0x48

.equ S01838C = 0x40

.equ S01838D = 0x41

;**** Revision Codes ****

.equ SW_MAJOR = 2 ; Major SW revision

number
.equ SW_MINOR = 0 ; Minor SW revision
number
.equ HW_MAJOR = 1 ; Major HW revision
number
.equ HW_MINOR = 0 ; Minor HW revision
number

;
***************************************************************************
;*
;* MACROS
;* Program Macros
;*
;* DESCRIPTION
;* Change the following four macros if the RESET pin
to the
;* target moves and/or if the SCK/MISO/MOSO moves.
;*
;
***************************************************************************

.macro set_reset
sbi portb,4
.endm

.macro clr_reset
cbi portb,4
.endm

.macro ddrd_init
nop
; sbi ddrd,3
.endm

.macro ddrb_init
ldi temp1,0xdf
out ddrb,temp1 ; PB5 is input, the rest is
output
.endm

.macro ddrb_release
ldi temp1,(1<= 0x20) && (device <= 0x7F) )
brlo s2
tst device
brmi s2
s0b: ; {
ldi count,32 ; count = 32;
s1: ; do {
rcall rdser ; if (rdser
== 0x53) // SPI read (byte 3)
cpi s_data,0x53
breq s3 ;
break;
ldi s_data,0x00 ; wrser
(0x00); // SPI write (byte 4)
rcall wrser
pulse_sck ; pulse SCK
ldi s_data,0xac ; wrser
(0xac); // SPI write (byte 1)
rcall wrser
ldi s_data,0x53 ; wrser
(0x53); // SPI write (byte 2)
rcall wrser
dec count ; } while(--count);
brne s1
rjmp s3 ; }
; else
s2: ; {
ldi s_data,0x00 ; wrser
(0x00); // SPI write (byte 3)
rcall wrser
s3: ; }
cpi device,S8252 ; if (device != S8252)
breq s4 ; {
ldi s_data,0x00 ; wrser(0x00); //
SPI write (byte 4)
rcall wrser
s4: ; }
ldi temp1,0x10 ; delay(0x10);
rcall delay
ret

;
***************************************************************************
;*
;* FUNCTION
;* show_id
;*
;* DESCRIPTION
;* Show our ID ("AVR ISP") on the serial line.
;*
;
***************************************************************************

show_id:ldi u_data,0x41 ; 'A'

rcall putc
ldi u_data,0x56 ; 'V'
rcall putc
ldi u_data,0x52 ; 'R'
rcall putc
ldi u_data,0x20 ; ' '
rcall putc
ldi u_data,0x49 ; 'I'
rcall putc
ldi u_data,0x53 ; 'S'
rcall putc
ldi u_data,0x50 ; 'P'
rcall putc
ret

;
***************************************************************************
;*
;* RESET
;*
;* DESCRIPTION
;* Initialization
;*
;
***************************************************************************

RESET: clr temp1

out GIMSK,temp1 ; disable external interrupt
ser temp1 ; Initialize
out PORTD,temp1
set_reset ; set RESET=1
out PORTB,temp1
ddrb_release
rcall u_init ; Initialize UART
sei ; Enable interrupts

;
***************************************************************************
;*
;* PROGRAM
;* waitcmd -> main
;*
;* DESCRIPTION
;* Wait for and execute commands.
;*
;
***************************************************************************

waitcmd:rcall getc ; while (getc() ==

ESC) {};
cpi u_data,0x1b
breq waitcmd

;**** Device Type ****

cpi u_data,0x54 ; 'T' Device type

brne w0
rcall getc ; getc(); // dummy
mov device,u_data ; putc(device);
rjmp put_ret

;**** Return Software Identifier ****

w0: cpi u_data,0x53 ; 'S' Return software

identifier
brne w1
rcall show_id ; show_id();
rjmp waitcmd

;**** Return Software Version ****

w1: cpi u_data,0x56 ;'V' Return software version

brne w2
ldi u_data,0x30+SW_MAJOR ; putc(0x30+SW_MAJOR);
rcall putc
ldi u_data,0x30+SW_MINOR ; putc(0x30+SW_MINOR);
rcall putc
rjmp waitcmd

;**** Return Hardware Version ****

w2: cpi u_data,0x76 ;'v' Return hardware version

brne w3
ldi u_data,0x30+HW_MAJOR ; putc(0x30+HW_MAJOR);
rcall putc
ldi u_data,0x30+HW_MINOR ; putc(0x30+HW_MINOR);
rcall putc
rjmp waitcmd

;**** Show Supported Devices ****

w3: cpi u_data,0x74 ; 't' Show supported devices

brne w4
ldi u_data,S1200C ; putc(S1200C);
rcall putc
ldi u_data,S1200D ; putc(S1200D);
rcall putc
ldi u_data,S2313A ; putc(S2313A);
rcall putc
ldi u_data,S4414A ; putc(S4414A);
rcall putc
ldi u_data,S8515A ; putc(S8515A);
rcall putc
ldi u_data,S2323A ; putc(S2323A);
rcall putc
ldi u_data,S8252 ; putc(S8252);
rcall putc
ldi u_data,0x00 ; putc(0x00); // end of
device list
rcall putc
rjmp waitcmd

;**** Return Programmer Type ****

w4: cpi u_data,0x70 ; 'p' Return programmer type

brne w5
ldi u_data,0x53 ; putc('S'); // serial
programmer
rcall putc
rjmp waitcmd

;**** Set LED ****

w5: cpi u_data,0x78 ; 'x' Set LED (ignored)

brne w6
rjmp put_ret

;**** Clear LED ****

w6: cpi u_data,0x79 ; 'y' Clear LED (ignored)

brne w7
rjmp put_ret

;**** Enter Programming Mode ****

; We require that the device code be selected before

any of the other commands

w7:
cpi device,S1200C ; if ((device != S1200C) &&
breq w72
cpi device,S1200D ; (device != S1200D) &&
breq w72
cpi device,S8515A ; (device != S8515A) &&
breq w72
cpi device,S4414A ; (device != S4414A) &&
breq w72
cpi device,S2313A ; (device != S2313A) &&
breq w72
cpi device,S8252 ; (device != S8252) &&
breq w72
cpi device,S01838C ; (device != S01838C) &&
breq w72
cpi device,S01838D ; (device != S01838D) &&
breq w72
cpi device,S2323A ; (device != S2323A))
breq w72
rjmp put_err ; goto put_err();

w72: cpi u_data,0x50 ; 'P' Enter

programming mode
brne w8
rcall spiinit ; spiinit();
rjmp put_ret

;**** Wait Program Memory ****

;* USAGE
;* wait_pm(byte cmd, byte c_data);
;*
;* cmd : 0x28 - wait for high byte written
;* 0x20 - wait for low byte written
;* u_data : current data written

;wait_pm: ; do
; ; {
; mov s_data,cmd ; wrser
(cmd); // SPI write (byte 1)
; rcall wrser
; mov s_data,addrh ; wrser
(addrh); // SPI write (byte 2)
; rcall wrser
; mov s_data,addrl ; wrser
(addrl); // SPI write (byte 3)
; rcall wrser
; rcall rdser ; s_data = rdser
(); // SPI read (byte 4)
; }
; cp s_data,u_data ; while(s_data != u_data);
; brne wait_pm
; ret

;**** Write Program Memory, High Byte ****

w8: cpi u_data,0x43 ; 'C' Write program memory,

high byte
brne w9
rcall getc
cpi device,S8252 ; if (device == S8252)
brne w81 ; {
rjmp put_err ; goto err();
; // (AT89 series
have byte wide program memory !)
; }
w81: ldi s_data,0x48 ; wrser
(0x48); // SPI write (byte 1)
rcall wrser
mov s_data,addrh ; wrser(addrh); //
SPI write (byte 2)
rcall wrser
mov s_data,addrl ; wrser(addrl); //
SPI write (byte 3)
rcall wrser
cpi device,S01838C ; invert data on 01838 rev
C!
brne w81b
com u_data
w81b:
mov s_data,u_data ; wrser(u_data); //
SPI write (byte 4)
rcall wrser
cpi device,S01838C ; no delay for S01838 (Uses
Page Write Mode instead)
breq w82
cpi device,S01838D
breq w82

ldi temp1,0x20 ; delay(0x20); //

24585 cycles delay
rcall delay ; //
Page mode requires no delay!
w82:
ldi temp1,0x01 ; Auto increment
address !!!!
clr temp2
add addrl,temp1
adc addrh,temp2
rjmp put_ret ; goto reply();

;**** Write Program Memory, Low Byte ****

w9: cpi u_data,0x63 ; 'c' Write program memory,

low byte
brne w12
rcall getc

cpi device,S8252 ; if (device != S8252)

breq w989 ; {
ldi s_data,0x40 ; wrser(0x40); //
SPI write (byte 1)
rcall wrser
mov s_data,addrh ; s_data = addrh;
rjmp w91 ; }
; else
w989: ; {
mov s_data,addrh ; s_data = (addrh <<
3) | 0x02;
rcall shift_s_data3
ori s_data,0x02
w91: ; }
rcall wrser ; wrser(s_data); //
SPI write (byte 2)
mov s_data,addrl ; wrser(addrl); //
SPI write (byte 3)
rcall wrser
cpi device,S01838C ; invert data on 01838 rev
C!
brne w91b
com u_data
w91b:
mov s_data,u_data ; wrser(u_data); //
SPI write (byte 4)
rcall wrser
cpi device,S01838C ; no delay for S01838 (Uses
Page Write Mode instead)
breq w92
cpi device,S01838D
breq w92
ldi temp1,0x20 ; delay(0x20); //
24585 cycles delay
rcall delay ; //
Page mode requires no delay!
w92:
rjmp put_ret ; goto reply();

;**** Read Program Memory ****

w12: cpi u_data,0x52 ; 'R' Read program

memory
brne w10 ;
cpi device,S8252 ; if (device != S8252)
breq w1289 ; {
ldi s_data,0x28 ; wrser(0x28); //
SPI write (byte 1)
rcall wrser
mov s_data,addrh ; s_data = addrh;
rjmp w121 ; }
; else
w1289: ; {
mov s_data,addrh ; s_data = (addrh <<
3) | 0x01;
rcall shift_s_data3
ori s_data,0x01
w121: ; }
rcall wrser ; wrser(s_data); //
SPI write (byte 2)
mov s_data,addrl ; wrser(addrl); //
SPI write (byte 3)
rcall wrser
rcall rdser ; putc(rdser()); //
Send data (byte 4)
mov u_data,s_data
rcall putc
cpi device,S8252 ; if (device == S8252)
brne w122 ; {
rjmp waitcmd ; goto waitcmd();
; }
; else
w122: ; {
ldi s_data,0x20 ; wrser(0x20); //
SPI write (byte 1)
rcall wrser
mov s_data,addrh ; wrser(addrh); //
SPI write (byte 2)
rcall wrser
mov s_data,addrl ; wrser(addrl); //
SPI write (byte 3)
rcall wrser
rcall rdser ; putc(rdser()); //
Send data (byte 4)
mov u_data,s_data
rcall putc

ldi temp1,0x01 ; Auto increment

address !!!!
clr temp2
add addrl,temp1
adc addrh,temp2

rjmp waitcmd ; goto waitcmd();

; }
shift_s_data3:
lsl s_data
lsl s_data
lsl s_data
ret

;**** Load Address ****

w10: cpi u_data,0x41 ; 'A' Load address

brne w11
rcall getc ; addrh = getc();
mov addrh,u_data
rcall getc ; addrl = getc();
mov addrl,u_data
rjmp put_ret ; goto reply();

;**** Write Data Memory ****

w11: cpi u_data,0x44 ; 'D' Write data

memory
brne w13
rcall getc
cpi device,S8252
breq w1189

ldi s_data,0xc0
rcall wrser
mov s_data,addrh
rjmp w111

w1189: mov s_data,addrh

rcall shift_s_data3
ori s_data,0x06

w111: rcall wrser

mov s_data,addrl
rcall wrser
mov s_data,u_data
rcall wrser
ldi temp1,0x20
rcall delay
rjmp put_ret

;;**** Read Data Memory ****

w13: cpi u_data,0x64 ; 'd' Read data

memory
brne w14
cpi device,S8252 ; if (device != S8252)
breq w1389 ; {
ldi s_data,0xa0 ; wrser(0xA0); //
SPI write (byte 1)
rcall wrser
mov s_data,addrh ; s_data = addrh;
rjmp w131 ; }
; else
w1389: ; {
mov s_data,addrh ; s_data = (addrh <<
3) | 0x05;
rcall shift_s_data3
ori s_data,0x05
w131: ; }
rcall wrser ; wrser(s_data); //
SPI write (byte 2)
mov s_data,addrl ; wrser(addrl); //
SPI write (byte 3)
rcall wrser
rcall rdser ; putc(rdser()); //
Send data (byte 4)
mov u_data,s_data
rcall putc
rjmp waitcmd ; goto waitcmd();

;**** Leave Programming Mode ****

w14: cpi u_data,0x4c ; 'L' Leave

programming mode
brne w15
ddrb_release
cpi device,S8252
breq w141
set_reset ; set RESET = 1
rjmp put_ret
w141: clr_reset ; set RESET = 0
rjmp put_ret

;**** Chip Erase ****

w15: cpi u_data,0x65 ; 'e' Chip erase

brne w16
ldi s_data,0xac
rcall wrser
cpi device,S8252
breq w1589
ldi s_data,0x80
rcall wrser
w1589: ldi s_data,0x04
rcall wrser
ldi s_data,0x00
rcall wrser
ldi temp1,0x30
rcall delay
rjmp put_ret

;**** Write Lock Bits ****

w16: cpi u_data,0x6c ; 'l' Write lock

bits
brne w17
rcall getc
ldi s_data,0xac
rcall wrser
mov s_data,u_data
cpi device,S8252
breq w1689
andi s_data,0x06
ori s_data,0xe0
rcall wrser
ldi s_data,0x00
rcall wrser
rjmp w162

w1689: andi s_data,0xe0

ori s_data,0x07
rcall wrser
w162: ldi s_data,0x00
rcall wrser
ldi temp1,0x30
rcall delay
rjmp put_ret

;**** Read Signature Bytes ****

w17: cpi u_data,0x73 ; 's' Read

signature bytes
brne w18
cpi device,S8252
brne w17begin
rjmp put_err
w17begin:
ldi param1,0x02
rcall w17call
ldi param1,0x01
rcall w17call
ldi param1,0x00
rcall w17call
rjmp waitcmd

w17call:ldi s_data,0x30
rcall wrser
ldi s_data,0x00
rcall wrser
mov s_data,param1
rcall wrser
rcall rdser
mov u_data,s_data
rcall putc
ret

;**** Write Program Memory Page ****

w18: cpi u_data,0x6D ; 'm' Write Program

Memory Page
brne w19

ldi s_data,0x4c ; wrser(0x4c); //

SPI write (byte 1)
rcall wrser

mov s_data,addrh ; wrser(addrh); //

SPI write (byte 2)
rcall wrser
mov s_data,addrl ; wrser(addrl); //
SPI write (byte 3)
rcall wrser

ldi s_data,0x00 ; wrser(0x00); //

SPI write (byte 4)
rcall wrser
ldi temp1,0xff ; delay(0xFF); //
0x20 = 24585 cycles delay
rcall delay
rjmp put_ret

;**** Universal Command ****

w19: cpi u_data,0x3A ; ':' Universal

Command
brne w99

rcall getc
mov cmd1,u_data
rcall getc
mov cmd2,u_data
rcall getc
mov cmd3,u_data
rcall universal
ldi temp1,0xff ; delay(0xFF); //
0x20 = 24585 cycles delay
rcall delay
rjmp put_ret

universal:
mov s_data,cmd1
rcall wrser
mov s_data,cmd2
rcall wrser
mov s_data,cmd3
rcall wrser
rcall rdser
mov u_data,s_data
rcall putc
ret

w99:

;**** Command Error ****

put_err:ldi u_data,0x3f ; putc('?'); \\ send '?'

rcall putc
rjmp waitcmd

;**** Reply Command ****

put_ret:ldi u_data,0x0d ; putc(0x0D); \\ send CR

rcall putc
rjmp waitcmd

;**** End of File ****

http://avr-asm.tripod.com/avrisp.html (1 of 2)1/20/2009 8:57:59 PM

16 BIT MATH (AVR 202)

Programming the AVR Microcontrollers in Machine Language

AVR
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© WebRing Inc. Search

Atmel AVR From Wikipedia, the free encyclopedia (Redirected

from Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing,
intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still
be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language

http://avr-asm.tripod.com/avrisp.html (2 of 2)1/20/2009 8:57:59 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

AVR ISP FOR 2313

HOME
RETRO_DAN
;*
ASM FORUM ;* Title : AVR ISP (Auto adr inc, 115200bps,
ASM MATH supports AVR109 commands)
;* Version : 3.7e
TUTORIAL #1
;* Last updated : Jan 14 2005
TUTORIAL #2 ;* Target : AT90S2313
TUTORIAL #3 ;* File : avr910_2313_v37e.asm
;* Author(s) : klaus@mikrocontroller-
MATH 200 projekte.de
MATH 200b ;* last Filename : avr910_2313_V36.asm
;* initial File : avr910_31.asm, Author:
MATH 201 wubblick@yahoo.com, source: www.mit8.ru/~mars/ )
MATH 202 ;*
;* DESCRIPTION
MATH 32X
;* The firmware on all programmers now support a
MATH YX unified protocol for
;* program and data memory programming. The host
DIV16 XX
computer do not need
DIV 24 24 ;* to know if the programmer operates in serial or
DIV 3216 parallel mode.
;*
FLOAT 128 ;* The following commands are supported. All commands
SQRT16 start with a
;* single letter. The programmer returns 13d (carriage
MATH 202 return) or the
MATH 202 ;* data read after the command is finished.
;*
DEC ASCII
;*
INT ASCII +-------------------+-------------+------+
;* Commands | Host
HX2ASC
writes | Host reads | |
AVG8 222 ;* -------- +-----------
FFT7 +-------+-------+-----+ |
;* | ID (hex ) |
COPY 102 data | data | | Note |
LPM 108 ;* +-----------------------------------+-----------
+-------+-------+-----+------+
EPROM 100 ;* | Enter programming mode | 'P'(0x50)
SER EPROM | | | 13d | 1 |
;* | Report autoincrement address | 'a'(0x61)
DFLASH AT45
| | | 'Y' | |
FLASH CARD ;* | Set address | 'A'(0x41) | ah
al | | 13d | 2 |
VFX SMIL
;* | Write program memory, low byte | 'c'(0x63) |
VFX MEM dd | | 13d | 3 |
SORT 220 ;* | Write program memory, high byte | 'C'(0x43) |
dd | | 13d | 3 |
CRC 236 ;* | Issue Page Write | 'm'(0x6d)
XMODEM REC | | | 13d | 13 |
;* | Read program memory | 'R'(0x52)
UART 304 | | dd(dd)| | 4 |
UART 305 ;* | Write data memory | 'D'(0x44) |
dd | | 13d | |
UART 128
;* | Read data memory | 'd'(0x64)
UART BUFF | | dd | | |
USB 232 ;* | Chip erase | 'e'(0x65)
| | | 13d | |
AVR ISP ;* | Write lock bits | 'l'(0x6c) |
ISP 2313 dd | | 13d | |
;* | Leave programming mode | 'L'(0x4c)
ISP 1200 | | | 13d | 5 |
AVR SPI ;* | Select device type | 'T'(0x54) |
dd | | 13d | 6 |
I2C 300 ;* | Read signature bytes | 's'(0x73)
I2C 302 | | 3*dd | | |
;* | Return supported device codes | 't'(0x74)
I2C TWI26
| | n*dd | 00d | 7 |
I2C/TWI 128 ;* | Return software identifier | 'S'(0x53)
I2C/TWI AT8 | | s[7] | | 8 |
;* | Return sofware version | 'V'(0x56)
DALLAS-1W | | dd dd | | 9 |
DALLAS CRC ;* | Return hardware version | 'v'(0x76)
| | dd dd | | 9 |
ETHNET 8019 ;* | Return programmer type | 'p'(0x70)
TEA | | dd | | 10 |
;* | Set LED | 'x'(0x78) |
ADC 128 dd | | 13d | 12 |
ADC 10B ;* | Clear LED | 'y'(0x79) |
dd | | 13d | 12 |
ADC 400
;* | Universial command | ':'(0x3a) |
ADC 401 3*dd | dd | 13d | 15 |
THERM 232 ;* | New universal command | '.'(0x2E) |
4*dd | dd | 13d | 15 |
IRD 410 ;* |-----------------------------------+-----------
LCD HD44 +-------+-------+-----+------|
;* | New Commands since Version 3.3 |
LCD 2313 | | | | |
LCD44 2313 ;* | Exit (AVR109, Bootloader) | 'E'(0x45)
| | | 13d | 15 |
KBD 240 ;* | Return Chip ID (Terminalmode only)| 'i'(0x69)
MUX 242 | | s[n] | | 14 |
;* +-----------------------------------+-----------
KBD PS2
+-------+-------+-----+------+
KBD PC/128 ;* | New Commands since Version 3.5 |
PS2 EMU | | | | |
;* | Implemented Atmel Bootloader commands (Atmel Appl.
BOOT MG8 Note 109) | | |
BOOT DR8 ;* | Report Block write Mode | 'b'(0x62)
| |'Y'2*nn| 13d | 16 |
ALM CLK ;* | Block Write | 'B'(0x42) |
CLOCK 8564 2*nn'M'| n*dd | 13d | 16 |
;* | Block Read | 'g'(0x67) |
90 DAYS
2*nn'M'| n*dd | 13d | 16 |
DELAYS ;* +-----------------------------------+-----------
+-------+-------+-----+------+
CALL ID
;* | Commands to test (Since V3.6, (Unverified)
DTMF 314 | | | | |
PWM 6CH ;* | Return Lockbits | 'r'(0x72)
| | dd | 13d | 17 |
PWM 10K ;* | Return High Fusebits | 'N'(0x4E)
ENCODE | | dd | 13d | 17 |
;* | Return extendet Fusebits | 'Q'(0x51)
STH-11 | | dd | 13d | 17 |
ATMEL CORP ;* | Write fuse bits (reserved) | 'f'(0x66) |
dd | | 13d | 11 |
AVR
;* | Read fuse and lock bits (reserved)| 'F'(0x46)
BUTTERFLY | | dd | | 11 |
AVR BOOK ;* +-----------------------------------+-----------
+-------+-------+-----+------+
;*
;* NOTE 1
;* The Enter programming mode command MUST be sent one
time prior to
;* the other commands, with the exception of the 't',
'S', 'V', 'v'
;* and 'T' commands. The 'T' command must be sent
before this command
;* (see note 6).
;*
;* For programmers supporting both parallel and serial
programming
;* mode this command enters parallel programming mode.
For programmers
;* supporting only serial programming mode, this
command enters serial
;* programming mode.
;*
;* NOTE 2
;* The ah and al are the high and low order bytes of
the address. For
;* parallel programmers this command issues the Load
Address Low/High
;* Byte command. For serial programmers the address
byte is stored for
;* use by the Read/Write commands.
;*
;* NOTE 3
;* For parallel programmers this command issues the
Program Flash
;* command. For serial programmers this command
iussues the Write
;* Program Memory Command. For devices with byte-wide
program memories
;* only the low byte command should be used.
;*
;* NOTE 4
;* The contents of the program memory at the address
given by the 'A'
;* command are written to the serial port in binary
form. For byte
;* wide memories one byte is written. For 16 bit
memories two bytes
;* are written,MSB first.
;*
;* NOTE 5
;* This command must be executed after the programming
is finished.
;*
;* NOTE 6
;* The select device type command must be sent before
the enter
;* programming command
;*
;* NOTE 7
;* The supported device codes are returned in binary
form terminated
;* by 0x00.
;*
;* NOTE 8
;* This return a 7 character ASCII string identifying
the programmer.
;* For the development board it is "AVR DEV", for the
parallel
;* programmer it is "AVR PPR" and for the in-curcuit
programmer it is
;* "AVR ISP".
;*
;* NOTE 9
;* The software/hardware version are returned as two
ASCII numbers.
;*
;* NOTE 10
;* This command should be used to identify the
programmer type. The
;* return value is 'S' for serial (or SPI) programmers
or 'P' for
;* parallel programmers.
;*
;* NOTE 11
;* The write fuse bits command are available only on
parallel
;* programmers and only for AVR devices (device code
&lt; 0x80). The host
;* should use the return programmer type command to
determine the
;* programmer type, do not use the "AVR PPR"
idenifier because other
;* programmers may be available in the future.
;*
;* NOTE 12
;* Currently only the AVR development board has LEDs.
The other boards
;* must implement this commands as NOPs.
;*
;* NOTE 13
;* Devices using Page Mode Programming write
one page of flash memory
;* before issuing a Page Mode Write Pulse.
;*
;* NOTE 14
;* The 'i' command is only used with a
Terminal, for debug reasons.
;* Not used in any Programmer so far
;*
;* NOTE 15
;* Lock and Fuse Bits are written using the
"universal command" (:) and
;* "new universal command" (.) in AVRProg and
AVRDUDE.
;* AVRProg has an Exit (E) command
implemented, which switches AVRProg offline
;*
;* NOTE 16
;* Atmel Bootloader commands described in
Atmel Application Note 109 implemented.
;* Very useful if you use USB to serial
converter.
;* AVRProg since Version 1.33 checks if
Programmer supports Block Mode,
;* IF Programmer responds 'Y' and the size of
the internal Buffer (nn nn), Bootloader commands
;* are used automatically from AVRProg.
(faster Protocoll)
;* Block commands send size Buffersize (nn nn)
and Type of Memory ('F'=Flash, 'E'=Data)
;* Compatibility to AVR Butterfly command set
and Bootloader. Works with AVR911 Open Source
;* Programmer.
;* For avrdude use -c butterfly instead of -c
avr910 and you get same behaviour.
;*
;* NOTE 17
;* Commands implemented but not tested yet.
;*
;* NOTE 18
;* Device 89S8252 was tested to programm with
avrprog. Shows a avrprog bug in "block Mode". Works in "standart"
;* avr910 Programming Mode. To program this
Device, disable the "Block Mode" by changing "w53: rjmp w6"
;*
;* HISTORY
;* V3.7e 11.01.05 (Klaus) Matched Devicecodes to the
new Atmel AVRProgV1.40
;* V3.7d 05.01.05 (Klaus) Removed 1200A/B/C
devicecodes, Polling 0x7F for AT90S4414, default PollcodeF = 0xFF
;* V3.7c 04.01.05 (Klaus/Micha) Some devicecodes
changed (Bootloader and "default" mode).
;* V3.7b 03.01.05 (Klaus/Leo) Bugfix for Block
read of Flash Mamory for AT89Snnnn Controllers.
;* V3.7a 29.12.04 (Klaus/Micha) addet devicecodes
for m64, m162 and m169.
;* V3.7 15.12.04 (Klaus) Rewriting polled
timing for "non Page Mode" Chips, reorganised Table for
;* different polling Codes.
Skip 0xFF Byte polling. (was buggy for some Controllers)
;* Added ATTiny2313 (device
Code 0x23), and ATMega8535 (0x6A)Support.
;* Not Supported from avrprog,
avrdude Support possible.
;* Reorganised Table for Page
Mode Chips with Pagesize. Adding different Pagesizes
;* Try to fix S89 write, BUG
in avrprog detected. Firmware should be OK now. (NOTE 18)
;* After 256 unsuccesful polls
for Flash wait additional standart time.
;* Modified "release_ports" so
that RESET is released also.
;* V3.6 10.07.04 (Klaus) Changed Block Mode Commands
to AVR109 compatibility.
;* Additional AVR109 Commands,
not testet yet.
;* V3.4-V3.5 unreleased (Klaus) cleaning up, tests for
Block Modes
;* V3.3 25.06.04 (Klaus, Thomas) added enhanced Block
write commands
; with own Protocol.
; Add 0xFF, 0x7F
(2313) check for polling Mode
;* V3.2.1 18.11.03 (Klaus) Commented out some
Controller Types, which are
; not really Supported by the
hardware, but from
; AVRProg Software. See
Comments at the end.
;* V3.2 16.11.03 (Klaus) Correctet typo in
Chrystal frequency.
;* V3.2 13.10.03 (Klaus) 7,3728 Mhz chrystal for
115.200 Baud.
;* Swap MOSI &lt;-
&gt; MISO Pinnumbers.
;* Add dual color
LED Support.
;* Add some new
Dewices.
;* V3.0 02.01.23 (wubble) Ported from 1200 to
2313.
;* Serial IO
modified to use hardware UART.
;* Added support
for multiple new devices.
;* Used data
polling to short write process.
;* Added LED
support to indicate R/W process.
;* V2.2 00.03.10 (pkastnes) Added support for
multiple new devices.
;* V2.1 98.10.26 (mlund) New date marking.
;* Removed support
for AT90S1200C.
;* Added support
for AT90S4433A.
;* V2.0 98.01.06 (mlund) ATmega103 support.
;* V1.7 97.11.06 (mlund) Universial command
(':') implemented.
;* Releases all
pins when not in
;* programming
mode.
;* V1.6e 97.11.04 (mlund) mega103 rev D support
;* V1.6c 97.10.30 (mlund) Auto incrementing / SPI sync
;* also works for
mega103.
;* V1.6 97.09.09 (hskar) Created Page Mode
Version (mega103)
;* V1.5 97.08.21 (mlund) Modified / Bugfix /
Major cleanup
;* ... ... (no records)
;* V?.? 97.03.15 (OS) Created
;*
;*
;* Device Support List: see table "Devices" at the end
of this file.

;
***************************************************************************

;**** includes ****

.include "2313def.inc"

;
***************************************************************************
;*
;* CONSTANTES
;*
;
***************************************************************************

;**** Constant declarations Data Rate ****

;******** Chrystals for maximum Baudrates

.equ XTAL = 7373 ; XTAL
frequency, Khz (7.3728 Mhz)
;********
.equ BAUD = 115200 ; Data rate, bauds
.equ N = 3 ; for
7.3728 Mhz/115.200Baud
;********
;.equ BAUD = 38400 ; Data rate, bauds
;.equ N = 11 ; for
7.3728 Mhz/38400Baud
;********

;**** definitions for different chrystals and 115.200

baud ****
;.equ XTAL = 3686 ; XTAL
frequency, Khz (3.6864 Mhz)
;*********
;.equ BAUD = 115200 ; Data rate, bauds
;.equ N = 1 ; for
3.6864 Mhz/115.200Baud
;*********
;
;********* Baudrates for 8 Mhz Chrystal
;.equ XTAL = 8000 ; XTAL
frequency, Khz (8.000 Mhz)
;*********
;.equ BAUD = 38400 ; Data rate, bauds
;.equ N = 12 ; for 8.00
Mhz/38.400 Baud
;*********
;.equ BAUD = 19200 ;Data rate, bauds
;.equ N = 25 ; for 8.00
Mhz/19.200 Baud
;*********
;.equ BAUD = 9600 ; Data
rate, bauds ! Not valid for AVRProg, use for avrdude only !
;.equ N = 51 ; for 8.00
Mhz/9.600 Baud
;*********

;********* Baudrates for 4 Mhz Chrystal

;.equ XTAL = 4000 ; XTAL
frequency, Khz (4.000 Mhz)
;*********
;.equ BAUD = 19200 ; Data rate, bauds
;.equ N = 12 ; for 4.00
Mhz/19.200 Baud
;*********
;.equ BAUD = 9600 ; Data
rate, bauds ! Not valid for AVRProg, use for avrdude only !
;.equ N = 25 ; for 4.00
Mhz/9.600 Baud
;*********

.equ RAMSTART = 0x60 ; first SRAM Adress

of 2313
.equ PAGESIZE = 0x10 ; default Page size
for Programming
.equ BUFSIZE = 0x40 ; 64 bytes internal
RAM for Buffer

;
***************************************************************************
;*
;* PORTS
;* Ports Definitions
;*
;* DESCRIPTION
;* Change the following definitions if the RESET pin
to the
;* target moves and/or if the SCK/MISO/MISO/LED moves.
;*
;
***************************************************************************

.equ LEDH = PB3 ; dual color LED

output, anode green (output)
.equ LED = PB0 ; LED output,
active low, dual color LED Kathode green (output)
.equ MISO = PB6 ; MISO pin of the
target (input)
.equ MOSI = PB5 ; MOSI pin of the
target (output)

.equ RESET = PB4 ; RESET pin of the

target (output)
.equ SCK = PB7 ; SCK pin of the
target (output)
.equ RXD = PD0 ; UART RXD line
.equ TXD = PD1 ; UART TXD line

;
***************************************************************************
;*
;* MACROS
;* Program Macros
;*
;* DESCRIPTION
;* Change the following macros if the RESET pin to the
;* target moves and/or if the SCK/MISO/MISO/LED moves.
;*
;
***************************************************************************

.macro init_ports ; init ports

ldi temp2,0xff
out PORTD,temp2
ldi temp2,0xff
out PORTB,temp2
.endm

.macro catch_ports ; catch

ports
ldi temp2,(1&lt;&lt;TXD)
out DDRD,temp2
ldi temp2,(1&lt;&lt;RESET) | (1&lt;&lt;MOSI) |
(1&lt;&lt;SCK) | (1&lt;&lt;LED) | (1&lt;&lt;LEDH)
out DDRB,temp2
.endm

.macro release_ports ; release ports

ldi temp2,(1&lt;&lt;TXD)
out DDRD,temp2
ldi temp2,(1&lt;&lt;LED) | (1&lt;&lt;LEDH)
out DDRB,temp2
.endm

.macro pas_RESET ; set RESET

passive
tst device
brmi m2 ; S89 device
sbi PORTB,RESET
rjmp m3
m2: cbi PORTB,RESET
m3:
.endm

.macro act_RESET ; set RESET

active
tst device
brmi m4 ; S89 device
cbi PORTB,RESET
rjmp m5
m4: sbi PORTB,RESET
m5:
.endm

.macro set_LED ; set LED

Port -&gt; Standart LED off, dual LED green
sbi PORTB,LED
cbi PORTB,LEDH ; added for dual
color support
.endm

.macro clr_LED ; clear LED

Port --&gt; Standart LED on, dual LED red
cbi PORTB,LED
sbi PORTB,LEDH ; added for dual
color support
.endm

.macro LED_off ; for dual

color LED, not in use
cbi PORTB,LED
cbi PORTB,LEDH
.endm

.macro sbic_MISO ; skip if

MISO cleared
sbic PINB,MISO
.endm

.macro set_MOSI ; set MOSI

sbi PORTB,MOSI
.endm

.macro clr_MOSI ; clear MOSI

cbi PORTB,MOSI
.endm

.macro clr_SCK ; clear SCK

cbi PORTB,SCK
.endm

.macro pulse_SCK ; pulse SCK

sbi PORTB,SCK
ldi temp2,(XTAL/750+1) ; had to slow down
for ATTiny2313 (internal clock) default was (XTAL/1500+1)
m0: dec temp2
brne m0
cbi PORTB,SCK
ldi temp2,(XTAL/1500+1) ; had to slow down
for ATTiny2313 (internal clock) default was (XTAL/3000+1)
m1: dec temp2
brne m1
.endm

.macro table ; load Z

pointer
ldi ZL,low(@0*2) ; low
ldi ZH,high(@0*2) ; high
.endm

;
***************************************************************************
;*
;* Global Register Variables
;*
;
***************************************************************************

;r0 used with lpm instruction

.def cmd1 = r1 ; Universal
commands params
.def cmd2 = r2 ; ..
.def cmd3 = r3 ; ..
.def pol_al = r4 ; Polling address
low
.def pol_ah = r5 ; Polling address
high
.def Bcnt1 = r6 ; Block Mode
Counter1
.def Bcnt2 = r7 ; Block Mode
Counter2
.def Bcnt3 = r8 ; Block Mode
Counter2
.def B_Flag = r9 ; Flag for ws_del
Routine
.def B_Mode = r10 ; Marks Block Mode
commands (See Note 16)
.def Memtype = r11 ; Flag for
Memorytype for Block Commands (See Note 16)
.def Pagewords = r12 ; Size of
Controller page to program in Page Mode (Words!)
.def PollcodeF = r13 ; Code for Polling
Flash

.def temp1 = r16 ; Temporary

register 1
.def temp2 = r17 ; Temporary
register 2
.def temp3 = r18 ; Temporary
register 3
.def s_data = r19 ; SPI data
.def u_data = r20 ; UART data
.def device = r21 ; Device code
.def param1 = r22 ; Param to read
signature
.def rd_s_data = r23 ; Read data on SPI
.def pol_cmd = r24 ; Polling command
.def p_data = r25 ; Polling data
;r26,r27 used as X register
.def addrl = r28 ; (YL) Low order
byte of address
.def addrh = r29 ; (YH) High order
byte of address
;r30,r31 used as Z register

;
***************************************************************************
;*
;* Interrupt Vectors
;*
;
***************************************************************************

.CSEG
rjmp INIT ; Reset Handle

;
***************************************************************************
;*
;* FUNCTION
;* u_init
;*
;* DESCRIPTION
;* Initialize UART.
;*
;
***************************************************************************

u_init:
ldi temp1,N ; set baud
rate
out UBRR,temp1
ldi temp1,(1&lt;&lt;TXEN)|(1&lt;&lt;RXEN) ;
initialize UART for TX and RX
out UCR,temp1
ret

;
***************************************************************************
;*
;* FUNCTION
;* getc
;*
;* DESCRIPTION
;* Wait for start bit and receive a character on the
UART Rx line.
;*
;
***************************************************************************

getc:
sbis USR,RXC ; wait until a
character has been received
rjmp getc
in u_data,UDR ; Read byte
from the UART
ret

;
***************************************************************************
;*
;* FUNCTION
;* putc
;*
;* DESCRIPTION
;* Send a character on the UART Tx line.
;*
;
***************************************************************************

putc:
sbis USR,UDRE ; test for TX
register empty
rjmp putc ; loop until TX
empty
out UDR,u_data ; send the
byte
ret

;
***************************************************************************
;*
;* FUNCTION
;* put_string
;*
;* DESCRIPTION
;* Send Z - pointed null-terminated string on the UART
Tx line.
;*
;
***************************************************************************

put_string:
lpm
tst r0
breq ps_ret ; check for end of
string (0x00)
mov u_data,r0
rcall putc ; putc(char)
adiw ZL,1 ; next char
rjmp put_string
ps_ret: ret

;
***************************************************************************
;*
;* FUNCTION
;* put_table
;*
;* DESCRIPTION
;* Send Z - pointed table on the UART Tx line.
;*
;
***************************************************************************

put_table:
lpm
tst r0
breq pt_ret ; check for end of
table (0x00)
mov u_data,r0
rcall putc ; putc(Byte)
adiw ZL,2 ; skip MSB
rjmp put_table
pt_ret: ret

;
***************************************************************************
;*
;* FUNCTION
;* bel_table
;*
;* DESCRIPTION
;* C=0 if device belongs to table.
;*
;
***************************************************************************

bel_table:
lpm ;
read table
tst r0 ;
check for end of table
breq c1_ret
cp device,r0
breq c0_ret ; C=0
adiw ZL,2 ; skip MSB
rjmp bel_table
c1_ret: sec ;
C=1
c0_ret: ret

;
***************************************************************************
;*
;* FUNCTION
;* set_pagesize
;*
;* DESCRIPTION
;* sets programming Page size for selected Device.
;*
;
***************************************************************************

set_pagesize:
lpm ; read table
tst r0 ; check for end of
table
breq spa_end ; no Pagesize to set
cp device,r0
breq spa_set ; C=0
adiw ZL,2 ; skip MSB
rjmp set_pagesize
spa_set:
adiw ZL,1 ; Point to high
Byte of Word
lpm ; get Pagesize to R0
mov Pagewords,r0
mov Bcnt3,Pagewords ; initiate Counter
spa_end:
ret

;
***************************************************************************
;*
;* FUNCTION
;* set_pollcode
;*
;* DESCRIPTION
;* sets Code for Polling Flash for selected Device.
;*
;
***************************************************************************

set_pollcode:
lpm ; read table
tst r0 ; check for end of
table
breq spo_end ; no Pollcode to set
cp device,r0
breq spo_set ; C=0
adiw ZL,2 ; skip MSB
rjmp set_pollcode
spo_set:
adiw ZL,1 ; Point to high
Byte of Word
lpm ; get Pagesize to R0
mov PollcodeF,r0 ; Set Pollcode for
Flash Rom
spo_end:
ret

;
***************************************************************************
;*
;* FUNCTION
;* delay
;*
;* DESCRIPTION
;* Make delay 1mS (x temp1).
;*
;
***************************************************************************

delay:
ldi temp2,40
dl2: ldi temp3,(XTAL/120)
dl1: dec temp3
brne dl1
dec temp2
brne dl2
dec temp1
brne delay
ret

;
***************************************************************************
;*
;* FUNCTION
;* spi123
;*
;* DESCRIPTION
;* Write bytes 1 to 3 on the SPI. Byte 1 must be
loadet into s_data
;* Byte 2 ist addrh, Byte 3 ist addrl
;*
;
***************************************************************************

spi123:
rcall wrser ; wrser(s_data) SPI
write (byte 1)
mov s_data,addrh
rcall wrser ; wrser(addrh) SPI
write (byte 2)
mov s_data,addrl
rcall wrser ; wrser(addrl) SPI
write (byte 3)
ret

;
***************************************************************************
;*
;* FUNCTION
;* w1234 (for Code simplification, not used yet)
;*
;* DESCRIPTION
;* Write SPI bytes 1 to 4.
; Byte 1 must be loadet into cmd1
; Byte 2 must be loadet into cmd2
; Byte 3 must be loadet into cmd3
; Byte 4 must be loadet into u_data
;*
;
***************************************************************************
w1234:
mov s_data,cmd1
rcall wrser
mov s_data,cmd2
rcall wrser
mov s_data,cmd3
rcall wrser
mov s_data,u_data
rcall wrser
ret

;
***************************************************************************
;*

http://avr-asm.tripod.com/isp2313.html (1 of 4)1/20/2009 8:58:51 PM

16 BIT MATH (AVR 202)

;* FUNCTION
;* w123r4 (for Code simplification, not used yet)
;*
;* DESCRIPTION
;* Write SPI bytes 1 to 3, read Byte 4 to serial.
; Byte 1 must be loadet into cmd1
; Byte 2 must be loadet into cmd2
; Byte 3 must be loadet into cmd3
;*
;
***************************************************************************
w123r4:
mov s_data,cmd1
rcall wrser
mov s_data,cmd2
rcall wrser
mov s_data,cmd3
rcall wrser
rcall rdser
mov u_data,s_data
rcall wrser ; get Byte 4 from
serial
rcall putc
ret

;
***************************************************************************
;*
;* FUNCTION
;* rdser, wrser
;*
;* DESCRIPTION
;* Write and read bytes on the SPI.
;*
;
***************************************************************************

rdser:
clr s_data
wrser:
ldi temp1,8 ; load bit counter
ldi rd_s_data,0
wrs0:
rol s_data
brcc wrs1
set_MOSI ; MOSI = 1
rjmp wrs2
wrs1:
clr_MOSI ; MOSI = 0
wrs2:
lsl rd_s_data
sbic_MISO ; read MISO
ori rd_s_data,1
pulse_SCK ; pulse SCK
dec temp1 ; advance bit
counter
brne wrs0 ; loop
mov s_data,rd_s_data
ret

;
***************************************************************************
;*
;* FUNCTION
;* read_send_progmem
;*
;* DESCRIPTION
;* Read one adress (2 Byte) from Program Memory and
send it through UART
;*
;
***************************************************************************
read_send_progmem:
tst device
brmi rsp1 ; S89 device
ldi s_data,0x20 ; read low Byte
rcall wrser ; wrser(0x28) SPI
write (byte 1)
mov s_data,addrh
rjmp rsp2
rsp1:
mov s_data,addrh ; s_data = (addrh
&lt;&lt; 3) | 0x01;
rcall shift_s_data3
ori s_data,0x01
rsp2:
rcall wrser ; wrser(addrh) SPI
write (byte 2) (S89=byte1)
mov s_data,addrl
rcall wrser ; wrser(addrl) SPI
write (byte 3)
rcall rdser ; SPI
read (byte 4)
mov u_data,s_data
rcall putc ; send data
tst device
brmi rsp3 ; S89 device
ldi s_data,0x28 ; read High
Byte
rcall wrser ; wrser(0x20) SPI
write (byte 1)
mov s_data,addrh
rcall wrser ; wrser(addrh) SPI
write (byte 2)
mov s_data,addrl
rcall wrser ; wrser(addrl) SPI
write (byte 3)
rcall rdser ; SPI
read (byte 4)
mov u_data,s_data
rcall putc ; send data
rsp3:
adiw addrl,1 ; Auto increment
address
ret

;
***************************************************************************
;*
;* FUNCTION
;* read_send_datamem
;*
;* DESCRIPTION
;* Read one Byte from Data Memory (eeprom) and send
it through UART
;*
;
***************************************************************************
read_send_datamem: ; Subroutine to
read one eeprom Address
tst device
brmi rsd1 ; S89 device
ldi s_data,0xa0
rcall wrser ; wrser(0xa0) SPI
write (byte 1)
mov s_data,addrh
rjmp rsd2
rsd1:
cpi device,0x87 ; if (device == S53)
breq rsd3 ; no Support for
89S53 device due to Bug in AVRProg V1.37
mov s_data,addrh
rcall shift_s_data3
ori s_data,0x05
rsd2:
rcall wrser ; wrser(addrh) SPI
write (byte 2)
mov s_data,addrl
rcall wrser ; wrser(addrl) SPI
write (byte 3)
rcall rdser ; SPI
read (byte 4)
mov u_data,s_data
rcall putc ; send data
adiw addrl,1 ; Auto increment
address
ret
rsd3:
pop temp1 ; remove return
Adress from Stack in case of Error
pop temp1
rjmp put_err

;
***************************************************************************
;*
;* FUNCTION
;* eeprom_write
;*
;* DESCRIPTION
;* Write u_data to Data Memory (eeprom)
;*
;
***************************************************************************
eeprom_write:
tst device
brmi eew1 ; S89 device
ldi s_data,0xc0
rcall wrser ; wrser(0xc0) SPI
write (byte 1)
mov s_data,addrh
rjmp eew2
eew1:
cpi device,0x87 ; if (device == S53)
breq eew3
mov s_data,addrh
rcall shift_s_data3
ori s_data,0x06
eew2:
rcall wrser ; wrser(addrh) SPI
write (byte 2)
mov s_data,addrl
rcall wrser ; wrser(addrl) SPI
write (byte 3)
mov s_data,u_data
rcall wrser ; wrser(u_data) SPI
write (byte 4)
ldi temp1,10 ; delay 10mS
rcall delay

adiw addrl,1 ; Auto increment

address
ret
eew3:
pop temp1 ; remove return
Adress from Stack in case of failure
pop temp1
rjmp put_err

;
***************************************************************************
;*
;* FUNCTION
;* shift_s_data3
;*
;* DESCRIPTION
;* Shift s_data 3 times left for S89 device.
;*
;
***************************************************************************

shift_s_data3:
lsl s_data
lsl s_data
lsl s_data
brcc s3_ret
cpi device,0x87 ; if (device != S53)
brne s3_ret
sbr s_data, 4 ; a13 +
s3_ret: ret

;
***************************************************************************
;*
;* FUNCTION
;* healthcheck
;*
;* DESCRIPTION
;* changes color of dual color led.
;*
;
***************************************************************************

healthcheck: ; for dual

color LED
clr_LED ; LED red
ldi temp1,200 ; 200 ms
rcall delay
ldi temp1,200 ; again 200 ms
rcall delay
ldi s_data,200 ; counter Register

LEDloop: ; Pulse for yellow

LED
set_LED ; LED green
ldi temp1,2 ; 2 ms
rcall delay
clr_LED ; LED red
ldi temp1,1 ; 1 ms
rcall delay
dec s_data ; dec. counter
brne LEDloop
set_LED ; LED green
ret

;
***************************************************************************
;
***************************************************************************
;
***************************************************************************
;*
;* INIT
;*
;* DESCRIPTION
;* Initialization
;*
;
***************************************************************************
;
***************************************************************************
;
***************************************************************************

INIT:
ldi temp1,RAMEND
out SPL,temp1 ; Locate stack
ldi temp1,PAGESIZE ; default Pagesize
mov Pagewords,temp1
mov Bcnt3,Pagewords ; set counter for
Pagesize
ldi device,0x20 ; S2313 as default
clr B_Mode ; Flag for Block
Modes (see Note 16)
clr B_Flag ; Flag for eNhanced
Block write
init_ports ; Initialize ports
release_ports ; Release ports
rcall u_init ; Initialize UART
rcall healthcheck ; show that Prog is
working after Powerup (LED test)

;
***************************************************************************
;*
;* PROGRAM
;* waitcmd -&gt; main
;*
;* DESCRIPTION
;* Wait for and execute commands.
;*
;
***************************************************************************

waitcmd:
rcall getc ; while (getc() ==
ESC) {};
cpi u_data,0x1b
breq waitcmd

;====== 'T' - Device Type

==================================================

cpi u_data,'T' ; 'T' Device type

brne w0
rcall getc
mov device,u_data ; get device type
table Dev_M ; prepare to set
Pagesize
rcall set_pagesize ; If device has
Page Mode support, set Pagesize
ldi temp1,0xFF
mov PollcodeF,temp1 ; preset PollcodeF
with 0xFF, will be overwritten if Pollcode known
table Dev_S ; prepare to set
Polling Code
rcall set_pollcode ; If device has no
Page Size support, set code for Polling Flash
rjmp put_ret

;====== 'S' - Return Software Identifier

===================================

w0:
cpi u_data,'S' ; 'S' Return
software identifier
brne w1
table ID_Str
rcall put_string ; put string "AVR
ISP"
rjmp waitcmd

;====== 'V' - Return Software Version

======================================

w1:
cpi u_data,'V' ; 'V' Return
software version
brne w2
table SW_Ver
rcall put_string ; put software
version
rjmp waitcmd

;====== 'v' - Return Hardware Version

======================================

w2:
cpi u_data,'v' ; 'v' Return
hardware version
brne w3
table HW_Ver
rcall put_string ; put hardware
version
rjmp waitcmd

;====== 't' - Show Supported Devices

=======================================

w3:
cpi u_data,'t' ; 't' Show
supported devices
brne w4
table Dev_S
rcall put_table ; put supported
devices codes
table Dev_M
rcall put_table ; put supported
devices codes
ldi u_data,0x00 ; putc(0x00) - end
of device list
rcall putc
rjmp waitcmd

;====== 'p' - Return Programmer Type

=======================================

w4:
cpi u_data,'p' ; 'p' Return
programmer type
brne w5
ldi u_data,'S' ; putc('S') -
serial programmer
rcall putc
rjmp waitcmd

;====== 'a' - Return autoincrement address support

=========================

w5:
cpi u_data,'a' ; 'a' Return
address auto increment
brne w51
ldi u_data,'Y' ; putc('Y') -
supports autoinc
rcall putc
rjmp waitcmd

;====== 'M' - Return enhanced Mode support (Note 14)

========================

w51:
; cpi u_data,'M' ; 'M' Return
enhanced mode Support
; brne w52
; ldi u_data,'Y' ; putc('Y') -
supports enhanced Mode
; rcall putc
; rjmp waitcmd

;====== 'i' - Return Chip ID (Note 14)

======================================

w52:
cpi u_data,'i' ; 'i' Return Chip ID
brne w53
table ChipID
rcall put_string ; put Chip ID
string
ldi u_data,0x0a ; putc(LF)
rcall putc
rjmp put_ret

;====== 'b' - Return Block write Mode support (Note 17)

========================

w53:
cpi u_data,'b' ; 'b' Return
enhanced mode Support
brne w6
ldi u_data,'Y' ; putc('Y') -
supports enhanced Mode
rcall putc
ldi u_data,high(BUFSIZE) ; putc((BUFSIZE&gt;
&gt;8) &amp; 0xff);
rcall putc
ldi u_data,low(BUFSIZE) ; putc
(BUFSIZE&amp;0xff);
rcall putc
rjmp waitcmd

;====== 'x' - Set LED

======================================================

w6:
cpi u_data,'x' ; 'x' Set LED (LED
off or green)
brne w61
rcall getc ; get parameter
set_LED
rjmp put_ret

;====== 'y' - Clear LED

====================================================

w61:
cpi u_data,'y' ; 'y' Clear LED
(LED on or red)
brne w7
rcall getc ; get parameter
clr_LED
rjmp put_ret

;
===========================================================================

; We require that the device code be selected before

any of the other commands

w7:
table Dev_S ; load pointer
rcall bel_table
brcc w71 ; device belongs to
table
table Dev_M
rcall bel_table
brcc w71 ; device belongs to
table
rjmp put_err ; not match, goto
put_err();

;====== 'P' - Enter Programming Mode

=======================================

w71:
cpi u_data,'P' ; 'P' Enter
programming mode
breq w70
rjmp w8
w70:
clr_LED ; LED on
catch_ports ; catch ports
clr_SCK ; clear SCK
pas_RESET ; set RESET passive
ldi temp1,50 ; delay 50mS;
rcall delay
act_RESET ; set RESET active
ldi temp1,50 ; delay 50mS;
rcall delay
ldi s_data,0xac
rcall wrser ; wrser(0xac) SPI
write (byte 1)
ldi s_data,0x53
rcall wrser ; wrser(0x53) SPI
write (byte 2)
; SPI
Synchronization (fix!)
cpi device,0x20 ; if ( (device &gt;
= 0x20) &amp;&amp; (device &lt;= 0x7F) )
brlo s2
tst device
brmi s2
ldi temp3,32 ; count = 32;
s1: rcall rdser ; SPI read (byte 3)
cpi s_data,0x53 ; if (rdser == 0x53)
breq s3 ; break
ldi
s_data,0x00
rcall wrser ; wrser(0x00) SPI
write (byte 4)
pulse_SCK ; pulse SCK
ldi s_data,0xac
rcall wrser ; wrser(0xac) SPI
write (byte 1)
ldi s_data,0x53
rcall wrser ; wrser(0x53) SPI
write (byte 2)
dec temp3 ; count-1
brne s1 ; loop
rjmp s3 ; else
s2: ldi s_data,0x00
rcall wrser ; wrser(0x00) SPI
write (byte 3)
s3: tst device
brmi s4 ; S89 device
ldi s_data,0x00
rcall wrser ; wrser(0x00) SPI
write (byte 4)
s4: ldi temp1,4 ; delay 4mS;
rcall delay
rjmp put_ret

;====== 'c' - Write Program Memory, Low Byte

===============================

w8:
cpi u_data,'c' ; 'c' Write program
memory, low byte
brne w9
rcall getc ; get data byte
w8b: ldi s_data,0x40
mov pol_cmd,s_data ; save command for
polling
tst device
brmi w81 ; S89 device
rcall wrser ; wrser(0x40) SPI
write (byte 1)
mov s_data,addrh
rjmp w82
w81:
mov s_data,addrh ; s_data = (addrh
&lt;&lt; 3) | 0x02;
rcall shift_s_data3
ori s_data,0x02
w82:
rcall wrser ; wrser(addrh) SPI
write (byte 2)
mov s_data,addrl
rcall wrser ; wrser(addrl) SPI
write (byte 3)
mov s_data,u_data
rcall wrser ; wrser(u_data) SPI
write (byte 4)
mov p_data,u_data ; save data for
polling
mov pol_al,addrl ; save address for
polling
mov pol_ah,addrh
tst device
brpl w83
adiw addrl,1 ; Auto increment
address for S89 device
w83:
rjmp wait_S ; write FLASH delay

;====== 'C' - Write Program Memory, High Byte

==============================

w9:
cpi u_data,'C' ; 'C' Write program
memory, high byte
brne w92
rcall getc ; get data byte
w9a: tst device
brmi w91 ; S89 device
ldi s_data,0x48
mov pol_cmd,s_data ; save command for
polling
rcall wrser ; wrser(0x48) SPI
write (byte 1)
mov s_data,addrh
rcall wrser ; wrser(addrh) SPI
write (byte 2)
mov s_data,addrl
rcall wrser ; wrser(addrl) SPI
write (byte 3)
mov s_data,u_data ; wrser(u_data) SPI
write (byte 4)
rcall wrser
mov p_data,u_data ; save data for
polling
mov pol_al,addrl ; save address for
polling
mov pol_ah,addrh
adiw addrl,1 ; Auto increment
address
rjmp wait_S ; write FLASH delay
w91:
rjmp put_err ; S89 device have
byte wide program memory!

;====== 'B' Block Write Memory (see Note 17)

======================

w92:
cpi u_data,'B' ; 'B' Block Write
Program Memory
breq w92a
rjmp w10
w92a:
rcall getc ; get count High
Byte
tst u_data
breq w92b
ldi u_data,1
rjmp put_err
w92b:
rcall getc ; get count Low Byte
cpi u_data,BUFSIZE+1 ; check maximum
count
brlo w92c
ldi u_data,2
rjmp put_err
w92c:
mov Bcnt1, u_data ; ignore BUFSIZE
high Byte (must be 0 here)
mov Bcnt2, u_data
rcall getc ; get Memory type
to write
mov Memtype,u_data ; Flag for Memtype
clr XH
ldi XL, RAMSTART ; set X pointer to
SRAM begin
w93:
rcall getc ; get data until
Bcnt1 is reached
st X+, u_data ; store data to SRAM
dec Bcnt1
brne w93
clr XH
ldi XL, RAMSTART ; set X pointer to
SRAM begin
ldi temp3,1
mov B_Mode,temp3 ; B_Mode != 0
mov u_data,Memtype ; restore Memtype
cpi u_data,'F' ; 'F' Flash Memory
ist to write
breq w94a
cpi u_data,'E' ; 'E' eeprom Memory
ist to write
breq w94 ; Entry Point for
Data Memory Block write
ldi u_data,3
rjmp put_err

w94: ; write
Data Memory
ld u_data,X+
rcall eeprom_write
dec Bcnt2
brne w94
rjmp put_ret

;Entry Point for Flash Block write

w94a:
table Dev_M
rcall bel_table
brcc w95 ; device belongs to
table
rjmp w96 ; not match, goto
"non Paged" Mode
w95: ; Entry
Point for AVRProg Block Flash write
ldi s_data,0x40 ; write low byte
rcall spi123
ld s_data, X+
rcall wrser ; wrser(s_data) SPI
write (byte 4)
ldi s_data,0x48 ; write high byte
mov pol_cmd,s_data ; save command for
polling
rcall spi123
ld s_data, X+
mov p_data,s_data ; save data for
polling
mov pol_al,addrl ; save address for
polling
mov pol_ah,addrh
rcall wrser ; wrser(u_data) SPI
write (byte 4)
adiw addrl,1 ; Auto increment
address
dec Bcnt2
breq w95b
dec Bcnt2
breq w95b
tst B_Mode
breq w95 ; Loop for "Block
Mode Commands" see Note 16
dec Bcnt3 ; count Bytes for
Pagesize
brne w95
w95b:
tst B_Mode
brne w95c
rjmp put_ret
w95c:
dec Bcnt3 ; Bcnt3 will be set
correct after write
ldi s_data,0x4c ; write Memory Page
rcall wrser ; wrser(0x4c) SPI
write (byte 1)
mov s_data,pol_ah ; last written
Adress is in Page to be programmed!
rcall wrser ; wrser(addrh) SPI
write (byte 2)
mov s_data,pol_al ; last written
Adress is in Page to be programmed!
rcall wrser ; wrser(addrl) SPI
write (byte 3)
ldi s_data,0x00
rcall wrser ; wrser(0x00) SPI
write (byte 4)
mov Bcnt3,Pagewords ; reload Counter
für Pagesize
rjmp wait_M

;#@KL4 test for 89S8252 Device

w96: ; Non Page
Mode Flash write
tst device
brmi w96b ; S89 device
ld p_data, X+ ; load byte to Poll
data
cpi p_data,0xFF ; if (p_data ==
0xFF)
breq w961 ; skip burning
ldi s_data,0x40 ; write low byte
mov pol_cmd,s_data ; save command for
polling
rcall spi123
mov s_data,p_data ; reload data from
Poll data
rcall wrser ; wrser(s_data) SPI
write (byte 4)
mov pol_al,addrl ; save address for
polling
mov pol_ah,addrh
rcall Bws_pol
w961:
dec Bcnt2
ld p_data, X+ ; load byte to Poll
data
cpi p_data,0xFF ; if (p_data ==
0xFF)
breq w962
ldi s_data,0x48 ; write high byte
mov pol_cmd,s_data ; save command for
polling
rcall spi123
mov s_data,p_data ; reload data from
Poll data
rcall wrser ; wrser(u_data) SPI
write (byte 4)
w96a: mov pol_al,addrl ; save
address for polling
mov pol_ah,addrh
rcall Bws_pol
w962:
adiw addrl,1 ; Auto increment
address
dec Bcnt2
brne w96
rjmp put_ret ; reply

w96b: ; Code for

89S8252
; ldi s_data,0x40
; mov pol_cmd,s_data ; save command for
polling
mov s_data,addrh ; s_data = (addrh
&lt;&lt; 3) | 0x02;
rcall shift_s_data3
ori s_data,0x02
rcall wrser ; wrser(addrh) SPI
write (byte 1)
mov s_data,addrl
rcall wrser ; wrser(addrl) SPI
write (byte 2)
ld s_data, X+
mov p_data,s_data ; save data for
polling
rcall wrser ; wrser(u_data) SPI
write (byte 3)
rjmp w96a

;====== 'R' - Read Program Memory

==========================================

w10:
cpi u_data,'R' ; 'R' Read program
memory
brne w10B
tst device
brmi rpm1 ; S89 device
ldi s_data,0x28 ; read high
Byte (order is different from Block Read!)
rcall wrser ; wrser(0x28) SPI
write (byte 1)
mov s_data,addrh
rjmp rpm2
rpm1:
mov s_data,addrh ; s_data = (addrh
&lt;&lt; 3) | 0x01;
rcall shift_s_data3
ori s_data,0x01
rpm2:
rcall wrser ; wrser(addrh) SPI
write (byte 2)
mov s_data,addrl
rcall wrser ; wrser(addrl) SPI
write (byte 3)
rcall rdser ; SPI
read (byte 4)
mov u_data,s_data
rcall putc ; send data
tst device
brmi rpm3 ; S89 device
ldi s_data,0x20 ; read Low
Byte
rcall wrser ; wrser(0x20) SPI
write (byte 1)
mov s_data,addrh
rcall wrser ; wrser(addrh) SPI
write (byte 2)
mov s_data,addrl
rcall wrser ; wrser(addrl) SPI
write (byte 3)
rcall rdser ; SPI
read (byte 4)
mov u_data,s_data
rcall putc ; send data
rpm3:
adiw addrl,1 ; Auto increment
address
rjmp waitcmd ; goto waitcmd();

;====== 'g' - Block Read Memory (See Note 17)

======================

w10B:
cpi u_data,'g' ; 'g' Block Read
Program Memory
brne w11
rcall getc ; XH = getc();
mov XH,u_data
rcall getc ; XL = getc();
mov XL,u_data
rcall getc ; getc(Memorytype);
cpi u_data,'F'
breq w10B2
cpi u_data,'E'
breq w10B1
rjmp put_err
w10B1:
rcall read_send_datamem
sbiw XL, 1
brne w10B1
rjmp waitcmd ; goto waitcmd();

w10B2:
rcall read_send_progmem
tst device

http://avr-asm.tripod.com/isp2313.html (2 of 4)1/20/2009 8:58:51 PM

16 BIT MATH (AVR 202)

brmi w10B3
sbiw XL, 2
brne w10B2
rjmp waitcmd
w10B3:
sbiw XL, 1
brne w10B2
rjmp waitcmd ; goto waitcmd();

;====== 'A' - Load Address

=================================================

w11:
cpi u_data,'A' ; 'A' Load address
brne w12
rcall getc ; addrh = getc();
mov addrh,u_data
rcall getc ; addrl = getc();
mov addrl,u_data
rjmp put_ret ; goto reply();

;====== 'D' - Write Data Memory

============================================

w12:
cpi u_data,'D' ; 'D' Write data
memory
brne w13
rcall getc ; get data
rcall eeprom_write
rjmp put_ret

;====== 'd' - Read Data Memory

=============================================

w13:
cpi u_data,'d' ; 'd' Read data
memory
brne w14
rcall read_send_datamem
rjmp waitcmd ; goto waitcmd();

;====== 'L' - Leave Programming Mode

=======================================

w14:
cpi u_data,'L' ; 'L' Leave
programming mode
brne w142
w141:
pas_RESET ; set RESET passive
release_ports ; release ports
set_LED ; LED off
rjmp put_ret

;====== 'E' - Exit , release all Ports, inhibit AVR910

=====================

w142:
cpi u_data,'E' ; 'E' xit
brne w15
rjmp w141 ; exit command for
AVR Prog

;====== 'e' - Chip Erase

===================================================

w15:
cpi u_data,'e' ; 'e' Chip erase
brne w16
ldi s_data,0xac
rcall wrser ; wrser(0xac) SPI
write (byte 1)
tst device
brmi w151 ; S89 device
ldi s_data,0x80
rcall wrser ; wrser(0x80) SPI
write (byte 2)
w151:
ldi s_data,0x04
rcall wrser ; wrser(0x04) SPI
write (byte 3)
ldi s_data,0x00
rcall wrser ; wrser(0x00) SPI
write (byte 4)
ldi temp1,40 ; delay 40mS
rcall delay
rjmp put_ret

;====== 'l' - Write Lock Bits

==============================================
; Some more different Adresses for other devices?
w16:
cpi u_data,'l' ; 'l' Write lock
bits
brne w17
rcall getc ; get data
ldi s_data,0xac
rcall wrser ; wrser(0xac) SPI
write (byte 1)
tst device
brmi w161 ; S89 device
cpi device,0x5e ; if (device ==
tn26)
breq w163
mov s_data,u_data
andi s_data,0x06 ; (u_data &amp;
0x06) | 0xe0
ori s_data,0xe0
rcall wrser ; wrser(u_data) SPI
write (byte 2)
ldi s_data,0x00
rcall wrser ; wrser(0x00) SPI
write (byte 3)
rjmp w162
w163:
ldi s_data,0xe0 ; tn26 device
rcall wrser ; wrser(0xe0) SPI
write (byte 2)
ldi s_data,0x00
rcall wrser ; wrser(0x00) SPI
write (byte 3)
mov s_data,u_data
ori s_data,0xfc
rcall wrser ; wrser(u_data) SPI
write (byte 4)
rjmp w164
w161:
mov s_data,u_data
andi s_data,0xe0 ; S89 device
ori s_data,0x07
rcall wrser
w162:
ldi s_data,0x00
rcall wrser ; wrser(0x00) SPI
write (byte 4)
w164:
ldi temp1,10 ; delay 10mS
rcall delay
rjmp put_ret

;====== 's' - Read Signature Bytes

=========================================

w17:
cpi u_data,'s' ; 's' Read
signature bytes
brne w18
tst device
brmi w171 ; S89 device
ldi param1,0x02 ; param1 = 0x02
rcall ca17
ldi param1,0x01 ; param1 = 0x01
rcall ca17
ldi param1,0x00 ; param1 = 0x00
rcall ca17
rjmp waitcmd
w171:
rjmp put_err
ca17:
ldi s_data,0x30
rcall wrser ; wrser(0x30) SPI
write (byte 1)
ldi s_data,0x00
rcall wrser ; wrser(0x00) SPI
write (byte 2)
mov s_data,param1
rcall wrser ; wrser(param1) SPI
write (byte 3)
rcall rdser ; SPI
read (byte 4)
mov u_data,s_data
rcall putc ; send data
ret

;====== 'm' - Write Program Memory Page

====================================

w18:
cpi u_data,'m' ; 'm' Write Program
Memory Page
brne w19
ldi s_data,0x4c
rcall wrser ; wrser(0x4c) SPI
write (byte 1)
; mov s_data,addrh ; original, reload
address
mov s_data,pol_ah ; for speeding up
transfer
rcall wrser ; wrser(addrh) SPI
write (byte 2)
; mov s_data,addrl ; original, reload
address
mov s_data,pol_al ; for speeding up
transfer
rcall wrser ; wrser(addrl) SPI
write (byte 3)
ldi s_data,0x00
rcall wrser ; wrser(0x00) SPI
write (byte 4)
rjmp wait_M ; write FLASH delay

;====== ':' - Universal Command

============================================

w19:
cpi u_data,':' ; ':' Universal
Command
brne w20
rcall getc ; get data1
mov cmd1,u_data ; cmd1 = data1
rcall getc ; get data2
mov cmd2,u_data ; cmd2 = data2
rcall getc ; get data3
mov cmd3,u_data ; cmd3 = data3
mov s_data,cmd1
rcall wrser ; wrser(cmd1) SPI
write (byte 1)
mov s_data,cmd2
rcall wrser ; wrser(cmd2) SPI
write (byte 2)
mov s_data,cmd3
rcall wrser ; wrser(cmd3) SPI
write (byte 3)
rcall rdser ; SPI
read (byte 4)
mov u_data,s_data
rcall putc ; send data
ldi temp1,50 ; delay 50mS
rcall delay
rjmp put_ret

;====== '.' - New Universal Command

========================================

w20:
cpi u_data,'.' ; '.' New Universal
Command
brne w21
rcall getc ; get data1
mov cmd1,u_data ; cmd1 =
data1
rcall getc ; get data2
mov cmd2,u_data ; cmd2 =
data2
rcall getc ; get data3
mov cmd3,u_data ; cmd3 =
data3
rcall getc ; get data4
mov s_data,cmd1
rcall wrser ; wrser(cmd1) SPI
write (byte 1)
mov s_data,cmd2
rcall wrser ; wrser(cmd2) SPI
write (byte 2)
mov s_data,cmd3
rcall wrser ; wrser(cmd3) SPI
write (byte 3)
mov s_data,u_data
rcall wrser ; wrser(u_data) SPI
write (byte 4)
mov u_data,rd_s_data
rcall putc ; send data
ldi temp1,50 ; delay 50mS
rcall delay
rjmp put_ret

;====== 'r' - Read Lock Bits

==============================================

w21:
cpi u_data,'r' ; 'r' Read lock bits
brne w30
ldi s_data,0x58
rcall wrser ; wrser(0x58) SPI
write (byte 1)
; ldi s_data,0x00
clr s_data
rcall wrser ; wrser(0x00) SPI
write (byte 2)
; ldi s_data,0x00
rcall wrser ; wrser(0x00) SPI
write (byte 3)
rcall rdser ; SPI
read (byte 4)
mov u_data,s_data
rcall putc ; send data
rjmp put_ret

;====== Unknown Command

====================================================

w30: rjmp put_err

;====== Wait for FLASH write in avr910 mode

==================================

wait_S:
table Dev_M
rcall bel_table
brcs ws_pol ; No Page Mode,
poll last Byte
rjmp put_ret ; in Byte Mode time
is long enougt to get next Byte...
Bws_pol: ; entry adress for
Block mode delay
ldi temp3,1
mov B_Flag,temp3 ; set Flag that
ws_poll comes back with ret ...

ws_pol:
tst PollcodeF ; if polling not
applicable, standart delay
breq ws_del ; polling not used
ws_def:
cp p_data,PollcodeF ; if (data ==
PollcodeF)
breq ws_del ; wait default delay
andi pol_cmd,0x0f ; write command:
0x48, 0x40
ori pol_cmd,0x20 ; read command:
0x28, 0x20
clr temp3 ; clear polling
counter
ws_cy:
tst device
brmi ws_89 ; S89 device
mov s_data,pol_cmd
rcall wrser ; wrser(pol_cmd)
SPI write (byte 1)
mov s_data,pol_ah
rjmp ws_90
ws_89:
mov s_data,pol_ah ; s_data = (pol_ah
&lt;&lt; 3) | 0x01;
rcall shift_s_data3
ori s_data,0x01
ws_90:
rcall wrser ; wrser(pol_ah) SPI
write (byte 2) (S89=byte1)
mov s_data,pol_al
rcall wrser ; wrser(pol_al) SPI
write (byte 3) (S89=byte2)
rcall rdser ; SPI
read (byte 4) (S89=byte3)
tst device
brpl ws_cb
andi s_data,0x80 ; compare only MSB
for S89 device
andi p_data,0x80
ws_cb:
cp s_data,p_data
breq ws_ok ; s_data = p_data
dec temp3
brne ws_cy ; loop
ws_del: ; 256
polling cycles are over, give additional standart Time
ldi temp1,10 ; delay 10mS
rcall delay
ws_ok:
tst B_Flag
breq put_ret
clr B_Flag ; Reset B_Flag for
normal operation
ret

;====== Wait for FLASH write in page mode

==================================

wait_M:
cpi device,0x41
breq wm_del ; polling
inapplicable for m103
cpi device,0x23
breq poll_t2313 ; polling different
for t2313
cpi p_data, 0xFF ; if last Byte was
0xFF give standart delay
breq wm_del
andi pol_cmd,0x0f ; write command:
0x48, 0x40
ori pol_cmd,0x20 ; read command:
0x28, 0x20
clr temp3 ; clear polling
counter
wm_cy:
mov s_data,pol_cmd
rcall wrser ; wrser(pol_cmd)
SPI write (byte 1)
mov s_data,pol_ah
rcall wrser ; wrser(pol_ah) SPI
write (byte 2)
mov s_data,pol_al
rcall wrser ; wrser(pol_al) SPI
write (byte 3)
rcall rdser ; SPI
read (byte 4)
cp s_data,p_data
breq wm_ok ; s_data = p_data
dec temp3
breq wm_del ; 256 polling
cycles are over, give another 50ms delay...
rjmp wm_cy ; loop
wm_del:
ldi temp1,50 ; delay 50mS
rcall delay
wm_ok:
tst B_Mode
breq wm_end
tst Bcnt2
breq wm_end
rjmp w95
wm_end:
clr B_Mode ; Reset Block Mode
Flag
rjmp put_ret

poll_t2313: ; Polling
ATTiny2313 is different
ldi pol_cmd,0xf0 ; Byte1= 0xF0
clr temp3 ; clear polling
counter
mov pol_ah,temp3 ; Byte2= 0x00
p2313_1:
mov s_data,pol_cmd
rcall wrser ; wrser(pol_cmd)
SPI write (byte 1)
mov s_data,pol_ah
rcall wrser ; wrser(pol_ah) SPI
write (byte 2)
mov s_data,pol_al
rcall wrser ; wrser(pol_al) SPI
write (byte 3)
rcall rdser ; SPI
read (byte 4)
andi s_data,0x01 ; last Bit tells if
polling OK
breq wm_ok ; s_data = p_data
dec temp3
breq wm_del ; 256 polling
cycles are over, give another 50ms delay...
rjmp p2313_1 ; loop

;====== Command Error

======================================================

put_debug: ; shows u_data on

serial for debug reason
rcall putc
put_err:
ldi u_data,'?' ; putc('?')
rcall putc ; send '?'
rjmp waitcmd

;====== Reply Command

======================================================

put_ret:
ldi u_data,0x0d ; putc(0x0D)
rcall putc ; send CR
rjmp waitcmd

;
***************************************************************************
;*
;* TABLE
;* device codes
;*
;* DESCRIPTION
;* The following device codes must be used by the host
computer. Note
;* that the device codes are arbitrary selected, they
do not have any
;* thing in common with the signature bytes stored in
the device.
;* This are the device Codes recognized by the AVRprog
Software. Some
;* Devices may require special hardware or a
different, not yet
;* implemented Protocol! Use at your own risk.
;*
;
***************************************************************************

Dev_S: ; byte write

; avr910-devcode ,Code during polling Flash.
0x00: no polling supported, program default time
; .db 0x10 ,0x00 ;AT90S1200A No support for
this type
; .db 0x11 ,0x00 ;AT90S1200B No support for
this type
; .db 0x12 ,0x00 ;AT90S1200C No support for
this type
.db 0x13 ,0x00 ;AT90S1200
.db 0x20 ,0x7F ;AT90S2313A
.db 0x28 ,0x7F ;AT90S4414A
.db 0x30 ,0xFF ;AT90S4433A
.db 0x34 ,0xFF ;AT90S2333A
.db 0x38 ,0x7F ;AT90S8515A
.db 0x48 ,0xFF ;AT90S2323A
.db 0x4C ,0xFF ;AT90S2343A
.db 0x51 ,0xFF ;tn10
.db 0x55 ,0xFF ;tn12
.db 0x56 ,0xFF ;tn15
.db 0x68 ,0xFF ;AT90S8535
.db 0x6C ,0xFF ;AT90S4434
.db 0x86 ,0xFF ;AT89S8252 bug in avrprog
in Block write Mode!(See Note 18 for Workaround)
.db 0x87 ,0xFF ;AT89S53 bug in avrprog
.dw 0 ;End of table

Dev_M: ; Devices which support Page Programming.

Dont forget the Page Size of different Devices.
; Maximum ist 0x40 due to limitated RAM in 2313
Chip. (Pages with bigger Pages are programmed multiple times)
; avr910-devcode ,Pagesite in Words
.db 0x23 ,0x10 ;tn2313 avr910-Devicecode
not official (STK500 Code used, avrdude.conf modification!)
.db 0x3a ,0x20 ;m8515, Pagesize 32 words
(0x20)
.db 0x3b ,0x20 ;m8515boot Bootloader Mode
untested!
.db 0x41 ,0x40 ;m103
.db 0x43 ,0x40 ;m128
.db 0x44 ,0x40 ;m128boot Bootloader Mode
untested!
.db 0x45 ,0x40 ;m64
.db 0x46 ,0x40 ;m64boot Bootloader Mode
untested!
.db 0x5E ,0x10 ;tn26
.db 0x60 ,0x40 ;m161
.db 0x61 ,0x40 ;m161boot Bootloader Mode
untested!
.db 0x62 ,0x40 ;m162
.db 0x63 ,0x40 ;m162boot Bootloader Mode
untested!
.db 0x64 ,0x40 ;m163
.db 0x66 ,0x40 ;m163boot Bootloader Mode
untested!
.db 0x69 ,0x20 ;m8535
.db 0x6a ,0x20 ;m8535boot Bootloader Mode
untested!
.db 0x72 ,0x40 ;m32
.db 0x73 ,0x40 ;m32boot Bootloader Mode
untested!
.db 0x74 ,0x40 ;m16
.db 0x75 ,0x40 ;m16boot Bootloader Mode
untested!
.db 0x76 ,0x20 ;m8
.db 0x77 ,0x20 ;m8boot Bootloader Mode
untested!
.db 0x78 ,0x40 ;m169
.db 0x79 ,0x40 ;m169boot Bootloader Mode
untested!
.db 0x65 ,0x20 ;m83 obsolete
.db 0x67 ,0x20 ;m83boot obsolete
.db 0x42 ,0x40 ;m603 obsolete
.dw 0 ;End of Table

; Devices with known avr910 Devicecodes, but not

supported with this Programmer
; .db 0x50 ;tn11 Needs additional High
Voltage Hardware and uses different Protocoll! No Support!
; .db 0x58 ;tn19 Obsolete
; .db 0x5C ;tn28 Only supported in
parallel Programming Mode!
; .db 0x70 ;AT90C8534 unknown
Hardware, untested!
; .db 0x71 ;AT90C8544 unknown
Hardware, untested!
; .db 0x80 ;AT89C1051 unknown
Hardware, untested!
; .db 0x81 ;AT89C2051 unknown
Hardware, untested!

;
***************************************************************************
;*
;* TABLE
;* revision codes
;*
;
***************************************************************************

SW_Ver:
.db "37",0,0
HW_Ver:
.db "12",0,0

;
***************************************************************************
;*
;* TABLE
;* ID string "AVR ISP"
;*
;
***************************************************************************

ID_Str:
.db "AVR ISP",0

;
***************************************************************************
;*
;* TABLE
;* Chip ID string to identify the Firmware
;*
;
***************************************************************************

ChipID:
.db "Ver.3.7e (AVR109 Mode, 7.3728Mhz, 115.200
baud) for AN910, AT90S2313"
.db "www.mikrocontroller-projekte.de 14.Jan.2005",0

;**** End of File ****

Programming the AVR Microcontrollers in Machine Language

AVR
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected

from Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing,
intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still
be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and

http://avr-asm.tripod.com/isp2313.html (3 of 4)1/20/2009 8:58:51 PM

16 BIT MATH (AVR 202)

Registers The data address space consists of the register file,

I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language

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16 BIT MATH (AVR 202)

The AVR Assembler Site

AVR ISP FOR 1200

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;
ASM FORUM ***************************************************************************
ASM MATH ;*
;* Title : AVR ISP (Auto adr inc, 19200bps)
TUTORIAL #1
;* Version : 2.0
TUTORIAL #2 ;* Last updated : 1998.01.06 (mlund)
TUTORIAL #3 ;* Target : AT90S1200
;* File : ispprog.asm
MATH 200 ;* Author : Atmel Norway
MATH 200b ;*
;* DESCRIPTION
MATH 201 ;* The firmware on all programmers now support a
MATH 202 unified protocol for
;* program and data memory programming. The host
MATH 32X
computer do not need
MATH YX ;* to know if the programmer operates in serial or
parallel mode.
DIV16 XX
;*
DIV 24 24 ;* The following commands are supported. All commands
DIV 3216 start with a
;* single letter. The programmer returns 13d (carriage
FLOAT 128 return) or the
SQRT16 ;* data read after the command is finished.
;*
MATH 202 ;* +-------------
MATH 202 +------------+------+
;* Commands | Host writes |
DEC ASCII
Host reads | |
INT ASCII ;* -------- +-----+-------
+------+-----+ |
HX2ASC
;* | ID | data |
AVG8 222 data | | Note |
FFT7 ;* +-----------------------------------+-----+-------
+------+-----+------+
COPY 102 ;* | Enter programming mode | 'P' |
LPM 108 | | 13d | 1 |
;* | Set address | 'A' | ah al
EPROM 100 | | 13d | 2 |
SER EPROM ;* | Write program memory, low byte | 'c' | dd
| | 13d | 3 |
DFLASH AT45
;* | Write program memory, high byte | 'C' | dd
FLASH CARD | | 13d | 3 |
;* | Issue Page Write | 'm' |
VFX SMIL
| | 13d | |
VFX MEM ;* | Read program memory | 'R' | |dd
SORT 220 (dd)| | 4 |
;* | Write data memory | 'D' | dd
CRC 236 | | 13d | |
XMODEM REC ;* | Read data memory | 'd' |
| dd | | |
UART 304 ;* | Chip erase | 'e' |
UART 305 | | 13d | |
;* | Write lock bits | 'l' | dd
UART 128
| | 13d | |
UART BUFF ;* | Write fuse bits | 'f' | dd
USB 232 | | 13d | 11 |
;* | Read fuse and lock bits | 'F' |
AVR ISP | dd | | 11 |
ISP 2313 ;* | Leave programming mode | 'L' |
| | 13d | 5 |
ISP 1200 ;* | Select device type | 'T' | dd
AVR SPI | | 13d | 6 |
;* | Read signature bytes | 's' | |
I2C 300 3*dd | | |
I2C 302 ;* | Return supported device codes | 't' | |
n*dd | 00d | 7 |
I2C TWI26
;* | Return software identifier | 'S' | | s
I2C/TWI 128 [7] | | 8 |
I2C/TWI AT8 ;* | Return sofware version | 'V' | |
dd dd | | 9 |
DALLAS-1W ;* | Return hardware version | 'v' | |
DALLAS CRC dd dd | | 9 |
;* | Return programmer type | 'p' |
ETHNET 8019 | dd | | 10 |
TEA ;* | Set LED | 'x' | dd
| | 13d | 12 |
ADC 128 ;* | Clear LED | 'y' | dd
ADC 10B | | 13d | 12 |
;* | Universial command | ':' | 3*dd
ADC 400
| dd | 13d | |
ADC 401 ;* +-----------------------------------+-----+-------
THERM 232 +------+-----+------+
;*
IRD 410 ;* NOTE 1
LCD HD44 ;* The Enter programming mode command MUST be sent one
time prior to
LCD 2313 ;* the other commands, with the exception of the 't',
LCD44 2313 'S', 'V', 'v'
;* and 'T' commands. The 'T' command must be sent
KBD 240 before this command
MUX 242 ;* (see note 6).
;*
KBD PS2
;* For programmers supporting both parallel and serial
KBD PC/128 programming
PS2 EMU ;* mode this command enters parallel programming mode.
For programmers
BOOT MG8 ;* supporting only serial programming mode, this
BOOT DR8 command enters serial
;* programming mode.
ALM CLK ;*
CLOCK 8564 ;* NOTE 2
;* The ah and al are the high and low order bytes of
90 DAYS
the address. For
DELAYS ;* parallel programmers this command issues the Load
Address Low/High
CALL ID
;* Byte command. For serial programmers the address
DTMF 314 byte is stored for
PWM 6CH ;* use by the Read/Write commands.
;*
PWM 10K ;* NOTE 3
ENCODE ;* For parallel programmers this command issues the
Program Flash
STH-11 ;* command. For serial programmers this command
ATMEL CORP iussues the Write
;* Program Memory Command. For devices with byte-wide
AVR
program memories
BUTTERFLY ;* only the low byte command should be used.
AVR BOOK ;*
;* NOTE 4
;* The contents of the program memory at the address
given by the 'A'
;* command are written to the serial port in binary
form. For byte
;* wide memories one byte is written. For 16 bit
memories two bytes
;* are written,MSB first.
;*
;* NOTE 5
;* This command must be executed after the programming
is finished.
;*
;* NOTE 6
;* The select device type command must be sent before
the enter
;* programming command
;*
;* NOTE 7
;* The supported device codes are returned in binary
form terminated
;* by 0x00.
;*
;* NOTE 8
;* This return a 7 character ASCII string identifying
the programmer.
;* For the in-system programmer it is "AVR ISP".
;*
;* NOTE 9
;* The software/hardware version are returned as two
ASCII numbers.
;*
;* NOTE 10
;* This command should be used to identify the
programmer type. The
;* return value is 'S' for serial (or SPI) programmers
or 'P' for
;* parallel programmers.
;*
;* NOTE 11
;* The write fuse bits command are available only on
parallel
;* programmers and only for AVR devices (device code <
0x80). The host
;* should use the return programmer type command to
determine the
;* programmer type, do not use the "AVR PPR"
idenifier because other
;* programmers may be available in the future.
;*
;* NOTE 12
;* Currently only the AVR development board has LEDs.
The other boards
;* must implement this commands as NOPs.
;*
;* NOTE 13
;* Devices using Page Mode Programming write one
page of flash memory
;* before issuing a Page Mode Write Pulse.
;
***************************************************************************

;**** includes ****

.include "1200def.inc"

;
***************************************************************************
;*
;* CONSTANTS
;* device codes
;*
;* DESCRIPTION
;* The following device codes must be used by the host
computer. Note
;* that the device codes are arbitrary selected, they
do not have any
;* thing in common with the signature bytes stored in
the device.
;*
;* The following devices are supported (make a new
table for each
;* software release):
;*
;* SW_MAJOR=1, SW_MINOR=5
;* AT90S1200 rev. C (abbreviated S1200C)
;* AT90S1200 rev. D (abbreviated S1200D)
;* AT90S8515 rev. A (abbreviated S8515A)
;* AT89S8252 (abbreviated S8252)
;*
;* SW_MAJOR=1, SW_MINOR=6
;* AT90S1200 rev. C (abbreviated S1200C)
;* AT90S1200 rev. D (abbreviated S1200D)
;* AT90S8515 rev. A (abbreviated S8515A)
;* AT89S8252 (abbreviated S8252)
;* ATmega103 rev. A (abbreviated S01838A)
;*
;
***************************************************************************

.equ S1200C = 0x12

.equ S1200D = 0x13
.equ S2313A = 0x20
.equ S4414A = 0x28
.equ S8515A = 0x38
.equ S8252 = 0x86
.equ S2323A = 0x48

.equ S01838C = 0x40

.equ S01838D = 0x41

;**** Revision Codes ****

.equ SW_MAJOR = 2 ; Major SW revision

number
.equ SW_MINOR = 0 ; Minor SW revision
number
.equ HW_MAJOR = 1 ; Major HW revision
number
.equ HW_MINOR = 0 ; Minor HW revision
number

;
***************************************************************************
;*
;* MACROS
;* Program Macros
;*
;* DESCRIPTION
;* Change the following four macros if the RESET pin
to the
;* target moves and/or if the SCK/MISO/MOSO moves.
;*
;
***************************************************************************

.macro set_reset
sbi portb,4
.endm

.macro clr_reset
cbi portb,4
.endm

.macro ddrd_init
nop
; sbi ddrd,3
.endm

.macro ddrb_init
ldi temp1,0xdf
out ddrb,temp1 ; PB5 is input, the rest is
output
.endm

.macro ddrb_release
ldi temp1,(1<<PB4)
out ddrb,temp1 ; PB4 (RESET) is output,
the rest is input
.endm

.macro pulse_sck
sbi portb,SCK
ldi temp2,6
m0: dec temp2
brne m0
cbi portb,SCK
ldi temp2,1 ; 3
m1: dec temp2
brne m1
.endm

;*****************
;* SPI Constants *
;*****************

.equ MOSI = 6 ; Bit number on

PORTB
.equ MISO = 5 ; Bit number on
PORTB
.equ SCK = 7 ; Bit number on
PORTB

;******************
;* UART Constants *
;******************

;**** Constant declarations Data Rate ****

;.equ N = 95 ; 115200 BAUD when

R=1 and XTAL=11.059MHz
;.equ N = 31 ; 57600 BAUD when
R=2 and XTAL=11.059MHz
;.equ N = 43 ; 38400 BAUD when
R=2 and XTAL=11.059MHz
.equ N = 33 ; 19200 BAUD when
R=2 and XTAL=4.00MHz
;.equ N = 102 ; 38400 BAUD when
R=1 and XTAL=4.00MHz
.equ R = 2

;**** UART transmit pin in PORTD ****

.equ TXPIN = 1
.equ RXPIN = 0 ; Receive pin must
be external interrupt !!

;**** Bit positions in UART Status Register ****

.equ TXC = 0 ; Transmit

.equ RXC = 1 ; Receive

;*****************************
;* Global Register Variables *
;*****************************

.def device = r16 ; Device code

.def temp1 = r17
.def temp2 = r18
.def s_data = r19 ; SPI data
.def u_data = r20 ; UART data
.def addrl = r21 ; Low order byte of
address
.def addrh = r22 ; High order byte
of address
.def bit_cnt = r23 ; Bit count used by
UART routine
.def u_stat = r24 ; Status byte used
by UART routine
.def cmd = r25 ; Serial
programming command
.def count = r26 ; Time out variable
for "enter programming mode"
.def param1 = r27
.def cmd1 = r28
.def cmd2 = r29
.def cmd3 = r30

;*********************
;* Interrupt Vectors *
;*********************

.CSEG
rjmp RESET ; Reset Handle
reti ; IRQ0 Handle (not used)
rjmp TIM0_OVF ; Timer0 Overflow Handle
reti ; Analog Comparator Handle
(not used)

;
***************************************************************************
;*
;* INTERRUPT
;* TIM0_OVF - Software UART Service Routine
;*
;
***************************************************************************

TIM0_OVF:
in r0,SREG ; store SREG
ldi temp1,(256-N+8)
out TCNT0,temp1 ; reset T/C0 to one bit
lenght
inc bit_cnt ; increment bit counter
sbrs u_stat,TXC ; if (transmit complete
flag clear)
rjmp transmit ; goto transmit

to_0: sec ; set carry

sbis PIND,RXPIN ; if (RxD == LOW)
clc ; clear carry
ror u_data ; shift carry into u_data

cpi bit_cnt,8 ; if (bit_cnt == 8)

brne to_1 ; {
clr temp1 ; disable T/C0 Overflow
Interrupt
out TIMSK,temp1
sbr u_stat,1<<RXC ; set receive complete
to_1: ; }
out SREG,r0 ; restore SREG
reti ; exit

transmit:
cpi bit_cnt,1 ; if (bit_cnt == 1) \\
start bit
brne to_2 ; {
cbi PORTD,TXPIN ; generate start bit
rjmp to_1 ; exit
to_2: ; }
cpi bit_cnt,10 ; if (bit_cnt == 10) \\
stop bit
brne to_3 ; {
sbi PORTD,TXPIN ; generate stop bit
clr temp1 ; disable TC0
overflow interrupt
out TIMSK,temp1
sbr u_stat,1<<TXC ; set transmit
complete bit
rjmp to_1 ; exit
to_3: ; }
sbrc u_data,0 ; if (LSB set)
sbi PORTD,TXPIN ; PD3 = HIGH
sbrs u_data,0 ; if (LSB clear)
cbi PORTD,TXPIN ; PD3 = LOW
lsr u_data ; shift left u_data
rjmp to_1 ; exit

;
***************************************************************************
;*
;* FUNCTION
;* u_init
;*
;* DESCRIPTION
;* Initialize UART.
;*
;
***************************************************************************

u_init: ldi u_stat,1<<TXC ; set TXC

ldi temp1,R ; set clock rate
out TCCR0,temp1
sbi DDRD,TXPIN ; initialize UART pins
cbi DDRD,RXPIN
ret

;
***************************************************************************
;*
;* FUNCTION
;* putc
;*
;* DESCRIPTION
;* Send a character on the UART Tx line.
;*
;
***************************************************************************

putc: clr u_stat ; clear UART status

flags
clr bit_cnt ; clear bit counter
ldi temp1,1<<TOV0 ; enable T/C0 overflow
interrupt
out TIMSK,temp1
putc0: sbrs u_stat,TXC ; while (!(u_stat &
TXC)); // Wait for TXC
rjmp putc0
ret

;
***************************************************************************
;*
;* FUNCTION
;* getc
;*
;* DESCRIPTION
;* Wait for start bit and receive a character on the
UART Rx line.
;*
;
***************************************************************************

getc: sbis PIND,RXPIN

rjmp getc
getc0: sbic PIND,RXPIN
rjmp getc0
ldi temp1,(256-(N+N/2)+8+12);
out TCNT0,temp1 ; preset T/C0 to 1.5 bit
lengths
ldi temp1,1<<TOIE0
out TIFR,temp1 ; clear T/C0 overflow flag
out TIMSK,temp1 ; enable T/C0 overflow
Interrupt
clr bit_cnt ; clear bit counter
getc1: sbrs u_stat,RXC ; wait for Receive
Complete
rjmp getc1
cbr u_stat,1<<RXC ; clear RXC
ret

;
***************************************************************************
;*
;* FUNCTION
;* delay
;*
;* DESCRIPTION
;* Make a small delay.
;*
;
***************************************************************************

delay: ldi temp2,0xff

dl: dec temp2
brne dl
dec temp1
brne delay
ret

;
***************************************************************************
;*
;* FUNCTION
;* wrser
;*
;* DESCRIPTION
;* Write a byte to the SPI.
;*
;
***************************************************************************

wrser: ldi temp1,8

wrs0: rol s_data
brcc wrs1
sbi portb,MOSI
rjmp wrs2
wrs1: cbi portb,MOSI
wrs2: pulse_sck
dec temp1
brne wrs0
ret

;
***************************************************************************
;*
;* FUNCTION
;* rdser
;*
;* DESCRIPTION
;* Read a byte from the SPI.
;*
;
***************************************************************************

rdser: ldi temp1,8

ldi s_data,0
rd0: lsl s_data
sbic pinb,MISO
ori s_data,1
pulse_sck
dec temp1
brne rd0
ret

;
***************************************************************************
;*
;* FUNCTION
;* spiinit (Enter programming mode)
;*
;* DESCRIPTION
;* Initialize SPI interface on AVR or 'AT89 device.
;*
;
***************************************************************************

spiinit:ddrd_init ; initialize port D

ddrb_init ; initialize port B
cbi portb,SCK ; clear SCK
cpi device,S8252 ; if (device != S8252)
breq s89 ; {
set_reset ; set RESET = 1
ldi temp1,0xff ; delay(0xff);
rcall delay
clr_reset ; set RESET = 0
rjmp s0 ; }
; else
s89: ; {
clr_reset ; set RESET = 0
ldi temp1,0xff ; delay(0xff);
rcall delay
set_reset ; set RESET = 1
s0: ; }
ldi temp1,0xff ; delay(0xff);
rcall delay

ldi s_data,0xac ; wrser(0xac); //

SPI write (byte 1)
rcall wrser
ldi s_data,0x53 ; wrser(0x53); //
SPI write (byte 2)
rcall wrser

; // SPI Synchronization
(fix!)
cpi device,0x20 ; if ( (device >= 0x20) &&
(device <= 0x7F) )
brlo s2
tst device
brmi s2
s0b: ; {
ldi count,32 ; count = 32;
s1: ; do {
rcall rdser ; if (rdser
== 0x53) // SPI read (byte 3)
cpi s_data,0x53
breq s3 ;
break;
ldi s_data,0x00 ; wrser
(0x00); // SPI write (byte 4)
rcall wrser
pulse_sck ; pulse SCK
ldi s_data,0xac ; wrser
(0xac); // SPI write (byte 1)
rcall wrser
ldi s_data,0x53 ; wrser
(0x53); // SPI write (byte 2)
rcall wrser
dec count ; } while(--count);
brne s1
rjmp s3 ; }
; else
s2: ; {
ldi s_data,0x00 ; wrser
(0x00); // SPI write (byte 3)
rcall wrser
s3: ; }
cpi device,S8252 ; if (device != S8252)
breq s4 ; {
ldi s_data,0x00 ; wrser(0x00); //
SPI write (byte 4)
rcall wrser
s4: ; }
ldi temp1,0x10 ; delay(0x10);
rcall delay
ret

;
***************************************************************************
;*
;* FUNCTION
;* show_id
;*
;* DESCRIPTION
;* Show our ID ("AVR ISP") on the serial line.
;*
;
***************************************************************************

show_id:ldi u_data,0x41 ; 'A'

rcall putc
ldi u_data,0x56 ; 'V'
rcall putc
ldi u_data,0x52 ; 'R'
rcall putc
ldi u_data,0x20 ; ' '
rcall putc
ldi u_data,0x49 ; 'I'
rcall putc
ldi u_data,0x53 ; 'S'
rcall putc
ldi u_data,0x50 ; 'P'
rcall putc
ret

;
***************************************************************************
;*
;* RESET
;*
;* DESCRIPTION
;* Initialization
;*
;
***************************************************************************

RESET: clr temp1

out GIMSK,temp1 ; disable external interrupt
ser temp1 ; Initialize
out PORTD,temp1
set_reset ; set RESET=1
out PORTB,temp1
ddrb_release
rcall u_init ; Initialize UART
sei ; Enable interrupts

;
***************************************************************************
;*
;* PROGRAM
;* waitcmd -> main
;*
;* DESCRIPTION
;* Wait for and execute commands.
;*
;
***************************************************************************

waitcmd:rcall getc ; while (getc() ==

ESC) {};
cpi u_data,0x1b
breq waitcmd

;**** Device Type ****

cpi u_data,0x54 ; 'T' Device type

brne w0
rcall getc ; getc(); // dummy
mov device,u_data ; putc(device);
rjmp put_ret

;**** Return Software Identifier ****

w0: cpi u_data,0x53 ; 'S' Return software

identifier
brne w1
rcall show_id ; show_id();
rjmp waitcmd

;**** Return Software Version ****

w1: cpi u_data,0x56 ;'V' Return software version

brne w2
ldi u_data,0x30+SW_MAJOR ; putc(0x30+SW_MAJOR);
rcall putc
ldi u_data,0x30+SW_MINOR ; putc(0x30+SW_MINOR);
rcall putc
rjmp waitcmd

;**** Return Hardware Version ****

w2: cpi u_data,0x76 ;'v' Return hardware version

brne w3
ldi u_data,0x30+HW_MAJOR ; putc(0x30+HW_MAJOR);
rcall putc
ldi u_data,0x30+HW_MINOR ; putc(0x30+HW_MINOR);
rcall putc
rjmp waitcmd

;**** Show Supported Devices ****

w3: cpi u_data,0x74 ; 't' Show supported devices

brne w4
ldi u_data,S1200C ; putc(S1200C);
rcall putc
ldi u_data,S1200D ; putc(S1200D);
rcall putc
ldi u_data,S2313A ; putc(S2313A);
rcall putc
ldi u_data,S4414A ; putc(S4414A);
rcall putc
ldi u_data,S8515A ; putc(S8515A);
rcall putc
ldi u_data,S2323A ; putc(S2323A);
rcall putc
ldi u_data,S8252 ; putc(S8252);
rcall putc
ldi u_data,0x00 ; putc(0x00); // end of
device list
rcall putc
rjmp waitcmd

;**** Return Programmer Type ****

w4: cpi u_data,0x70 ; 'p' Return programmer type

brne w5
ldi u_data,0x53 ; putc('S'); // serial
programmer
rcall putc
rjmp waitcmd

;**** Set LED ****

w5: cpi u_data,0x78 ; 'x' Set LED (ignored)

brne w6
rjmp put_ret

;**** Clear LED ****

w6: cpi u_data,0x79 ; 'y' Clear LED (ignored)

brne w7
rjmp put_ret

;**** Enter Programming Mode ****

; We require that the device code be selected before

any of the other commands

w7:
cpi device,S1200C ; if ((device != S1200C) &&
breq w72
cpi device,S1200D ; (device != S1200D) &&
breq w72
cpi device,S8515A ; (device != S8515A) &&
breq w72
cpi device,S4414A ; (device != S4414A) &&
breq w72
cpi device,S2313A ; (device != S2313A) &&
breq w72
cpi device,S8252 ; (device != S8252) &&
breq w72
cpi device,S01838C ; (device != S01838C) &&
breq w72
cpi device,S01838D ; (device != S01838D) &&
breq w72
cpi device,S2323A ; (device != S2323A))
breq w72
rjmp put_err ; goto put_err();

w72: cpi u_data,0x50 ; 'P' Enter

programming mode
brne w8
rcall spiinit ; spiinit();
rjmp put_ret

;**** Wait Program Memory ****

;* USAGE
;* wait_pm(byte cmd, byte c_data);
;*
;* cmd : 0x28 - wait for high byte written
;* 0x20 - wait for low byte written
;* u_data : current data written

;wait_pm: ; do
; ; {
; mov s_data,cmd ; wrser
(cmd); // SPI write (byte 1)
; rcall wrser
; mov s_data,addrh ; wrser
(addrh); // SPI write (byte 2)
; rcall wrser
; mov s_data,addrl ; wrser
(addrl); // SPI write (byte 3)
; rcall wrser
; rcall rdser ; s_data = rdser
(); // SPI read (byte 4)
; }
; cp s_data,u_data ; while(s_data != u_data);
; brne wait_pm
; ret

;**** Write Program Memory, High Byte ****

w8: cpi u_data,0x43 ; 'C' Write program memory,

high byte
brne w9
rcall getc
cpi device,S8252 ; if (device == S8252)
brne w81 ; {
rjmp put_err ; goto err();
; // (AT89 series
have byte wide program memory !)
; }
w81: ldi s_data,0x48 ; wrser
(0x48); // SPI write (byte 1)
rcall wrser
mov s_data,addrh ; wrser(addrh); //
SPI write (byte 2)
rcall wrser
mov s_data,addrl ; wrser(addrl); //
SPI write (byte 3)
rcall wrser
cpi device,S01838C ; invert data on 01838 rev
C!
brne w81b
com u_data
w81b:
mov s_data,u_data ; wrser(u_data); //
SPI write (byte 4)
rcall wrser
cpi device,S01838C ; no delay for S01838 (Uses
Page Write Mode instead)
breq w82
cpi device,S01838D
breq w82

ldi temp1,0x20 ; delay(0x20); //

24585 cycles delay
rcall delay ; //
Page mode requires no delay!
w82:
ldi temp1,0x01 ; Auto increment
address !!!!
clr temp2
add addrl,temp1
adc addrh,temp2
rjmp put_ret ; goto reply();

http://avr-asm.tripod.com/isp1200.html (1 of 3)1/20/2009 8:59:30 PM

16 BIT MATH (AVR 202)

;**** Write Program Memory, Low Byte ****

w9: cpi u_data,0x63 ; 'c' Write program memory,

low byte
brne w12
rcall getc

cpi device,S8252 ; if (device != S8252)

breq w989 ; {
ldi s_data,0x40 ; wrser(0x40); //
SPI write (byte 1)
rcall wrser
mov s_data,addrh ; s_data = addrh;
rjmp w91 ; }
; else
w989: ; {
mov s_data,addrh ; s_data = (addrh <<
3) | 0x02;
rcall shift_s_data3
ori s_data,0x02
w91: ; }
rcall wrser ; wrser(s_data); //
SPI write (byte 2)
mov s_data,addrl ; wrser(addrl); //
SPI write (byte 3)
rcall wrser
cpi device,S01838C ; invert data on 01838 rev
C!
brne w91b
com u_data
w91b:
mov s_data,u_data ; wrser(u_data); //
SPI write (byte 4)
rcall wrser
cpi device,S01838C ; no delay for S01838 (Uses
Page Write Mode instead)
breq w92
cpi device,S01838D
breq w92
ldi temp1,0x20 ; delay(0x20); //
24585 cycles delay
rcall delay ; //
Page mode requires no delay!
w92:
rjmp put_ret ; goto reply();

;**** Read Program Memory ****

w12: cpi u_data,0x52 ; 'R' Read program

memory
brne w10 ;
cpi device,S8252 ; if (device != S8252)
breq w1289 ; {
ldi s_data,0x28 ; wrser(0x28); //
SPI write (byte 1)
rcall wrser
mov s_data,addrh ; s_data = addrh;
rjmp w121 ; }
; else
w1289: ; {
mov s_data,addrh ; s_data = (addrh <<
3) | 0x01;
rcall shift_s_data3
ori s_data,0x01
w121: ; }
rcall wrser ; wrser(s_data); //
SPI write (byte 2)
mov s_data,addrl ; wrser(addrl); //
SPI write (byte 3)
rcall wrser
rcall rdser ; putc(rdser()); //
Send data (byte 4)
mov u_data,s_data
rcall putc
cpi device,S8252 ; if (device == S8252)
brne w122 ; {
rjmp waitcmd ; goto waitcmd();
; }
; else
w122: ; {
ldi s_data,0x20 ; wrser(0x20); //
SPI write (byte 1)
rcall wrser
mov s_data,addrh ; wrser(addrh); //
SPI write (byte 2)
rcall wrser
mov s_data,addrl ; wrser(addrl); //
SPI write (byte 3)
rcall wrser
rcall rdser ; putc(rdser()); //
Send data (byte 4)
mov u_data,s_data
rcall putc

ldi temp1,0x01 ; Auto increment

address !!!!
clr temp2
add addrl,temp1
adc addrh,temp2

rjmp waitcmd ; goto waitcmd();

; }
shift_s_data3:
lsl s_data
lsl s_data
lsl s_data
ret

;**** Load Address ****

w10: cpi u_data,0x41 ; 'A' Load address

brne w11
rcall getc ; addrh = getc();
mov addrh,u_data
rcall getc ; addrl = getc();
mov addrl,u_data
rjmp put_ret ; goto reply();

;**** Write Data Memory ****

w11: cpi u_data,0x44 ; 'D' Write data

memory
brne w13
rcall getc
cpi device,S8252
breq w1189

ldi s_data,0xc0
rcall wrser
mov s_data,addrh
rjmp w111

w1189: mov s_data,addrh

rcall shift_s_data3
ori s_data,0x06

w111: rcall wrser

mov s_data,addrl
rcall wrser
mov s_data,u_data
rcall wrser
ldi temp1,0x20
rcall delay
rjmp put_ret

;;**** Read Data Memory ****

w13: cpi u_data,0x64 ; 'd' Read data

memory
brne w14
cpi device,S8252 ; if (device != S8252)
breq w1389 ; {
ldi s_data,0xa0 ; wrser(0xA0); //
SPI write (byte 1)
rcall wrser
mov s_data,addrh ; s_data = addrh;
rjmp w131 ; }
; else
w1389: ; {
mov s_data,addrh ; s_data = (addrh <<
3) | 0x05;
rcall shift_s_data3
ori s_data,0x05
w131: ; }
rcall wrser ; wrser(s_data); //
SPI write (byte 2)
mov s_data,addrl ; wrser(addrl); //
SPI write (byte 3)
rcall wrser
rcall rdser ; putc(rdser()); //
Send data (byte 4)
mov u_data,s_data
rcall putc
rjmp waitcmd ; goto waitcmd();

;**** Leave Programming Mode ****

w14: cpi u_data,0x4c ; 'L' Leave

programming mode
brne w15
ddrb_release
cpi device,S8252
breq w141
set_reset ; set RESET = 1
rjmp put_ret
w141: clr_reset ; set RESET = 0
rjmp put_ret

;**** Chip Erase ****

w15: cpi u_data,0x65 ; 'e' Chip erase

brne w16
ldi s_data,0xac
rcall wrser
cpi device,S8252
breq w1589
ldi s_data,0x80
rcall wrser
w1589: ldi s_data,0x04
rcall wrser
ldi s_data,0x00
rcall wrser
ldi temp1,0x30
rcall delay
rjmp put_ret

;**** Write Lock Bits ****

w16: cpi u_data,0x6c ; 'l' Write lock

bits
brne w17
rcall getc
ldi s_data,0xac
rcall wrser
mov s_data,u_data
cpi device,S8252
breq w1689
andi s_data,0x06
ori s_data,0xe0
rcall wrser
ldi s_data,0x00
rcall wrser
rjmp w162

w1689: andi s_data,0xe0

ori s_data,0x07
rcall wrser
w162: ldi s_data,0x00
rcall wrser
ldi temp1,0x30
rcall delay
rjmp put_ret

;**** Read Signature Bytes ****

w17: cpi u_data,0x73 ; 's' Read

signature bytes
brne w18
cpi device,S8252
brne w17begin
rjmp put_err
w17begin:
ldi param1,0x02
rcall w17call
ldi param1,0x01
rcall w17call
ldi param1,0x00
rcall w17call
rjmp waitcmd

w17call:ldi s_data,0x30
rcall wrser
ldi s_data,0x00
rcall wrser
mov s_data,param1
rcall wrser
rcall rdser
mov u_data,s_data
rcall putc
ret

;**** Write Program Memory Page ****

w18: cpi u_data,0x6D ; 'm' Write Program

Memory Page
brne w19

ldi s_data,0x4c ; wrser(0x4c); //

SPI write (byte 1)
rcall wrser

mov s_data,addrh ; wrser(addrh); //

SPI write (byte 2)
rcall wrser
mov s_data,addrl ; wrser(addrl); //
SPI write (byte 3)
rcall wrser

ldi s_data,0x00 ; wrser(0x00); //

SPI write (byte 4)
rcall wrser
ldi temp1,0xff ; delay(0xFF); //
0x20 = 24585 cycles delay
rcall delay
rjmp put_ret

;**** Universal Command ****

w19: cpi u_data,0x3A ; ':' Universal

Command
brne w99

rcall getc
mov cmd1,u_data
rcall getc
mov cmd2,u_data
rcall getc
mov cmd3,u_data
rcall universal
ldi temp1,0xff ; delay(0xFF); //
0x20 = 24585 cycles delay
rcall delay
rjmp put_ret

universal:
mov s_data,cmd1
rcall wrser
mov s_data,cmd2
rcall wrser
mov s_data,cmd3
rcall wrser
rcall rdser
mov u_data,s_data
rcall putc
ret

w99:

;**** Command Error ****

put_err:ldi u_data,0x3f ; putc('?'); \\ send '?'

rcall putc
rjmp waitcmd

;**** Reply Command ****

put_ret:ldi u_data,0x0d ; putc(0x0D); \\ send CR

rcall putc
rjmp waitcmd

;**** End of File ****

Programming the AVR Microcontrollers in Machine Language

AVR
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected

from Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing,
intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still
be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
http://avr-asm.tripod.com/isp1200.html (2 of 3)1/20/2009 8:59:30 PM
16 BIT MATH (AVR 202)

the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language

http://avr-asm.tripod.com/isp1200.html (3 of 3)1/20/2009 8:59:30 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

AVR SPI PROTOCOL

HOME
RETRO_DAN
;**** A P P L I C A T I O N N O T E A V R 3 2 0
ASM FORUM *****************
ASM MATH ;*
;* Title : Software SPI Master
TUTORIAL #1
;* Version : 1.0
TUTORIAL #2 ;* Last updated : 98.04.21
TUTORIAL #3 ;* Target : AT90S1200
;* Easily modified for : Any AVR microcontroller
MATH 200 ;*
MATH 200b ;* Support E-mail :avr@atmel.com
;*
MATH 201 ;* DESCRIPTION
MATH 202 ;* This is a collection of 8/16-bit word, Mode 0,
Master SPI routines.
MATH 32X
;* It simultaneously transmits and receives SPI data
MATH YX in 8- or 16-bit
;* word format. Data is sent and received MSB-first.
DIV16 XX
One pair of
DIV 24 24 ;* registers is used both to send and to receive; i.
DIV 3216 e., when one bit
;* is shifted out (transmitted), the vacated bit
FLOAT 128 position is used to
SQRT16 ;* store the new received bit. These routines are low-
level
MATH 202 ;* interface routines, and do not inherently contain a
MATH 202 command
;* structure; that is dictated by the connected SPI
DEC ASCII
peripheral(s).
INT ASCII ;*
;* Due to having separate Enable/Disable and Read/
HX2ASC
Write-Word
AVG8 222 ;* routines, larger blocks of data can be sent simply
FFT7 by calling
;* the RW_SPI routine multiple times before disabling /
COPY 102 SS.
LPM 108 ;*
;* MAJOR ROUTINES:
EPROM 100 ;* init_spi: initializes the port lines used for SPI.
SER EPROM ;* No calling requirements, returns
nothing.
DFLASH AT45
;* ena_spi: forces SCK low, and activates /SS signal.
FLASH CARD ;* No calling requirements, returns
nothing.
VFX SMIL
;* disa_spi: brings /SS signal hi (inactive).
VFX MEM ;* No calling requirements, returns
SORT 220 nothing.
;* rw_spi: sends/receives a an 8-bit or 16-bit data
CRC 236 word.
XMODEM REC ;* Must set up data to be sent in
(spi_hi,spi_lo)
UART 304 ;* prior to calling; it returns
UART 305 received data in
;* the same register pair (if 8-bit,
UART 128
uses only
UART BUFF ;* the spi_lo register).
USB 232 ;*
;* VARIABLES:
AVR ISP ;* The spi_hi and spi_lo variables are the high and
ISP 2313 low data bytes.
;* They can be located anywhere in the register file.
ISP 1200 ;*
AVR SPI ;* The temp variable holds the bit count, and is also
used in timing
I2C 300 ;* the high/low minimum pulse width. This must be
I2C 302 located in an
;* upper register due to the use of an IMMEDIATE-mode
I2C TWI26
instruction.
I2C/TWI 128 ;*
I2C/TWI AT8 ;* HISTORY
;* V1.0 98.04.21 (rgf) Created
DALLAS-1W ;*
DALLAS CRC ;
***************************************************************************
ETHNET 8019
TEA
ADC 128 ;**** includes ****
ADC 10B
.include "1200def.inc" ;you can change
ADC 400
this to any device
ADC 401
THERM 232
IRD 410
LCD HD44 ;
***************************************************************************
LCD 2313 ;*
LCD44 2313 ;* CONSTANTS
;*
KBD 240 ;
MUX 242 ***************************************************************************
KBD PS2
;**** Revision Codes ****
KBD PC/128
PS2 EMU .equ SW_MAJOR = 1 ; Major SW revision
number
BOOT MG8 .equ SW_MINOR = 0 ; Minor SW revision
BOOT DR8 number
.equ HW_MAJOR = 0 ; Major HW revision
ALM CLK number
CLOCK 8564 .equ HW_MINOR = 0 ; Minor HW revision
number
90 DAYS
DELAYS
CALL ID
;
DTMF 314 ***************************************************************************
PWM 6CH ;*
;* PORT DEFINITIONS
PWM 10K ;*
ENCODE ;
***************************************************************************
STH-11
ATMEL CORP .equ sck = 0 ;PB0 pin
.equ nss = 1 ;PB1 pin
AVR
.equ mosi = 2 ;PB2 pin
BUTTERFLY .equ miso = 3 ;PB3 pin
AVR BOOK

;
***************************************************************************
;*
;* REGISTER DEFINITIONS
;*
;
***************************************************************************

.def spi_lo =r0 ;change as needed

.def spi_hi =r1 ; "
.def temp =r16 ;misc usage, must be in
upper regs for IMMED mode

;
***************************************************************************
;*
;* MACROS
;* Program Macros
;*
;* DESCRIPTION
;* Change the following macros if a port other than
PORTB is used.
;*
;
***************************************************************************

.macro ss_active
cbi portb,nss
.endm

.macro ss_inactive
sbi portb,nss
.endm

.macro sck_hi
sbi portb,sck
.endm

.macro sck_lo
cbi portb,sck
.endm

.macro mosi_hi
sbi portb,mosi
.endm

.macro mosi_lo
cbi portb,mosi
.endm

.macro addi
subi @0, -@1 ;subtract the negative of
an immediate value
.endm

.macro set_delay ;set up the time

delay amount, from 1 to 7
subi @0, (@1 << 5) ;NOTE: THIS shift affects
INC macro (below)!
.endm

.macro inc_delay ;bump the delay

counter
subi @0, -(1 << 5) ;shift value here must be
same as above!
.endm

;
***************************************************************************
;*
;* SAMPLE APPLICATION, READY TO RUN ON AN AT90S1200
;*
;
***************************************************************************

.cseg
.org 0
Rvect: rjmp Reset

;
***************************************************************************
;*
;* FUNCTION
;* init_spi
;*
;* DESCRIPTION
;* Initialize our port pins for use as SPI master.
;*
;* CODE SIZE:
;* 8 words
;*
;
***************************************************************************

init_spi:
ss_inactive ;set latch bit hi (inactive)
sbi ddrb,nss ;make it an output
;
sck_lo ;set clk line lo
sbi ddrb,sck ;make it an output
;
mosi_lo ;set data-out lo
sbi ddrb,mosi ;make it an output
;
cbi ddrb,miso ;not really required, it
powers up clr'd!
ret

;
***************************************************************************
;*
;* FUNCTION
;* ena_spi
;*
;* DESCRIPTION
;* Init data & clock lines, then assert /SS. Note
that if more than
;* one slave is used, copies of this could be made
that would each
;* reference a different /SS port pin (use SS_ACTIVE0,
SS_ACTIVE1, ...)
;*
;* CODE SIZE:
;* 4 words
;*
;
***************************************************************************

ena_spi:
sck_lo ;(should already be
there...)
mosi_lo
ss_active
ret

;
***************************************************************************
;*
;* FUNCTION
;* disa_spi
;*
;* DESCRIPTION
;* De-assert /SS. Since this routine is so short, it
might be better
;* to use the SS_INACTIVE statement directly in higher
level code.
;* Again, if multiple slaves exist, additional copies
of this could
;* be created; or ONE routine that disabled ALL /ss
signals could be
;* used instead to make the code less error-prone due
to calling the
;* wrong Disable routine.
;*
;* CODE SIZE:
;* 2 words
;*
;
***************************************************************************

disa_spi:
ss_inactive
ret

;
***************************************************************************
;*
;* FUNCTION
;* rw_spi
;*
;* DESCRIPTION
;* Write a word out on SPI while simultaneously
reading in a word.
;* Data is sent MSB-first, and info read from SPI goes
into
;* the same buffer that the write data is going out
from.
;* Make sure data, clock and /SS are init'd before
coming here.
;* SCK high time is ((delay * 3) + 1) AVR clock cycles.
;*
;* If 8-bit use is needed, change LDI TEMP,16 to ,8
and also
;* eliminate the ROL SPI_HI statement.
;*
;* CODE SIZE:
;* 21 words
;* NUMBER OF CYCLES:
;* Overhead = 8, loop = 16 * (16 + (2*
(delay_value*3)))
; (With call + return + delay=4, it is about 648
cycles.)
;*
;
***************************************************************************

rw_spi:
ldi temp,16 ;init loop counter to 16
bits
;ldi temp,8 ;use THIS line instead if 8-
bit desired
;
spi_loop:
lsl spi_lo ;move 0 into D0, all other
bits UP one slot,
rol spi_hi ; and C ends up being first
bit to be sent.
;If 8-bit desired, also comment out the preceding ROL
SPI_HI statement
;
brcc lo_mosi
mosi_hi
rjmp mosi_done ;this branch creates setup
time on MOSI
lo_mosi:
mosi_lo
nop ;also create setup time on
MOSI
mosi_done:
;
sck_hi
;
;must now time the hi pulse - not much else we can do
here but waste time
;
set_delay temp,4 ;(4 * 3) cycle delay; range
is from 1 to 7!
time_hi:
inc_delay temp ;inc upper nibble until it
rolls over; then,
brcs time_hi ; C gets CLEARED, & temp
has original value
;
sck_lo ;drop clock line low
;
;must now delay before reading in SPI data on MISO
;
set_delay temp,4
time_lo:
inc_delay temp
brcs time_lo
;
sbic pinb,miso ;after delay, read in SPI
bit & put into D0
inc spi_lo ;we FORCED D0=0, so use INC
to set D0.
;
dec temp
brne spi_loop
ret

;************************ End of SPI routines

****************************

;**** Application example ****

Reset: rcall init_spi

ser temp ;load w/ FF
out DDRD,temp
rjmp Main

Main: ldi R22,0xA3 ;misc data

mov spi_lo,R22 ;set up information to be
sent
mov spi_hi,R22 ;COMMENT THIS OUT IF 8-BIT
MODE
rcall ena_spi ;activate /SS
rcall rw_spi ;send/receive 16 bits (or 8
bits)
rcall disa_spi ;deactivate /SS
rcall use_spi_rcv ;go use whatever we received
rjmp Main

Use_spi_rcv: ;just copy rcv'd

data to Port D pins
out PortD,R22
ret

;**** End of File ****

Programming the AVR Microcontrollers in Machine Language

AVR
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected

from Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing,
intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still
be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
http://avr-asm.tripod.com/avrspi.html (1 of 2)1/20/2009 9:00:10 PM
16 BIT MATH (AVR 202)

AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR

Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language

http://avr-asm.tripod.com/avrspi.html (2 of 2)1/20/2009 9:00:10 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

AVR I2C MASTER PROTOCOL (AVR 300)

HOME
RETRO_DAN
;**** A P P L I C A T I O N N O T E A V R 3 0 0
ASM FORUM ************************
ASM MATH ;*
;* Title : I2C (Single) Master Implementation
TUTORIAL #1
;* Version : 1.0 (BETA)
TUTORIAL #2 ;* Last updated : 97.08.27
TUTORIAL #3 ;* Target : AT90Sxxxx (any AVR device)
;*
MATH 200 ;* Support email : avr@atmel.com
MATH 200b ;*
;* DESCRIPTION
MATH 201 ;* Basic routines for communicating with I2C slave
MATH 202 devices. This
;* "single" master implementation is limited to one
MATH 32X
bus master on the
MATH YX ;* I2C bus. Most applications do not need the
multimaster ability
DIV16 XX
;* the I2C bus provides. A single master
DIV 24 24 implementation uses, by far,
DIV 3216 ;* less resources and is less XTAL frequency dependent.
;*
FLOAT 128 ;* Some features :
SQRT16 ;* * All interrupts are free, and can be used for
other activities.
MATH 202 ;* * Supports normal and fast mode.
MATH 202 ;* * Supports both 7-bit and 10-bit addressing.
;* * Supports the entire AVR microcontroller family.
DEC ASCII
;*
INT ASCII ;* Main I2C functions :
;* 'i2c_start' - Issues a start condition
HX2ASC
and sends address
AVG8 222 ;* and transfer direction.
FFT7 ;* 'i2c_rep_start' - Issues a repeated start
condition and sends
COPY 102 ;* address and transfer
LPM 108 direction.
;* 'i2c_do_transfer' - Sends or receives data
EPROM 100 depending on
SER EPROM ;* direction given in address/
dir byte.
DFLASH AT45
;* 'i2c_stop' - Terminates the data
FLASH CARD transfer by issue a
;* stop condition.
VFX SMIL
;*
VFX MEM ;* USAGE
SORT 220 ;* Transfer formats is described in the AVR300
documentation.
CRC 236 ;* (An example is shown in the 'main' code).
XMODEM REC ;*
;* NOTES
UART 304 ;* The I2C routines can be called either from non-
UART 305 interrupt or
;* interrupt routines, not both.
UART 128
;*
UART BUFF ;* STATISTICS
USB 232 ;* Code Size : 81 words (maximum)
;* Register Usage : 4 High, 0 Low
AVR ISP ;* Interrupt Usage : None
ISP 2313 ;* Other Usage : Uses two I/O pins on port D
;* XTAL Range : N/A
ISP 1200 ;*
AVR SPI ;
***************************************************************************
I2C 300
I2C 302 ;**** Includes ****
I2C TWI26
.include "1200def.inc" ; change if
I2C/TWI 128 an other device is used
I2C/TWI AT8
;**** Global I2C Constants ****
DALLAS-1W
DALLAS CRC .equ SCLP = 1 ; SCL Pin
number (port D)
ETHNET 8019 .equ SDAP = 0 ; SDA Pin
TEA number (port D)
ADC 128 .equ b_dir = 0 ; transfer
ADC 10B direction bit in i2cadr
ADC 400
.equ i2crd = 1
ADC 401 .equ i2cwr = 0
THERM 232
;**** Global Register Variables ****
IRD 410
LCD HD44 .def i2cdelay= r16 ; Delay
loop variable
LCD 2313 .def i2cdata = r17 ; I2C data
LCD44 2313 transfer register
.def i2cadr = r18 ; I2C
KBD 240 address and direction register
MUX 242 .def i2cstat = r19 ; I2C bus
status register
KBD PS2
KBD PC/128 ;**** Interrupt Vectors ****
PS2 EMU
rjmp RESET ; Reset handle
BOOT MG8 ; ( rjmp EXT_INT0 ) ; ( IRQ0 handle )
BOOT DR8 ; ( rjmp TIM0_OVF ) ; ( Timer 0
overflow handle )
ALM CLK ; ( rjmp ANA_COMP ) ; ( Analog
CLOCK 8564 comparator handle )
90 DAYS
DELAYS ;
***************************************************************************
CALL ID
;*
DTMF 314 ;* FUNCTION
PWM 6CH ;* i2c_hp_delay
;* i2c_qp_delay
PWM 10K ;*
ENCODE ;* DESCRIPTION
;* hp - half i2c clock period delay (normal: 5.0us /
STH-11 fast: 1.3us)
ATMEL CORP ;* qp - quarter i2c clock period delay (normal:
2.5us / fast: 0.6us)
AVR
;*
BUTTERFLY ;* SEE DOCUMENTATION !!!
AVR BOOK ;*
;* USAGE
;* no parameters
;*
;* RETURN
;* none
;*
;
***************************************************************************

i2c_hp_delay:
ldi i2cdelay,2
i2c_hp_delay_loop:
dec i2cdelay
brne i2c_hp_delay_loop
ret

i2c_qp_delay:
ldi i2cdelay,1
i2c_qp_delay_loop:
dec i2cdelay
brne i2c_qp_delay_loop
ret

;
***************************************************************************
;*
;* FUNCTION
;* i2c_rep_start
;*
;* DESCRIPTION
;* Assert repeated start condition and sends slave
address.
;*
;* USAGE
;* i2cadr - Contains the slave address and transfer
direction.
;*
;* RETURN
;* Carry flag - Cleared if a slave responds to the
address.
;*
;* NOTE
;* IMPORTANT! : This funtion must be directly followed
by i2c_start.
;*
;
***************************************************************************

i2c_rep_start:
sbi DDRD,SCLP ; force SCL low
cbi DDRD,SDAP ; release SDA
rcall i2c_hp_delay ; half period delay
cbi DDRD,SCLP ; release SCL
rcall i2c_qp_delay ; quarter period
delay

;
***************************************************************************
;*
;* FUNCTION
;* i2c_start
;*
;* DESCRIPTION
;* Generates start condition and sends slave address.
;*
;* USAGE
;* i2cadr - Contains the slave address and transfer
direction.
;*
;* RETURN
;* Carry flag - Cleared if a slave responds to the
address.
;*
;* NOTE
;* IMPORTANT! : This funtion must be directly followed
by i2c_write.
;*
;
***************************************************************************

i2c_start:
mov i2cdata,i2cadr ; copy address to
transmitt register
sbi DDRD,SDAP ; force SDA low
rcall i2c_qp_delay ; quarter period
delay

;
***************************************************************************
;*
;* FUNCTION
;* i2c_write
;*
;* DESCRIPTION
;* Writes data (one byte) to the I2C bus. Also used
for sending
;* the address.
;*
;* USAGE
;* i2cdata - Contains data to be transmitted.
;*
;* RETURN
;* Carry flag - Set if the slave respond transfer.
;*
;* NOTE
;* IMPORTANT! : This funtion must be directly followed
by i2c_get_ack.
;*
;
***************************************************************************

i2c_write:
sec ; set carry flag
rol i2cdata ; shift in carry
and out bit one
rjmp i2c_write_first
i2c_write_bit:
lsl i2cdata ; if transmit
register empty
i2c_write_first:
breq i2c_get_ack ; goto get
acknowledge
sbi DDRD,SCLP ; force SCL low

brcc i2c_write_low ; if bit high

nop ; (equalize
number of cycles)
cbi DDRD,SDAP ; release SDA
rjmp i2c_write_high
i2c_write_low: ; else
sbi DDRD,SDAP ; force SDA
low
rjmp i2c_write_high ; (equalize
number of cycles)
i2c_write_high:
rcall i2c_hp_delay ; half period delay
cbi DDRD,SCLP ; release SCL
rcall i2c_hp_delay ; half period delay

rjmp i2c_write_bit

;
***************************************************************************
;*
;* FUNCTION
;* i2c_get_ack
;*
;* DESCRIPTION
;* Get slave acknowledge response.
;*
;* USAGE
;* (used only by i2c_write in this version)
;*
;* RETURN
;* Carry flag - Cleared if a slave responds to a
request.
;*
;
***************************************************************************

i2c_get_ack:
sbi DDRD,SCLP ; force SCL low
cbi DDRD,SDAP ; release SDA
rcall i2c_hp_delay ; half period delay
cbi DDRD,SCLP ; release SCL

i2c_get_ack_wait:
sbis PIND,SCLP ; wait SCL high
;(In case wait
states are inserted)
rjmp i2c_get_ack_wait

clc ; clear carry flag

sbic PIND,SDAP ; if SDA is high
sec ; set carry
flag
rcall i2c_hp_delay ; half period delay
ret

;
***************************************************************************
;*
;* FUNCTION
;* i2c_do_transfer
;*
;* DESCRIPTION
;* Executes a transfer on bus. This is only a
combination of i2c_read
;* and i2c_write for convenience.
;*
;* USAGE
;* i2cadr - Must have the same direction as when
i2c_start was called.
;* see i2c_read and i2c_write for more information.
;*
;* RETURN
;* (depends on type of transfer, read or write)
;*
;* NOTE
;* IMPORTANT! : This funtion must be directly followed
by i2c_read.
;*
;
***************************************************************************

i2c_do_transfer:
sbrs i2cadr,b_dir ; if dir = write
rjmp i2c_write ; goto write
data

;
***************************************************************************
;*
;* FUNCTION
;* i2c_read
;*
;* DESCRIPTION
;* Reads data (one byte) from the I2C bus.
;*
;* USAGE
;* Carry flag - If set no acknowledge is given to
the slave
;* indicating last read operation
before a STOP.
;* If cleared acknowledge is given to
the slave
;* indicating more data.
;*
;* RETURN
;* i2cdata - Contains received data.
;*
;* NOTE
;* IMPORTANT! : This funtion must be directly followed
by i2c_put_ack.
;*
;
***************************************************************************

i2c_read:
rol i2cstat ; store acknowledge
; (used by
i2c_put_ack)
ldi i2cdata,0x01 ; data = 0x01
i2c_read_bit: ; do
sbi DDRD,SCLP ; force SCL
low
rcall i2c_hp_delay ; half period
delay

cbi DDRD,SCLP ; release SCL

rcall i2c_hp_delay ; half period
delay

clc ; clear carry

flag
sbic PIND,SDAP ; if SDA is
high
sec ; set
carry flag

rol i2cdata ; store data

bit
brcc i2c_read_bit ; while receive
register not full

;
***************************************************************************
;*
;* FUNCTION
;* i2c_put_ack
;*
;* DESCRIPTION
;* Put acknowledge.
;*
;* USAGE
;* (used only by i2c_read in this version)
;*
;* RETURN
;* none
;*
;
***************************************************************************

i2c_put_ack:
sbi DDRD,SCLP ; force SCL low

ror i2cstat ; get status bit

brcc i2c_put_ack_low ; if bit low goto
assert low
cbi DDRD,SDAP ; release SDA
rjmp i2c_put_ack_high
i2c_put_ack_low: ; else
sbi DDRD,SDAP ; force SDA
low
i2c_put_ack_high:

rcall i2c_hp_delay ; half period delay

cbi DDRD,SCLP ; release SCL
i2c_put_ack_wait:
sbis PIND,SCLP ; wait SCL high
rjmp i2c_put_ack_wait
rcall i2c_hp_delay ; half period delay
ret

;
***************************************************************************
;*
;* FUNCTION
;* i2c_stop
;*
;* DESCRIPTION
;* Assert stop condition.
;*
;* USAGE
;* No parameters.
;*
;* RETURN
;* None.
;*
;
***************************************************************************

i2c_stop:
sbi DDRD,SCLP ; force SCL low
sbi DDRD,SDAP ; force SDA low
rcall i2c_hp_delay ; half period delay
cbi DDRD,SCLP ; release SCL
rcall i2c_qp_delay ; quarter period
delay
cbi DDRD,SDAP ; release SDA
rcall i2c_hp_delay ; half period delay
ret

;
***************************************************************************
;*
;* FUNCTION
;* i2c_init
;*
;* DESCRIPTION
;* Initialization of the I2C bus interface.
;*
;* USAGE
;* Call this function once to initialize the I2C bus.
No parameters
;* are required.
;*
;* RETURN
;* None
;*
;* NOTE
;* PORTD and DDRD pins not used by the I2C bus
interface will be
;* set to Hi-Z (!).
;*
;* COMMENT
;* This function can be combined with other PORTD
initializations.
;*
;
***************************************************************************

i2c_init:
clr i2cstat ; clear I2C status
register (used
; as a temporary
register)
out PORTD,i2cstat ; set I2C pins to
open colector
out DDRD,i2cstat
ret

;
***************************************************************************
;*
;* PROGRAM
;* main - Test of I2C master implementation
;*
;* DESCRIPTION
;* Initializes I2C interface and shows an example of
using it.
;*
;
***************************************************************************

RESET:
main: rcall i2c_init ;
initialize I2C interface

;**** Write data => Adr(00) = 0x55 ****

ldi i2cadr,$A0+i2cwr ; Set device

address and write
rcall i2c_start ; Send start
condition and address

ldi i2cdata,$00 ; Write word

address (0x00)
rcall i2c_do_transfer ; Execute transfer

ldi i2cdata,$55 ; Set write data to

01010101b
rcall i2c_do_transfer ; Execute transfer

rcall i2c_stop ; Send stop

condition

;**** Read data => i2cdata = Adr(00) ****

ldi i2cadr,$A0+i2cwr ; Set device

address and write
rcall i2c_start ; Send start
condition and address

ldi i2cdata,$00 ; Write word address

rcall i2c_do_transfer ; Execute transfer

ldi i2cadr,$A0+i2crd ; Set device

address and read
rcall i2c_rep_start ; Send repeated
start condition and address

sec ; Set no
acknowledge (read is followed by a stop condition)
rcall i2c_do_transfer ; Execute transfer
(read)

rcall i2c_stop ; Send stop

condition - releases bus

rjmp main ; Loop forewer

;**** End of File ****

Programming the AVR Microcontrollers in Machine Language

AVR
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© WebRing Inc. Search

Atmel AVR From Wikipedia, the free encyclopedia (Redirected

from Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing,
intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still
be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15

http://avr-asm.tripod.com/avr300.html (1 of 2)1/20/2009 9:00:50 PM

16 BIT MATH (AVR 202)

have different addressing capabilities than register locations

R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language

http://avr-asm.tripod.com/avr300.html (2 of 2)1/20/2009 9:00:50 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

AVR I2C SLAVE PROTOCOL (AVR 302)

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;**** A P P L I C A T I O N N O T E A V R 3 0 2
ASM FORUM ************************
ASM MATH ;*
;* Title : I2C Slave Implementation
TUTORIAL #1
;* Version : 1.2
TUTORIAL #2 ;* Last updated : 97.07.17
TUTORIAL #3 ;* Target : AT90Sxxxx (All AVR Device)
;* Fast Mode: AT90S1200 only
MATH 200 ;*
MATH 200b ;* Support email : avr@atmel.com
;*
MATH 201 ;* Code Size : 160 words
MATH 202 ;* Low Register Usage : 0
;* High Register Usage : 5
MATH 32X
;* Interrupt Usage : External Interrupt0,
MATH YX ;* Timer/Counter0 overflow interrupt
;*
DIV16 XX
;* DESCRIPTION
DIV 24 24 ;* This application note shows how to implement an AVR
DIV 3216 AT90S1200 device
;* as an I2C slave peripheral. For use with other
FLOAT 128 AT90S AVR devices, other
SQRT16 ;* I/O pins might have to be used, and the stack
pointer might have to be
MATH 202 ;* initialized.
MATH 202 ;* Received data is stored in r0 and r0 is transmitted
during a master
DEC ASCII
;* read transfer. This simple protocol is implemented
INT ASCII for demonstration
;* purposes only.
HX2ASC
;*
AVG8 222 ;* Some features :
FFT7 ;* * Interrupt based (using INT0 and TIM0).
;* * The device can be given any 7-bit address.
COPY 102 (Expandable to 10bit).
LPM 108 ;* * Supports normal and fast mode.
;* * Easy insertion of "wait states".
EPROM 100 ;* * Size and speed optimized.
SER EPROM ;* * Supports wake-up from idle mode.
;*
DFLASH AT45
;* Refers to the application note AVR302 documentation
FLASH CARD for more
;* detailed description.
VFX SMIL
;*
VFX MEM ;* USAGE
SORT 220 ;* Insert user code in the two locations marked
"insert user code here".
CRC 236 ;*
XMODEM REC ;* NOTES
;* Minimum one instruction will be executed between
UART 304 each interrupt.
UART 305 ;*
;* STATISTICS
UART 128
;* Code Size : 160
UART BUFF ;* Register Usage : 5 High, 0 Low
USB 232 ;* Interrupt Usage : EXT_INT0 and TIM0_OVF
;* Port Usage : PD4(T0) and PD2(INT0)
AVR ISP ;* XTAL : - I2C Fast Mode : min 16.0MHz
ISP 2313 ;* - I2C Standard Mode : min 3.0MHz
;*
ISP 1200 ;
AVR SPI ***************************************************************************
I2C 300 ;**** Includes ****
I2C 302
.include "1200def.inc"
I2C TWI26
I2C/TWI 128 ;**** Global I2C Constants ****
I2C/TWI AT8
.equ devadr = 0x50 ; Slave device
DALLAS-1W address
DALLAS CRC .equ devadrm = 0x7F ; Slave multi
address mask
ETHNET 8019
TEA .equ pinmask = 0x14 ; <=> (1<
ADC 128
ADC 10B
ADC 400
ADC 401
THERM 232
IRD 410
LCD HD44
LCD 2313
LCD44 2313
Programming the AVR Microcontrollers in Machine Language
KBD 240
MUX 242
AVR
KBD PS2
<< Prev | Ring Hub | Join | Rate| Next
KBD PC/128 >>
PS2 EMU © WebRing Inc. Search
BOOT MG8
BOOT DR8
ALM CLK Atmel AVR From Wikipedia, the free encyclopedia (Redirected
CLOCK 8564 from Avr) Jump to: navigation, search The AVRs are a family
90 DAYS
DELAYS
of RISC microcontrollers from Atmel. Their internal
CALL ID architecture was conceived by two students: Alf-Egil Bogen
DTMF 314 and Vegard Wollan, at the Norwegian Institute of Technology
PWM 6CH
PWM 10K
(NTH] and further developed at Atmel Norway, a subsidiary
ENCODE founded by the two architects. Atmel recently released the
STH-11 Atmel AVR32 line of microcontrollers. These are 32-bit RISC
ATMEL CORP
AVR
devices featuring SIMD and DSP instructions, along with
BUTTERFLY many additional features for audio and video processing,
AVR BOOK
intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still
be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language

http://avr-asm.tripod.com/avr302.html (1 of 2)1/20/2009 9:01:29 PM

16 BIT MATH (AVR 202)

http://avr-asm.tripod.com/avr302.html (2 of 2)1/20/2009 9:01:29 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

I2C/TWI PROTOCOL FOR ATINY26

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ASM FORUM .include "tn26def.inc"
ASM MATH
TUTORIAL #1
TUTORIAL #2 .org $0000
TUTORIAL #3 rjmp reset ;(1)
;.org INT0addr
MATH 200 ;rjmp EXT_INT0 ;(2)
MATH 200b .org OC1Aaddr
rjmp TIMER1_CMPA ;(4)
MATH 201 ;.org OVF0addr
MATH 202 ;rjmp TIMER0_OVF0 ;(7)
.org USI_STARTaddr
MATH 32X
rjmp USI_STRT ;(8)
MATH YX .org USI_OVFaddr
rjmp USI_OVF ;(9)
DIV16 XX
DIV 24 24
DIV 3216 ;Cal=0x99

FLOAT 128 .equ OwnTWIAddress =11;16

SQRT16
.equ UserRAM =$0060
MATH 202 .equ USI_State =UserRAM
MATH 202 .equ AddressAndWR =UserRAM+1
.equ USI_ByteReceivedPointerLow =UserRAM+2
DEC ASCII
.equ USI_ByteReceivedPointerHigh =UserRAM+3
INT ASCII .equ USI_Byte0 =UserRAM+4
.equ USI_Byte1 =UserRAM+5
HX2ASC
.equ USI_Byte2 =UserRAM+6
AVG8 222 .equ USI_Byte3 =UserRAM+7
FFT7
COPY 102
LPM 108 reset:
EPROM 100 ;*** Init at startup ***
SER EPROM
;Clear RAM at startup
DFLASH AT45
clr r16
FLASH CARD sts USI_State,r16
sts USI_Byte0,r16
VFX SMIL
sts USI_Byte1,r16
VFX MEM sts USI_Byte2,r16
SORT 220 sts USI_Byte3,r16

CRC 236 ldi r16,RAMEND ;Setting stackpointer to RAM end

XMODEM REC out SP,
r16
UART 304
UART 305 ;*** MCUCR ***
;MCU Control Register MCUCR
UART 128
;Bit1,Bit0=ISC01,ISC00: Interrupt Sense Control (11=rising edge)
UART BUFF ldi r16,(1< 40 kHz) ;xxx
USB 232 ldi
r16,255 ;
AVR ISP xxx
ISP 2313 out OCR1C,r16

ISP 1200 ;*** USI ***

AVR SPI ;USI Control Register: USICR
;Bit7=USISIE: Start Condition Interrupt Enable
I2C 300 ;Bit6=USIOIE: Counter Overflow Interrupt Enable
I2C 302 ;Bit5,Bit4=USIWM1,USIWM0: Wire Mode (11=TWI)
;Bit3,Bit2=USICS1,USICS0: Clock Source Select (110=Negative edge External,
I2C TWI26
TWI)
I2C/TWI 128 ;Bit1=USICLK: Clock Strobe
I2C/TWI AT8 ;Bit0=USITC: Toggle Clock Port Pin
ldi r16,(1<
DALLAS-1W
DALLAS CRC
ETHNET 8019
TEA
ADC 128
ADC 10B
ADC 400
ADC 401
THERM 232
IRD 410 Programming the AVR Microcontrollers in Machine Language
LCD HD44
LCD 2313 AVR
LCD44 2313 << Prev | Ring Hub | Join | Rate| Next
KBD 240 >>
© WebRing Inc. Search
MUX 242
KBD PS2
KBD PC/128
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr)
PS2 EMU
BOOT MG8
Jump to: navigation, search The AVRs are a family of RISC microcontrollers
BOOT DR8 from Atmel. Their internal architecture was conceived by two students: Alf-
ALM CLK
Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology
CLOCK 8564
90 DAYS
(NTH] and further developed at Atmel Norway, a subsidiary founded by the
DELAYS two architects. Atmel recently released the Atmel AVR32 line of
CALL ID
microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP
DTMF 314
PWM 6CH
instructions, along with many additional features for audio and video
PWM 10K processing, intended to compete with ARM based processors. Note that the
ENCODE
use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR
STH-11
ATMEL CORP
Microcontrollers. The acronym AVR has been reported to stand for
AVR Advanced Virtual RISC. It's also rumoured to stand for the company's
BUTTERFLY
AVR BOOK
founders: Alf and Vegard, who are evasive when questioned about it.
Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory
and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2
Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel
Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other AVR
Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with programs and
data stored and addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external memory
(though still available on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory. Each instruction
for the AVR line is either 16 or 32 bits in length. The Flash memory is
addressed using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the ATmega64x
line has 64Kbytes of Flash. Almost all AVR devices are self-programmable.
[edit] Data Memory and Registers The data address space consists of the
register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-001F16) followed
by the 64 I/O registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O register space may
be larger on some more extensive devices, in which case memory mapped I/
O registers will occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for register file and I/
O register access, all can still be addressed and manipulated as if they were
in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be retrieved even after
cycling the power of the device. [edit] Program Execution Atmel's AVRs
have a single level pipeline design. The next machine instruction is fetched
as the current one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit microcontrollers.
The AVR family of processors were designed for the efficient execution of
compiled C code. The AVR instruction set is more orthogonal than most
eight-bit microcontrollers, however, it is not completely regular: Pointer
registers X, Y, and Z have addressing capabilities that are different from
each other. Register locations R0 to R15 have different addressing
capabilities than register locations R16 to R31. I/O ports 0 to 31 have
different addressing capabilities than I/O ports 32 to 63. CLR affects flags,
while SER does not, even though they are complementary instructions. CLR
set all bits to zero and SER sets them to one. (Note though, that neither CLR
nor SER are native instructions. Instead CLR is syntactic sugar for
[produces the same machine code as] EOR R,R while SER is syntactic
sugar for LDI R,$FF. Math operations such as EOR modify flags while
moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR
line can normally support clock speeds from 0-16MHz, with some devices
reaching 20MHz. Lower powered operation usually requires a reduced clock
speed. All AVRs feature an on-chip oscillator, removing the need for
external clocks or resonator circuitry. Because many operations on the AVR
are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit]
Development AVRs have a large following due to the free and inexpensive
development tools available, including reasonably priced development
boards and free development software. The AVRs are marketed under
various names that share the same basic core but with different peripheral
and memory combinations. Some models (notably, the ATmega range) have
additional instructions to make arithmetic faster. Compatibility amongst
chips is fairly good. See external links for sites relating to AVR
development. [edit] Features Current AVRs offer a wide range of features:
RISC Core Running Many Single Cycle Instructions Multifunction, Bi-
directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple
Internal Oscillators Internal, Self-Programmable Instruction Flash Memory
up to 256K In-System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock Bits for
Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit
and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM
Specific) Controller models Dedicated I²C Compatible Two-Wire Interface
(TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As
used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed hardware &
Hub controller with embedded AVR. Also freely available low-speed (HID)
software emulation Ethernet Controller Support Universal Serial Interface
(USI) for Two or Three-Wire Synchronous Data Transfer Analog
Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex
of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-
voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep
Modes picoPower Devices Atmel AVR assembler programming language
Atmel AVR machine programming language Atmel AVR From Wikipedia, the
free encyclopedia (Redirected from Avr) Jump to: navigation, search The
AVRs are a family of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen and Vegard
Wollan, at the Norwegian Institute of Technology (NTH] and further
developed at Atmel Norway, a subsidiary founded by the two architects.
Atmel recently released the Atmel AVR32 line of microcontrollers. These are
32-bit RISC devices featuring SIMD and DSP instructions, along with many
additional features for audio and video processing, intended to compete
with ARM based processors. Note that the use of "AVR" in this article refers
to the 8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has
been reported to stand for Advanced Virtual RISC. It's also rumoured to
stand for the company's founders: Alf and Vegard, who are evasive when
questioned about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program
Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion
Groups 6.3 Machine Language Development 6.4 C Language Development
6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard architecture machine
with programs and data stored and addressed separately. Flash, EEPROM,
and SRAM are all integrated onto a single die, removing the need for
external memory (though still available on some devices). [edit] Program
Memory Program instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in length. The Flash
memory is addressed using 16 bit word sizes. The size of the program
memory is indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data address space
consists of the register file, I/O registers, and SRAM. The AVRs have thirty-
two single-byte registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two memory spaces
(000016-001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address 006016). (Note
that the I/O register space may be larger on some more extensive devices,
in which case memory mapped I/O registers will occupy a portion of the
SRAM.) Even though there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM Almost all devices
have on-die EEPROM. This is most often used for long-term parameter
storage to be retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline design. The
next machine instruction is fetched as the current one is executing. Most
instructions take just one or two clock cycles, making AVRs relatively fast
among the eight-bit microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The AVR
instruction set is more orthogonal than most eight-bit microcontrollers,
however, it is not completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other. Register
locations R0 to R15 have different addressing capabilities than register
locations R16 to R31. I/O ports 0 to 31 have different addressing capabilities
than I/O ports 32 to 63. CLR affects flags, while SER does not, even though
they are complementary instructions. CLR set all bits to zero and SER sets
them to one. (Note though, that neither CLR nor SER are native instructions.
Instead CLR is syntactic sugar for [produces the same machine code as]
EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations such
as EOR modify flags while moves/loads/stores/branches such as LDI do
not.) [edit] Speed The AVR line can normally support clock speeds from 0-
16MHz, with some devices reaching 20MHz. Lower powered operation
usually requires a reduced clock speed. All AVRs feature an on-chip
oscillator, removing the need for external clocks or resonator circuitry.
Because many operations on the AVR are single cycle, the AVR can achieve
up to 1MIPS per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available, including
reasonably priced development boards and free development software. The
AVRs are marketed under various names that share the same basic core but
with different peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make arithmetic faster.
Compatibility amongst chips is fairly good. See external links for sites
relating to AVR development. [edit] Features Current AVRs offer a wide
range of features: RISC Core Running Many Single Cycle Instructions
Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-Programmable
Instruction Flash Memory up to 256K In-System Programmable using ICSP,
JTAG, or High Voltage methods Optional Boot Code Section with
Independent Lock Bits for Protection Internal Data EEPROM up to 4KB
Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time
generator Lighting (PWM Specific) Controller models Dedicated I²C
Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial
Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB Controller Support
Proper High-speed hardware & Hub controller with embedded AVR. Also
freely available low-speed (HID) software emulation Ethernet Controller
Support Universal Serial Interface (USI) for Two or Three-Wire Synchronous
Data Transfer Analog Comparators LCD Controller Support 10-Bit A/D
Converters, with multiplex of up to 16 channels Brownout Detection
Watchdog Timer (WDT) Low-voltage Devices Operating Down to 1.8v
Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine programming
language Atmel AVR From Wikipedia, the free encyclopedia (Redirected
from Avr) Jump to: navigation, search The AVRs are a family of RISC
microcontrollers from Atmel. Their internal architecture was conceived by
two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute
of Technology (NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the Atmel AVR32
line of microcontrollers. These are 32-bit RISC devices featuring SIMD and
DSP instructions, along with many additional features for audio and video
processing, intended to compete with ARM based processors. Note that the
use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR
Microcontrollers. The acronym AVR has been reported to stand for
Advanced Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned about it.
Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory
and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2
Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel
Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other AVR
Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with programs and
data stored and addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external memory
(though still available on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory. Each instruction
for the AVR line is either 16 or 32 bits in length. The Flash memory is
addressed using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the ATmega64x
line has 64Kbytes of Flash. Almost all AVR devices are self-programmable.
[edit] Data Memory and Registers The data address space consists of the
register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-001F16) followed
by the 64 I/O registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O register space may
be larger on some more extensive devices, in which case memory mapped I/
O registers will occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for register file and I/
O register access, all can still be addressed and manipulated as if they were
in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be retrieved even after
cycling the power of the device. [edit] Program Execution Atmel's AVRs
have a single level pipeline design. The next machine instruction is fetched
as the current one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit microcontrollers.
The AVR family of processors were designed for the efficient execution of
compiled C code. The AVR instruction set is more orthogonal than most
eight-bit microcontrollers, however, it is not completely regular: Pointer
registers X, Y, and Z have addressing capabilities that are different from
each other. Register locations R0 to R15 have different addressing
capabilities than register locations R16 to R31. I/O ports 0 to 31 have
different addressing capabilities than I/O ports 32 to 63. CLR affects flags,
while SER does not, even though they are complementary instructions. CLR
set all bits to zero and SER sets them to one. (Note though, that neither CLR
nor SER are native instructions. Instead CLR is syntactic sugar for
[produces the same machine code as] EOR R,R while SER is syntactic
sugar for LDI R,$FF. Math operations such as EOR modify flags while
moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR
line can normally support clock speeds from 0-16MHz, with some devices
reaching 20MHz. Lower powered operation usually requires a reduced clock
speed. All AVRs feature an on-chip oscillator, removing the need for
external clocks or resonator circuitry. Because many operations on the AVR
are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit]
Development AVRs have a large following due to the free and inexpensive
development tools available, including reasonably priced development
boards and free development software. The AVRs are marketed under
various names that share the same basic core but with different peripheral
and memory combinations. Some models (notably, the ATmega range) have
additional instructions to make arithmetic faster. Compatibility amongst
chips is fairly good. See external links for sites relating to AVR
development. [edit] Features Current AVRs offer a wide range of features:
RISC Core Running Many Single Cycle Instructions Multifunction, Bi-
directional I/O Ports with Internal, Configurable Pull-up Resistors Multiple
Internal Oscillators Internal, Self-Programmable Instruction Flash Memory
up to 256K In-System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock Bits for
Protection Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit
and 16-Bit Timers PWM Channels & dead time generator Lighting (PWM
Specific) Controller models Dedicated I²C Compatible Two-Wire Interface
(TWI) Synchronous/Asynchronous Serial Peripherals (UART/USART) (As
used with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed hardware &
Hub controller with embedded AVR. Also freely available low-speed (HID)
software emulation Ethernet Controller Support Universal Serial Interface
(USI) for Two or Three-Wire Synchronous Data Transfer Analog
Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex
of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-
voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep
Modes picoPower Devices Atmel AVR assembler programming language
Atmel AVR machine programming language
http://avr-asm.tripod.com/twi26.html (1 of 2)1/20/2009 9:02:06 PM
16 BIT MATH (AVR 202)

http://avr-asm.tripod.com/twi26.html (2 of 2)1/20/2009 9:02:06 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

I2C/TWI PROTOCOL FOR 128

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;
ASM FORUM ***************************************************************************
ASM MATH ;
; File Name :'twi.asm"
TUTORIAL #1
; Title : I2C (TWI) Hardware
TUTORIAL #2 ; Date :2003.04.29. Lastmod.:[2003.04.29.]
TUTORIAL #3 ; Version :1.0.0
; Support telephone :+36-70-333-4034, Old: +36-30-9541-658 VFX
MATH 200 ; Support fax :
MATH 200b ; Support Email :info@vfx.hu
; Target MCU :ATmaga128
MATH 201 ;
MATH 202 ;
***************************************************************************
MATH 32X
; D E S C R I P T I O N
MATH YX ;
;
DIV16 XX
;
DIV 24 24 ;
DIV 3216 ***************************************************************************
; M O D I F I C A T I O N H I S T O R Y
FLOAT 128 ;
SQRT16 ;
; rev. date who why
MATH 202 ; ---- ---------- ---
MATH 202 --------------------------------------------
; 0.01 2003.04.29 VFX Creation
DEC ASCII
;
INT ASCII ;
***************************************************************************
HX2ASC
;
AVG8 222 ;
FFT7 ;
;Hardware
COPY 102 ;
LPM 108 ***************************************************************************
;*
EPROM 100
SER EPROM
;
DFLASH AT45
**************************************************************************
FLASH CARD ;* Const Def
;
VFX SMIL
;Bit Rate Generator in Master Mode
VFX MEM ;TWBR = Value of the TWI Bit Rate Register
SORT 220 ;TWPS = Value of the prescaler bits in the TWI Status Register
;
CRC 236 ;Note: TWBR should be 10 or higher if the TWI operates in Master mode.
XMODEM REC ; If TWBR is lower than 10, the master may produce an incorrect output
on SDA
UART 304 ; and SCL for the reminder of the byte.
UART 305 ;
; SCL = SYSCLK/(16+2*TWBR*4^TWPS) , TWPS= 0..3, TWBR= 0..255
UART 128
;
UART BUFF ; we use 100kHz I2C Bus & TWPS = 0, always for LOW Power
USB 232
.EQU SCL_Freq = 100000 ;Hz
AVR ISP .EQU TWI_SlaveAddress = 0xFE ;Slave Address is FECO :)
ISP 2313
ISP 1200 .equ TWI_WriteByte = 0x00 ;Send Byte
AVR SPI .equ TWI_WriteRAW = 0x01 ;Send Blokk of data
.equ TWI_ReadByte = 0x02 ;Read Byte
I2C 300 .equ TWI_ReadRAW = 0x03 ;Read Block of data
I2C 302
I2C TWI26
;
I2C/TWI 128 ***************************************************************************
I2C/TWI AT8 .DSEG

DALLAS-1W TWI_CTL: .byte 2 ;Address of TWI IO Control Blokk

DALLAS CRC TWI_Count: .byte 1 ;Byte counter for TWI
TWI_Slave: .byte 1 ;Slave Address
ETHNET 8019 TWI_ADR: .byte 1 ;Slave internal Address
TEA TWI_Flag: .byte 1 ;0. = 1 TWI in use
TWI_SADR: .byte 2 ;TWI State Machin Address
ADC 128
ADC 10B
ADC 400
;
ADC 401 *************************************************************************
THERM 232 ;* Code
;*
IRD 410 .CSEG
LCD HD44
;
LCD 2313 *************************************************************************
LCD44 2313 ;* Init TWI Device, Clear TWI_CTL
;
KBD 240 TWI_Init:
MUX 242 ldi R16,Low(TWIRET)
sts TWI_SADR+0,R16
KBD PS2
ldi R16,High(TWIRET)
KBD PC/128 sts TWI_SADR+1,R16
PS2 EMU
ldi R16,SYSCLK/(2*SCL_Freq)-8 ;TWI Bit Rate
BOOT MG8 Register - TWBR
BOOT DR8 sts TWBR,R16
ldi R16,0b00000101 ;TWI Control
ALM CLK Register – TWCR
CLOCK 8564 sts TWCR,R16 ;7 – TWINT: TWI
Interrupt Flag
90 DAYS
;6 – TWEA: TWI
DELAYS Enable Acknowledge
;5 – TWSTA: TWI
CALL ID
START Condition
DTMF 314 ;4 – TWSTO: TWI
PWM 6CH STOP Condition
;3 - TWWC: TWI
PWM 10K Write Collision Flag
ENCODE ;2 – TWEN: TWI
Enable
STH-11 ;1 – Res: Reserved
ATMEL CORP Bit
;0 – TWIE: TWI
AVR
Interrupt Enable
BUTTERFLY
AVR BOOK ldi R16,0b11111000 ;TWI Status
Register – TWSR
sts TWSR,R16 ;7..3 – TWS: TWI
Status
;2 – Res: Reserved
Bit
;1..0 – TWPS: TWI
Prescaler Bits

ldi R16,TWI_SlaveAddress ;TWI (Slave)

Address Register
sts TWAR,R16
clr R16
sts TWI_Flag,R16
ret

;
*************************************************************************
;* Start TWI Comunication in Master Mode
; In: X - Address of IO_CTR Block
;
; R17 - count of byte
; R18 - Slave Address
; R19 - Internal Address of Slave
; Out: c = 1 error
;
TWI_StartRead:
rcall WaitToTWI

ldi R16,Low(RBlock0)
sts TWI_SADR+0,R16
ldi R16,High(RBlock0)
sts TWI_SADR+1,R16
TWI_Common:
sts TWI_CTL+0,XL
sts TWI_CTL+1,XH
sts TWI_Count,R17
sts TWI_Slave,R18
sts TWI_ADR,R19

lds R16,TWI_Flag
ori R16,1 ;TWI in use!
andi R16,0b11111101 ;TWI no error
sts TWI_Flag,R16

ldi R16,0b11100101
sts TWCR,R16 ;7 – TWINT: TWI
Interrupt Flag
;6 – TWEA: TWI
Enable Acknowledge
;5 – TWSTA: TWI
START Condition
;4 – TWSTO: TWI
STOP Condition
;3 – TWWC: TWI
Write Collision
;2 – TWEN: TWI
Enable
;1 – Res: Reserved
;0 – TWIE: TWI
Interrupt Enable
TWIRET:
ret

;
*************************************************************************
;* Start TWI Comunication in Master Mode - Write!
; In: X - Address of IO_CTR Block
; R17 - count of byte
; R18 - Slave Address
; R19 - Internal Address of Slave
; Out: c = 1 error
;
TWI_StartWrite:
rcall WaitToTWI

ldi R16,Low(WBlock0)
sts TWI_SADR+0,R16
ldi R16,High(WBlock0)
sts TWI_SADR+1,R16
rjmp TWI_Common

;
*************************************************************************
;* TWI interrupt
;*
TWI: ; Two-wire Serial Interface
Interrupt Handler
push ZL
push ZH
in ZL,SREG ;preserve main OS status
reg.
push ZL
push R16
push R0
push R17
in ZL,RAMPZ
push ZL

lds R16,TWSR ;Load TWI Status

andi R16,0b11111000 ;csak a status marad

lds ZL,TWI_SADR+0
lds ZH,TWI_SADR+1
icall

pop ZL
out RAMPZ,ZL
pop R17
POP R0
POP R16
POP ZL
OUT SREG,ZL
POP ZH
POP ZL
RETI

;
************************************************************************************************************
;*** R E A D B L O C K
;***
;
;***********************
; Read Block of data - State 0
; Start bit sended
RBlock0:
cpi R16,0x08 ;A
START condition has been transmitted
breq Rbl0
cpi R16,0x10 ;A
Repeated START condition has been transmitted
breq Rbl0
rjmp TWI_ReadError
Rbl0:
lds R16,TWI_Slave
andi R16,0b11111110 ;Write SLA
sts TWDR,R16 ;Send Slave
Address

ldi R16,Low(RBlock1)
sts TWI_SADR+0,R16
ldi R16,High(RBlock1)
sts TWI_SADR+1,R16

ldi R16,(1< Send slave internal address

RBlock1:
cpi R16,0x18 ;SLA
+W has been transmitted
breq RBl1
rjmp TWI_ReadError
RBl1:
lds R16,TWI_ADR
sts TWDR,R16 ;Send Slave
Internal Address

ldi R16,Low(RBlock2)
sts TWI_SADR+0,R16
ldi R16,High(RBlock2)
sts TWI_SADR+1,R16
ldi R16,(1< Repeated Satrt send
RBlock2:
cpi R16,0x28 ;
SlaveAddress sended + ACK received
breq Rbl21
rjmp TWI_ReadError
Rbl21:
ldi R16,Low(RBlock3)
sts TWI_SADR+0,R16
ldi R16,High(RBlock3)
sts TWI_SADR+1,R16

ldi R16,(1< Send SLA+R

RBlock3:
cpi R16,0x10 ;Repeated
Start sended + ACK received
breq RBl31
rjmp TWI_ReadError
RBl31:
lds R16,TWI_Slave
ori R16,1 ;Write SLA+R
sts TWDR,R16 ;Send Slave
Address

ldi R16,Low(RBlock4)
sts TWI_SADR+0,R16
ldi R16,High(RBlock4)
sts TWI_SADR+1,R16

ldi R16,(1< Read data byte

RBlock4:
cpi R16,0x40 ;SLA+R send
+ ACK received
brne TWI_ReadError

lds R16,TWI_Count
cpi R16,1
breq TWILAstByte

ldi R16,Low(RBlock5)
sts TWI_SADR+0,R16
ldi R16,High(RBlock5)
sts TWI_SADR+1,R16

ldi R16,(1< Send slave internal address

WBlock1:
cpi R16,0x18 ;SLA
+W has been transmitted
breq WBl1
rjmp TWI_WriteError
WBl1:
lds R16,TWI_ADR
sts TWDR,R16 ;Send Slave
Internal Address

ldi R16,Low(WBlock2)
sts TWI_SADR+0,R16
ldi R16,High(WBlock2)
sts TWI_SADR+1,R16
ldi R16,(1< Write data
WBlock2:
cpi R16,0x28 ;Data byte
has been transmitted + ACK received
breq WB12
rjmp TWI_WriteError
WB12: ;
Send data byte continous
lds ZL,TWI_CTL+0
lds ZH,TWI_CTL+1
ld R0,Z+
sts TWDR,R0 ;next data
byte
sts TWI_CTL+0,ZL
sts TWI_CTL+1,ZH

lds R16,TWI_Count
cpi R16,1
breq TWI_WriteLastByte
dec R16
sts TWI_Count,R16

ldi R16,(1<

Programming the AVR Microcontrollers in Machine Language

AVR
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr)
Jump to: navigation, search The AVRs are a family of RISC
microcontrollers from Atmel. Their internal architecture was conceived
by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel Norway, a
subsidiary founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices
featuring SIMD and DSP instructions, along with many additional
features for audio and video processing, intended to compete with ARM
based processors. Note that the use of "AVR" in this article refers to the
8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has
been reported to stand for Advanced Virtual RISC. It's also rumoured to
stand for the company's founders: Alf and Vegard, who are evasive
when questioned about it. Contents [hide] 1 Device Overview 1.1
Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5
See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C Language
Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly
Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a
Harvard architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all integrated onto
a single die, removing the need for external memory (though still
available on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory. Each
instruction for the AVR line is either 16 or 32 bits in length. The Flash
memory is addressed using 16 bit word sizes. The size of the program
memory is indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data address
space consists of the register file, I/O registers, and SRAM. The AVRs
have thirty-two single-byte registers and are classified as 8-bit RISC
devices. The working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O registers (002016-
005F16). The actual usable RAM starts after both these sections
(address 006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped I/O
registers will occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for register file
and I/O register access, all can still be addressed and manipulated as if
they were in SRAM. [edit] EEPROM Almost all devices have on-die
EEPROM. This is most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design. The next
machine instruction is fetched as the current one is executing. Most
instructions take just one or two clock cycles, making AVRs relatively
fast among the eight-bit microcontrollers. The AVR family of processors
were designed for the efficient execution of compiled C code. The AVR
instruction set is more orthogonal than most eight-bit microcontrollers,
however, it is not completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other. Register
locations R0 to R15 have different addressing capabilities than register
locations R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while SER does
not, even though they are complementary instructions. CLR set all bits
to zero and SER sets them to one. (Note though, that neither CLR nor
SER are native instructions. Instead CLR is syntactic sugar for
[produces the same machine code as] EOR R,R while SER is syntactic
sugar for LDI R,$FF. Math operations such as EOR modify flags while
moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR
line can normally support clock speeds from 0-16MHz, with some
devices reaching 20MHz. Lower powered operation usually requires a
reduced clock speed. All AVRs feature an on-chip oscillator, removing
the need for external clocks or resonator circuitry. Because many
operations on the AVR are single cycle, the AVR can achieve up to
1MIPS per MHz. [edit] Development AVRs have a large following due to
the free and inexpensive development tools available, including
reasonably priced development boards and free development software.
The AVRs are marketed under various names that share the same basic
core but with different peripheral and memory combinations. Some
models (notably, the ATmega range) have additional instructions to
make arithmetic faster. Compatibility amongst chips is fairly good. See
external links for sites relating to AVR development. [edit] Features
Current AVRs offer a wide range of features: RISC Core Running Many
Single Cycle Instructions Multifunction, Bi-directional I/O Ports with
Internal, Configurable Pull-up Resistors Multiple Internal Oscillators
Internal, Self-Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage methods
Optional Boot Code Section with Independent Lock Bits for Protection
Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit
Timers PWM Channels & dead time generator Lighting (PWM Specific)
Controller models Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used
with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed hardware
& Hub controller with embedded AVR. Also freely available low-speed
(HID) software emulation Ethernet Controller Support Universal Serial
Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog
Comparators LCD Controller Support 10-Bit A/D Converters, with
multiplex of up to 16 channels Brownout Detection Watchdog Timer
(WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR assembler
programming language Atmel AVR machine programming language
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr)
Jump to: navigation, search The AVRs are a family of RISC
microcontrollers from Atmel. Their internal architecture was conceived
by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel Norway, a
subsidiary founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices
featuring SIMD and DSP instructions, along with many additional
features for audio and video processing, intended to compete with ARM
based processors. Note that the use of "AVR" in this article refers to the
8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has
been reported to stand for Advanced Virtual RISC. It's also rumoured to
stand for the company's founders: Alf and Vegard, who are evasive
when questioned about it. Contents [hide] 1 Device Overview 1.1
Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5
See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C Language
Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly
Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a
Harvard architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all integrated onto
a single die, removing the need for external memory (though still
available on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory. Each
instruction for the AVR line is either 16 or 32 bits in length. The Flash
memory is addressed using 16 bit word sizes. The size of the program
memory is indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data address
space consists of the register file, I/O registers, and SRAM. The AVRs
have thirty-two single-byte registers and are classified as 8-bit RISC
devices. The working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O registers (002016-
005F16). The actual usable RAM starts after both these sections
(address 006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped I/O
registers will occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for register file
and I/O register access, all can still be addressed and manipulated as if
they were in SRAM. [edit] EEPROM Almost all devices have on-die
EEPROM. This is most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design. The next
machine instruction is fetched as the current one is executing. Most
instructions take just one or two clock cycles, making AVRs relatively
fast among the eight-bit microcontrollers. The AVR family of processors
were designed for the efficient execution of compiled C code. The AVR
instruction set is more orthogonal than most eight-bit microcontrollers,
however, it is not completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other. Register
locations R0 to R15 have different addressing capabilities than register
locations R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while SER does
not, even though they are complementary instructions. CLR set all bits
to zero and SER sets them to one. (Note though, that neither CLR nor
SER are native instructions. Instead CLR is syntactic sugar for
[produces the same machine code as] EOR R,R while SER is syntactic
sugar for LDI R,$FF. Math operations such as EOR modify flags while
moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR
line can normally support clock speeds from 0-16MHz, with some
devices reaching 20MHz. Lower powered operation usually requires a
reduced clock speed. All AVRs feature an on-chip oscillator, removing
the need for external clocks or resonator circuitry. Because many
operations on the AVR are single cycle, the AVR can achieve up to
1MIPS per MHz. [edit] Development AVRs have a large following due to
the free and inexpensive development tools available, including
reasonably priced development boards and free development software.
The AVRs are marketed under various names that share the same basic
core but with different peripheral and memory combinations. Some
models (notably, the ATmega range) have additional instructions to
make arithmetic faster. Compatibility amongst chips is fairly good. See
external links for sites relating to AVR development. [edit] Features
Current AVRs offer a wide range of features: RISC Core Running Many
Single Cycle Instructions Multifunction, Bi-directional I/O Ports with
Internal, Configurable Pull-up Resistors Multiple Internal Oscillators
Internal, Self-Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage methods
Optional Boot Code Section with Independent Lock Bits for Protection
Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit
Timers PWM Channels & dead time generator Lighting (PWM Specific)
Controller models Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used
with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed hardware
& Hub controller with embedded AVR. Also freely available low-speed
(HID) software emulation Ethernet Controller Support Universal Serial
Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog
Comparators LCD Controller Support 10-Bit A/D Converters, with
multiplex of up to 16 channels Brownout Detection Watchdog Timer
(WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR assembler
programming language Atmel AVR machine programming language
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr)
Jump to: navigation, search The AVRs are a family of RISC
microcontrollers from Atmel. Their internal architecture was conceived
by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel Norway, a
subsidiary founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices
featuring SIMD and DSP instructions, along with many additional
features for audio and video processing, intended to compete with ARM
based processors. Note that the use of "AVR" in this article refers to the
8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has
been reported to stand for Advanced Virtual RISC. It's also rumoured to
stand for the company's founders: Alf and Vegard, who are evasive
when questioned about it. Contents [hide] 1 Device Overview 1.1
Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5
See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C Language
Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly
Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a
Harvard architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all integrated onto
a single die, removing the need for external memory (though still
available on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory. Each
instruction for the AVR line is either 16 or 32 bits in length. The Flash
memory is addressed using 16 bit word sizes. The size of the program
memory is indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data address
space consists of the register file, I/O registers, and SRAM. The AVRs
have thirty-two single-byte registers and are classified as 8-bit RISC
devices. The working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O registers (002016-
005F16). The actual usable RAM starts after both these sections
(address 006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped I/O
registers will occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for register file
and I/O register access, all can still be addressed and manipulated as if
they were in SRAM. [edit] EEPROM Almost all devices have on-die
EEPROM. This is most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design. The next
machine instruction is fetched as the current one is executing. Most
instructions take just one or two clock cycles, making AVRs relatively
fast among the eight-bit microcontrollers. The AVR family of processors
were designed for the efficient execution of compiled C code. The AVR
instruction set is more orthogonal than most eight-bit microcontrollers,
however, it is not completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other. Register
locations R0 to R15 have different addressing capabilities than register
locations R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while SER does
not, even though they are complementary instructions. CLR set all bits
to zero and SER sets them to one. (Note though, that neither CLR nor
SER are native instructions. Instead CLR is syntactic sugar for
[produces the same machine code as] EOR R,R while SER is syntactic
sugar for LDI R,$FF. Math operations such as EOR modify flags while
moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR
line can normally support clock speeds from 0-16MHz, with some
devices reaching 20MHz. Lower powered operation usually requires a
reduced clock speed. All AVRs feature an on-chip oscillator, removing
the need for external clocks or resonator circuitry. Because many
operations on the AVR are single cycle, the AVR can achieve up to
1MIPS per MHz. [edit] Development AVRs have a large following due to
the free and inexpensive development tools available, including
reasonably priced development boards and free development software.
The AVRs are marketed under various names that share the same basic
core but with different peripheral and memory combinations. Some
models (notably, the ATmega range) have additional instructions to
make arithmetic faster. Compatibility amongst chips is fairly good. See
external links for sites relating to AVR development. [edit] Features
Current AVRs offer a wide range of features: RISC Core Running Many
Single Cycle Instructions Multifunction, Bi-directional I/O Ports with
Internal, Configurable Pull-up Resistors Multiple Internal Oscillators
Internal, Self-Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage methods
Optional Boot Code Section with Independent Lock Bits for Protection
Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit
Timers PWM Channels & dead time generator Lighting (PWM Specific)
Controller models Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used
with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed hardware
& Hub controller with embedded AVR. Also freely available low-speed
(HID) software emulation Ethernet Controller Support Universal Serial
Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog
Comparators LCD Controller Support 10-Bit A/D Converters, with

http://avr-asm.tripod.com/twi128.html (1 of 2)1/20/2009 9:02:45 PM

16 BIT MATH (AVR 202)

multiplex of up to 16 channels Brownout Detection Watchdog Timer

(WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR assembler
programming language Atmel AVR machine programming language

http://avr-asm.tripod.com/twi128.html (2 of 2)1/20/2009 9:02:45 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

I2C/TWI PROTOCOL FOR ATEMGA8

HOME
RETRO_DAN
;
ASM FORUM ***************************************************************************
ASM MATH ;
; File Name :'twi.asm"
TUTORIAL #1
; Title : I2C (TWI) Hardware
TUTORIAL #2 ; Date :2003.04.29. Lastmod.:[2003.04.29.]
TUTORIAL #3 ; Version :1.0.0
; Support telephone :+36-70-333-4034, Old: +36-30-9541-658 VFX
MATH 200 ; Support fax :
MATH 200b ; Support Email :info@vfx.hu
; Target MCU :ATmaga8
MATH 201 ;
MATH 202 ;
***************************************************************************
MATH 32X
; D E S C R I P T I O N
MATH YX ;
;
DIV16 XX
;
DIV 24 24 ;
DIV 3216 ***************************************************************************
; M O D I F I C A T I O N H I S T O R Y
FLOAT 128 ;
SQRT16 ;
; rev. date who why
MATH 202 ; ---- ---------- ---
MATH 202 --------------------------------------------
; 0.01 2003.04.29 VFX Creation
DEC ASCII
;
INT ASCII ;
***************************************************************************
HX2ASC
;
AVG8 222 ;
FFT7 ;
;Hardware
COPY 102 ;
LPM 108 ***************************************************************************
;*
EPROM 100
SER EPROM
;
DFLASH AT45
**************************************************************************
FLASH CARD ;* Const Def
;
VFX SMIL
;Bit Rate Generator in Master Mode
VFX MEM ;TWBR = Value of the TWI Bit Rate Register
SORT 220 ;TWPS = Value of the prescaler bits in the TWI Status Register
;
CRC 236 ;Note: TWBR should be 10 or higher if the TWI operates in Master mode.
XMODEM REC ; If TWBR is lower than 10, the master may produce an incorrect output
on SDA
UART 304 ; and SCL for the reminder of the byte.
UART 305 ;
; SCL = SYSCLK/(16+2*TWBR*4^TWPS) , TWPS= 0..3, TWBR= 0..255
UART 128
;
UART BUFF ; we use 100kHz I2C Bus & TWPS = 0, always for LOW Power
USB 232
.EQU SCL_Freq = 100000 ;Hz
AVR ISP .EQU TWI_SlaveAddress = 0xFE ;Slave Address is FECO :)
ISP 2313
ISP 1200 .equ TWI_WriteByte = 0x00 ;Send Byte
AVR SPI .equ TWI_WriteRAW = 0x01 ;Send Blokk of data
.equ TWI_ReadByte = 0x02 ;Read Byte
I2C 300 .equ TWI_ReadRAW = 0x03 ;Read Block of data
I2C 302
I2C TWI26
;
I2C/TWI 128 ***************************************************************************
I2C/TWI AT8 .DSEG

DALLAS-1W TWI_CTL: .byte 2 ;Address of TWI IO Control Blokk

DALLAS CRC TWI_Count: .byte 1 ;Byte counter for TWI
TWI_Slave: .byte 1 ;Slave Address
ETHNET 8019 TWI_ADR: .byte 1 ;Slave internal Address
TEA TWI_Flag: .byte 1 ;0. = 1 TWI in use
TWI_SADR: .byte 2 ;TWI State Machin Address
ADC 128
ADC 10B
ADC 400
;
ADC 401 *************************************************************************
THERM 232 ;* Code
;*
IRD 410 .CSEG
LCD HD44
;
LCD 2313 *************************************************************************
LCD44 2313 ;* Init TWI Device, Clear TWI_CTL
;
KBD 240 TWI_Init:
MUX 242 ldi R16,Low(TWIRET)
sts TWI_SADR+0,R16
KBD PS2
ldi R16,High(TWIRET)
KBD PC/128 sts TWI_SADR+1,R16
PS2 EMU
ldi R16,SYSCLK/(2*SCL_Freq)-8 ;TWI Bit Rate
BOOT MG8 Register - TWBR
BOOT DR8 out TWBR,R16
ldi R16,0b00000101 ;TWI Control
ALM CLK Register – TWCR
CLOCK 8564 out TWCR,R16 ;7 – TWINT: TWI
Interrupt Flag
90 DAYS
;6 – TWEA: TWI
DELAYS Enable Acknowledge
;5 – TWSTA: TWI
CALL ID
START Condition
DTMF 314 ;4 – TWSTO: TWI
PWM 6CH STOP Condition
;3 - TWWC: TWI
PWM 10K Write Collision Flag
ENCODE ;2 – TWEN: TWI
Enable
STH-11 ;1 – Res: Reserved
ATMEL CORP Bit
;0 – TWIE: TWI
AVR
Interrupt Enable
BUTTERFLY
AVR BOOK ldi R16,0b11111000 ;TWI Status
Register – TWSR
out TWSR,R16 ;7..3 – TWS: TWI
Status
;2 – Res: Reserved
Bit
;1..0 – TWPS: TWI
Prescaler Bits

ldi R16,TWI_SlaveAddress ;TWI (Slave)

Address Register
out TWAR,R16
clr R16
sts TWI_Flag,R16
ret

;
*************************************************************************
;* Start TWI Comunication in Master Mode
; In: X - Address of IO_CTR Block
;
; R17 - count of byte
; R18 - Slave Address
; R19 - Internal Address of Slave
; Out: c = 1 error
;
TWI_StartRead:
rcall WaitToTWI
ldi R16,Low(RBlock0)
sts TWI_SADR+0,R16
ldi R16,High(RBlock0)
sts TWI_SADR+1,R16
TWI_Common:
sts TWI_CTL+0,XL
sts TWI_CTL+1,XH
sts TWI_Count,R17
sts TWI_Slave,R18
sts TWI_ADR,R19

lds R16,TWI_Flag
ori R16,1 ;TWI in use!
andi R16,0b11111101 ;TWI no error
sts TWI_Flag,R16

ldi R16,0b11100101
out TWCR,R16 ;7 – TWINT: TWI
Interrupt Flag
;6 – TWEA: TWI
Enable Acknowledge
;5 – TWSTA: TWI
START Condition
;4 – TWSTO: TWI
STOP Condition
;3 – TWWC: TWI
Write Collision
;2 – TWEN: TWI
Enable
;1 – Res: Reserved
;0 – TWIE: TWI
Interrupt Enable
TWIRET:
ret

;
*************************************************************************
;* Start TWI Comunication in Master Mode - Write!
; In: X - Address of IO_CTR Block
; R17 - count of byte
; R18 - Slave Address
; R19 - Internal Address of Slave
; Out: c = 1 error
;
TWI_StartWrite:
rcall WaitToTWI

ldi R16,Low(WBlock0)
sts TWI_SADR+0,R16
ldi R16,High(WBlock0)
sts TWI_SADR+1,R16
rjmp TWI_Common

;
*************************************************************************
;* TWI interrupt
;*
TWI: ; Two-wire Serial Interface
Interrupt Handler
push ZL
push ZH
in ZL,SREG ;preserve main OS status
reg.
push ZL
push R16
push R0
push R17

; cbi GreenLED_PORT,GreenLED ;LED

in R16,TWSR ;Load TWI Status

andi R16,0b11111000 ;csak a status marad

lds ZL,TWI_SADR+0
lds ZH,TWI_SADR+1
icall

pop R17
POP R0
POP R16
POP ZL
OUT SREG,ZL
POP ZH
POP ZL
RETI

;
************************************************************************************************************
;*** R E A D B L O C K
;***
;
;***********************
; Read Block of data - State 0
; Start bit sended
RBlock0:
cpi R16,0x08 ;A
START condition has been transmitted
breq Rbl0
cpi R16,0x10 ;A
Repeated START condition has been transmitted
breq Rbl0
rjmp TWI_ReadError
Rbl0:
lds R16,TWI_Slave
andi R16,0b11111110 ;Write SLA
out TWDR,R16 ;Send Slave
Address

ldi R16,Low(RBlock1)
sts TWI_SADR+0,R16
ldi R16,High(RBlock1)
sts TWI_SADR+1,R16

ldi R16,(1< Send slave internal address

RBlock1:
cpi R16,0x18 ;SLA
+W has been transmitted
breq RBl1
rjmp TWI_ReadError
RBl1:
lds R16,TWI_ADR
out TWDR,R16 ;Send Slave
Internal Address

ldi R16,Low(RBlock2)
sts TWI_SADR+0,R16
ldi R16,High(RBlock2)
sts TWI_SADR+1,R16
ldi R16,(1< Repeated Satrt send
RBlock2:
cpi R16,0x28 ;
SlaveAddress sended + ACK received
breq Rbl21
rjmp TWI_ReadError
Rbl21:
ldi R16,Low(RBlock3)
sts TWI_SADR+0,R16
ldi R16,High(RBlock3)
sts TWI_SADR+1,R16

ldi R16,(1< Send SLA+R

RBlock3:
cpi R16,0x10 ;Repeated
Start sended + ACK received
breq RBl31
rjmp TWI_ReadError
RBl31:
lds R16,TWI_Slave
ori R16,1 ;Write SLA+R
out TWDR,R16 ;Send Slave
Address

ldi R16,Low(RBlock4)
sts TWI_SADR+0,R16
ldi R16,High(RBlock4)
sts TWI_SADR+1,R16

ldi R16,(1< Read data byte

RBlock4:
cpi R16,0x40 ;SLA+R send
+ ACK received
brne TWI_ReadError

lds R16,TWI_Count
cpi R16,1
breq TWILAstByte

ldi R16,Low(RBlock5)
sts TWI_SADR+0,R16
ldi R16,High(RBlock5)
sts TWI_SADR+1,R16

ldi R16,(1< Send slave internal address

WBlock1:
cpi R16,0x18 ;SLA
+W has been transmitted
breq WBl1
rjmp TWI_WriteError
WBl1:
lds R16,TWI_ADR
out TWDR,R16 ;Send Slave
Internal Address

ldi R16,Low(WBlock2)
sts TWI_SADR+0,R16
ldi R16,High(WBlock2)
sts TWI_SADR+1,R16
ldi R16,(1< Write data
WBlock2:
cpi R16,0x28 ;Data byte
has been transmitted + ACK received
breq WB12
rjmp TWI_WriteError
WB12: ;
Send data byte continous
lds ZL,TWI_CTL+0
lds ZH,TWI_CTL+1
ld R0,Z+
out TWDR,R0 ;next data
byte
sts TWI_CTL+0,ZL
sts TWI_CTL+1,ZH

lds R16,TWI_Count
cpi R16,1
breq TWI_WriteLastByte
dec R16
sts TWI_Count,R16

ldi R16,(1<

Programming the AVR Microcontrollers in Machine Language

AVR
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr)
Jump to: navigation, search The AVRs are a family of RISC
microcontrollers from Atmel. Their internal architecture was conceived
by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel Norway, a
subsidiary founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices
featuring SIMD and DSP instructions, along with many additional
features for audio and video processing, intended to compete with ARM
based processors. Note that the use of "AVR" in this article refers to the
8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has
been reported to stand for Advanced Virtual RISC. It's also rumoured to
stand for the company's founders: Alf and Vegard, who are evasive
when questioned about it. Contents [hide] 1 Device Overview 1.1
Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5
See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C Language
Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly
Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a
Harvard architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all integrated onto
a single die, removing the need for external memory (though still
available on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory. Each
instruction for the AVR line is either 16 or 32 bits in length. The Flash
memory is addressed using 16 bit word sizes. The size of the program
memory is indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data address
space consists of the register file, I/O registers, and SRAM. The AVRs
have thirty-two single-byte registers and are classified as 8-bit RISC
devices. The working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O registers (002016-
005F16). The actual usable RAM starts after both these sections
(address 006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped I/O
registers will occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for register file
and I/O register access, all can still be addressed and manipulated as if
they were in SRAM. [edit] EEPROM Almost all devices have on-die
EEPROM. This is most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design. The next
machine instruction is fetched as the current one is executing. Most
instructions take just one or two clock cycles, making AVRs relatively
fast among the eight-bit microcontrollers. The AVR family of processors
were designed for the efficient execution of compiled C code. The AVR
instruction set is more orthogonal than most eight-bit microcontrollers,
however, it is not completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other. Register
locations R0 to R15 have different addressing capabilities than register
locations R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while SER does
not, even though they are complementary instructions. CLR set all bits
to zero and SER sets them to one. (Note though, that neither CLR nor
SER are native instructions. Instead CLR is syntactic sugar for
[produces the same machine code as] EOR R,R while SER is syntactic
sugar for LDI R,$FF. Math operations such as EOR modify flags while
moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR
line can normally support clock speeds from 0-16MHz, with some
devices reaching 20MHz. Lower powered operation usually requires a
reduced clock speed. All AVRs feature an on-chip oscillator, removing
the need for external clocks or resonator circuitry. Because many
operations on the AVR are single cycle, the AVR can achieve up to
1MIPS per MHz. [edit] Development AVRs have a large following due to
the free and inexpensive development tools available, including
reasonably priced development boards and free development software.
The AVRs are marketed under various names that share the same basic
core but with different peripheral and memory combinations. Some
models (notably, the ATmega range) have additional instructions to
make arithmetic faster. Compatibility amongst chips is fairly good. See
external links for sites relating to AVR development. [edit] Features
Current AVRs offer a wide range of features: RISC Core Running Many
Single Cycle Instructions Multifunction, Bi-directional I/O Ports with
Internal, Configurable Pull-up Resistors Multiple Internal Oscillators
Internal, Self-Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage methods
Optional Boot Code Section with Independent Lock Bits for Protection
Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit
Timers PWM Channels & dead time generator Lighting (PWM Specific)
Controller models Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used
with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed hardware
& Hub controller with embedded AVR. Also freely available low-speed
(HID) software emulation Ethernet Controller Support Universal Serial
Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog
Comparators LCD Controller Support 10-Bit A/D Converters, with
multiplex of up to 16 channels Brownout Detection Watchdog Timer
(WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR assembler
programming language Atmel AVR machine programming language
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr)
Jump to: navigation, search The AVRs are a family of RISC
microcontrollers from Atmel. Their internal architecture was conceived
by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel Norway, a
subsidiary founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices
featuring SIMD and DSP instructions, along with many additional
features for audio and video processing, intended to compete with ARM
based processors. Note that the use of "AVR" in this article refers to the
8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has
been reported to stand for Advanced Virtual RISC. It's also rumoured to
stand for the company's founders: Alf and Vegard, who are evasive
when questioned about it. Contents [hide] 1 Device Overview 1.1
Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5
See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C Language
Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly
Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a
Harvard architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all integrated onto
a single die, removing the need for external memory (though still
available on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory. Each
instruction for the AVR line is either 16 or 32 bits in length. The Flash
memory is addressed using 16 bit word sizes. The size of the program
memory is indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data address
space consists of the register file, I/O registers, and SRAM. The AVRs
have thirty-two single-byte registers and are classified as 8-bit RISC
devices. The working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O registers (002016-
005F16). The actual usable RAM starts after both these sections
(address 006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped I/O
registers will occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for register file
and I/O register access, all can still be addressed and manipulated as if
they were in SRAM. [edit] EEPROM Almost all devices have on-die
EEPROM. This is most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design. The next
machine instruction is fetched as the current one is executing. Most
instructions take just one or two clock cycles, making AVRs relatively
fast among the eight-bit microcontrollers. The AVR family of processors
were designed for the efficient execution of compiled C code. The AVR
instruction set is more orthogonal than most eight-bit microcontrollers,
however, it is not completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other. Register
locations R0 to R15 have different addressing capabilities than register
locations R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while SER does
not, even though they are complementary instructions. CLR set all bits
to zero and SER sets them to one. (Note though, that neither CLR nor
SER are native instructions. Instead CLR is syntactic sugar for
[produces the same machine code as] EOR R,R while SER is syntactic
sugar for LDI R,$FF. Math operations such as EOR modify flags while
moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR
line can normally support clock speeds from 0-16MHz, with some
devices reaching 20MHz. Lower powered operation usually requires a
reduced clock speed. All AVRs feature an on-chip oscillator, removing
the need for external clocks or resonator circuitry. Because many
operations on the AVR are single cycle, the AVR can achieve up to
1MIPS per MHz. [edit] Development AVRs have a large following due to
the free and inexpensive development tools available, including
reasonably priced development boards and free development software.
The AVRs are marketed under various names that share the same basic
core but with different peripheral and memory combinations. Some
models (notably, the ATmega range) have additional instructions to
make arithmetic faster. Compatibility amongst chips is fairly good. See
external links for sites relating to AVR development. [edit] Features
Current AVRs offer a wide range of features: RISC Core Running Many
Single Cycle Instructions Multifunction, Bi-directional I/O Ports with
Internal, Configurable Pull-up Resistors Multiple Internal Oscillators
Internal, Self-Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage methods
Optional Boot Code Section with Independent Lock Bits for Protection
Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit
Timers PWM Channels & dead time generator Lighting (PWM Specific)
Controller models Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used
with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed hardware
& Hub controller with embedded AVR. Also freely available low-speed
(HID) software emulation Ethernet Controller Support Universal Serial
Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog
Comparators LCD Controller Support 10-Bit A/D Converters, with
multiplex of up to 16 channels Brownout Detection Watchdog Timer
(WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR assembler
programming language Atmel AVR machine programming language
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr)
Jump to: navigation, search The AVRs are a family of RISC
microcontrollers from Atmel. Their internal architecture was conceived
by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel Norway, a
subsidiary founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices
featuring SIMD and DSP instructions, along with many additional
features for audio and video processing, intended to compete with ARM
based processors. Note that the use of "AVR" in this article refers to the
8-bit RISC line of Atmel AVR Microcontrollers. The acronym AVR has
been reported to stand for Advanced Virtual RISC. It's also rumoured to
stand for the company's founders: Alf and Vegard, who are evasive
when questioned about it. Contents [hide] 1 Device Overview 1.1
Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5
See also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C Language
Development 6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly
Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a
Harvard architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all integrated onto
a single die, removing the need for external memory (though still
available on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory. Each
instruction for the AVR line is either 16 or 32 bits in length. The Flash
memory is addressed using 16 bit word sizes. The size of the program
memory is indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data address
space consists of the register file, I/O registers, and SRAM. The AVRs
have thirty-two single-byte registers and are classified as 8-bit RISC
devices. The working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O registers (002016-
005F16). The actual usable RAM starts after both these sections
(address 006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped I/O
registers will occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for register file
and I/O register access, all can still be addressed and manipulated as if
they were in SRAM. [edit] EEPROM Almost all devices have on-die
EEPROM. This is most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design. The next
machine instruction is fetched as the current one is executing. Most
instructions take just one or two clock cycles, making AVRs relatively
fast among the eight-bit microcontrollers. The AVR family of processors
were designed for the efficient execution of compiled C code. The AVR
instruction set is more orthogonal than most eight-bit microcontrollers,
however, it is not completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other. Register
locations R0 to R15 have different addressing capabilities than register
locations R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while SER does
not, even though they are complementary instructions. CLR set all bits
to zero and SER sets them to one. (Note though, that neither CLR nor
SER are native instructions. Instead CLR is syntactic sugar for
[produces the same machine code as] EOR R,R while SER is syntactic
sugar for LDI R,$FF. Math operations such as EOR modify flags while
moves/loads/stores/branches such as LDI do not.) [edit] Speed The AVR
line can normally support clock speeds from 0-16MHz, with some
devices reaching 20MHz. Lower powered operation usually requires a
reduced clock speed. All AVRs feature an on-chip oscillator, removing
the need for external clocks or resonator circuitry. Because many
operations on the AVR are single cycle, the AVR can achieve up to
1MIPS per MHz. [edit] Development AVRs have a large following due to
the free and inexpensive development tools available, including
reasonably priced development boards and free development software.
The AVRs are marketed under various names that share the same basic
core but with different peripheral and memory combinations. Some
models (notably, the ATmega range) have additional instructions to
make arithmetic faster. Compatibility amongst chips is fairly good. See
external links for sites relating to AVR development. [edit] Features
Current AVRs offer a wide range of features: RISC Core Running Many
Single Cycle Instructions Multifunction, Bi-directional I/O Ports with
Internal, Configurable Pull-up Resistors Multiple Internal Oscillators
Internal, Self-Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage methods
Optional Boot Code Section with Independent Lock Bits for Protection
Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit
Timers PWM Channels & dead time generator Lighting (PWM Specific)
Controller models Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used
with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed hardware
& Hub controller with embedded AVR. Also freely available low-speed
(HID) software emulation Ethernet Controller Support Universal Serial
Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog
Comparators LCD Controller Support 10-Bit A/D Converters, with
multiplex of up to 16 channels Brownout Detection Watchdog Timer
http://avr-asm.tripod.com/twi8.html (1 of 2)1/20/2009 9:03:20 PM
16 BIT MATH (AVR 202)

(WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-

Saving Sleep Modes picoPower Devices Atmel AVR assembler
programming language Atmel AVR machine programming language

http://avr-asm.tripod.com/twi8.html (2 of 2)1/20/2009 9:03:20 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

DALLAS 1 WIRE PROTOCOL

HOME
RETRO_DAN
;***********************************************************************
ASM FORUM ;*
ASM MATH ;* Number :Dallas 1-wire
;* File Name :"ds1wire.asm"
TUTORIAL #1
;* Title :Dallas 1-wire rutinok
TUTORIAL #2 ;* Date :2000.10.15.
TUTORIAL #3 ;* Version :0.0
;* Support telephone :+36-70-333-4034, Old: +36-30-9541-658
MATH 200 ;* Support fax :
MATH 200b ;* Support E-mail :info@vfx.hu
;* Target MCU :AVR
MATH 201 ;*
MATH 202 ;
**************************************************************************
MATH 32X
;* DESCRIPTION
MATH YX ;* - DS1990A security unit
;*
DIV16 XX
;* SYSCLK=3686400 Hz (T=271.267 ns)
DIV 24 24 ;*
DIV 3216 ;* DS119A - Family Code (0x01)
;* 48-bit Serial Number
FLOAT 128 ;* 8-bit CRC
SQRT16 ;*
;*
MATH 202 ;
MATH 202 **************************************************************************
;* Hardware Def.
DEC ASCII
INT ASCII .EQU DS1wire_PORT =PORTB ;Dallas 1-Wire bus
.equ DS1wire_DIR = DDRB
HX2ASC
.equ DS1wire_PIN = PINB
AVG8 222 .EQU DS1wire = 0
FFT7
COPY 102
LPM 108 .equ DSReadROM = 0x33
.equ DSMatchROM = 0x55
EPROM 100 .equ DSSkipROM = 0xCC
SER EPROM .equ DSSearchROM = 0xF0
.equ DSAlarmSearch = 0xEC
DFLASH AT45
.equ DSWriteScratchpad= 0x4E
FLASH CARD .equ DSReadScratchpad = 0xBE
.equ DSCopyScratchpad = 0x48
VFX SMIL
.equ DSConvertTemp = 0x44
VFX MEM .equ DSRecall = 0xB8
SORT 220
CRC 236 .equ DSDev1990A = 0x01
XMODEM REC .equ DSDev1920 = 0x10
UART 304
UART 305 ;
******************************************************************************
UART 128
;**** VARIABLES
UART BUFF .DSEG
USB 232 CRC: .BYTE 1 ;DS1990A CRC GENERATOR HASZNALJA
DSRD: .BYTE 9 ;Ide olvassa be a DS Chipet
AVR ISP DSRDMem:.byte 9 ;Scrach Pad tartalma
ISP 2313 BadCRC: .BYTE 1 ;Bad CRC szamlalo

ISP 1200
AVR SPI ;
*****************************************************************************
I2C 300 .CSEG
I2C 302
I2C TWI26
I2C/TWI 128
I2C/TWI AT8 ;************************************************************************
;*********************** 1-Wire Bus *************************************
DALLAS-1W ;************************************************************************
DALLAS CRC
DS1Wire_Init:
ETHNET 8019 clr R16,
TEA sts CRC,R16
sts BadCRC,R16
ADC 128
ADC 10B cbi DS1wire_PORT,DS1wire
cbi DS1wire_DIR,DS1wire
ADC 400
ret
ADC 401
THERM 232
;
IRD 410 *******************************************************************************
LCD HD44 ;****** T O U C H R E S E T
;
LCD 2313 *******************************************************************************
LCD44 2313 ;
;Inicialization procedure "Reset and PreSence Pulses"
KBD 240 ;
MUX 242 ; Ez a rutin egy Reset jelet general a mikrovrzerlo ketiranyu DS_BIT nevu
laban,
KBD PS2
;a Touch Memory fele es figyeli a visszajovo PreSence jelet.
KBD PC/128 ;Ha a PreSence jel megerkezett, akkor C=1 kulonben C=0 (nincs eszkoz a
PS2 EMU buszon)
;
BOOT MG8 ; |-Master Rx "Presence Pulse"-|
BOOT DR8 ; |---Master Reset Tx Pulse---| |----t(RSTH)---------------|
; __ t(RSTL) _____ _____ \\ ___
ALM CLK ; \ / \ / \
CLOCK 8564 ; \_________________________/ \______/ \__ ...
; |-----|-------|
90 DAYS
; t(PDH) t(PDL)
DELAYS ; t(R) <-- |-|
;
CALL ID
; 480us<=t(RSTL)< . t(RSTL)+t(R)<960us
DTMF 314 ; 480us<=t(RSTH)<
PWM 6CH ; 15us<=t(PDH)<=60us
; 60us<=t(PDL)<=240us
PWM 10K ;
ENCODE ; C-flag = 1 DS1990A a buszon van
; = 0 DS1990A nincs a buszon
STH-11 ;
ATMEL CORP ; R16, X
AVR
TouchReset:
BUTTERFLY
AVR BOOK SBI DS1wire_DIR,DS1wire ; 1-wire = Master LOW ,
Start the reset pulse
ldi YL,low((480*SYSCLK)/(1000000*4))
ldi YH,high((480*SYSCLK)/(1000000*4));loop cycle = 4
TR0: sbiw YL,1 ;[2]
brne TR0 ;[1/2] 480us wait with data
low

SBI DS1wire_PORT,DS1wire ;[2] 1-wire =Active Hi

nop ;[1]
nop
CBI DS1wire_DIR,DS1wire ;[2] 1-wire HI (felengedve)
CBI DS1wire_PORT,DS1wire ;[2] 1-wire = Tri-state
nop ;[1]
nop

SBIS DS1wire_PIN,DS1wire ;[1/2]

RJMP Short ;[2] ha egybol Low az rossz

ldi YL,low((60*SYSCLK)/(1000000*6))
ldi YH,high((60*SYSCLK)/(1000000*6));loop cycle = 6
TR1: SBIS DS1wire_PIN,DS1wire ;[1/2]
RJMP WL ;[2] Exit loop if line low
sbiw YL,1 ;[2]
BRNE TR1 ;[1/2] 60 us wait with data
low
RJMP SHORT ;[2] Line could not go low

WL:
ldi YL,low((240*SYSCLK)/(1000000*6))
ldi YH,high((240*SYSCLK)/(1000000*6));loop cycle = 6
TR3: SBIC DS1wire_PIN,DS1wire ;[1/2]
RJMP WH ;[2] Exit loop if line hi
sbiw YL,1 ;[2]
BRNE TR3 ;[1/2] us wait with data low

SHORT: CLC ;[1] Error

RET ;[4]

WH:
ldi YL,low((480*SYSCLK)/(1000000*4))
ldi YH,high((480*SYSCLK)/(1000000*4))
TR4: sbiw YL,1 ;[2]
BRNE TR4 ;[1/2] us wait with data low

SEC ;[1] RESET OK.

RET ;[4]

;
****************************************************************************
;******* TOUCHBYTE
;
****************************************************************************
;R0-ban megadott byte-ot kikuldi a touchmemory-nak
;es szimultan beolvas egy byte-ot onnan az R1-be
;Hasznalja a R17, R16 R3, R2, X
;

TouchByte:
LDI R17,8 ;[1]
BIT_LOOP:
ROR R1 ;[1]
RCALL TOUCHBIT ;[3]
ROR R0 ;[1]
DEC R17 ;[1]
BRNE BIT_LOOP ;[1/2]
RET ;[1]

TOUCHBIT:
sbi DS1wire_DIR,DS1wire ;[2] Start Window line = L,
1us <= Tlowr <= 15us
ldi YL,low((2*SYSCLK)/(1000000*4)) ;[1] 2us
ldi YH,high((2*SYSCLK)/(1000000*4)) ;[1] loop cycle = 4
BW0: sbiw YL,1 ;[2]
BRNE BW0 ;[1/2] eddig

SBRC R0,0 ;[1/2]

CBI DS1wire_DIR,DS1wire ;[2]

ldi YL,low((13*SYSCLK)/(1000000*4)) ;[1] 13us

ldi YH,high((13*SYSCLK)/(1000000*4)) ;[1] loop cycle = 4
BW1: sbiw YL,1 ;[2]
BRNE BW1 ;[1/2]

IN R2,DS1wire_PIN ;[1]
BST R2,DS1wire ;[1]
BLD R1,7 ;[1]

ldi YL,low((45*SYSCLK)/(1000000*4)) ;[1] 45us

ldi YH,high((45*SYSCLK)/(1000000*4));[1] loop cycle = 4
TCHL: sbiw YL,1 ;[2]
BRNE TCHL ;[1/2]
CBI DS1wire_DIR,DS1wire ;[2]
RET ;[4]

;***********************************************************************
;.......................................................................
;Read ROM
; In: X = address
; Out:
;c=1 Chip kiolvasva
;c=0 Chip nincs
;(Beolvas egy chippet az X-ban megadott cimre)
;
;Hasznalja a R18, R17, R16, R3, R2, R0;
;.......................................................................
ReadDS:
LDI XL,LOW(DSRD)
LDI XH,HIGH(DSRD) ;ide olvassa DS Chipet

clr R16
sts CRC,R16 ;CRC=0
rcall TouchReset
BRCS RDS1 ;ESZKOZ A BUSZON VAN
CLC
RET

RDS1:
LDI R16,DSReadROM ;SEARCH ROM COMMAND
MOV R0,R16
LDI R19,7 ;7-SZER OLVASUNK BE
RCALL TouchByte
RDS2: LDI R16,0xFF ;BEOLVASUNK 8 BITET
MOV R0,R16
RCALL TouchByte
ST X+,R1
RCALL CRCGEN
DEC R19
BRNE RDS2
LDI R16,0xFF ;BEOLVASSUK A CRC-t
MOV R0,R16
RCALL TouchByte
ST X+,R1
ldi YL,low((480*SYSCLK)/4000000)
ldi YH,high((480*SYSCLK)/4000000)
RDS3: sbiw YL,1
brne RDS3
SEC ;CHIP RENDBEN
RET

;***********************************************************************
;.......................................................................
;Read Scratchpad
; In: X = address
; Out:
;c=1 Chip kiolvasva
;c=0 Chip nincs
;(Beolvassa a Scratchpadot az X-ban megadott cimre)
;
;Hasznalja a R19, R18, R17, R16, R3, R2, R0; X
;.......................................................................
ReadScratchpadMem:
LDI XL,LOW(DSRDMem)
LDI XH,HIGH(DSRDMem) ;ide olvassa DS Chipet

LDI R16,DSSkipROM ;Skip ROM Command

MOV R0,R16
RCALL TouchByte

ldi R16,DSReadScratchpad
mov R0,R16
RCALL TouchByte
clr R16
sts CRC,R16 ;CRC=0

LDI R19,8 ;Read 8 byte

RDS2s: LDI R16,0xFF
MOV R0,R16
RCALL TouchByte
ST X+,R1
RCALL CRCGEN
DEC R19
BRNE RDS2s

LDI R16,0xFF ;BEOLVASSUK A CRC-t

MOV R0,R16
RCALL TouchByte
ST X+,R1

ldi YL,low((480*SYSCLK)/4000000)
ldi YH,high((480*SYSCLK)/4000000)
RDS3s: sbiw YL,1
brne RDS3s
RET

;***********************************************************************
;.......................................................................
;Convert Temperature to digital
; In: -
; Out: -
;c=1 Chip convert ok
;c=0 Chip none
;
;Hasznalja a R18, R17, R16, R3, R2, R0; SWTmr0
;.......................................................................
ConvTemp:
LDI R16,DSConvertTemp ;Convert T Command
MOV R0,R16
RCALL TouchByte

sbi DS1wire_PORT,DS1wire ;1-wire port ACTIVE 'H' during convert

sbi DS1wire_DIR,DS1wire

ldi R16,(SYSTACK/4)*3 ;most 0.75s a gyari 0.5s

helyett
sts SWTmr0,R16
sei ;interrupt enabled!!!
W1sec:
sleep
nop
lds R16,SWTmr0
cpi R16,0
brne W1sec

cbi DS1wire_PORT,DS1wire ;1-wire port tre-stated,

external pullup
cbi DS1wire_DIR,DS1wire
nop
rcall TouchReset
ret

;*************************************************************************
;.........................................................................
; DS1990A CRC GENERATOR
;IN: R1
;USE: R21,R20, R4,R3, R0, R18
;.........................................................................
CRCGEN: PUSH R1
LDI R20,8
LDI R18,0x18
PUSH R1

CRC_L: lds R3,CRC ;CRC

EOR R1,R3
ROR R1
MOV R1,R3
BRCC ZERO
EOR R1,R18
ZERO: ROR R1
sts CRC,R1
POP R1
SEC
SBRS R1,0
CLC
ROR R1
PUSH R1
DEC R20
BRNE CRC_L
POP R1

POP R1
RET

;*************************************************************************
;.........................................................................
; wait until Dallas 1-wire device is on bus
;IN:
;USE:
;.........................................................................
EszkVan: CLI
rcall TouchReset
rcall ReadDS
SEI
brcs EszkVan ;mig eszkoz van a buszon, addig nem
megy tovabb

ldi YL,low(1285) ;legalabb 1785 ciklusig ne legyenek a

buszon
ldi YH,high(1285)
Cikl1: push YL
push YH
CLI
rcall ReadDS
SEI
pop YH
pop YL
brcs EszkVan ;ha ismet eszkoz van kezdjuk elolrol!!
sbiw YL,1
brne Cikl1
ret

;*************************************************************************
;.........................................................................
; Extend DS1920 & DS1820 temperature
;IN:
; out R23:R22 - temperature
;USE:
;
;Tc=8T-2+(8*Count-8*Remainder)/8Count
;.........................................................................
ComuteT: LDI ZL,LOW(DSRDMem)
LDI ZH,HIGH(DSRDMem) ;ide olvassa DS Chipet

LDD dd16uL,Z+7 ;CPC

LDI dd16uH,0

LDD R22,Z+6 ;CRM

LDI R23,0

LSL dd16uL ;8*CPC

ROL dd16uH
LSL dd16uL
ROL dd16uH
LSL dd16uL
ROL dd16uH

LSL R22 ;8*CRM

ROL R23
LSL R22
ROL R23
LSL R22
ROL R23

SUB dd16uL,R22
SBC dd16uH,R23

LDD dv16uL,Z+7 ;CPC

LDI dv16uH,0

MOV R0,dv16uL
OR r0,dv16uH
BRNE DIV1 ;0-VAL NEM OSZTUNK
LDI R16,0
LDI R17,0
RJMP LKI1

DIV1: RCALL div16u ;OSZTAS eredmeny az

R16,R17-ben

LKI1: CLC
SBCI dres16uL,2
SBCI dres16uH,0 ;eredmeny-2

LDD R22,Z+0 ;Temperature

LDD R23,Z+1
CBR R22,1 ;Truncate 0.5C

LSL R22 ;8*T

ROL R23
LSL R22
ROL R23
LSL R22
ROL R23

ADD R22,dres16uL ;R22,R23 a korigalt

homerseklet
ADC R23,dres16uH
ret

Programming the AVR Microcontrollers in Machine Language

AVR
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr)
Jump to: navigation, search The AVRs are a family of RISC
microcontrollers from Atmel. Their internal architecture was conceived by
two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel Norway, a
subsidiary founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices
featuring SIMD and DSP instructions, along with many additional features
for audio and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to the 8-bit
RISC line of Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also rumoured to stand
for the company's founders: Alf and Vegard, who are evasive when
questioned about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program
Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion
Groups 6.3 Machine Language Development 6.4 C Language Development
6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other
AVR Links [edit] Device Overview The AVR is a Harvard architecture
machine with programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die, removing the
need for external memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-permanent
Flash memory. Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word sizes. The size
of the program memory is indicated in the naming of the device itself. For
instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and Registers The
data address space consists of the register file, I/O registers, and SRAM.
The AVRs have thirty-two single-byte registers and are classified as 8-bit
RISC devices. The working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O registers (002016-
005F16). The actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on some more
extensive devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are separate
addressing schemes and optimized opcodes for register file and I/O
register access, all can still be addressed and manipulated as if they were
in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program Execution Atmel's
AVRs have a single level pipeline design. The next machine instruction is
fetched as the current one is executing. Most instructions take just one or
two clock cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were designed for the
efficient execution of compiled C code. The AVR instruction set is more
orthogonal than most eight-bit microcontrollers, however, it is not
completely regular: Pointer registers X, Y, and Z have addressing
capabilities that are different from each other. Register locations R0 to
R15 have different addressing capabilities than register locations R16 to
R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports
32 to 63. CLR affects flags, while SER does not, even though they are
complementary instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native instructions.
Instead CLR is syntactic sugar for [produces the same machine code as]
EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations
such as EOR modify flags while moves/loads/stores/branches such as
LDI do not.) [edit] Speed The AVR line can normally support clock speeds
from 0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs feature an on-
chip oscillator, removing the need for external clocks or resonator
circuitry. Because many operations on the AVR are single cycle, the AVR
can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large
following due to the free and inexpensive development tools available,
including reasonably priced development boards and free development
software. The AVRs are marketed under various names that share the
same basic core but with different peripheral and memory combinations.
Some models (notably, the ATmega range) have additional instructions to
make arithmetic faster. Compatibility amongst chips is fairly good. See
external links for sites relating to AVR development. [edit] Features
Current AVRs offer a wide range of features: RISC Core Running Many
Single Cycle Instructions Multifunction, Bi-directional I/O Ports with
Internal, Configurable Pull-up Resistors Multiple Internal Oscillators
Internal, Self-Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage methods
Optional Boot Code Section with Independent Lock Bits for Protection
Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit
Timers PWM Channels & dead time generator Lighting (PWM Specific)
Controller models Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used
with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed hardware
& Hub controller with embedded AVR. Also freely available low-speed
(HID) software emulation Ethernet Controller Support Universal Serial
Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog
Comparators LCD Controller Support 10-Bit A/D Converters, with
multiplex of up to 16 channels Brownout Detection Watchdog Timer
(WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR assembler
programming language Atmel AVR machine programming language
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr)
Jump to: navigation, search The AVRs are a family of RISC
microcontrollers from Atmel. Their internal architecture was conceived by
two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel Norway, a
subsidiary founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices
featuring SIMD and DSP instructions, along with many additional features
for audio and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to the 8-bit
RISC line of Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also rumoured to stand
for the company's founders: Alf and Vegard, who are evasive when
questioned about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program
Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion
Groups 6.3 Machine Language Development 6.4 C Language Development
6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other
AVR Links [edit] Device Overview The AVR is a Harvard architecture
machine with programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die, removing the
need for external memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-permanent
Flash memory. Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word sizes. The size
of the program memory is indicated in the naming of the device itself. For
instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and Registers The
data address space consists of the register file, I/O registers, and SRAM.
The AVRs have thirty-two single-byte registers and are classified as 8-bit
RISC devices. The working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O registers (002016-
005F16). The actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on some more
extensive devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are separate
addressing schemes and optimized opcodes for register file and I/O
register access, all can still be addressed and manipulated as if they were
in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program Execution Atmel's
AVRs have a single level pipeline design. The next machine instruction is
fetched as the current one is executing. Most instructions take just one or
two clock cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were designed for the
efficient execution of compiled C code. The AVR instruction set is more
orthogonal than most eight-bit microcontrollers, however, it is not
completely regular: Pointer registers X, Y, and Z have addressing
capabilities that are different from each other. Register locations R0 to
R15 have different addressing capabilities than register locations R16 to
R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports
32 to 63. CLR affects flags, while SER does not, even though they are
complementary instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native instructions.
Instead CLR is syntactic sugar for [produces the same machine code as]
EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations
such as EOR modify flags while moves/loads/stores/branches such as
LDI do not.) [edit] Speed The AVR line can normally support clock speeds
from 0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs feature an on-
chip oscillator, removing the need for external clocks or resonator
circuitry. Because many operations on the AVR are single cycle, the AVR
can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large
following due to the free and inexpensive development tools available,
including reasonably priced development boards and free development
software. The AVRs are marketed under various names that share the
same basic core but with different peripheral and memory combinations.
Some models (notably, the ATmega range) have additional instructions to
make arithmetic faster. Compatibility amongst chips is fairly good. See
external links for sites relating to AVR development. [edit] Features
Current AVRs offer a wide range of features: RISC Core Running Many
Single Cycle Instructions Multifunction, Bi-directional I/O Ports with
Internal, Configurable Pull-up Resistors Multiple Internal Oscillators
Internal, Self-Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage methods
Optional Boot Code Section with Independent Lock Bits for Protection
Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit
Timers PWM Channels & dead time generator Lighting (PWM Specific)
Controller models Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used
with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed hardware
& Hub controller with embedded AVR. Also freely available low-speed
(HID) software emulation Ethernet Controller Support Universal Serial
Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog
Comparators LCD Controller Support 10-Bit A/D Converters, with
multiplex of up to 16 channels Brownout Detection Watchdog Timer
(WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR assembler
programming language Atmel AVR machine programming language
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr)
Jump to: navigation, search The AVRs are a family of RISC
microcontrollers from Atmel. Their internal architecture was conceived by
two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel Norway, a
subsidiary founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices
featuring SIMD and DSP instructions, along with many additional features
for audio and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to the 8-bit
RISC line of Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also rumoured to stand
for the company's founders: Alf and Vegard, who are evasive when
questioned about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program
Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion
Groups 6.3 Machine Language Development 6.4 C Language Development
6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other
AVR Links [edit] Device Overview The AVR is a Harvard architecture
machine with programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die, removing the
need for external memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-permanent
Flash memory. Each instruction for the AVR line is either 16 or 32 bits in
http://avr-asm.tripod.com/dallas1.html (1 of 2)1/20/2009 9:03:56 PM
16 BIT MATH (AVR 202)

length. The Flash memory is addressed using 16 bit word sizes. The size
of the program memory is indicated in the naming of the device itself. For
instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and Registers The
data address space consists of the register file, I/O registers, and SRAM.
The AVRs have thirty-two single-byte registers and are classified as 8-bit
RISC devices. The working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O registers (002016-
005F16). The actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on some more
extensive devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are separate
addressing schemes and optimized opcodes for register file and I/O
register access, all can still be addressed and manipulated as if they were
in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program Execution Atmel's
AVRs have a single level pipeline design. The next machine instruction is
fetched as the current one is executing. Most instructions take just one or
two clock cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were designed for the
efficient execution of compiled C code. The AVR instruction set is more
orthogonal than most eight-bit microcontrollers, however, it is not
completely regular: Pointer registers X, Y, and Z have addressing
capabilities that are different from each other. Register locations R0 to
R15 have different addressing capabilities than register locations R16 to
R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports
32 to 63. CLR affects flags, while SER does not, even though they are
complementary instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native instructions.
Instead CLR is syntactic sugar for [produces the same machine code as]
EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations
such as EOR modify flags while moves/loads/stores/branches such as
LDI do not.) [edit] Speed The AVR line can normally support clock speeds
from 0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs feature an on-
chip oscillator, removing the need for external clocks or resonator
circuitry. Because many operations on the AVR are single cycle, the AVR
can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large
following due to the free and inexpensive development tools available,
including reasonably priced development boards and free development
software. The AVRs are marketed under various names that share the
same basic core but with different peripheral and memory combinations.
Some models (notably, the ATmega range) have additional instructions to
make arithmetic faster. Compatibility amongst chips is fairly good. See
external links for sites relating to AVR development. [edit] Features
Current AVRs offer a wide range of features: RISC Core Running Many
Single Cycle Instructions Multifunction, Bi-directional I/O Ports with
Internal, Configurable Pull-up Resistors Multiple Internal Oscillators
Internal, Self-Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage methods
Optional Boot Code Section with Independent Lock Bits for Protection
Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit
Timers PWM Channels & dead time generator Lighting (PWM Specific)
Controller models Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used
with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed hardware
& Hub controller with embedded AVR. Also freely available low-speed
(HID) software emulation Ethernet Controller Support Universal Serial
Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog
Comparators LCD Controller Support 10-Bit A/D Converters, with
multiplex of up to 16 channels Brownout Detection Watchdog Timer
(WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR assembler
programming language Atmel AVR machine programming language

http://avr-asm.tripod.com/dallas1.html (2 of 2)1/20/2009 9:03:56 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

DALLAS 1 WIRE CRC CHECK

HOME
RETRO_DAN
I've implemented the 1-wire CRC with both calculation
ASM FORUM and table lookup.
ASM MATH I haven't actually used it with 1-wire stuff, but for
some other communication.
TUTORIAL #1
TUTORIAL #2 These routines do 1 byte at a time, so you need to put
TUTORIAL #3 input data into the register crc_in, and the register crc is used for
the crc value. So what you typically do is the set crc
MATH 200 to whatever init value it should have (I think it's 0 for 1-wire),
MATH 200b and run one of these routines for each byte. And in the
end register crc will contain the crc value calulated.
MATH 201
MATH 202 Calculated:
dow_crc:
MATH 32X
ldi crc_bitcnt, 8
MATH YX crc_loop:
mov crc_data, crc_in
DIV16 XX
eor crc_data, crc
DIV 24 24 ror crc_data
DIV 3216 mov crc_data, crc
brcc crc_zero
FLOAT 128 ldi crc_temp, 0x18
SQRT16 eor crc_data, crc_temp
crc_zero:
MATH 202 ror crc_data
MATH 202 mov crc, crc_data
lsr crc_in
DEC ASCII
dec crc_bitcnt
INT ASCII brne crc_loop
ret
HX2ASC
AVG8 222
FFT7
Table lookup:
COPY 102 dow_crc:
LPM 108 ldi ZL, low(crc_tab * 2)
ldi ZH, high(crc_tab * 2)
EPROM 100 eor r0, crc_in
SER EPROM add ZL, r0
brcc crc_b1
DFLASH AT45
inc ZH
FLASH CARD crc_b1: lpm
ret
VFX SMIL
VFX MEM crc_tab:
SORT 220 .db 0, 94, 188, 226, 97, 63, 221, 131, 194, 156, 126,
32, 163, 253, 31, 65
CRC 236 .db 157, 195, 33, 127, 252, 162, 64, 30, 95, 1, 227,
XMODEM REC 189, 62, 96, 130, 220
.db 35, 125, 159, 193, 66, 28, 254, 160, 225, 191, 93,
UART 304 3, 128, 222, 60, 98
UART 305 .db 190, 224, 2, 92, 223, 129, 99, 61, 124, 34, 192,
158, 29, 67, 161, 255
UART 128
.db 70, 24, 250, 164, 39, 121, 155, 197, 132, 218, 56,
UART BUFF 102, 229, 187, 89, 7
USB 232 .db 219, 133, 103, 57, 186, 228, 6, 88, 25, 71, 165,
251, 120, 38, 196, 154
AVR ISP .db 101, 59, 217, 135, 4, 90, 184, 230, 167, 249, 27,
ISP 2313 69, 198, 152, 122, 36
.db 248, 166, 68, 26, 153, 199, 37, 123, 58, 100, 134,
ISP 1200 216, 91, 5, 231, 185
AVR SPI .db 140, 210, 48, 110, 237, 179, 81, 15, 78, 16, 242,
172, 47, 113, 147, 205
I2C 300 .db 17, 79, 173, 243, 112, 46, 204, 146, 211, 141, 111,
I2C 302 49, 178, 236, 14, 80
.db 175, 241, 19, 77, 206, 144, 114, 44, 109, 51, 209,
I2C TWI26
143, 12, 82, 176, 238
I2C/TWI 128 .db 50, 108, 142, 208, 83, 13, 239, 177, 240, 174, 76,
I2C/TWI AT8 18, 145, 207, 45, 115
.db 202, 148, 118, 40, 171, 245, 23, 73, 8, 86, 180,
DALLAS-1W 234, 105, 55, 213, 139
DALLAS CRC .db 87, 9, 235, 181, 54, 104, 138, 212, 149, 203, 41,
119, 244, 170, 72, 22
ETHNET 8019 .db 233, 183, 85, 11, 136, 214, 52, 106, 43, 117, 151,
TEA 201, 74, 20, 246, 168
.db 116, 42, 200, 150, 21, 75, 169, 247, 182, 232, 10,
ADC 128 84, 215, 137, 107, 53
ADC 10B
ADC 400
ADC 401
THERM 232
IRD 410
LCD HD44
LCD 2313
LCD44 2313
KBD 240
MUX 242
KBD PS2
KBD PC/128 Programming the AVR Microcontrollers in Machine Language
PS2 EMU
BOOT MG8 AVR
BOOT DR8 << Prev | Ring Hub | Join | Rate| Next
>>
ALM CLK
© WebRing Inc. Search
CLOCK 8564
90 DAYS
DELAYS Atmel AVR From Wikipedia, the free encyclopedia (Redirected
CALL ID
DTMF 314
from Avr) Jump to: navigation, search The AVRs are a family
PWM 6CH of RISC microcontrollers from Atmel. Their internal
PWM 10K architecture was conceived by two students: Alf-Egil Bogen
ENCODE
STH-11
and Vegard Wollan, at the Norwegian Institute of Technology
ATMEL CORP (NTH] and further developed at Atmel Norway, a subsidiary
AVR founded by the two architects. Atmel recently released the
BUTTERFLY
AVR BOOK
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing,
intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still
be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language

http://avr-asm.tripod.com/dalcrc.html (1 of 2)1/20/2009 9:04:29 PM

16 BIT MATH (AVR 202)

http://avr-asm.tripod.com/dalcrc.html (2 of 2)1/20/2009 9:04:29 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

ETHERNET DRIVER FOR RTL8019

HOME
RETRO_DAN
;
ASM FORUM ***************************************************************************
ASM MATH ;
; File Name :"RTL8019.asm"
TUTORIAL #1
; Title :RTL8019AS Ethernet
TUTORIAL #2 Controller driver
TUTORIAL #3 ; Date :2002.11.22.
; Version :1.0.0
MATH 200 ; Support telephone :+36-70-333-4034, old: +36-30-9541-
MATH 200b 658 VFX
; Support fax :
MATH 201 ; Support Email :info@vfx.hu
MATH 202 ; Target MCU :AT90S8515
;
MATH 32X
;
MATH YX ***************************************************************************
; D E S C R I P T I O N
DIV16 XX
;
DIV 24 24 ; EGZ-03002-v1 Ethernet Driver
DIV 3216 ;
; Support Devices
FLOAT 128 ; RTL8019AS Ethernet Controller Card
SQRT16 ;
; Provides functions to initialize the Realtek 8019AS,
MATH 202 and send and retreive
MATH 202 ; packets
;
DEC ASCII
;Ethernet Frame Header
INT ASCII ;
; +--------------------------------------+
HX2ASC
; | Destination | Source | Frame |
AVG8 222 ; | Address | Address | Type |
FFT7 ; | (6 octets) | (6 octets) |(2 octets)|
; +--------------------------------------+
COPY 102 ;
LPM 108
EPROM 100 .EQU NICBASE = 0x4300h
SER EPROM ; IRQ = 0
; BOOTROM = none
DFLASH AT45
FLASH CARD ;
******************************************************************
VFX SMIL
;* REALTEK CONTROL REGISTER OFFSETS
VFX MEM ;* All offsets in Page 0 unless otherwise specified
SORT 220 ;* All functions accessing CR must leave CR in page
0 upon exit
CRC 236 ;
XMODEM REC ******************************************************************
; RTL8019AS Register Def
UART 304
UART 305 .EQU NICCR = 0x00 ;Command Register R/
W
UART 128
;This register is used to
UART BUFF select register pages,
USB 232 ;enable or disable remote
DMA operation and
AVR ISP ;issue commands.
ISP 2313
.EQU NICISR = 0x07 ;Interrupt Status
ISP 1200 Register, R/W in Page0
AVR SPI ;This register reflects the
NIC status. The host
I2C 300 ;reads it to determine the
I2C 302 cause of an interrupt
;Individual bits are
I2C TWI26
cleared by writing a "1"
I2C/TWI 128 ;into the corresponding bit.
I2C/TWI AT8 ;It must be cleared after
power up.
DALLAS-1W
DALLAS CRC .EQU NICIMR = 0x0F ;Interrupt Mask
Register, W in Page0, Type=R in Page2
ETHNET 8019 ;All bits correspond to the
TEA bits in the ISR register
;POWER UP=all 0s. Setting
ADC 128 individual bits will
ADC 10B ;enable the corresponding
interrupts.
ADC 400
ADC 401 .EQU NICDCR = 0x0E ;Data Configuration
THERM 232 Register, Type=W in Page0, Type=R in Page2

IRD 410 .EQU NICTCR = 0x0D ;Transmit

LCD HD44 Configuration Register, Type=W in Page0, Type=R in Page2

LCD 2313 .EQU NICTSR = 0x04 ;Transmit Status

LCD44 2313 Register, Type=R in Page0
;This register indicates
KBD 240 the status of a packet transmission
MUX 242 .EQU NICRCR = 0x0C ;Receive
Configuration Register, Type=W in Page0, Type=R in Page2
KBD PS2
KBD PC/128 .EQU NICRSR = 0x0C ;Receive Status
PS2 EMU Register, Type=R in Page0

BOOT MG8 .EQU NICCLDA0 = 0x01

BOOT DR8 .EQU NICCLDA1 = 0x02 ;Current Local DMA
Registers Type=R in Page0
ALM CLK ;These two registers can be
CLOCK 8564 read to get the
;current local DMA address.
90 DAYS
DELAYS .EQU NICPSTART = 0x01 ;Page Start
Register, Type=W in Page0, Type=R in Page 2
CALL ID
;The Page Start register
DTMF 314 sets the start page
PWM 6CH ;address of the receive
buffer ring
PWM 10K
ENCODE .EQU NICPSTOP = 0x02 ;Page Stop
Register, Type=W in Page0, Type=R in Page2
STH-11 ;The Page Stop register
ATMEL CORP sets the stop page
;address of the receive
AVR
buffer ring. In 8 bit
BUTTERFLY ;mode the PSTOP register
AVR BOOK should not exceed
;to 0x60, in 16 bit mode
the PSTOP register
;should not exceed to 0x80.

.EQU NICBNRY = 0x03 ;Boundary Register,

Type=R/W in Page0
;This register is used to
prevent overwrite
;of the receive buffer
ring. It is typically
;used as a pointer
indicating the last receive
;buffer page the host has
read.

.EQU NICTPSR = 0x04 ;Transmit Page

Start Register, Type=W in Page0
;This register sets the
start page address of the
;packet to the transmitted

.EQU NICTBCR0 = 0x05

.EQU NICTBCR1 = 0x06 ;Transmit Byte
Count Registers, Type=W in Page0
;These two registers set
the byte counts of the
;packet to be transmitted.

.EQU NICNCR = 0x05 ;Number of

Collisions Register, Type=R in Page0
;The register records the
number of collisions
;a node experiences during
a packet transmission.

.EQU NICFIFO = 0x06 ;First In First Out

Register, Type=R in Page0
;This register allows the
host to examine
;the contents of the FIFO
after loopback.

.EQU NICCRDA0 = 0x08

.EQU NICCRDA1 = 0x09 ;Current Remote DMA
Address registers, Type=R in Page0
;These two registers
contain the current address of remote DMA.

.EQU NICRSAR0 = 0x08

.EQU NICRSAR1 = 0x09 ;Remote Start
Address Registers, Type=W in Page0
;These two registers set
the start address of
;remote DMA.

.EQU NICRBCR0 = 0x0A

.EQU NICRBCR1 = 0x0B ;Remote Byte Count
Registers, Type=W in Page0
;These two registers se the
data byte counts of
;remote DMA.

.EQU NICCNTR0 = 0x0D ;Frame Alignment

Error Tally Counter Register, Type=R in Page0

.EQU NICCNTR1 = 0x0E ;CRC Error Tally

Counter Register, Type=R in Page0

.EQU NICCNTR2 = 0x0F ;Missed Packet

Tally Counter Register, Type=R in Page0

.EQU NICPAR0 = 0x01

.EQU NICPAR1 = 0x02
.EQU NICPAR2 = 0x03
.EQU NICPAR3 = 0x04
.EQU NICPAR4 = 0x05
.EQU NICPAR5 = 0x06 ;Physical Address
Registers, Type=R/W in Page1
;These registers contain my
Ethernet node address
;and are used to compare
the destination adderss
;of incoming packets for
acceptation or rejection

.EQU NICCURR = 0x07 ;Current Page

Register, Type=R/W in Page1
;This register points to
the page address of
;the first receive buffer
page to be used for
;a packet reception.

.EQU NICMAR0 = 0x08

.EQU NICMAR1 = 0x09
.EQU NICMAR2 = 0x0A
.EQU NICMAR3 = 0x0B
.EQU NICMAR4 = 0x0C
.EQU NICMAR5 = 0x0D
.EQU NICMAR6 = 0x0E
.EQU NICMAR7 = 0x0F ;Multicast Address
Register, Type=R/W in Page1
;These registers provide
filtering bits of
;multicast addresses hashed
by the CRC logic

.EQU NICCR9346 = 0x01 ;Page 3

.EQU NICRDMAPORT = 0x10
.EQU NICRSTPORT = 0x18

;
*****************************************************************************
;
; RTL ISR Register Bits
;
;
****************************************************************************/
.EQU ISR_RST = 7
.EQU ISR_RDC = 6
.EQU ISR_OVW = 4
.EQU ISR_PTX = 1
.EQU ISR_PRX = 0

;
*****************************************************************************
;
; RTL Register Initialization Values
;
;
****************************************************************************
;RCR : accept broadcast
packets and packets destined to this MAC
; drop short frames
and receive errors
.equ RCR_INIT = 0x04

;TCR : default transmit

operation - CRC is generated
.equ TCR_INIT = 0x00

;DCR : allows send packet

to be used for packet retreival
; FIFO threshold: 8-
bits (works)
; 8-bit transfer mode
.equ DCR_INIT = 0x58

;IMR : interrupt enabled

for receive and overrun events
.equ IMR_INIT = 0x11

;buffer boundaries -
transmit has 6 256-byte pages
; receive has 26 256-byte
pages
; entire available packet
buffer space is allocated
.equ TXSTART_INIT = 0x40
.equ RXSTART_INIT = 0x46
.equ RXSTOP_INIT = 0x60

;
*********************************************************
;* Receive RTL8019's Ring Buffer Page Header Layout
;* This is the 4-byte header that resides infront of
the
;* data packet in the receive buffer.
;
*********************************************************
.equ enetpacketstatus= 0x00
.equ nextblock_ptr = 0x01
.equ enetpacketLenL = 0x02
.equ enetpacketLenH = 0x03

; LANBUFSIZE: The size of the buffer that holds

incoming and outgoing packets.
.equ LANBUFSIZE = 1564

;
*****************************************************************************
;
; Ethernet constants
;
;
****************************************************************************
.equ ETHERNET_MIN_PACKET_LENGTH = 0x3C
.equ ETHERNET_HEADER_LENGTH = 0x0E

.equ IP_TCP_HEADER_LENGTH = 40
.equ TOTAL_HEADER_LENGTH = IP_TCP_HEADER_LENGTH
+ETHERNET_HEADER_LENGTH

;
***************************************************************************
.ESEG

; ETHADDR: The Ethernet address

; 48 bit IEEE OUI (Organizationally Unique Identifier)

EETHADDR: .db "DEDO",0x00,0x01

;
***************************************************************************
.DSEG

; packet[LANBUFSIZE]
;
; The packet array is used to hold incoming and
outgoing packets.
; The device driver fills this with incoming packets.

pageheader: .byte 4 ;Rx RTL8019's page

header
packet: .byte LANBUFSIZE
nextPage: .byte 1 ;RTL8019's page
header -> next page
currentRetreiveAddress: .byte 2 ;innen kell
a kilvasast folytatni (pointer)

;pointers to locations in the RTL8019 receive buffer

uip_len: .byte 2

ETHADDR: .byte 6

;
***************************************************************************

.CSEG

;*****************************************************
;** SetLANToActive
;**
;** IN: -
;**
;** Out: -
;*
;* Alt: R16
;*
;* Description: Sets LAN to Active & SRAM to Inactive
;*
;
SetLANToActive:
SBI RAMCS_PORT,RAMCS
nop
CBI LANCS_PORT,LANCS
nop
ret

;*****************************************************
;** SetLANToInactive
;**
;** IN: -
;**
;** Out: -
;*
;* Alt: R16
;*
;* Description: Sets LAN to Inactive LANCS=H
;*
;
SetLANToInactive:
SBI LANCS_PORT,LANCS
nop
ret

;*****************************************************
;** SetISAReset
;**
;** IN: R0 -> 1 ISA Reset, 0 Normal mode
;**
;** Out: -
;*
;* Alt: -
;*
;* Description: Sets ISA RESET Line to R0; 0 = low, 1 =
hi
;*
;
SetISAReset:
sbrs R0,0
CBI LANRES_PORT,LANRES
sbrc R0,0
SBI LANRES_PORT,LANRES
nop
ret

;*****************************************************
;** Wait1ms
;**
;** In: R16 - 16*1ms varakozas
;**
;** Out: -
;**
;**
;** Alt R16, XL,XH
;**
;** Description: wating for R16 * 1 ms
;*
Wait1ms:
ldi XL,low(SYSCLK/(5*1000))
ldi Xh,high(SYSCLK/(5*1000))
Waitx1: sbiw XL,1 ;[2] \
nop ;[1] - 5 cycles in
loop
brne Waitx1 ;[2] /
dec R16
brne Wait1ms
ret

;******************************************************
;** RTLHW_Reset
;**
;** In: -
;**
;** Out: -
;**
;** ALt: R0, R16, XL, XH
;**
;** Description: Power-up initialization of the RTL8019
and ISA
;*
RTLHW_Reset:
rcall SetLANToInactive
clr R0
inc R0
rcall SetISAReset
ldi R16,10
rcall Wait1ms ;10ms
warakozas
clr R0
rcall SetISAReset
ret

;
*****************************************************************************
;** RTLreadReg
;**
;** IN: R16 - RTL_ADDRESS offset
;**
;** Out: R17 - register data
;**
;** Alt: -
;**
;** Description: Reads byte from RTL8019 register
;*
RTLReadReg:
rcall SetLANToActive
push XL
push XH
ldi XL,low(NICBASE)
add XL,R16
ldi XH,high(NICBASE)
ldi R17,0
adc XH,R17 ;X
= NIC real address to ISA
ld R17,X
rcall SetLANToInactive
pop XH
pop XL
ret

;
*****************************************************************************
;** RTLWriteReg
;**
;** IN: R16 - RTL_ADDRESS offset
;** R17 - RTL_DATA
;**
;** Out: -
;**
;** Alt: R0
;**
;** Description: Writes byte to RTL8019 register.
;*
RTLWriteReg:
rcall SetLANToActive
push XL
push XH
clr R0
ldi XL,low(NICBASE)
add XL,R16
ldi XH,high(NICBASE)
adc XH,R0 ;X
= NIC real address to ISA
st X,R17
rcall SetLANToInactive
pop XH
pop XL
ret

;
***********************************************************************
;** RTL8019_Init
;**
;** IN: -
;**
;** Out: -
;**
;** ALt: R0, R16, XL, XH
;**
;* Description: Sets up the RTL8019 NIC hardware
interface, and initializes
;* the buffers and configuration of the NIC
;
RTL8019_Init:
rcall RTLHW_Reset
;do soft
reset & clear pending interrupt
ldi R16,NICISR ;clear
Interrupt register
rcall RTLReadReg
ldi R16,NICISR
rcall RTLWriteReg

ldi R16,50 ;50ms

varakozas
rcall Wait1ms

ldi R16,NICCR ;stop the

NIC, abort DMA, page 0
ldi R17,0x21
rcall RTLWriteReg
ldi R16,2 ;Delay 2ms
rcall Wait1ms ;make sure
nothing is coming in or going out

; CONFIGx
ldi R16,NICCR
ldi R17,0xC0 ;select
Page3
rcall RTLWriteReg

ldi R16,NICCR9346 ;Enable SW

Config
ldi R17,0xC0
rcall RTLWriteReg

ldi R16,0x04
ldi R17,0b10000000 ;IRQ0, Base
0x300
rcall RTLWriteReg

ldi R16,0x05
ldi R17,0b00100000 ;
AutoDetect, ROM Disabled
rcall RTLWriteReg

ldi R16,0x06
ldi R17,0b00010000 ;
Halfduplex, LED0 - link, LED1 - RX led2 - TX
rcall RTLWriteReg

ldi R16,0x0D
ldi R17,0x00
rcall RTLWriteReg

ldi R16,NICCR9346
ldi R17,0x00 ;End Config
rcall RTLWriteReg

; !!!!

ldi R16,NICCR ;stop the

NIC, page 0
ldi R17,0x01
rcall RTLWriteReg

ldi R16,NICDCR
ldi R17,DCR_INIT ;0x58
Normal Operation, FIFO Treshold, Auto Init Remote
rcall RTLWriteReg

ldi R16,NICRBCR0
ldi R17,0x00
rcall RTLWriteReg
ldi R16,NICRBCR1
rcall RTLWriteReg ;Remote DMA
Byte Count =0x0000

ldi R16,NICRCR
ldi R17,0x04 ;only
packets with broadcast
rcall RTLWriteReg ;
destination address are accepted

ldi R16,NICTPSR
ldi R17,TXSTART_INIT ;Transmit
Page Start Register=40
rcall RTLWriteReg

ldi R16,NICTCR
ldi R17,0x02 ;Internal
loopback
rcall RTLWriteReg

ldi R16,NICPSTART
ldi R17,RXSTART_INIT ;page
address of the receive buffer ring = 46
rcall RTLWriteReg
ldi R16,NICBNRY ;utolso
olvasott page = 46
rcall RTLWriteReg

ldi R16,NICPSTOP
ldi R17,RXSTOP_INIT ;stop page
address of the receive buffer ring = 60
rcall RTLWriteReg

ldi R16,NICCR
ldi R17,0x61 ;Stop &
Abort DMA
rcall RTLWriteReg
ldi R16,2 ;2ms
varakozas
rcall Wait1ms

ldi R16,NICCURR
ldi R17,RXSTART_INIT ;Rx Page =
46
rcall RTLWriteReg

ldi ZL,low(EETHADDR) ;MAC

address from EEPROM
ldi ZH,high(EETHADDR)
call EERead
sts ETHADDR+0,R0
mov R17,R0
ldi R16,NICPAR0 ;Setup our
MAC Address
rcall RTLWriteReg

adiw ZL,1
call EERead
sts ETHADDR+1,R0
mov R17,R0
ldi R16,NICPAR1
rcall RTLWriteReg

adiw ZL,1
call EERead
sts ETHADDR+2,R0
mov R17,R0
ldi R16,NICPAR2
rcall RTLWriteReg

adiw ZL,1
call EERead
sts ETHADDR+3,R0
mov R17,R0
ldi R16,NICPAR3
rcall RTLWriteReg

adiw ZL,1
call EERead
sts ETHADDR+4,R0
mov R17,R0
ldi R16,NICPAR4
rcall RTLWriteReg

adiw ZL,1
call EERead
sts ETHADDR+5,R0
mov R17,R0
ldi R16,NICPAR5
rcall RTLWriteReg

ldi R16,NICCR
ldi R17,0x21 ;Stop NIC,
Abort DMA
rcall RTLWriteReg

ldi R16,NICDCR
ldi R17,DCR_INIT ;58 Normal
operation...
rcall RTLWriteReg

ldi R16,NICCR
ldi R17,0x22 ;Start
Command, DMA abort
rcall RTLWriteReg

ldi R16,NICISR
ldi R17,0xFF
rcall RTLWriteReg ;Clear
pending Interrupt

ldi R16,NICIMR
ldi R17,IMR_INIT ;11,
Interrupt Enable
rcall RTLWriteReg ;packet
received with no errors
;receive
buffer has been exhausted
ldi R16,NICTCR
ldi R17,TCR_INIT ;00 -
Normal operation
rcall RTLWriteReg

ldi R16,NICCR
ldi R17,0x22
rcall RTLWriteReg ;start the
NIC
ret

;
***********************************************************************
;** RTL8019endPacketSend
;**
;** In : -
;**
;**
;** Alt :
;**
;* Description: Ends a packet send operation and
instructs the NIC to transmit
;* the frame over the network
;
RTL8019endPacketSend:
ldi R16,NICCR ;send the contents
of the transmit buffer onto the network
ldi R17,0x24
rcall RTLWriteReg
;clear the remote
DMA interrupt
ldi R16,NICISR
ldi R17,(1< sendPacketLength
push R16 ;R17:R16 - >
packetLength

ldi R16,NICCR
ldi R17,0x22
rcall RTLWriteReg ;start the NIC

packf: ldi R16,NICCR ;still

transmitting a packet - wait for it to finish
rcall RTLReadReg ;while( readRTL(CR)
& 0x04 );
andi R17,0x04
brne packf

;load beginning
page for transmit buffer
ldi R16,NICTPSR
ldi R17,TXSTART_INIT
rcall RTLWriteReg

;set start address

for remote DMA operation
ldi R16,NICRSAR0
ldi R17,0x00
rcall RTLWriteReg
ldi R16,NICRSAR1
ldi R17,0x40
rcall RTLWriteReg

;clear the packet

stored interrupt
ldi R16,NICISR
ldi R17,(1<= RXSTOP_INIT) || (bnry <
RXSTART_INIT))

invpointer:
ldi R16,NICBNRY
ldi R17,RXSTART_INIT
rcall RTLWriteReg
ldi R16,NICCR
ldi R17,0x62
rcall RTLWriteReg
ldi R16,NICCURR
ldi R17,RXSTART_INIT
rcall RTLWriteReg
ldi R16,NICCR
ldi R17,0x22
rcall RTLWriteReg
clc
ret ;Z= meg
mindig 0!!

jopointer:
ldi R16,NICRBCR0 ;initiate
DMA to transfer the RTL8019 packet header
ldi R17,0x04
rcall RTLWriteReg
ldi R16,NICRBCR1
ldi R17,0x00
rcall RTLWriteReg ;Remote
Byte Count = 4

ldi R16,NICRSAR0
ldi R17,0x00
rcall RTLWriteReg
ldi R16,NICRSAR1
mov R17,R20
rcall RTLWriteReg ;Remote
start address= Start boundary page

ldi R16,NICCR
ldi R17,0x0A
rcall RTLWriteReg ;Start
Remote Read DMA

ldi R18,4 ;4 byte-ot

olvasunk be
ldi XL,Low(pageheader) ;ide
ldi XH,high(pageheader)

Getph: ldi R16,NICRDMAPORT

rcall RTLReadReg
st X+,R17
dec R18
brne Getph

ldi R16,NICCR ;end the

DMA operation
ldi R17,0x22
rcall RTLWriteReg

rcall WaitToDMA

lds ZL,pageheader+enetpacketLenL
lds ZH,pageheader+enetpacketLenH ;
Z=rxlen

lds R16,pageheader+nextblock_ptr ;
nextPage
sts nextPage,R16 ;
eltaroljuk ,aborthoz kell

ldi R17,4
sts currentRetreiveAddress+0,R17
sts currentRetreiveAddress+1,R20 ;
innen folytatjuk majd a kiolvasast (offset cim)

;if the nextPage pointer is invalid, the packet is

not ready yet - exit

ldi R18,RXSTOP_INIT
cp R16,R18
brsh pageErr1
ldi R18,RXSTART_INIT
cp R16,R18
brcs pageErr1 ;if((nextPage >=
RXSTOP_INIT) || (nextPage < RXSTART_INIT))
clr R18
sub ZL,R17
sbc ZH,R18 ;rxlen-4
sec
ret

pageErr1: clr Zl
clr ZH
clc
ret

;
*****************************************************************************
; Device Manager
; A foprogrambol ezek hivhatoak

;
*****************************************************************************
;* RTL8019dev_send
;*
;* In:
;*
;* Out:

http://avr-asm.tripod.com/ethnet8019.html (1 of 2)1/20/2009 9:05:10 PM

16 BIT MATH (AVR 202)

;*
;* Alt:
;*
;* Description: Sends the packet contained in
packet over the network
;
RTL8019dev_send:
ldi R16,low(LANBUFSIZE)
ldi R17,high(LANBUFSIZE)
RTL8019dev_sendA:
push R16
push R17
rcall RTL8019beginPacketSend

;send packet, using data in ip_appdata if

over the IP+TCP header size

ldi XL,Low(packet)
ldi XH,high(packet)
pop ZH
pop ZL
rcall RTL8019sendPacketData

rcall RTL8019endPacketSend
ret

;
*****************************************************************************
;* RTL8019dev_poll
;*
;* In: -
;*
;* Out: Z = Length of the packet retreived, or zero if
no packet retreived
;* Y = Address of retreived packet
;* c flag = 0, no packet
;*
;* Description: Polls the RTL8019 looking for an
overflow condition or a new
;* packet in the receive buffer. If a new
packet exists and will
;* fit in packet, it is retreived, and the
length is returned.
;* A packet bigger than the buffer is discarded
;
*****************************************************************************/
;
RTL8019dev_poll:
rcall RTL8019beginPacketRetreive ;Z =
packetLength
brcs Vanpacket2 ;if there's
no packet or an error
;exit
without ending the operation
ret
Vanpacket2:
cpi ZL,low(LANBUFSIZE+1)
ldi R16,high(LANBUFSIZE+1) ;drop
anything too big for the buffer
cpc ZH,R16
brcs PacketSizejo
;Ezt el
kell dobni, tul nagy
rcall RTL8019endPacketRetreive
clr ZL
clr ZH
clc
ret

PacketSizejo:
push ZL ;copy the
packet data into the IP packet buffer
push ZH
ldi XL,low(packet)
ldi XH,high(packet)
rcall RTL8019retreivePacketData
rcall RTL8019endPacketRetreive
pop ZH
pop ZL
sts pageheader+enetpacketLenL,ZL
sts pageheader+enetpacketLenH,ZH
ldi YL,low(packet)
ldi YH,high(packet)
sec
ret

Programming the AVR Microcontrollers in Machine Language

AVR
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© WebRing Inc. Search

Atmel AVR From Wikipedia, the free encyclopedia (Redirected

from Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing,
intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still
be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language

http://avr-asm.tripod.com/ethnet8019.html (2 of 2)1/20/2009 9:05:10 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

TEA PROTOCOL
HOME
RETRO_DAN
;(C)2005 wek http://www.efton.sk
ASM FORUM ;free for personal use
ASM MATH ;for commercial use, please contact wek@efton.sk
TUTORIAL #1
;implementation of original TEA algorithm by
TUTORIAL #2 Needham&Wheeler for AVR
TUTORIAL #3 ;

MATH 200 ;uses 8 bytes of SRAM (input/output data) and 14

MATH 200b registers
;!!! uses reordered key !!!
MATH 201 ;;!!! reordered key !!! k[1]k[0]k[3]k[2]
MATH 202
MATH 32X
;6861 cycles
MATH YX ;5E=94 words = 188 bytes, excl. key
;no stack
DIV16 XX
DIV 24 24
DIV 3216 ;key can be easily placed into SRAM - replace lpm xxx,Z
+ by ld xxx,Z+
FLOAT 128 ;for devices which don't support lpm xxx,Z+ replace it
SQRT16 by lpm; mov xxx,r0

MATH 202
MATH 202 .dseg
DEC ASCII
ydata: .byte 4
INT ASCII zdata: .byte 4
HX2ASC
;register definitions
AVG8 222 .def ZL = r30
FFT7 .def ZH = r31
.def YL = r28
COPY 102 .def YH = r29
LPM 108
EPROM 100 .def tmp0 = r1
SER EPROM .def tmp1 = r2
.def tmp2 = r3
DFLASH AT45
.def tmp3 = r4
FLASH CARD .def tmp4 = r5
.def tmp5 = r6
VFX SMIL
.def tmp6 = r7
VFX MEM .def tmp7 = r8
SORT 220 .def tmp8 = r9

CRC 236 .def sum0 = r16

XMODEM REC .def sum1 = r17
.def sum2 = r18
UART 304 .def sum3 = r19
UART 305
.def RoundCnt = r20
UART 128
UART BUFF .cseg
USB 232
Tea:
AVR ISP ldi RoundCnt,2*32
ISP 2313 clr sum0
clr sum1
ISP 1200 clr sum2
AVR SPI clr sum3
ldi YL,LOW(zdata)
I2C 300 ldi YH,HIGH(zdata)
I2C 302 ldd tmp0,Y+0
ldd tmp1,Y+1
I2C TWI26
ldd tmp2,Y+2
I2C/TWI 128 ldd tmp3,Y+3
I2C/TWI AT8 TeaRound:
ldi ZL,LOW(Key*2)
DALLAS-1W ldi ZH,HIGH(Key*2)
DALLAS CRC subi sum0,$47
sbci sum1,$86
ETHNET 8019 sbci sum2,$C8
TEA sbci sum3,$61
TeaSubRound:
ADC 128 clr tmp4 ;z>>5 but as (z<<3)>>8
ADC 10B (simultaneously preparing for z<<4)
lsl tmp0
ADC 400
rol tmp1
ADC 401 rol tmp2
THERM 232 rol tmp3
rol tmp4
IRD 410 lsl tmp0
LCD HD44 rol tmp1
rol tmp2
LCD 2313 rol tmp3
LCD44 2313 rol tmp4
lsl tmp0
KBD 240 rol tmp1
MUX 242 rol tmp2
rol tmp3
KBD PS2
rol tmp4
KBD PC/128
PS2 EMU lpm tmp5,Z+ ;!!! reordered key !!! k[1]k[0]k[3]k
[2]
BOOT MG8 add tmp5,tmp1 ;z>>5 + key[1]
BOOT DR8 lpm tmp6,Z+
adc tmp6,tmp2
ALM CLK lpm tmp7,Z+
CLOCK 8564 adc tmp7,tmp3
lpm tmp8,Z+
90 DAYS
adc tmp8,tmp4
DELAYS
lsl tmp0 ;last shift for z<<4
CALL ID
rol tmp1
DTMF 314 rol tmp2
PWM 6CH rol tmp3
lpm tmp4,Z+ ;z<<4 + key[0]
PWM 10K add tmp0,tmp4
ENCODE lpm tmp4,Z+
adc tmp1,tmp4
STH-11 lpm tmp4,Z+
ATMEL CORP adc tmp2,tmp4
lpm tmp4,Z+
AVR
adc tmp3,tmp4
BUTTERFLY
AVR BOOK eor tmp5,tmp0 ;xor the first two parts
eor tmp6,tmp1
eor tmp7,tmp2
eor tmp8,tmp3

ldd tmp0,Y+0 ;z+sum

ldd tmp1,Y+1
ldd tmp2,Y+2
ldd tmp3,Y+3
add tmp0,sum0
adc tmp1,sum1
adc tmp2,sum2
adc tmp3,sum3

eor tmp0,tmp5
eor tmp1,tmp6
eor tmp2,tmp7
eor tmp3,tmp8

sbrc RoundCnt,0 ;in the first subround

increment sum (AVR: decrement by its neg)
rjmp TeaRoundX3
ldi YL,LOW(ydata) ;and set pointer to ydata to
add the calculated value in tmp (and it remains valid for the next
subround, too)
ldi YH,HIGH(ydata)
rjmp TeaRoundX4
TeaRoundX3:
ldi YL,LOW(zdata) ;in the second subround only
set pointer to zdata
ldi YH,HIGH(zdata)
TeaRoundX4:

ldd tmp4,Y+0 ;add the calculated value to

y or z
add tmp0,tmp4
std Y+0,tmp0
ldd tmp4,Y+1
adc tmp1,tmp4
std Y+1,tmp1
ldd tmp4,Y+2
adc tmp2,tmp4
std Y+2,tmp2
ldd tmp4,Y+3
adc tmp3,tmp4
std Y+3,tmp3

dec RoundCnt
brne TeaRoundA
ret
TeaRoundA:
sbrs RoundCnt,0
rjmp TeaRound
rjmp TeaSubRound

Key:
; .db 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0

.db $0f,$1e,$2d,$3c
.db $4b,$5a,$69,$78
.db $87,$96,$a5,$b4
.db $c3,$d2,$e1,$f0

Programming the AVR Microcontrollers in Machine Language

Atmel AVR From Wikipedia, the free

encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language
http://avr-asm.tripod.com/tea.html (1 of 2)1/20/2009 9:05:44 PM
16 BIT MATH (AVR 202)

http://avr-asm.tripod.com/tea.html (2 of 2)1/20/2009 9:05:44 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

ANALOG TO DIGITAL COMPARATOR (AVR 128)

HOME
RETRO_DAN
;**** A P P L I C A T I O N N O T E A V R 1 2 8
ASM FORUM ************************
ASM MATH ;*
;* Title: Setup and Use the Analog Comparator
TUTORIAL #1
;* Version: 1.1
TUTORIAL #2 ;* Last updated: 97.07.04
TUTORIAL #3 ;* Target: AT90Sxxxx (Devices with Analog
Comparator)
MATH 200 ;*
MATH 200b ;* Support E-mail: avr@atmel.com
;*
MATH 201 ;* DESCRIPTION:
MATH 202 ;* This Application note shows how to enable and use
some features of the
MATH 32X
;* AVR's on-board precision Analog Comparator.
MATH YX ;*
;* The Application note is written as a program example
DIV16 XX
performing the
DIV 24 24 ;* following tasks:
DIV 3216 ;*
;* - Wait for a positive output edge by polling the
FLOAT 128 comparator output
SQRT16 ;* - Wait for a positive output edge by polling the
interrupt flag
MATH 202 ;* - Enable interrupt on comparator output toggle. The
MATH 202 interrupt routine
;* increments a 16 bit register counter each time it
DEC ASCII
is executed
INT ASCII ;*
;
HX2ASC
***************************************************************************
AVG8 222
FFT7 .include "1200def.inc"

COPY 102 ;***** Global Register Variables

LPM 108
.def temp =r16 ;temporary storage
EPROM 100 register
SER EPROM .def cntL =r17 ;register counter
low byte
DFLASH AT45
.def cntH =r18 ;register counter
FLASH CARD high byte
VFX SMIL
;***** Interrupt Vectors
VFX MEM
SORT 220 rjmp RESET ;Reset Handle

CRC 236 .org ACIaddr

XMODEM REC rjmp ANA_COMP ;Analog Comparator Handle
UART 304
UART 305
;
UART 128
***************************************************************************
UART BUFF ;*
USB 232 ;* "ANA_COMP"
;*
AVR ISP ;* This interrupt routine is served each time ACI in
ISP 2313 the ACSR register is
;* set, provided that the Analog Comparator interrupt
ISP 1200 is enabled (ACIE is
AVR SPI ;* set). The routine increments a 16-bit counter each
time it is run
I2C 300 ;*
I2C 302 ;* Number of words :5
;* Number of cycles :8
I2C TWI26
;* Low registers used :1 (ac_tmp)
I2C/TWI 128 ;* High registers used :2 (cntL,cntH)
I2C/TWI AT8 ;*
;
DALLAS-1W ***************************************************************************
DALLAS CRC
;***** Interrupt Routine Register Variables
ETHNET 8019
TEA .def ac_tmp =r0 ;temporary storage
register for SREG
ADC 128
ADC 10B ;***** Code
ADC 400
ANA_COMP:
ADC 401
THERM 232 in ac_tmp,SREG ;temporarily store the
Status register
IRD 410 subi cntL,low(-1)
LCD HD44 sbci cntH,high(-1) ;counter = counter + 1
out SREG,ac_tmp ;restore Status register
LCD 2313 reti
LCD44 2313
KBD 240
MUX 242 ;
***************************************************************************
KBD PS2
;*
KBD PC/128 ;* PROGRAM EXECUTION STARTS HERE
PS2 EMU ;*
;
BOOT MG8 ***************************************************************************
BOOT DR8
RESET:
ALM CLK
CLOCK 8564
;***** Include if used on device with RAM
90 DAYS
; ldi temp,low(RAMEND)
DELAYS ; out SPL,temp
; ldi temp,high(RAMEND)
CALL ID
; out SPH,temp
DTMF 314
PWM 6CH ;
***************************************************************************
PWM 10K ;*
ENCODE ;* "wait_edge1"
;*
STH-11 ;* This piece of code waits until the output of the
ATMEL CORP comparator (the ACO-bit
;* in ACSR) goes high. This way of doing it requires no
AVR
setup, however,
BUTTERFLY ;* extremely short pulses can be missed, since the
AVR BOOK program runs three clock
;* cycles between each time the comparator is checked.
Another disadvantage
;* is that the program has to wait for the output to be
come negative first,
;* in case the output is positive when polling starts.
;*
;* Number of words :4
;* Number of cycles :4 per loop. Response time: 3 - 5
clock cycles
;* Low registers used :None
;* High registers used :None
;*
;
***************************************************************************

;***** Code

wait_edge1:
sbic ACSR,ACO ;if output is high
rjmp wait_edge1 ; wait
we1_1: sbis ACSR,ACO ;if output is low
rjmp we1_1 ; wait

;
***************************************************************************
;*
;* "wait_edge2"
;*
;* This piece of code waits until the output of the
comparator (the ACO-bit
;* in ACSR) goes high. This is a more secure solution,
since the interrupt
;* flag is polled. This allows the user to insert code
within the wait loop
;* because hardware "remembers" pulses of shorter
duration than the polling
;* interval. Another positive feature is that there is
no need to wait for
;* a preceeding negative edge.
;*
;* Number of words :5
;* Number of cycles :Inital setup :2
;* Flag clearing:1
;* Loop :4
;* Response time:3 - 5
;* Low registers used :None
;* High registers used :None
;*
;
***************************************************************************

;***** Code

wait_edge2:

;***** Initial Hardware setup (assumes ACIE = 0 from

reset)

sbi ACSR,ACIS0
sbi ACSR,ACIS1 ;enable interrupt on rising
output edge

;***** Wait

sbi ACSR,ACI ;write a "1" to the ACI

flag to clear it
we2_1: ;----------------------- user code goes here
sbis ACSR,ACI ;if ACI is low
rjmp we2_1 ; wait more

;
***************************************************************************
;*
;* "ana_init"
;*
;* This code segment enables Analog Comparator
Interrupt on output toggle.
;* The program then enters an infinite loop.
;* The 16-bit counter is cleared prior to enabling the
interrupt.
;*
;* Performance figures apply to interrupt
initialization only.
;*
;* Number of words :4
;* Number of cycles :5
;* Low registers used :None
;* High registers used :1 (temp)
;*
;
***************************************************************************

;***** Register Variables

.def temp =r16 ;temporary register

;***** Code

ana_init:

;***** Clear 16-bit counter

clr cntL
clr cntH

;***** Enable Interrupt (assumes ACIE = 0 from reset)

ldi temp,(ACI<<1) ;clear interrupt flag and

ACIS1/ACIS0...
out ACSR,temp ;...to select interrupt on
toggle
sei ;enable global interrupts
sbi ACSR,ACIE ;enable Analog Comparator
interrupt

forever:rjmp forever

Programming the AVR Microcontrollers in Machine Language

AVR
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected

from Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing,
intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still
be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language
http://avr-asm.tripod.com/avr128.html (1 of 2)1/20/2009 9:06:20 PM
16 BIT MATH (AVR 202)

http://avr-asm.tripod.com/avr128.html (2 of 2)1/20/2009 9:06:20 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

10 BIT ANALOG TO DIGITAL COMPARATOR FOR 128

HOME
RETRO_DAN
;
ASM FORUM ***************************************************************************
ASM MATH ;
; File Name :'adc.asm"
TUTORIAL #1
; Title :ATmega128 internal 10-bit
TUTORIAL #2 ADC Driver
TUTORIAL #3 ; Date :2003.08.03.
; Version :1.0.0
MATH 200 ; Support telephone :+36-70-333-4034, old: +36-30-9541-
MATH 200b 658 VFX
; Support fax :
MATH 201 ; Support Email :info@vfx.hu
MATH 202 ; Target MCU :AVR
;
MATH 32X
;
MATH YX ***************************************************************************
; D E S C R I P T I O N
DIV16 XX
;
DIV 24 24 ;
DIV 3216 ***************************************************************************
; M O D I F I C A T I O N H I S T O R Y
FLOAT 128 ;
SQRT16 ;
; rev. date who why
MATH 202 ; ---- ---------- ---
MATH 202 ------------------------------------
; 0.01 2003.08.03 VFX Creation
DEC ASCII
;
INT ASCII ;
***************************************************************************
HX2ASC
;Hardware
AVG8 222 ;
FFT7 ***************************************************************************
;*
COPY 102 ;* SYSCLK: f=16.000 MHz (T= 62.5 ns)
LPM 108 ;*
;
EPROM 100 ***************************************************************************
SER EPROM ;
;
DFLASH AT45
;
FLASH CARD **************************************************************************
;* Hardware Def.
VFX SMIL
;
VFX MEM ;
SORT 220 ***************************************************************************
;**** VARIABLES
CRC 236 .DSEG
XMODEM REC
;egymas utan kell aljanak!!!!
UART 304 ADCCH0: .byte 2
UART 305 ADCCH1: .byte 2
ADCCH2: .byte 2
UART 128
ADCCH3: .byte 2
UART BUFF ADCCH4: .byte 2
USB 232 ADCCH5: .byte 2
ADCCH6: .byte 2
AVR ISP ADCCH7: .byte 2
ISP 2313
ISP 1200
AVR SPI
;
I2C 300 ***************************************************************************
I2C 302 .ESEG
I2C TWI26
I2C/TWI 128 ;
I2C/TWI AT8 ***************************************************************************
;**** CODE SEG
DALLAS-1W ;
DALLAS CRC ***************************************************************************
.CSEG
ETHNET 8019
TEA
ADC_Init:
ADC 128 clr R16
ADC 10B ldi R17,16 ;2*8 csatorna
valtozoterulet = 0
ADC 400
ldi ZL,low(ADCCH0)
ADC 401 ldi ZH,high(ADCCH0)
THERM 232 ADCI1: st Z+,R16
dec R17
IRD 410 brne ADCI1
LCD HD44
LCD 2313 ldi R16,0b00000000
LCD44 2313 out ADMUX,R16 ;[7:6] - REFS1:0:
Reference Selection Bits
KBD 240 ; REFS1 REFS0
MUX 242 Vref Selection
; 0 0
KBD PS2
AREF, Internal Vref turned off
KBD PC/128 ; 0 1
PS2 EMU AVCC with external capacitor at AREF pin
; 1 0
BOOT MG8 Reserved
BOOT DR8 ; 1 1
Internal 2.56V Voltage Reference with external capacitor at AREF pin
ALM CLK ;[5] - ADLAR: ADC
CLOCK 8564 Left Adjust Result
;[4:0] - MUX4:0:
90 DAYS
Analog Channel and Gain Selection Bits
DELAYS ; MUX4..0
Single Ended Input
CALL ID
; 00000 ADC0
DTMF 314 ; 00001 ADC1
PWM 6CH ; 00010 ADC2
; 00011 ADC3
PWM 10K ; 00100 ADC4
ENCODE ; 00101 ADC5
; 00110 ADC6
STH-11 ; 00111 ADC7
ATMEL CORP
ldi R16,0b00011111
AVR
out ADCSRA,R16 ;[7] - ADEN: ADC
BUTTERFLY Enable
AVR BOOK ;[6] - ADSC: ADC
Start Conversion
;[5] - ADFR: ADC
Free Running Select
;[4] - ADIF: ADC
Interrupt Flag
;[3] - ADIE: ADC
Interrupt Enable
;[2:0] - ADPS2:0:
ADC Prescaler Select Bits
;ADPS2 ADPS1 ADPS0
Division Factor
; 0 0
0 2
; 0 0
1 2
; 0 1
0 4
; 0 1
1 8
; 1 0
0 16
; 1 0
1 32
; 1 1
0 64
; 1 1
1 128
ret

StartADC:
in ZL,ADCSRA
ori ZL,0b11011000
out ADCSRA,ZL
ret

;****************************************
;ADC Conversion Complete Handler
;
;
ADC:
PUSH ZL
PUSH ZH
IN ZL,SREG
PUSH ZL
push R0

in ZL,ADCL
push ZL
in R0,ADCH
push R0

cbi ADCSRA,ADEN ;ADC Stop

in ZL,ADMUX
inc ZL
andi ZL,7
out ADMUX,ZL ;kovetkezo
csatorna kivalasztva

clr R0
dec ZL
andi ZL,7
add ZL,ZL
ldi ZH,Low(ADCCH0+2)
add ZL,ZH
ldi ZH,high(ADCCH0+2)
adc ZH,R0
pop R0
st -Z,R0
pop R0
st -Z,R0

pop R0
POP ZL
OUT SREG,ZL
POP ZH
POP ZL
RETI

Programming the AVR Microcontrollers in Machine Language

AVR
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected

from Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing,
intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still
be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language

http://avr-asm.tripod.com/adc10b.html (1 of 2)1/20/2009 9:06:54 PM

16 BIT MATH (AVR 202)

http://avr-asm.tripod.com/adc10b.html (2 of 2)1/20/2009 9:06:54 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

CHEAP ANALOG DIGITAL COMPARATOR (AVR 400)

HOME
RETRO_DAN
;**** A P P L I C A T I O N N O T E A V R 4 0 0
ASM FORUM ************************
ASM MATH ;*
;* Title: Low Cost A/D Converter
TUTORIAL #1
;* Version: 1.0
TUTORIAL #2 ;* Last updated: 97.07.18
TUTORIAL #3 ;* Target: AT90Sxxxx (All AVR Devices)
;*
MATH 200 ;* Support E-mail: avr@atmel.com
MATH 200b ;*
;* Code Size :37 words
MATH 201 ;* Low Register Usage :0
MATH 202 ;* High Register Usage :2
;* Status Flag Usage :1 (t flag)
MATH 32X
;* Interrupt usage :Timer/Counter0 overflow interrupt,
MATH YX ;* Analog comparator interrupt
;*
DIV16 XX
;* DESCRIPTION
DIV 24 24 ;*
DIV 3216 ;* This application note shows how you can make a A/D
converter using a AVR
FLOAT 128 ;* device, one external resistor and one external
SQRT16 capacitor. This solution
;* uses the Timer/Counter0 overflow interrupt in
MATH 202 addition to the Analog
MATH 202 ;* comparator interrupt. The usage of interrupts free's
the MCU while
DEC ASCII
;* conversion is taking place.
INT ASCII ;*
;* To minimize the usage of external components, this A/
HX2ASC
D converter uses
AVG8 222 ;* the charging of a capacitor (controlled by port D
FFT7 pin 2)through a
;* resistor while converting.
COPY 102 ;* The voltage across the capacitor will follow an
LPM 108 exponential curve of
;* voltage versus time. By constricting the voltage
EPROM 100 range of
SER EPROM ;* the converter to 2/5Vdd, the exponential curve is a
good approximation
DFLASH AT45
;* of a straight line. This makes it possible to simply
FLASH CARD measure the time
;* it takes before the voltage across the capacitor
VFX SMIL
equals the voltage which
VFX MEM ;* is to be converted. To do this we use the analog
SORT 220 comparator. The
;* comparator will give an interrupt when the voltage
CRC 236 across the capacitor
XMODEM REC ;* rises above the measurement voltage. The output is
divided into 64
UART 304 ;* different levels.
UART 305 ;*
;* To ensure correct timing the time constant of the RC-
UART 128
network must
UART BUFF ;* satisfie 512*(1/f)=-R*C*ln(1-2/5).
USB 232 ;* For the A/D converter to operate properly, the
capacitor must be
AVR ISP ;* completly discharged between each conversion. This
ISP 2313 is done by allowing
;* the discharging to take a minimum of 200us.
ISP 1200 ;*
AVR SPI ;*
;* *** Initialization
I2C 300 ;*
I2C 302 ;* 1. Call convert_init
;* 2. Enable global interrupts (with sei)
I2C TWI26
;*
I2C/TWI 128 ;* *** A/D conversion
I2C/TWI AT8 ;*
;* 1. Call AD_convert
DALLAS-1W ;* 2. Wait for conversion complete (t to be set) (less
DALLAS CRC than 521 cycles)
;* 3. Read data from result
ETHNET 8019 ;
TEA **************************************************************************
ADC 128
ADC 10B .include "1200def.inc"
ADC 400
;***** Constants
ADC 401
THERM 232 .equ preset=192 ;T/C0
Preset constant (256-64)
IRD 410
LCD HD44 ;***** A/D converter Global Registers

LCD 2313 .def result=r16 ;Result and

LCD44 2313 intermediate data
.def temp=r17 ;Scratch
KBD 240 register
MUX 242
KBD PS2
KBD PC/128
PS2 EMU ;
**************************************************************************
BOOT MG8 ;*
BOOT DR8 ;* PROGRAM START - EXECUTION STARTS HERE
;*
ALM CLK ;
CLOCK 8564 **************************************************************************
.cseg
90 DAYS
DELAYS
.org $0000
CALL ID
rjmp RESET ;Reset handle
DTMF 314 .org OVF0addr
PWM 6CH rjmp ANA_COMP ;Timer0 overflow handle
.org ACIaddr
PWM 10K rjmp ANA_COMP ;Analog comparator handle
ENCODE
STH-11
ATMEL CORP ;
**************************************************************************
AVR
;*
BUTTERFLY ;* ANA_COMP - Analog comparator interrupt routine
AVR BOOK ;*
;*
;* DESCRIPTION
;* This routine is executed when one of two events
occur:
;* 1. Timer/counter0 overflow interrupt
;* 2. Analog Comparator interrupt
;* Both events signals the end of a conversion. Timer
overflow if the signal
;* is out of range, and analog comparator if it is in
range.
;* The offset will be corrected, and the t'flag will be
set.
;* Due to the cycles needed for interruption handling,
it is necessary
;* to subtract 1 more than was added previously.
;*
;*
;* Total numbers of words : 7
;* Total number of cycles : 10
;* Low register usage : 0
;* High register usage : 2 (result,
temp)
;* Status flags : 1 (t flag)
;*
;
**************************************************************************
ANA_COMP: in result,TCNT0 ;Load timer
value

clr temp ;Stop timer0

out TCCR0,temp

subi result,preset+1 ;Rescale A/D output

cbi PORTD,PD2 ;Start discharge

set ;Set conversion
complete flag

reti ;Return from

interrupt

;
**************************************************************************
;*
;* convert_init - Subroutine for A/D converter
initialization
;*
;*
;* DESCRIPTION
;* This routine initializes the A/D converter. It sets
the timer and the
;* analog comparator. The analog comparator interrupt
is being initiated by
;* a rising edge on AC0. To enable the A/D converter
the global interurrupt
;* flag must be set (with SEI).
;*
;* The conversion complete flag (t) is cleared.
;*
;* Total number of words : 6
;* Total number of cycles : 10
;* Low register usage : 0
;* High register usage : 1 (result)
;* Status flag usage : 0
;*
;
**************************************************************************
convert_init:
ldi result,$0B ;Initiate comparator
out ACSR,result ;and enable
comparator interrupt

ldi result,$02 ;Enable timer

interrupt
out TIMSK,result

sbi PORTD,PD2 ;Set converter

charge/discharge
;as output

ret ;Return from

subroutine

;
**************************************************************************
;*
;* AD_convert - Subroutine to start an A/D conversion
;*
;* DESCRIPTION
;* This routine starts the conversion. It loads the
offset value into the
;* timer0 and starts the timer. It also starts the
charging of the
;* capacitor.
;*
;*
;* Total number of words : 7
;* Total number of cycles : 10
;* Low register usage : 0
;* High register usage : 1 (result)
;* Status flag usage : 1 (t flag)
;*
;
**************************************************************************
AD_convert:
ldi result,preset ;Clear counter
out TCNT0,result ;and load offset
value

clt ;Clear conversion

complete flag (t)

ldi result,$02 ;Start timer0 with

prescaling f/8
out TCCR0,result
sbi PORTB,PB2 ;Start charging of
capacitor

ret ;Return from

subroutine

;
**************************************************************************
;*
;* Example program
;*
;* This program can be used as an example on how to set
up the A/D
;* converter properly.
;* NOTE! To ensure proper operation, make sure the
discharging period
;* of the capacitor is longer than 200us in front of
each conversion.
;* The results of the conversion is presented on port B.
;* To ensure proper discharging we have added a delay
loop. This loop is
;* 11 thousand cycles. This will give a 550us delay
with a 20MHz oscillator
;* (11ms with a 1MHz oscillator).
;*
;
**************************************************************************

RESET:
rcall convert_init ;Initialize A/D
converter
sei ;Enable global
interrupt
ldi result,$ff ;set port B as
output
out DDRB,result
Delay: clr result ;Clear temp
counter 1
ldi temp,$f0 ;Reset temp counter
2
loop1: inc result ;Count up
temp counter 1
brne loop1 ;Check if inner
loop is finished
inc temp ;Count up temp
counter 2
brne loop1 ;Check if delay is
finished

rcall AD_convert ;Start conversion

Wait: brtc Wait ;Wait until
conversion is complete
out PORTB,result ;Write result on
port B

rjmp Delay ;Repeat conversion

Programming the AVR Microcontrollers in Machine Language

AVR
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected

from Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing,
intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still
be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
http://avr-asm.tripod.com/avr400.html (1 of 2)1/20/2009 9:07:27 PM
16 BIT MATH (AVR 202)

System Programmable using ICSP, JTAG, or High Voltage

methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language

http://avr-asm.tripod.com/avr400.html (2 of 2)1/20/2009 9:07:27 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

PRECISION 8 BIT ADC (AVR 401)

HOME
RETRO_DAN
;**** A P P L I C A T I O N N O T E A V R 4 0 1
ASM FORUM ************************
ASM MATH ;*
;* Title: 8-bit precision A/D converter
TUTORIAL #1
;* Version: 1.03
TUTORIAL #2 ;* Last Updated: 97.07.17
TUTORIAL #3 ;* Target: AT90Sxxxx (All AVR Devices with
analog comparator)
MATH 200 ;*
MATH 200b ;* Support E-mail: avr@atmel.com
;*
MATH 201 ;* DESCRIPTION
MATH 202 ;* This Application note shows how to perform dual-
slope-alike
MATH 32X
;* A/D conversion utilizing the on-chip analog
MATH YX comparator and a few
;* external components. Included is a test program that
DIV16 XX
performs
DIV 24 24 ;* conversions in a eternal loop, outputting the result
DIV 3216 to eight LEDs.
;*
FLOAT 128 ;
SQRT16 ***************************************************************************

MATH 202 ;***** Registers used by mpy9u multiplication routine

MATH 202
.def mc9u =r0 ;multiplicand used by
DEC ASCII
multiplication routine
INT ASCII .def mp9u =r1 ;multiplier used by
multiplication routine
HX2ASC
.def m9uL =r1 ;result Low byte
AVG8 222 .def m9uH =r2 ;result High byte
FFT7
;***** Registers used by div17u division routine
COPY 102
LPM 108 .def didL =r1 ;Dividend
.def didH =r2
EPROM 100 .def dresL =r1 ;Holds the result of the
SER EPROM division
.def dresH =r2
DFLASH AT45
.def divL =r3 ;Divisor
FLASH CARD .def divH =r4
.def remL =r5 ;Reminder variables used by
VFX SMIL
division routine
VFX MEM .def remH =r6
SORT 220
.def TinH =r14 ;Time to reach input voltage
CRC 236 .def TinL =r15
XMODEM REC .def Tref =r16 ;Time to reach reference
voltage
UART 304 .def TH =r17 ;Timer variable
UART 305
.def Vref =r18 ;Computed Vref
UART 128
UART BUFF .def temp =r19
USB 232 .def temp2 =r20

AVR ISP
ISP 2313 ;Port B pins
.equ AIN0 =0
ISP 1200 .equ AIN1 =1
AVR SPI .equ Ref1 =2
.equ Ref2 =3
I2C 300 .equ LED =4
I2C 302 .equ T =7
I2C TWI26
.equ PRESC =2 ;Timer clocked at CK/8
I2C/TWI 128 .equ VrefAddr=0 ;EEPROM Address holding Vref
I2C/TWI AT8
DALLAS-1W .include "1200def.inc"
DALLAS CRC
.cseg
ETHNET 8019 .org 0
TEA rjmp reset ;Reset handler
reti
ADC 128
ADC 10B .org OVF0addr
;** Timer/counter 0 overflow interrupt
ADC 400
******************************
ADC 401 T0_int: inc TH ;Increase
THERM 232 timer high-byte
reti
IRD 410
LCD HD44
;*** Reset handler
LCD 2313 **************************************************
LCD44 2313 reset: sbi DDRB,LED ;PB4 and
ser temp ;Port D as output,
KBD 240 used to
MUX 242 out DDRD,temp ;drive LEDs
KBD PS2
ldi temp,(1< multiplier
KBD PC/128 ldi temp,128 ;128 ->
PS2 EMU multiplicand ( = 2.5 volts)
mov mc9u,temp
BOOT MG8 rcall mpy9u ;Tref x 128
BOOT DR8
clr divH ;(Tref x 128)
ALM CLK mov divL,TinL ; -----------
CLOCK 8564 rcall div17u ; Tcal
90 DAYS
ldi temp,VrefAddr ;Store Vref
DELAYS out EEAR,temp
out EEDR,dresL
CALL ID
sbi EECR,EEWE
DTMF 314
PWM 6CH calibrate1: sbic EECR,EEWE
rjmp calibrate1
PWM 10K
ENCODE
STH-11 ;Main program
ATMEL CORP main: cbi PORTB,T ;Turn off
pull-up on T-pin
AVR
BUTTERFLY ldi temp,VrefAddr ;Read Vref from
AVR BOOK EEPROM
out EEAR,temp
sbi EECR,EERE
in Vref,EEDR

loop: rcall reference ;Measure

Tref
rcall delay ;A small delay to
let
; the capacitor
discharge,
rcall input ;Measure Tin

brts error ;If Vin > Vcc

calc: lsr TinH ;TinH -> C

(multiplier)
mov mp9u,TinL ;TinL -> multiplier
mov mc9u,Vref ;Tref ->
multiplicand
rcall mpy9u ;Tin x Tref

clr divH ;(Tin x Vref)

mov divL,Tref ;------------
rcall div17u ; Tref

tst dresH
breq write

error: ldi temp,255 ; Vin

= 255
mov dresL,temp

write: com dresL ;Show the

value on the LEDs
rcall long_delay
rcall long_delay
rcall long_delay

out PORTD,dresL
rol dresL
brcs wr1
cbi PORTB,LED
rjmp loop

wr1: sbi PORTB,LED

rjmp loop

;*** Subroutine delay

******************************************************
delay: ldi temp,$FF
d1: dec temp
brne d1
ret

long_delay: ser temp2

ld1: rcall delay
dec temp2
brne ld1
ret

;*** Subroutine reference

**************************************************
;* Measures Tref

reference: sbi DDRB,AIN0 ;Discharge the

capacitor

sbi DDRB,Ref1 ;Turn on Vref

sbi PORTB,Ref1
sbi DDRB,Ref2

rcall delay ;Let the capacitor

discharge completely

clr TH ;Reset timer

out TCNT0,TH

cbi DDRB,AIN0 ;AIN0 as input

ldi temp,PRESC ;Start timer

out TCCR0,temp

sbi DDRB,T ;Turn on the

transistor

ref_wait: sbic ACSR,ACO ;If Capacitor

voltage > reference voltage
rjmp ref_ok ; conversion
conplete
cpi TH,1 ;Continue if timer
overflow
brlo ref_wait

ref_ok: in Tref,TCNT0 ;Store Tref

clr temp ;Stop timer

out TCCR0,temp

cbi DDRB,T ;Turn off transistor

sbi DDRB,AIN0 ;Discharge capacitor

cbi PORTB,Ref1 ;Turn off Vref

cbi DDRB,Ref1
cbi DDRB,Ref2

ret

;*** subroutine input

**************************************************
;* Measures Tin
;* Returns with the T-flag set if timer overflow (i.e.
Vin > Vcc)

input: cbi DDRB,AIN0 ;Tri-state

AIN0

clt ;Clear error flag

clr TH ;Clear timer
out TCNT0,TH

ldi temp,PRESC ;Start timer

out TCCR0,temp

sbi DDRB,T ;Turn on transistor

input_wait: sbic ACSR,ACO ;If Capacitor

voltage > Vin
rjmp input_ok ; charging
complete
cpi TH,2
brlo input_wait
set ;T=1 indicates Vin
> Vcc

input_ok: in TinL,TCNT0 ;Store Tin

mov TinH,TH

input_exit: clr temp ;Stop timer

out TCCR0,temp

cbi DDRB,T ;Turn off transistor

sbi DDRB,AIN0 ;Discharge capacitor

ret

;
********************************************************************
;*
;* This routine divides a 17 bit number (carry:didH:
didLL) on
;* a 16 bit number (divH:divL).
;* The result is placed in (dresH:dresL)
;*
;* The carry flag must contain the 17th bit of the
divident before
;* the routine is executed.
;*
;* The routine is based on the div16u - 16/16 Bit
Unsigned Division
;* routine found in the avr200.asm application note file
;*
;
********************************************************************

div17u: clr remL ;clear

remainder Low byte
clr remH ;clear remainder
High byte
ldi temp,17 ;init loop counter

d17u_1: rol remL ;shift

dividend into remainder
rol remH
sub remL,divL ;remainder = remainder -
divisor
sbc remH,divH ;
brcc d17u_2 ;if result negative
add remL,divL ; restore remainder
adc remH,divH
clc ; clear carry to
be shifted into result
rjmp d17u_3 ;else

d17u_2: sec
d17u_3: rol didL ;shift left
dividend
rol didH
dec temp ;decrement counter
brne d17u_1 ;if done
ret ; return with
value in didL

;
***************************************************************************
;*
;* "mpy9u" - 9x8 Bit Unsigned Multiplication
;*
;* This subroutine multiplies the two register
variables (carry:mp9u) and mc9u.
;* The result is placed (carry:m8uH:m8uL)
;*
;* Number of words :11 (return included)
;* Number of cycles : (return included)
;* Low registers used :3 (mp9u,mc9/m9uL,m9uH)
;* High registers used :1 (temp)
;*
;* Note: Result Low byte and the multiplier share the
same register.
;* This causes the multiplier to be overwritten by the
result.
;*
;
***************************************************************************

mpy9u: clr m9uH ;clear

result High byte
ldi temp,9 ;init loop counter
ror mp9u

m9u_1: brcc m9u_2 ;if bit 0

of multiplier set
add m9uH,mc9u ; add
multiplicand to result High byte

m9u_2: dec temp ;decrement

loop counter
brne m9u_3 ;if not done, loop
more
ret

m9u_3: ror m9uH ;shift

right result High byte
ror m9uL ;rotate right
result L byte and multiplier
rjmp m9u_1

Programming the AVR Microcontrollers in Machine Language

AVR
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected

from Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing,
intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still
be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
http://avr-asm.tripod.com/avr401.html (1 of 2)1/20/2009 9:08:03 PM
16 BIT MATH (AVR 202)

The next machine instruction is fetched as the current one is

executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language

http://avr-asm.tripod.com/avr401.html (2 of 2)1/20/2009 9:08:03 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

THERMOMETER DS1820 VIA RS232 PROGRAM

HOME
RETRO_DAN
;***********************************************************************
ASM FORUM ;*
ASM MATH ;* Number :DS1820
;* File Name :"DS1820.asm"
TUTORIAL #1
;* Title :AVR alapu DS1820 thermometer + RS232 interface
TUTORIAL #2 ;* - LM16x21A Driver via Lattice ispLSI2032
TUTORIAL #3 ;*
;* Date :2000.06.12.
MATH 200 ;* Version :1.0
MATH 200b ;* Support telephone :+36-70-333-4034
;* Support fax :
MATH 201 ;* Support E-mail :info@vfx.hu
MATH 202 ;* Target MCU :AT90S2313
;*
MATH 32X
;* DESCRIPTION
MATH YX ;* kezeli a következõ eszközöket:
;* - DS1820 Thermometer unit
DIV16 XX
;* - Fulduplex RS232 port
DIV 24 24 ;* - SS0=0 & SS1=0 akkor az LCD port az SPI target
DIV 3216 ;*
;* AT90S2313 lábkiosztás
FLOAT 128 ;*
SQRT16 ;* RESET 1. 20. VCC
;* * RxD (PD0) 2. 19. (PB7) SCK *
MATH 202 ;* * TxD (PD1) 3. 18. (PB6) MISO *
MATH 202 ;* XTAL2 4. 17. (PB5) MOSI *
;* XTAL1 5. 16. (PB4) SS0 *
DEC ASCII
;* INT0 (PD2) 6. 15. (PB3 OC1) LED0
INT ASCII ;* INT1 (PD3) 7. 14. (PB2) SS1 *
;* (T0 PD4) 8. 13. PB1 {AIN1} AT45D CS
HX2ASC
;* DS1820 T1 (PD5) 9. 12. PB0 {AIN0}
AVG8 222 ;* GND 10. 11. {PD6 ICP}
FFT7 ;*
;* Kristályfrekvencia: f=1.8432 MHz (T=0.54253 us)
COPY 102 ;*
LPM 108 ;* * a csillagos IO labak fix huzalozasuak, masra nem hasznalhatok fel!!!
;***********************************************************************
EPROM 100 .include "2313def.inc"
SER EPROM
DFLASH AT45
;
FLASH CARD **************************************************************************
;* Hardware Def.
VFX SMIL
VFX MEM .EQU DS1820_BIT = 5 ;Dallas 1-Wire bus
SORT 220 .EQU DS1820_PORT =DDRD ;Dallas Port cime

CRC 236
XMODEM REC .EQU LEDPORT = DDRB
.EQU LED = 3 ;A LED bitcime
UART 304
UART 305
;SPI selector - 00 LCD
UART 128
.EQU SS0PORT= DDRB
UART BUFF .EQU SS0= BP4
USB 232 .EQU SS1PORT= DDRB
.EQU SS1= BP2
AVR ISP
ISP 2313
;
ISP 1200 **************************************************************************
AVR SPI ;* UART Def
.EQU BaudRate=11 ;11 - 9600
I2C 300 ;7 - 14400
I2C 302 ;5 - 19200
;1 - 57600
I2C TWI26
I2C/TWI 128
I2C/TWI AT8
;
DALLAS-1W ***************************************************************************
DALLAS CRC ;***** Divide Subroutine Register Variables

ETHNET 8019 .def drem16uL=r14

TEA .def drem16uH=r15
.def dres16uL=r16
ADC 128 .def dres16uH=r17
ADC 10B .def dd16uL =r16
.def dd16uH =r17
ADC 400
.def dv16uL =r18
ADC 401 .def dv16uH =r19
THERM 232
IRD 410
LCD HD44 ;
***************************************************************************
LCD 2313 ;* SPI Master, Mode 0, MSB-first
LCD44 2313 ;*
;* MAJOR ROUTINES:
KBD 240 ;* init_spi: initializes the port lines used for SPI.
MUX 242 ;* No calling requirements, returns nothing.
;* ena_AT: forces SCK low, and activates /SS signal.
KBD PS2
;* No calling requirements, returns nothing.
KBD PC/128 ;* disa_AT: brings /SS signal hi (inactive).
PS2 EMU ;* No calling requirements, returns nothing.
;* rw_spi: sends/receives an 8-bit data.
BOOT MG8 ;* Must set up data to be sent in (spi_lo)
BOOT DR8 ;* prior to calling; it returns received data in
;* the same register (spi_lo register).
ALM CLK ;*
CLOCK 8564 ;*
.equ sck = 7 ;PB7 pin
90 DAYS
.equ miso = 6 ;PB6 pin
DELAYS .equ mosi = 5 ;PB5 pin
CALL ID
.equ ATss = 1 ;PB4=1 , PB2=0 pin AT45D041 CS ???????
DTMF 314
PWM 6CH .def spi_lo = R0 ;change as needed
.def temp = R16 ;misc usage, must be in upper regs for IMMED
PWM 10K mode
ENCODE .def ATComm = R20 ;AT45Dxxx command parameter register
.def ATPoint = R21 ;AT45Dxxx Buffer Pointer register
STH-11 .def ATPageL = R21 ;AT45Dxxx Page Address low
ATMEL CORP .def ATPageH = R22 ;AT45Dxxx Page Address hi
AVR
.def LCDLo = R20 ;LCD Low byte
BUTTERFLY .def LCDHi = R21 ;
AVR BOOK

.equ BFSeg = 32 ;32 byte r/w

.macro Select_LCD
CBI SS0PORT+1,SS0
cbi SS1PORT+1,SS1
.endm

;
***************************************************************************
;*
;* SPI MACROS
;* Program Macros

.macro AT_active
cbi portb,ATss
.endm

.macro AT_inactive
sbi portb,ATss
.endm

.macro sck_hi
sbi portb,sck
.endm

.macro sck_lo
cbi portb,sck
.endm

.macro mosi_hi
sbi portb,mosi
.endm

.macro mosi_lo
cbi portb,mosi
.endm

;.macro addi
; subi @0, -@1 ;subtract the negative of an immediate value
;.endm

.macro set_delay ;set up the time delay amount, from 1

to 7
subi @0, (@1 << 5) ;NOTE: THIS shift affects INC macro (below)!
.endm

.macro inc_delay ;bump the delay counter

subi @0, -(1 << 5) ;shift value here must be same as above!
.endm

;
******************************************************************************
;**** CONST

;;;;.EQU RPMFACT = 17280 ;RPM= RPMFACT/IMP*100

.EQU T0Freq=220 ;1.8432MHz = 50Hz

;FLAGS
.EQU Active = 2 ;Imo Active bit

;
******************************************************************************
;**** VARIABLES
.DSEG
DS1: .BYTE 1 ;Flagbitek
; 0. = 1 RPM overflow
; 1. = 1 Velocity overflow
; 2. = 1 Immo. Active
; 4. = 1 LED kijelzo frissites kell

CNT1: .BYTE 2 ;Interupt COUNTER

DS3: .BYTE 4 ;RealTime Clock
DS4: .BYTE 2 ;UART Transmit Interrupt rutin cime
DS5: .BYTE 2 ;UART Receive Interrupt rutin cime
DS6: .BYTE 2 ;UART Transmit Buffer Address
DS7: .BYTE 2 ;Fordulatszam binaris
DS8: .BYTE 2 ;Sebesseg bin
DS9: .BYTE 2 ;Fordulatszamalalo start
DS10: .BYTE 2 ;SebessegSZAMLALO start
DS11: .BYTE 1 ;TEMP az UART RX-hez
CRC: .BYTE 1 ;DS1820 CRC GENERATOR HASZNALJA
DSRD: .BYTE 10 ;Ide olvassa be a DS Chipet
DS12: .BYTE 1 ;Bad CRC szamlalo
IOBuff: .BYTE BFSeg ;AT45Dxxx IO munkaterulet

;*Variables Offset to Y

.EQU FLAGS = DS1-DS1 ;Z+0

.EQU RTC = DS3-DS1 ;RealTime Clock
.EQU UTx = DS4-DS1 ;UART Transmit Interrupt
rutin cime
.EQU URx = DS5-DS1 ;UART Receive Interrupt rutin
cime
.EQU TXT = DS6-DS1 ;UART Transmit Buffer Address
.EQU RPMB = DS7-DS1 ;Fordulatszam binaris
.EQU VELB = DS8-DS1 ;Sebesseg bin
.EQU RPMC = DS9-DS1 ;Fordulatszamalalo start
.EQU VELC = DS10-DS1 ;SebessegSZAMLALO start
.EQU TEMP = DS11-DS1 ;TEMP az UART RX-hez
.EQU CRCoff = CRC-DS1 ;CRC
.EQU CNT1L = CNT1-DS1 ;CNT1
.EQU CNT1H = CNT1-DS1+1
.EQU BadCRC = DS12-DS1 ;

;
**************************************************************************************
.ESEG
KEY1: .DB 0x01
.DB 0x88
.DB 0xDD
.DB 0x07
.DB 0x02
.DB 0x00
.DB 0x00
KEY2: .DB 0x01
.DB 0x6D
.DB 0xB9
.DB 0x07
.DB 0x02
.DB 0x00
.DB 0x00

;
*****************************************************************************
;**** I N T E R R U P T S
;****
;
*****************************************************************************
.CSEG
rjmp RESET ;Reset Handle
rjmp EXT_INTO ;IRQ0 Handle
rjmp EXT_INT1 ;IRQ1 Handle
rjmp TIM_CAPT1 ;Timer1 capture Handle
rjmp TIM_COMP1 ;Timer1 compare Handle
rjmp TIM_OVF1 ;Timer1 overflow Handle
rjmp TIM_OVF0 ;Timer0 overflow Handle
rjmp UART_RXC ;UART RX Complete Handle
rjmp UART_DRE ;UDR Empty Handle
rjmp UART_TXC ;UART TX Complete Handle
rjmp ANA_COMP ;Analog Comparator Handle

;***********
;* RESET
;***********
RESET: CLI ;GLOBAL INTERRUP DIS.

LDI R16,42 ;Sleep enable, Idle mode,INT0, INT1 fall-edge

sens.
OUT MCUCR,R16

LDI R16,RAMEND
OUT SPL,R16 ;STACK A BELSO RAM VEGETOL INDUL LEFELE

LDI R16,0 ;INT0, INT1 Disabled

OUT GIMSK,R16 ;7. = 1 EXT INT1 ACTIVE
;6. = 1 EXT INT0 ACTIVE

LDI R16,2
OUT TIMSK,R16 ;7. = 1 TC1 OWRF EN. *
;6. = 1 TC1 COMP MATCH EN.
;3. = 1 TC1 INP CAPTURE EN.
;1. = 1 TC0 OWRF EN. *

LDI R16,0
OUT TCCR1A,R16 ;TC1 Disconected from OC1 pin, PWM Dis.
LDI R16,3
OUT TCCR1B,R16 ;Input Capture Dis., f=CLK/64

LDI R16,T0Freq
OUT TCNT0,R16 ;50Hz
LDI R16,5
OUT TCCR0,R16 ;f(TC1)=CLK/1024

LDI YL,LOW(DS1)
LDI YH,HIGH(DS1) ;BAZIS 'X' +0

LDI R16,0

STD Y+CRCoff,R16 ;CRC=0

STD Y+CNT1L,R16
STD Y+CNT1H,R16 ;CNT1=0

STD Y+RTC+0,R16 ;RealTime Clock=1970\01\01

STD Y+RTC+1,R16
STD Y+RTC+2,R16
STD Y+RTC+3,R16
STD Y+BadCRC,R16 ;BadCRC=0

LDI R16,(1< R0
ADIW ZL,1
MOV R16,R0
STD Y+TXT+0,ZL
STD Y+TXT+1,ZH
CPI R16,0
BRNE MoreTXT ;VAN MEG SZOVEG

LDI R16,low(UReti)
STD Y+UTx+0,R16
LDI R16,high(UReti)
STD Y+UTx+1,R16 ;UART TX INT. ADDR
CPSE R16,R16 ;AZERT, HOGY
AKOVETKEZO SOR KIMARADJON

MoreTXT: OUT UDR,R16

POP R0
POP R16
POP ZL
OUT SREG,ZL
POP ZH
POP ZL
RETI

;*************************************************************************
;* Text Const
;*
Copyr: .DB "(C) 2000, DS1820 Thermometer V1.0 ", 10,13
Ready: .DB "Ready>>",0
Hiba: .DB "Error..",10,13,0

;***********************************************************************
;***********************************************************************
;******** M A I N ********
;******** ********
;***********************************************************************
Main: LDI R16,10
STD Y+CNT1L,R16
LDI R16,0
STD Y+CNT1H,R16 ;CNT1=25 0.5s

wait: ;SLEEP

ldd R16,Y+TEMP
CPI R16,'R'
BREQ WHTROM
CPI R16,'r'
BREQ WHTROM

CPI R16,'T'
BREQ RDTH
CPI R16,'t'
BREQ RDTH

rjmp Csokkent

RDTH: cli
rcall ReadTh
sei
brcc CMDsEND ;ha nincs eszkoz a buszon, akkor
kihagy

rcall ComuteT ;R22,R23 a korigalt hom

MOV R0,R23
rcall TOUART
MOV R0,R22
rcall TOUART

Wt6: SBIS USR,UDRE ;a kovetkezo kimarad, ha a TX

reg ures
RJMP Wt6
LDI R16,' '
OUT UDR,R16

Wt7: SBIS USR,UDRE ;a kovetkezo kimarad, ha a TX

reg ures
RJMP Wt7
LDI R16,' '
OUT UDR,R17

LDI XL,LOW(DSRD)
LDI XH,HIGH(DSRD) ;ide olvasta a DS Chipet
LDI R19,8 ;8 byteot kuldunk ki
rjmp WHTR1

WHTROM: CLI
rcall ReadROM
SEI
brcc CMDsEND ;ha nincs eszkoz a buszon, akkor
kihagy

LDI R19,8 ;8 byteot kuldunk ki

LDI XL,LOW(DSRD)
LDI XH,HIGH(DSRD) ;ide olvasta a DS Chipet

WHTR1: LD R16,X+
MOV R0,R16
rcall TOUART
Wt4: SBIS USR,UDRE ;a kovetkezo kimarad, ha a TX
reg ures
RJMP Wt4
LDI R16,' '
OUT UDR,R16
dec R19
BRNE WHTR1

CMDsEND: SBIS USR,UDRE ;a kovetkezo kimarad, ha a TX reg ures

RJMP CMDsEND
LDI R16,13
OUT UDR,R16

Wt9: SBIS USR,UDRE ;a kovetkezo kimarad, ha a TX

reg ures
RJMP Wt9
LDI R16,10
OUT UDR,R16
LDI R16,0
std Y+TEMP,R15 ;a parancssort kinullazzuk

Csokkent: LDD R24,Y+CNT1L

LDD R25,Y+CNT1H
OR R24,R25
BRNE wait

;Kell-e villogni?

LDD R16,Y+FLAGS
SBRS R16,Active ;a kovetkezo kimarad ha az Active=1
rjmp Main

; Led villogtato

LEDvil: SBIS LEDPORT+1,LED ;kihagy, ha LED=1

RJMP Led_be
CBI LEDPORT+1,LED ;LED eg
RJMP Main
Led_be: SBI LEDPORT+1,LED ;LED nem eg
RJMP Main

;CRC-t ellenorzi
; LD R1,X+ ;olvasott CRC
; LDD R0,Y+CRCOff ;szamolt CRC
; CP R1,R0
; BREQ CRCOK ;GoodCRC

;R0-ban levo byte kiirasa az uartra (HEX)

TOUART: LDI R17,48

LDI R18,7

Wt1: SBIS USR,UDRE ;a kovetkezo kimarad, ha a TX

reg ures
RJMP Wt1

MOV R16,R0
SWAP R16
ANDI R16,0x0F
CPI R16,10
BRCS Kicsi1
ADD R16,R18
Kicsi1: ADD R16,R17
OUT UDR,R16

Wt2: SBIS USR,UDRE ;a kovetkezo kimarad, ha a TX

reg ures
RJMP Wt2

MOV R16,R0
ANDI R16,0x0F
CPI R16,10
BRCS Kicsi0
ADD R16,R18
Kicsi0: ADD R16,R17
OUT UDR,R16

ret

.include "div16.asm"
.include "SPI.asm"

;************************************************************************
;*********************** 1-Wire Bus *************************************
;************************************************************************
;------------------------------------------------------------------------
;Kiolvasott DS chip tartalmat osszehasonlitja az EEpromban taroltakkal
;
; R14 a KEY Offsetcime
;
;C=0 Nem jo
;C=1 Kulcs jo
DScomp:
LDI XL,LOW(DSRD)
LDI XH,HIGH(DSRD) ;ide olvassa DS Chipet
OUT EEAR,R24 ;EEPROM address

LDI R16,7 ;CRC-vel egyutt 8 byte comp.

Cikl2: RCALL EERead_seq ;EEPrombol akovetkezo elem R0-ba

LD R1,X+
SUB R1,R0
BRNE Rossz
DEC R16
BRNE Cikl2
SEC
RET
Rossz: CLC
RET

;***********************************************************************
;.......................................................................
;Read DS1820
;c=1 Chip kiolvasva
;c=0 Chip nincs
;(Beolvas egy chippet az Y-ban megadott cimre)
;
;Hasznalja a R18, R17, R16, R3, R2, R0;
;.......................................................................
ReadROM:
LDI XL,LOW(DSRD)
LDI XH,HIGH(DSRD) ;ide olvassa DS Chipet
LDI R16,0
STD Y+CRCoff,R16 ;CRC=0 ;
RCALL TouchReset
BRCS RDS1 ;ESZKOZ A BUSZON VAN
CLC
RET

RDS1: LDI R16,0x33 ;SEARCH ROM COMMAND

MOV R0,R16
LDI R19,7 ;7-SZER OLVASUNK BE
RCALL TouchByte
RDS2: LDI R16,0xFF ;BEOLVASUNK 8 BITET
MOV R0,R16
RCALL TouchByte
ST X+,R1
RCALL CRCGEN
DEC R19
BRNE RDS2

LDI R16,0xFF ;BEOLVASSUK A CRCT

MOV R0,R16
RCALL TouchByte
ST X+,R1

LDI R19,0xFF
RDS3: DEC R19
BRNE RDS3
SEC ;CHIP RENDBEN
RET

;
****************************************************************************
;******* TOUCHBYTE
;
****************************************************************************
;
;R0-ban megadott byte-ot kiküldi a touchmemory-nak
;és szimultán beolvas egy byte-ot onnan az R1-be
;Hasznalja a R17, R16 R3, R2
;
TouchByte:
LDI R17,8 ;[1]
BIT_LOOP:
ROR R1 ;[1]
RCALL TOUCHBIT ;[3]
ROR R0 ;[1]
DEC R17 ;[1]
BRNE BIT_LOOP ;[1/2]
RET ;[1]
TOUCHBIT:
SBI DS1820_PORT,DS1820_BIT ;[2]
LDI R16,3 ;[1]
BW0: DEC R16 ;[1]
BRNE BW0 ;[1/2]
SBRC R0,0 ;[1/2]
CBI DS1820_PORT,DS1820_BIT ;[2]
LDI R16,8 ;[1]
BW1: DEC R16 ;[1]
BRNE BW1 ;[1/2]
IN R2,DS1820_PORT-1 ;[1]
BST R2,DS1820_BIT ;[1]
BLD R1,7 ;[1]
LDI R16,26 ;[1]
TCHL: DEC R16 ;[1]
BRNE TCHL ;[1/2]
CBI DS1820_PORT,DS1820_BIT ;[2]
RET ;[4]

;
*******************************************************************************
;****** T O U C H R E S E T
;
*******************************************************************************
;
;Inicialization procedure "Reset and PreSence Pulses"
;
; Ez a rutin egy Reset jelet general a mikrovrzerlo ketiranyu DS_BIT nevu
laban,
;a Touch Memory fele es figyeli a visszajovo PreSence jelet.
;Ha a PreSence jel megerkezett, akkor C=1 kulonben C=0 (nincs eszkoz a
buszon)
;
; |-Master Rx "Presence Pulse"-|
; |---Master Reset Tx Pulse---| |----t(RSTH)---------------|
; __ t(RSTL) _____ _____ \\ ___
; \ / \ / \
; \_________________________/ \______/ \__ ...
; |-----|-------|
; t(PDH) t(PDL)
; t(R) <-- |-|
;
; 480us<=t(RSTL)< . t(RSTL)+t(R)<960us
; 480us<=t(RSTH)<
; 15us<=t(PDH)<=60us
; 60us<=t(PDL)<=240us
;
; C-flag = 1 DS1990A a buszon van
; = 0 DS1990A nincs a buszon
;
; R16

; Testelt jol mukodik

; Cyc:
TouchReset:
SBI DS1820_PORT,DS1820_BIT ;[2] 1-wire = Master LOW , Start
the reset pulse
LDI R16,222 ;[1]
TR0: NOP ;[1]
DEC R16 ;[1]
BRNE TR0 ;[1/2] 480us wait with data
low
SBI DS1820_PORT+1,DS1820_BIT ;[2] 1-wire =Active Hi
nop ;[1]
CBI DS1820_PORT,DS1820_BIT ;[2] 1-wire HI (felengedve)
CBI DS1820_PORT+1,DS1820_BIT ;[2] 1-wire = Tri-state
nop ;[1]
SBIS DS1820_PORT-1,DS1820_BIT ;[1/2]
RJMP Short ;[2] ha egybol Low az rossz
LDI R16,21 ;[1]
TR1: SBIS DS1820_PORT-1,DS1820_BIT ;[1/2]
RJMP WL ;[2] Exit loop if line low
DEC R16 ;[1]
BRNE TR1 ;[1/2] us wait with data low
RJMP SHORT ;[2] Line could not go low
WL: LDI R16,87 ;[1]
TR3: SBIC DS1820_PORT-1,DS1820_BIT ;[1/2]
RJMP WH ;[2] Exit loop if line hi
DEC R16 ;[1]
BRNE TR3 ;[1/2] us wait with data low
SHORT: CLC ;[1] Error
RET ;[4]
WH: SEC ;[1] RESET OK.
RET ;[4]

;*************************************************************************
;.........................................................................
; DS1990A CRC GENERATOR
;IN: R1
;USE: R21,R20, R4,R3, R0, R18
;.........................................................................
CRCGEN: PUSH R1
LDI R20,8
LDI R18,0x18
PUSH R1

CRC_L: LDD R3,Y+CRCoff ;CRC

EOR R1,R3
ROR R1
MOV R1,R3
BRCC ZERO
EOR R1,R18
ZERO: ROR R1
STD Y+CRCoff,R1
POP R1
SEC
SBRS R1,0
CLC
ROR R1
PUSH R1
DEC R20
BRNE CRC_L
POP R1

POP R1
RET

;***********************************************************************
;.......................................................................
;Read DS1820
;c=1 Chip kiolvasva
;c=0 Chip nincs
;(Beolvas egy chippet az Y-ban megadott cimre)
;
;Hasznalja a R18, R17, R16, R3, R2, R0;
;.......................................................................
ReadTh:
LDI XL,LOW(DSRD)
LDI XH,HIGH(DSRD) ;ide olvassa DS Chipet
LDI R16,0
STD Y+CRCoff,R16 ;CRC=0
RCALL TouchReset
BRCS DSVAN ;ESZKOZ A BUSZON VAN
CLC
RET

DSVAN: LDI R16,0xCC ;Skip ROM Command

MOV R0,R16
RCALL TouchByte

LDI R16,0x44 ;Convert T Command

MOV R0,R16
RCALL TouchByte

nop
nop
nop
nop
nop
nop
nop

DSW1: SBIS DS1820_PORT-1,DS1820_BIT ;ha 1 akkor a

kovetkezo kimarad
RJMP DSW1 ;varunk mig a komvertalas vege nincs

nop
nop

LDI R16,0
STD Y+CRCoff,R16 ;CRC=0 ;
RCALL TouchReset
BRCS DS2VAN ;ESZKOZ A BUSZON VAN
CLC
RET

DS2VAN:
LDI R16,0xCC ;Skip ROM Command
MOV R0,R16
RCALL TouchByte

LDI R16,0xBE ;Read Scratchpad command.

MOV R0,R16
RCALL TouchByte

nop
nop

LDI R19,8 ;8-SZOR OLVASUNK BE

DS2T: LDI R16,0xFF ;BEOLVASUNK 8 BITET
MOV R0,R16
RCALL TouchByte
ST X+,R1
RCALL CRCGEN
DEC R19
BRNE DS2T

LDI R16,0xFF ;BEOLVASSUK A CRCT

MOV R0,R16
RCALL TouchByte
ST X+,R1

LDI R19,0xFF
DS3T: DEC R19
BRNE DS3T
RCALL TouchReset
SEC ;CHIP RENDBEN
RET

;Tc=8T-2+(8*Count-8*Remainder)/8Count

ComuteT: LDI ZL,LOW(DSRD)

LDI ZH,HIGH(DSRD) ;ide olvassa DS Chipet

LDD dd16uL,Z+7 ;CPC

LDI dd16uH,0

LDD R22,Z+6 ;CRM

LDI R23,0

LSL dd16uL ;8*CPC

ROL dd16uH
LSL dd16uL
ROL dd16uH
LSL dd16uL
ROL dd16uH

LSL R22 ;8*CRM

ROL R23
LSL R22
ROL R23
LSL R22
ROL R23

SUB dd16uL,R22
SBC dd16uH,R23

LDD dv16uL,Z+7 ;CPC

LDI dv16uH,0

http://avr-asm.tripod.com/therm232.html (1 of 2)1/20/2009 9:08:49 PM

16 BIT MATH (AVR 202)

MOV R0,dv16uL
OR r0,dv16uH
BRNE DIV1 ;0-VAL NEM OSZTUNK
LDI R16,0
LDI R17,0
RJMP LKI1

DIV1: RCALL div16u ;OSZTAS eredmeny az

R16,R17-ben

LKI1: CLC
SBCI dres16uL,2
SBCI dres16uH,0 ;eredmeny-2

LDD R22,Z+0 ;Temperature

LDD R23,Z+1
CBR R22,1 ;Truncate 0.5C

LSL R22 ;8*T

ROL R23
LSL R22
ROL R23
LSL R22
ROL R23

ADD R22,dres16uL ;R22,R23 a korigalt

homerseklet
ADC R23,dres16uH
ret

;
***************************************************************************
;*
;* EERead_seq
;*
;* This subroutine increments the address stored in EEAR and reads the
;* EEPROM into the register variable "EEdrd_s".
;*
;* Number of words :8515 ; 7 + return
;* Number of cycles :8515 ; 11 + return (if EEPROM is ready)
;* Low Registers used :R0
;* High Registers used: :R24
;*
;
***************************************************************************
EERead_seq:
sbic EECR,EEWE ;if EEWE not clear
rjmp EERead_seq ; wait more
;The above sequence for EEWE = 0
;can be skipped if no write is initiated.
in R24,EEAR ;get address low 8515
inc R24 ;increment address 8515
out EEAR,R24 ;output address 8515

sbi EECR,EERE ;set EEPROM Read strobe

;This instruction takes 4 clock cycles since
;it halts the CPU for two clock cycles
in R0,EEDR ;get data
ret

;
***************************************************************************
;*
;* FUNCTION
;* ena_LCD
;*
;* DESCRIPTION
;* Init data & clock lines, then assert /CS for LCD.
;*
;* CODE SIZE:
;* 4 words
;*
;
***************************************************************************

ena_LCD:
sck_lo ;(should already be there...)
mosi_lo
Select_LCD
ret

;* LCDlo, LCDHi - kikuldese

RW_LCD:
mov spi_lo,LCDHi ;Mov Command byte
rcall ena_LCD ;activate /CS
rcall rw_spi ;send Command byte
mov spi_lo,LCDLo ;Mov Command byte
rcall rw_spi ;send Command byte
ret
;**** A P P L I C A T I O N N O T E A V R 2 0 0
************************
;*
;* Title: Multiply and Divide Routines
;* Version: 1.1
;* Last updated: 97.07.04
;* Target: AT90Sxxxx (All AVR Devices)
;*
;* Support E-mail: avr@atmel.com
;*

;* DESCRIPTION
;* This Application Note lists subroutines for the following
;* Divide applications. Routines are straight-line implementations
;* optimized for speed:
;*
;* 16 / 16 = 16 + 16 bit unsigned
;*

;
***************************************************************************

;
***************************************************************************
;*
;* "div16u" - 16/16 Bit Unsigned Division
;*
;* This subroutine divides the two 16-bit numbers
;* "dd16uH:dd16uL" (dividend) and "dv16uH:dv16uL" (divisor).
;* The result is placed in "dres16uH:dres16uL" and the remainder in
;* "drem16uH:drem16uL".
;*
;* Number of words :196 + return
;* Number of cycles :148/173/196 (Min/Avg/Max)
;* Low registers used :2 (drem16uL,drem16uH)
;* High registers used :4 (dres16uL/dd16uL,dres16uH/dd16uH,dv16uL,dv16uH)
;*
;
***************************************************************************

;***** Code

div16u: clr drem16uL ;clear remainder Low byte

sub drem16uH,drem16uH;clear remainder High byte and carry

rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_1 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into result
rjmp d16u_2 ;else
d16u_1: sec ; set carry to be shifted into
result

d16u_2: rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_3 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into result
rjmp d16u_4 ;else
d16u_3: sec ; set carry to be shifted into
result

d16u_4: rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_5 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into result
rjmp d16u_6 ;else
d16u_5: sec ; set carry to be shifted into
result

d16u_6: rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_7 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into result
rjmp d16u_8 ;else
d16u_7: sec ; set carry to be shifted into
result

d16u_8: rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_9 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into result
rjmp d16u_10 ;else
d16u_9: sec ; set carry to be shifted into
result

d16u_10:rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_11 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into result
rjmp d16u_12 ;else
d16u_11:sec ; set carry to be shifted into result

d16u_12:rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_13 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into result
rjmp d16u_14 ;else
d16u_13:sec ; set carry to be shifted into result

d16u_14:rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_15 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into result
rjmp d16u_16 ;else
d16u_15:sec ; set carry to be shifted into result

d16u_16:rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_17 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into result
rjmp d16u_18 ;else
d16u_17: sec ; set carry to be shifted into
result

d16u_18:rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_19 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into result
rjmp d16u_20 ;else
d16u_19:sec ; set carry to be shifted into result

d16u_20:rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_21 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into result
rjmp d16u_22 ;else
d16u_21:sec ; set carry to be shifted into result

d16u_22:rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_23 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into result
rjmp d16u_24 ;else
d16u_23:sec ; set carry to be shifted into result

d16u_24:rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_25 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into result
rjmp d16u_26 ;else
d16u_25:sec ; set carry to be shifted into result

d16u_26:rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_27 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into result
rjmp d16u_28 ;else
d16u_27:sec ; set carry to be shifted into result

d16u_28:rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_29 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into result
rjmp d16u_30 ;else
d16u_29:sec ; set carry to be shifted into result

d16u_30:rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_31 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into result
rjmp d16u_32 ;else
d16u_31:sec ; set carry to be shifted into result

d16u_32:rol dd16uL ;shift left dividend

rol dd16uH
ret

Programming the AVR Microcontrollers in Machine Language

AVR
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr)
Jump to: navigation, search The AVRs are a family of RISC
microcontrollers from Atmel. Their internal architecture was conceived by
two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel Norway, a
subsidiary founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices
featuring SIMD and DSP instructions, along with many additional features
for audio and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to the 8-bit
RISC line of Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also rumoured to stand
for the company's founders: Alf and Vegard, who are evasive when
questioned about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program
Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion
Groups 6.3 Machine Language Development 6.4 C Language Development
6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other
AVR Links [edit] Device Overview The AVR is a Harvard architecture
machine with programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die, removing the
need for external memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-permanent
Flash memory. Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word sizes. The size
of the program memory is indicated in the naming of the device itself. For
instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and Registers The
data address space consists of the register file, I/O registers, and SRAM.
The AVRs have thirty-two single-byte registers and are classified as 8-bit
RISC devices. The working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O registers (002016-
005F16). The actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on some more
extensive devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are separate
addressing schemes and optimized opcodes for register file and I/O
register access, all can still be addressed and manipulated as if they were
in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program Execution Atmel's
AVRs have a single level pipeline design. The next machine instruction is
fetched as the current one is executing. Most instructions take just one or
two clock cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were designed for the
efficient execution of compiled C code. The AVR instruction set is more
orthogonal than most eight-bit microcontrollers, however, it is not
completely regular: Pointer registers X, Y, and Z have addressing
capabilities that are different from each other. Register locations R0 to
R15 have different addressing capabilities than register locations R16 to
R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports
32 to 63. CLR affects flags, while SER does not, even though they are
complementary instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native instructions.
Instead CLR is syntactic sugar for [produces the same machine code as]
EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations
such as EOR modify flags while moves/loads/stores/branches such as
LDI do not.) [edit] Speed The AVR line can normally support clock speeds
from 0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs feature an on-
chip oscillator, removing the need for external clocks or resonator
circuitry. Because many operations on the AVR are single cycle, the AVR
can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large
following due to the free and inexpensive development tools available,
including reasonably priced development boards and free development
software. The AVRs are marketed under various names that share the
same basic core but with different peripheral and memory combinations.
Some models (notably, the ATmega range) have additional instructions to
make arithmetic faster. Compatibility amongst chips is fairly good. See
external links for sites relating to AVR development. [edit] Features
Current AVRs offer a wide range of features: RISC Core Running Many
Single Cycle Instructions Multifunction, Bi-directional I/O Ports with
Internal, Configurable Pull-up Resistors Multiple Internal Oscillators
Internal, Self-Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage methods
Optional Boot Code Section with Independent Lock Bits for Protection
Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit
Timers PWM Channels & dead time generator Lighting (PWM Specific)
Controller models Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used
with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed hardware
& Hub controller with embedded AVR. Also freely available low-speed
(HID) software emulation Ethernet Controller Support Universal Serial
Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog
Comparators LCD Controller Support 10-Bit A/D Converters, with
multiplex of up to 16 channels Brownout Detection Watchdog Timer
(WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR assembler
programming language Atmel AVR machine programming language
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr)
Jump to: navigation, search The AVRs are a family of RISC
microcontrollers from Atmel. Their internal architecture was conceived by
two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel Norway, a
subsidiary founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices
featuring SIMD and DSP instructions, along with many additional features
for audio and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to the 8-bit
RISC line of Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also rumoured to stand
for the company's founders: Alf and Vegard, who are evasive when
questioned about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program
Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion
Groups 6.3 Machine Language Development 6.4 C Language Development
6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other
AVR Links [edit] Device Overview The AVR is a Harvard architecture
machine with programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die, removing the
need for external memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-permanent
Flash memory. Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word sizes. The size
of the program memory is indicated in the naming of the device itself. For
instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and Registers The
data address space consists of the register file, I/O registers, and SRAM.
The AVRs have thirty-two single-byte registers and are classified as 8-bit
RISC devices. The working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O registers (002016-
005F16). The actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on some more
extensive devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are separate
addressing schemes and optimized opcodes for register file and I/O
register access, all can still be addressed and manipulated as if they were
in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program Execution Atmel's
AVRs have a single level pipeline design. The next machine instruction is
fetched as the current one is executing. Most instructions take just one or
two clock cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were designed for the
efficient execution of compiled C code. The AVR instruction set is more
orthogonal than most eight-bit microcontrollers, however, it is not
completely regular: Pointer registers X, Y, and Z have addressing
capabilities that are different from each other. Register locations R0 to
R15 have different addressing capabilities than register locations R16 to
R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports
32 to 63. CLR affects flags, while SER does not, even though they are
complementary instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native instructions.
Instead CLR is syntactic sugar for [produces the same machine code as]
EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations
such as EOR modify flags while moves/loads/stores/branches such as
LDI do not.) [edit] Speed The AVR line can normally support clock speeds
from 0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs feature an on-
chip oscillator, removing the need for external clocks or resonator
circuitry. Because many operations on the AVR are single cycle, the AVR
can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large
following due to the free and inexpensive development tools available,
including reasonably priced development boards and free development
software. The AVRs are marketed under various names that share the
same basic core but with different peripheral and memory combinations.
Some models (notably, the ATmega range) have additional instructions to
make arithmetic faster. Compatibility amongst chips is fairly good. See
external links for sites relating to AVR development. [edit] Features
Current AVRs offer a wide range of features: RISC Core Running Many
Single Cycle Instructions Multifunction, Bi-directional I/O Ports with
Internal, Configurable Pull-up Resistors Multiple Internal Oscillators
Internal, Self-Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage methods
Optional Boot Code Section with Independent Lock Bits for Protection
Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit
Timers PWM Channels & dead time generator Lighting (PWM Specific)
Controller models Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used
with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed hardware
& Hub controller with embedded AVR. Also freely available low-speed
(HID) software emulation Ethernet Controller Support Universal Serial
Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog
Comparators LCD Controller Support 10-Bit A/D Converters, with
multiplex of up to 16 channels Brownout Detection Watchdog Timer
(WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR assembler
programming language Atmel AVR machine programming language
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr)
Jump to: navigation, search The AVRs are a family of RISC
microcontrollers from Atmel. Their internal architecture was conceived by
two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel Norway, a
subsidiary founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC devices
featuring SIMD and DSP instructions, along with many additional features
for audio and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to the 8-bit
RISC line of Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also rumoured to stand
for the company's founders: Alf and Vegard, who are evasive when
questioned about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program
Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion
Groups 6.3 Machine Language Development 6.4 C Language Development
6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other
AVR Links [edit] Device Overview The AVR is a Harvard architecture
machine with programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die, removing the
need for external memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-permanent
Flash memory. Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word sizes. The size
of the program memory is indicated in the naming of the device itself. For
instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and Registers The
data address space consists of the register file, I/O registers, and SRAM.
The AVRs have thirty-two single-byte registers and are classified as 8-bit
RISC devices. The working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O registers (002016-
005F16). The actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on some more
extensive devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are separate
addressing schemes and optimized opcodes for register file and I/O
register access, all can still be addressed and manipulated as if they were
in SRAM. [edit] EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program Execution Atmel's
AVRs have a single level pipeline design. The next machine instruction is
fetched as the current one is executing. Most instructions take just one or
two clock cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were designed for the
efficient execution of compiled C code. The AVR instruction set is more
orthogonal than most eight-bit microcontrollers, however, it is not
completely regular: Pointer registers X, Y, and Z have addressing
capabilities that are different from each other. Register locations R0 to
R15 have different addressing capabilities than register locations R16 to
R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports
32 to 63. CLR affects flags, while SER does not, even though they are
complementary instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native instructions.
Instead CLR is syntactic sugar for [produces the same machine code as]
EOR R,R while SER is syntactic sugar for LDI R,$FF. Math operations
such as EOR modify flags while moves/loads/stores/branches such as
LDI do not.) [edit] Speed The AVR line can normally support clock speeds
from 0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs feature an on-
chip oscillator, removing the need for external clocks or resonator
circuitry. Because many operations on the AVR are single cycle, the AVR
can achieve up to 1MIPS per MHz. [edit] Development AVRs have a large
following due to the free and inexpensive development tools available,
including reasonably priced development boards and free development
software. The AVRs are marketed under various names that share the
same basic core but with different peripheral and memory combinations.
Some models (notably, the ATmega range) have additional instructions to
make arithmetic faster. Compatibility amongst chips is fairly good. See
external links for sites relating to AVR development. [edit] Features
Current AVRs offer a wide range of features: RISC Core Running Many
Single Cycle Instructions Multifunction, Bi-directional I/O Ports with
Internal, Configurable Pull-up Resistors Multiple Internal Oscillators
Internal, Self-Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage methods
Optional Boot Code Section with Independent Lock Bits for Protection
Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit
Timers PWM Channels & dead time generator Lighting (PWM Specific)
Controller models Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used
with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed hardware
& Hub controller with embedded AVR. Also freely available low-speed
(HID) software emulation Ethernet Controller Support Universal Serial
Interface (USI) for Two or Three-Wire Synchronous Data Transfer Analog
Comparators LCD Controller Support 10-Bit A/D Converters, with
multiplex of up to 16 channels Brownout Detection Watchdog Timer
(WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR assembler
programming language Atmel AVR machine programming language

http://avr-asm.tripod.com/therm232.html (2 of 2)1/20/2009 9:08:49 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

INFARED REMOTE DECODER (AVR 410)

HOME
RETRO_DAN
;
ASM FORUM ***************************************************************************
ASM MATH ;* A P P L I C A T I O N N O T E F O R T H E A
V R F A M I L Y
TUTORIAL #1
;*
TUTORIAL #2 ;* Number : AVR410
TUTORIAL #3 ;* File Name :"rc5.asm"
;* Title :RC5 IR Remote Control Decoder
MATH 200 ;* Date :97.08.15
MATH 200b ;* Version :1.0
;* Target MCU :AT90S1200
MATH 201 ;*
MATH 202 ;* DESCRIPTION
;* This Application note describes how to decode the
MATH 32X
frequently used
MATH YX ;* RC5 IR remote control protocol.
;*
DIV16 XX
;* The timing is adapted for 4 MHz crystal
DIV 24 24 ;*
DIV 3216 ;
***************************************************************************
FLOAT 128 .include "1200def.inc"
SQRT16 .device AT90S1200

MATH 202
MATH 202 .equ INPUT =2 ;PD2
.equ SYS_ADDR =0 ;The system address
DEC ASCII
INT ASCII
.def S =R0
HX2ASC
.def inttemp =R1
AVG8 222 .def ref1 =R2
FFT7 .def ref2 =R3

COPY 102 .def temp =R16

LPM 108
.def timerL =R17
EPROM 100 .def timerH =R16
SER EPROM
.def system =R19
DFLASH AT45
.def command =R20
FLASH CARD
.def bitcnt =R21
VFX SMIL
VFX MEM
SORT 220 .cseg
.org 0
CRC 236 rjmp reset
XMODEM REC
;
UART 304 ********************************************************************
UART 305 ;* "TIM0_OVF" - Timer/counter overflow interrupt handler
;*
UART 128
;* The overflow interrupt increments the "timerL" and
UART BUFF "timerH"
USB 232 ;* every 64us and 16,384us.
;*
AVR ISP ;* Number of words: 7
ISP 2313 ;* Number of cycles: 6 + reti
;* Low registers used: 1
ISP 1200 ;* High registers used: 3
AVR SPI ;* Pointers used: 0
;
I2C 300 ********************************************************************
I2C 302 .org OVF0addr
TIM0_OVF: in S,sreg
I2C TWI26
inc timerL ;Updated every 64us
I2C/TWI 128 inc inttemp
I2C/TWI AT8 brne TIM0_OVF_exit

DALLAS-1W inc timerH

DALLAS CRC
TIM0_OVF_exit: out sreg,S
ETHNET 8019 reti
TEA
ADC 128
ADC 10B
;
ADC 400
********************************************************************
ADC 401 ;* Example program
THERM 232 ;*
;* Initializes timer, ports and interrupts.
IRD 410 ;*
LCD HD44 ;* Calls "detect" in an endless loop and puts the
result out on
LCD 2313 ;* port B.
LCD44 2313 ;*
;* Number of words: 16
KBD 240 ;* Low registers used: 0
MUX 242 ;* High registers used: 3
;* Pointers used: 0
KBD PS2
;
KBD PC/128 ********************************************************************
PS2 EMU
reset: ;ldi temp,low(RAMEND) ;
BOOT MG8 Initialize stackpointer
BOOT DR8 ;out SPL,temp
;ldi temp,high(RAMEND) ; Commented
ALM CLK out since 1200 does not hae SRAM
CLOCK 8564 ;out SPH,temp
90 DAYS
ldi temp,1 ;Timer/Counter 0
DELAYS clocked at CK
out TCCR0,temp
CALL ID
DTMF 314 ldi temp,1< 3/4 bit time
PWM 6CH brge fault ; exit

PWM 10K sbic PIND,INPUT ;Wait for falling

ENCODE edge start bit 2
rjmp start3
STH-11
ATMEL CORP clr timerL
ldi bitcnt,12 ;Receive 12 bits
AVR
clr command
BUTTERFLY clr system
AVR BOOK

sample: cp timerL,ref1 ;Sample

INPUT at 1/4 bit time
brlo sample

sbic PIND,INPUT
rjmp bit_is_a_1 ;Jump if line high

bit_is_a_0: clc ;Store a '0'

rol command
rol system

;Synchronize timing
bit_is_a_0a: cp timerL,ref2 ;If no edge
within 3/4 bit time
brge fault ; exit
sbis PIND,INPUT ;Wait for rising
edge
rjmp bit_is_a_0a ;in the middle of
the bit

clr timerL
rjmp nextbit

bit_is_a_1: sec ;Store a '1'

rol command
rol system
;Synchronize timing
bit_is_a_1a: cp timerL,ref2 ;If no edge
within 3/4 bit time
brge fault ; exit
sbic PIND,INPUT ;Wait for falling
edge
rjmp bit_is_a_1a ;in the middle of
the bit

clr timerL

nextbit: dec bitcnt ;If bitcnt > 0

brne sample ; get next bit

;All bits sucessfully received!

mov temp,command ;Place system bits
in "system"
rol temp
rol system
rol temp
rol system

bst system,5 ;Move toggle bit

bld command,6 ;to "command"

;Clear remaining
bits
andi command,0b01111111
andi system,0x1F

ret

fault: ser command ;Both

"command" and "system"
ser system ;0xFF indicates
failure
ret

Programming the AVR Microcontrollers in Machine Language

AVR
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected

from Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing,
intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still
be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language
http://avr-asm.tripod.com/ird410.html (1 of 2)1/20/2009 9:09:24 PM
16 BIT MATH (AVR 202)

http://avr-asm.tripod.com/ird410.html (2 of 2)1/20/2009 9:09:24 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

LCD DRIVER FOR HD44xx

HOME
RETRO_DAN
;
ASM FORUM ***************************************************************************
ASM MATH ;
; File Name :'lcd4.asm"
TUTORIAL #1
; Title :HD44xx kompatibilis LCD
TUTORIAL #2 Driver (I/O Port)
TUTORIAL #3 ; Date :2003.10.28.
; Version :1.0.0
MATH 200 ; Support telephone :+36-70-333-4034, old: +36-30-9541-
MATH 200b 658 VFX
; Support fax :
MATH 201 ; Support Email :info@vfx.hu
MATH 202 ; Target MCU :ATmega128
;
MATH 32X
;
MATH YX ***************************************************************************
; D E S C R I P T I O N
DIV16 XX
;
DIV 24 24 ; http://home.iae.nl/users/pouweha/lcd/lcd.shtml
DIV 3216 ;
; Support 2x16 char LCD
FLOAT 128 ;
SQRT16 ;
***************************************************************************
MATH 202 ; M O D I F I C A T I O N H I S T O R Y
MATH 202 ;
;
DEC ASCII
; rev. date who why
INT ASCII ; ---- ---------- ---
------------------------------------
HX2ASC
; 0.01 2003.10.28 VFX Creation
AVG8 222 ;
FFT7 ;
***************************************************************************
COPY 102 ;Hardware
LPM 108 ;
***************************************************************************
EPROM 100 ;*
SER EPROM ;* SYSCLK: f=16.000 MHz (T= 62.5 ns)
;*
DFLASH AT45
;
FLASH CARD ***************************************************************************
;
VFX SMIL
;
VFX MEM ;
SORT 220 **************************************************************************
;* Hardware Def.
CRC 236 ;
XMODEM REC ;
***************************************************************************
UART 304
UART 305
.equ LCDRS_PORT=PORTD ;LCD Register Select
UART 128
.equ LCDRS_DIR=DDRD ;Register Select
UART BUFF 1=data 0=command
USB 232 .equ LCDRS=0

AVR ISP .equ LCDRW_PORT=PORTD ;LCD Read/Write

ISP 2313 .equ LCDRW_DIR=DDRD ;0=write to
display, 1= read from display
ISP 1200 .equ LCDRW=1
AVR SPI
.equ LCDEN_PORT=PORTD ;LCD Enable
I2C 300 .equ LCDEN_DIR=DDRD ;Enable - data
I2C 302 clocked on falling edge
.equ LCDEN=4
I2C TWI26
I2C/TWI 128 .equ LCDDAT_PORT=PORTF ;LCD Data PortF
I2C/TWI AT8 [3..0]
.equ LCDDAT_DIR=DDRF
DALLAS-1W .equ LCDDAT_PIN=PINF
DALLAS CRC .equ LCDDAT_Mask=0b00001111

ETHNET 8019
TEA
ADC 128 ;
ADC 10B ***************************************************************************
;**** VARIABLES
ADC 400
.DSEG
ADC 401
THERM 232
IRD 410 ;
LCD HD44 ***************************************************************************
.ESEG
LCD 2313
LCD44 2313
;
KBD 240 ***************************************************************************
MUX 242 ;**** CODE SEG
;
KBD PS2
***************************************************************************
KBD PC/128 .CSEG
PS2 EMU
BOOT MG8 ;*****************************************************
BOOT DR8 ;** Wait1ms
;**
ALM CLK ;** In: R16 - 16*1ms varakozas
CLOCK 8564 ;**
;** Out: -
90 DAYS
;**
DELAYS ;**
;** Alt R16
CALL ID
;**
DTMF 314 ;** Description: wating for R16 * 1 ms
PWM 6CH ;*
Wait1ms:
PWM 10K ldi XL,low(SYSCLK/(5*1000))
ENCODE ldi XH,high(SYSCLK/(5*1000))
Waitx1: sbiw XL,1 ;[2] \
STH-11 nop ;[1] - 5 cycles in
ATMEL CORP loop
brne Waitx1 ;[2] /
AVR
dec R16
BUTTERFLY brne Wait1ms
AVR BOOK ret

;*****************************************************
;** LCD_pulseE
;**
;** In: -
;**
;** Out: R0 - Data on LCDDat pin
;**
;**
;** Alt
;**
;** Description: Generate ENABLE signal to LCD
;*
LCD_pulseE:
sbi LCDEN_PORT,LCDEN ;Enable high
nop ;Wait 500ns
@16MHz
nop
nop
nop
nop
nop
nop
nop
in R0,LCDDAT_PIN
cbi LCDEN_PORT,LCDEN ;Enable
low, latch data
ret

;*****************************************************
;** LCD_Init
;**
;** In: -
;**
;** Out: -
;**
;**
;** Alt:
;**
;** Description: Initialize LCD in 4 bit mode
;*
LCD_Init:
sbi LCDEN_DIR,LCDEN ;LCD I/O
Disabled
cbi LCDEN_PORT,LCDEN

sbi LCDRS_DIR,LCDRS ;Sel. LCD

Command Register
cbi LCDRS_PORT,LCDRS

sbi LCDRW_DIR,LCDRW ;LCD Write

mode
cbi LCDRW_PORT,LCDRW

ldi R16,LCDDAT_Mask ;LCD Data

lines outputs
sts LCDDAT_DIR,R16
ldi R16,0 ;All zeros
sts LCDDAT_PORT,R16

ldi R16,15 ;Wait at

least 15msec after
rcall Wait1ms ;powerup
before writing to display
;tuti ami
tuti legyen 250ms

; Put the LCD in 8-bit mode. Even though

we want the display to
; operate in 4-bit mode, the only way to
guarantee that our commands
; are aligned properly is to initialize in
8-bit. (The user might have
; hit reset between nibbles of a dual 4-bit
cycle.)

lds R16,LCDDAT_PORT
andi R16,255-LCDDAT_PORT
ori R16,0b00000011 ;3x
probalkozunk 8 bit mode-ba rakni
sts LCDDAT_PORT,R16
nop
nop
cbi LCDRS_PORT,LCDRS ;Set to
Command Reg.
cbi LCDRW_PORT,LCDRW ;read
rcall LCD_pulseE ;1
ldi R16,15
rcall Wait1ms ;wait 5ms

cbi LCDRS_PORT,LCDRS ;Set to

Command Reg.
cbi LCDRW_PORT,LCDRW ;read
rcall LCD_pulseE ;2
ldi R16,5
rcall Wait1ms ;wait 5ms

cbi LCDRS_PORT,LCDRS ;Set to

Command Reg.
cbi LCDRW_PORT,LCDRW ;read
rcall LCD_pulseE ;3
ldi R16,5
rcall Wait1ms ;wait 5ms

; Now it's safe to go into 4-bit mode.

lds R16,LCDDAT_PORT
andi R16,255-LCDDAT_PORT
ori R16,0b00000010 ;4bit bus
mode
sts LCDDAT_PORT,R16
rcall LCD_pulseE
ldi R16,5
rcall Wait1ms ;wait 5ms

; *** Send the 'FUNCTION SET' command

; +------ Data: 0 = 4-bit;
1 = 8-bit
; |+----- Lines: 0 = 1; 1 = 2
; ||+---- Font: 0 = 5x8; 1
= 5x11
ldi R16,0b00101000
rcall LCD_SendCmd

; *** Send the 'CURSOR/DISPLAY SHIFT'

command
; +----- S/C: 0 = cursor;
1 = display
; |+---- R/L: 0 = left; 1
= right
ldi R16,0b00010100
rcall LCD_SendCmd

; *** Send the 'ENTRY MODE' command

; +--- Direction: 0 =
left; 1 = right
; |+-- Shift Dislay: 0 =
off; 1 = on
ldi R16,0b00000110
rcall LCD_SendCmd

; *** Send the 'DISPLAY ON/OFF' command

; +---- Display: 0 = off;
1 = on
; |+--- Cursor: 0 = off; 1
= on
; ||+-- Blink: 0 = off; 1
= on
ldi R16,0b00001100
rcall LCD_SendCmd

rcall LCD_Clear
ret

;*****************************************************
;** LCD_Clear
;**
;** In: -
;**
;** Out: -
;**
;**
;** Alt:
;**
;** Description:
;** Clears the display and sends the cursor home.
;
LCD_Clear:
ldi R16,0b00000001 ;Clear LCD
rcall LCD_SendCmd
ldi R16,0b00000010 ;Send the
cursor home
rcall LCD_SendCmd
ret

;*****************************************************
;** LCD_WaitBusy
;**
;** In: -
;**
;** Out: -
;**
;**
;** Alt: R0, R16
;**
;** Description:
;** Waits for the busy flag to go low. Since we're in
4-bit mode,
;** the register has to be read twice (for a total of 8
bits).
;*
LCD_WaitBusy:
push R16

lds R16,LCDDAT_DIR
andi R16,255-LCDDAT_Mask ;LCD data
bits going to input
sts LCDDAT_DIR,R16

lds R16,LCDDAT_PORT
ori R16,LCDDAT_Mask ;pull-up
sts LCDDAT_PORT,R16
rjmp LCDWait1

LCDWait0:
ldi R16,2 ;Wait min.
~1us
LCDWait01: nop
dec R16
brne LCDWait01
LCDWait1:
cbi LCDRS_PORT,LCDRS ;Set to
Command Reg.
sbi LCDRW_PORT,LCDRW ;read
rcall LCD_pulseE ;Busy Flag
read bit 7.
mov R16,R0
rcall LCD_pulseE ;lower
nibble must read
sbrc R16,3 ;Check busy
flag
rjmp LCDWait0

lds R16,LCDDAT_DIR ;LCD Data

lines outputs
ori R16,LCDDAT_Mask
sts LCDDAT_DIR,R16
lds R16,LCDDAT_PORT
andi R16,255-LCDDAT_Mask ;All zero
sts LCDDAT_PORT,R16
pop R16
ret

;*****************************************************
;** LCD_SendCmd
;**
;** In: R16 - Command byte
;**
;** Out: -
;**
;**
;** Alt: R0, R1, R16, R17
;**
;** Description:
;** Routine to write a command to the instruction
register.
;
LCD_SendCmd:
rcall LCD_WaitBusy
mov R1,R16
swap R16
andi R16,LCDDAT_Mask ;send upper
nibble first
lds R17,LCDDAT_PORT
andi R17,255-LCDDAT_Mask
or R17,R16
sts LCDDAT_PORT,R17
cbi LCDRS_PORT,LCDRS ;Set to
Command Reg.
cbi LCDRW_PORT,LCDRW ;Write
rcall LCD_PulseE ;Latch
upper nibble

mov R16,R1
andi R16,LCDDAT_Mask ;send lower
nibble
lds R17,LCDDAT_PORT
andi R17,255-LCDDAT_Mask
or R17,R16
sts LCDDAT_PORT,R17
cbi LCDRS_PORT,LCDRS ;Set to
Command Reg.
cbi LCDRW_PORT,LCDRW ;Write
rcall LCD_PulseE ;Latch
lower nibble
ret

;*****************************************************
;** LCD_SendChar
;**
;** In: R16 - character code
;**
;** Out: -
;**
;**
;** Alt: R0,R1, R16, R17
;**
;** Description:
;** Routine to write a character to the data register.
;
LCD_SendChar:
rcall LCD_WaitBusy
mov R1,R16
swap R16
andi R16,LCDDAT_Mask ;send upper
nibble first
lds R17,LCDDAT_PORT
andi R17,255-LCDDAT_Mask
or R17,R16
sts LCDDAT_PORT,R17
sbi LCDRS_PORT,LCDRS ;Set to
data Reg.
cbi LCDRW_PORT,LCDRW ;Write
rcall LCD_PulseE ;Latch
upper nibble
mov R16,R1
andi R16,LCDDAT_Mask ;send lower
nibble
lds R17,LCDDAT_PORT
andi R17,255-LCDDAT_Mask
or R17,R16
sts LCDDAT_PORT,R17
sbi LCDRS_PORT,LCDRS ;Set to
Data Reg.
cbi LCDRW_PORT,LCDRW ;Write
rcall LCD_PulseE ;Latch
lower nibble
ret

;*****************************************************
;** LCD_Goto
;**
;** In: R16 - position
;** 0x00 - 1.row, 1.col
;** 0x40 - 1.row, 2.col
;**
;** Out: -
;**
;**
;** Alt: R0, R1, R16, R17
;**
;** Description:
;**
;
LCD_Goto:
ori R16,0b10000000 ;Set
address Command
rcall LCD_SendCmd
ret

;*****************************************************
;** LCD_PrnFLASHStr
;**
;** In: Z+RAMP - start address of string
;**
;** Out: -
;**
;**
;** Alt: R0, R1, R16, R17
;**
;** Description:
;** Print a null terminated string to LCD
;
LCD_PrnFLASHStr:
elpm R16,Z+
tst R16
breq LCD_PrnFLSH0
rcall LCD_SendChar
rjmp LCD_PrnFLASHStr
LCD_PrnFLSH0:
ret

Programming the AVR Microcontrollers in Machine Language

AVR
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© WebRing Inc. Search

Atmel AVR From Wikipedia, the free encyclopedia (Redirected

from Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing,
intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still
be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
http://avr-asm.tripod.com/lcdhd44.html (1 of 2)1/20/2009 9:10:19 PM
16 BIT MATH (AVR 202)

Synchronous/Asynchronous Serial Peripherals (UART/

USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language

http://avr-asm.tripod.com/lcdhd44.html (2 of 2)1/20/2009 9:10:19 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

LCD DRIVER FOR HD44780 AND 2313

HOME
RETRO_DAN
;
ASM FORUM ***************************************************************
ASM MATH ;Programm LCD.ASM
;Das Programm demonstriert, wie man eine LCD-Anzeige
TUTORIAL #1
mit
TUTORIAL #2 ;16 Zeichen x 2 Zeilen an einen AT90S2313 anschliesst.
TUTORIAL #3 ;Es wird vorausgesetzt, dass die Anzeige einen HD44780
oder
MATH 200 ;kompatiblen Controller verwendet.
MATH 200b ;AT90S2313 mit 4 MHz Takt
;
MATH 201 ***************************************************************
MATH 202
.device AT90S2313
MATH 32X
.include "2313def.inc" ;muss im selben
MATH YX ;Verzeichnis stehen
DIV16 XX
DIV 24 24 ;Definition der Steuerleitungen
DIV 3216 .equ E = PD0 ;E an Pin PD0
.equ RW = PD1 ;RW an Pin PD1
FLOAT 128 .equ RS = PD2 ;RS an Pin PD2
SQRT16 ;.equ LCD_cntr = PORTD ;PORTD ist Kontroll-Port
;.equ LCD_data = PORTB ;PORTB ist Daten-Port
MATH 202 .equ BF = PB7 ;Busy flag
MATH 202
DEC ASCII
;LCD Befehle
INT ASCII .equ clear_LCD = 0b00000001 ;loesche Anzeige
.equ home_LCD = 0b00000010 ;return home
HX2ASC
.equ set_LCD = 0b00111000 ;8 bits,2 Zeilen,5x7dots
AVG8 222 .equ LCD_on = 0b00001110 ;schalte LCD ein
FFT7 .equ entry_mode = 0b00000110 ;setze Cursor

COPY 102
LPM 108 ;Variablendefinition
EPROM 100 .def zeichen = r0 ;Zeichen aus der Tabelle
SER EPROM .def buffer = r16 ;RX/TX Daten von/zu LCD
.def counter = r17 ;Zaehler fuer den Text
DFLASH AT45
.def temp = r18
FLASH CARD
VFX SMIL
.CSEG
VFX MEM .ORG 0x00 ; Programm beginnt bei 0
SORT 220 rjmp main ; Starte Hauptprogramm

CRC 236 ;
XMODEM REC **************************************************************
; Subroutine init
UART 304 ; Initialisiere PORTD
UART 305 ;
**************************************************************
UART 128
UART BUFF init: ldi temp,0b11111111 ;PORTD ist Ausgang
USB 232 out DDRD,temp
cbi PORTD,E ;E initialisieren
AVR ISP cbi PORTD,RS
ISP 2313 cbi PORTD,RW
ret
ISP 1200
AVR SPI
I2C 300 ;
I2C 302 ***************************************************************
; Subroutine busy_flag
I2C TWI26
; Diese Routine testet, ob die LCD-Anzeige bereit ist,
I2C/TWI 128 einen
I2C/TWI AT8 ; neuen Befehl oder weitere Daten zu empfangen.
;
DALLAS-1W ***************************************************************
DALLAS CRC
busy_flag: ldi temp,0b00000000 ;PORTB ist Eingang
ETHNET 8019 out DDRB,temp
TEA cbi PORTD,RS ;Befehl wird gesendet
sbi PORTD,RW ;setze LCD in Lesemodus
ADC 128 sbi PORTD,E ;spreche LCD an
ADC 10B nop
nop
ADC 400
sbic PINB,BF ;LCD bereit?
ADC 401 rjmp busy_flag ;nein, wiederhole
THERM 232 cbi PORTD,E ;disable LCD
ret ;LCD bereit
IRD 410
LCD HD44
;
LCD 2313 ***************************************************************
LCD44 2313 ; Subroutine write_data
; Diese Routine sendet Daten zur LCD-Anzeige.
KBD 240 ; Die Daten muessen im Register buffer uebergeben
MUX 242 werden.
;
KBD PS2
***************************************************************
KBD PC/128
PS2 EMU write_data: rcall busy_flag ;LCD bereit?
ldi temp,0b11111111 ;PORTB ist Ausgang
BOOT MG8 out DDRB,temp
BOOT DR8 sbi PORTD,RS ;Daten werden gesendet
cbi PORTD,RW ;LCD in Schreibmodus
ALM CLK sbi PORTD,E ;spreche LCD an
CLOCK 8564 out PORTB,buffer ;sende Daten
cbi PORTD,E ;disable LCD
90 DAYS
ret
DELAYS
CALL ID
;
DTMF 314 ***************************************************************
PWM 6CH ; Subroutine write_instr
; Diese Routine sendet Befehle zur LCD-Anzeige.
PWM 10K ; Der Befehl muss im Register buffer uebergeben werden.
ENCODE ;
***************************************************************
STH-11
ATMEL CORP write_instr: rcall busy_flag ;LCD bereit?
ldi temp,0b11111111 ;RB ist Ausgang
AVR
out DDRB,temp
BUTTERFLY cbi PORTD,RS ;Befehl wird gesendet
AVR BOOK cbi PORTD,RW ;LCD in Schreibmodus
sbi PORTD,E ;spreche LCD an
out PORTB,buffer ;sende Befehl
cbi PORTD,E ;disable LCD
ret

;
***************************************************************
; Hauptprogramm
; Schreibt "AT90S2313" in die erste Zeile und "LCD-
Routine"
; in die zweite Zeile des LCDs.
;
***************************************************************

main: ldi temp,RAMEND ; setze Stack-Pointer

out SPL,temp ; an das SRAM-Ende

rcall init ; PORTD initialisieren

ldi buffer,set_LCD ;setze LCD Funktion

rcall write_instr

ldi buffer,LCD_on ;schalte LCD ein

rcall write_instr

ldi buffer,clear_LCD ;loesche Anzeige

rcall write_instr

ldi buffer,entry_mode ;Eingabemodus

rcall write_instr

;Holt den Text 'AT90S2313' aus der Tabelle und schreibt

diesen in
;die erste Zeile der Anzeige

ldi counter,9 ;Zeichenzaehler

ldi ZL,LOW(Tabelle1*2) ;Low-Zeiger auf Tabellenanfang
ldi ZH,HIGH(Tabelle1*2) ;High-Zeiger auf Tabellenanfang
loop_msg1: lpm ;hole Zeichen aus Tabelle
mov buffer,zeichen ;Zeichen uebergeben
rcall write_data ;schreibe Zeichen in LCD
adiw ZL+1 ;16-Bit Zeiger erhoehen
dec counter ;alle Zeichen gesendet?
brne loop_msg1 ;Nein! Sende naechstes Zeichen

;Holt den Text 'LCD-Routine' aus der Tabelle und

schreibt diesen
;in die zweite Zeile der Anzeige

ldi buffer,0b11000000 ;LCD-Startadresse 2.Zeile

rcall write_instr ;sende Befehl
ldi counter,11 ;Zeichenzaehler
ldi ZL,LOW(Tabelle2*2) ;Low-Zeiger auf Tabellenanfang
ldi ZH,HIGH(Tabelle2*2) ;High-Zeiger auf Tabellenanfang
loop_msg2: lpm ;hole Zeichen aus Tabelle
mov buffer,zeichen ;Zeichen uebergeben
rcall write_data ;schreibe Zeichen in LCD
adiw ZL+1 ;16-Bit Zeiger erhoehen
no_carry2: dec counter ;alle Zeichen gesendet?
brne loop_msg2 ;Nein! Sende naechstes Zeichen

;Endlosschleife. AVR zuruecksetzen, um Programm erneut

zu starten

loop: rjmp loop

;Tabelle 1 mit dem Text "AT90S2313", der in die 1.Zeile

geschrieben
;werden soll

Tabelle1: .DB "AT90S2313"

;Tabelle 2 mit dem Text "LCD-Routine", der in die 2.

Zeile geschrieben
;werden soll

Tabelle2: .DB "LCD-Routine"

Programming the AVR Microcontrollers in Machine Language

AVR
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected

from Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing,
intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still
be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language
http://avr-asm.tripod.com/lcd2313.html (1 of 2)1/20/2009 9:10:53 PM
16 BIT MATH (AVR 202)

http://avr-asm.tripod.com/lcd2313.html (2 of 2)1/20/2009 9:10:53 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

LCD DRIVER II FOR HD44780 AND 2313

HOME
RETRO_DAN
The attached code shows how to connect, initialise and drive a
ASM FORUM 44780-based LCD in 4-bit mode.
ASM MATH
The 2 additional pins are probably reserved for a backlight
TUTORIAL #1
option - they were on my display from Dontronics.
TUTORIAL #2
TUTORIAL #3 ;-----------------------------------------------------------------
;
MATH 200 ; Name: LCDMain.asm
MATH 200b ; Title: Main routine for driving Hitach LCD display
; Version: 1.0
MATH 201 ; Last updated: 2001.06.04
MATH 202 ; Target: AT90S2313
;
MATH 32X
;-----------------------------------------------------------------
MATH YX ;
; DESCRIPTION
DIV16 XX
;
DIV 24 24 ; Driver for Hitachi HD44780-based LCD display
DIV 3216 ;
; Display is wired to Port B. Each individual pin on the display
FLOAT 128 ; is wired as follows:
SQRT16 ;
; Pin 1 - Vss GND Supply ground
MATH 202 ; Pin 2 - Vdd VTG Supply +ve
MATH 202 ; Pin 3 - Vee GND Contrast adjust = maximum
; Pin 4 - RS PB4 Command/data
DEC ASCII
; Pin 5 - R/W PB5 Read/write
INT ASCII ; Pin 6 - EN PB6 Enable
; Pin 7 - DB0 GND Data bit 0 = 0
HX2ASC
; Pin 8 - DB1 GND Data bit 1 = 0
AVG8 222 ; Pin 9 - DB2 GND Data bit 2 = 0
FFT7 ; Pin 10- DB3 VTG Data bit 3 = 1 to indicate 2-line display at
startup
COPY 102 ; Pin 11- DB4 PB0 Data bit 4 = PortB:0
LPM 108 ; Pin 12- DB5 PB1 Data bit 5 = PortB:1
; Pin 13- DB6 PB2 Data bit 6 = PortB:2
EPROM 100 ; Pin 14- DB7 PB3 Data bit 7 = PortB:3
SER EPROM ; Pin 15- (if present) No connection
; Pin 16- (if present) No connection
DFLASH AT45
;
FLASH CARD ;-----------------------------------------------------------------
VFX SMIL
.nolist
VFX MEM .include "2313def.inc"
SORT 220 .list

CRC 236 ;-----------------------------------------------------------------

XMODEM REC ;
; General purpose registers
UART 304
UART 305 .def rRETURN =r0 ; return value from functions
UART 128
.def rZERO =r1
UART BUFF
USB 232 .def rSCRATCH =r7
.def rSCRATCH2 =r8
AVR ISP .def rSCRATCH3 =r9
ISP 2313 .def rSCRATCH4 =r10

ISP 1200 .def rISCRATCH =r11 ; for use in interrupt routines

AVR SPI .def rISCRATCH2 =r12 ; ditto
.def rISCRATCH3 =r13 ; ditto
I2C 300 .def rISCRATCH4 =r14 ; ditto
I2C 302
.def rISREGSAVE =r15 ; sreg saved here in interrupts
I2C TWI26
I2C/TWI 128 .def rTEMP =r16
I2C/TWI AT8 .def rTEMP2 =r17

DALLAS-1W .def rITICK =r18 ; Decreasing tick, used for delays

DALLAS CRC .def rITEMP =r19

ETHNET 8019 .def rPARAM1 =r20

TEA .def rPARAM2 =r21
ADC 128 .def rLOOPI =r22 ; loop counters
ADC 10B .def rLOOPJ =r23
ADC 400
;-----------------------------------------------------------------
ADC 401 ;
THERM 232 ; Equates

IRD 410 ;-----------------------------------------------------------------

LCD HD44 ;
; IO Port Bits
LCD 2313
LCD44 2313 .equ mDATA =0x0F
.equ bRS =4
KBD 240 .equ bRW =5
MUX 242 .equ bEN =6
KBD PS2
;-----------------------------------------------------------------
KBD PC/128 ;
PS2 EMU ; Timings
;
BOOT MG8 ; We need a multiple of 100Hz for the clock tick, so for 4MHz
BOOT DR8 ; this equates to 40,000 clock cycles, and for a 3.6864MHz clock,
; this is 36,864 cycles. Given the prescaler values available
ALM CLK ; on counter/timer 0, we get the following:
CLOCK 8564 ;
; Divider Counts 4MHz Counts 3.7MHz In range?
90 DAYS
; Clk/8 5000 4608 No (greater than 255)
DELAYS ; Clk/64 625 576 No (greater than 255)
; Clk/64 125 for 500Hz 144 for 400Hz Yes
CALL ID
;
DTMF 314 ; The actual values loaded into the registers are these values
PWM 6CH ; subtracted from 256, since we are counting up, and the clock
; interrupt happens when the clock register overflows to 256.
PWM 10K
ENCODE .equ TIMERSCALE =$03 ; Clk/64
STH-11 ; Timer value for 3.6864 MHz clock
ATMEL CORP .equ TIMERVALUE = (256-144)
.equ TICKVALUE = 4 ; 4 x 400Hz ticks = 100Hz clock
AVR
BUTTERFLY ; Timer value for 4 MHz clock
AVR BOOK ; .equ TIMERVALUE = (256-125)
; .equ TICKVALUE = 5 ; 5 x 500Hz ticks = 100Hz clock

;-----------------------------------------------------------------
;
; Variables

.dseg

tickcount: .byte 1 ; clock count to 4 or 5 for centiseconds

centi: .byte 1 ; centisecond count
second: .byte 1 ; second count
minute: .byte 1 ; minute
hour: .byte 1 ; hour
day: .byte 1 ; day

;-----------------------------------------------------------------
;
; Interrupt service vectors

.cseg
.org 0
rjmp Reset ; Reset vector

.org OVF0addr
rjmp Timer0 ; Timer tick

;-----------------------------------------------------------------
;
; Start of actual code.
;

;-----------------------------------------------------------------
;
; Timer 0 overflow - decreases tick count in tickcount until it
; reaches 0, then ripples the count along to the next biggest
; counter, all the way up to the "days" count.

Timer0: in rISREGSAVE,SREG ; store status register

ldi rITEMP,TIMERVALUE ; reset counter

out TCNT0,rITEMP ; to start counting again

mov rISCRATCH,YL ; store Y register

mov rISCRATCH2,YH ; since we will be using it

dec rITICK ; decrease register tick count

ldi YL,low(tickcount) ; Y points to tick count

clr YH

ld rITEMP,Y ; get tick count

inc rITEMP ; increment it
cpi rITEMP,TICKVALUE ; is it the target value yet?
brne Timer0_Done ; no... exit immediately

clr rITEMP ; yes - clear it and store it again

st Y+,rITEMP ; increment Y to point to centiseconds

;
; We get through to here once every 4 or 5 timer ticks, in
; other words, 100 times every second.
;

ld rITEMP,Y ; load centiseconds

inc rITEMP ; increment
cpi rITEMP,100 ; and check for overflow
brne Timer0_Done ; no... exit immediately

clr rITEMP ; else reset to 0

st Y+,rITEMP ; store, and increment Y to point to seconds

ld rITEMP,Y ; load seconds

inc rITEMP ; increment
cpi rITEMP,60 ; check for overflow
brne Timer0_Done ; no... exit immediately

clr rITEMP ; else reset to 0

st Y+,rITEMP ; store, and increment Y to point to minutes

ld rITEMP,Y ; load minutes

inc rITEMP ; increment
cpi rITEMP,60 ; check for overflow
brne Timer0_Done ; no... exit immediately

clr rITEMP ; else reset to 0

st Y+,rITEMP ; store, and increment Y to point to hours

ld rITEMP,Y ; load hours

inc rITEMP ; increment
cpi rITEMP,24 ; check for overflow
brne Timer0_Done ; no... exit immediately

clr rITEMP ; else reset to 0

st Y+,rITEMP ; store, and increment Y to point to days

ld rITEMP,Y ; load days

inc rITEMP ; and increment

;
; However we get here, the most recently incremented value is in
rITEMP,
; and Y points to where we got it from.
;

Timer0_Done:
st Y,rITEMP ; store valid value back again

mov YL,rISCRATCH ; restore saved Y pointer

mov YH,rISCRATCH2
out SREG,rISREGSAVE ; restore status register
reti ; and return from interrupt, done.

;-----------------------------------------------------------------
;
; WaitTick
; Waits for between rPARAM1 and rPARAM1+1 timer ticks, depending
; on exactly when the next tick is about to happen. Each tick
takes
; 20ms on a 4MHz clock, or 25ms on a 3.6864MHz clock. This is
enough
; to act as a timed delay for those commands which take more than
; the 40us "standard" delay.

WaitTick:
inc rPARAM1
mov rITICK,rPARAM1
WaitTick_Loop:
and rITICK,rITICK
brne WaitTick_Loop
ret

;-----------------------------------------------------------------
;
; Reset vector - generic system.

Reset:
ldi rTEMP,RAMEND-1 ; Set stack to end of RAM
out SPL,rTEMP

; Get the timer going

ldi rTEMP,(1< out TIMSK,rTEMP

ldi rTEMP,TIMERVALUE ; timer value

out TCNT0,rTEMP

ldi rTEMP,TIMERSCALE ; clock prescaler for Timer 0

out TCCR0,rTEMP

;
; And allow timer interrupts
;

sei

; Set port B to all output, all 0.

ldi rTEMP,$00
out PORTB,rTEMP

ldi rTEMP,$FF
out DDRB,rTEMP

;
; Now initialize the display
;

rcall InitDisplay

;
; And reset the displayed time to 00 00:00:00.00
;

clr rTEMP
sts tickcount,rTEMP
sts centi,rTEMP
sts second,rTEMP
sts minute,rTEMP
sts hour,rTEMP
sts day, rTEMP

ldi rPARAM1,0x00
rcall LCDGoto ; go to display position 0

ldi ZL,low(String*2)
ldi ZH,high(String*2)
rcall LCDString ; and send string

Loop:
ldi rPARAM1,0x40
rcall LCDGoto ; go to display position 0x40 (2nd line)

lds rPARAM1,day ; get the day

rcall LCDNumber ; output as a 2-digit number

ldi rPARAM1,' ' ; followed by a space,

rcall WriteData

lds rPARAM1,hour ; then the hour

rcall LCDNumber ; as a 2 digit number

ldi rPARAM1,':' ; followed by a colon

rcall WriteData

lds rPARAM1,minute ; then the minute

rcall LCDNumber ; as a 2 digit number

ldi rPARAM1,':' ; followed by a colon

rcall WriteData

lds rPARAM1,second ; then the second

rcall LCDNumber ; as a 2 digit number

ldi rPARAM1,'.' ; followed by a decimal point

rcall WriteData

lds rPARAM1,centi ; and finally the 1/100ths of a second

rcall LCDNumber ; yes, as a 2 digit number.

lds rTEMP,centi ; get the centiseconds "then"

Wait: lds rTEMP2,centi ; get the centiseconds "now"
cp rTEMP,rTEMP2 ; same?
breq Wait ; yes... go round again and wait till it changes

rjmp Loop ; then display all over again, for ever

;-----------------------------------------------------------------
;
; InitDisplay
; Initialize display as shown in data sheet.

InitDisplay:

; Initial power-up delay

; Wait for 15ms or more (100-125ms in fact)

ldi rPARAM1,5
rcall WaitTick

; Send 8-bit mode command

ldi rTEMP2,0x03 ; 8 bit mode indicator

rcall Strobe ; and strobe it out

; Wait again

ldi rPARAM1,1 ; min 20ms delay (4ms + leeway)

rcall WaitTick ; until ready to receive

; Send 8-bit mode command again

ldi rTEMP2,0x03 ; 8 bit mode indicator

rcall Strobe ; and strobe it out

; Wait again

ldi rPARAM1,100 ; 100us

rcall WaitMicro ; until ready to receive

; Now 4-bit mode command to actually place us in 4-bit mode

; as originally required.

ldi rTEMP2,0x02 ; 4 bit mode indicator

rcall Strobe ; and strobe it out

; Wait

ldi rPARAM1,100 ; 100us

rcall WaitMicro ; until ready to receive

;
; We can now use the normal functions for writing data,
; which are designed to work with 4-bit mode data timings
;

; Function set

ldi rPARAM1,0x28 ; 4 bit, dual line

rcall WriteInstruction

; Display on

ldi rPARAM1,0x0E ; display on, cursor on, no blink.

rcall WriteInstruction

; Display clear

ldi rPARAM1,0x01
rcall WriteInstruction

ldi rPARAM1,1 ; min 20ms delay (4ms + leeway)

rcall WaitTick ; until ready to receive

; Entry mode set

ldi rPARAM1,0x06 ; Advance cursor, no shift

rcall WriteInstruction

ret

;-----------------------------------------------------------------
;
; LCDGoto
; Go to character position rPARAM1

LCDGoto:
ori rPARAM1,0x80
rjmp WriteInstruction

;-----------------------------------------------------------------
;
; LCDNumber
; Write number from 00 to 99 at current position

LCDNumber:
mov rPARAM2,rPARAM1
ldi rTEMP,'0'
LCD10s: subi rPARAM2,10
brmi LCD1s
inc rTEMP
rjmp LCD10s

LCD1s: mov rPARAM1,rTEMP

rcall WriteData
subi rPARAM2,-(0x3A)
mov rPARAM1,rPARAM2
rjmp WriteData

;-----------------------------------------------------------------
;
; LCDString
; Write string at Z from flash to LCD at current position

LCDString:
lpm
and r0,r0
breq LCDString_End
adiw ZL,1
mov rPARAM1,r0
rcall WriteData
rjmp LCDString

LCDString_End:
ret

;-----------------------------------------------------------------
;
; WriteData
; Write rPARAM1 as data

WriteData:
ldi rTEMP,(1< rjmp Write

;-----------------------------------------------------------------
;
; WriteInstruction
; Write rPARAM1 as instruction

WriteInstruction:
ldi rTEMP,0

Write:
mov rTEMP2,rPARAM1

swap rTEMP2
andi rTEMP2,$0F
or rTEMP2,rTEMP

rcall Strobe

mov rTEMP2,rPARAM1
andi rTEMP2,$0F
or rTEMP2,rTEMP

rcall Strobe

rjmp Wait40

;-----------------------------------------------------------------
;
; Strobe
; Output rTEMP2 to PortB and then strobe the enable line

Strobe:
out PORTB,rTEMP2
nop
nop
nop
sbi PORTB,bEN
nop
nop
nop
cbi PORTB,bEN
ret

;-----------------------------------------------------------------
;
; Wait40, WaitMicro
; Wait 40 (or rPARAM1) microseconds

Wait40:
ldi rPARAM1,40 ; 40uS

WaitMicro: ; 4 cycles
nop ; per loop
dec rPARAM1 ; at 4 MHz
brne WaitMicro ; = 1 uS per loop

ret

;-----------------------------------------------------------------
;
; ReadStatus
; Read Status into rReturn.

ReadStatus:
ldi rTEMP,(1< rjmp Read

;-----------------------------------------------------------------
;
; ReadData
; Read Data into rReturn

ReadData:
ldi rTEMP,(1<
Read: out PORTB,rTEMP
nop
sbi PORTB,bEN
nop
nop
in rTEMP,PINB
cbi PORTB,bEN
andi rTEMP,0x0F
swap rTEMP
sbi PORTB,bEN
mov rRETURN,rTEMP
nop
in rTEMP,PINB
cbi PORTB,bEN
andi rTEMP,0x0F
or rRETURN,rTEMP

rjmp Wait40

;-----------------------------------------------------------------
;
; WaitBusy
; Waits until device is not busy

WaitBusy:
rcall ReadStatus
and rRETURN,rRETURN
brmi WaitBusy ; if bit 7 still set, go round again
ret

;-----------------------------------------------------------------
;
; Strings to display

String:
.db "Time since start:", 0

;-----------------------------------------------------------------

Programming the AVR Microcontrollers in Machine Language

AVR
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from

Avr) Jump to: navigation, search The AVRs are a family of RISC
microcontrollers from Atmel. Their internal architecture was
conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the
Norwegian Institute of Technology (NTH] and further developed at
Atmel Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers. These
are 32-bit RISC devices featuring SIMD and DSP instructions, along
with many additional features for audio and video processing,
intended to compete with ARM based processors. Note that the use
of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR
Microcontrollers. The acronym AVR has been reported to stand for
Advanced Virtual RISC. It's also rumoured to stand for the
company's founders: Alf and Vegard, who are evasive when
questioned about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program
Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See
also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR
Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The
AVR is a Harvard architecture machine with programs and data
stored and addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external memory
(though still available on some devices). [edit] Program Memory
Program instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in length. The
Flash memory is addressed using 16 bit word sizes. The size of the
program memory is indicated in the naming of the device itself. For
instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and Registers
The data address space consists of the register file, I/O registers,
and SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are mapped
in as the first thirty-two memory spaces (000016-001F16) followed by
the 64 I/O registers (002016-005F16). The actual usable RAM starts
after both these sections (address 006016). (Note that the I/O register
space may be larger on some more extensive devices, in which case
memory mapped I/O registers will occupy a portion of the SRAM.)
Even though there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still be
addressed and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often used for
long-term parameter storage to be retrieved even after cycling the
power of the device. [edit] Program Execution Atmel's AVRs have a
single level pipeline design. The next machine instruction is fetched
as the current one is executing. Most instructions take just one or
two clock cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were designed for
the efficient execution of compiled C code. The AVR instruction set
is more orthogonal than most eight-bit microcontrollers, however, it
is not completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other. Register
locations R0 to R15 have different addressing capabilities than
register locations R16 to R31. I/O ports 0 to 31 have different
addressing capabilities than I/O ports 32 to 63. CLR affects flags,
while SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to one. (Note
though, that neither CLR nor SER are native instructions. Instead
CLR is syntactic sugar for [produces the same machine code as]
EOR R,R while SER is syntactic sugar for LDI R,$FF. Math
operations such as EOR modify flags while moves/loads/stores/
branches such as LDI do not.) [edit] Speed The AVR line can
normally support clock speeds from 0-16MHz, with some devices
reaching 20MHz. Lower powered operation usually requires a
reduced clock speed. All AVRs feature an on-chip oscillator,
removing the need for external clocks or resonator circuitry.
Because many operations on the AVR are single cycle, the AVR can
achieve up to 1MIPS per MHz. [edit] Development AVRs have a large
following due to the free and inexpensive development tools
available, including reasonably priced development boards and free
development software. The AVRs are marketed under various names
that share the same basic core but with different peripheral and
memory combinations. Some models (notably, the ATmega range)
have additional instructions to make arithmetic faster. Compatibility
amongst chips is fairly good. See external links for sites relating to
AVR development. [edit] Features Current AVRs offer a wide range
of features: RISC Core Running Many Single Cycle Instructions
Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-
up Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-System
Programmable using ICSP, JTAG, or High Voltage methods Optional
Boot Code Section with Independent Lock Bits for Protection
Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and
16-Bit Timers PWM Channels & dead time generator Lighting (PWM
Specific) Controller models Dedicated I²C Compatible Two-Wire
Interface (TWI) Synchronous/Asynchronous Serial Peripherals
(UART/USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB Controller
Support Proper High-speed hardware & Hub controller with
embedded AVR. Also freely available low-speed (HID) software
emulation Ethernet Controller Support Universal Serial Interface
(USI) for Two or Three-Wire Synchronous Data Transfer Analog
Comparators LCD Controller Support 10-Bit A/D Converters, with
multiplex of up to 16 channels Brownout Detection Watchdog Timer
(WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR assembler
programming language Atmel AVR machine programming language
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from
Avr) Jump to: navigation, search The AVRs are a family of RISC
microcontrollers from Atmel. Their internal architecture was
conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the
Norwegian Institute of Technology (NTH] and further developed at
Atmel Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers. These
are 32-bit RISC devices featuring SIMD and DSP instructions, along
with many additional features for audio and video processing,
intended to compete with ARM based processors. Note that the use
of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR
Microcontrollers. The acronym AVR has been reported to stand for
Advanced Virtual RISC. It's also rumoured to stand for the
company's founders: Alf and Vegard, who are evasive when
questioned about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program
Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See
also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR
Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The
AVR is a Harvard architecture machine with programs and data
stored and addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external memory
(though still available on some devices). [edit] Program Memory
Program instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in length. The
Flash memory is addressed using 16 bit word sizes. The size of the
program memory is indicated in the naming of the device itself. For
instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and Registers
The data address space consists of the register file, I/O registers,
and SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are mapped
in as the first thirty-two memory spaces (000016-001F16) followed by
the 64 I/O registers (002016-005F16). The actual usable RAM starts
after both these sections (address 006016). (Note that the I/O register
space may be larger on some more extensive devices, in which case
memory mapped I/O registers will occupy a portion of the SRAM.)
Even though there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still be
addressed and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often used for
long-term parameter storage to be retrieved even after cycling the
power of the device. [edit] Program Execution Atmel's AVRs have a
single level pipeline design. The next machine instruction is fetched
as the current one is executing. Most instructions take just one or
two clock cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were designed for
the efficient execution of compiled C code. The AVR instruction set
is more orthogonal than most eight-bit microcontrollers, however, it
is not completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other. Register
locations R0 to R15 have different addressing capabilities than
register locations R16 to R31. I/O ports 0 to 31 have different
addressing capabilities than I/O ports 32 to 63. CLR affects flags,
while SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to one. (Note
though, that neither CLR nor SER are native instructions. Instead
http://avr-asm.tripod.com/lcd44.html (1 of 2)1/20/2009 9:11:30 PM
16 BIT MATH (AVR 202)

CLR is syntactic sugar for [produces the same machine code as]
EOR R,R while SER is syntactic sugar for LDI R,$FF. Math
operations such as EOR modify flags while moves/loads/stores/
branches such as LDI do not.) [edit] Speed The AVR line can
normally support clock speeds from 0-16MHz, with some devices
reaching 20MHz. Lower powered operation usually requires a
reduced clock speed. All AVRs feature an on-chip oscillator,
removing the need for external clocks or resonator circuitry.
Because many operations on the AVR are single cycle, the AVR can
achieve up to 1MIPS per MHz. [edit] Development AVRs have a large
following due to the free and inexpensive development tools
available, including reasonably priced development boards and free
development software. The AVRs are marketed under various names
that share the same basic core but with different peripheral and
memory combinations. Some models (notably, the ATmega range)
have additional instructions to make arithmetic faster. Compatibility
amongst chips is fairly good. See external links for sites relating to
AVR development. [edit] Features Current AVRs offer a wide range
of features: RISC Core Running Many Single Cycle Instructions
Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-
up Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-System
Programmable using ICSP, JTAG, or High Voltage methods Optional
Boot Code Section with Independent Lock Bits for Protection
Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and
16-Bit Timers PWM Channels & dead time generator Lighting (PWM
Specific) Controller models Dedicated I²C Compatible Two-Wire
Interface (TWI) Synchronous/Asynchronous Serial Peripherals
(UART/USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB Controller
Support Proper High-speed hardware & Hub controller with
embedded AVR. Also freely available low-speed (HID) software
emulation Ethernet Controller Support Universal Serial Interface
(USI) for Two or Three-Wire Synchronous Data Transfer Analog
Comparators LCD Controller Support 10-Bit A/D Converters, with
multiplex of up to 16 channels Brownout Detection Watchdog Timer
(WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR assembler
programming language Atmel AVR machine programming language
Atmel AVR From Wikipedia, the free encyclopedia (Redirected from
Avr) Jump to: navigation, search The AVRs are a family of RISC
microcontrollers from Atmel. Their internal architecture was
conceived by two students: Alf-Egil Bogen and Vegard Wollan, at the
Norwegian Institute of Technology (NTH] and further developed at
Atmel Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers. These
are 32-bit RISC devices featuring SIMD and DSP instructions, along
with many additional features for audio and video processing,
intended to compete with ARM based processors. Note that the use
of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR
Microcontrollers. The acronym AVR has been reported to stand for
Advanced Virtual RISC. It's also rumoured to stand for the
company's founders: Alf and Vegard, who are evasive when
questioned about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program
Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See
also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR
Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The
AVR is a Harvard architecture machine with programs and data
stored and addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external memory
(though still available on some devices). [edit] Program Memory
Program instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in length. The
Flash memory is addressed using 16 bit word sizes. The size of the
program memory is indicated in the naming of the device itself. For
instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and Registers
The data address space consists of the register file, I/O registers,
and SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are mapped
in as the first thirty-two memory spaces (000016-001F16) followed by
the 64 I/O registers (002016-005F16). The actual usable RAM starts
after both these sections (address 006016). (Note that the I/O register
space may be larger on some more extensive devices, in which case
memory mapped I/O registers will occupy a portion of the SRAM.)
Even though there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still be
addressed and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often used for
long-term parameter storage to be retrieved even after cycling the
power of the device. [edit] Program Execution Atmel's AVRs have a
single level pipeline design. The next machine instruction is fetched
as the current one is executing. Most instructions take just one or
two clock cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were designed for
the efficient execution of compiled C code. The AVR instruction set
is more orthogonal than most eight-bit microcontrollers, however, it
is not completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other. Register
locations R0 to R15 have different addressing capabilities than
register locations R16 to R31. I/O ports 0 to 31 have different
addressing capabilities than I/O ports 32 to 63. CLR affects flags,
while SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to one. (Note
though, that neither CLR nor SER are native instructions. Instead
CLR is syntactic sugar for [produces the same machine code as]
EOR R,R while SER is syntactic sugar for LDI R,$FF. Math
operations such as EOR modify flags while moves/loads/stores/
branches such as LDI do not.) [edit] Speed The AVR line can
normally support clock speeds from 0-16MHz, with some devices
reaching 20MHz. Lower powered operation usually requires a
reduced clock speed. All AVRs feature an on-chip oscillator,
removing the need for external clocks or resonator circuitry.
Because many operations on the AVR are single cycle, the AVR can
achieve up to 1MIPS per MHz. [edit] Development AVRs have a large
following due to the free and inexpensive development tools
available, including reasonably priced development boards and free
development software. The AVRs are marketed under various names
that share the same basic core but with different peripheral and
memory combinations. Some models (notably, the ATmega range)
have additional instructions to make arithmetic faster. Compatibility
amongst chips is fairly good. See external links for sites relating to
AVR development. [edit] Features Current AVRs offer a wide range
of features: RISC Core Running Many Single Cycle Instructions
Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-
up Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-System
Programmable using ICSP, JTAG, or High Voltage methods Optional
Boot Code Section with Independent Lock Bits for Protection
Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and
16-Bit Timers PWM Channels & dead time generator Lighting (PWM
Specific) Controller models Dedicated I²C Compatible Two-Wire
Interface (TWI) Synchronous/Asynchronous Serial Peripherals
(UART/USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB Controller
Support Proper High-speed hardware & Hub controller with
embedded AVR. Also freely available low-speed (HID) software
emulation Ethernet Controller Support Universal Serial Interface
(USI) for Two or Three-Wire Synchronous Data Transfer Analog
Comparators LCD Controller Support 10-Bit A/D Converters, with
multiplex of up to 16 channels Brownout Detection Watchdog Timer
(WDT) Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR assembler
programming language Atmel AVR machine programming language

http://avr-asm.tripod.com/lcd44.html (2 of 2)1/20/2009 9:11:30 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

KEYPAD WAKE UP (AVR 240)

HOME
RETRO_DAN
;**** A P P L I C A T I O N N O T E A V R 2 4 0
ASM FORUM ************************
ASM MATH ;*
;* Title: 4x4 keypad, wake-up on keypress
TUTORIAL #1
;* Version: 1.2
TUTORIAL #2 ;* Last Updated: 2004.11.11
TUTORIAL #3 ;* Target: All AVR Devices
;*
MATH 200 ;* Support E-mail: avr@atmel.com
MATH 200b ;*
;* DESCRIPTION
MATH 201 ;* This Application note scans a 4 x 4 keypad and uses
MATH 202 sleep mode
;* causing the AVR to wake up on keypress. The design
MATH 32X
uses a minimum of
MATH YX ;* external components. Included is a test program that
wakes up the AVR
DIV16 XX
;* and performs a scan when a key is pressed and
DIV 24 24 flashes one of two LEDs
DIV 3216 ;* the number of the key pressed. The external
interrupt line is used for
FLOAT 128 ;* wake-up. The example runs on the AT90S1200 but can
SQRT16 be any AVR with suitable
;* changes in vectors, EEPROM and stack pointer. The
MATH 202 timing assumes a 4 MHz clock.
MATH 202 ;* A look up table is used in EEPROM to enable the same
structure to be used
DEC ASCII
;* with more advanced programs e.g ASCII output to
INT ASCII displays.
;
HX2ASC
***************************************************************************
AVG8 222
FFT7 ;***** Register used by all programs
;******Global variable used by all routines
COPY 102
LPM 108 .def temp =r16 ;general scratch space
EPROM 100 ;Port B pins
SER EPROM
.equ ROW1 =3 ;keypad input rows
DFLASH AT45
.equ ROW2 =2
FLASH CARD .equ ROW3 =1
.equ ROW4 =0
VFX SMIL
.equ COL1 =7 ;keypad output columns
VFX MEM .equ COL2 =6
SORT 220 .equ COL3 =5
.equ COL4 =4
CRC 236
XMODEM REC ;Port D pins
UART 304 .equ GREEN =0 ;green LED
UART 305 .equ RED =1 ;red LED
.equ INTR =2 ;interrupt input
UART 128
UART BUFF .include "1200def.inc"
USB 232
;***** Registers used by interrupt service routine
AVR ISP
ISP 2313
.def key =r17 ;key pointer for EEPROM
ISP 1200 .def status =r21 ;preserve sreg here
AVR SPI
;***** Registers used by delay subroutine
I2C 300 ;***** as local variables
I2C 302
.def fine =r18 ;loop delay counters
I2C TWI26
.def medium =r19
I2C/TWI 128 .def coarse =r20
I2C/TWI AT8
;*****Look up table for key
DALLAS-1W conversion******************************
DALLAS CRC .eseg ;EEPROM
segment
ETHNET 8019 .org 0
TEA
.db 1,2,3,15,4,5,6,14,7,8,9,13,10,0,11,12
ADC 128 ;****Source
ADC 10B code***************************************************
.cseg ;CODE
ADC 400
segment
ADC 401 .org 0
THERM 232 rjmp reset ;Reset handler
rjmp scan ;interrupt service
IRD 410 routine
LCD HD44 reti ;unused timer
interrupt
LCD 2313 reti ;unused analogue
LCD44 2313 interrupt
KBD 240
;*** Reset handler
MUX 242 **************************************************
reset:
KBD PS2
KBD PC/128 ldi temp,0xFB ;initialise port D
PS2 EMU as O/I
out DDRD,temp ;all OUT except PD2
BOOT MG8 ext.int.
BOOT DR8 ldi temp,0x30 ;turn on sleep mode
and power
ALM CLK out MCUCR,temp ;down plus
CLOCK 8564 interrupt on low level.
ldi temp,0x40 ;enable external
90 DAYS
interrupts
DELAYS out GIMSK,temp
sbi ACSR,ACD ;shut down
CALL ID
comparator to save power
DTMF 314 main: cli ;disable
PWM 6CH global interrupts
ldi temp,0xF0 ;initialise port B
PWM 10K as I/O
ENCODE out DDRB,temp ; 4 OUT 4 IN
ldi temp,0x0F ;key columns all
STH-11 low and
ATMEL CORP out PORTB,temp ;active pull ups on
rows enabled
AVR
ldi temp,0x07 ;enable pull up on
BUTTERFLY PD2 and
AVR BOOK out PORTD,temp ;turn off LEDs
sei ;enable global
interrupts ready
sleep ;fall asleep
rcall flash ;flash LEDs for
example usage
ldi temp,0x40
out GIMSK,temp ;enable external
interrupt
rjmp main ;go back to sleep
after keyscan

;****Interrupt service
routine***************************************
scan:
in status,SREG ;preserve status
register
sbis PINB,ROW1 ;find row of
keypress
ldi key,0 ;and set ROW pointer
sbis PINB,ROW2
ldi key,4
sbis PINB,ROW3
ldi key,8
sbis PINB,ROW4
ldi key,12
ldi temp,0x0F ;change port B I/O
to
out DDRB,temp ;find column press
ldi temp,0xF0 ;enable pull ups and
out PORTB,temp ;write 0s to rows
rcall settle ;allow time for
port to settle
sbis PINB,COL1 ;find column of
keypress
ldi temp,0 ;and set COL pointer
sbis PINB,COL2
ldi temp,1
sbis PINB,COL3
ldi temp,2
sbis PINB,COL4
ldi temp,3
add key,temp ;merge ROW and COL
for pointer
ldi temp,0xF0 ;reinitialise port
B as I/O
out DDRB,temp ; 4 OUT 4 IN
ldi temp,0x0F ;key columns all
low and
out PORTB,temp ;active pull ups on
rows enabled
out SREG,status ;restore status
register

ldi temp,0x00
out GIMSK,temp ;disable external
interrupt
;have to do this,
because we're
;using a level-
triggered interrupt

reti ;go back to main

for example program

;***Example test program to flash LEDs using key press

data************

flash: out EEAR,key ;address

EEPROM
sbi EECR,EERE ;strobe EEPROM
in temp,EEDR ;set number of
flashes
tst temp ;is it zero?
breq zero ;do RED LED
green_flash:
cbi PORTD,GREEN ;flash green LED
'temp' times
rcall delay
sbi PORTD,GREEN
rcall delay
dec temp
brne green_flash
exit: ret
zero: ldi temp,10
flash_again: cbi PORTD,RED ;flash red
LED ten times
rcall delay
sbi PORTD,RED
rcall delay
dec temp
brne flash_again
rjmp exit

;****Time Delay Subroutine for LED

flash*********************************
delay:
ldi coarse,8 ;triple nested FOR
loop
cagain: ldi medium,255 ;giving
about 1/2 second
magain: ldi fine,255 ;delay on 4
MHz clock
fagain: dec fine
brne fagain
dec medium
brne magain
dec coarse
brne cagain
ret

;***Settling time delay for port to

stabilise******************************
settle:
ldi temp,255
tagain: dec temp
brne tagain
ret

Programming the AVR Microcontrollers in Machine Language

AVR
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected

from Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing,
intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still
be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language
http://avr-asm.tripod.com/kbd240.html (1 of 2)1/20/2009 9:12:04 PM
16 BIT MATH (AVR 202)

http://avr-asm.tripod.com/kbd240.html (2 of 2)1/20/2009 9:12:04 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

KEYPAD LED MUX (AVR 242)

HOME
RETRO_DAN
;**** A P P L I C A T I O N N O T E A V R ???
ASM FORUM ************************
ASM MATH ;*
;* Title: Multiplexing LED drive and 4x4
TUTORIAL #1
keypad sampling
TUTORIAL #2 ;* Version: 1.0
TUTORIAL #3 ;* Last Updated: 98.07.24
;* Target: All AVR Devices
MATH 200 ;*
MATH 200b ;* Support E-mail: avr@atmel.com
;*
MATH 201 ;* DESCRIPTION
MATH 202 ;* This Application note covers a program to provide a
24 hr Industrial
MATH 32X
;* timer or real-time clock using I/O pins for dual
MATH YX functions.
;* With input via a 4 x 4 matrix keypad, output to a
DIV16 XX
multiplexed
DIV 24 24 ;* four digit LED display and two ON/OFF outputs to
DIV 3216 drive loads via additional
;* interface circuitry. LED loads are driven in this
FLOAT 128 example but it could drive
SQRT16 ;* any load with the addition of suitable components.
Tactile feedback is provided
MATH 202 ;* on every key press by a piezo sounder which beeps
MATH 202 when a key is pressed.
;* Included is a main program that allows clock setting
DEC ASCII
via the keypad
INT ASCII ;* and one ON/OFF time setting per 24 hours for each
load, functions for the
HX2ASC
;* real time clock, key scanning, and adjustment
AVG8 222 routines. The example runs on
FFT7 ;* the AT90S1200 to demonstrate how limited I/O can be
overcome, but can
COPY 102 ;* be any AVR with suitable changes in vectors, EEPROM
LPM 108 and stack pointer.
;* The timing assumes a 4.096 MHz crystal is employed
EPROM 100 (a 4 MHz crystal produces
SER EPROM ;* an error of -0.16% if 178 instead of 176 used in the
timer load sequence, but this
DFLASH AT45
;* could be adjusted in software at regular intervals).
FLASH CARD Look up tables are
;* used in EEPROM to decode the display data, with
VFX SMIL
additional characters provided
VFX MEM ;* for time and ON/OFF setting displays and a key pad
SORT 220 conversion table.
;* If the EEPROM is needed for your application the
CRC 236 tables could be moved
XMODEM REC ;* to ROM in the larger AVR devices.
;
UART 304 ***************************************************************************
UART 305
;***** Registers used by all programs
UART 128
;******Global variables used by routines
UART BUFF
USB 232 .def loset =r1 ;storage for timeset minutes
.def hiset =r2 ;storage for timeset
AVR ISP hours
ISP 2313 .def ld1minon=r3 ;storage for load on and
off times
ISP 1200 .def ld1hron =r4 ;set from keypad entry
AVR SPI .def ld1minoff=r5 ;and tested in the
housekeeping function
I2C 300 .def ld1hroff=r6 ;and stores on or off times
I2C 302 for the loads
.def ld2minon=r7
I2C TWI26
.def ld2hron =r8
I2C/TWI 128 .def ld2minoff=r9
I2C/TWI AT8 .def ld2hroff=r10

DALLAS-1W .def temp =r16 ;general scratch space

DALLAS CRC .def second =r17 ;storage for RTC second
count
ETHNET 8019 .def minute =r18 ;storage for RTC minute
TEA count
.def hour =r19 ;storage for RTC hour count
ADC 128 .def mask =r20 ;flash mask for digits
ADC 10B flashing
.def blink =r21 ;colon blink rate counter
ADC 400
.def bounce =r22 ;keypad debounce counter
ADC 401 .def flash =r23 ;flash delay counter
THERM 232 .def lobyte =r24 ;storage for display
function minutes digits
IRD 410 .def hibyte =r25 ;storage for display
LCD HD44 function hours digits
.def key =r26 ;key number from scan
LCD 2313
LCD44 2313 ;***'key' values returned by
'keyscan'***************************
KBD 240
;VALUE 0 1 2 3 4 5 6 7 8 9 10
MUX 242 11 12 13 14 15 16
;KEY 1 2 3 F 4 5 6 E 7 8
KBD PS2
9 D A 0 B C NONE
KBD PC/128 ;FUNC 1 2 3 LD1ON 4 5 6 LD1OFF 7 8 9
PS2 EMU LD2ON SET 0 CLEAR LD2OFF

BOOT MG8 .def tock =r27 ;5 ms pulse

BOOT DR8 .def flags =r28 ;flag byte for keypad
command keys
ALM CLK ; 7 6 5 4 3
CLOCK 8564 2 1 0
; 5ms keyok ld2off ld2on ld1off
90 DAYS
ld1on ld2 ld1
DELAYS ; tick 0 = off, 1 = on
.equ ms5 =7 ;ticks at 5 ms intervals
CALL ID
for display time
DTMF 314 .equ keyok =6 ;sets when key is
PWM 6CH debounced, must be cleared again
.equ ld2off =5 ;set by load ON/OFF key
PWM 10K press and flags
ENCODE .equ ld2on =4 ;up the need for action
.equ ld1off =3 ;in the housekeeping routine
STH-11 .equ ld1on =2
ATMEL CORP .equ ld2 =1 ;when set tells the
housekeeping routine to
AVR
.equ ld1 =0 ;check load on/off times.
BUTTERFLY
AVR BOOK ;***the T flag in the status register is used as a SET
flag for time set
.equ clear =0 ;RTC modification demand
flag

;Port B pins

.equ col1 =0 ;LED a segment/keypad col 1

.equ col2 =1 ;LED b segment/keypad col 2
.equ col3 =2 ;LED c segment/keypad col 3
.equ col4 =3 ;LED d segment/keypad col 4
.equ row1 =4 ;LED e segment/keypad row 1
.equ row2 =5 ;LED f segment/keypad row 2
.equ row3 =6 ;LED g segment/keypad row 3
.equ row4 =7 ;LED decimal point/keypad
row 4

;Port D pins

.equ A1 =0 ;common anode drives

(active low)
.equ A2 =1 ;
.equ A3 =2 ;
.equ A4 =3 ;
.equ LOAD1 =4 ;Load 1 output (active low)
.equ LOAD2 =5 ;Load 2 output (active low)
.equ PZ =6 ;Piezo sounder output
(active low)

.include "1200def.inc"

;***** Registers used by timer overflow interrupt

service routine

.def timer =r31 ;scratch space for timer

loading
.def status =r0 ;low register to preserve
status register

;*****Look up table for LED display decoding

**********************
.eseg ;EEPROM
segment
.org 0

table1: .db
0xc0,0xf9,0xa4,0xb0,0x99,0x92,0x82,0xf8,0x80,0x90
;digit 0 1 2 3 4 5 6 7
8 9

.db 0x86,0x8E,0xA3,0xAB,0XFF,0XFF
;digit E f o n BLANK special
characters

;****Look up table for key value conversion into useful

numbers****

;key 1 2 3 F 4 5 6 E 7 8 9 D A
0 B C
table2: .db 1, 2, 3,15, 4, 5, 6,14, 7, 8, 9,
13, 10, 0, 11, 12
;value 0 1 2 3 4 5 6 7 8 9 10 11 12
13 14 15

;****Source
code***************************************************
.cseg ;CODE
segment
.org 0
rjmp reset ;Reset handler
nop ;unused ext.
interrupt
rjmp tick ;timer counter
overflow (5 ms)
nop ;unused analogue
interrupt

;*** Reset handler

**************************************************
;*** to provide initial port, timer and interrupt
setting up

reset:
ser temp ;
out DDRB,temp ;initialize port B
as all Outputs
out DDRD,temp ;initialize port D
as all Outputs
out PORTB,temp ;key columns all
high/LEDs off
out PORTD,temp ;turn off LEDs and
loads off
ldi temp,0x04 ;timer
prescalar /256
out TCCR0,temp
ldi timer,176 ;load timer for 5 ms
out TCNT0,timer ;(256 - n)
*256*0.2441 us
ldi temp,0x02 ;enable timer
interrupts
out TIMSK,temp
clr flags ;clear control flags
clr tock ;clear 5 ms tick
clr bounce ;clear key bounce
counter
clr flash
clr blink
sei ;enable global
interrupts

;****Flash EEEE on LEDS as test and power down

warning**************
;****repeats until SET key is pressed on keypad

timesetting: ldi hibyte,0xaa ;show

"EEEE" on LED
ldi lobyte,0xaa ;display and
ser mask ;set flashing
display
notyet: rcall display ;display
until time set
brtc notyet ;repeat until SET
key pressed
rcall setrtc ;and reset
time
mov hour,hiset ;and reload
hours
mov minute,loset ;and minutes
clt ;clear T flag

;*****Main clock house keeping

loop*****************************

do:
clr mask ;do housekeeping
cpi blink,100 ;is half second up
brne nohalf
clr blink
com flash ;invert flash
nohalf:
cpi second,60 ;is one minute up?
brne nochange ;no
clr second ;yes clear seconds
and
inc minute ;add one to minutes
mov temp,minute
andi temp,0x0f ;mask high minute
cpi temp,10 ;is it ten minutes?
brne nochange ;no
andi minute,0xf0 ;clear low minutes
ldi temp,0x10
add minute,temp ;increment high
minutes
cpi minute,0x60 ;is it 60 minutes?
brne nochange ;no
clr minute ;yes, clear minutes
and
inc hour ;add one to hours
mov temp,hour
andi temp,0x0f ;mask high hour
cpi temp,10 ;is 10 hours up?
brne nochange ;no
andi hour,0xf0 ;yes, increment
ldi temp,0x10
add hour,temp ;high hours
nochange:
cpi hour,0x24 ;is it 24
hours?
brne sameday ;no,
clr hour ;yes, clear time
variables
clr minute ;to start new day
clr second
sameday: ;update times
mov lobyte,minute
mov hibyte,hour
rcall display ;show time for 20 ms
brtc case1 ;if not SET
rcall setrtc ;and reset
time
mov hour,hiset ;and reload
hours
mov minute,loset ;and minutes
clt ;else, clear T
flag
case1: sbrc flags,ld1 ;is load 1
active?
rjmp chkload1 ;yes, check load 1
case2: sbrc flags,ld2 ;is load 2
active
rjmp chkload2 ;yes, check load 2
case3: sbrc flags,ld1on ;is load 1
on time reset
rjmp setld1on ;yes reset on time
case4: sbrc flags,ld1off ;is load 1
off time reset
rjmp setld1off ;yes reset off time
case5: sbrc flags,ld2on ;is load 2
on time reset
rjmp setld2on ;yes reset on time
case6: sbrc flags,ld2off ;is load 2
on time reset
rjmp setld2off ;yes reset on time
case7: rjmp do ;repeat
housekeeping loop

;****case routines to service load times and key

presses********

chkload1: cp hour,ld1hroff ;is load 1 off time

reached?
brne onload1
cp minute,ld1minoff
brne onload1
sbi PORTD,LOAD1 ;yes, turn load 1
off
onload1:
cp hour,ld1hron ;is load 1 on time
reached?
brne case2
cp minute,ld1minon
brne case2
cbi PORTD,LOAD1 ;yes,turn load 1 on
rjmp case2 ;repeat with load on

chkload2: cp hour,ld2hroff ;is load 2 off time

reached?
brne onload2
cp minute,ld2minoff
brne onload2
sbi PORTD,LOAD2 ;yes, turn load 2
off
onload2:
cp hour,ld2hron ;is load 2 on time
reached?
brne case3
cp minute,ld2minon
brne case3
cbi PORTD,LOAD2 ;yes,turn load 2 on
rjmp case3 ;repeat with load on
setld1on:
sbr flags,0x01 ;make load 1 active
rcall setrtc ;pickup new on time
mov ld1hron,hiset ;and store
mov ld1minon,loset
cbr flags,0x04 ;clear ld1on flag
rjmp case4

setld1off:

rcall setrtc ;pickup new off time

mov ld1hroff,hiset ;and store
mov ld1minoff,loset
cbr flags,0x08 ;clear ld1off flag
rjmp case5
setld2on:
sbr flags,0x02 ;make load 2 active
rcall setrtc ;pickup new on time
mov ld2hron,hiset ;and store
mov ld2minon,loset
cbr flags,0x10 ;clear ld2on flag
rjmp case6
setld2off:

rcall setrtc ;pickup new on time

mov ld2hroff,hiset ;and store
mov ld2minoff,loset
cbr flags,0x20 ;clear ld2off flag
rjmp case7

;****Multiplexing routine to display time and scan

keypad every*****
;****second pass,used by all routines taking digits
from hibyte
;****and lobyte locations with each digit on for 5 ms

display: ser temp ;clear display

out PORTB,temp
;****Keypad scanning routine to update key
flags*******************

keyscan: cbr flags,0x40 ;clear keyok flag

ldi key,0x10 ;set no key pressed
value
ser temp ;set keypad port
high prior to
out PORTB,temp ;reinitializing the
port
in temp,PORTD ;turn off LEDs and
leave loads
ori temp,0x0f ;untouched prior to
out PORTD,temp ;key scan
ldi temp,0x0f ;set columns output
and
out DDRB,temp ;rows input with
pull-ups
ldi temp,0xf0 ;enabled and all
columns
out PORTB,temp ;low ready for scan
ldi temp,20 ;short settling time
tagain1: dec temp
brne tagain1
sbis PINB,ROW1 ;find row of
keypress
ldi key,0 ;and set ROW pointer
sbis PINB,ROW2
ldi key,4
sbis PINB,ROW3
ldi key,8
sbis PINB,ROW4
ldi key,12
ldi temp,0xF0 ;change port B I/O
to
out DDRB,temp ;find column press
ldi temp,0x0F ;enable pull ups and
out PORTB,temp ;write 0s to rows
ldi temp,20 ;short settling time
tagain2: dec temp
brne tagain2 ;allow time for
port to settle
clr temp
sbis PINB,COL1 ;find column of
keypress
ldi temp,0 ;and set COL pointer
sbis PINB,COL2
ldi temp,1
sbis PINB,COL3
ldi temp,2
sbis PINB,COL4
ldi temp,3
add key,temp ;merge ROW and COL
for pointer
cpi key,0x10 ;if no key pressed
breq nokey ;escape routine,
else
ldi temp,0x10
add key,temp ;change to table 2
out EEAR,key ;send address to
EEPROM (0 - 15)
sbi EECR,EERE ;strobe EEPROM
in key,EEDR ;read decoded
number for true key
convert: cpi key,10 ;is it SET key ?
brne notset ;no check next key
set ;yes set T flag in
status register
notset: cpi key,11 ;is key
CLEAR?
brne notclear ;no, check next key
sbi PORTD,LOAD1 ;yes, shut down all
loads
sbi PORTD,LOAD2
cbr flags,0x03 ;deactivate both
loads
notclear: cpi key,15 ;is key LD1ON?
brne notld1on ;no, check next key
sbr flags,0x04 ;yes, set LD1ON flag
notld1on: cpi key,14 ;is key LD1OFF?
brne notld1off ;no, check next key
sbr flags,0x08 ;yes, set LD1OFF
flag
notld1off: cpi key,13 ;is key LD2ON?
brne notld2on ;no, check next key
sbr flags,0x10 ;yes, set LD2ON flag
notld2on: cpi key,12 ;is key LD2OFF?
brne notld2off ;no, check next key
sbr flags,0x20 ;yes, set LD2OFF
flag
notld2off:

;***Tactile feedback note generation

routine*****************
;***provides a 4 kHz TONE to the piezo sounder for 5
ms*****

tactile: cbr flags,0x80

cbi PORTD,PZ ;turn on piezo
ldi temp,125 ;for a short time
t1again: dec temp
brne t1again
sbi PORTD,PZ ;turn on piezo
ldi temp,125 ;for a short time
t2again: dec temp
brne t2again
sbrs flags,ms5 ;repeat for 5ms
rjmp tactile
notok: cpi bounce,40
brlo nokey
sbr flags,0x40 ;set bounce flag
nokey: ser temp
out DDRB,temp ;reinitialize port
B as all Outputs
out PORTB,temp ;and clear LEDs

;***Display routine to multiplex all four LED

digits****************

cbi PORTD,A1 ;turn digit 1 on

mov temp,lobyte ;find low minute
digit1:
cbr flags,0x80 ;clear 5 ms tick
flag
andi temp,0x0f ;mask high nibble
of digit
out EEAR,temp ;send address to
EEPROM (0 - 15)
sbi EECR,EERE ;strobe EEPROM
in temp,EEDR ;read decoded number
sbrs flash,clear ;flash every 1/2
second
or temp,mask ;flash digit if
needed
out PORTB,temp ;write to LED for 5
ms
led1: sbrs flags,ms5 ;5 ms
finished?
rjmp led1 ;no, check again
sbi PORTD,A1 ;turn digit 1 off
ser temp ;clear display
out PORTB,temp
cbi PORTD,A2 ;
mov temp,lobyte ;find high minute
swap temp
digit2:
cbr flags,0x80 ;clear 5 ms tick
flag
andi temp,0x0f ;mask high nibble
of digit
out EEAR,temp ;send address to
EEPROM (0 - 15)
sbi EECR,EERE ;strobe EEPROM
in temp,EEDR ;read decoded number
sbrs flash,clear ;flash every 1/2
second
or temp,mask ;flash digit if
needed
out PORTB,temp ;write to LED for 5
ms
led2: sbrs flags,ms5 ;5 ms
finished?
rjmp led2 ;no, check again
sbi PORTD,A2 ;
ser temp ;clear display
out PORTB,temp
cbi PORTD,A3 ;
mov temp,hibyte
digit3:
cbr flags,0x80 ;clear 5 ms tick
flag
andi temp,0x0f ;mask high nibble
of digit
out EEAR,temp ;send address to
EEPROM (0 - 15)
sbi EECR,EERE ;strobe EEPROM
in temp,EEDR ;read decoded number
sbrs second,clear ;flash colon
andi temp,0x7f
sbrs flash,clear ;flash every 1/2
second
or temp,mask ;flash digit if
needed
out PORTB,temp ;write to LED for 5
ms
led3: sbrs flags,ms5 ;5 ms
finished?
rjmp led3 ;no, check again
sbi PORTD,A3
ser temp ;clear display
out PORTB,temp
cbi PORTD,A4 ;
mov temp,hibyte
swap temp
andi temp,0x0f ;is hi hour zero?
brne digit4
ldi temp,0xff ;yes,blank hi hour
digit4:
cbr flags,0x80 ;clear 5 ms tick
flag
andi temp,0x0f ;mask high nibble
of digit
out EEAR,temp ;send address to
EEPROM (0 - 15)
sbi EECR,EERE ;strobe EEPROM
in temp,EEDR ;read decoded number
sbrs flash,clear ;flash every 1/2
second
or temp,mask ;flash digit if
needed
out PORTB,temp ;write to LED for 5
ms
led4: sbrs flags,ms5 ;5 ms
finished?
rjmp led4 ;no, check again
sbi PORTD,A4
ser temp ;clear display
out PORTB,temp
tst mask ;is flash complete?
breq outled ;yes, exit
cpi blink,50 ;is blink time done?
brlo outled ;no, exit
clr blink ;yes, clear blink
rate counter
com flash ;and invert flash
byte
outled: ret

;****Function to Set RTC/on-off hours and minutes from

keypad
;****returns with minutes in 'loset' and hours in'hiset'

setrtc: ser mask ;set

flashing display
ldi hibyte,0xdf ;place 'n' in hi
hour
ser lobyte ;and blank in lo hr
& minutes
hihrus: clr bounce
bounce1: rcall display ;display and check
keypad
sbrs flags,keyok
rjmp bounce1
cbr flags,0x40 ;clear keyok flag
cpi key,0x03 ;is high hour > 2
brsh hihrus ;yes, read key again
hihrok: ;no, valid
entry
swap key ;move hihour to hi
nibble
mov hiset,key ;and store in hours
ldi hibyte,0x0d ;place 'n' in lo
hour
add hibyte,hiset ;merge hihour and
'n'
lohrus: clr bounce
bounce2: rcall display ;display and check
keypad
sbrs flags,keyok ;is key stable?
rjmp bounce2 ;no try again
cbr flags,0x40 ;yes, clear keyok
flag
mov temp,hibyte ;check that total
hours
andi temp,0xf0 ;are not > 24
add temp,key
cpi temp,0x24 ;is hour>24?
brsh lohrus ;yes, read key again
add hiset,key ;no, merge hi and
lo hours
lohrok:
mov hibyte,hiset ;display hours as
set
ldi lobyte,0xdf ;place 'n' in hi
minutes
himinus: clr bounce
bounce3: rcall display ;display and check
keypad
sbrs flags,keyok
rjmp bounce3
cbr flags,0x40 ;clear keyok flag
cpi key,6 ;is hi minutes >5
brsh himinus ;no, read key again
lominok:
swap key ;move himin to hi
nibble
mov loset,key ;and store in
minutes
ldi lobyte,0x0d ;place 'n' in lo
minutes
add lobyte,loset ;merge with hi
minute
lominus: clr bounce
bounce4: rcall display ;display and check
keypad
sbrs flags,keyok
rjmp bounce4
cbr flags,0x40 ;clear keyok flag
cpi key,10 ;is key >9
brsh lominus ;no, read key again
add loset,key ;yes, merge hi and
lo minutes
clr mask ;clear digits flash
ret ;and return with
time set

;****Timer Overflow Interrupt service

routine******************************
;****Updates 5 ms, flash and debounce counter to
provide RTC time reference

tick:
in status,SREG ;preserve status
register
inc tock ;add one to 5 ms
'tock' counter
inc blink ;and blink rate
counter
inc bounce ;and bounce rate
delay
sbr flags,0x80 ;set 5 ms flag for
display time
cpi tock,200 ;is one second up?
breq onesec ;yes, add one to
seconds
nop ;balance interrupt
time
rjmp nosecond ;no, escape
onesec: inc second ;add one to
seconds
clr tock ;clear 5 ms counter
nosecond: ldi timer,176 ;reload timer
out TCNT0,timer
out SREG,status ;restore status
register
reti ;return to main

Programming the AVR Microcontrollers in Machine Language

AVR
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© WebRing Inc. Search

Atmel AVR From Wikipedia, the free encyclopedia (Redirected

from Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing,
intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still
be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due

http://avr-asm.tripod.com/mux242.html (1 of 2)1/20/2009 9:12:40 PM

16 BIT MATH (AVR 202)

to the free and inexpensive development tools available,

including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language

http://avr-asm.tripod.com/mux242.html (2 of 2)1/20/2009 9:12:40 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

AT/PS2 KEYBOARD PROGRAM

HOME
RETRO_DAN
;
ASM FORUM ***************************************************************************
ASM MATH ;
; File Name :"PS2Drv.asm"
TUTORIAL #1
; Title :PS/2 target communication
TUTORIAL #2 protocoll
TUTORIAL #3 ; Date :2001.10.06.
; Date (Last) :2002.12.15.
MATH 200 ; Version :1.10
MATH 200b ; Support telephone :+36-70-333-4034, Old: +36-30-9541-658
VFX
MATH 201 ; Support fax :
MATH 202 ; Support Email :info@vfx.hu
; Target MCU :AT90S8515
MATH 32X
;
MATH YX ;
***************************************************************************
DIV16 XX
; D E S C R I P T I O N
DIV 24 24 ;
DIV 3216 ; - PS/2 style communication from AT keyboard or MARGOR HI-
01 to MAGOR CP01-1v2
FLOAT 128 ;
SQRT16 ; CLK & DATA = H -> Two way communication
; DATA = L -> PC (MAGOR) sends to Keyb
MATH 202 ; CLK = L -> PC (MAGOR) inhibits communiaction
MATH 202 ;
;
DEC ASCII
***************************************************************************
INT ASCII ; M O D I F I C A T I O N H I S T O R Y
;
HX2ASC
;
AVG8 222 ; rev. date who why
FFT7 ; ---- ---------- ---
--------------------------------------------
COPY 102 ; 0.01 2001.10.06 VFX Creation
LPM 108 ; 1.02 2001.12.27 VFX Modify for MAGOR CP01-1v2
; 1.10 2002.12.15 VFX Fixed Sendig Command to
EPROM 100 keyboard, time out added
SER EPROM ;
;
DFLASH AT45
;
FLASH CARD **************************************************************************
;* Hardware Abstraction Layer
VFX SMIL
VFX MEM .EQU PS2_CLKPort = PORTD
SORT 220 .EQU PS2_CLKDIR = DDRD
.EQU PS2_CLKPIN = PIND
CRC 236 .EQU KCLK = 2
XMODEM REC
.EQU PS2_DATPort = PORTB
UART 304 .EQU PS2_DATDIR = DDRB
UART 305 .EQU PS2_DATPIN = PINB
.EQU KDATA = 0
UART 128
UART BUFF
USB 232 ;
***************************************************************************
AVR ISP ;* Const Def
ISP 2313
.equ wait100us = SYSCLK/10000 ;ennyi ciklus
ISP 1200 100us
AVR SPI
.EQU Kb_ScData_Lenght = 6 ;Received
I2C 300 ScanCode buffer
I2C 302
;--------------------------------
I2C TWI26
;Define commands to the keyboard.
I2C/TWI 128 ;
I2C/TWI AT8 .equ SET_KEYBOARD_INDICATORS = 0xED
.equ KEYBOARD_ECHO = 0xEE
DALLAS-1W .equ SELECT_SCAN_CODE_SET = 0xF0
DALLAS CRC .equ READ_KEYBOARD_ID = 0xF2
.equ SET_KEYBOARD_TYPEMATIC = 0xF3
ETHNET 8019 .equ KBD_ENABLE = 0xF4
TEA .equ KBD_DISABLE = 0xF5
.equ SET_ALL_TYPEMATIC_MAKE_BREAK = 0xFA
ADC 128 .equ KEYBOARD_RESET = 0xFF
ADC 10B
;---------------------------------
ADC 400
; Define the keyboard responses.
ADC 401 ;
THERM 232 .equ ACKNOWLEDGE = 0xFA
.equ RESEND = 0xFE
IRD 410 .equ KEYBOARD_COMPLETE_SUCCESS = 0xAA ;BAT complete
LCD HD44 .equ KEYBOARD_COMPLETE_FAILURE = 0xFC
.equ KEYBOARD_BREAK_CODE = 0xF0
LCD 2313 .equ KEYBOARD_DEBUG_HOTKEY_ENH = 0x37 ;SysReq scan
LCD44 2313 code for Enhanced Keyboard
.equ KEYBOARD_DEBUG_HOTKEY_AT = 0x54 ;SysReq scan
KBD 240
code for 84-key Keyboard
MUX 242
KBD PS2
.equ ST_Success = 0x80 ;a parancs
KBD PC/128 sikeres volt
PS2 EMU .equ ST_Unsuccess = 0x81 ;a parancs
sikertelen
BOOT MG8 .equ ST_ResendError = 0x82 ;3-szor probltuk
BOOT DR8 kuldeni a keyboard fele, de nem ment
.equ ST_ACKnotreseived=0x83 ;ACK-t vartunk
ALM CLK de nem az jott...
CLOCK 8564
;
90 DAYS
***************************************************************************
DELAYS ;**** VARIABLES
.DSEG
CALL ID
DTMF 314 PtrINT0: .BYTE 2 ;INT0 Keyboard interrupt
PWM 6CH aktualis cime
;int0 eseten ide ugrik
PWM 10K
ENCODE Kb_BitCounter: .BYTE 1 ;hany bitet olvasott
eddig be
STH-11 ResevedBits: .byte 1 ;received Kb_bits
ATMEL CORP Kb_Paritas: .byte 1 ;Vett paritas bit
AVR
BUTTERFLY Kb_ScHead: .byte 1 ;Dekodolatlan Scankod buffer
AVR BOOK Head mutato
Kb_ScTail: .byte 1
Kb_ScData: .byte Kb_ScData_Lenght

kb_SendByte: .byte 1 ;send this data to

keyboard
kb_ComStat: .byte 1 ;=0 szabadon megallithato a
komunikacio
;=1 komunikacio megallitasa tilos
;=3 kuldes folyamatban
kb_lastAction: .byte 1 ;utolso muvelet mi volt
;=255 normal mukodes
;=0,1,2,3,4,5 command/parameter
kuldes volt ACK-ot varunk vissza
kb_CmdBuffer: .byte 3 ;1 CMD + 3 data bytenak
van hely
kb_ResendCnt: .byte 1 ;hanyszor probaltuk
elkuldeni, ha tobb mint 3 akkor error
kb_Status: .byte 2
jumptabla: .byte 2

kb_SWStatus: .byte 1 ;keyboard status

; [7:6] = 00 Standard PS/2
keyboard
; = 01 MAGOR HI-01 keyboard
; = 1x future
; [5:0] = CAPS,NUM, SCROLL lock
& future LEDs

;
***************************************************************************
.ESEG

;
***************************************************************************
.CSEG

;
***************************************************************************
; PS/2 Billentyuzet inicializalasa
;
Init_PS2: CBI PS2_CLKPort,KCLK
CBI PS2_CLKDIR,KCLK ;CLK pin tre-
stated external pull-up res!!
CBI PS2_DATPort,KDATA
CBI PS2_DATDIR,KDATA ;DATA pin tre-
stated external pull-up res!!

ldi R16,Low(Kb_Rec_Start) ;Most csak adat

vetele van!
sts PtrINT0+0,R16
ldi R16,High(Kb_Rec_Start)
sts PtrINT0+1,R16

clr R16
sts Kb_ScHead,R16 ;ScanCode
Pointer Head = 0
sts Kb_ScTail,R16
sts kb_ComStat,R16
sts kb_ResendCnt,R16
sts kb_Status,R16
sts kb_SWStatus,R16
ldi R16,255
sts kb_lastAction,R16 ;normal mukodes

ldi R16,11 ;1 start +8 adat

+1 par +1 stop
sts Kb_BitCounter,R16

ldi ZL,low(NormalUzem)
ldi ZH,high(NormalUzem)
sts jumptabla+0,ZL
sts jumptabla+1,ZH

in R16,MCUCR
cbr R16,0b00000011 ;mask for 1,0
bits
sbr R16,0b00000010 ;set for falling
edge
OUT MCUCR,R16 ;1:0 = Inerrupt
Sense Control for INT0
; 00 -> Low
Level INT0
; 01 -> Reserved
; 10 -> Falling
Edge INT0
; 11 -> Rising
Edge INT0

ldi R16,64 ;INT0,1 IRQ flag

torlese
out GIFR,R16

in R16,GIMSK
ori R16,64 ;INT0 enabled
OUT GIMSK,R16 ;6. = 1 EXT INT0
ACTIVE

ldi R16,250 ;varunk 2500ms-

ig, hogy a power-up reset befejezodjon
sts SWTmr0,R16 ;ha kozben
megjon az 0xAA, akkor jo.
WTC0:
lds R16,SWTmr0
tst R16
breq WTCTO ;ha innen ugrik,
szinte biztos hogy hiba lesz
sleep
nop
rcall Get_ScanC
brcs WTC0

WTCTO:

rcall kb_CMD_Reset
rcall WaitToComplete
brcs KeybErr
cpi R16,KEYBOARD_COMPLETE_SUCCESS
brne KeybErr

rcall kb_CMD_ReadID
rcall WaitToComplete
brcs KeybErr

ldi R18,64
cpi R16,0xDE
brne nonPS2
cpi R17,0xD0 ;0x83AB
nem tudom mi lehet minden billentyu
breq storeType ;0x9EAB -
vel ter vissza
;0xDED0
csak MAGOR HI-01 lehet
nonPS2: ldi R18,04 ;
Itt csak szabvany billentyu lehet
storeType:
sts kb_SWStatus,R18 ;
keyboard tipus eltarolva, majd kesobb kell meg

rcall kb_CMD_ALLMakeBrake
rcall WaitToComplete
brcs KeybErr
cpi R16,ST_Success
brne KeybErr

ldi R17,0 ;30char/

s, 250ms rep. time
rcall kb_CMD_SetSpeed
rcall WaitToComplete
brcs KeybErr
cpi R16,ST_Success
brne KeybErr

ldi R17,0
rcall kb_CMD_SetLEDs ;LEDek
kikapcsolva
rcall WaitToComplete
brcs KeybErr
cpi R16,ST_Success
brne KeybErr

ldi R16,low(ps2stszov*2)
ldi R17,high(ps2stszov*2)
lds R18,kb_SWStatus
andi R18,0b11000000 ;csak a
bill tipusa kell
breq kszoveg
ldi R16,low(magorszov*2)
ldi R17,high(magorszov*2)
rjmp kszoveg
KeybErr:
ldi R16,Low(kbTimeOutErr*2)
ldi R17,High(kbTimeOutErr*2)
kszoveg: rcall SendMSG
ret

;************************************************
;* WaitToComplete
;* kivarja egy billentyuparancs vegrehajtasat vagy time-out
;* R17:R16 ststus kod (redszerint csak az R16 kell)
; c=1 error
WaitToComplete:
ldi R16,40 ;ha 400ms-ig
nincs valasz hiba @100Hz rendszermegwszakitas mellett
sts SWTmr0,R16
WTC1: lds R16,SWTmr0
tst R16
breq WTCTimeOut
lds R16,kb_Status+0
cpi R16,0x33
breq WTC1
ldi R17,kb_Status+1
clc
ret
WTCTimeOut: sec
ret

;
******************************************************************************
;* INERRUPT: R E C E I V E
;*
;* External generated clock & data - host changes the Data
line only when
;* the Clock line is low, and data is latched on the falling
edge of the clock pulse
;* Host may abort transmission at time before the 11th clock
pulse (acknowledge bit)
;* by holding Clock low for at least 100 microseconds.
;*
;*
EXT_INT0: push ZL
push ZH
in ZL,SREG ;
preserve main OS status reg.
push ZL
push R16
push R2

in R2,PS2_DATPIN
bst R2,KDATA ;T-ben a
vett bit
lds ZL,PtrINT0+0
lds ZH,PtrINT0+1
icall ;Int0
vegrehajto rutin meghivasa
ldi R16,64 ;INT0
IRQ flag torlese
out GIFR,R16 ;lehet,
hogy ez nem kell majd!!!!

pop R2
pop R16
pop ZL
out SREG,ZL ;
restore previous status reg
pop ZH
pop ZL
reti

;*****************************************
; Receive 11 keyboard bit
;
Kb_Rec_Start: lds R16,Kb_BitCounter
dec R16
sts Kb_BitCounter,R16
cpi R16,10 ;start bitnel
tartunk
breq JaStartbit
cpi R16,1 ;Paritasbit jon?
breq JaParitasJon
cpi R16,0 ;Stopbit jon?
breq JaStopJon

;************************************** ;8
adatbit vetele
;* 8 DATA BIT

Kb_Rec_Dat: lds R16,ResevedBits ;az eddig

beolvasott bitek
lsr R16 ;rota 7. -> 0.
bld R16,7 ;az ujbitet a 7.
pos-on taroljuk
sts ResevedBits,R16 ;tarolas
clr R2
bld R2,0 ;a paritas
generalashoz kell
lds R16,Kb_Paritas
add R16,R2
sts Kb_Paritas,R16 ;uj paritas
eltarolva

lds R16,Kb_BitCounter ;ha tobb mint 9

bit jott eddig,
;akor mar nem
lehet megallitani
;a vetelt. Be
kell fejezni!
cpi R16,4
brsh kb_Rec_end1
ldi R16,1
sts kb_ComStat,R16

kb_Rec_end1: ret

;**************************************
;* START BIT

JaStartbit: clr R16

sts Kb_Paritas,R16 ;Paritas = 0,
most meg :)
bld R16,0 ;Received Start
bit in pos. 0
tst R16
brne Kb_StartErr
ret

Kb_StartErr:
;ide jon az az eset, ha a start bit = 1 ,azaz
hiba van!!!!
;de Vigyazat! Meg interrupt rutinban vagyuk!!!!
ret

;**************************************
; PARITAS BIT

JaParitasJon: clr R16

bld R16,0 ;Paritasbit
tarolasa a 0. bitben
lds R2,Kb_Paritas ;R2 vett adat
par, R16 vett paritas bit
inc R2 ;paratlan
paritas kell!
eor R2,R16 ;R2 = parity xor
parity bit
ror R2 ;C-flagben a
parity
brcs Kb_RxParErr
ret

Kb_RxParErr: ;ide jon majd a paritas hiba lekezelese

;De figyelem, meg mindig interruptban
vagyuk!!!!!!

ret

;************************************
;* STOP BIT

JaStopJon: bld R16,0 ;itt mar R16=0,

R16=stop bit
tst R16
breq Kb_StopErr
ldi R16,11 ;1 start
+8 adat +1 par +1 stop
sts Kb_BitCounter,R16 ;a kovetkezo
adat vetelehez

lds R16,kb_lastAction
cpi R16,255
breq NemParancsvolt

lds R16,ResevedBits
cpi R16,RESEND
brne nemresend

lds R16,kb_ResendCnt
inc R16
sts kb_ResendCnt,R16
cpi R16,4 ;ha mar
haromszor probaltuk elkuldeni, de nem ment
;akkor resend
error
brne Mehettovabb
ldi R16,255
sts kb_lastAction,R16 ;vissza anormal
mukodesre
ldi R16,ST_ResendError
sts kb_Status,R16
ret
Mehettovabb:
rcall NextComdData
ret

nemresend: lds ZL,jumptabla+0

lds ZH,jumptabla+1
ijmp

NemParancsvolt:
rcall Put_ScanC ;Scankod a
bufferbe
clr R16
sts kb_ComStat,R16 ;Stop tilalom
feloldva!

ret

Kb_StopErr: ;ide jon majd a hibas stop bit lekezelese

;Meg mindig INTERRUPTBAN vagyunk!!!!

clr R16
sts kb_ComStat,R16 ;Stop tilalom
feloldva!
ret

;************************************************
;* The Put_ScanC FIFO manager *
;* in: - *
;* out c=1 hiba *
;************************************************
Put_ScanC: lds R16,Kb_ScHead
ldi ZL,Kb_ScData_Lenght
lds R2,Kb_ScTail
sub R2,R16
breq PSC4 ;T=H, akkor
Kb_ScData_Lenght hely van
brcs PSC2
clr ZL
PSC2: add ZL,R2
dec ZL
PSC4: cpi ZL,1 ;ZL = hely a
bufferben
brcs PSCExitwError ;ha <1 nincs elg
hely! Hiba!

clr R2
ldi ZL,low(Kb_ScData) ;Pointer to the
buffer (FIFO)
ldi ZH,high(Kb_ScData)
add ZL,R16
adc ZH,R2 ;add address
offset..
lds R2,ResevedBits ;ez elobb vet 8
kb_data bit
st Z,R2 ;eltarolva a
scankod bufferben
inc R16
cpi R16,Kb_ScData_Lenght ;Pointer>Len
brcs PSC3
clr R16 ;ha igen
Pointer=0, atfordult
PSC3: sts Kb_ScHead,R16
ScanCexit: clc ; Nincs hiba
ret

PSCExitwError: ;ide jon az, ha a scankod bufferben

nincs hely!
;de mi van ha nincs hely, es meg mindig
megszakitasban vagyunk!!

sec ;Hiba!!
ret

;**************************************
; FIFO Manager folytatasa
; mar nem interruptbol megy!!!!
; Out: c=0, R0 = scankod
;
Get_ScanC: clr R0
lds R18,Kb_ScTail
lds R19,Kb_ScHead
cp R19,R18
breq ScanErrExit ;nincs adat a
bufferben

ldi ZL,low(Kb_ScData) ;Pointer to the

rxbuffer (FIFO)
ldi ZH,high(Kb_ScData)
add ZL,R18
adc ZH,R0 ;add address
offset...
ld R0,Z
inc R18
cpi R18,Kb_ScData_Lenght
brlo ScanCbx
clr R18 ;Circle around
to the first buffer pos.
ScanCbx: sts Kb_ScTail,R18
clc ;Valid Char
ret
ScanErrExit: sec ;no char
in buff, or error
ret

;***************************************************
;* Send data to keyboard
;* start bit sending
;
Kb_StartSend:
lds R16,Kb_BitCounter
dec R16
sts Kb_BitCounter,R16
cpi R16,2
breq SendParitas
cpi R16,1
breq SendStopbit
cpi R16,0
breq GetAckBit

lds R16,kb_SendByte
lds R2,Kb_Paritas
ror R16
sts kb_SendByte,R16
brcs send1bit
CBI PS2_DATPort,KDATA ;send
bit 0
inc R2
rjmp kb_sendbitx
send1bit:
SBI PS2_DATPort,KDATA ;send
bit 1
kb_sendbitx: ;
uj adatbit a porton
sts Kb_Paritas,R2 ;uj
paritas eltarolasa
ret

;**************************************
;* Paritas bit kuldese
SendParitas:
lds R16,Kb_Paritas
ror R16
brcc send1paritas
CBI PS2_DATPort,KDATA ;send
bit 0
ret
send1paritas:
SBI PS2_DATPort,KDATA ;paritas
bit = 1
ret

;***************************************
;* Stop bit kuldese
;
SendStopbit:
CBI PS2_DATPort,KDATA
CBI PS2_DATDIR,KDATA ;DATA pin tre-
stated external pull-up!!
ret

;**************************************
;* Get Ack bit from keyboard
;
GetAckBit:
ldi R16,11 ;1 start
+8 adat +1 par +1 stop
sts Kb_BitCounter,R16 ;a kovetkezo
adat vetelehez

ldi R16,Low(Kb_Rec_Start) ;Vissza allunk

adat vetelre
sts PtrINT0+0,R16
ldi R16,High(Kb_Rec_Start)
sts PtrINT0+1,R16

bld R16,0 ;R16=ack bit

tst R16
brne Kb_SendAckErr
ret
Kb_SendAckErr:
;ide jon az az eset amikor nem kuldott ack-ot
;es amost mit kezdjek vele, kuldjem ujra az
egeszet???
ret

;***************************************************
;** Parancskuldes kezdemenyezese a keyboard fele
;** In : R0 data to keyboard
;** Out: c=0 sikeres kuldes meginidtasa
;** c=1 sikertelen kuldes

TrySendCmd:
lds R2,kb_ComStat ;Stop tilalom
van-e?
tst R2
breq TrySend
sec
NormalUzem: ret

TrySend:
sts jumptabla+0,ZL
sts jumptabla+1,ZH
sts kb_CmdBuffer+0,R16
sts kb_CmdBuffer+1,R17
sts kb_CmdBuffer+2,R18

ldi R16,0x33
sts kb_Status,R16
clr R16
sts kb_lastAction,R16 ;0. byte kuldese
lesz
NewParam:
clr R16
sts kb_ResendCnt,R16

NextComdData:
clr R16
lds R2,kb_lastAction ;a kovetkezo
byte kuldese
ldi ZL,low(kb_CmdBuffer)
ldi ZH,high(kb_CmdBuffer)
add ZL,R2
adc ZH,R16

ld R0,Z
sts kb_SendByte,R0

in R16,GIMSK
andi R16,0b10111111
OUT GIMSK,R16 ;6. = 0 EXT INT0
inactive
;hogy ne
okozzunk megszakitas
;mikor
leallitjuk a CLK vonalat

SBI PS2_CLKDIR,KCLK ;CLK push-pull

Low
nop

ldi ZL,low(wait100us/5)
ldi ZH,high(wait100us/5) ;100us idozito
konstans
w100us: nop ;[1]
sbiw ZL,1 ;[2]
brne w100us ;[2]

nop ;itt mart eszre

kellett vegye
;hogy adni
akarunk
ldi R16,Low(Kb_StartSend) ;Most parancs
kuldes lesz
sts PtrINT0+0,R16
ldi R16,High(Kb_StartSend)
sts PtrINT0+1,R16

ldi R16,3
sts kb_ComStat,R16 ;Stop tilalom
lesz az adas allat...

ldi R16,11 ;1 start +8 adat

+1 par +1 stop +1 ack
sts Kb_BitCounter,R16

clr R16
sts Kb_Paritas,R16 ;paritas
szamolashoz kell

SBI PS2_DATDIR,KDATA ;DATA pin push-

pull low
nop
CBI PS2_CLKDIR,KCLK ;CLK tre-state
ismet

ldi R16,64 ;INT0 IRQ flag

torlese
out GIFR,R16

in R16,GIMSK
ori R16,64
OUT GIMSK,R16 ;6. = 1 EXT INT0
ujra aktive

clc
ret

;jump tablak

;**********************
;* Reset keyboard
;* In: R17,R18,R19 parameter ahol kell
;* Out: status
;
kb_CMD_Reset:
ldi R16,KEYBOARD_RESET
kb_CMD_single: ldi ZL,low(Egyvalasz)
ldi ZH,high(Egyvalasz)
rjmp TrySendCmd

kb_CMD_ALLMakeBrake:
ldi R16,SET_ALL_TYPEMATIC_MAKE_BREAK
ldi ZL,low(CsakACKkell)
ldi ZH,high(CsakACKkell)
rjmp TrySendCmd

kb_CMD_Echo:
ldi R16,KEYBOARD_ECHO
ldi ZL,low(StoreResult)
ldi ZH,high(StoreResult)
rjmp TrySendCmd

kb_CMD_SetLEDs:
andi R17,0b00111111 ;csak az
also 6 bit kell -> 6 LEDek
lds R16,kb_SWStatus
andi R16,0b11000000
or R16,R17
sts kb_SWStatus,R16
ldi R16,SET_KEYBOARD_INDICATORS
param1: ldi ZL,low(EgyParameter)
ldi ZH,high(EgyParameter)
rjmp TrySendCmd

kb_CMD_SetSpeed:
ldi R16,SET_KEYBOARD_TYPEMATIC
rjmp param1

kb_CMD_ReadID:
ldi R16,READ_KEYBOARD_ID
ldi ZL,low(ketparamjon)
ldi ZH,high(ketparamjon)
rjmp TrySendCmd

;
*************************************************************
;* subrutinok a keyboard parancsok vegrehajtasahoz
;
CsakACKkell:
cpi R16,ACKNOWLEDGE
ldi R16,ST_Success
breq StoreResult
ldi R16,ST_Unsuccess
rjmp StoreResult

Egyvalasz: cpi R16,ACKNOWLEDGE

breq nyugtamegjott

ldi R16,ST_ACKnotreseived
StoreResult:
ldi ZL,low(NormalUzem)
ldi ZH,high(NormalUzem)
sts jumptabla+0,ZL
sts jumptabla+1,ZH

Alaphelyzebe: sts kb_Status,R16

ldi R16,255
sts kb_lastAction,R16 ;vissza anormal
mukodesre
clr R16
sts kb_ComStat,R16 ;Stop tilalom
feloldva!
ret

nyugtamegjott:
ldi ZL,low(StoreResult)
ldi ZH,high(StoreResult)
sts jumptabla+0,ZL
sts jumptabla+1,ZH
ret

EgyParameter:
cpi R16,ACKNOWLEDGE
breq Elsonyugtaok
ldi R16,ST_ACKnotreseived
rjmp StoreResult
Elsonyugtaok:
lds R16,kb_lastAction ;a kovetkezo
byte kuldese
inc R16
sts kb_lastAction,R16
ldi ZL,low(CsakACKkell)
ldi ZH,high(CsakACKkell)
sts jumptabla+0,ZL
sts jumptabla+1,ZH
rjmp NewParam

ketparamjon:
sts kb_Status+1,R16
rjmp nyugtamegjott

http://avr-asm.tripod.com/kbdps2.html (1 of 2)1/20/2009 9:13:24 PM

16 BIT MATH (AVR 202)

Programming the AVR Microcontrollers in Machine Language

AVR
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected

from Avr) Jump to: navigation, search The AVRs are a family of
RISC microcontrollers from Atmel. Their internal architecture was
conceived by two students: Alf-Egil Bogen and Vegard Wollan, at
the Norwegian Institute of Technology (NTH] and further
developed at Atmel Norway, a subsidiary founded by the two
architects. Atmel recently released the Atmel AVR32 line of
microcontrollers. These are 32-bit RISC devices featuring SIMD
and DSP instructions, along with many additional features for
audio and video processing, intended to compete with ARM
based processors. Note that the use of "AVR" in this article
refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced Virtual
RISC. It's also rumoured to stand for the company's founders: Alf
and Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory
and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2
Development 3 Features 4 Footnotes 5 See also 6 External Links
6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3
Machine Language Development 6.4 C Language Development
6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7
Other AVR Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit] Program
Memory Program instructions are stored in semi-permanent
Flash memory. Each instruction for the AVR line is either 16 or 32
bits in length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the naming
of the device itself. For instance, the ATmega64x line has
64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-001F16)
followed by the 64 I/O registers (002016-005F16). The actual
usable RAM starts after both these sections (address 006016).
(Note that the I/O register space may be larger on some more
extensive devices, in which case memory mapped I/O registers
will occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for register
file and I/O register access, all can still be addressed and
manipulated as if they were in SRAM. [edit] EEPROM Almost all
devices have on-die EEPROM. This is most often used for long-
term parameter storage to be retrieved even after cycling the
power of the device. [edit] Program Execution Atmel's AVRs have
a single level pipeline design. The next machine instruction is
fetched as the current one is executing. Most instructions take
just one or two clock cycles, making AVRs relatively fast among
the eight-bit microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The AVR
instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular: Pointer
registers X, Y, and Z have addressing capabilities that are
different from each other. Register locations R0 to R15 have
different addressing capabilities than register locations R16 to
R31. I/O ports 0 to 31 have different addressing capabilities than I/
O ports 32 to 63. CLR affects flags, while SER does not, even
though they are complementary instructions. CLR set all bits to
zero and SER sets them to one. (Note though, that neither CLR
nor SER are native instructions. Instead CLR is syntactic sugar
for [produces the same machine code as] EOR R,R while SER is
syntactic sugar for LDI R,$FF. Math operations such as EOR
modify flags while moves/loads/stores/branches such as LDI do
not.) [edit] Speed The AVR line can normally support clock
speeds from 0-16MHz, with some devices reaching 20MHz. Lower
powered operation usually requires a reduced clock speed. All
AVRs feature an on-chip oscillator, removing the need for
external clocks or resonator circuitry. Because many operations
on the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due to
the free and inexpensive development tools available, including
reasonably priced development boards and free development
software. The AVRs are marketed under various names that
share the same basic core but with different peripheral and
memory combinations. Some models (notably, the ATmega
range) have additional instructions to make arithmetic faster.
Compatibility amongst chips is fairly good. See external links for
sites relating to AVR development. [edit] Features Current AVRs
offer a wide range of features: RISC Core Running Many Single
Cycle Instructions Multifunction, Bi-directional I/O Ports with
Internal, Configurable Pull-up Resistors Multiple Internal
Oscillators Internal, Self-Programmable Instruction Flash Memory
up to 256K In-System Programmable using ICSP, JTAG, or High
Voltage methods Optional Boot Code Section with Independent
Lock Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/
Asynchronous Serial Peripherals (UART/USART) (As used with
RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed
hardware & Hub controller with embedded AVR. Also freely
available low-speed (HID) software emulation Ethernet Controller
Support Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD Controller
Support 10-Bit A/D Converters, with multiplex of up to 16
channels Brownout Detection Watchdog Timer (WDT) Low-
voltage Devices Operating Down to 1.8v Multiple Power-Saving
Sleep Modes picoPower Devices Atmel AVR assembler
programming language Atmel AVR machine programming
language Atmel AVR From Wikipedia, the free encyclopedia
(Redirected from Avr) Jump to: navigation, search The AVRs are
a family of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen and
Vegard Wollan, at the Norwegian Institute of Technology (NTH]
and further developed at Atmel Norway, a subsidiary founded by
the two architects. Atmel recently released the Atmel AVR32 line
of microcontrollers. These are 32-bit RISC devices featuring SIMD
and DSP instructions, along with many additional features for
audio and video processing, intended to compete with ARM
based processors. Note that the use of "AVR" in this article
refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced Virtual
RISC. It's also rumoured to stand for the company's founders: Alf
and Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory
and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2
Development 3 Features 4 Footnotes 5 See also 6 External Links
6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3
Machine Language Development 6.4 C Language Development
6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7
Other AVR Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit] Program
Memory Program instructions are stored in semi-permanent
Flash memory. Each instruction for the AVR line is either 16 or 32
bits in length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the naming
of the device itself. For instance, the ATmega64x line has
64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-001F16)
followed by the 64 I/O registers (002016-005F16). The actual
usable RAM starts after both these sections (address 006016).
(Note that the I/O register space may be larger on some more
extensive devices, in which case memory mapped I/O registers
will occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for register
file and I/O register access, all can still be addressed and
manipulated as if they were in SRAM. [edit] EEPROM Almost all
devices have on-die EEPROM. This is most often used for long-
term parameter storage to be retrieved even after cycling the
power of the device. [edit] Program Execution Atmel's AVRs have
a single level pipeline design. The next machine instruction is
fetched as the current one is executing. Most instructions take
just one or two clock cycles, making AVRs relatively fast among
the eight-bit microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The AVR
instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular: Pointer
registers X, Y, and Z have addressing capabilities that are
different from each other. Register locations R0 to R15 have
different addressing capabilities than register locations R16 to
R31. I/O ports 0 to 31 have different addressing capabilities than I/
O ports 32 to 63. CLR affects flags, while SER does not, even
though they are complementary instructions. CLR set all bits to
zero and SER sets them to one. (Note though, that neither CLR
nor SER are native instructions. Instead CLR is syntactic sugar
for [produces the same machine code as] EOR R,R while SER is
syntactic sugar for LDI R,$FF. Math operations such as EOR
modify flags while moves/loads/stores/branches such as LDI do
not.) [edit] Speed The AVR line can normally support clock
speeds from 0-16MHz, with some devices reaching 20MHz. Lower
powered operation usually requires a reduced clock speed. All
AVRs feature an on-chip oscillator, removing the need for
external clocks or resonator circuitry. Because many operations
on the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due to
the free and inexpensive development tools available, including
reasonably priced development boards and free development
software. The AVRs are marketed under various names that
share the same basic core but with different peripheral and
memory combinations. Some models (notably, the ATmega
range) have additional instructions to make arithmetic faster.
Compatibility amongst chips is fairly good. See external links for
sites relating to AVR development. [edit] Features Current AVRs
offer a wide range of features: RISC Core Running Many Single
Cycle Instructions Multifunction, Bi-directional I/O Ports with
Internal, Configurable Pull-up Resistors Multiple Internal
Oscillators Internal, Self-Programmable Instruction Flash Memory
up to 256K In-System Programmable using ICSP, JTAG, or High
Voltage methods Optional Boot Code Section with Independent
Lock Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/
Asynchronous Serial Peripherals (UART/USART) (As used with
RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed
hardware & Hub controller with embedded AVR. Also freely
available low-speed (HID) software emulation Ethernet Controller
Support Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD Controller
Support 10-Bit A/D Converters, with multiplex of up to 16
channels Brownout Detection Watchdog Timer (WDT) Low-
voltage Devices Operating Down to 1.8v Multiple Power-Saving
Sleep Modes picoPower Devices Atmel AVR assembler
programming language Atmel AVR machine programming
language Atmel AVR From Wikipedia, the free encyclopedia
(Redirected from Avr) Jump to: navigation, search The AVRs are
a family of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen and
Vegard Wollan, at the Norwegian Institute of Technology (NTH]
and further developed at Atmel Norway, a subsidiary founded by
the two architects. Atmel recently released the Atmel AVR32 line
of microcontrollers. These are 32-bit RISC devices featuring SIMD
and DSP instructions, along with many additional features for
audio and video processing, intended to compete with ARM
based processors. Note that the use of "AVR" in this article
refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced Virtual
RISC. It's also rumoured to stand for the company's founders: Alf
and Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory
and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2
Development 3 Features 4 Footnotes 5 See also 6 External Links
6.1 Atmel Official Links 6.2 AVR Forums & Discussion Groups 6.3
Machine Language Development 6.4 C Language Development
6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7
Other AVR Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit] Program
Memory Program instructions are stored in semi-permanent
Flash memory. Each instruction for the AVR line is either 16 or 32
bits in length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the naming
of the device itself. For instance, the ATmega64x line has
64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-001F16)
followed by the 64 I/O registers (002016-005F16). The actual
usable RAM starts after both these sections (address 006016).
(Note that the I/O register space may be larger on some more
extensive devices, in which case memory mapped I/O registers
will occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for register
file and I/O register access, all can still be addressed and
manipulated as if they were in SRAM. [edit] EEPROM Almost all
devices have on-die EEPROM. This is most often used for long-
term parameter storage to be retrieved even after cycling the
power of the device. [edit] Program Execution Atmel's AVRs have
a single level pipeline design. The next machine instruction is
fetched as the current one is executing. Most instructions take
just one or two clock cycles, making AVRs relatively fast among
the eight-bit microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The AVR
instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular: Pointer
registers X, Y, and Z have addressing capabilities that are
different from each other. Register locations R0 to R15 have
different addressing capabilities than register locations R16 to
R31. I/O ports 0 to 31 have different addressing capabilities than I/
O ports 32 to 63. CLR affects flags, while SER does not, even
though they are complementary instructions. CLR set all bits to
zero and SER sets them to one. (Note though, that neither CLR
nor SER are native instructions. Instead CLR is syntactic sugar
for [produces the same machine code as] EOR R,R while SER is
syntactic sugar for LDI R,$FF. Math operations such as EOR
modify flags while moves/loads/stores/branches such as LDI do
not.) [edit] Speed The AVR line can normally support clock
speeds from 0-16MHz, with some devices reaching 20MHz. Lower
powered operation usually requires a reduced clock speed. All
AVRs feature an on-chip oscillator, removing the need for
external clocks or resonator circuitry. Because many operations
on the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due to
the free and inexpensive development tools available, including
reasonably priced development boards and free development
software. The AVRs are marketed under various names that
share the same basic core but with different peripheral and
memory combinations. Some models (notably, the ATmega
range) have additional instructions to make arithmetic faster.
Compatibility amongst chips is fairly good. See external links for
sites relating to AVR development. [edit] Features Current AVRs
offer a wide range of features: RISC Core Running Many Single
Cycle Instructions Multifunction, Bi-directional I/O Ports with
Internal, Configurable Pull-up Resistors Multiple Internal
Oscillators Internal, Self-Programmable Instruction Flash Memory
up to 256K In-System Programmable using ICSP, JTAG, or High
Voltage methods Optional Boot Code Section with Independent
Lock Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI) Synchronous/
Asynchronous Serial Peripherals (UART/USART) (As used with
RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed
hardware & Hub controller with embedded AVR. Also freely
available low-speed (HID) software emulation Ethernet Controller
Support Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD Controller
Support 10-Bit A/D Converters, with multiplex of up to 16
channels Brownout Detection Watchdog Timer (WDT) Low-
voltage Devices Operating Down to 1.8v Multiple Power-Saving
Sleep Modes picoPower Devices Atmel AVR assembler
programming language Atmel AVR machine programming
language

http://avr-asm.tripod.com/kbdps2.html (2 of 2)1/20/2009 9:13:24 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

AT KEYBOARD PROGRAM 128

HOME
RETRO_DAN
Below is some assembly code I wrote for the mega128
ASM FORUM last fall. It worked but has not been tested extensively. I did a look-up
ASM MATH table to give me a ASCII character for the
corresponding keyboard scan code.
TUTORIAL #1
TUTORIAL #2
TUTORIAL #3 ; Date: 9/26/03
; By: Stephen L. Nuttall
MATH 200 ; Hardware platform; STK500/STK501
MATH 200b ; Software platform: Atmel Studio 4.07
; File location: C:\My Documents\AVR Projects
MATH 201 \keyboard4a\keyboard4a.asm
MATH 202 ; Clock frequency: 3.6864MHz (via STK500 onboard
oscillator)
MATH 32X
;
MATH YX ;
; The purpose of this project is to:
DIV16 XX
; 1. Read a keyboard scan code using the keyboard
DIV 24 24 SCL and SDA lines
DIV 3216 ; 2. Determine if the scan code is 0xAA in which case
it will transmit
FLOAT 128 ; "Basic Assurance Test complete" via USART0
SQRT16 ; 3. Determine if the scan code is 0xF0, if it is not
it will look up and
MATH 202 ; transmit the equivalent ASCII code for that key
MATH 202 (in other words,
; if the key is held down it will keep
DEC ASCII
transmitting that ASCII character).
INT ASCII ; If it is 0xF0 then it will transmit the word
"Break" and then wait for
HX2ASC
; the next scan code
AVG8 222 ; 4. Only the alphabet and number keys are decoded in
FFT7 this code. The Ctrl, Alt,
; Shift, Enter, Function, etc. keys are not
COPY 102 decoded. Hitting one of those keys
LPM 108 ; will result in a capital letter or a "?" being
sent via the USART0. You can
EPROM 100 ; look at the table at the end of the code and get
SER EPROM an idea of what I mean.
;
DFLASH AT45
; This project will use code from previous projects as
FLASH CARD well as code
; from keyboard5.asm, keyboard5a.asm and keyboard5b.
VFX SMIL
asm.
VFX MEM ;
SORT 220 .nolist
.include "m128def.inc"
CRC 236 .list
XMODEM REC ;
.def temp = R16
UART 304 .def bitcntr = R17
UART 305 .def keydata = R18
.def temphi = R19
UART 128
.def templo = R20
UART BUFF .def flags = R21
USB 232 .def parity = R22
;
AVR ISP .org 0x0000
ISP 2313 jmp RESET ; Reset Handler

ISP 1200 .org 0x0046

AVR SPI
RESET: ; Main program start
I2C 300 ldi temp, high(RAMEND) ; Stack pointer = top
I2C 302 of internal SRAM
out SPH,temp
I2C TWI26
ldi temp, low(RAMEND)
I2C/TWI 128 out SPL,temp
I2C/TWI AT8 ser temp ; PortB =
out DDRB,temp ; all outputs
DALLAS-1W out PORTB,temp ; PortB LED's = off
DALLAS CRC ldi temp,0b11111100 ; PortD0 and PortD1 =
inputs, all
ETHNET 8019 out DDRD,temp ; other pins = output
TEA com temp ; temp now becomes
0b00000011
ADC 128 out PORTD,temp ; PortD0 and PortD1 have
ADC 10B pullups
; enabled, remaining pins
ADC 400
output 0's
ADC 401
THERM 232 ldi temphi,0x00 ; setup BAUD rate for
9600 @ 3.6864MHz
IRD 410 ldi templo,0x17
LCD HD44 sts UBRR0H,temphi ; "sts" is used because
UBRR0H is not within reach
LCD 2313 ; of "out"
LCD44 2313 out UBRR0L,templo ; UBRR0L is within reach
of "out"
KBD 240
MUX 242 ;
***********************************************************************************
KBD PS2
; USART
KBD PC/128 ; Frame format = 1 start bit, 8 data bits, no parity
PS2 EMU bit, 1 stop bit (8,N,1)
;
BOOT MG8 ; Registers UCSR0B and UCSR0C are already setup for
BOOT DR8 this Frame format at RESET.
;
ALM CLK ; No programming action is required for the above
CLOCK 8564 registers...if any settings need
; to be changed I need to remember that UCSR0C cannot
90 DAYS
be accessed via the OUT
DELAYS ; instruction, use STS instead.
;
CALL ID
;
DTMF 314 ***********************************************************************************
PWM 6CH ;
init:
PWM 10K clr bitcntr ; initialize appropriate
ENCODE registers
clr keydata
STH-11 clr parity
ATMEL CORP clr flags
AVR
main:
BUTTERFLY call sclhi ; make sure SCL is high to
AVR BOOK start off
call scllo ; look for SCL going low
inc bitcntr
cpi bitcntr,0x01 ; is this a Start bit?
breq startbit ; yes, go check Start bit
cpi bitcntr,0x0A ; is this a Data bit?
brlt databit ; yes, go get Data bit
breq paritybit ; no, go get and calculate
parity
cpi bitcntr,0x0B ; is this a Stop bit
breq stopbit ; yes, go check Stop bit

startbit:
sbic PIND,PD1 ; Start bit = 0?
rjmp starterr ; no...go send error message
rjmp main ; yes..go look for data bits

databit:
bclr 0 ; pre-clear Carry flag
sbic PIND,PD1 ; SDA = 0?
bset 0 ; no, then set Carry flag
brbc 0,rotate ; now check status of Carry
flag for parity chk
in flags,SREG ; save
push flags ; status register
inc parity ; for parity check later
pop flags ; restore
out SREG,flags ; status register
rotate:
ror keydata ; rotate contents of
Carry flag into keydata
rjmp main ; go get another bit
;
; Parity checking.....
; this routine is based on Odd Parity; meaning if there
are an even number of 1's
; in the data byte the Parity bit will be 1 so that an
odd number of 1's now exist,
; if there are already an odd number of 1's then the
Parity bit will be 0.
;
; I will keep track of Parity by incrementing the
parity register once for every 1
; that is received on the data line. If there are an
odd number of 1's the lsb of
; parity register will always be 1
;
; Therefore, if the lsb of the parity register = 1 (odd
number of 1's) then the
; Parity bit should be 0 (there were an odd number of
1's already. This condition
; can be checked by exclusive ORing those 2 bits. As
long as they are opposite
; the parity checks out good.
;
paritybit:
in flags,PIND ; SDA = PD1
ror flags ; rotate SDA into bit 0
position
andi flags,0x01 ; clear all but bit 0
position
andi parity,0x01 ; again, clear all but
bit 0
eor flags,parity ; exclusive-or to find
out if lsb's of flags
; and parity the same
breq parerr ; report error if they are
the same
rjmp main ; return and get stop bit now

stopbit:
sbis PIND,PD1 ; SDA = 1?
rjmp stoperr ; no, go report error
cpi keydata,0xAA ; BAT message from
keyboard?
brne chkforbrkcode ; no, check for next code
of interest
ldi ZH,high(2*batmsg) ; pre-load BAT message
address
ldi ZL,low(2*batmsg)
call sendmsg ; go send message
rjmp init ; go look for another key
press

chkforbrkcode:
cpi keydata,0xF0 ; Break code (0xF0):?
brne sendkeychar ; no, go send ASCII key
code
ldi ZH,high(2*brkmsg) ; yes, now pre-load
Break message address
ldi ZL,low(2*brkmsg)
call sendmsg ; go send message
rjmp init ; look for another keypress

starterr:
ldi ZH,high(2*sterrmsg) ; load high part of
message address in ZH
ldi ZL,low(2*sterrmsg) ; load low part of
message address in ZL
call senderrmsg

parerr:
ldi ZH,high(2*parerrmsg); load high part of
message address in ZH
ldi ZL,low(2*parerrmsg) ; load low part of
message address in ZL
call senderrmsg

stoperr:
ldi ZH,high(2*sperrmsg) ; load high part of
message address in ZH
ldi ZL,low(2*sperrmsg) ; load low part of
message address in ZL
call senderrmsg

;********* Subroutines **************

scllo:
sbic PIND,PD0 ; PD0(SCL) = 0?
rjmp scllo ; no...continue checking SCL
ret ; yes...return main program

sclhi:
sbis PIND,PD0 ; PD0(SCL) = 1?
rjmp sclhi ; no...continue checking SCL
ret ; yes..return to main
program

getsda:
bclr 0 ; pre-clear the Carry flag
sbic PIND,PD1 ; check state of SDA
bset 0 ; if SDA = 1, set Carry flag
ret ; if SDA = 0. Carry flag is
already cleared

;
******************************************************************************
senderrmsg:
; the calling program will have to load ZH and ZL with
the appropriate message
; address

sbi UCSR0B,TXEN0 ; enable transmitter,

TXEN = 1
getmsg:
lpm R0,Z+ ; retrieve character from
program memory
tst R0 ; is it the last
character?
breq loop ; yes..then loop forever
out UDR0,R0 ; no...transmit
character
call chkxmitend ; wait for transmit to
finish
rjmp getmsg ; get next character

loop:
cbi UCSR0B,TXEN0 ; disable transmitter
rjmp loop ; program stops here when
error occurs, user
; will have to reset the
STK500 and try again

;
******************************************************************************
sendmsg:
; the calling program will have to load ZH and ZL with
the appropriate message
; address

sbi UCSR0B,TXEN0 ; enable transmitter,

TXEN = 1
getmsg1:
lpm R0,Z+ ; retrieve character from
program memory
tst R0 ; is it the last
character?
breq continue ; yes..then loop forever
out UDR0,R0 ; no...transmit
character
call chkxmitend ; wait for transmit to
finish
rjmp getmsg1 ; get next character
continue:
cbi UCSR0B,TXEN0 ; disable transmitter
ret

;
******************************************************************************
sendkeychar:

sbi UCSR0B,TXEN0 ; enable transmitter,

TXEN = 1

ldi ZH,high(2*ascii) ; load high part of key

character address in ZH
ldi ZL,low(2*ascii) ; load low part of key
character address in ZL
add ZL,keydata ; add keydata offset to
ZL register
brcc getchar ; if no carry, load key
character in R0
inc ZH ; if there is a carry,
increment ZH register

getchar:
lpm ; load appropriate key
character into R0
out UDR0,R0 ; no...transmit
character
call chkxmitend ; wait for transmit to
finish
cbi UCSR0B,TXEN0 ; disable transmitter
ret

;
******************************************************************************

chkxmitend:
sbis UCSR0A,UDRE0 ; data register empty flag
= 1
rjmp chkxmitend ; no...keep checking
ret ; yes..continue with program

;************* MESSAGES
******************************************************

batmsg:
.db " Basic Assurance Test complete ",0

brkmsg:
.db " Break ",0

; ************* ERROR MESSAGES

************************************************

sterrmsg:
.db "Start Bit Error",0

parerrmsg:
.db "Parity Bit Error"
.db 0,0

sperrmsg:
.db "Stop Bit Error"
.db 0,0

; ************ KEY CHARACTERS

************************************************

ascii:
; 0x00 - 0x0F
.db
'?','F','?','F','F','F','F','F','?','F','F','F','F','T','`','?'

; 0x10 - 0x1F
.db
'?','L','L','?','L','q','1','?','?','?','z','s','a','w','2','?'

; 0x20 - 0x2F
.db
'?','c','x','d','e','4','3','?','?','S','v','f','t','r','5','?'

; 0x30 - 0x3F
.db
'?','n','b','h','g','y','6','?','?','?','m','j','u','7','8','?'

; 0x40 - 0x4F
.db
'?',',','k','i','o','0','9','?','?','.','/','l',';','p','-','?'

; 0x50 - 0x5F
.db
'?','?',''','?','[','=','?','?','C','R','E',']','?','\','?','?'

; 0x60 - 0x6F
.db
'?','?','?','?','?','?','B','?','?','1','?','4','7','?','?','?'

; 0x70 - 0x7F
.db
'0','.','2','5','6','8','E','N','F','+','3','-','*','9','S','?'

; 0x80 - 0x83
.db '?','?','?','F'

Programming the AVR Microcontrollers in Machine Language

AVR
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected

from Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing,
intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still
be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
http://avr-asm.tripod.com/kbd128.html (1 of 2)1/20/2009 9:13:59 PM
16 BIT MATH (AVR 202)

indicated in the naming of the device itself. For instance, the

ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language

http://avr-asm.tripod.com/kbd128.html (2 of 2)1/20/2009 9:13:59 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

PS2 KEYBOARD EMULATOR FOR 8515

HOME
RETRO_DAN
;
ASM FORUM ***********************************************************************
ASM MATH ;*
;* Number : **.**
TUTORIAL #1
;* File Name :"Main.asm"
TUTORIAL #2 ;* Title :Keymatrix interface to AT PS/2
TUTORIAL #3 ;*
;* Date (Orig.) :2001.09.13.
MATH 200 ;* Date (Last) :2001.10.14.
MATH 200b ;* Version :1.1.0
;* Support telephone :+36-30-9541-658
MATH 201 ;* Support fax :+36-30-9809-372
MATH 202 ;* Support E-mail :info@vfx.hu
;* Target MCU :AT90S8515
MATH 32X
;*
MATH YX ;* DESCRIPTION
;* kezeli a kovetkezo eszkozoket:
DIV16 XX
;* - 84 key
DIV 24 24 ;* - 6 LED
DIV 3216 ;* - 16,11,11x Jacksly??
;* - PS/2 style interface to AT or MARGOR CP-01
FLOAT 128 ;*
SQRT16 ;* AT90S8515 PLCC Pin discriptions
;*
MATH 202 ;* ROW0 T0 (PB0) VCC
MATH 202 ;* ROW1 T1 (PB1) (PA0) AD0 D0
;* ROW2 AIN0 (PB2) (PA1) AD1 D1
DEC ASCII
;* ROW3 AIN1 (PB3) (PA2) AD2 D2
INT ASCII ;* ROW4 SS (PB4) (PA3) AD3 D3
;* LED3 * MOSI (PB5) (PA4) AD4 D4
HX2ASC
;* LED4 * MISO (PB6) (PA5) AD5 D5
AVG8 222 ;* LED5 * SCK (PB7) (PA6) AD6 D6
FFT7 ;* RESET (PA7) AD7 D7
;* LED0 RxD (PD0) ICP
COPY 102 ;* LED1 TxD (PD1) ALE
LPM 108 ;* KCLK INT0 (PD2) OC1B
;* KDATA INT1 (PD3) (PC7) A15 D8
EPROM 100 ;* LED2 (PD4) (PC6) A14 D9
SER EPROM ;* ROW5 OC1A (PD5) (PC5) A13 D10
;* ROW6 WR (PD6) (PC4) A12 D11
DFLASH AT45
;* ROW7 RD (PD7) (PC3) A11 D12
FLASH CARD ;* XTAL2 (PC2) A10 D13
;* XTAL1 (PC1) A9 D14
VFX SMIL
;* GND (PC0) A8 D15
VFX MEM ;*
SORT 220 ;* Quarc: f=3.6864 MHz (T=0.27126 us)
;*
CRC 236 ;
XMODEM REC ***********************************************************************
.include "8515def.inc"
UART 304
UART 305
UART 128
;**********************!!!!!!!!!!!!!!!!!!!!!!
UART BUFF ***************************
USB 232
;* R15 regisztert modositani tilos!
AVR ISP ;* Atjaro az interrupt rutinok es a foprogram kozott!!!!
ISP 2313 ; 0. = 1 ismetles kell a
bill.nyomas utan, Timer lejart
ISP 1200
AVR SPI
;**********************!!!!!!!!!!!!!!!!!!!!!!
I2C 300 ***************************
I2C 302
I2C TWI26
I2C/TWI 128 ;
I2C/TWI AT8 **************************************************************************
;* Const Def
DALLAS-1W .EQU BaudRate=23 ;23 - 9600
DALLAS CRC @3.6864MHz

ETHNET 8019 .EQU T0Freq=227 ;220

TEA @1.8432MHz/1024 = 50Hz
;184 @3.6864MHz/1024 = 50Hz
ADC 128 ;220 @7.3728MHz/1024 = 200Hz
ADC 10B ;227 @7.3728MHz/64 =
4000Hz/250us
ADC 400
ADC 401
THERM 232 ;238 @3.6864MHz/1024 = 200Hz
;250 @3.6864MHz/1024 = 600Hz
IRD 410
LCD HD44
.EQU ONESEC=200 ;for 1s
LCD 2313
LCD44 2313 .EQU FlashPeriod=1000 ;LEDek villogasi
periodusa ~250us egysegekben
KBD 240
MUX 242
;
KBD PS2
***************************************************************************
KBD PC/128 ;***** Hardware Abstraction Layer
PS2 EMU
.EQU DTLo_PORT = DDRA
BOOT MG8 .EQU DTHi_PORT =
BOOT DR8 DDRC ;2x8 bit adat port Pull-upos kell

ALM CLK
CLOCK 8564
.EQU Row0 = 0 ;PortB kiosztasa
90 DAYS
.EQU Row1 = 1
DELAYS .EQU Row2 = 2
.EQU Row3 = 3
CALL ID
.EQU Row4 = 4
DTMF 314 .EQU LED3 = 5 ;
PWM 6CH LED3
.EQU LED4 = 6 ;
PWM 10K LED4
ENCODE .EQU LED5 = 7 ;
LED5
STH-11
ATMEL CORP .EQU LED345 = PORTB
.EQU Row01234 = PORTB
AVR
BUTTERFLY
AVR BOOK .EQU LED0 = 0 ;PortD kiosztasa
LED0
.EQU LED1 = 1 ;
LED1
.EQU LED2 = 4 ;
LED2
.EQU Row5 = 5
.EQU Row6 = 6
.EQU Row7 = 7

.EQU LED012 = PORTD

.EQU Row567 = PORTD

;
******************************************************************************
;**** VARIABLES
.DSEG
Flag1: .BYTE 1 ;Flagbitek
;2 = paros/paratlan
szamlalo led villogtatashoz
;1:0 = scan mode 01 =
scan1, 10 = scan2, 11 = scan3

CNT1L: .BYTE 1
CNT1H: .BYTE 1 ;software Timer

CNT2L: .BYTE 1
CNT2H: .BYTE 1 ;LED villogtatas
freki

KeyHead: .BYTE 1 ;Bill. puffer eleje

KeyTrail:.BYTE 1 ;Bill. puffer vege

WTime: .BYTE 2 ;Bill.nyomas utan a

varakozas ido
WRep: .BYTE 2 ;Bill.nyomas utan a
ismetlesi ido

PS2Flag: .BYTE 1 ;PS2 flag csak az int.

rutin hasznalhatja
;3. = 1 Parameterre var,
komunikacio kozben vagyunk
;2. = 1 Request resend
;1. = 1 Resend last data to
host
;0. = 1 Send ACK

PS2NextA:.BYTE 2 ;PS2 program cim, ahova a

kovetkezo int ugrik
LastSend:.BYTE 1 ;PS2 Utoljara kuldott kod
RepChar: .BYTE 1 ;karakter sorszama amit
ismetelni kell

StatLEDs:.BYTE 2 ;STAUS LEDek allapota eg /

nem eg
;masodik byte a villogas
mask byte-ja

ParamErr:.BYTE 1 ;parameterre max 4ms ideig

var utana hiba

.EQU KeyBuffLen = 17
KeyBuff: .BYTE KeyBuffLen ;Transmit key-buffer

.EQU KeyCount = 128 ;max 128

bill.,de csak 119 db billenyut kell kezelni
Matrix: .BYTE KeyCount ;Keys
allapota

;
**************************************************************************************
.ESEG
.db "MAGOR HI-01 Keyboard-matrix Controller by
VFX. V1.1.0 [orig. 2001.09.16] "
.db "Last Upd. [2001.10.14] Info: info@vfx.hu
Data area>>"

;
*****************************************************************************
;**** I N T E R R U P T S
;****
;
*****************************************************************************
.CSEG
rjmp RESET ; Reset Handler
rjmp EXT_INT0 ; IRQ0 Handler
rjmp EXT_INT1 ; IRQ1 Handler
rjmp TIM1_CAPT ; Timer1 Capture Handler
rjmp TIM1_COMPA ; Timer1 CompareA Handler
rjmp TIM1_COMPB ; Timer1 CompareB Handler
rjmp TIM1_OVF ; Timer1 Overflow Handler
rjmp TIM0_OVF ; Timer0 Overflow Handler
rjmp SPI_INT ; SPI Transfer Complete
Handler
rjmp UART_RXC ; UART RX Complete Handler
rjmp UART_DRE ; UDR Empty Handler
rjmp UART_TXC ; UART TX Complete Handler
rjmp ACI_INT ; Analog Comparator Handler

;*********************
EXT_INT0: RETI
EXT_INT1: RETI
TIM1_CAPT: RETI
;************************
;* Key Deleay & Rep Time
;************************
TIM1_COMPA: PUSH ZL
IN ZL,SREG
PUSH ZL

ldd ZL,Y+WRep+1-RAMSTRT
out OCR1AH,ZL
ldd ZL,Y+WRep+0-RAMSTRT
out OCR1AL,ZL ;rep. timer
beallitasa
ldi ZL,1
or R15,Zl ;timer
lejart ismetles mehet Flag

POP ZL
OUT SREG,ZL
POP ZL
RETI
;**
TIM1_COMPB: RETI
TIM1_OVF: RETI

;*********************
;* RealTime Clock Int
;*********************
;*
TIM0_OVF: PUSH ZL
PUSH ZH
IN ZL,SREG
PUSH ZL

LDI ZL,T0Freq
OUT TCNT0,ZL ;Reload
Timer

LDD ZL,Y+CNT1L-RAMSTRT
LDD ZH,Y+CNT1H-RAMSTRT
OR ZL,ZH
BREQ TIM_01
LDD ZL,Y+CNT1L-RAMSTRT
SBIW ZL,1
STD Y+CNT1L-RAMSTRT,ZL
STD Y+CNT1H-RAMSTRT,ZH

TIM_01:
LDD ZL,Y+CNT2L-RAMSTRT
LDD ZH,Y+CNT2H-RAMSTRT
OR ZL,ZH
BREQ TIM_02
LDD ZL,Y+CNT2L-RAMSTRT
SBIW ZL,1
STD Y+CNT2L-RAMSTRT,ZL
STD Y+CNT2H-RAMSTRT,ZH

TIM_02: POP ZL
OUT SREG,ZL
POP ZH
POP ZL
RETI

;********************
;* SPI Int Handle
;********************
SPI_INT: RETI
UART_RXC: RETI
UART_DRE: RETI
UART_TXC: RETI
EPR_INT: RETI
ACI_INT: RETI

;
**********************************************************************
;* Iclude files

.include "keyb.asm"
.include "ps2.asm"
.include "EEprom.asm"

;
**********************************************************************
;* RESET
;
**********************************************************************
RESET: CLI ;GLOBAL INTERRUP
DIS.
clr R15 ;Flags!!!