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Verilog Lab 2012

EXPERIMENT NO. 1
AIM:
To write a VERILOG code for a master slave D-flip flop & simulate the code using Modelsim simulator.

Block Diagram & Schematic:-

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Verilog Lab 2012


FUNCTIONAL DESCRIPTION :A masterslave D flip-flop is created by connecting two gated D latches in series, and inverting the enable input to one of them. It is called masterslave because the second latch in the series only changes in response to a change in the first (master) latch. VERILOG CODE : Module for D Flipflip module dff(d,clk,rst, q,qbar); input d,clk,rst; output q,qbar; reg q,qbar; always @(posedge clk or negedge rst) begin if(!rst) begin q<=0; qbar<=0; end else q<=d; end endmodule
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Verilog Lab 2012

Module for Master Slave D Flipflop module mslave_dff(d,clk,rst, q,qbar); input d,clk,rst; output q,qbar; wire q1,qbar1; dff dff1(d,clk,rst,q1,qbar1); dff dff2(q1,~clk,rst,q,qbar); endmodule

WAVEFORM:-

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Verilog Lab 2012


EXPERIMENT NO. 2

AIM:To write a verilog code for 8:1 Multiplexer and simulate the code using Modelsim simulator.

Block Diagram and Schematic:-

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Verilog Lab 2012

FUNTIONAL DESCRIPTION:A multiplexer (or MUX) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line.A multiplexer of 2 n inputs has n select lines, which are used to select which input line to send to the output.A multiplexer is also called a data selector.

VERILOG CODE: Module for 8:1 Multiplexer

module mux_8(a, sel, y); input [7:0] a; input [2:0] sel; output y; assign y =sel[2]?(sel[1]?(sel[0]?a[7]:a[6]):(sel[0]?a[5]:a[4])):(sel[1]?(sel[0]?a[3]:a[2]):(sel[ 0]?a[1]:a[0])); endmodule

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Verilog Lab 2012

WAVEFORM:-

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Verilog Lab 2012


EXPERIMENT NO. 3

AIM: To write a VERILOG code for an 8-bit Synchronous Counter with LOAD, RESET & up/down controls & simulate the code using Modelsim Simulator.

Block Diagram and Schematic: -

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Verilog Lab 2012


FUNCTIONAL DESCRIPTION:An 8-bit synchronous counter with up-down control is basically used to count either up or down(i.e. from 0 to 255 or 255 to 0) using a single clock for each flip flop. There are 4 input signals clock, load, reset & updown. The clock signal provides the synchronous operation. The load signal is used to start the count operation i.e. when it is active high the counter will count otherwise the output loads the present count value. When the reset signal is active high then the output is zero & the counter will start to operate only when reset is made active low. The updown control is used to select the count up or count down operation. The count value is stored in an 8 bit output register out

VERILOG CODE: Module for synchronous counter module count(out,data,load,reset,clk); output[7:0] out; input[7:0] data; input load,clk,reset; reg[7:0] out; always @(posedge clk) begin if (!reset) out = 8'h00;
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else if (load) out = data;


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Verilog Lab 2012


else out = out + 1; end endmodule

WAVEFORM:-

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Verilog Lab 2012


EXPERIMENT NO. 4

AIM:To write a verilog code for 8 bit parity checker & generator and simulate the code using Modelsim simulator.

Block Diagram and schematic:-

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Verilog Lab 2012


FUNCTIONAL DESCRIPTION:A parity bit is used for the purpose of detecting errors during transmission of binary information. A parity bit is an extra bit included with a binary message to make the number of 1s either odd or even. The message including the parity bit is transmitted and then checked at the receiving end for errors. An error is detected if the checked parity does not correspond with the one transmitted. The circuit that generates the parity bit in the transmitter is called a parity generator and the circuit that checks the parity in the receiver is called a parity checker. In even parity the added parity bit will make the total number of 1s an even amount and in odd parity the added parity bit will make the total number of 1s an odd amount.

VERILOG CODE: Module for parity checker and generator module parity_checker8(a, y); input [7:0] a; output [8:0] y; reg [8:0]y; reg even=0; reg odd=1; integer i,count; always @(a) begin count<=0;
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Verilog Lab 2012


for(i=0;i<=7;i=i+1) begin if(a[i]==1) count<=count+1; end if(count%2==0) begin y<={even,a}; $display("even parity"); end else begin y<={odd,a}; $display("odd parity"); end end endmodule

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Verilog Lab 2012

WAVEFORM:-

(i) Parity checker

(ii) parity generator waveform

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Verilog Lab 2012

EXPERIMENT NO. 5

AIM:To write a verilog code for 4 digit decade counter and simulate the code using Modelsim simulator.

Block Diagram and schematic :-

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Verilog Lab 2012

FUNCTIONAL DESCRIPTION:The decade counter is known as a mod-counter when it counts to ten (0, 1, 2, 3, 4, 5, 6, 7, 8, 9).

VERILOG CODE : Module for Decade Counter module decade_counter(clk,rst, q); input clk,rst; output [3:0]q; reg [3:0]q; always @(posedge clk) begin if ((rst==1'b1) && (q<4'b1001) ) q=q+1; else q=4'b0000; end endmodule

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Verilog Lab 2012

WAVEFORM:-

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Verilog Lab 2012

EXPERIMENT NO. 6

AIM: To write a VERILOG code for a 4-bit combinational multiplier & simulate the code using Modelsim simulator.

Block Diagram and schematic:-

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Verilog Lab 2012

FUNCTIONAL DESCRIPTION:A combinational multiplier is a circuit which is used to multiply two 4-bit unsigned numbers and give the result as an 8-bit number. It is possible to construct a 4x4 combinational multiplier from an array of AND gates, half-adders and full-adders.

VERILOG CODE: Module for half_adder module half_adder1(a, b, s, cout); input a,b; output s,cout; assign s= a^b; assign cout =a&b; endmodule
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Verilog Lab 2012

Module for full adder module full_adder1(a, b, cin, sum, cout); input a,b,cin; output sum,cout; assign sum= a^b^cin; assign cout= (a&b)|(a&cin)|(b&cin); endmodule

Module for 4 bit combinational multiplier module combmul_4bit(m,a,b); input [3:0]a,b; output [7:0]m; wire w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13,w14,w15; wire s1,s2,s3,s4,s5,s6; wire c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11; assign m[0]= a[0]&b[0]; assign w1=a[1]&b[0]; assign w2=a[0]&b[1]; assign w3=a[0]&b[2]; assign w4=a[1]&b[1]; assign w5=a[2]&b[0];
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Verilog Lab 2012


assign w6=a[0]&b[3]; assign w7=a[1]&b[2]; assign w8=a[2]&b[1]; assign w9=a[3]&b[0]; assign w10=a[1]&b[3]; assign w11=a[2]&b[2]; assign w12=a[3]&b[1]; assign w13=a[2]&b[3]; assign w14=a[3]&b[2]; assign w15=a[3]&b[3]; half_adder1 h1(w1,w2,m[1],c1); half_adder1 h2(w3,w4,s1,c2); half_adder1 h3(w6,w7,s2,c3); full_adder1 h4(w10,w11,c3,s3,c4); full_adder1 h5(c1,s1,w5,m[2],c5); full_adder1 h6(c2,s2,w8,s4,c6); full_adder1 h7(c6,s3,w12,s5,c7); full_adder1 h8(c4,w13,w14,s6,c8); full_adder1 h9(c5,s4,w9,m[3],c9); half_adder1 h10(c9,s5,m[4],c10); full_adder1 h11(c7,c10,s6,m[5],c11); full_adder1 h12(c11,c8,w15,m[6],m[7]);
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Verilog Lab 2012


endmodule

WAVEFORM:-

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Verilog Lab 2012


EXPERIMENT NO.7

AIM :To write a verilog code for 4-bit sequential multiplier and simulate the code using Modelsim simulator .

Block Diagram and Schematic:-

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Verilog Lab 2012


FUNCTIONAL DESCRIPTION:To implement the sequential multiplier, we will use the Shift-and-Add algorithm. A sequential multiplier requires some additional signals for synchronization purpose. Input clk: clock signal to synchronize the system. Input reset: asynchronous reset signal to initialize the system. Input start: synchronous signal that must be high to start a new operation. Output done: synchronous signal that is set during 1 cycle by the multiplier when the result of the operation is available.

VERILOG CODE : Module for sequentional multiplier

module sequential_mul(a,b, clk, prod); input [3:0]a,b; input clk; output [7:0]prod; reg [7:0]prod; reg [7:0]ans; integer i; integer recode; initial begin
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Verilog Lab 2012


prod=8'b0; ans=8'b0; end always@(posedge clk) begin prod=8'b0; for(i=1;i<=3;i=i+2) begin if(i==1) recode=b[0]-b[1]-b[1]; else recode=b[i-1]+b[i-2]-b[i]-b[i]; case(recode) 1: begin ans=a; ans=ans<<(i-1); prod=prod+ans; end 2: begin ans=a<<1; ans=ans<<(i-1); prod=prod+ans; end -1:begin ans=~a+1; ans=ans<<(i-1); prod=prod+ans;
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Verilog Lab 2012


end -2: begin ans=a<<1; ans=~ans+1; ans=ans<<(i-1); prod=prod+ans; end endcase end end endmodule

WAVEFORM:-

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Verilog Lab 2012


EXPERIMENT NO. 8

AIM:To write a verilog code for PIPO and PISO type registers and simulate the code using Modelsim simulator.

Block Diagram and Schematic:-

(i) PIPO

(ii) PISO

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Verilog Lab 2012


FUNCTIONAL DESCRIPTION:The purpose of the parallel-in/ parallel-out shift register is to take in parallel data, shift it. A universal shift register is a do-everything device in addition to the parallel-in/ parallel-out function.

VERILOG CODE: Module for PIPO Shift register module pipo(y,a,clk); output [7:0]y; input clk; input [7:0]a; reg [7:0]y; always @(posedge clk) begin y<=a; end endmodule Module for PISO Shift register module piso(clk,rst,load,shift, set_data, data_out,eoc); input clk,rst,load,shift; input [7:0] set_data; output regdata_out,eoc; reg [7:0]sr;
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Verilog Lab 2012


integer count; always@(posedgeclk ) begin if (rst ==1) begin data_out<=1'b0; eoc<=1'b0; end else if(load ==1) begin sr<= set_data; count<= 8; data_out<=1'bz; eoc<=1'b0; end else if ((shift ==1)&& (count !=0)) begin sr<= sr>>1; data_out<=(sr[0]); count<= count -1; eoc<=1'b0; end else if ((shift ==1)&& (count ==0)) begin
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Verilog Lab 2012


data_out<=1'bz; eoc<=1'b1; end else; end endmodule

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Verilog Lab 2012

WAVEFORM:-

(i)

PIPO Waveform

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(ii)

PISO Waveform
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Verilog Lab 2012


EXPERIMENT NO. 9

AIM:To write a verilog code for SISO and SIPO & simulate the code using Modelsim simulator.

Block Diagram and schematic:-

(i)

Schematic for SISO


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Verilog Lab 2012

(ii)

Schematic for SIPO

FUNCTIONAL DESCRIPTION:Serial-in, serial-out shift registers delay data by one clock time for each stage. They will store a bit of data for each register. A serial-in, serial-out shift register may be one to 64 bits in length, longer if registers or packages are cascaded.

WAVEFORM :-

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(i) SISO Waveform


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Verilog Lab 2012

(ii)

SIPO Waveform

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