COMPUTER ARCHITECTURE Credit Units: 04 Course Objective: This course deals with computer architecture as well as computer organization

and design. Computer architecture is concerned with the structure and behaviour of the various functional modules of the computer and how they interact to provide the processing needs of the user. Computer organization is concerned with the way the hardware components are connected together to form a computer system. Computer design is concerned with the development of the hardware for the computer taking into consideration a given set of specifications. Course Contents: Module I: Register Transfer Language Register Transfer, Bus and Memory Transfers, Arithmetic Micro-operations, Logic Micro-operations, Shift Micro-operations, Arithmetic Logic shift Unit. Module II: Basic Computer Organizations and Design Instruction Codes, Computer Registers, Computer Instructions, Timing and Control, Instruction Cycle, Memory Reference Instructions, Input-Output and Interrupt, Design of Accumulator Logic. Hardwired and Micro programmed control: Control Memory, Address Sequencing, Design of Control Unit Module III: Central Processing Unit Introduction, General Register Organization, Stack Organization, Instruction representation, Instruction Formats, Instruction type, Addressing Modes, Data Transfer and Manipulation, Program Control, Reduced Instruction Set Computer RISC and CISC Computer Arithmetic: Introduction, Multiplication Algorithms, Division Algorithms, Floating-Point Arithmetic Operations Module IV: Memory and Intrasystem Communication and Input output organisation Memory: Memory types and organization Memory Hierarchy, Main Memory, Auxiliary Memory, Associative Memory, Cache Memory, Virtual Memory, Memory Management Hardware Intrasystem communication and I/O: Peripheral Devices, Input-Output Controller and I/O driver, IDE for hard disk, I/O port and Bus concept, Bus cycle, Synchronous and asynchronous transfer, Interrupt handling in PC, Parallel Port, RS 232 interface, Serial port in PC, Serial I/O interface, Universal serial bus IEEE 1394, Bus Arbitration Techniques, Uni-bus and multi-bus architectures EISA Bus, VESA Bus. Module V: Pipelining, Vector Processing and Multiprocessors Parallel Processing, Pipelining, Arithmetic Pipeline, Instruction Pipeline, RISC Pipeline, Vector Processing, Array Processors. Multiprocessors: Characteristics of Multiprocessors, Interconnection Structures, Interprocessor Arbitration, Interprocessor Communication and Synchronization, Advanced computer architecture, Pentium and Pentinum Pro, Power PC Architecture

Examination Scheme: Components Weightage (%) Text & References: CT 10 H 7

V/S/Q 8 Attendance 5

EE 70

Text: Morris Mano, Computer System Architecture, 3rd Edition 1999, Prentice-Hall of India Private Limited. Harry & Jordan, Computer Systems Design & Architecture, Edition 2000, Addison Wesley, Delhi. References: William Stallings, Computer Organization and Architecture, 4th Edition-2000, Prentice-Hall of India Private Limited. Kai Hwang-McGraw-Hill, Advanced Computer Architecture. Kai Hwang & Faye A Briggs, McGrew Hill, inc., Computer Architecture & Parallel Processing. John D. Carpinelli, Computer system Organization & Architecture, Edition 2001, Addison Wesley, Delhi John P Hayes, McGraw-Hill Inc, Computer Architecture and Organization. M. Morris Mano and Charles, Logic and Computer Design Fundamentals, 2nd Edition Updated, Pearson Education, ASIA. Hamacher, Computer Organization, McGraw hill. Tennenbaum, Structured Computer Organization, PHI B. Ram, Computer Fundamentals architecture and organization, New age International Gear C. w., Computer Organization and Programming, McGraw hill

COMPUTER ARCHITECTURE TUTORIAL - 1 Q1. Assuming 1024x16 memory model, calculate the size of a) PC b) AR c) IR d) DR e)AC Q2. Show the block diagram of the hardware that implements the following register transfer statement: Xyz: R2 R1, R1 R2. Q3. Draw the block diagram for the hard ware that implements the following statements X+YZ: AR AR+BR Q4. Explain the memory operation in each case a) R2 M[AR] b) M [AR] R3 c) R5 M [R5] Q5. A digital computer has a common bus system for 16 registers 32 bit each. The bus is constructed with MUX. a) How many selection bits are there in each MUX? b) What size of MUX are required c) How many multiplexers are there in the bus? Q6. Show the block diagram of the hardware that implements the following register transfer statements T0: R5 R0 T1: R5R1 T2: R5R2 T3: R5 R3 Note only one variable is equal to one at any given time Hint: use selection lines SO and S1 to select registers, S1= T2+ T3, SO= T1+ T3, Load = T0 +T1 + T2 + T3 Q7. Represent the following conditional control statements by two register transfer statements with control functions. If (P= 1 then (R1 R2) else if (Q = 1) then (R1 R3) Q8. Register A holds 8 bit binary 11011001. Determine the B operand and the logic operation to be performed in order to change the value in A to a. 01101101 b. 11111101 Q9. What is wrong with the following register transfer statements 1.xT:AR AR,AR 0 2.yT: R1 R2, R1 R3 3. zT:PC AR,PC PC+1

Q10. AR = 11110010,BR = 111111,CR = 10111001, DR= 11101010. What will value of register after sequence of micro operation? AR AR+BR, AR AR BR CR CRDR COMPUTER ARCHITECTURE TUTORIAL - 2 Q1. R = 11011101. What will be the value after logical left shift, logical right shift, Circular right shift, circular left shift. Q2. State with reasons, which statement is correct and which is wrong. (i) abT : R2 R1, R2 R3 (ii) abT : R2 R1,R3 R2 (iii) abT : R5 R2, R4 R2 (iv) abT : R2 R2 + R3, R3 R2 +R3 Q3 Consider the following register transfer statements for two 4-bit registers R1 and R2. xT :R1 R2 xT : R1 R2 Draw a complete block diagram showing the hardware implementation of the two statements. Use block diagram for the two 4-bit registers, a 4-bit adder, and a quadruple 2-to -1 line multiplexer that selects the inputs to R1. Q4. A computer uses a memory unit with 256k registers of 32 bits each. A binary instruction code is stored in one word of memory. The instruction has four parts, and indirect bit, an operation code, a register code part to specify one of the 64 registers and an address part. (a) How many bits are there in the operation code. The register code part. (b) Draw the instruction word format and indicate the number of bits in each part. (c) How many bits are there in data and address inputs of memory ? Q5. The content of the PC in the basic computer is 3AF. The content of AC is 7EC3. the content of memory at address 3AF is is 932E. the content of memory at address 32E is 09AC. The content of memory at address 9AC is 8B9F. a. What is the instruction that will fetched and executed next? b. Show the binary operation that will be performed in AC when the instruction is executed? c. Give the content of register PC,AR,DR,AC and IR in hexademical Q6. How many times does the control unit refers to the memory when it fetches and executes an indirect addressing mode instruction if the instruction is a) A computational type requiring an operand form memory b) A branch type Q7. What are the basic differences between a branch instruction, a call subroutine instruction a program interrupt? Q8. What are the two instructions needed in the basic computer in order to set the E flip-flop to 1?

Q9. Derive the Boolean logic expression for x2. Show that x2 can be generated with one AND and one OR gate. Q10. An output program resides in memory starting from address 2300. It is executed after the computer recognizes an interrupt when FGO becomes a 1 (While IEN = 1) a) What instruction must be placed at address 1? b) What must be the last two instructions of the output program?

COMPUTER ARCHITECTURE TUTORIAL - 3 Q1. Define the following. (i) Microoperation (ii) Tristate Buffer Q2. Explain the difference between microprogrammed control and hardwired control ? Q3. If a system uses a control memory of 1024 words of 32 bits each. The microndstruction field has three fields(microoperation, address, select). The microoperation field has 16 bits. a) How many bits are there in branch address field and select field b) For 16 status bits how many bits in branch logic are used to select a status bit? c) How many bits are left to select an input for MUX. Q4. The control memory has 4096 words of 24 bits each. How many bits are there in CAR? Q5. Explain how mapping from an instruction code to a microinstruction address can be done by means of a ROM. What is advantage of this method? Q6. Formulate a mapping procedure that provides eight consecutive microinstructions for each routine. The operation code ahs six bits and the control memory has 2048 words? Q7. Show how 9-bit microoperation field in a microinstruction can be divided in to subfields to specify 46 microoperations. How many microoperation can be specified in one microinstruction? Q8. Using the mapping procedure, give the first microinstruction address for the following operation code: a) 0010 b) 1011 c) 1111 Q9. What is the difference between a microprocessor and a microprogram? Q10. Why do we need the two multiplexers in the computer hardware configuration? Is there another way that information from multiple sources can be transferred to a common destination. COMPUTER ARCHITECTURE TUTORIAL - 4 Q1. A bus-organized CPU (Fig. 8-2) has 16 registers with 32 bits in each, an ALU and a destination decoder. (a) How many multiplexers are there in the A bus, and what is the size of each multiplexer? (b) How many selection inputs are needed for MUX A and MUX B? (c) How many inputs and outputs are there in the decoder?

(d) How many inputs and outputs are there in the ALU for data, including input and output carries? (e) Formulate a control word for the system assuming that the ALU has 35 operations. Q2. The bus system of Fig. 8-2 has the following propagation delay times: 30ns for the signals to propagate through the multiplexers, 80ns to perform the ADD operation in the ALU, 20ns delay in the destination decoder, and 10ns to clock the data into the destination register. What is the minimum cycle time that can be used for the clock? Q3. Specify the control word that must be applied to the processor of Fig. 8-2 to implement the following microoperations. (a) R1 R2 + R3 (b) R4 R4 (c) R5 R5 1 (d) R6 shl R1 (e) R7 input Q4. Convert the following numerical arithmetic expression into reverse Polish notation and show the stack operations for evaluating the numerical result. (3 + 4)[10(2 + 6) + 8] Q5. A computer has 32-bit instructions and 12-bit addresses. If there are 250 two-address instructions, how many one-address can be formulated? Q6. How many times does the control unit refer to memory when it fetches and executes an indirect addressing mode instruction if the instruction is (a) a computational type requiring an operand from memory; (b) a batch type. Q7. What must the address field of an indexed addressing mode instruction be to make it the same as a register indirect mode instruction? Q8. An instruction is stored at location 300 with its address field at location 301. The address filed has the value 400. A processor register R1 contains the number 200. Evaluate the effective address if the addressing mode of the instruction is (a) direct; (b) immediate; (c) relative; (d) register indirect; (e) index with R1 as the index register. Q9. Perform the logic AND, OR and XOR with the two binary strings 10011100 and 10101010.

Q10. What are the basic differences between a branch instruction, a call subroutine instruction, and program interrupt?

COMPUTER ARCHITECTURE TUTORIAL 5 Q1. Formulate a hardware procedure for detecting an overflow by comparing the sign of the sum with the signs of the augend and addend. The numbers are in signed-2s complement representation. Q2. Perform the operation (-9) + (-6) = -15 with binary numbers in signed-1s complement representation using only five bits to represent each number (including the sign). Show that the overflow detection procedure of checking the inequality of the last two carries fails in this case. Q3. Suggest a modified procedure for detecting an overflow when signed-1s complement numbers are used.

Q4. Derive an algorithm in flowchart form for adding and subtracting two fixed-point binary numbers when negative numbers are in signed-1s complement representation. Q5. Prove that the multiplication of two n-digit numbers in base r gives a product no more than 2n digits in length. Show that this statement implies that no overflow can occur in the multiplication operation. Q6. Show that adding E after the operation A + + 1 restores the original value of A. What should be done with the end carry? Q7. Q8. Q9. Q10. Q11. Why should the sign of the reminder after a division be the same as the sign of the dividend? Design an array multiplier that multiplies two 4-bit numbers. Use AND gates and binary adders. Derive an algorithm in flowchart form for the nonrestoring method of fixed-point binary division. Derive an algorithm for evaluating the square root of a binary fixed-point binary division. Show that there can be no mantissa overflow after a multiplication operation.

COMPUTER ARCHITECTURE TUTORIAL 6 Q1. a) How many 128 x 8 RAM chips are needed to provide a memory capacity of 2048 bytes? b) How many lines of the address bus must be used to access 2048 bytes of memory? How many of these lines will be common to all chips? c) How many lines must be decoded for chips select? Specify the size of the decoders. Q2. Describe in words and by means of a block diagram how multiple matched words can be read out from an associative memory. Q3. What additional logic is required to give a no-match result for a word in an associative memory when all key bits are zero? Q4. An 8-bit computer has a 16-bit address bus. The first 15 lines of the address are used to select a bank of 32K bytes of memory. The high order bit of the address is used to select a register which receives the contents of the data bus. Explain how this configuration can be used to extend the memory capacity of the system to 8 banks of 32 bytes each, for a total of 256K bytes of memory. Q5. An address space is specified by 24 bits and the corresponding memory space by 16 bits. a) How many words are there in the address space? b) How many words are there in the memory space? c) If a page consists of 2K words, how many pages and blocks are there in the system? Q6. The access time of a cache memory is 100 ns and that of main memory 1000 ns. It is estimated that 80 % of the memory requests are for read and the remaining 20% for write. The hit ratio for read access only is 0.9. A write through procedure is used.

a) What is the average access time of the system considering only memory read cycles? b) What is hit ratio taking into consideration the write cycles? Q7.Obtain the complement functions for match logic of one word in an associative memory. In other words, show that Mi` is the sum of exclusive OR functions. Draw the logic diagram for Mi and terminate it with an inverter to obtain Mi . Q8. What are the various techniques for data transformation from main memory to cache memory? Q9. Describe the methods for writing into cache memory. Q10. Explain the memory hierarchy in the computer system. COMPUTER ARCHITECTURE

Tutorial-7
1. A magnetic disk system has the following parameters: Ts= average time to position the magnetic head over a track R= rotation speed of disk in revolutions per second Nt= no of bits per sector Ns= no of bits per sector Calculate the avg. time Ta that will take to read to one sector? 2. A computer uses RAM chips of 256x8 and ROM chips of 1024x8. The computer system needs 2K bytes of RAM and 4K bytes of ROM and four interface units each four registers. A memory mapped I/O configuration is used. The two highest-order bits of the address bus are assigned 00 for RAM,01 for ROM and 10 for interface registers a) How many ROM and RAM chips are needed b) Draw a memory address map for system c) Give the address range in hexadecimal for RAM, ROM and Interface. 3. A two-way set associative cache memory uses blocks of four words. The cache can accommodate a total of 2048 words from main memory. The main memory size is 128Kx32 a) Formulate all pertinent information required to construct the cache memory b) What is size of the cache memory 4. A virtual memory has a page size of 1K words. There are 8 pages and 4 blocks. The associative memory page table contains the following entries: Page Block 1 3 2 1 4 2 5 0 Make a list of all virtual addresses (in decimal) that will cause a page fault if used by CPU 5. The logical address space in a computer system consists of 128 segments. Each segment can have up to 32 pages of 4K words in each. Physical memory consists of 4K blocks of 4K words in each. Formulate the logical and physical address formats. 6. An 8-bit computer has a 16-bit address bus .The first 15 lines of the address are used to select a bank of 32K bytes of memory. The high order bit of the address is used to select a register which receives the contents of the data bus. Explain how this configuration can be used to extend the memory capacity of the system to eight banks of 32K bytes each, for a total of 256 bytes of memory.

7. What is the transfer rate of an eight-track magnetic tape whose speed is 120 inches per second and whose desity is 1600 bits per inch? 8. What is the reason for not having a large enough main memory for storing the totality of information in a computer system. 9. A digital computer has memory unit of 64K X 16 and cache memory of 1K words. The cache uses direct mapping with a block size of 4 words. a) How many bits are there in tag, index, block and words fields of the address format? b) How many bits are there on each word of caches includes valid bits? c) How many blocks can be the cache accommodate? 10. What do you understand by associative memory? Draw the circuit for match logic for a one word of associative memory.

COMPUTER ARCHITECTURE TUTORIAL 8 Q1. What are the difference between isolated I/O and memory-mapped I/O? What are the advantages and disadvantages of each? Q2. Give at least six status conditions for the setting of individual bits in the status register of an asynchronous communication interfaces. Q3. How many characters per second can be transmitted over a 1200-baud line in each of the following modes? a) Synchronous serial transmission. b) Asynchronous serial transmission with two stop bits. c) Asynchronous serial transmission with one stop bits. Q4. Design parallel priority interrupt hardware for a system with eight interrupt sources. Q5. Why does DMA have priority over the CPU when both request a memory transfer? Q6. Writ your full name in ASCII using 8 bits per character with the leftmost bit always 0. Include a space between names and a period after middle initial. Q7.Why are the read and writes control lines in a DMA controller bidirectional? Under what condition and for what purpose are they used as inputs? Under what condition and for what purpose are they used as outputs? Q8.What happens in the daisy chain priority interrupt when device 1 requests an interrupt after device 2 has sent an interrupt request to the CPU but before the CPU responds with the interrupt acknowledge? Q9. What are the various modes of data transfer? Q10. What is the difference between asynchronous and synchronous data transfer

COMPUTER ARCHITECTURe TUTORIAL 9

Q1. In certain scientific computations it is necessary to perform the arithmetic operation (Ai +Bi)(Ci +Di) with a stream of numbers. Specify a pipeline configuration to carry out this task. List the contents of all registers in the pipeline for i = 1 through 6. Q2. Q3. Draw a space-time diagram for a six-segment pipeline showing the time it takes to process eight tasks. Determine the number of clock cycles that it takes to process 200 tasks in a six-segment pipeline.

Q4. A non-pipeline system takes 50ns to process a task. The same task can be processed in a six-segment pipeline with a clock cycle of 10ns. Determine the speedup ratio of the pipeline for 100 tasks. What is the maximum speedup that can be achieved? Q5. Formulate a six-segment instruction pipeline for a computer. Specify the operations to be performed in each segment. Q6. Explain four possible hardware schemes that can be used in an instruction pipeline in order to minimize the performance degradation caused by instruction branching. Q7. Q8. Q9. Q10. Give an example of a program that will cause data conflict in the three-segment pipeline of Sec. 9-5. Give an example that uses delayed load with the three-segment pipeline of Sec. 9-5. Give an example of a program that will cause a branch penalty in the three-segment pipeline of Sec. 9-5. Give an example that uses delayed branch with the three-segment pipeline of Sec.9-5.

Q11. A weather forecasting computation requires 250 billion floating-point operations. The problem is processed in a supercomputer that can perform 100 megaflops. How long will it take to do these calculations?

COMPUTER ARCHITECTURE TUTORIAL 10 Q1. What is the difference between tightly coupled multiprocessors and loosely coupled multiprocessors? Q2. How many switch points are there are there in a crossbar switch network that connects p processors to m memory modules? Q3. What is cache coherence, and why it is important in shared memory multiprocessors systems? Q4. Construct a diagram for a 4 x 4 omega switching network. Show the switch setting required to connect input 3 to output 1. Q5. What are the different techniques for establishing an interconnection network? Q6. What is interprocessor arbitration? Discuss serial and parallel Arbitration.

Q7. How cache coherence problem can be solved with a snoopy cache controller? Q8. Explain how the priority is determined once the bus line is disabled in case of daisy chain arbitration procedure, Q8. Describe hardware lock and test- and-set instruction associated with multiprocessors . Q9. What is the purpose of the system bus controller? Explain how the system can be designed to distinguish between references to local memory and references to common shared memory. Q10. What is the difference between multiprocessor and multicomputer systems?

Amity School of Engineering and Technology Computer Architecture Lab 1.Simulation of Half Adder and Half Subtractor . 2.Simulation of Full Adder Circuit and full Subtractor Circuit. 3.Simulation of the logical part of Arithmetic logical Unit. 4.Simulation of Transfer of data from one register to another using MUX 5.Transfer of Data from different registers to a common Bus using decoders and tristate buffers. 6.Simulation of combinational circuit decrementer using full adder circuits. 7.Verification of arithmetic operations by using MUX and full adders. 8.Simulation of a BCD Adder. 9.Writing assembly Language programs using 8085 Simulator. Lecture Plan Lectur e No. 1 Module No. 1 Topic Introduction to subject Subtopics Definition of CO,CA,Computer design. Block diagram digital computer. Problems on simplification of Boolean expressions and its circuit. Examples of Sequential and combinational circuits. Microperation and its block diagram representation and timimng diagram. Register Transfer Control Function Basic symbols of register transfer Bus system for 4 registers Three state bus buffers.

Register Transfer Language

Bus and Memory

transfers Arithemetic microperations

Logic microperations

Shift microperations ,Arithmetic Logic Shift Unit Basic computer organization and design: Instruction codes Computer instructions

Memory transfer Symolic designation of various arithemetic microperations. 4-bit binary Adder Subtractor circuit Binary Incrementer circuit Arithmetic Circuit and its function table Various logic microperations One stage of logic circuit Some applications-selective set,selective complement,selective clear, Various shift microperations 4-bit combinational circuit shifter One stage of arithmetic logic shift unit and its function table. Stored program organization Basic computer registers and memory and its function Connection to a common bus Basic computer instruction formats Memory reference instruction Register reference instruction Input output instruction Instruction set completeness Hardwired control Microprogrammed control Control unit of basic computer(diagram) Fetch and decode phase Register transfers for the fetch phase Flowchart for instruction cycle Flowchart for interrupt cycle Interrupt cycle Design of basic computer Flowchart for computer operation Control gates associated with AR Control of common bus Circuit associated with AC Gate structure for contolling the LD,INR,and CLR of AC. Adder and Logic Circuit. Control memory:microinstruction,microprogram Control address register,microprogram sequencer Addressing sequencing:selection of address for control memory

Timing and Control

10

Instruction cycle

11 12

Interrupt

13

Design of accumulator logic Microprogram med Control: Control memory,

14

15

Addressing sequencing Mapping of instruction

Mapping from instruction code to microinstruction address Microprogram example Microinstruction format Fetch routine Decoding of microoperation fields introduction, general register organization, stack organization

16 17 3

Design of control unit Central Processing Unit:introducti on,general register organization,st ack organization Instruction formats,instruc tion types Addressing modes

18

19

Three address instructions Two address instructions One address instruction Zero address instruction Advantage, Types:immediate,register,register indirect,autoincrement,autodecrement,direct,indirect, relative,indexed,base register, numerical exampleData transfer instructions, data manipulation instructions:arithemetic,logical and bit manipulation,shift instructions Status bits, Conditional Branch, Subroutine call and return, Program interrupt, External internal software interrupts RISC characteristics CISC characteristics

20 Data transfer Manipulation 23 Interrupt 24 RISC and CISC

21-22

Program control

25

Memory :Main memory

26 27 28 Auxiliary memory Associtaive memory

29-30

Cache memory

31

Virtual memory

32 33

Virtual memory Memory mant. h/w

34

Intrasystem communication and I/O

35

36

37 38 3 Computer arithmetic Multiplication Algorithm Division algo 5 Parallel

39

Differences Memory hierarchy, Main memory- Ram and Rom chips Memory address map Memory address map and Memory connection to CPU Magnetic disks, Magnetic tape Hardware organization, Associative memory of m word n cells per word, Match logic, read and write operation. Locality of reference, Hitratio Mapping :Associative ,Direct,set-associative, writing to cache reading from cache Address space memory space mapping virtual address Address mapping using pages Associative memory page table page replacement Segment,logical address, segmented page mapping, numerical example, memory protection. Peripheral devices and controllers, drivers, IDE for harddisk I/O port bus concept,bus cycle, synchronous and asynchronous transfer Parallel port, RS-232 interface, serial interface, USB Bus arbitration methods Uni bus and muti bus architectures Introduction, addition, subtraction Booths Algorithm

40

Introduction

41 42 43

processing Pipelining vector processing,Arr ay processing Multiprocessor s

Instruction pipeling Arithemetic pipelining

44 45 Advanced computer Architecture

Characteristics, Interconnection structures:Time shared,Multiport,Crossbar switch,Multistage,Hypercube Interprocessor arbitration, interprocessor communication and synchronization Pentium Pentium Pro