Static Load MOS Inverter

4: DC and Transient Response

CMOS VLSI Design

Slide 5

nMOS Operation
Cutoff Vgsn < Vtn Vin < Vtn Linear Vgsn > Vtn Vin > Vtn Vdsn < Vgsn Vtn Vout < Vin - Vtn Saturated Vgsn > Vtn Vin > Vtn Vdsn > Vgsn Vtn Vout > Vin - Vtn
VDD

Vgsn = Vin Vdsn = Vout

4: DC and Transient Response CMOS VLSI Design

Vin

Idsp Idsn

Vout

Slide 14

pMOS Operation
Cutoff Vgsp > Vtp Vin > VDD + Vtp Linear Vgsp < Vtp Vin < VDD + Vtp Vdsp > Vgsp Vtp Vout > Vin - Vtp Saturated Vgsp < Vtp Vin < VDD + Vtp Vdsp < Vgsp Vtp Vout < Vin - Vtp
VDD

Vgsp = Vin - VDD Vdsp = Vout - VDD

4: DC and Transient Response

Vtp < 0
Vin

Idsp Idsn

Vout

CMOS VLSI Design

Slide 18

Current vs. Vout, Vin

Vin0 Vin5

Idsn, |Idsp|

Vin1 Vin2 Vin3 Vin4 Vout VDD

Vin4 Vin3 Vin2 Vin1

4: DC and Transient Response

CMOS VLSI Design

Slide 20

Load Line Summary

Vin0 Vin5

Idsn, |Idsp|

Vin1 Vin2 Vin3 Vin4 Vout VDD

Vin4 Vin3 Vin2 Vin1

4: DC and Transient Response

CMOS VLSI Design

Slide 28

Operating Regions
Revisit transistor operating regions

Region A B C D E

nMOS Cutoff Saturation Saturation Linear Linear

pMOS Linear Linear Saturation Saturation Cutoff

VDD A Vout B

D 0
Vtn VDD/2

E
VDD+Vtp

VDD

Vin

4: DC and Transient Response

CMOS VLSI Design

Slide 31

Region Operation

4: DC and Transient Response

CMOS VLSI Design

Slide 32

CMOS Inverter as Switch

V DD Rp V DD

tpHL = f(Ron.CL) = 0.69 RonCL

V out CL Rn V out CL

V in 5 0 (a) Low-to-high
4: DC and Transient Response

V in 5 V DD (b) High-to-low
CMOS VLSI Design Slide 8