Design of binary divider

Consider parallel divider for positive binary numbers 8-bit dividend, 4-bit divisor, results are 4-bit quotient and 4-bit reminder

 Similar to multiplier, instead of series of addshift operations, here series of subtract-shift operations are required 9-bit dividend register and a 4-bit divisor register are required Block diagram of parallel binary divider:

 Operation: Initial register contents:

Shift dividend one place left:

Subtraction carried out, and 1 is stored in first quotient digit:

 Shift dividend one place left: Subtraction result negative result, shift dividend to left and quotient digit remains zero

Subtraction carried out, and 1 is stored in the third quotient digit:

 Final shift is carried out and fourth quotient bit is set to zero:

The result is available in dividend register If quotient contain more bits than available for storing the quotient, an overflow has occurred, such a case no need to carry out the division

 State graph: