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Colour Television

Chassis

Q552.2E
LA

19100_000_110214.eps 110214

Contents
1. 2. 3. 4. 5. 6. 7. 8. 9.

Page

Contents

Page

Revision List 2 Technical Specifications, Diversity, and Connections2 Precautions, Notes, and Abbreviation List 6 Mechanical Instructions 10 Service Modes, Error Codes, and Fault Finding 17 Alignments 36 Circuit Descriptions 40 IC Data Sheets 46 Block Diagrams Wiring diagram Blockbuster 32" 59 Wiring diagram Blockbuster 37" 60 Wiring diagram Blockbuster 40" 61 Block Diagram Video 62 Block Diagram Audio 63 Block Diagram Control & Clock Signals 64 Block Diagram I2C 65 Supply Lines Overview 66 10. Circuit Diagrams and PWB Layouts Drawing B01 393912364954 67 B02 393912364954 78 B03 393912364954 87 B04 393912364954 95 B05 393912364954 100 B06 393912364954 101 B07 393912364954 105 B08 393912364954 106 B09 393912364954 108 313912364954 SSB Layout 109 E 27221719026x IR/LED/Key Board 111 11. Styling Sheets Blockbuster 32" 112 Blockbuster 37" 113 Blockbuster 40"& 46" 114

Copyright 2011 Koninklijke Philips Electronics N.V. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted, in any form or by any means, electronic, mechanical, photocopying, or otherwise without the prior permission of Philips.

Published by ER/TY 1162 BU TV Consumer Care, the Netherlands

Subject to modification

EN 3122 785 19100 2011-Feb-18

EN 2

1.

Q552.2E LA

Revision List

1. Revision List
Manual xxxx xxx xxxx.0 First release.

2. Technical Specifications, Diversity, and Connections


Index of this chapter: 2.1 Technical Specifications 2.2 Directions for Use 2.3 Connections 2.4 Chassis Overview Notes: Figures can deviate due to the different set executions. Specifications are indicative (subject to change). Table 2-1 Described Model Numbers and Diversity
SSB 2 4 Mechanics 7 Descriptions 9 10 Schematics ALxx (Ambilight) Everlight ALxx (Ambilight) LiteOn B06 (non-DVBS-LVDS) B09 (non-DVBS-conn.)

2.1

Technical Specifications
For on-line product support please use the CTN links in Table 2-1. Here is product information available, as well as getting started, user manuals, frequently asked questions and software & drivers.

B03 (DC/DC / Class D)

Connection Overview

32PFL6606H/12 32PFL6606K/02 37PFL6606H/12 37PFL6606K/02 40PFL6606H/12 40PFL6606K/02

Blockbuster 64954 2.3 4-1 4.3 4.3.8 7.2 11-1 Blockbuster 64954 2.3 4-1 4.3 4.3.8 7.2 11-1 Blockbuster 64954 2.3 4-2 4.3 4.3.8 7.2 11-2 Blockbuster 64954 2.3 4-2 4.3 4.3.8 7.2 11-2 Blockbuster 64954 2.3 4-3 4.3 4.3.8 7.2 11-3 Blockbuster 64954 2.3 4-3 4.3 4.3.8 7.2 11-3

7.4.1 7.4.1 7.4.1 7.4.1 7.4.1 7.4.1 -

9-1 9-1 9-2 9-2 9-3 9-3 -

10-1 10-1 10-1 10-1 10-1 10-1

10-2 10-2 10-2 10-2 10-2 10-2

10-3 10-3 10-3 10-3 10-3 10-3

10-4 10-4 10-4 10-4 10-4 10-4

10-5 10-5 10-5 10-5 10-5 10-5

10-6 10-6 10-6 10-6 10-6 10-6

10-7 10-7 10-7 10-7 10-7 10-7

10-8 10-8 10-8 10-8 10-8 10-8

10-9 10-9 10-9 10-9 10-9 10-9

10-11 10-11 10-11 10-11 10-11 10-11 -

2.2

Directions for Use


You can download this information from the following websites: http://www.philips.com/support http://www.p4c.philips.com

2011-Feb-18

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CTN

Styling

E (IR/LED/Key Board)

Assembly Removal

B08 (DVBS-Supp.)

B02 (PNX85500)

Wiring Diagram

3139 123 xxxxx

B07 (DVBS-FE)

Wire Dressing

LCD Removal

B01 (Tuner)

B05 (DDR)

AmbiLight

B04 (I/O)

TCON

Tuner

PSU

Technical Specifications, Diversity, and Connections 2.3 Connections

Q552.2E LA

2.

EN 3

REAR CONNECTORS
5

SIDE CONNECTORS

12 1 2 4 3 13 9 10 11

BOTTOM REAR CONNECTORS


6 7 8

14 15 16

19100_043_110214.eps 110216

Figure 2-1 Connection overview Note: The following connector colour abbreviations are used (acc. to DIN/IEC 757): Bk= Black, Bu= Blue, Gn= Green, Gy= Grey, Rd= Red, Wh= White, Ye= Yellow. 2.3.1 Rear Connections 1 - EXT1: Video RGB - In, CVBS - In/Out, Audio - In/Out
20 2

13 14 15 16 17 18 19 20 21

- Ground Red - Ground P50 - Video Red - Status/FBL - Ground Video - Ground FBL - Video CVBS/Y - Video CVBS - Shield

Gnd Gnd 0.7 VPP / 75 ohm 0 - 0.4 V: INT 1 - 3 V: EXT / 75 ohm Gnd Gnd 1 VPP / 75 ohm 1 VPP / 75 ohm Gnd

H H j j H H k j H

21

10000_001_090121.eps 090121

Figure 2-2 SCART connector 1 2 3 4 5 6 7 8 - Audio R - Audio R - Audio L - Ground Audio - Ground Blue - Audio L - Video Blue - Function Select 0.5 VRMS / 1 kohm 0.5 VRMS / 10 kohm 0.5 VRMS / 1 kohm Gnd Gnd 0.5 VRMS / 10 kohm 0.7 VPP / 75 ohm 0 - 2 V: INT 4.5 - 7 V: EXT 16:9 9.5 - 12 V: EXT 4:3 Gnd 0.7 VPP / 75 ohm k j k H H j jk j H j

2 - Service Connector (UART) 1 - Ground Gnd 2 - UART_TX Transmit 3 - UART_RX Receive 3 - EXT2: Cinch: Video YPbPr - In, Audio - In Gn - Video Y 1 VPP / 75 ohm Bu - Video Pb 0.7 VPP / 75 ohm Rd - Video Pr 0.7 VPP / 75 ohm Rd - Audio - R 0.5 VRMS / 10 kohm Wh - Audio - L 0.5 VRMS / 10 kohm 4 - Cinch: Audio - In (VGA/DVI) Rd - Audio R 0.5 VRMS / 10 kohm Wh - Audio L 0.5 VRMS / 10 kohm 5 - SAT - In - - F-type
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H k j

jq jq jq jq jq

9 10 11 12

- Ground Green - n.c. - Video Green - n.c.

jq jq

Coax, 75 ohm

D
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EN 4
2.3.2

2.

Q552.2E LA

Technical Specifications, Diversity, and Connections


13 14 15 16 17 18 19 20 - Easylink/CEC - ARC - DDC_SCL - DDC_SDA - Ground - +5V - HPD - Ground Control channel Audio Return Channel DDC clock DDC data Gnd Hot Plug Detect Gnd jk k j jk H j j H

Rear Connections - Bottom 6 - RJ45: Ethernet


12345678

10000_025_090121.eps 090121

Figure 2-3 Ethernet connector 1 2 3 4 5 6 7 8 - TD+ - TD- RD+ - CT - CT - RD- GND - GND Transmit signal Transmit signal Receive signal Centre Tap: DC level fixation Centre Tap: DC level fixation Receive signal Gnd Gnd k k j j H H

10 - Aerial - In - - IEC-type (EU)

Coax, 75 ohm

11 - VGA: Video RGB - In


1 6 11 5 10 15

10000_002_090121.eps 090127

Figure 2-6 VGA Connector 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 2.3.3 - Video Red - Video Green - Video Blue - n.c. - Ground - Ground Red - Ground Green - Ground Blue - +5VDC - Ground Sync - n.c. - DDC_SDA - H-sync - V-sync - DDC_SCL 0.7 VPP / 75 ohm 0.7 VPP / 75 ohm 0.7 VPP / 75 ohm Gnd Gnd Gnd Gnd +5 V Gnd DDC data 0-5V 0-5V DDC clock j j j H H H H j H j j j j

7 - Cinch: S/PDIF - Out Bk - Coaxial 0.4 - 0.6VPP / 75 ohm 8 - HDMI 2: Digital Video, Digital Audio - In
19 18 1 2

kq

10000_017_090121.eps 090428

Figure 2-4 HDMI (type A) connector 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 - D2+ - Shield - D2- D1+ - Shield - D1- D0+ - Shield - D0- CLK+ - Shield - CLK- Easylink/CEC - n.c. - DDC_SCL - DDC_SDA - Ground - +5V - HPD - Ground Data channel Gnd Data channel Data channel Gnd Data channel Data channel Gnd Data channel Data channel Gnd Data channel Control channel DDC clock DDC data Gnd Hot Plug Detect Gnd j H j j H j j H j j H j jk j jk H j j H

Side Connections 12 - Common Interface 68p - See diagram B01A Common Interface 13 - SD-Card: Secure Digital Card - In/Out (optional)
14 GND WP GND CD 8 7 6 5 4 3 2 1 DAT1/IRQ DAT0/D0 GND2 CLOCK VDD GND1 CMD/DI DAT3/CS DAT2/NC 12 11 10

jk

9 - HDMI 1: Digital Video - In, Digital Audio with ARC - In/ Out
19 18 1 2

9 GND 13

10000_017_090121.eps 090428

10000_049_100210.eps 100210

Figure 2-5 HDMI (type A) connector Figure 2-7 SD-Card connector 1 2 3 4 5 6 7 8 9 10 11 12


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- D2+ - Shield - D2- D1+ - Shield - D1- D0+ - Shield - D0- CLK+ - Shield - CLK-

Data channel Gnd Data channel Data channel Gnd Data channel Data channel Gnd Data channel Data channel Gnd Data channel

j H j j H j j H j j H j
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1 2 3 4 5 6 7 8 9 10 11

- DAT3/CS - CMD/DI - GND1 - Vdd - CLOCK - GND2 - DAT0/D0 - DAT1/IRQ - DAT2/NC - CD - GND

Signal Signal Gnd Supply Signal Gnd Signal Signal Signal Signal Gnd

jk k H k k H jk jk jk j H

Technical Specifications, Diversity, and Connections


12 - WP 13 - GND 14 - GND 14 - USB2.0 Signal Gnd Gnd j H H 1 2 3 4 - +5V - Data (-) - Data (+) - Ground

Q552.2E LA

2.

EN 5
k jk jk H

Gnd

15 - Head phone (Output) Bk - Head phone 32 - 600 ohm / 10 mW


1 2 3 4 10000_022_090121.eps 090121

ot

16 - HDMI : Digital Video, Digital Audio - In See 8 - HDMI 2: Digital Video, Digital Audio - In

Figure 2-8 USB (type A)

2.4

Chassis Overview
Refer to chapter Block Diagrams for PWB/CBA locations.

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3.

Q552.2E LA

Precautions, Notes, and Abbreviation List

3. Precautions, Notes, and Abbreviation List


Index of this chapter: 3.1 Safety Instructions 3.2 Warnings 3.3 Notes 3.4 Abbreviation List Where necessary, measure the waveforms and voltages with (D) and without (E) aerial signal. Measure the voltages in the power supply section both in normal operation (G) and in stand-by (F). These values are indicated by means of the appropriate symbols.

3.1

Safety Instructions
Safety regulations require the following during a repair: Connect the set to the Mains/AC Power via an isolation transformer (> 800 VA). Replace safety components, indicated by the symbol h, only by components identical to the original ones. Any other component substitution (other than original type) may increase risk of fire or electrical shock hazard. Safety regulations require that after a repair, the set must be returned in its original condition. Pay in particular attention to the following points: Route the wire trees correctly and fix them with the mounted cable clamps. Check the insulation of the Mains/AC Power lead for external damage. Check the strain relief of the Mains/AC Power cord for proper function. Check the electrical DC resistance between the Mains/AC Power plug and the secondary side (only for sets that have a Mains/AC Power isolated power supply): 1. Unplug the Mains/AC Power cord and connect a wire between the two pins of the Mains/AC Power plug. 2. Set the Mains/AC Power switch to the on position (keep the Mains/AC Power cord unplugged!). 3. Measure the resistance value between the pins of the Mains/AC Power plug and the metal shielding of the tuner or the aerial connection on the set. The reading should be between 4.5 M and 12 M. 4. Switch off the set, and remove the wire between the two pins of the Mains/AC Power plug. Check the cabinet for defects, to prevent touching of any inner parts by the customer.

3.3.2

Schematic Notes All resistor values are in ohms, and the value multiplier is often used to indicate the decimal point location (e.g. 2K2 indicates 2.2 k). Resistor values with no multiplier may be indicated with either an E or an R (e.g. 220E or 220R indicates 220 ). All capacitor values are given in micro-farads ( 10-6), nano-farads (n 10-9), or pico-farads (p 10-12). Capacitor values may also use the value multiplier as the decimal point indication (e.g. 2p2 indicates 2.2 pF). An asterisk (*) indicates component usage varies. Refer to the diversity tables for the correct values. The correct component values are listed on the Philips Spare Parts Web Portal.

3.3.3

Spare Parts For the latest spare part overview, consult your Philips Spare Part web portal.

3.3.4

BGA (Ball Grid Array) ICs Introduction For more information on how to handle BGA devices, visit this URL: http://www.atyourservice-magazine.com. Select Magazine, then go to Repair downloads. Here you will find Information on how to deal with BGA-ICs. BGA Temperature Profiles For BGA-ICs, you must use the correct temperature-profile. Where applicable and available, this profile is added to the IC Data Sheet information section in this manual.

3.3.5

Lead-free Soldering Due to lead-free technology some rules have to be respected by the workshop during a repair: Use only lead-free soldering tin. If lead-free solder paste is required, please contact the manufacturer of your soldering equipment. In general, use of solder paste within workshops should be avoided because paste is not easy to store and to handle. Use only adequate solder tools applicable for lead-free soldering tin. The solder tool must be able: To reach a solder-tip temperature of at least 400C. To stabilize the adjusted temperature at the solder-tip. To exchange solder-tips for different applications. Adjust your solder tool so that a temperature of around 360C - 380C is reached and stabilized at the solder joint. Heating time of the solder-joint should not exceed ~ 4 sec. Avoid temperatures above 400C, otherwise wear-out of tips will increase drastically and flux-fluid will be destroyed. To avoid wear-out of tips, switch off unused equipment or reduce heat. Mix of lead-free soldering tin/parts with leaded soldering tin/parts is possible but PHILIPS recommends strongly to avoid mixed regimes. If this cannot be avoided, carefully clear the solder-joint from old tin and re-solder with new tin.

3.2

Warnings
All ICs and many other semiconductors are susceptible to electrostatic discharges (ESD w). Careless handling during repair can reduce life drastically. Make sure that, during repair, you are connected with the same potential as the mass of the set by a wristband with resistance. Keep components and tools also at this same potential. Be careful during measurements in the high voltage section. Never replace modules or other components while the unit is switched on. When you align the set, use plastic rather than metal tools. This will prevent any short circuits and the danger of a circuit becoming unstable.

3.3
3.3.1

Notes
General Measure the voltages and waveforms with regard to the chassis (= tuner) ground (H), or hot ground (I), depending on the tested area of circuitry. The voltages and waveforms shown in the diagrams are indicative. Measure them in the Service Default Mode with a colour bar signal and stereo sound (L: 3 kHz, R: 1 kHz unless stated otherwise) and picture carrier at 475.25 MHz for PAL, or 61.25 MHz for NTSC (channel 3).
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3.3.6

Alternative BOM identification It should be noted that on the European Service website, Alternative BOM is referred to as Design variant.

2011-Feb-18

Precautions, Notes, and Abbreviation List


The third digit in the serial number (example: AG2B0335000001) indicates the number of the alternative B.O.M. (Bill Of Materials) that has been used for producing the specific TV set. In general, it is possible that the same TV model on the market is produced with e.g. two different types of displays, coming from two different suppliers. This will then result in sets which have the same CTN (Commercial Type Number; e.g. 28PW9515/12) but which have a different B.O.M. number. By looking at the third digit of the serial number, one can identify which B.O.M. is used for the TV set he is working with. If the third digit of the serial number contains the number 1 (example: AG1B033500001), then the TV set has been manufactured according to B.O.M. number 1. If the third digit is a 2 (example: AG2B0335000001), then the set has been produced according to B.O.M. no. 2. This is important for ordering the correct spare parts! For the third digit, the numbers 1...9 and the characters A...Z can be used, so in total: 9 plus 26= 35 different B.O.M.s can be indicated by the third digit of the serial number. Identification: The bottom line of a type plate gives a 14-digit serial number. Digits 1 and 2 refer to the production centre (e.g. AG is Bruges), digit 3 refers to the B.O.M. code, digit 4 refers to the Service version change code, digits 5 and 6 refer to the production year, and digits 7 and 8 refer to production week (in example below it is 2006 week 17). The 6 last digits contain the serial number.
MODEL : 32PF9968/10
MADE IN BELGIUM 220-240V ~ 50/60Hz 128W VHF+S+H+UHF

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3.

EN 7

3.4

Abbreviation List
0/6/12 SCART switch control signal on A/V board. 0 = loop through (AUX to TV), 6 = play 16 : 9 format, 12 = play 4 : 3 format Automatic Aspect Ratio Adaptation: algorithm that adapts aspect ratio to remove horizontal black bars; keeps the original aspect ratio Automatic Channel Installation: algorithm that installs TV channels directly from a cable network by means of a predefined TXT page Analogue to Digital Converter Automatic Frequency Control: control signal used to tune to the correct frequency Automatic Gain Control: algorithm that controls the video input of the feature box Amplitude Modulation Asia Pacific Aspect Ratio: 4 by 3 or 16 by 9 Auto Screen Fit: algorithm that adapts aspect ratio to remove horizontal black bars without discarding video information Advanced Television Systems Committee, the digital TV standard in the USA See Auto TV A hardware and software control system that measures picture content, and adapts image parameters in a dynamic way External Audio Video Audio Video Controller Audio Video Input Processor Monochrome TV system. Sound carrier distance is 5.5 MHz Business Display Solutions (iTV) Board-Level Repair Broadcast Television Standard Committee. Multiplex FM stereo sound system, originating from the USA and used e.g. in LATAM and AP-NTSC countries Blue TeleteXT Centre channel (audio) Consumer Electronics Control bus: remote control bus on HDMI connections Constant Level: audio output to connect with an external amplifier Component Level Repair Computer aided rePair Connected Planet / Copy Protection Customer Service Mode Color Transient Improvement: manipulates steepness of chroma transients Composite Video Blanking and Synchronization Digital to Analogue Converter Dynamic Bass Enhancement: extra low frequency amplification Data Communication Module. Also referred to as System Card or Smartcard (for iTV). See E-DDC Monochrome TV system. Sound carrier distance is 6.5 MHz Dynamic Frame Insertion
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AARA

ACI

ADC AFC

AGC

AM AP AR ASF

ATSC

PROD.NO: AG 1A0617 000001

ATV Auto TV

BJ3.0E LA

10000_024_090121.eps 100105

Figure 3-1 Serial number (example) 3.3.7 Board Level Repair (BLR) or Component Level Repair (CLR) If a board is defective, consult your repair procedure to decide if the board has to be exchanged or if it should be repaired on component level. If your repair procedure says the board should be exchanged completely, do not solder on the defective board. Otherwise, it cannot be returned to the O.E.M. supplier for back charging! 3.3.8 Practical Service Precautions It makes sense to avoid exposure to electrical shock. While some sources are expected to have a possible dangerous impact, others of quite high potential are of limited current and are sometimes held in less regard. Always respect voltages. While some may not be dangerous in themselves, they can cause unexpected reactions that are best avoided. Before reaching into a powered TV set, it is best to test the high voltage insulation. It is easy to do, and is a good service precaution.

AV AVC AVIP B/G BDS BLR BTSC

B-TXT C CEC

CL CLR ComPair CP CSM CTI

CVBS DAC DBE DCM

DDC D/K DFI


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EN 8
DFU DMR DMSD DNM DNR DRAM DRM DSP DST

3.

Q552.2E LA

Precautions, Notes, and Abbreviation List


SDI), is a digitized video format used for broadcast grade video. Uncompressed digital component or digital composite signals can be used. The SDI signal is self-synchronizing, uses 8 bit or 10 bit data words, and has a maximum data rate of 270 Mbit/s, with a minimum bandwidth of 135 MHz. Institutional TeleVision; TV sets for hotels, hospitals etc. Last Status; The settings last chosen by the customer and read and stored in RAM or in the NVM. They are called at start-up of the set to configure it according to the customer's preferences Latin America Liquid Crystal Display Light Emitting Diode Monochrome TV system. Sound carrier distance is 6.5 MHz. L' is Band I, L is all bands except for Band I LG.Philips LCD (supplier) Loudspeaker Low Voltage Differential Signalling Mega bits per second Monochrome TV system. Sound carrier distance is 4.5 MHz Part of a set of international standards related to the presentation of multimedia information, standardised by the Multimedia and Hypermedia Experts Group. It is commonly used as a language to describe interactive television services Microprocessor without Interlocked Pipeline-Stages; A RISC-based microprocessor Matrix Output Processor Metal Oxide Silicon Field Effect Transistor, switching device Motion Pictures Experts Group Multi Platform InterFace MUTE Line Mainstream TV: TV-mode with Consumer TV features enabled (iTV) Not Connected Near Instantaneous Compounded Audio Multiplexing. This is a digital sound system, mainly used in Europe. Negative Temperature Coefficient, non-linear resistor National Television Standard Committee. Color system mainly used in North America and Japan. Color carrier NTSC M/N= 3.579545 MHz, NTSC 4.43= 4.433619 MHz (this is a VCR norm, it is not transmitted off-air) Non-Volatile Memory: IC containing TV related data such as alignments Open Circuit On Screen Display Over the Air Download. Method of software upgrade via RF transmission. Upgrade software is broadcasted in TS with TV channels. On screen display Teletext and Control; also called Artistic (SAA5800) Project 50: communication protocol between TV and peripherals Phase Alternating Line. Color system mainly used in West Europe (color carrier= 4.433619 MHz) and South America (color carrier PAL M=

DTCP

DVB-C DVB-T DVD DVI(-d) E-DDC

EDID EEPROM EMI EPG EPLD EU EXT FDS FDW FLASH FM FPGA FTV Gb/s G-TXT H HD HDD HDCP

HDMI HP I I2 C I2 D I2 S IF IR IRQ ITU-656

Directions For Use: owner's manual Digital Media Reader: card reader Digital Multi Standard Decoding Digital Natural Motion Digital Noise Reduction: noise reduction feature of the set Dynamic RAM Digital Rights Management Digital Signal Processing Dealer Service Tool: special remote control designed for service technicians Digital Transmission Content Protection; A protocol for protecting digital audio/video content that is traversing a high speed serial bus, such as IEEE-1394 Digital Video Broadcast - Cable Digital Video Broadcast - Terrestrial Digital Versatile Disc Digital Visual Interface (d= digital only) Enhanced Display Data Channel (VESA standard for communication channel and display). Using E-DDC, the video source can read the EDID information form the display. Extended Display Identification Data (VESA standard) Electrically Erasable and Programmable Read Only Memory Electro Magnetic Interference Electronic Program Guide Erasable Programmable Logic Device Europe EXTernal (source), entering the set by SCART or by cinches (jacks) Full Dual Screen (same as FDW) Full Dual Window (same as FDS) FLASH memory Field Memory or Frequency Modulation Field-Programmable Gate Array Flat TeleVision Giga bits per second Green TeleteXT H_sync to the module High Definition Hard Disk Drive High-bandwidth Digital Content Protection: A key encoded into the HDMI/DVI signal that prevents video data piracy. If a source is HDCP coded and connected via HDMI/DVI without the proper HDCP decoding, the picture is put into a snow vision mode or changed to a low resolution. For normal content distribution the source and the display device must be enabled for HDCP software key decoding. High Definition Multimedia Interface HeadPhone Monochrome TV system. Sound carrier distance is 6.0 MHz Inter IC bus Inter IC Data bus Inter IC Sound bus Intermediate Frequency Infra Red Interrupt Request The ITU Radio communication Sector (ITU-R) is a standards body subcommittee of the International Telecommunication Union relating to radio communication. ITU-656 (a.k.a.
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ITV LS

LATAM LCD LED L/L'

LPL LS LVDS Mbps M/N MHEG

MIPS

MOP MOSFET MPEG MPIF MUTE MTV NC NICAM

NTC NTSC

NVM O/C OSD OAD

OTC P50 PAL

2011-Feb-18

Precautions, Notes, and Abbreviation List


3.575612 MHz and PAL N= 3.582056 MHz) Printed Circuit Board (same as PWB) Pulse Code Modulation Plasma Display Panel Power Factor Corrector (or Preconditioner) Picture In Picture Phase Locked Loop. Used for e.g. FST tuning systems. The customer can give directly the desired frequency Point Of Deployment: a removable CAM module, implementing the CA system for a host (e.g. a TV-set) Power On Reset, signal to reset the uP Power Supply for Direct view LED backlight with 2D-dimming Power Supply with integrated LED drivers Power Supply with integrated LED drivers with added Scanning functionality Positive Temperature Coefficient, non-linear resistor Printed Wiring Board (same as PCB) Pulse Width Modulation Quasi Resonant Converter Quality Temporal Noise Reduction Quality Video Composition Processor Random Access Memory Red, Green, and Blue. The primary color signals for TV. By mixing levels of R, G, and B, all colors (Y/C) are reproduced. Remote Control Signal protocol from the remote control receiver RESET signal Read Only Memory Reduced Swing Differential Signalling data interface Red TeleteXT Service Alignment Mode Short Circuit Syndicat des Constructeurs d'Appareils Radiorcepteurs et Tlviseurs Serial Clock I2C CLock Signal on Fast I2C bus Standard Definition Serial Data I2C DAta Signal on Fast I2C bus Serial Digital Interface, see ITU-656 Synchronous DRAM SEequence Couleur Avec Mmoire. Color system mainly used in France and East Europe. Color carriers= 4.406250 MHz and 4.250000 MHz Sound Intermediate Frequency Switched Mode Power Supply System on Chip Sync On Green Self Oscillating Power Supply Serial Peripheral Interface bus; a 4wire synchronous serial data link standard Sony Philips Digital InterFace Static RAM Service Reference Protocol Small Signal Board Spread Spectrum Clocking, used to reduce the effects of EMI Set Top Box STand-BY 800 600 (4:3)
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Q552.2E LA

3.

EN 9

PCB PCM PDP PFC PIP PLL

SVHS SW SWAN SXGA TFT THD TMDS TS TXT TXT-DW UI uP UXGA V VESA VGA VL VSB WYSIWYR

POD

POR PSDL PSL PSLS

PTC PWB PWM QRC QTNR QVCP RAM RGB

WXGA XTAL XGA Y Y/C YPbPr

RC RC5 / RC6 RESET ROM RSDS R-TXT SAM S/C SCART

YUV

Super Video Home System Software Spatial temporal Weighted Averaging Noise reduction 1280 1024 Thin Film Transistor Total Harmonic Distortion Transmission Minimized Differential Signalling Transport Stream TeleteXT Dual Window with TeleteXT User Interface Microprocessor 1600 1200 (4:3) V-sync to the module Video Electronics Standards Association 640 480 (4:3) Variable Level out: processed audio output toward external amplifier Vestigial Side Band; modulation method What You See Is What You Record: record selection that follows main picture and sound 1280 768 (15:9) Quartz crystal 1024 768 (4:3) Luminance signal Luminance (Y) and Chrominance (C) signal Component video. Luminance and scaled color difference signals (B-Y and R-Y) Component video

SCL SCL-F SD SDA SDA-F SDI SDRAM SECAM

SIF SMPS SoC SOG SOPS SPI

S/PDIF SRAM SRP SSB SSC STB STBY SVGA

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EN 10

4.

Q552.2E LA

Mechanical Instructions

4. Mechanical Instructions
Index of this chapter: 4.1 Cable Dressing Blockbuster Styling (xxPFL66xx/xx series) 4.2 Service Positions 4.3 Assy/Panel Removal Sundance Styling (xxPFL76xx/xx series) 4.4 Set Re-assembly Notes: Figures below can deviate slightly from the actual situation, due to the different set executions.

4.1

Cable Dressing Blockbuster Styling (xxPFL66xx/xx series)

19100_044_110214.eps 110214

Figure 4-1 Cable dressing 32PFL6606x/xx (Blockbuster)

2011-Feb-18

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Mechanical Instructions

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4.

EN 11

19100_045_110214.eps 110214

Figure 4-2 Cable dressing 37PFL6606x/xx (Blockbuster)

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EN 12

4.

Q552.2E LA

Mechanical Instructions

19100_046_110214.eps 110214

Figure 4-3 Cable dressing 40PFL6606x/xx (Blockbuster)

4.2

Service Positions
For easy servicing of a TV set, the set should be put face down on a soft flat surface, foam buffers or other specific workshop tools. Ensure that a stable situation is created to perform measurements and alignments. When using foam bars take care that these always support the cabinet and never only the display. Caution: Failure to follow these guidelines can seriously damage the display! Ensure that ESD safe measures are taken.

1. Remove all screws of the rear cover. 2. Lift the rear cover from the TV. Make sure that wires and flat coils are not damaged while lifting the rear cover from the set. Additional instructions for Blockbuster 40-/46PFL6606x/xx 40"and 46"Blockbuster (40-/46PFL6606x/xx) sets have a dedicated method to open the bottom catches when removing the rear cover. Refer to Figure 4-4 and Figure 4-5 for details.

4.3

Assy/Panel Removal Sundance Styling (xxPFL76xx/xx series)


The instructions in this section also apply to the Blockbuster sets (xxPFL66xx/xx series). For the 40" and 46" Blockbuster sets, additional instructions (rear cover removal) apply. Refer to subsection Additional instructions for Blockbuster 40-/46PFL6606x/xx. The instructions apply to the 32PFL7406K/02. Figure 4-4 Bottom catches 40" and 46" Blockbuster sets -1-

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4.3.1

Rear Cover Warning: Disconnect the mains power cord before you remove the rear cover. Note: it is not necessary to remove the stand while removing the rear cover.

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2 1

Figure 4-5 Bottom catches 40" and 46" Blockbuster sets -2It is advised to lay the set with front facing down before executing this operation. 1. Remove all screws from the rear cover. 2. Use a round rod (diameter 2 mm) and insert it in one of the holes [1]. 3. Push the catch located inside the rear cover away by inserting the rod [2] through the hole and lifting the rear cover at the same time. 4. Repeat the same procedure on the other hole. 4.3.2 Speakers Tweeters Each tweeter unit is mounted with one screw. When defective, replace the whole unit. Subwoofer The central subwoofer is located in the centre of the set and is secured by two bosses. When defective, replace the whole unit. 4.3.3 Mains Switch Refer to Figure 4-6 for details. 4.3.5

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Figure 4-7 Main Power Supply 1. Unplug all connectors [1]. 2. Remove the fixation screws [2]. 3. Take the board out. When defective, replace the whole unit. Small Signal Board (SSB) Refer to Figure 4-8 for details.

1
2 1 2

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Figure 4-8 SSB 1. Unplug all connectors [1]. 2. Remove the fixation screws [2]. 3. Take the board out. When remounting, ensure that the side shielding [3] is positioned correctly.

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Figure 4-6 Mains switch The mains switch is mounted on a plastic subframe and can be removed without removing the subframe. 1. Use a screwdriver and push the switch out of its casing [1]. 2. Unplug the connectors [2]. When defective, replace the whole unit. 4.3.4 Main Power Supply Refer to Figure 4-7 for details.

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4.3.7 Ambilight Units The Ambilight units can be lifted from the subframes without the use of tools. Refer to Figure 4-11 for details.

Keyboard Control, IR & LED Board Refer to Figure 4-9 and Figure 4-10 for details.

1 1

2
1 1 1

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Figure 4-9 Keyboard control, IR & LED board [1/2] Figure 4-11 Ambilight units

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1. Unplug the connector [1]. 2. Carefully lift the board [2] and take the board out. When defective, replace the whole unit.

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Figure 4-10 Keyboard control, IR & LED board [2/2] 1. Remove the stand and the plastic support [1]. 2. Unplug the connector [2]. 3. Remove the screws [3] and take the board out. When defective, replace the whole unit.

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Mechanical Instructions
4.3.8 LCD Panel Refer to Figure 4-12 and Figure 4-13 for details.

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2 2 2

1 4 4 2 2 4 4

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Figure 4-12 LCD panel [1/2] 1. Remove the SSB as described earlier. 2. Remove the PSU as described earlier. 3. Remove the tweeters with their subframes and subwoofer as described earlier. 4. Remove the stand and -support as described earlier. 5. Remove the cables [1]. 6. Remove the stand subframe [2]. 7. Remove the mains switch subframe [3]. 8. Remove the Ambilight units together with their subframes as described earlier. 9. Unplug the connector from the keyboard control-, and IR & LED board as described earlier. 10. Remove all remaining cables and subframes. 11. Use a screwdriver to release the clamps [4] that secure the panel and take the panel out. Remove the clamps from the panel before sending the panel in for Service.

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Figure 4-13 LCD panel [2/2]

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Set Re-assembly
To re-assemble the whole set, execute all processes in reverse order. Notes: While re-assembling, make sure that all cables are placed and connected in their original position. Pay special attention not to damage the EMC foams in the set. Ensure that EMC foams are mounted correctly.

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5. Service Modes, Error Codes, and Fault Finding


Index of this chapter: 5.1 Test Points 5.2 Service Modes 5.3 Stepwise Start-up 5.4 Service Tools 5.5 Error Codes 5.6 The Blinking LED Procedure 5.7 Protections 5.8 Fault Finding and Repair Tips 5.9 Software Upgrading All service-unfriendly modes (if present) are disabled, like: (Sleep) timer. Child/parental lock. Picture mute (blue mute or black mute). Automatic volume levelling (AVL). Skip/blank of non-favourite pre-sets.

5.1

Test Points
As most signals are digital, it will be difficult to measure waveforms with a standard oscilloscope. However, several key ICs are capable of generating test patterns, which can be controlled via ComPair. In this way it is possible to determine which part is defective. Perform measurements under the following conditions: Service Default Mode. Video: Colour bar signal. Audio: 3 kHz left, 1 kHz right.

How to Activate SDM For this chassis there are two kinds of SDM: an analogue SDM and a digital SDM. Tuning will happen according Table 5-1. Analogue SDM: use the standard RC-transmitter and key in the code 062596, directly followed by the MENU (or HOME) button. Note: It is possible that, together with the SDM, the main menu will appear. To switch it off, push the MENU (or "HOME") button again. Analogue SDM can also be activated by grounding for a moment the solder path on the SSB, with the indication SDM (see Service mode pad). Digital SDM: use the standard RC-transmitter and key in the code 062593, directly followed by the MENU (or "HOME") button. Note: It is possible that, together with the SDM, the main menu will appear. To switch it off, push the MENU (or "HOME") button again.

5.2

Service Modes
Service Default mode (SDM) and Service Alignment Mode (SAM) offers several features for the service technician, while the Customer Service Mode (CSM) is used for communication between the call centre and the customer.

SDM
This chassis also offers the option of using ComPair, a hardware interface between a computer and the TV chassis. It offers the abilities of structured troubleshooting, error code reading, and software version read-out for all chassis. (see also section 5.4.1 ComPair). Note: For the new model range, a new remote control (RC) is used with some renamed buttons. This has an impact on the activation of the Service modes. For instance the old MENU button is now called HOME (or is indicated by a house icon). 5.2.1 Service Default Mode (SDM) Purpose To create a pre-defined setting, to get the same measurement results as given in this manual. To override SW protections detected by stand-by processor and make the TV start up to the step just before protection (a sort of automatic stepwise start-up). See section 5.3 Stepwise Start-up. To start the blinking LED procedure where only LAYER 2 errors are displayed. (see also section 5.5 Error Codes). Specifications 5.2.2 Table 5-1 SDM default settings Default system PAL B/G Purpose To perform (software) alignments. To change option settings. To easily identify the used software version. To view operation hours. To display (or clear) the error code buffer. How to Activate SAM Via a standard RC transmitter: Key in the code 062596 directly followed by the INFO or OK button. After activating SAM with this method a service warning will appear on the screen, continue by pressing the OK button on the RC.
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Figure 5-1 Service mode pad After activating this mode, SDM will appear in the upper right corner of the screen (when a picture is available). How to Navigate When the MENU (or HOME) button is pressed on the RC transmitter, the TV set will toggle between the SDM and the normal user menu. How to Exit SDM Use one of the following methods: Switch the set to STAND-BY via the RC-transmitter. Via a standard customer RC-transmitter: key in 00sequence. Service Alignment Mode (SAM)

Region Europe, AP(PAL/Multi) Europe, AP DVB-T

Freq. (MHz) 475.25

DVB-T 546.00 PID Video: 0B 06 PID PCR: 0B 06 PID Audio: 0B 07

All picture settings at 50% (brightness, colour, contrast). Sound volume at 25%.

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Contents of SAM Hardware Info. A. SW Version. Displays the software version of the main software (example: Q555X-1.2.3.4 = AAAAB_X.Y.W.Z). AAAA= the chassis name. B= the SW branch version. This is a sequential number (this is no longer the region indication, as the software is now multi-region). X.Y.W.Z= the software version, where X is the main version number (different numbers are not compatible with one another) and Y.W.Z is the sub version number (a higher number is always compatible with a lower number). B. STBY PROC Version. Displays the software version of the stand-by processor. C. Production Code. Displays the production code of the TV, this is the serial number as printed on the back of the TV set. Note that if an NVM is replaced or is initialized after corruption, this production code has to be re-written to NVM. ComPair will foresee in a possibility to do this. Operation Hours. Displays the accumulated total of operation hours (not the stand-by hours). Every time the TV is switched on/off, 0.5 hours is added to this number. Errors (followed by maximum 10 errors). The most recent error is displayed at the upper left (for an error explanation see section 5.5 Error Codes). Reset Error Buffer. When cursor right (or OK button) pressed here, followed by the OK button, the error buffer is reset. Alignments. This will activate the ALIGNMENTS submenu. See Chapter 6. Alignments. Dealer Options. Extra features for the dealers. Options. Extra features for Service. For more info regarding option codes, see chapter 6. Alignments. Note that if the option code numbers are changed, these have to be confirmed with pressing the OK button before the options are stored, otherwise changes will be lost. Initialize NVM. The moment the processor recognizes a corrupted NVM, the initialize NVM line will be highlighted. Now, two things can be done (dependent of the service instructions at that moment): Save the content of the NVM via ComPair for development analysis, before initializing. This will give the Service department an extra possibility for diagnosis (e.g. when Development asks for this). Initialize the NVM. Note: When the NVM is corrupted, or replaced, there is a high possibility that no picture appears because the display code is not correct. So, before initializing the NVM via the SAM, a picture is necessary and therefore the correct display option has to be entered. Refer to Chapter 6. Alignments for details. To adapt this option, its advised to use ComPair (the correct values for the options can be found in Chapter 6. Alignments) or a method via a standard RC (described below). Changing the display option via a standard RC: Key in the code 062598 directly followed by the MENU (or "HOME") button and XXX (where XXX is the 3 digit decimal display code as mentioned on the sticker in the set). Make sure to key in all three digits, also the leading zeros. If the above action is successful, the front LED will go out as an indication that the RC sequence was correct. After the display option is changed in the NVM, the TV will go to the Stand-by mode. If the NVM was corrupted or empty before this action, it will be initialized first (loaded with default values). This initializing can take up to 20 seconds.

Display Option Code

39mm

PHILIPS
27mm

040

MODEL: 32PF9968/10
PROD.SERIAL NO: AG 1A0620 000001

(CTN Sticker)

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Figure 5-2 Location of Display Option Code sticker Store - go right. All options and alignments are stored when pressing cursor right (or the OK button) and then the OK-button. Operation hours display. Displays the accumulated total of operation hours of the screen itself. In case of a display replacement, reset to 0 or to the consumed operation hours of the spare display. SW Maintenance. SW Events. In case of specific software problems, the development department can ask for this info. HW Events. In case of specific software problems, the development department can ask for this info : - Event 26: refers to a power dip, this is logged after the TV set reboots due to a power dip. - Event 17: refers to the power OK status, sensed even before the 3 x retry to generate the error code. Test settings. For development purposes only. Development file versions. Not useful for Service purposes, this information is only used by the development department. Upload to USB. To upload several settings from the TV to an USB stick, which is connected to the SSB. The items are Channel list, Personal settings, Option codes, Alignments, Identification data (includes the set type and prod code + all 12NC like SSB, display, boards), History list. The All item supports to upload all several items at once. First a directory repair\ has to be created in the root of the USB stick. To upload the settings, select each item separately, press cursor right (or the OK button), confirm with OK and wait until the message Done appears. In case the download to the USB stick was not successful, Failure will be displayed. In this case, check if the USB stick is connected properly and if the directory repair is present in the root of the USB stick. Now the settings are stored onto the USB stick and can be used to download into another TV or other SSB. Uploading is of course only possible if the software is running and preferably a picture is available. This method is created to be able to save the customers TV settings and to store them into another SSB. Download from USB. To download several settings from the USB stick to the TV, same way of working needs to be followed as described in Upload to USB. To make sure that the download of the channel list from USB to the TV is executed properly, it is necessary to restart the TV and tune to a valid preset if necessary. The All item supports to download all several items at once. NVM editor. For NET TV the set type number must be entered correctly. Also the production code (AG code) can be entered here via the RC-transmitter. Correct data can be found on the side/rear sticker. CURSOR UP/DOWN key on the RC-transmitter. The selected item will be highlighted. When not all menu items
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How to Navigate In SAM, the menu items can be selected with the
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fit on the screen, move the CURSOR UP/DOWN key to display the next/previous menu items. With the CURSOR LEFT/RIGHT keys, it is possible to: (De) activate the selected menu item. (De) activate the selected sub menu. With the OK key, it is possible to activate the selected action.

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Contents of CSM The contents are reduced to 3 pages: General, Software versions and Quality items. The group names itself are not shown anywhere in the CSM menu. General Set Type. This information is very helpful for a helpdesk/ workshop as reference for further diagnosis. In this way, it is not necessary for the customer to look at the rear of the TV-set. Note that if an NVM is replaced or is initialized after corruption, this set type has to be re-written to NVM. ComPair will foresee in a possibility to do this. The update can also be done via the NVM editor available in SAM. Production Code. Displays the production code (the serial number) of the TV. Note that if an NVM is replaced or is initialized after corruption, this production code has to be re-written to NVM. ComPair will foresee in a possibility to do this. The update can also be done via the NVM editor available in SAM. Installed date. Indicates the date of the first installation of the TV. This date is acquired via time extraction. Options 1. Gives the option codes of option group 1 as set in SAM (Service Alignment Mode). Options 2. Gives the option codes of option group 2 as set in SAM (Service Alignment Mode). 12NC SSB. Gives an identification of the SSB as stored in NVM. Note that if an NVM is replaced or is initialized after corruption, this identification number has to be re-written to NVM. ComPair will foresee in a possibility to do this. This identification number is the 12nc number of the SSB. 12NC display. Shows the 12NC of the display. 12NC supply. Shows the 12NC of the power supply. 12NC 200Hz board. Shows the 12NC of the 200Hz Panel (when present). 12NC AV PIP. Shows the 12NC of the AV PIP board (when present). Software versions Current main SW. Displays the build-in main software version. In case of field problems related to software, software can be upgraded. As this software is consumer upgradeable, it will also be published on the Internet. Example: Q55xx1.2.3.4 Stand-by SW. Displays the build-in stand-by processor software version. Upgrading this software will be possible via ComPair or via USB (see section 5.9 Software Upgrading). Example: STDBY_83.84.0.0. e-UM version. Displays the electronic user manual SWversion (12NC version number). Most significant number here is the last digit. AV PIP software. 3D dongle software version. Quality items Signal quality. Bad / average /good (not for DVB-S). Ethernet MAC address. Displays the MAC address present in the SSB. Wireless MAC address. Displays the wireless MAC address to support the Wi-Fi functionality. BDS key. Indicates if the set is in the BDS status. CI module. Displays status if the common interface module is detected. CI + protected service. Yes/No. Event counter : S : 000X 0000(number of software recoveries : SW EVENT-LOG #(reboots) S : 0000 000X (number of software events : SW EVENTLOG #(events) H : 000X 0000(number of hardware errors) H : 0000 000X (number of hardware events : SW EVENTLOG #(events).

How to Exit SAM Use one of the following methods: Switch the TV set to STAND-BY via the RC-transmitter. Via a standard RC-transmitter, key in 00 sequence, or select the BACK key. 5.2.3 Customer Service Mode (CSM) Purpose When a customer is having problems with his TV-set, he can call his dealer or the Customer Helpdesk. The service technician can then ask the customer to activate the CSM, in order to identify the status of the set. Now, the service technician can judge the severity of the complaint. In many cases, he can advise the customer how to solve the problem, or he can decide if it is necessary to visit the customer. The CSM is a read only mode; therefore, modifications in this mode are not possible. When in this chassis CSM is activated, a test pattern will be displayed during 5 seconds (1 second Blue, 1 second Green and 1 second Red, then again 1 second Blue and 1 second Green). This test pattern is generated by the PNX51X0 (located on the 200Hz board as part of the display). So if this test pattern is shown, it could be determined that the back end video chain (PNX51X0 and display) is working.For TV sets without the PNX51X0 inside, every menu from CSM will be used as check for the back end chain video. When CSM is activated and there is a USB stick connected to the TV set, the software will dump the CSM content to the USB stick. The file (CSM_model number_serial number.txt) will be saved in the root of the USB stick. This info can be handy if no information is displayed. When in CSM mode (and a USB stick connected), pressing OK will create an extended CSM dump file on the USB stick. This file (Extended_CSM_model number_serial number.txt) contains: The normal CSM dump information, All items (from SAM load to USB, but in readable format), Operating hours, Error codes, SW/HW event logs. To have fast feedback from the field, a flashdump can be requested by development. When in CSM, push the red button and key in serial digits 2679 (same keys to form the word COPY with a cellphone). A file Dump_model number_serial number.bin will be written on the connected USB device. This can take 1/2 minute, depending on the quantity of data that needs to be dumped. Also when CSM is activated, the LAYER 1 error is displayed via blinking LED. Only the latest error is displayed (see also section 5.5 Error Codes). How to Activate CSM Key in the code 123654 via the standard RC transmitter. Note: Activation of the CSM is only possible if there is no (user) menu on the screen! How to Navigate By means of the CURSOR-DOWN/UP knob on the RCtransmitter, can be navigated through the menus.
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on XVX-line). It is recommended to measure first the FET 7U0X or others FETs on shortcircuit before activating SDM via the service pads.

How to Exit CSM Press MENU (or "HOME") / Back key on the RC-transmitter.

5.3

Stepwise Start-up
When the TV is in a protection state due to an error detected by stand-by software (error blinking is displayed) and SDM is activated via shortcutting the SDM solder path on the SSB, the TV starts up until it reaches the situation just before protection. So, this is a kind of automatic stepwise start-up. In combination with the start-up diagrams below, you can see which supplies are present at a certain moment. Caution: in case the start-up in this mode with a faulty FET 7U0X is done, you can destroy all ICs supplied by the +1V8 and +1v1, due to overvoltage (12V The abbreviations SP and MP in the figures stand for: SP: protection or error detected by the Stand-by Processor. MP: protection or error detected by the MIPS Main Processor.

Mains off

Mains on

- WakeUp requested - Acquisition needed - Tact switch pushed

WakeUp requested

St by

- stby requested and no data Acquisition required

Semi St by

Active
- St by requested - tact SW pushed

Tact switch pushed WakeUp requested (SDM) GoToProtection GoToProtection

Hibernate

- Tact switch pushed - last status is hibernate after mains ON

Protection

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Figure 5-3 Transition diagram

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Off
Mains is applied

Stand by or Protection

Standby Supply starts running. All standby supply voltages become available.

st-by P resets

Initialise I/O pins of the st-by P: - Switch reset-AVC LOW (reset state) - Switch reset-system LOW (reset state) - Switch reset-Ethernet LOW (reset state) - Switch reset-USB LOW (reset state) - Switch reset-DVBs LOW (reset state) - keep Audio-reset and Audio-Mute-Up HIGH

If the protection state was left by short circuiting the SDM pins, detection of a protection condition during startup will stall the startup. Protection conditions in a playing set will be ignored. The protection mode will not be entered.

start keyboard scanning, RC detection. Wake up reasons are off.

- Switch Audio-Reset high. It is low in the standby mode if the standby mode lasted longer than 10s.

Switch ON Platform and display supply by switching LOW the Standby line.

+12V, +24Vs, AL and Bolt-on power is switched on, followed by the +1V2 DCDC converter Detect2 is moved to an interrupt. To be checked if the detection on interrupt base is feasible or not or if we should stick to the standard 40ms interval.

Detect2 high received within 2 seconds?

No

12V error: Layer1: 3 Layer2: 16

Yes

Enter protection

Enable the DCDC converters (ENABLE-3V3n LOW)

Wait 50ms

Enable the supply detection algorithm

Set IC slave address of Standby P to (A0h)

Detect EJTAG debug probe (pulling pin of the probe interface to ground by inserting EJTAG probe)

An EJTAG probe (e.g. WindPower ICE probe) can be connected for Linux Kernel debugging purposes.

EJTAG probe connected ?

Yes

No No

No

Cold boot?

Yes Release AVC system reset Feed warm boot script Release AVC system reset Feed cold boot script Release AVC system reset Feed initializing boot script disable alive mechanism

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Figure 5-4 Off to Semi Stand-by flowchart (part 1)

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Reset-system is switched HIGH by the AVC at the end of the bootscript No AVC releases Reset-Ethernet, Reset-USB and Reset-DVBs when the end of the AVC bootscript is detected

Reset-system is switched HIGH by the AVC at the end of the bootscript

This cannot be done through the bootscript, the I/O is on the standby P

AVC releases Reset-Ethernet, Reset-USB and Reset-DVBs when the end of the AVC bootscript is detected

Timing need to be updated if more mature info is available.

Reset-Audio and Audio-Mute-Up are switched by MIPS code later on in the startup process

Reset-Audio and Audio-Mute-Up are switched by MIPS code later on in the startup process

No

Bootscript ready in 1250 ms?

Yes Set IC slave address of Standby P to (60h)

RPC start (comm. protocol) Timing needs to be updated if more mature info is available.

No Code = Layer1: 2 Layer2: 15

Flash to Ram image transfer succeeded within 30s? Yes

Switch AVC PNX85500 in reset (active low)

Code = Layer1: 2 Layer2: 53

No

SW initialization succeeded within 20s?

Timing needs to be updated if more mature info is available.

Wait 10ms

Yes

Enable Alive check mechanism Disable all supply related protections and switch off the +3V3 +5V DC/DC converter. MIPS reads the wake up reason from standby P. Wait 5ms Startup screen shall only be visible when there is a coldboot to an active state end situation. The startup screen shall not be visible when waking up for reboot reasons or waking up to semistandby conditions or waking up to enter Hibernate mode.. Wait until AVC starts to communicate

switch off the remaining DC/DC converters

Wake up reason coldboot & not semistandby? yes

3-th try?

Switch Standby I/O line high and wait 4 seconds

Yes Blink Code as error code

Startup screen cfg file present? yes

The first time after the option turn on of the startup screen or when the set is virgin, the cfg file is not present and hence the startup screen will not be shown.

200Hz set?

yes

Enter protection
No

No

85500 sends out startup screen

85500 sends out startup screen

85500 starts up the display. No To keep this flowchart readable, the exact display turn on description is not copied here. Please see the Semi-standby to On description for the detailed display startup During the complete display time of the Startup screen, the preheat condition of sequence. 100% PWM is valid. Startup screen visible

200Hz Tcon has started up the display.

85500 requests Lamp on

Startup screen visible

Initialize audio initialize tuner and channel decoders Initialize source selection Initialize video processing ICs

initialize AutoTV by triggering CHS AutoTV Init interface Initialize Ambilight with Lights off.

Semi-Standby
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Figure 5-5 Off to Semi Stand-by flowchart (part 2)

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Constraints taken into account:


- Display may only be started when valid LVDS output clock can be delivered by the AVC. - To have a reliable operation of the EEFL backlight, the backlight should be driven with a maximum PWM duty cycle during the first seconds. Only after this first one or two seconds, the PWM may be set to the required output level (Note that the PWM output should be present before the backlight is switched on). To minimize the artefacts, the picture should only be unblanked after these first seconds.

The assumption here is that a fast toggle (<2s) can only happen during ON->SEMI ->ON. In these states, the AVC is still active and can provide the 2s delay. A transition ON->SEMI->STBY->SEMI->ON cannot be made in less than 2s, because the standby state will be maintained for at least 4s.

Semi Standby
Wait until previous on-state is left more than 2 seconds ago. (to prevent LCD display problems)

CPipe already generates a valid output clock in the semi-standby state: display startup can start immediately when leaving the semi-standby state.

Assert RGB video blanking and audio mute

Display already on? (splash screen) No

The exact timings to switch on the display (LVDS delay, lamp delay) are defined in the display file.

Switch on the display power by switching LCD-PWR-ON low Yes Wait x ms Switch on LVDS output in the 85500 Delay Lamp-on with the sum of the LVDS delay and the Lamp delay indicated in the display file Initialize audio and video processing IC's and functions according needed use case.

Switch off the dimming backlight feature, set the BOOST control to nominal and make sure PWM output is set to maximum allowed PWM

Switch on LCD backlight (Lamp-ON)

Start POK line detection algorithm

return

Wait until valid and stable audio and video, corresponding to the requested output is delivered by the AVC AND the backlight has been switched on for at least the time which is indicated in the display file as preheat time.

Switch Audio-Reset low and wait 5ms A LED set does not normally need a preheat time. The preheat remains present but is set to zero in the display file.

Release audio mute and wait 100ms before any other audio handling is done (e.g. volume change)

The higher level requirement is that audio and video should be demuted without transient effects and that the audio should be demuted maximum 1s before or at the same time as the unblanking of the video.

Restore dimming backlight feature, PWM and BOOST output and unblank the video.

Switch on the Ambilight functionality according the last status settings.

Startup screen Option and Installation setting Photoscreen ON? Yes Display cfg file present and up to date, according correct display option? No No Yes Prepare Start screen Display config file and copy to Flash

Active
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Figure 5-6 Semi Stand-by to Active flowchart (EEFL or LED backlight 50/100 Hz only)

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The assumption here is that a fast toggle (<2s) can only happen during ON->SEMI ->ON. In these states, the AVC is still active and can provide the 2s delay. If the transition ON->SEMI>STBY->SEMI->ON can be made in less than 2s, we have to delay the semi -> stby transition until the requirement is met.

Semi Standby
Wait until previous on-state is left more than 2 seconds ago. (to prevent LCD display problems)

Assert RGB video blanking and audio mute

There is no need to define the display timings since the timing implementation is part of the Tcon.

Backlight already on? (splash screen) Yes No Request Tcon to Switch on the backlight in a direct LED or set Lamp-on I/O line in case of a side LED Initialize audio and video processing IC's and functions according needed use case.

Start POK line detection algorithm Wait until valid and stable audio and video, corresponding to the requested output is delivered by the AVC. return Switch Audio-Reset low and wait 5ms

The higher level requirement is that audio and video should be demuted without transient effects and that the audio should be demuted maximum 1s before or at the same time as the unblanking of the video.

Release audio mute and wait 100ms before any other audio handling is done (e.g. volume change)

unblank the video.

Switch on the Ambilight functionality according the last status settings.

Startup screen Option and Installation setting Photoscreen ON? Yes Display cfg file present and up to date, according correct display option? No No Yes Prepare Start screen Display config file and copy to Flash

Active
18770_254_100216.eps 100216

Figure 5-7 Semi Stand-by to Active flowchart (LED backlight 200 Hz)

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Service Modes, Error Codes, and Fault Finding

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Active
Mute all sound outputs via softmute

Wait 100ms

Set main amplifier mute (I/O: audio-mute)

Force ext audio outputs to ground (I/O: audio reset) And wait 5ms

switch off Ambilight

Wait until Ambilight has faded out: Output power Observer should be zero

Switch off POK line detection algorithm

switch off LCD backlight (I/O or IC)

Mute all video outputs

Yes

200Hz set?

No

Wait x ms (display file) Instruct 200Hz Tcon to turn off the display

Switch off LVDS output in 85500

Wait x ms

The exact timings to switch off the display (LVDS delay, lamp delay) are defined in the display file.

Switch off the display power by switching LCD-PWR-ON high

Semi Standby
18770_255_100216.eps 100216

Figure 5-8 Active to Semi Stand-by flowchart

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Semi Stand by

If ambientlight functionality was used in semi-standby (lampadaire mode), switch off ambient light (see CHS ambilight)

Delay transition until ramping down of ambient light is finished. *)

*) If this is not performed and the set is switched to standby when the switch off of the ambilights is still ongoing, the lights will switch off abruptly when the supply is cut.

transfer Wake up reasons to the Stand by P.

Switch Memories to self-refresh (this creates a more stable condition when switching off the power).

Switch AVC system in reset state (reset-system and reset-AVC lines) Switch reset-USB, Reset-Ethernet and Reset-DVBs LOW

Wait 10ms

Disable all supply related protections and switch off the DC/DC converters (ENABLE-3V3n)

Wait 5ms

Switch OFF all supplies by switching HIGH the Standby I/O line

Important remarks: release reset audio 10 sec after entering standby to save power Also here, the standby state has to be maintained for at least 4s before starting another state transition.

Stand by
18770_256_100216.eps 100216

Figure 5-9 Semi Stand-by to Stand-by flowchart

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Service Modes, Error Codes, and Fault Finding 5.4


5.4.1

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Service Tools
ComPair Introduction ComPair (Computer Aided Repair) is a Service tool for Philips Consumer Electronics products. and offers the following: 1. ComPair helps to quickly get an understanding on how to repair the chassis in a short and effective way. 2. ComPair allows very detailed diagnostics and is therefore capable of accurately indicating problem areas. No knowledge on I2C or UART commands is necessary, because ComPair takes care of this. 3. ComPair speeds up the repair time since it can automatically communicate with the chassis (when the P is working) and all repair information is directly available. 4. ComPair features TV software up possibilities. Specifications ComPair consists of a Windows based fault finding program and an interface box between PC and the (defective) product. The ComPair II interface box is connected to the PC via an USB cable. For the TV chassis, the ComPair interface box and the TV communicate via a bi-directional cable via the service connector(s). The ComPair fault finding program is able to determine the problem of the defective television, by a combination of automatic diagnostics and an interactive question/answer procedure. How to Connect This is described in the chassis fault finding database in ComPair.
TO TV
TO UART SERVICE CONNECTOR TO I2C SERVICE CONNECTOR TO UART SERVICE CONNECTOR

5.5
5.5.1

Error Codes
Introduction The error code buffer contains all detected errors since the last time the buffer was erased. The buffer is written from left to right, new errors are logged at the left side, and all other errors shift one position to the right. When an error occurs, it is added to the list of errors, provided the list is not full. When an error occurs and the error buffer is full, then the new error is not added, and the error buffer stays intact (history is maintained). To prevent that an occasional error stays in the list forever, the error is removed from the list after more than 50 hrs. of operation. When multiple errors occur (errors occurred within a short time span), there is a high probability that there is some relation between them. New in this chassis is the way errors can be displayed: If no errors are there, the LED should not blink at all in CSM or SDM. No spacer must be displayed as well. There is a simple blinking LED procedure for board level repair (home repair) so called LAYER 1 errors next to the existing errors which are LAYER 2 errors (see Table 5-2). LAYER 1 errors are one digit errors. LAYER 2 errors are 2 digit errors. In protection mode. From consumer mode: LAYER 1. From SDM mode: LAYER 2. Fatal errors, if I2C bus is blocked and the set reboots, CSM and SAM are not selectable. From consumer mode: LAYER 1. From SDM mode: LAYER 2. In CSM mode. When entering CSM: error LAYER 1 will be displayed by blinking LED. Only the latest error is shown. In SDM mode. When SDM is entered via Remote Control code or the hardware pins, LAYER 2 is displayed via blinking LED. Error display on screen. In CSM no error codes are displayed on screen. In SAM the complete error list is shown.

ComPair II RC in RC out

Multi function

Optional Power Link/ Mode Switch Activity

I2C

RS232 /UART

PC

ComPair II Developed by Philips Brugge Optional power 5V DC

HDMI I2C only

10000_036_090121.eps 091118

Figure 5-10 ComPair II interface connection Caution: It is compulsory to connect the TV to the PC as shown in the picture above (with the ComPair interface in between), as the ComPair interface acts as a level shifter. If one connects the TV directly to the PC (via UART), ICs can be blown! How to Order ComPair II order codes: ComPair II interface: 3122 785 91020. Software is available via the Philips Service web portal. ComPair UART interface cable for Q55x.x. (using 3.5 mm Mini Jack connector): 3138 188 75051. Note: When you encounter problems, contact your local support desk.
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Basically there are three kinds of errors: Errors detected by the Stand-by software which lead to protection. These errors will always lead to protection and an automatic start of the blinking LED LAYER 1 error. (see section 5.6 The Blinking LED Procedure). Errors detected by the Stand-by software which not lead to protection. In this case the front LED should blink the involved error. See also section 5.5 Error Codes, 5.5.4 Error Buffer. Note that it can take up several minutes before the TV starts blinking the error (e.g. LAYER 1 error = 2, LAYER 2 error = 15 or 53). Errors detected by main software (MIPS). In this case the error will be logged into the error buffer and can be read out via ComPair, via blinking LED method LAYER 1-2 error, or in case picture is visible, via SAM. 5.5.2 How to Read the Error Buffer Use one of the following methods: On screen via the SAM (only when a picture is visible). E.g.: 00 00 00 00 00: No errors detected 23 00 00 00 00: Error code 23 is the last and only detected error. 37 23 00 00 00: Error code 23 was first detected and error code 37 is the last detected error. Note that no protection errors can be logged in the error buffer.
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content, as this history can give significant information). This to ensure that old error codes are no longer present. If possible, check the entire contents of the error buffer. In some situations, an error code is only the result of another error code and not the actual cause (e.g. a fault in the protection detection circuitry can also lead to a protection). There are several mechanisms of error detection: Via error bits in the status registers of ICs. Via polling on I/O pins going to the stand-by processor. Via sensing of analog values on the stand-by processor or the PNX8550. Via a not acknowledge of an I2C communication. Take notice that some errors need several minutes before they start blinking or before they will be logged. So in case of problems wait 2 minutes from start-up onwards, and then check if the front LED is blinking or if an error is logged.

Via the blinking LED procedure. See section 5.5.3 How to Clear the Error Buffer. Via ComPair.

How to Clear the Error Buffer Use one of the following methods: By activation of the RESET ERROR BUFFER command in the SAM menu. If the content of the error buffer has not changed for 50+ hours, it resets automatically.

5.5.4

Error Buffer In case of non-intermittent faults, clear the error buffer before starting to repair (before clearing the buffer, write down the Table 5-2 Error code overview

Description I2C3 I2C2 I2C4 12V Inverter or display supply PNX51X0 HDMI mux I2C switch Channel dec DVB-S Lnb controller Tuner Main nvm Tuner DVB-S T sensor SSB/set T sensor LED driver/Tcon Display

Monitored Error/ Error Buffer/ Layer 1 Layer 2 by Prot Blinking LED Device 2 2 2 3 3 2/9 2 2 2 2 2 2 2 2 7 5 13 14 18 15 16 17 21 23 24 28 31 34 35 36 42 42 53 64 MIPS MIPS MIPS Stby P Stby P MIPS MIPS MIPS MIPS MIPS MIPS MIPS MIPS MIPS MIPS MIPS Stby P MIPS E E E P P E E E E E E E E E E E P E BL / EB BL / EB BL / EB BL BL EB EB EB EB EB EB EB EB EB EB EB BL BL / EB SSB SSB SSB PNX8550 / / PNX51X0 Sil9x87A PCA9540 STV0903 LNBH23 DTT 71300 STM24C64 STV6110 LM 75 LM 75 PNX8550 Altera

Defective Board SSB SSB SSB SSB Supply Supply 200 Hz board SSB SSB SSB SSB SSB SSB SSB T sensor T sensor SSB Display

PNX doesnt boot (HW cause) 2

PNX doesnt boot (SW cause) 2

Extra Info Rebooting. When a TV is constantly rebooting due to internal problems, most of the time no errors will be logged or blinked. This rebooting can be recognized via a ComPair interface and Hyperterminal (for Hyperterminal settings, see section 5.8 Fault Finding and Repair Tips, 5.8.7 Logging). Its shown that the loggings which are generated by the main software keep continuing. In this case diagnose has to be done via ComPair. Error 13 (I2C bus 3, SSB bus blocked). Current situation: when this error occurs, the TV will constantly reboot due to the blocked bus. The best way for further diagnosis here, is to use ComPair. Error 14 (I2C bus 2, TV set bus blocked). Current situation: when this error occurs, the TV will constantly reboot due to the blocked bus. The best way for further diagnosis here, is to use ComPair. Error 18 (I2C bus 4, Tuner bus blocked). In case this bus is blocked, short the SDM solder paths on the SSB during startup, LAYER error 2 = 18 will be blinked. Error 15 (PNX8550 doesnt boot). Indicates that the main processor was not able to read his bootscript. This error will point to a hardware problem around the PNX8550 (supplies not OK, PNX 8550 completely dead, I2C link between PNX and Stand-by Processor broken, etc...). When error 15 occurs it is also possible that I2C1 bus is blocked (NVM). I2C1 can be indicated in the schematics as follows: SCL-UP-MIPS, SDA-UP-MIPS. LAYER 2 error = 28 will be logged and displayed via the
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Other root causes for this error can be due to hardware problems regarding the DDRs and the bootscript reading from the PNX8550. Error 16 (12V). This voltage is made in the power supply and results in protection (LAYER 1 error = 3) in case of absence. When SDM is activated we see blinking LED LAYER 2 error = 16. Error 17 (Invertor or Display Supply). Here the status of the Power OK is checked by software, no protection will occur during failure of the invertor or display supply (no picture), only error logging. LED blinking of LAYER 1 error = 3 in CSM, in SDM this gives LAYER 2 error = 17. Error 21 (PNX51X0). When there is no I2C communication towards the PNX51X0 after start-up, LAYER 2 error = 21 will be logged and displayed via the blinking LED procedure if SDM is switched on. This device is located on the 200 Hz panel from the display. Error 23 (HDMI). When there is no I2C communication towards the HDMI mux after start-up, LAYER 2 error = 23 will be logged and displayed via the blinking LED procedure if SDM is switched on. Error 24 (I2C switch). When there is no I2C communication towards the I2C switch, LAYER 2 error = 24 will be logged and displayed via the blinking LED procedure when SDM is switched on. Remark: this only works for TV sets with an I2C controlled screen included. Error 28 (Channel dec DVB-S). When there is no I2C communication towards the DVB-S channel decoder, blinking LED procedure if SDM is switched on.

Service Modes, Error Codes, and Fault Finding


Error 31 (Lnb controller). When there is no I2C communication towards this device, LAYER 2 error = 31 will be logged and displayed via the blinking LED procedure if SDM is activated. Error 34 (Tuner). When there is no I2C communication towards the tuner during start-up, LAYER 2 error = 34 will be logged and displayed via the blinking LED procedure when SDM is switched on. Error 35 (main NVM). When there is no I2C communication towards the main NVM during start-up, LAYER 2 error = 35 will be displayed via the blinking LED procedure when SDM is switched on. All service modes (CSM, SAM and SDM) are accessible during this failure, observed in the Uart logging as follows: "<< ERRO >>> PFPOW_.C: First Error (id19, Layer_1= 2 Layer_= 35)". Error 36 (Tuner DVB-S). When there is no I2C communication towards the DVB-S tuner during start-up, LAYER 2 error = 36 will be logged and displayed via the blinking LED procedure when SDM is switched on. Error 42 (Temp sensor). Only applicable for TV sets equipped with temperature devices. Error 53. This error will indicate that the PNX8550 has read his bootscript (when this would have failed, error 15 would blink) but initialization was never completed because of hardware problems (NAND flash, ...) or software initialization problems. Possible cause could be that there is no valid software loaded (try to upgrade to the latest main software version). Note that it can take a few minutes before the TV starts blinking LAYER 1 error = 2 or in SDM, LAYER 2 error = 53. Error 64. Only applicable for TV sets with an I2C controlled screen.

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4. Six short blinks followed by a pause of 3 s 5. One long blink of 3 s to finish the sequence (spacer). 6. The sequence starts again. 5.6.2 How to Activate Use one of the following methods: Activate the CSM. The blinking front LED will show only the latest layer 1 error, this works in normal operation mode or automatically when the error/protection is monitored by the Stand-by processor. In case no picture is shown and there is no LED blinking, read the logging to detect whether error devices are mentioned. (see section 5.8 Fault Finding and Repair Tips, 5.8.7 Logging). Activate the SDM. The blinking front LED will show the entire content of the LAYER 2 error buffer, this works in normal operation mode or when SDM (via hardware pins) is activated when the tv set is in protection.

5.7
5.7.1

Protections
Software Protections Most of the protections and errors use either the stand-by microprocessor or the MIPS controller as detection device. Since in these cases, checking of observers, polling of ADCs, and filtering of input values are all heavily software based, these protections are referred to as software protections. There are several types of software related protections, solving a variety of fault conditions: Related to supplies: presence of the +5V, +3V3 and 1V2 needs to be measured, no protection triggered here. Protections related to breakdown of the safety check mechanism. E.g. since the protection detections are done by means of software, failing of the software will have to initiate a protection mode since safety cannot be guaranteed any more. Remark on the Supply Errors The detection of a supply dip or supply loss during the normal playing of the set does not lead to a protection, but to a cold reboot of the set. If the supply is still missing after the reboot, the TV will go to protection. Protections during Start-up During TV start-up, some voltages and IC observers are actively monitored to be able to optimise the start-up speed, and to assure good operation of all components. If these monitors do not respond in a defined way, this indicates a malfunction of the system and leads to a protection. As the observers are only used during start-up, they are described in the start-up flow in detail (see section 5.3 Stepwise Start-up).

5.6
5.6.1

The Blinking LED Procedure


Introduction The blinking LED procedure can be split up into two situations: Blinking LED procedure LAYER 1 error. In this case the error is automatically blinked when the TV is put in CSM. This will be only one digit error, namely the one that is referring to the defective board (see table 5-2 Error code overview) which causes the failure of the TV. This approach will especially be used for home repair and call centres. The aim here is to have service diagnosis from a distance. Blinking LED procedure LAYER 2 error. Via this procedure, the contents of the error buffer can be made visible via the front LED. In this case the error contains 2 digits (see table 5-2 Error code overview) and will be displayed when SDM (hardware pins) is activated. This is especially useful for fault finding and gives more details regarding the failure of the defective board. Important remark: For an empty error buffer, the LED should not blink at all in CSM or SDM. No spacer will be displayed. When one of the blinking LED procedures is activated, the front LED will show (blink) the contents of the error buffer. Error codes greater then 10 are shown as follows: 1. n long blinks (where n = 1 to 9) indicating decimal digit 2. A pause of 1.5 s 3. n short blinks (where n= 1 to 9) 4. A pause of approximately 3 s, 5. When all the error codes are displayed, the sequence finishes with a LED blink of 3 s (spacer). 6. The sequence starts again. Example: Error 12 8 6 0 0. After activation of the SDM, the front LED will show: 1. One long blink of 750 ms (which is an indication of the decimal digit) followed by a pause of 1.5 s 2. Two short blinks of 250 ms followed by a pause of 3 s 3. Eight short blinks followed by a pause of 3 s
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5.7.2

Hardware Protections The only real hardware protection in this chassis appears in case of an audio problem e.g. DC voltage on the speakers. This protection will only affect the Class D audio amplifier (item 7D10; see diagram B03A) and puts the amplifier in a continuous burst mode (cyclus approximately 2 seconds). Repair Tip There still will be a picture available but no sound. While the Class D amplifier tries to start-up again, the cone of the loudspeakers will move slowly in one or the other direction until the initial failure shuts the amplifier down, this cyclus starts over and over again. The headphone amplifier will also behaves similar.

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+5V-TUN supply voltage (5V nominal) for tuner and IF amplifier.

Fault Finding and Repair Tips


Read also section 5.5 Error Codes, 5.5.4 Error Buffer, Extra Info.

+3V3-STANDY (3V3 nominal) is the permanent voltage, supplying the Stand-by microprocessor inside PNX855xx. Supply voltage +1V1 is started immediately when +12V voltage becomes available (+12V is enabled by STANDBY signal when "low"). Supply voltages +3V3, +2V5, +1V8, +1V2 and +5V-TUN are switched "on" by signal ENABLE-3V3 when "low", provided that +12V (detected via 7U40 and 7U41) is present. +12V is considered OK (=> DETECT2 signal becomes "high", +12V to +1V8, +12V to +3V3, +12V to +5V DC-DC converter can be started up) if it rises above 10V and doesnt drop below 9V5. A small delay of a few milliseconds is introduced between the start-up of 12V to +1V8 DC-DC converter and the two other DC-DC converters via 7U48 and associated components. Description DVB-S2: LNB-RF1 (0V = disabled, 14V or 18V in normal operation) LNB supply generated via the second conversion channel of 7T03 followed by 7T50 LNB supply control IC. It provides supply voltage that feeds the outdoor satellite reception equipment. +3V3-DVBS (3V3 nominal), +2V5-DVBS (2V5 nominal) and +1V-DVBS (1.03V nominal) power supply for the silicon tuner and channel decoder. +1V-DVBS is generated via a 5V to 1V DC-DC converter and is stabilized at the point of load (channel decoder) by means of feedback signal SENSE+1V0-DVBS. +3V3-DVBS and +2V5-DVBS are generated via linear stabilizers from +5V-DVBS that by itself is generated via the first conversion channel of 7T03. At start-up, +24V becomes available when STANDBY signal is "low" (together with +12V for the basic board), when +3V3 from the basic board is present the two DC-DC converters channels inside 7T03 are activated. Initially only the 24V to 5V converter (channel 1 of 7T03 generating +5V-DVBS) will effectively work, while +V-LNB is held at a level around 11V7 via diode 6T55. After 7T05 is initialized, the second channel of 7T03 will start and generates a voltage higher then LNB-RF1 with 0V8. +5VDVBS start-up will imply +3V3-DVBS start-up, with a small delay of a few milliseconds => +2V5-DVBS and +1V-DVBS will be enabled. If +24V drops below +15V level then the DVB-S2 supply will stop, even if +3V3 is still present. Debugging The best way to find a failure in the DC/DC converters is to check their start-up sequence at power on via the mains cord, presuming that the stand-by microprocessor and the external supply are operational. Take STANDBY signal "high"-to-"low" transition as time reference. When +12V becomes available (maximum 1 second after STANDBY signal goes "low") then +1V1 is started immediately. After ENABLE-3V3 goes "low", all the other supply voltages should rise within a few milliseconds. Tips Behaviour comparison with a reference TV550 platform can be a fast way to locate failures. If +12V stays "low", check the integrity of fuse 1U40. Check the integrity (at least no short circuit between drain and source) of the power MOS-FETs before starting up the platform in SDM, otherwise many components might be damaged. Using a ohmmeter can detect short circuits between any power rail and ground or between +12V and any other power rail. Short circuit at the output of an integrated linear stabilizer (7UC0, 7UD2 or 7UD3) will heat up this device strongly. Switching frequencies should be 500 kHz ...600 kHz for 12 V to 1.1 V and 12 V to 1.8 V DC-DC converters,
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5.8.1

Ambilight Due to degeneration process of the LEDs fitted on the ambi module, there can be a difference in the colour and/or light output of the spare ambilight modules in comparison with the originals ones contained in the TV set. Via SAM => alignments => ambilight, the spare module can be adjusted.

5.8.2

Audio Amplifier The Class D-IC 7D10 has a powerpad for cooling. When the IC is replaced it must be ensured that the powerpad is very well pushed to the PWB while the solder is still liquid. This is needed to insure that the cooling is guaranteed, otherwise the Class DIC could break down in short time.

5.8.3

AV PIP To check the AV PIP board (if present) functionality, a dedicated tespattern can be invoke as follows: select the multiview icon in the User Interface and press the OK button. Apply for the main picture an extended source, e.g. HDMI input. Proceed by entering CSM (push 123654 on the remote control) and press the yellow button. A coloured testpattern should appear now, generated by the AV PIP board (this can take a few seconds).

5.8.4

CSM When CSM is activated and there is a USB stick connected to the TV, the software will dump the complete CSM content to the USB stick. The file (Csm.txt) will be saved in the root of the USB stick. If this mechanism works it can be concluded that a large part of the operating system is already working (MIPS, USB...)

5.8.5

DC/DC Converter Description basic board The basic board power supply consists of 4 DC/DC converters and 5 linear stabilizers. All DC/DC converters have +12V input voltage and deliver: +1V1 supply voltage (1.15V nominal), for the core voltage of PNX855xx, stabilized close to the point of load; SENSE+1V1 signal provides the DC-DC converter the needed feedback to achieve this. +1V8 supply voltage, for the DDR2 memories and DDR2 interface of PNX855xx. +3V3 supply voltage (3.30V nominal), overall 3.3 V for onboard ICs, for non-5000 series SSB diversities only. +5V (5.15V nominal) for USB, WIFI and Conditional Access Module and +5V5-TUN for +5V-TUN tuner stabilizer. The linear stabilizers are providing: +1V2 supply voltage (1.2V nominal), stabilized close to PNX855xx device, for various other internal blocks of PNX855xx; SENSE+1V2 signal provides the needed feedback to achieve this. +2V5 supply voltage (2.5V nominal) for LVDS interface and various other internal blocks of PNX855xx; for 5000 series SSB diversities the stabilizer is 7UD2 while for the other diversities 7UC0 is used. +3V3 supply voltage (3V3 nominal) for 5000 series SSB diversities, provided by 7UD3; in this case the 12V to 3V3 DC-DC converter is not present.

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900 kHz for 12 V to 3.3 V and 12 V to 5 V DC-DC converters. The DVB-S2 supply 24 V to 5 V and 24 V to +V LNB DC-DC converters operates at 300 kHz while for 5 V to 1.1 V DC-DC converter 900 kHz is used. 5.8.6 Exit Factory Mode When an F is displayed in the screens right corner, this means the set is in Factory mode, and it normally happens after a new SSB is mounted. To exit this mode, push the VOLUME minus button on the TVs local keyboard for 10 seconds (this disables the continuous mode). Then push the SOURCE button for 10 seconds until the F disappears from the screen. 5.8.7 Logging When something is wrong with the TV set (f.i. the set is rebooting) you can check for more information via the logging in Hyperterminal. The Hyperterminal is available in every Windows application via Programs, Accessories, Communications, Hyperterminal. Connect a ComPair UARTcable (3138 188 75051) from the service connector in the TV to the multi function jack at the front of ComPair II box. Required settings in ComPair before starting to log: - Start up the ComPair application. - Select the correct database (open file Q55X.X, this will set the ComPair interface in the appropriate mode). - Close ComPair After start-up of the Hyperterminal, fill in a name (f.i. logging) in the Connection Description box, then apply the following settings: 1. COMx 2. Bits per second = 115200 3. Data bits = 8 4. Parity = none 5. Stop bits = 1 6. Flow control = none During the start-up of the TV set, the logging will be displayed. This is also the case during rebooting of the TV set (the same logging appears time after time). Also available in the logging is the Display Option Code (useful when there is no picture), look for item DisplayRawNumber in the beginning of the logging. Tip: when there is no picture available during rebooting you are able to check for error devices in the logging (LAYER 2 error) which can be very helpful to determine the failure cause of the reboot. For protection state, there is no logging. 5.8.8 Guidelines Uart logging Description possible cases: Uart loggings are displayed: When Uart loggings are coming out, the first conclusion we can make is that the TV set is starting up and communication with the flash RAM seems to be supported. The PNX855xx is able to read and write in the DRAMs. We can not yet conclude : Flash RAM and DRAMs are fully operational/reliable.There still can be errors in the data transfers, DRAM erros, read/write speed and timing control. No Uart logging at all: In case there is no Uart logging coming out, check if the startup script can be send over the I2C bus (3 trials to startup) + power supplies are switched on and stable. No startup will end up in a blinking LED status : error LAYER 1 = 2, error LAYER 2 = 53 (startup with SDM solder paths short). Error LAYER 2 = 15 (hardware cause) is more related to a supply issue while error LAYER 2 = 53 (software cause) refers more to boot issues.

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Uart loggings reporting fault conditions, error messages, error codes, fatal errors: Failure messages should be checked and investigated.For instance fatal error on the PNX51x0: check startup of the back-end processor, supplies..reset, I2C bus. => error mentioned in the logging as: *51x0 failed to start by itself*. Some failures are indicated by error codes in the logging, check with error codes table (see Table 5-2 Error code overview).e.g. => <<<ERROR>>>PLFPOW_MERR.C : First Error (id=10,Layer_1=2,Layer_2=23). I2C bus error mentioned as e.g.: I2C bus 4 blocked. Not all failures or error messages should be interpreted as fault.For instance root cause can be due to wrong option codes settings => e.g. DVBS2Suppoprted : False/True. In the Uart log startup script we can observe and check the enabled loaded option codes. Defective sectors (bad blocks) in the Nand Flash can also be reported in the logging. Startup in the SW upgrade application and observe the Uart logging: Starting up the TV set in the Manual Software Upgrade mode will show access to USB, meant to copy software content from USB to the DRAM.Progress is shown in the logging as follows: cosupgstdcmds_mcmdwritepart: Programming 102400 bytes, 40505344 of 40607744 bytes programmed. Startup in Jett Mode: Check Uart logging in Jet mode mentioned as : JETT UART READY. Uart logging changing preset: => COMMAND: calling DFB source = RC6, system=0, key = 4.

5.8.9

Loudspeakers Make sure that the volume is set to minimum during disconnecting the speakers in the ON-state of the TV. The audio amplifier can be damaged by disconnecting the speakers during ON-state of the set!

5.8.10 PSL In case of no picture when CSM (test pattern) is activated and backlight doesnt light up, its recommended first to check the inverter on the PSL + wiring (LAYER 2 error = 17 is displayed in SDM). 5.8.11 Tuner Attention: In case the tuner is replaced, always check the tuner options! 5.8.12 Display option code Attention: In case the SSB is replaced, always check the display option code in SAM, even when picture is available. Performance with the incorrect display option code can lead to unwanted side-effects for certain conditions. New in this chassis: While in the download application (start up in TV mode + OK button pressed), the display option code can be changed via 062598 HOME XXX special SAM command (XXX=display option in 3 digits).

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5.

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Service Modes, Error Codes, and Fault Finding

5.8.13 SSB Replacement Follow the instructions in the flowchart in case a SSB has to be exchanged. See figure SSB replacement flowchart.
In st ru ct io n n o t e SSB rep lacem en t Q543.x, Q548.x, Q549.x, and Q55x.x

Before starting: - prepare a USB memory stick with the latest software - download the latest Main Software (Fus) from www.p4c.philips.com - unzip this file - create a folder upgrades in the root of a USB stick (size > 50 MB) and save the autorun.upg file in this "upgrades" folder. Note: it is possible to rename this file, e.g."Q54x_SW_version.upg"; this in case there are more than one "autorun.upg" files on the USB stick.

ST AR T

Set is still oper ating? No Yes

C onnect the U SB stick to the set, go to SAM and save the current TV settings via Upload to USB 1. D isconnect the WiF i module fr om the PC I connector (only for Q549.x SSB) 2. Replace the SSB by a Service SSB. 3. Place the WiFi module in the PCI connector. 4. Mount the Service SSB in the set.

Start-up the set Due to a possible wrong display option code in the received Service SSB (NVM), its possible that no picture is displayed. Due to this the download application will not be shown either. This tree enables you to load the main software step-by-step via the UART logging on the PC (this for visual feedback). No pictur e displayed

Set behaviour?

Pictur e displayed Set is starting up without software upgrade menu appearing on screen

1) Start up the TV set, equiped with the Service SSB, and enable the UART logging on the PC. 2) The TV set will start-up automatically in the download application if main TV software is not loaded.

Pictur e displayed Set is starting up with software upgrade menu appearing on screen

3) Plug the prepared USB stick into the TV set. Follow the instructions in the UART log file, press Right cursor key to enter the list. Navigate to the autorun.upg file in the UART logging printout via the cursor keys on the remote control. When the correct file is selected, press Ok.

1) Plug the USB stick into the TV set and select the autorun .upg file in the displayed browser.

2) Now the main software will be loaded automatically, supported by a progress bar. 4) Press "Down" cursor and Ok to start flashing the main TV software. Printouts like: L: 1-100%, V: 1-100% and P: 1-100% should be visible now in the UART logging. 3) Wait until the message Operation successful ! is displayed and remove all inserted media. Restart the TV set.

5) Wait until the message Operation successful ! is logged in the UART log and remove all inserted media. Restart the TV set.

Set the correct Display code via 062598 -HOME- xxx where xxx is the 3 digit display panel code (see sticker on the side or bottom of the cabinet)

After entering the Display Option code, the set is going to Standby (= validation of code) Restart the set

No

Connect PC via the ComPair interface to Service connector.

Saved settings on USB stick?

Start TV in Jett mode (DVD I + (OSD)) Open ComPair browser Q54x

Yes
In case of settings reloaded from USB, the set type, serial number, display 12 NC, are automatically stored when entering display options.

Go to SAM and reload settings via Download from USB function. Program set type number, serial number, and display 12 NC Program E - DFU if needed. If not already done: Check latest software on Service website. Update main and Stand-by software via USB.

- Check if correct display option code is programmed. - Verify option codes according to sticker inside the set. - Default settings for white drive > see Service Manual.

Attention point for Net TV: If the set type and serial number are not filled in, the Net TV functionality will not work. It will not be possible to connect to the internet.

Check and perform alignments in SAM according to the Service Manual. Option codes, colour temperature, etc.

Final check of all menus in CSM. Special attention for HDMI Keys and Mac address. Check if E - D F U is present.

End

Q54x.E SSB Board swap VDS Updated 22-03-2010

H_16771_007a.eps 100402

Figure 5-11 SSB replacement flowchart

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Service Modes, Error Codes, and Fault Finding

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5.

EN 33

Set is st art in g u p in F act o ry m o d e

Set is starting up in F actory m ode?

Noisy picture with bands/lines is visible and the RED LED is continuous on.

An F is displayed (and the HDMI 1 input is displayed).

- Press the volume minus button on the TVs local keyboard for 5 ~10 seconds - Press the SOURCE button for 10 seconds until the F disappears from the screen or the noise on the screen is replaced by blue mute

The noise on the screen is replaced with the blue mute or the F is disappeared!

Unplug the mains cord to verify the correct disabling of the Factory mode.

Program display option code via 062598 MENU, followed by the 3 digits code of the display (this code can be found on a sticker on - or inside - the set).

After entering display option code, the set is going in stand-by mode (= validation of code)

R estart the set

H_16771_007b.eps 100322

Figure 5-12 SSB replacement flowchart - Factory mode

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5.

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Service Modes, Error Codes, and Fault Finding

18753_211_100811.eps 100811

Figure 5-13 SSB start-up

5.9

Software Upgrading
Attention! Software version numbers for 2011 sets are all defined below number 0.40.x.x. This might confuse servicers who store software versions for more than one set and/or platform on the same storage device (USB stick). Always check the latest software version on the servicer website in relation to the correct CTN!!! 5.9.2

For the correct order number of a new SSB, always refer to the Spare Parts list! Main Software Upgrade The UpgradeAll.upg file is only used in the factory.

5.9.1

Introduction The set software and security keys are stored in a NANDFlash, which is connected to the PNX855xx. It is possible for the user to upgrade the main software via the USB port. This allows replacement of a software image in a stand alone set, without the need of an E-JTAG debugger. A description on how to upgrade the main software can be found in the electronic User Manual. Important: When the NAND-Flash must be replaced, a new SSB must be ordered, due to the presence of the security keys! (CI +, MAC address, ...). Perform the following actions after SSB replacement: 1. Set the correct option codes (see sticker inside the TV). 2. Update the TV software => see the eUM (electronic User Manual) for instructions. 3. Perform the alignments as described in chapter 6 (section 6.5 Reset of Repaired SSB). 4. Check in CSM if the CI + key, MAC address.. are valid.

Automatic Software Upgrade In normal conditions, so when there is no major problem with the TV, the main software and the default software upgrade application can be upgraded with the AUTORUN.UPG (FUS part of the one-zip file: e.g. 3104 337 05661 _FUS _Q555X_ x.x.x.x_prod.zip). This can also be done by the consumers themselves, but they will have to get their software from the commercial Philips website or via the Software Update Assistant in the user menu (see eUM). The autorun.upg file must be placed in the root of the USB stick. How to upgrade: 1. Copy AUTORUN.UPG to the root of the USB stick. 2. Insert USB stick in the set while the set is operational. The set will restart and the upgrading will start automatically. As soon as the programming is finished, a message is shown to remove the USB stick and restart the set. Manual Software Upgrade In case that the software upgrade application does not start automatically, it can also be started manually. How to start the software upgrade application manually: 1. Disconnect the TV from the Mains/AC Power. 2. Press the OK button on a Philips TV remote control or a Philips DVD RC-6 remote control (it is also possible to use

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Service Modes, Error Codes, and Fault Finding


a TV remote in DVD mode). Keep the OK button pressed while reconnecting the TV to the Mains/AC Power. 3. The software upgrade application will start. Attention! In case the download application has been started manually, the autorun.upg will maybe not be recognized. What to do in this case: 1. Create a directory UPGRADES on the USB stick. 2. Rename the autorun.upg to something else, e.g. to software.upg. Do not use long or complicated names, keep it simple. Make sure that AUTORUN.UPG is no longer present in the root of the USB stick. 3. Copy the renamed upg file into this directory. 4. Insert USB stick into the TV. 5. The renamed upg file will be visible and selectable in the upgrade application. Back-up Software Upgrade Application If the default software upgrade application does not start (could be due to a corrupted boot sector) via the above described method, try activating the back-up software upgrade application. How to start the back-up software upgrade application manually: 1. Disconnect the TV from the Mains/AC Power. 2. Press the CURSOR DOWN-button on a Philips TV remote control while reconnecting the TV to the Mains/AC Power. 3. The back-up software upgrade application will start. 5.9.3 Stand-by Software Upgrade via USB In this chassis it is possible to upgrade the Stand-by software via a USB stick. The method is similar to upgrading the main software via USB. Use the following steps: 1. Create a directory UPGRADES on the USB stick. 2. Copy the Stand-by software (part of the one-zip file, e.g. StandbyFactory_88.0.0.0.upg) into this directory. 3. Insert the USB stick into the TV. 4. Start the download application manually (see section Manual Software Upgrade. 5. Select the appropriate file and press the OK button to upgrade. 5.9.4 Content and Usage of the One-Zip Software File Below the content of the One-Zip file is explained, and instructions on how and when to use it. AmbiCpld_Q55XX_x.x.x.x_prod.zip. Contains the program instruction and software content, needed to upgrade the ambilight CPLD on the TV550 platform. BalanceFPGA_Q555X_x.x.x.x_prod.zip. Contains the BalanceFPGA software in upg format. FUS_Q555X_x.x.x.x_prod.zip. Contains the autorun.upg which is needed to upgrade the TV main software and the software download application. PNX5130UPG_Q555X_x.x.x.x_prod.zip. Contains the PNX5130 software in upg format. StandbySW_Q555X_x.x.x.x_prod.zip. Contains the StandbyFactory software in upg format. ProcessNVM_Q55XX_x.x.x.x_prod.zip. Default NVM content. Must be programmed via ComPair or can be loaded via USB, be aware that all alignments stored in NVM are overwritten here. 5.9.5 UART logging 2K10 (see section 5.8 Fault Finding and Repair Tips, 5.8.7 Logging)

Q552.2E LA

5.

EN 35

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EN 36

6.

Q552.2E LA

Alignments

6. Alignments
Index of this chapter: 6.1 General Alignment Conditions 6.2 Hardware Alignments 6.3 Software Alignments 6.4 Option Settings 6.5 Reset of Repaired SSB 6.6 Total Overview SAM modes EU/AP-PAL models: a PAL B/G TV-signal with a signal strength of at least 1 mV and a frequency of 475.25 MHz US/AP-NTSC models: an NTSC M/N TV-signal with a signal strength of at least 1 mV and a frequency of 61.25 MHz (channel 3). LATAM models: an NTSC M TV-signal with a signal strength of at least 1 mV and a frequency of 61.25 MHz (channel 3).

6.1

General Alignment Conditions


Perform all electrical adjustments under the following conditions: Power supply voltage (depends on region): AP-NTSC: 120 VAC or 230 VAC / 50 Hz ( 10%). AP-PAL-multi: 120 - 230 VAC / 50 Hz ( 10%). EU: 230 VAC / 50 Hz ( 10%). LATAM-NTSC: 120 - 230 VAC / 50 Hz ( 10%). US: 120 VAC / 60 Hz ( 10%). Connect the set to the mains via an isolation transformer with low internal resistance. Allow the set to warm up for approximately 15 minutes. Measure voltages and waveforms in relation to correct ground (e.g. measure audio signals in relation to AUDIO_GND). Caution: It is not allowed to use heat sinks as ground. Test probe: Ri > 10 M, Ci < 20 pF. Use an isolated trimmer/screwdriver to perform alignments.

6.3.1

White Point Choose TV menu, Setup, More TV Settings and then Picture and set picture settings as follows:
100 50 0 Off Unscaled

Picture Setting Contrast Brightness Colour Light Sensor Picture format

In menu Picture, choose Pixel Plus HD and set picture settings as follows:
Off Off Off 0

Picture Setting Dynamic Contrast Dynamic Backlight Colour Enhancement Gamma

6.1.1 Alignment Sequence First, set the correct options: In SAM, select Option numbers. Fill in the option settings for Group 1 and Group 2 according to the set sticker (see also paragraph 6.4 Option Settings). Press OK on the remote control before the cursor is moved to the left. In submenu Option numbers select Store and press OK on the RC. OR: In main menu, select Store again and press OK on the RC. Switch the set to Stand-by. Warming up (>15 minutes).

Go to the SAM and select Alignments-> White point.

White point alignment LCD screens: Use a 100% white screen (format: 720p50) to the HDMI input and set the following values: Colour temperature: Cool. All White point values to: 127. In case you have a colour analyser: Measure, in a dark environment, with a calibrated contactless colour analyser (Minolta CA-210 or Minolta CS-200) in the centre of the screen and note the x, y value. Change the pattern to 90% white screen. If a Quantum Data generator is used, select the GreyAll test pattern at level = 230. Adjust the correct x, y coordinates (while holding one of the White point registers R, G or B on 127) by means of decreasing the value of one or two other white points to the correct x, y coordinates (see Table 6-1 White D alignment values - LED - Minolta CA-210, or 6-2 White D alignment values - LED - Minolta CS-200). Tolerance: dx: 0.002, dy: 0.002. Repeat this step for the other colour temperatures that need to be aligned. When finished press OK on the RC and then press STORE (in the SAM root menu) to store the aligned values to the NVM. Restore the initial picture settings after the alignments. Table 6-1 White D alignment values - LED - Minolta CA-210
Value x y Cool (9420K) 0.282 0.298 Normal (8120K) 0.292 0.311 Warm (6080K) 0.320 0.345

6.2

Hardware Alignments
Not applicable.

6.3

Software Alignments
Put the set in SAM mode (see Chapter 5. Service Modes, Error Codes, and Fault Finding). The SAM menu will now appear on the screen. Select ALIGNMENTS and go to one of the sub menus. The alignments are explained below. The following items can be aligned: White point Ambilight. To store the data: Press OK on the RC before the cursor is moved to the left In main menu select Store and press OK on the RC Switch the set to stand-by mode. For the next alignments, supply the following test signals via a video generator to the RF input:
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Table 6-2 White D alignment values - LED - Minolta CS-200


Value x y Cool (11000K) 0.276 0.282 Normal (9000K) 0.287 0.296 Warm (6500K) 0.313 0.329

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Alignments
If you do not have a colour analyser, you can use the default values. This is the next best solution. The default values are average values coming from production. Select a COLOUR TEMPERATURE (e.g. COOL, NORMAL, or WARM). Set the RED, GREEN and BLUE default values according to the values in Table 6-3 to Table 6-5. When finished press OK on the RC, then press STORE (in the SAM root menu) to store the aligned values to the NVM. Restore the initial picture settings after the alignments. Table 6-3 White tone default setting 32" (Blockbuster)
White Tone Normal Cool Warm e.g. 32PFL6606x G t.b.d. t.b.d. t.b.d. B t.b.d. t.b.d. t.b.d. t.b.d. t.b.d. t.b.d.

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EN 37

6.4.4

Opt. No. (Option numbers) Select this sub menu to set all options at once (expressed in two long strings of numbers). An option number (or option byte) represents a number of different options. When you change these numbers directly, you can set all options very quickly. All options are controlled via eight option numbers. When the NVM is replaced, all options will require resetting. To be certain that the factory settings are reproduced exactly, you must set both option number lines. You can find the correct option numbers on a sticker inside the TV set. Example: The options sticker gives the following option numbers: 08192 00133 01387 45160 12232 04256 00164 00000 The first line (group 1) indicates hardware options 1 to 4, the second line (group 2) indicate software options 5 to 8. Every 5-digit number represents 16 bits (so the maximum value will be 65536 if all options are set). When all the correct options are set, the sum of the decimal values of each Option Byte (OB) will give the option number. Diversity Not all sets with the same Commercial Type Number (CTN) necessarily have the same option code! Use of Alternative BOM => an alternative BOM number usually indicates the use of an alternative display or power supply. This results in another display code thus in another Option code. Refer to Chapter 2. Technical Specifications, Diversity, and Connections.

Colour Temp R

Table 6-4 White tone default setting 37" (Blockbuster)


White Tone Normal Cool Warm e.g. 37PFL6606x G 118 106 110 B 127 127 88 126 112 127

Colour Temp R

Table 6-5 White tone default setting 40" (Blockbuster)


White Tone Normal Cool Warm e.g. 40PFL6606x G t.b.d. t.b.d. t.b.d. B t.b.d. t.b.d. t.b.d. t.b.d. t.b.d. t.b.d.

Colour Temp R

6.4.5

Option Code Overview Refer to the sticker in the set for the correct option codes. Important: after having edited the option numbers as described above, you must press OK on the remote control before the cursor is moved to the left!

6.4
6.4.1

Option Settings
Introduction The microprocessor communicates with a large number of I C ICs in the set. To ensure good communication and to make digital diagnosis possible, the microprocessor has to know which ICs to address. The presence / absence of these PNX51XX ICs (back-end advanced video picture improvement IC which offers motion estimation and compensation features (commercially called HDNM) plus integrated Ambilight control) is made known by the option codes. Notes: After changing the option(s), save them by pressing the OK button on the RC before the cursor is moved to the left, select STORE in the SAM root menu and press OK on the RC. The new option setting is only active after the TV is switched off / stand-by and on again with the mains switch (the NVM is then read again).
2

6.5

Reset of Repaired SSB


A very important issue towards a repaired SSB from a Service repair shop (SSB repair on component level) implies the reset of the NVM on the SSB. A repaired SSB in Service should get the service Set type 00PF0000000000 and Production code 00000000000000. Also the virgin bit is to be set. To set all this, you can use the ComPair tool or use the NVM editor and Dealer options items in SAM (do not forget to store). After a repaired SSB has been mounted in the set (set repair on board level), the type number (CTN) and production code of the TV has to be set according to the type plate of the set. For this, you can use the NVM editor in SAM. This action also ensures the correct functioning of the Net TV feature and access to the Net TV portals. The loading of the CTN and production code can also be done via ComPair (Model number programming). After a SSB repair, the original channel map can be restored, provided that the original channel map was stored on a USB stick before repair was commenced and that basic functionality of the TV, needed for this procedure, was not hampered as a result of the defect. The procedure of channel map cloning is clearly described in the (electronic) user manual. In case of a display replacement, reset the Operation hours display to 0, or to the operation hours of the replacement display.

6.4.2

Dealer Options For dealer options, in SAM select Dealer options. See Table 6-6 SAM mode overview.

6.4.3

(Service) Options From 2011 onwards, it is not longer possible to change individual option settings in SAM. Options can only be changed all at once by using the option codes as described in section 6.4.4.

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EN 38
6.5.1

6.

Q552.2E LA

Alignments

SSB identification Whenever ordering a new SSB, it should be noted that the correct ordering number (12nc) of a SSB is located on a sticker on the SSB. The format is <12nc SSB><serial number>. The ordering number of a Service SSB is the same as the ordering number of an initial factory SSB.

18310_221_090318.eps 090319

Figure 6-1 SSB identification

6.6

Total Overview SAM modes


Table 6-6 SAM mode overview
Main Menu Hardware Info Sub-menu 1 A. SW version C. Production code Operation hours Errors Reset error buffer Alignment White point Colour temperature Normal Warn Cool White point red White point green White point blue Ambilight Select module Brightness Select matrix Dealer options Virgin mode Off/On Select Virgin mode On/Off. TV starts up / does not start up (once) with a language selection menu after the mains switch is turned on for the first time (virgin mode) Select E-sticker On/Off (USPs on-screen) LCD White Point Alignment. For values, see Table 6-3 White tone default setting 32" (Blockbuster) to 6-5 White tone default setting 40" (Blockbuster) Sub-menu 2 e.g. Q5551_0.9.1.0 e.g. see type plate Displays the accumulated total of operation hours.TV switched on/off & every 0.5 hours is increase one Displayed the most recent errors Clears all content in the error buffer 3 different modes of colour temperature can be selected Sub-menu 3 Description Display TV & Stand-by SW version and CTN serial number

B. Stand-by processor version e.g. STDBY_83.84.0.0

E-sticker Auto store mode

Off/On None PDC/VPS TXT page PDC/VPS/TXT

Option numbers

Group 1 Group 2 Store

e.g. 00008.00001.15421.02239 e.g. 44816.34311.33024.00000

The first line (group 1) indicates hardware options 1 to 4 The second line (group 2) indicates software options 5 to 8 Store after changing N.A. Select Store in the SAM root menu after making any changes

Initialise NVM Store Operation hours display 0003

In case the display must be swapped for repair, you can reset the Display operation hours to 0. So, this one does keeps up the lifetime of the display itself (mainly to compensate the degeneration behaviour) Display information is for development purposes

Software maintenance

Software events

Display Clear Test reboot Test cold reboot Test application crash

Hardware events

Display Clear

Display information is for development purposes

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Alignments
Main Menu Test setting Sub-menu 1 Digital info Sub-menu 2 Current frequency: 538 QAM modulation: 64-qam Symbol rate: Original network ID: 12871 Network ID: 12871 Transport stream ID: 2 Service ID: 3 Hierarchical modulation: 0 Selected video PID: 35 Selected main audio PID: 99 Selected 2nd audio PID: 8191 Install start frequency Install end frequency Default install frequency Installation Development file versions Development 1 file version Digital only Digital + Analogue Display parameters DISPT5.0.9.29 Acoustics parameters ACSTS 5.0.6.20 PQ - TV550 1.0.27.22 PQS- Profile set PQF - Fixed settings PQU - User styles Ambilight parameters PRFAM 5.0.5.2 Development 2 file version 12NC one zip software Initial main software NVM version Q55x1_0.4.5.0 Flash units software Temp com file version none Upload to USB Channel list Personal settings Option codes Alignments Identification data History list All (options included) Download from USB Channel list Personal settings Option codes Alignments Identification data All (options included) NVM editor Type number AG code see type plate see type plate 000 999 Sub-menu 3

Q552.2E LA
Description

6.

EN 39

Display information is for development purposes

Install start frequency from 0 MHz Install end frequency as 999 MHz Select Digital only or Digital + Analogue before installation Display information is for development purposes

Display information is for development purposes

To upload several settings from the TV to an USB stick

To download several settings from the USB stick to the TV

NVM editor; re key-in type number and production code after SSB replacement

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EN 40

7.

Q552.2E LA

Circuit Descriptions

7. Circuit Descriptions
Index of this chapter: 7.1 Introduction 7.2 Power Supply 7.3 DC/DC Converters 7.4 Front-End Analogue and DVB-T, DVB-C; ISDB-T reception 7.5 Front-End DVB-S(2) reception 7.6 HDMI 7.7 Video and Audio Processing - PNX855xx Notes: Only new circuits (circuits that are not published recently) are described. Figures can deviate slightly from the actual situation, due to different set executions. For a good understanding of the following circuit descriptions, please use the wiring-, block- (see chapter 9. Block Diagrams) and circuit diagrams (see chapter 10. Circuit Diagrams and PWB Layouts).Where necessary, you will find a separate drawing for clarification. 7.1.1 implementation of passive 3D removal of TCON from the SSB (comes with the display) changed power architecture new USB hub (for Sundance xxPFL76xx/xx sets).

The Q552.2E LA chassis comes with the following stylings: Blockbuster (series xxPFL66xx), Sundance (series xxPFL76xx). Implementation Key components of this chassis are: PNX855xx System-On-Chip (SOC) TV Processor TX26xx Hybrid Tuner (DVB-T/C, analogue) STV6110AT DVB-S Satellite Tuner SII9x87 HDMI Switch TPA312xD2PWP Class D Power Amplifier LAN8710 Dual Port Gigabit Ethernet media access controller. 7.1.2 TV550 Architecture Overview For details about the chassis block diagrams refer to chapter 9. Block Diagrams. An overview of the TV550 2011 architecture can be found in Figure 7-1.

7.1

Introduction
The Q552.2E LA is part of the TV550 platform, is a derivative from the Q552.1E LA and uses the (same) PNX855xx chipset. The major deltas versus its predecessor Q551 are: support of DVB-T2 (second generation DVBT)

FLASH 512MB DDR2 4x 128MB -533


32

NVM 8kB

SPI 64kB

LVDS only
Matrix FHD@120p FHD@100p

Hybrid Tuner DVB-S2 Tuner

DVB-T (EU) DVB-C (EU+HK)

NXP PNX85500 SOC

DVB-S2 (EU)

AL

CPLD

HDMI 1.3 mux Ethernet PHY


1V1 1V8 2V5 3V3 5V

CLASS-D

Stdby

3V3

USB

3D

buffer
WIFI

DC/DC

CI

IR

SD-CARD

19100_059_110217.eps 110217

Figure 7-1 Architecture of TV550 platform 2011

2011-Feb-18

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Circuit Descriptions
7.1.3 SSB Cell Layout

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7.

EN 41

1M95

1M99

1M59

DVB-S DC/DC

DC/DC C
1M71

Ambilight CPLD

DDR2
1G50

PCMCIA

LONG

FLASH

CD
DDR2
LVDS-OUT

DVB-S2

Tuner

DDR

CA PNX85500 M1 27x27 1.00mm

TS-IN USB HDMI GPIO STDBY

DVB-S DC/DC

DDR2
1735

ETH
IS SPDIF

Heatsink
ANA AUD ANA VID

SD-SLOT
DDR2
1F24

1D38

USB2.0
1G51

SCART1/YPbPr
1E32
7E01

SVC

Hybrid Tuner
Pb Pr
O U T

1M21

Process Support Wire

L/R

1M20

91 87

SPDIF Output

19100_058_110217.eps 110217

Figure 7-2 SSB layout cells (top view)

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Head Phone HDMI

F-type 13.65mm

VGA

Class-D

C TR L

3D

HDMI

HDMI

HDMI

EN 42 7.2
7.2.1

7.

Q552.2E LA

Circuit Descriptions
Table 7-3 Connector overview 40" sets
Connector no. 1308 Mains CN1 N L 1316 to display CN2 Anode 1+ n.c. Cathode 1n.c. Anode 2+ n.c. Cathode 2n.c. Anode 3+ n.c. Cathode 3n.c. Anode 4+ n.c. Cathode 41M95 to SSB CN4 +3V3stdby Standby GND1 GND1 +12V +12V +Vsnd (+24V) GND_SND BL-ON-OFF BL-DIM1 (Vsync) BL-I-CTRL POK +24V (AL2_DVBS) GND1 Descr. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1M95 to SSB CN4 +3V3SB Standby GND1 GND1 +12V3 +12V3 +Vsnd GND1 BL-ON-OFF BL-DIM1 BL-I-CTRL POK +24V GND1 -

Power Supply
Power Supply Unit All power supplies are a black box for Service. When defective, a new board must be ordered and the defective one must be returned, unless the main fuse of the board is broken. Always replace a defective fuse with one with the correct specifications! This part is available in the regular market. Consult the Philips Service web portal for the order codes of the boards. In this manual, no detailed information is available because of design protection issues.

7.2.2

Connector overview Blockbuster (series xxPFL6600/xx) Table 7-1 Connector overview 32" sets
Connector no. Descr. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1308 Mains CN1 N L 1316 to display CN2 A2 n.c. pin 5 n.c. pin 3 n.c. OCD n.c. A1 n.c. pin 13 n.c. pin 11 n.c. GND1

7.3

DC/DC Converters
The on-board DC/DC converters deliver the following voltages (depending on set execution): +3V3-STANDBY, permanent voltage for the Stand-by controller, LED/IR receiver and controls; connector 1M95 pin 1 +12V, input from the power supply for TV550 common (active mode); connector 1M95 pins 6, 7 and 8 +24V, input from the power supply for DVB-S2 (in active mode); connector 1M09 pins 1 and 2 +1V1, core voltage supply for PNX855xx; has to be started up first and switched "off" last (diagram B03B) +1V2, supply voltage for analogue blocks inside PNX855xx +1V8, supply voltage for DDR2 (diagram B03B) +2V5, supply voltage for analogue blocks inside PNX855xx (see diagram B03E) +3V3, general supply voltage (diagram B03E) +5V, supply voltage for USB and CAM (diagram B03E) +5V-TUN, supply voltage for tuner (diagram B03E) +V-LNB, input voltage for LNB supply IC (item no. 7T50) +5V-DVBS, input intermediate supply voltage for DVB-S2 (diagram B08A) +3V3-DVBS, clean voltage for silicon tuner and DVB-S2 channel decoder +2V5-DVBS, clean voltage for DVB-S2 channel decoder +1V-DVBS, core voltage for DVB-S2 channel decoder. A +12 V under-voltage detector (see diagram B03C) enables the 12V to 3.3V and 12V to 5V DC/DC converters via the ENABLE-3V3-5V line, and the 12V to 1.8V DC/DC converter via the ENABLE-1V8 line. DETECT2 is the signal going to the Stand-by microcontroller and ENABLE-3V3n is the signal coming from the Stand-by microcontroller. Diagram B03D contains the following linear stabilisers: +2V5 stabiliser, built around item no. 7UCO +5V-TUN stabiliser, built around items no. 7UA6 and 7UA7 +1V2 stabiliser, built around items no. 7UA3 and 7UA4. Diagram B08A contains the DVB-S2-related DC/DC converters and -stabilisers: a +24V under-voltage detection circuitry is built around item no. 7T04 the switching frequency of the 24 to 14...20V switched mode converter is 350 kHz (item no. 7T03 and +V-LNB lines) the output signal on the +V-LNB line goes to the LNBH23Q (item no. 7T50) the LNBH23Q (item no. 7T50) sends a feedback signal via the V0-CNTRL line

Table 7-2 Connector overview 37" sets


Connector no. Descr. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1308 Mains CN1 N L 1316 to display CN2 Anode_R n.c. R5 Cathode R4 Cathode R3 Cathode R2 Cathode R1 Cathode L1 Cathode L2 Cathode L3 Cathode L4 Cathode L5 Cathode n.c. Anode_L 1M95 to SSB CN4 +3V3stdby Standby GND1 GND1 +12V +12V +Vsnd (+24V) GND_SND BL-ON-OFF BL-DIM1 (Vsync) BL-I-CTRL POK +24V (AL2_DVBS) GND1 -

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Circuit Descriptions
the switching frequency of the +5V-DVBS to +1-DVBS switched mode converter is 900 kHz (item no. 7T00) a delay line for the +2V5-DVBS and +1V-DVBS lines is created with item no. 3T03 (R=10k) and 2T06 (C=100n) a 3.3V to 2.5V linear stabiliser is built around item no. 7T01 a 5V to 3.3V linear stabiliser is built around item no. 7T02.

Q552.2E LA

7.

EN 43

7.5

Front-End DVB-S(2) reception


The Front-End for the DVB-S(2) application consist of the following key components: Satellite Tuner; I2C address 0xC6 (bridged via channel decoder) Channel decoder; I2C address 0xD0 LNB switching regulator; I2C address 0x14 Amplifier PNX855xx SoC TV processor with integrated DVB-T and DVB-C channel decoder and analogue demodulator.

Diagram B08B contains the DVB-S2 LNB supply: the +V-LNB signal comes from item no. 7T03 the V0-CTRL signal goes to item no. 7T03 the LNB-RF1 goes to the LNB. Figures gives a graphical representation of the DC/DC converters with its current consumptions:
+ 5V 5-TUN 196 m A + 5V dc -dc + 5V 2179 m A + 5V 5-TUN + 5V -TUN s tabiliz er + 5V -TUN 196 m A

Below find a block diagram of the front-end application for DVB-S(2) reception.

+ 12V 2919 m A

+ 3V 3 dc -dc

+ 3V 3 2371 m A

+ 3V 3

+ 2V 5 s tabiliz er

+ 2V 5 450 m A

+ 1V 8 dc -dc

+ 1V 8 2450 m A

+ 1V 8

+ 1V 2 s tabiliz er

+ 1V 2 550 m A

+ 1V 1 dc -dc

+ 1V 1 5100 m A

18770_226_100127.eps 100426

18770_237_100127.eps 100219

Figure 7-3 DC/DC converters

Figure 7-5 Front-End block diagram DVB-S(2) reception This application supports the following protocols: Polarization selection via supply voltage (18V = horizontal, 13V = vertical) Band selection via toneburst (22 kHz): tone on = high band, tone off = low band Satellite (LNB) selection via DiSEqC 1.0 protocol Reception of DVB-S (supporting QPSK encoded signals) and DVB-S2 (supporting QPSK, 8PSK, 16APSK and 32APSK encoded signals), introducing LDPC low-density parity check techniques.

7.4

Front-End Analogue and DVB-T, DVB-C; ISDB-T reception


European/China region The Front-End for the European/China region consist of the following key components: Hybrid Tuner Switchable SAW filter 7/8 MHz (Eur.), or single SAW filter (8 MHz) (China) Bandpass filter Amplifier PNX855xx SoC TV processor with integrated DVB-T and DVB-C channel decoder and analogue demodulator.

7.4.1

7.6

HDMI
In this platform, the Silicon Image Sil9x87 HDMI multiplexer is implemented. Refer to figure 7-6 HDMI input configuration for the application.

Below find a block diagram of the front-end application for this region.

18770_235_100127.eps 100219

Figure 7-4 Front-End block diagram European/China region

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EN 44

7.

Q552.2E LA

Circuit Descriptions
and vivid colour management. High flat panel screen resolutions and refresh rates are supported with formats including 1366 768 @ 100Hz/120Hz and 1920 1080 @ 100Hz/120Hz. The combination of Ethernet, CI+ and H.264 supports new TV experiences with IPTV and VOD. On top of that, optional support is available for 2D dimming in combination with LED backlights for optimum contrast and power savings up to 50%. For a functional diagram of the PNX855xx, refer to Figure 7-7.

18770_243_100203.eps 100203

Figure 7-6 HDMI input configuration The following multiplexers can be used: Sil9187A (does not support Instaport technology for fast switching between input signals) Sil9287B (supports Instaport technology for fast switching between input signals). The hardware default I2C addresses are: Sil9187A: 0xB0/0xB2 (random: software workaround) Sil9287B: 0xB2 (fixed). The Sil9x87 has the following specifications: +5V detection mechanism Stable clock detection mechanism Integrated EDID RT control HPD control Sync detection TMDS output control CEC control EDID stored in Sil9x87, therefore there are no EDID pins on the SSB.

7.7

Video and Audio Processing - PNX855xx


The PNX855xx is the main audio and video processor (or System-on-Chip) for this platform. It has the following features: Multi-standard digital video decoder (MPEG-2, H.264, MPEG-4) Integrated DVB-T/DVB-C channel decoder Integrated CI+ Integrated motion accurate picture processing (MAPP2) High definition ME/MC 2D LED backlight dimming option Embedded HDMI HDCP keys Extended colour gamut and colour booster Integrated USB2.0 host controller Improved MPEG artefact reduction compared with PNX8543 Security for customers own code/settings (secure flash).

The TV550 combines front-end video processing functions, such as DVB-T channel decoding, MPEG-2/H.264 decode, analog video decode and HDMI reception, with advanced back-end video picture improvements. It also includes next generation Motion Accurate Picture Processing (MAPP2). The MAPP2 technology provides state-of-the-art motion artifact reduction with movie judder cancellation, motion sharpness
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Circuit Descriptions

Q552.2E LA

7.

EN 45

PNX85500x

MEMORY CONTROLLER

TS input TS out/in for PCMCIA CI/CA

MPEG SYSTEM PROCESSOR

PRIMARY VIDEO OUTPUT

LVDS

LVDS for flat panel display (single, dual or quad channel)

DVB

DVB-T/C channel decoder AV-PIP SUB-PICTURE

CVBS, Y/C, RGB

VIDEO DECODER

3D COMB SECONDARY VIDEO OUTPUT VIDEO ENCODER analog CVBS

Low-IF

DIGITAL IF

MPEG/H.264 VIDEO DECODER

Motion-accurate pixel processing SCALER, DE-INTERLACE AND NOISE REDUCTION AUDIO DACS analog audio

SSIF, LR

AUDIO DEMOD AND DECODE

SPDIF

AUDIO IN AUDIO DSP AUDIO OUT I 2S SPDIF

HDMI

HDMI RECEIVER

450 MHz AV-DSP 560 MHz MIPS32 24KEf CPU DRAWING ENGINE

SYSTEM CONTROLLER (8051)

DMA BLOCK

I2C

PWM GPIO

IR

ADC

SPI

UART

I 2C

GPIO Flash USB 2.0 SD Ethernet Memory MAC x8 Card

18770_241_100201.eps 100219

Figure 7-7 PNX855xx functional diagram

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EN 46

8.

Q552.2E LA

IC Data Sheets

8. IC Data Sheets
This chapter shows the internal block diagrams and pin configurations of ICs that are drawn as black boxes in the electrical diagrams (with the exception of memory and logic ICs).

8.1

Diagram USB Hub B01C, USB2513B (IC 7F25)

Block diagram
To Upstream VBUS Upstream USB Data 3.3 V 24 MHz Crystal To EEPROM or SMBus Master SDA SCL

BusPower Detect/ Vbus Pulse

Upstream PHY

Regulator

PLL

Serial Interface

Repeater

Serial Interface Engine

Controller

3.3 V Regulator
CRFILT

TT #1

...

TT #x

Port Controller

Routing & Port Re-Ordering Logic

Port #1 PHY#1
OC Sense Switch Driver/ LED Drivers

...

Port #x PHY#x
OC Sense Switch Driver/ LED Drivers

OC USB Data Port Downstream Sense Power Switch/ LED Drivers

USB Data OC Port Downstream Sense Power Switch/ LED Drivers

The x indicates the number of available downstream ports: 2, 3, 4, or 7.


Note : The LED port indicators only apply to USB2513i.
SDA / SMBDATA / NON_REM[1]

SCL / SMBCLK / CFG_SEL[0]

Pinning information
HS_IND / CFG_SEL[1] VBUS_DET RESET_N

VDD33

NC

NC

23

22

27

26

25

24

21

SUSP_IND / LOCAL_PWR / NON_REM[0] VDD33 USBDM_UP USBDP_UP XTALOUT XTALIN / CLKIN PLLFILT RBIAS VDD33

28 29 30 31 32 33 34 35 36

20

19
18 17

NC

NC OCS_N[2] PRTPWR[2] / BC_EN[2]* VDD33 CRFILT OCS_N[1] PRTPWR[1] / BC_EN[1]* TEST VDD33

SMSC USB2512/12A/12B USB2512i/12Ai/12Bi (Top View QFN-36)


Ground Pad (must be connected to VSS)

16 15 14 13 12 11 10

8
NC

USBDM_DN[1]

USBDM_DN[2]

USBDP_DN[1]

USBDP_DN[2]

VDD33

NC

Indicates pins on the bottom of the device.

NC

NC

18770_301_100217.eps 100217

Figure 8-1 Internal block diagram and pin configuration


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IC Data Sheets 8.2 Diagram Temp sensor & headphone B01J, LM75BDP (IC 7FD1)

Q552.2E LA

8.

EN 47

Block diagram
VCC

LM75B
BIAS REFERENCE POINTER REGISTER COUNTER 11-BIT SIGMA-DELTA A-to-D CONVERTER CONFIGURATION REGISTER TEMPERATURE REGISTER TOS REGISTER THYST REGISTER OS

BAND GAP TEMP SENSOR

TIMER COMPARATOR/ INTERRUPT

OSCILLATOR

POWER-ON RESET

LOGIC CONTROL AND INTERFACE

A2

A1

A0

SCL SDA

GND

Pinning information

SDA SCL OS GND

1 2 3 4

8 7

VCC A0 A1 A2
18770_300_100217.eps 100217

LM75BDP

6 5

Figure 8-2 Pin configuration

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EN 48 8.3

8.

Q552.2E LA

IC Data Sheets

Diagram NANDflash - conditional access B02A, PNX855xx (IC7S00)

Block diagram
PNX8550x
MEMORY CONTROLLER

TS input TS out/in for PCMCIA CI/CA

MPEG SYSTEM PROCESSOR

PRIMARY VIDEO OUTPUT

LVDS

LVDS for flat panel display (single, dual or quad channel)

DVB

DVB-T/C channel decoder AV-PIP SUB-PICTURE

CVBS, Y/C, RGB

VIDEO DECODER

3D COMB SECONDARY VIDEO OUTPUT VIDEO ENCODER analog CVBS analog Y/C

Low-IF Direct-IF

DIGITAL IF

MULTISTANDARD VIDEO DECODER

Motion-accurate pixel processing SCALER, DE-INTERLACE AND NOISE REDUCTION AUDIO DACS analog audio

SSIF, LR

AUDIO DEMOD AND DECODE

SPDIF

AUDIO IN AUDIO DSP AUDIO OUT I2S SPDIF

HDMI

HDMI RECEIVER

450 MHz AV-DSP 500 MHz MIPS32 24KEf CPU DRAWING ENGINE Scatter/Gather TS Demux

SYSTEM CONTROLLER (8051)

I2C

PWM Px_x

IR

ADC

SPI

UART

I2C

GPIO Flash USB 2.0 SD Ethernet Memory MAC x 10 Card

Pinning information
ball A1 index area A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF Transparent top view
18770_308_100217.eps 100217

PNX8550xE
2 4 6 8 10 12 14 16 18 20 22 24 26 1 3 5 7 9 11 13 15 17 19 21 23 25

Figure 8-3 Internal block diagram and pin configuration

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IC Data Sheets 8.4 Diagram Audio B03A, TPA312xD2PWP (IC7D10)

Q552.2E LA

8.

EN 49

Block diagram
TPA3120D2
1 F LIN RIN 1 F BSR ROUT PGNDR 1 F BYPASS AGND PGNDL LOUT BSL 0.22 F 22 H 470 F 0.68 F 0.68 F 0.22 F 22 H 470 F

PVCCL AVCC PVCCR

VCLAMP Shutdown Control SD 1 F

MUTE GAIN0 GAIN1

}
PGNDL PGNDL LOUT BSL AVCC AVCC GAIN0 GAIN1 BSR ROUT PGNDR PGNDR

Control

Pinning information

PWP (TSSOP) PACKAGE (TOP VIEW)


1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13

PVCCL SD PVCCL MUTE LIN RIN BYPASS AGND AGND PVCCR VCLAMP PVCCR

I_18020_142.eps 100402

Figure 8-4 Internal block diagram and pin configuration

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EN 50 8.5

8.

Q552.2E LA

IC Data Sheets

Diagram DC/DC B03B, TPS53126PW (IC7U03)

Block diagram

Pinning information
VBST1 NC EN1 VO1 VFB1 NC GND TEST1 NC VFB2 VO2 EN2 NC VBST2 1 2 3 4 5 TPS53124 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 DRVH1 LL1 DRVL1 PGND1 TRIP1 VIN VREG5 V5FILT TEST2 TRIP2 PGND2 DRVL2 LL2 DRVH2

18310_300_090319.eps 100416

Figure 8-5 Internal block diagram and pin configuration

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IC Data Sheets 8.6 Diagram DC/DC B03E, ST1S10PH (IC 7UD0)

Q552.2E LA

8.

EN 51

Block diagram

Pinning information

DFN8 (4 4)

PowerSO-8
I_18010_083.eps 100402

Figure 8-6 Internal block diagram and pin configuration

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EN 52 8.7

8.

Q552.2E LA

IC Data Sheets

Diagram DC/DC B03E, LD1117DT25 (IC 7UD2)

Block diagram

LD1117DT

Pinning information

DPAK

F_15710_166.eps 100402

Figure 8-7 Internal block diagram and pin configuration

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IC Data Sheets 8.8 Diagram Ethernet & Service B04C, LAN8710A-EZKH (IC 7E10)

Q552.2E LA

8.

EN 53

Block diagram
MODE0 MODE1 MODE2 nRST RMIISEL MODE Control Reset Control

AutoNegotiation

10M Tx Logic

10M Transmitter

HP Auto-MDIX
TXP / TXN RXP / RXN

Transmit Section Management Control 100M Tx Logic 100M Transmitter MDIX Control

SMI

TXD[0:3] TXEN TXER TXCLK RMII / MII Logic RXD[0:3] RXDV RXER RXCLK CRS COL/CRS_DV MDC MDIO

100M Rx Logic

DSP System: Clock Data Recovery Equalizer

Analog-toDigital

PLL Interrupt Generator

XTAL1/CLKIN XTAL2 nINT

Receive Section 10M Rx Logic 10M PLL

100M PLL LED Circuitry Squelch & Filters Central Bias PHY Address Latches
LED1 LED2

RBIAS

PHYAD[0:2]

Pinning information
RBIAS VDD1A RXDV 26 RXN RXP TXN TXP TXD3 25 24 23

32

30

29

31

VDD2A LED2/nINTSEL LED1/REGOFF XTAL2 XTAL1/CLKIN VDDCR RXCLK/PHYAD1 RXD3/PHYAD2

1 2 3 4 5 6 7 8 13 10 12 11 9 14 15 16

28

27

TXD2 TXD1 TXD0 TXEN TXCLK nRST nINT/TXER/TXD4 MDC

SMSC LAN8710/LAN8710i 32 PIN QFN (Top View)


VSS

22 21 20 19 18 17

RXD1/MODE1

RXD0/MDE0

RXD2/RMIISEL

CRS

COL/CRS_DV/MODE2

VDDIO

RXER/RXD4/PHYAD0

MDIO

18770_302_100217.eps 100217

Figure 8-8 Internal block diagram and pin configuration

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2011-Feb-18

EN 54 8.9

8.

Q552.2E LA

IC Data Sheets

Diagram HDMI B04D, SII9x87B (IC 7EC1)

Block diagram

Pinning information

18770_303_100217.eps 100217

Figure 8-9 Internal block diagram and pin configuration

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IC Data Sheets 8.10 Diagram Headphone B04E, TPA6111A2DGN (IC 7EE1)

Q552.2E LA

8.

EN 55

Block diagram
VDD 8

VDD/2 2 IN 1 + VO1 1

BYPASS

IN 2 + SHUTDOWN

VO2 7

Bias Control

Pinning information
D OR DGN PACKAGE (TOP VIEW)

VO1 IN1 BYPASS GND

1 2 3 4

8 7 6 5

VDD VO2 IN2 SHUTDOWN


18770_309_100217.eps 100217

Figure 8-10 Internal block diagram and pin configuration

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EN 56

8.

Q552.2E LA

IC Data Sheets

8.11 Diagram DVBS-FE B07A, STV6110AT (IC 7R02)

Block diagram
RF_OUT IP IN QP AGC QN PLL, dividers XTAL_IN XTAL_INN XTAL_OUT DC offset compensation SCL Amplifier I C bus interface SDA
18770_304_100217.eps 100217

RF_IN

Figure 8-11 Internal block diagram and pin configuration

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IC Data Sheets 8.12 Diagram DVBS supply B08A, TPS54283PWP (IC 7T03)

Q552.2E LA

8.

EN 57

Block diagram
2 CLK1 BP Level Shift f(IDRAIN1) + DC(ofst) GND 4 + FB1 7 0.8 VREF f(IDRAIN1) Overcurrent Comp Current Comparator + S R R Q Q 1 PVDD1 BOOT1

+
RCOMP f(ISLOPE1) f(IMAX1) CLK1 BP Weak Pull-Down MOSFET

SW1

Soft Start 1

SD1

CCOMP

Anti-Cross Conduction f(ISLOPE1) Ramp Gen 1

VDD2

TSD 6 A EN1 EN2 5 6 150 k SEQ 10 150 k CLK2 Level Shift f(IDRAIN2) + DC(ofst) GND 4 Current Comparator + BP FB1 FB2 Output Undervoltage Detect Internal Control 6 A SD1 SD2 UVLO

1.2 MHz Oscilator

Divide by 2/4 Ramp Gen 2

CLK1 f(ISLOPE2)

CLK2

13 BOOT2 BP 14 PVDD2 FET Switch

S R R

Q Q

+ FB2 8 0.8 VREF f(IDRAIN2)

+
RCOMP f(ISLOPE2)

Overcurrent Comp f(IMAX2) CLK2 BP Weak Pull-Down MOSFET

12 SW2

Soft Start 2

SD2

CCOMP

Anti-Cross Conduction

BP 11 150 k BP ILIM2 9 150 k Level Select

5.25-V Regulator

PVDD2

0.8 VREF References IMAX2 (Set to one of two limits)


UDG-07007

18770_305_100217.eps 100217

Figure 8-12 Internal block diagram and pin configuration

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EN 58

8.

Q552.2E LA

IC Data Sheets

8.13 Diagram DVBS supply B08B, LNBH23Q (IC 7T50)

Block diagram
ISEL TTX ADDR SDA SCL Vcc Byp Vcc- L LX
PWM Controller Preregulator +U.V.lockout +P.ON reset EN VSEL VSEL TTX EN

Rsense

P-GND

Vup

ITEST VOUT Control TEN

I2C interface

VoRX

Linear Post-reg +Modulator +Protections +Diagnostics


22KHz Oscill.

I2C Diagnostics

VoTX
TTX 22KHz Tone Amp. Diagn. 22KHz Tone Freq. Detector

EXTM

DETIN

DSQOUT

DSQIN V CTRL

LNBH23
A-GND

Pinning information
1 n.c . 2 n.c . 3 n.c . 4 LX 5 P -G N D 6 S DA 7 n.c . 8 n.c . 9 S CL 10 A D DR 11 DS Q out 12 DS Q IN 13 E XTM 14 TTX 15 B Y P 16 n.c . 17 n.c . 18 V c c -L 19 V c c 20 A -G N D 21 V oRX 22 V oTX 23 n.c . 24 n.c . 25 n.c . 26 n.c . 27 V up 28 IS E L 29 D E TIN 30 V C TRL 31 n.c . 32 n.c .

Epad

Connected with power grounds and to the ground layer through vias to dissipate the heat.

18770_306_100217.eps 100217

Figure 8-13 Internal block diagram and pin configuration

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Block Diagrams

Q552.2E LA

9.

EN 59

9. Block Diagrams
9-1 Wiring diagram Blockbuster 32"
WIRING DIAGRAM 32" BLOCKBUSTER

1M95

TO DISPLAY SUPPLY

1M95 14P

LOUDSPEAKER
(5213)

1G50

41P

SSB
3139 123 6495.x (1150)

1316 10P

1M95
1735 1D38

14P

3P

8G50

1G51

2P 130 8

51P

41P

SPDIF

PHONE

TO DISPLAY

TO DISPLAY

ETHER NET

LCD DISPLAY (1004)

1M19

8P

TUNER

(1005)

HDMI

HDMI

HDMI

VGA

LOUDSPEAKER

HDMI

MAIN POWER SUPPLY 32" DPS-93BP

8G51

51P

SCART

USB

SD-CARD READER

4P

LOUDSPEAKER
1M95 (B03C) 1. +3V3-STANDBY 2. STANDBY 3. GND 4. GND 5. +12VIN 6. +12VIN 7. +24V-AUDIO-POWER 8. GND 9. LAMP-ON 10. BACKLIGHT-PWM_BL-VS 11. BACKLIGHT-BOOST 12. POWER-OK 13. +24V GND 1D38 (B03A) 1735 (B03A)
1. 2. 3. 4. LEFT-SPEAKER GND-AUDIO RIGHT-SPEAKER GND-AUDIO RIGHT-SPEAKER

(5216)

8308

INLET

MAINS SWITCH (8308)

C2

C1

IR / LED BOARD

J1 8P

(1108)
1316 (PSU)
1. ANODE 1 2. NC 3. CATHODE 1 4. GND 5. ANODE 2 6. NC 7. CATHODE 2 8. NC 9. ANODE 3 10. NC 11. CATHODE 3 12. NC 13. ANODE 4 14. NC 15. CATHODE 4

1M95 (PSU)
1. +3V3STDBY 2. STANDBY 3. GND 4. GND 5. +12V 6. +12V 7. +VSND 8. GND_SND 9. BL-ON-OFF 10. BL-DIM1 11. BL-I-CTRL 12. POK 13. +24V 14. GND1

1308 (PSU)
1. N 2. L

1M19 (B09A)
1. 2. 3. 4. 5. 6. 7. 8. LIGHT-SENSOR GND RC LED-2 +3V3-STANDBY LED-1 KEYBOARD +5V

1735 (B03A)
1. 2. 3. 4. LEFT-SPEAKER GND-AUDIO GND-AUDIO RIGHT-SPEAKER

1G51 (B06B) 1. +VDISP 2. +VDISP 3. +VDISP 4. +VDISP | | 51. CTRL-DISP

19100_808_110211.eps 110211

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(5216)

Block Diagrams

Q552.2E LA

9.

EN 60

9-2 Wiring diagram Blockbuster 37"


WIRING DIAGRAM 37" BLOCKBUSTER

TO DISPLAY SUPPLY

1M95

LOUDSPEAKER
(5213)

1M95 14P

1G50

41P

SSB
3139 123 6495.x (1150)

1316 10P

1M95 3P

8G50

1735 1D38

14P

8G51

1G51

51P
2P 13 0 8

41P

SPDIF

PHONE

TO DISPLAY

TO DISPLAY

ETHER NET

LCD DISPLAY (1004)

1M19

8P

TUNER

(1005)

HDMI

HDMI

HDMI

VGA

HDMI

MAIN POWER SUPPLY 37" FSP110-4FS01

51P

SCART

USB

SD-CARD READER

4P

LOUDSPEAKER

LOUDSPEAKER
1M95 (B03C) 1. +3V3-STANDBY 2. STANDBY 3. GND 4. GND 5. +12VIN 6. +12VIN 7. +24V-AUDIO-POWER 8. GND 9. LAMP-ON 10. BACKLIGHT-PWM_BL-VS 11. BACKLIGHT-BOOST 12. POWER-OK 13. +24V GND 1D38 (B03A)
1. LEFT-SPEAKER 2. GND-AUDIO 3. RIGHT-SPEAKER

(5216)

8308

C2

C1

INLET

MAINS SWITCH

IR / LED BOARD

J1 8P

(1108)

1316 (PSU)
1. ANODE 1 2. NC 3. CATHODE 1 4. GND 5. ANODE 2 6. NC 7. CATHODE 2 8. NC 9. ANODE 3 10. NC 11. CATHODE 3 12. NC 13. ANODE 4 14. NC 15. CATHODE 4

1M95 (PSU) 1. +3V3STDBY 2. STANDBY 3. GND 4. GND 5. +12V 6. +12V 7. +VSND 8. GND_SND 9. BL-ON-OFF 10. BL-DIM1 11. BL-I-CTRL 12. POK 13. +24V 14. GND1

1308 (PSU)
1. N 2. L

(8308)

1M19 (B09A)
1. 2. 3. 4. 5. 6. 7. 8. LIGHT-SENSOR GND RC LED-2 +3V3-STANDBY LED-1 KEYBOARD +5V

1G51 (B06B)
1. +VDISP 2. +VDISP 3. +VDISP 4. +VDISP | | 51. CTRL-DISP

1735 (B03A)
1. 2. 3. 4. LEFT-SPEAKER GND-AUDIO GND-AUDIO RIGHT-SPEAKER

19100_809_110211.eps 110211

2011-Feb-18 back to

div. table

(5216)

Block Diagrams

Q552.2E LA

9.

EN 61

9-3 Wiring diagram Blockbuster 40"


WIRING DIAGRAM 40" BLOCKBUSTER

TO DISPLY SUPPLT

1316 10P

1M99

14P

1M95
1M95

MAIN POWER SUPPLY 40" PLDE-P007A


(1005)

14P

1G50

41P

SSB
3139 123 6495.x (1150)

1735 1D38

3P

1G51

8G51

51P

SCART TUNER

LOUDSPEAKER
(5213)

8G50
1M19 8P ETHER NET SPDIF PHONE

HDMI

HDMI

HDMI

VGA

TO DISPLAY 51P

LCD DISPLAY (1004)

TO DISPLAY 41P

8308

INLET LOUDSPEAKER
(5216)
MAINS SWITCH (8308)

LOUDSPEAKER
(5216)
C2 C1

IR / LED BOARD

J1 8P

1316 (PSU)
1. ANODE 1 2. NC 3. CATHODE 1 4. GND 5. ANODE 2 6. NC 7. CATHODE 2 8. NC 9. ANODE 3 10. NC 11. CATHODE 3 12. NC 13. ANODE 4 14. NC 15. CATHODE 4

1M95 (PSU)
1. +3V3STDBY 2. STANDBY 3. GND 4. GND 5. +12V 6. +12V 7. +VSND 8. GND_SND 9. BL-ON-OFF 10. BL-DIM1 11. BL-I-CTRL 12. POK 13. +24V 14. GND1

1308 (PSU)
1. N 2. L

(1112)

1M95 (B03C) 1. +3V3-STANDBY 2. STANDBY 3. GND 4. GND 5. +12VIN 6. +12VIN 7. +24V-AUDIO-POWER 8. GND 9. LAMP-ON 10. BACKLIGHT-PWM_BL-VS 11. BACKLIGHT-BOOST 12. POWER-OK 13. +24V GND

1735 (B03A)
1. 2. 3. 4. LEFT-SPEAKER GND-AUDIO GND-AUDIO RIGHT-SPEAKER

1M19 (B09A)
1. 2. 3. 4. 5. 6. 7. 8. LIGHT-SENSOR GND RC LED-2 +3V3-STANDBY LED-1 KEYBOARD +5V

1D38 (B03A) 1. LEFT-SPEAKER 2. GND-AUDIO 3. RIGHT-SPEAKER

1G51 (B06B) 1. +VDISP 2. +VDISP 3. +VDISP 4. +VDISP | | 51. CTRL-DISP

HDMI

USB

SD-CARD READER

1308

2P

4P

19100_807_110211.eps 110211

2011-Feb-18 back to

div. table

Block Diagrams

Q552.2E LA

9.

EN 62

9-4 Block Diagram Video


VIDEO
B01A
COMMON INTERFACE
1P00 17 18 51 52
68P

B02
+5VCA 7F01 74LVC245APW 20

PNX85500

B06B

VIDEO OUT - LVDS

7S00 PNX85537EB +3V3 B02A VIDEO STREAM B02F LVDS

PCMCIA

1G50 1 2

CONDITIONAL ACCESS

MDO(0-7)

BUFFER CA-MDI(0-7)

CA-MDO(0-7)

MD0 LOUT1 MDI PX1

TO DISPLAY
LOUT2 PX2

B07A

DVBS-FE
1R01 4 SAT IN 30
1R10 16M

7R02 STV6110A

7R01 STV0903BAC 21 20 32 18 19 IP IM XTAL QP QM AGC 7

DVB-S TUNER

122 12 11 16

DVB-S CHANNEL 8 DECODER

78 75 74 73

TS-DVBS-VALID TS-DVBS-SOP TS-DVBS-CLOCK TS-DVBS-DATA

9R03-1 9R03-2 9R04 9R03-4

3 41

TS-FE-VALID TS-FE-SOP TS-FE-CLOCK TS-FE-DATA

R23 TNR_SER1_MIVAL R22 TNR_SER1_SOP T22 TNR_SER1_MICLK T21 TNR_SER1_DATA

N.C.

31

B10A

DVBT2
7FJ1 53

7FJ0 CXD2820R 4 TS-FE-VALID TS-FE-SOP 3 5 TS-FE-CLOCK 7 TS-FE-DATA B02I ANALOG VIDEO LOUT3 PX3

N.C. I2C

1G51 51 50 49 40

B01F

TUNER
1T01 TH2627

DVBT2-IFN DVBT2-IFP IF-AGC +5V-TUN-PIN 3 10 11 RF-AGC TUN-IF-P TUN-IF-N 4 5F73 3 1


5F70

49 50 64

DVBT2 CHANNEL DECODER

MAIN HYBRID TUNER


RF IN RF_AGC IF-OUT1 IF-OUT2

7F75 UPC3221GV VCC

TO DISPLAY
SSB 3104 313 6519.x LOUT4 IF-P-DVBT2 IF-P-DVBT2 PNX-IF-P AE12 AF12 PX4 40 4 3 2 +VDISP 1

1 2F90 1 2 1F75 5 4 2F74 2F78 2 3

AGC AMPLIFIER 7 3F79-1


6 3F79-4

BANDPASS FILTER

PNX-IF-N

SAW 36MHZ17 7F70 B02E CONTROL SELECT-SAW

OUT 4 IN AGC CONTROL

TUNER_N

PNX-IF-AGC

AD12

IF_AGC

B01H

HDMI

B04D

HDMI

B04A

ANALOGUE EXTERNALS A

*7EC1 SII9187BC SII9287BC 1P05 1 3


1 2

PNX85537

TUNER_P

1E01 15 11 7
7

B01C
B02E CONROL

USB HUB

DRX2+ DRX2DRX1+ DRX1DRX0+ DRX0DRXC+ DRXC-

26 25 24 23 RXD 22 21 20 19 EXT 1
16 20

AV1-R AV1-G AVI-B AV1-CVBS 7E05 EF 7E06 EF AV1-STATUS 7E09-1 AV1-BLK B02G CONTROL B02G CONTROL CVBS-MON-OUT1

4 6 7 9 10 12

11

19
15

AF11

CVBS1_OUT

19 18

8
21

USB_DN USB_DP

R25

9F25

HDMI SIDE CONNECTOR

SCART1

16

SIDE USB CONNECTOR

B02A FLASH

B01B

FLASH
7F20 H27U4G8F2DTR

1P04 1
1 2

ARX2+ ARX2ARX1+ ARX1ARX0+ ARX0ARXC+ ARXC-

72 71 70

17 18

3 4 6 7 9 10 12

USB2-DM USB2-DP

2 3 4

B01I

VGA
1E05 1
10 5 15

1FL5

69 RXA 68 67 66 65
1 6 11

XIO_D R-VGA G-VGA B-VGA H-SYNC-VGA V-SYNC-VGA AF16 VGA_R AD16 VGA_G AE16 VGA_B AB18 HSYNC_IN AC18 VSYNC_IN B02B MEMORY VREF_1 VREF_2 A2 V1

XIO-D(00-07)

NAND FLASH

21
24M

+5V

19 18

2 3 13 14

1F24 1 2 3 4 5

SIDE USB CONNECTOR

22 VCC 12,37 DDR2-VREF-CTRL2 DDR2-VREF-CTRL3

13 14

HDMI 3 CONNECTOR

USB-WIFI-DDn USB-WIFI-DDP

1P03 1 3
1 2

VGA CONNECTOR
BRX2+ BRX2BRX1+ BRX1BRX0+ BRX0BRXC+ BRXC8 7 6 5 RXB 4 3 2 1 PB EXT 3 Y 1E03 2

+3V3

B04B

ANALOGUE EXTERNALS B
1E04 PR 1E08 2 2 AV3-PR AV3-Y AV3-PB AC15 AE15 AD15 PR_R_C1

SSB 3139 123 6519.x

4 6 7 9 10 12

B05A
DQ Y_G1 PB_B1
D(0-7)

DDR
DDR2-D(0-31)
D(16-23) D(24-31) D(8-15)
7B00 H5PS1G83E 7B02 H5PS1G83E 7B03 H5PS1G83E 7B01 H5PS1G83E

HDMI 2 CONNECTOR

19 18

1P02 1 3
1 2

SDRAM 128Mx8
CRX2+ CRX2CRX1+ CRX1CRX0+ CRX0CRXC+ CRXC18 17 16 15 14 13 12 11 9,27,64 RXC 62 TXC_P 63 TXC_N 60 TX0_P 61 TX0_N 58 TX1_P 59 TX1_N 56 TX2_P 57 TX2_N HDMIA-RXC+ HDMIA-RXCHDMIA-RX0+ HDMIA-RX0HDMIA-RX1+ HDMIA-RX1HDMIA-RX2+ HDMIA-RX23S0W +3V3 *6000 SERIE MUX SII9187 NON INSTAPORT 7000 SERIE MUX SII9287 INSTAPORT B02C HDMI_DV
VDDL VREF

SDRAM 128Mx8
VDDL VREF

SDRAM 128Mx8
VDDL VREF

SDRAM 128Mx8
VDDL VREF

4 6 7 9 10 12

HDMI 1 CONNECTOR

+3V3-HDMI

VCC33

W25 RXC_A_P W26 RXC_A_N V25 RX2_A_P V26 RX2_A_N U25 RX1_A_P U26 RX1_A_N T25 RX0_A_P T26 RX0_A_N W24 RREF

A1 E2 A

A1 E2

A1 E2

A1 E2 DDR2-A(0-14) +1V8 DDR2-VREF-DDR

19 18

19100_811_110214.eps 110214

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3 2

HDMI SWITCH

7FL5 CY7C65631

USB HUB

10 5

+5V-USB2 1P07 1

R26

USB-DM USB-DP

9F26

USB1-DM USB1-DP

2 3

3 2

20

AC13 AV1_R AE13 AV1_G AD13 AV1_B AB15 CVBS_Y1

+5V-USB1 1P08 1

Block Diagrams

Q552.2E LA

9.

EN 63

9-5 Block Diagram Audio


AUDIO
B01A
COMMON INTERFACE
1P00 17 18 51 52

B02
+5VCA 7F01 74LVC245APW 20

PNX85500

B02D

CLASS-D

B03A

AUDIO

68P

PCMCIA

+3V3

7S00 PNX85537EB B02A VIDEO STREAM B02D AUDIO 7D10 TPA3123D2PWP PVCC_L 5D07 10,12 5D08 1,3 22 +24V-AUDIO-POWER 1735 1 2 SPEAKER L 3 15 RIGHT-SPEAKER 4 SPEAKER R 1D38 1 5D03 DETECT2 7D03 MAINS SWITCH DETECT A-STBY 7D03 STANDBY & PROTECTION 2 3 SPEAKER WOOFER

CONDITIONAL ACCESS

MDO(0-7)

BUFFER CA-MDI(0-7)

CA-MDO(0-7)

MD0 MDI AD7 ADAC(1) 12 7S05 LM324P ADAC_1 14 +AUDIO-L 5

PVCC_R OUT-L

B07A

DVBS-FE
1R01 4 SAT IN 30

7R02 STV6110A

7R01 STV0903BAC 21 20 32 18 19 IP IM XTAL QP QM AGC 7 8 122 12 11 16

LEFT-SPEAKER

IN-L

DVB-S TUNER

DVB-S CHANNEL DECODER

78 75 74 73

TS-DVBS-VALID TS-DVBS-SOP TS-DVBS-CLOCK TS-DVBS-DATA

9R03-1 9R03-2 9R04 9R03-4

TS-FE-VALID TS-FE-SOP TS-FE-CLOCK TS-FE-DATA

1R10

R23 TNR_SER1_MIVAL R22 TNR_SER1_SOP T22 TNR_SER1_MICLK T21 TNR_SER1_DATA

CLASS D POWER AMPLIFIER


ADAC_2 AE7 ADAC(2) 10 8 7D15 A-PLOP B02G STANDBY AC19 B04E A-PLOP A-STBY 2 SD -AUDIO-R 6 IN-R OUT-R

16M

31

B10A

DVBT2

7FJ0 CXD2820R 49

DVBT2-IFN

DVBT2 CHANNEL DECODER

PO_7 TS-FE-VALID 4 TS-FE-SOP 3 5 TS-FE-CLOCK 7 TS-FE-DATA

AUDIO-MUTE-UP

MUTE

B01F

TUNER
1T01 TH2627 IF-OUT1 +5V-TUN-PIN 1 TUN-IF-P TUN-IF-N 4 5F73 3 1 2F90 1 2 1F75 5 4 2F74 2F78 2 3 OUT 4 IN AGC CONTROL

DVBT2-IFP

50

B03C

7F75 UPC3221GV VCC

B02I ANALOG VIDEO SSB 3139 123 6519.x IF-P-DVBT2 IF-P-DVBT2 PNX-IF-P AE12 AF12 PO_6 TUNER_P TUNER_N AB19

B04E

HEADPHONE
7EE0-1 RESET-AUDIO 7EE0-2 A-PLOP B03A B04A

B01J

TEMP SENSOR + HEADPHONE

RF IN

IF-OUT2 10

AGC AMPLIFIER 7 3F79-1


6 3F79-4

7F70 B02E CONTROL SELECT-SAW

PNX85537

MAIN HYBRID TUNER

11

BANDPASS FILTER

5F70

PNX-IF-N

SAW 36MHZ17

7EE1 TPA6111A2DGN HEADPHONE AMPLIFIER 5 SHUTDOWN VO_1 2 IN-1 VO_2 VDD 1 7 8 AMP1 AMP2

PNX-IF-AGC

AD12

IF_AGC

1328
2 3 1 HEADPHONE OUT 3.5mm

B01H

HDMI

B04D

HDMI

B04A

ANALOGUE EXTERNALS A
1E01-1 3 1
7 11 15

B02D
3EA7-1 3EA7-4 AUDIO-OUT-L AUDIO-OUT-R 1 7

PNX85500: AUDIO

*7EC1 SII9187BCNU SII9287BCNU


1

ADAC3

AF7

ADAC(3)

AP-SCART-OUT-L AP-SCART-OUT-R

7S05

3 5

ADAC(5) ADAC(6)

AE6

1P05 1 3
1 2

ADAC_5

ADAC4

AD6

ADAC(4)

IN-2

+3V3

DRX2+ DRX2DRX1+ DRX1DRX0+ DRX0DRXC+ DRXC-

26 25 24 23 RXD 22 21 20 19
16 20

AF6 ADAC_6 AE10 AIN1_L AF10 AIN1_R

4 6 7 9 10 12

6 2

AUDIO-IN1-L AUDIO-IN1-R

B02E CONROL

B01C

USB HUB

19 18

21

SCART1 7E01 A-PLOP A-PLOP B04E

+5V-USB1 1P08 1
USB_DN USB_DP R25 9F25
3 2

HDMI SIDE CONNECTOR

R26

USB-DM USB-DP

9F26

USB1-DM USB1-DP

2 3 4

SIDE USB CONNECTOR

1P04 1
1 2

HDMI SWITCH
ARX2+ ARX2ARX1+ ARX1ARX0+ ARX0ARXC+ ARXC72 71 70 69 68 RXA 67 66 65 9,27,64

B04B

ANALOGUE EXTERNALS B
1E08 6 AUDIO-IN3-L AUDIO-IN3-R AE9 AF9 AIN3_L AIN3_R

B02A FLASH

B01B

FLASH
7F20 H27U4G8F2DTR-BC 17 18

7FL5 CY7C65631

3 4 6 7 9 10 12

19 18

1E09
2 VGA (OR DVI) AUDIO VCC33 3 1 AUDIO-IN4-L AUDIO-IN4-R AD9 AC9 AIN4_L AIN4_R

XIO_D

XIO-D(00-07)

1FL5

24M

HDMI 3 CONNECTOR

NAND FLASH

21

+5V
13 14

1F24 1 2 3 4 5

+3V3-HDMI 1P03 1 3
1 2

22 VCC 12,37 +3V3

USB-WIFI-DDn USB-WIFI-DDP

BRX2+ BRX2BRX1+ BRX1BRX0+ BRX0BRXC+ BRXC-

8 7 6 5 RXB 4 3 2 1 DIGITAL AUDIO OUT

1E10

4 6 7 9 10 12

2 1 3

+3V3

SPDIF-OPT SSB 3139 123 6519.*

+3V3 7S09 2 3 & 1 4 B02G STANDBY 8 SSB 3139 123 6495.* 5 SEL-HDMI-ARC AF18 P0_4 B02B MEMORY SPDIF-OUT-PNX AF5 SSB 3139 123 6519.x

1E07 1 SPDIF-OUT

19 18

SPDIF_OUT DQ

B05A

DDR
DDR2-D(0-31)

D(16-23)

1P02 1 3
1 2

CRX2+ CRX2CRX1+ CRX1CRX0+ CRX0CRXC+ CRXC-

18 17 16 15 RXC 14 13 12 11

4 6 7 9 10 12 14

HDMI 1 CONNECTOR

62 TXC_P 63 TXC_N 60 TX0_P 61 TX0_N 58 TX1_P 59 TX1_N 56 TX2_P 57 TX2_N 5EC2 eHDMI+

HDMIA-RXC+ HDMIA-RXCHDMIA-RX0+ HDMIA-RX0HDMIA-RX1+ HDMIA-RX1HDMIA-RX2+ HDMIA-RX23S0W +3V3

B02C HDMI_DV W25 RXC_A_P W26 RXC_A_N V25 RX2_A_P V26 RX2_A_N U25 RX1_A_P U26 RX1_A_N T25 RX0_A_P T26 RX0_A_N W24 RREF

SDRAM 128Mx8
VDDL VREF

SDRAM 128Mx8
VDDL VREF

SDRAM 128Mx8
VDDL VREF

D(24-31)

D(8-15)

D(0-7)

HDMI 2 CONNECTOR

7B00 H5PS1G83EFR

7B02 H5PS1G83EFR

7B03 H5PS1G83EFR

7B01 H5PS1G83EFR

SDRAM 128Mx8
VDDL VREF

A1 E2 A

A1 E2

A1 E2

A1 E2 DDR2-A(0-14) +1V8

19 18

ARC-eHDMI+

VREF_1 VREF_2

A2 V1

DDR2-VREF-DDR DDR2-VREF-CTRL2 DDR2-VREF-CTRL3

*6000 SERIE MUX SII9187 NON INSTAPORT 7000 SERIE MUX SII9287 INSTAPORT 19100_812_110215.eps 110215

2011-Feb-18 back to

div. table

3 2

AUDIO IN L+R

USB HUB

9 10 5 USB2-DM USB2-DP

+5V-USB2 1P07 1
2 3
1

SIDE USB CONNECTOR

Block Diagrams

Q552.2E LA

9.

EN 64

9-6 Block Diagram Control & Clock Signals


CONTROL + CLOCK SIGNALS
B01D
SD-CARD

B02A
1P09 1 2
Pin1

PNX85500
B02B MEMORY

B05A
DQ

DDR

7S00 PNX85537EB B02E ETHERNET


SDIO-DAT3 SDIO-CMD SDIO-CLK SDIO-DAT0 SDIO-DAT1 SDIO-DAT2 SDIO-CDn SDIO-WP W2 CC_DAT3 W6 CMD W1 CLK W5 DAT_0 W4 DAT_1 W3 DAT_2 U6 SDCD V6 SDWP

DDR2-D(0-31) D(16-23) D(24-31) D(8-15) D(0-7)


7B00 H5PS1G83EFR 7B02 H5PS1G83EFR 7B03 H5PS1G83EFR 7B01 H5PS1G83EFR

Pin9

5 7 8 9 10 12

Pin4

Pin3

Pin2

SDRAM 128Mx8

SDRAM 128Mx8

SDRAM 128Mx8

SDRAM 128Mx8

SD-CARD CONNECTOR

Pin8 Pin7

Pin6 Pin5

F8 E8

F8 E8 DDR-CLK_N DDR-CLK_P

F8 E8 DDR2-A(0-13)

F8 E8

B04C

ETHERNET + SERVICE
1N00 7E10 LAN8710A-EZK

A CLK_N CLK_P ETH-RXD ETH-TXD 7 20 ETHERNET CONNECTOR RJ45 5 1E70 25M ETH-RXCLK ETH-TXCLK AA3 AA2 RXD TXD RXCLK TXCLK B02H POWER AF1 VDD_1V1 AA15 VDDA_1V2 N5 N4

ETHERNET

B06C

AMBILIGHT CPLD
B03B B03D 5 41 40 39

7GA0 XC9572XL

B09A

NON DVBS CONNECTOR BOARD

SENSE+1V1 SENSE+1V2

AMBI-SPI-CLK-OUT

1M59 1
2 3 5 7 8 10 11 13 14 15

PNX-SPI-CSBn B02E CONTROL PNX-SPI-CLK PNX-SPI-SDI PNX-SPI-SDO

CPLD

27 23 29 30 31 19 20 28

AMBI-SPI-SDO-OUT AMBI-SPI-SDI-OUT_G1 AMBI-PWM-CLK_B2 AMBI-SPI-CS-OUTn_R2 AMBI-LATCH1_G2 AMBI-PROG_B1 AMBI-BLANK_R1 AMBI-LATCH2_DIS AMBI-SPI-CS-EXTLAMPSn AMBI-TEMP

4 19 RESET-ETHERNETn

B02G B02A VIDEO STREAM

TO AMBILIGHT MODULE

B07A

DVBS-FE
7R02 STV6110A 32 XTAL QP QM IP IM 122 12 18 19 21 20 B08A 7R01 STV0903BAC 73 TS-DVBS-DATA 9R03-4 9R04 9R03-2 9R03-1 B02G TS-FE-DATA TS-FE-CLOCK TS-FE-SOP TS-TS-VALID T21 T22 74 TS-DVBS-CLOCK MULTI 11 TS-DVBS-SOP 75 STANDARD 7 DEMODULATOR 78 TS-DVBS-VALID 8 FOR SAT DIG TV 62 RESET-DVBS 52 GPIO_1 TNR_SER1_DATA CLK_54_OUT GPI0_7 Y22 AC5 V22 B02G 3D-LR 7 43 3 VCCIO 26 AD5 BACKLIGHT-PWM 9GA0

SATELLITE TUNER

TNR_SER1_MICLK R22 TNR_SER1_SOP R23 TNR_SER1_MIVAL

PXCLK54 PNX-SPI-CS-BLn

21 32

VIO BACKLIGHT-PWM_BL-VS B03C

B10A
B01F B01F B02E

PNX85537

SENSE+1V0-DVBS

DVBT2
DVBT2-IFN DVBT2-IFP 49 50

7FJ0 CXD2820R TS-FE-VALID 4 TS-FE-SOP 3 DVBT2 CHANNEL 5 TS-FE-CLOCK

BL_PWM

OPTIONAL

B02E

PNX85500: MIPS

B01C

USB HUB
3 2

+5V-USB2 1P08 1
USB_DN USB_DP R26 R25 USB-DM USB-DP RESET-SYSTEMn SELECT-SAW 9F26 9F25 SSB 3139 123 6495.x 7FL5 CY7C65631 USB-DM2 USB-DP2 2 3 4 B01K B02G B01F

RESET-SYSTEMn

B01B

FLASH

B01A

COMMON INTERFACE
1P00 1 20 62 63 7F00 MOCLK MOVAL MOSTRT CA-MDI(0-7) 7F01 CA-MOCLK CA-MOVAL CA-MOSTRT K24 L23 L22 VS_2 MOVAL MOSTRT MDI

AE4 RESET_SYS U23 GPI0_11

SIDE USB CONNECTOR

B04C

ETHERNET + SERVICE
17 18

USB HUB

9 10 5 6 USB-DM1 USB-DP1

2 3 4

1E06
GPI0_2 GPI0_3

Y23 Y24

RXD1-MIPS TXD1-MIPS

2 3 1 UART SERVICE CONNECTOR 1FL5

21 24M

SIDE USB CONNECTOR

+5V
13 14

COMMON INTERFACE

MDO(0-7) 7F02 7F03

CA-MDO(0-7)

MDO B02A FLASH

1F24 1 2 3 4 5

22

7F20 H27U4G8F2DTR

PCMCIA

USB-DM3 USB-DP3

NAND FLASH
VCC

CA-A(00-14) 7F04 7F05

XIO-A(0-15)

XIO_A

12,37

+3V3

CONDITIONAL ACCESS

SSB 3139 123 6519.x

CA-D(0-7) 68 XIO-D(00-07)

XIO-D(00-15)

XIO_D

B02G
GPIO_10 V23

PNX85500: STANDBY CONTROLLER


BOOST-PWM

B01E

PNX85500-CONTROL
BACKLIGHT-BOOST

B02G STANDBY

9CH0

B03C

B06C

B09A

CONNECTORS COMP
1M19 1 2 3 4 TO IR / LED BOARD AND KEYBOARD CONTROL 5 6 7 8 +5V +3V3-STANDBY LED-1

B03C

DC / DC
LIGHT-SENSOR RC AE26 AD19 AC25 AD26 AD23 P5_1 P1_0 PWM_1 PWM_0 P3_0 KEYBOARD P5_0 P3_1 P1_7 RESET_IN P6_4 DETECT2 RESET-SYSTEMn AV1-BLK AV1-STATUS LCD-PWR-ONn AA22 AB22 AD22 AE25 AC20 XTAL_IN SPI_CLK P6_5 SPI_CSB SPI_SDO SPI_SDI AF24 AE22 AF23 AE23 AF25 PNX-SPI-CLK PNX-SPI-WPn PNX-SPI-CSBn PNX-SPI-SDO PNX-SPI-SDI 6 3 1 5 2

7F52 M25P05-AVMN6P

FLASH
VCC 8 +3V3-STANDBY

LED-2

9U41 7U43

LED2 LED1

512K
1F51 3 FF04 SDM FF29 SPI-PROG 1 LEVEL SHIFTED 2 FOR DEBUG USE 4 ONLY 5

AE21 AF21 AB20 AA26


AF22 AE17 1S02

RXD-UP TXD-UP
SDM RESET-STBYn SPI-PROG +3V3-STANDBY 7S20 NCP303LSN28G 2 3 INP OUTP GND 1 RESET-STBYn

B02G

PNX85500: STANDBY CONTROLLER


B03C B02E B04A B04A B03H P3_2 P3_3 P3_5 XTAL_OUT CADC_2 P1_1 P2_0 P2_7 P0_4 P2_2 7EC0 EF 7EC1 SII9187ACNU SII9187ACNU 31 35 41 45 CEC-HDMI AF19 P1_2 P0_1 P0_3 P2_6 P2_3 P0_6 P0_7

3 2

+5V-USB1 1P07 1

DECODER 7

TS-FE-DATA

RES
ENABLE-3V3-5V ENABLE-1V8 DETECT2

54M

B03C

DC / DC

CONTROL

AF17 AD18 AD21 AF18 AE20 AA18 AE18 AC21 AF20 AB19 AC19

B03E B03B B03D B02G B03A

RESET-USBn ENABLE-3V3n SEL-HDMI-ARC LAMP-ON RESET-DVBS RESET-ETHERNETn POWER-OK STANDBY RESET-AUDIO AUDIO-MUTE-UP

B01C

+12V +3V3-STANDBY

B04D HDMI
TO PIN: 1P02-13 1P03-13 PCEC-HDMI 1P04-13 1P05-13 ARX-HOTPLUG 1P02-19 BRX-HOTPLUG 1P03-19 CRX-HOTPLUG 1P04-19 DRX-HOTPLUG 1P05-19

B02D B07A B04C B06C B01E BACKLIGHT-PWM_BL-VS BACKLIGHT-BOOST

1 2

1M95 9 10 TO 11 POWER SUPPLY 12 2

B02C HDMI_DV HDMIA-RC 3S0W +3V3 RX

B04E B03A

4x HDMI CONNECTOR

HDMI SWITCH

19 18

W24

RREF

19100_813_110216.eps 110216

2011-Feb-18 back to

div. table

Block Diagrams

Q552.2E LA

9.

EN 65

9-7 Block Diagram I2C


IC
B01E
PNX85500: CONTROL

B02E

PNX85500: MIPS 7S00 PNX85537EB 3S6D B02E B25 3_SDA 3_SCL A24 3S5Z +3V3 3S6A 3S5Y +3V3 3S6E

B01E

PNX85500-CONTROL

B01J

TEMP SENSOR + HEADPHONE

B04D

HDMI

B01K

TUNER BRAZIL

B07A

DVBS-FE

B08B

DVBS-SUPPLY

B10A

DVBT2

SDA-SSB SCL-SSB 3FD3 3FD4 3EC3 3EC5 3FE8 3FE9 3R00 3R01 3T61 3FJJ AIN-5V 3EC1-1 3EC1-3 54 29 30 BIN-5V 3ECA-1 3ECA-2 3T51 +3V3RF 97 3R15 3R14 18 19
19 18

PNX85537
CONTROL C25 1_SDA 7F52 M25P05-AVMN6P 1_SCL B02G PNX-SPI-CLK PNX-SPI-WPn PNX-SPI-CSBn PNX-SPI-SDO PNX-SPI-SDI AF24 SPI_CLK AE22 P6_5 AF23 SPI_CSB AE23 SPI_SDO AF25 SPI_SDI C26

ERR 13

53 7EC1 SII9287B SII9187A HDMI MUX


ERR 23

46

45

98

29

3FJH

30

3S69

1P04 ARX-DDC-SDA ARX-DDC-SCL 16 15 7FE0 TC90517FG DEMODULATOR 7R01 STV903BAC CHANEL DEC DVBS
ERR 28
1 2

3S56 3S57

SDA-UP-MIPS SCL-UP-MIPS 3F60

7FD1 LM75BDP TEMP SENSOR 6


ERR 42

SDAT SCLT

7T50 LNBH23QT LNB CONTROLLER


ERR 31

7FJ0 CXD2820R DVBT CHANNEL DECODER

B02G

PNX85500: STANDBY CONTROLER +3V3-STANDBY

3F59

RES 13 12

HDMI CONNECTOR 3
1P03 BRX-DDC-SDA BRX-DDC-SCL 16 15
19 18 1 2

+3V3-STANDBY

FLASH
VCC

6 3 1 5 2

STANDBY 3S6W 3S6V


ERR 15 ERR 53

512K
STANDBY SW

7F58 M24C64 EEPROM (NVM) RES


ERR 35

33 34

7R02 STV6110A SATELITE TUNER


ERR 36

AC23 MC_SDA MC_SCL AC24

3S2F 3S2G

RES
3ECA-3 3F63 3F62 1F52 3 1 DEBUG ONLY 39 40

CIN-5V 3ECA-4

HDMI CONNECTOR 2
1P02 CRX-DDC-SDA CRX-DDC-SCL 16 15
19 18 1 2

RES

B01H

HDMI

+3V3-STANDBY 3S1G 3S1H

B01B

FLASH AE21 7F20 H27U4G8F2DTR P3_0 P3_1 B02A FLASH XIO-D(00-07) MAIN SW Y23 GPIO_2 GPIO_3 B02I Y24 XIO_D DDC_A_SCL HDMI_DV B02C] DDC_A_SDA Y26 AF21

MAIN NVM SW RXD-UP TXD-UP 3F65 3F64

DIN-5V 3FBF-2 3FBF-1

1F51 3

3ECU-2

3ECU-4

uP LEVEL SHIFTED FOR DEBUG 1 USE ONLY

+3V3 43 44 DRX-DDC-SDA DRX-DDC-SCL

HDMI CONNECTOR 1

1P05 16 15
19 18 1 2

FLASH (4Gx16)

RES
Y25 DDCA-SDA DDCA-SCL +3V3

HDMI CONNECTOR SIDE

OPTIONAL

OPTIONAL

B01I B04C
ETHERNET + SERVICE 3E53-4 3E53-2 3E53-3 3E53-1 +5V-EDID 3ECP-1 3ECP-3

VGA +5V-VGA

3S83

3S84

3FC1

3FC2

1E06
3 2 1 UART SERVICE CONNECTOR 47 EDID SW 48

RXD1-MIPS TXD1-MIPS

1E05
5

VGA-SDA-EDID-HDMI VGA-SCL-EDID-HDMI

9FC1 9FC3

12 15

10 1 6

B02I
AD25

PNX85500: ANALOG VIDEO 3S5V-1 3S5V-3 RES

B05A

DDR

VGA_EDID_SDA VGA_EDID_SCL AD24

VGA-SDA-EDID VGA-SCL-EDID

9FC2 9FC4

VGA CONNECTOR

7B00 H5PS1G83EFR

7B01 H5PS1G83EFR

RES

ANALOGUE VIDEO +3V3 3S6G 3S6F

SDRAM 128Mx8
D(0-7)

SDRAM 128Mx8
D(8-15) B02B B24 MEMORY A DQ 4_SDA 4_SCL A23 3S61 3S60

B01F

TUNER

SDA-TUNER SCL-TUNER

3F75 3F76

TUN-P7 TUN-P6

DDR2-A(0-13) DDR2-D(0-31)
7B02 H5PS1G83EFR 7B03 H5PS1G83EFR

ERR 18

7 1T01 TH2627 MAIN TUNER


ERR 34

D(16-23)

SDRAM 128Mx8

SDRAM 128Mx8

D(24-31)

B04C

ETHERNET + SERVICE

+3V3 3S6C 3S6B

B06B

VIDEO OUT - LVDS

7E10 LAN8710A-EZK 11 10 9 ETH-RXD(0) ETH-RXD(1) ETH-RXD(2) ETH-RXD(3) ETH-RXCLK ETH-TXD(0) ETH-TXD(1) ETH-TXD(2) ETH-TXD(3) ETH-TXCLK Y5 Y6 AB4 AC1 AA3 AA1 AA4 AB1 AB2 AA2

1G51 SDA-SET SCL-SET +3V3 3S67 3S65 3S68 3S66 9S12 9S11 SDA-DISP SCL-DISP 3G2W 3G2Y 50 49

B26 2_SDA 2_SCL RXD_0 RXD_1 RXD_2 RXD_3 RXCLK GPIO_2 TXD_0 TXD_1 TXD_2 TXD_3 TXCLK GPIO_3 W22 A25

3S58 3S5W

LVDS CONNECTOR

ERR 14

+3V3 2 3S81 3S80 7S01 PCA9540B 2 CHAN. MULTIPLEX.


ERR 24

ETHERNET

8 7 22 23 24 25 20

1 4 5

ERR 64

B09A

DVBS CONNECTOR BOARD

W21

RXD2-MIPS TXD2-MIPS

ETHERNET CONNECTOR RJ45

7 8

3C83 3C81 RES 9S13 9S10

1M71 3

TO 1 TEMPERATURE SENSOR RES SDA-BL SCL-BL

11

15

SW

Programmable via USB


19100_814_110217.eps 110217

2011-Feb-18 back to

div. table

Block Diagrams

Q552.2E LA

9.

EN 66

9-8 Supply Lines Overview


SUPPLY LINES OVERVIEW
B03C
1M99 1 GND1 2 +12V3 3 GND1 4 +12V3 5 GND1 6 +12V3 1M99 1
2 3 4 5 6 7 8 9 +12V_AL B03h

DC / DC

B01H

HDMI
1P05 18 DIN-5V B03c B03c B04d

B03A

AUDIO
+3V3-STANDBY +24V-AUDIO-POWER +AVCC

+3V3-STANDBY +24V-AUDIO-POWER 3D09

HDMI SIDE CONNECTOR

B04A
+3V3 B03e B03e +5V

ANALOGUE EXTERNALS A
+3V3 +5V B03e

B08A

DVBS-SUPPLY

+3V3 +24V

+3V3 +24V

B01I
GND_AL

VGA
1E05 9 +5V-VGA B04d B03c

B04B B03B
DC / DC
B03e +3V3-STANDBY +12V 5U02 +3V3-STANDBY B03e +12V +3V3 +5V

ANALOGUE EXTERNALS B
+5V +3V3

B03c

N.C. GND1 +12V3

7 8 9

3D-LR

B02E +12VIN B03h

VGA CONNECTOR

PSU
3V3SB STANDBY GND1 GND1 GND1 +12V3
1M95 1
2 3 4 5 6

B01J
B03e +3V3

TEMP SENSOR + HEADPHONE


+3V3

B03c

7T03 1 TPS54283PWP 3 5T03 Dual N-Synchr Converter

+5V-DVBS

7T00
5T00
IN OUT COM

5T01 +1V-DVBS B07a +3V3-DVBS B07a,B08b

7T02
12V/1V8 COVERSION B03e 5U00 +1V8 B02b,h,B03d, B05a

1M95 1
2 3 4 5 6 1U40

+3V3-STANDBY

5T02

STANDBY

B02G

B01e,B02e, g,h,B03a,b,h, B04d,e,B09a

7U03 TPS53126PW

7U02-1

B04C
+3V3

ETHERNET + SERVICE
+3V3 5E08 +3V3-ET-ANA

IN OUT COM

B01K
+12VIN B03h +12VD +12V +24V-AUDIO-POWER B01g

TUNER BRAZIL
+1V2-BRA-VDDC +1V2-BRA-DR1 +3V3 5FE7 5FE4 +3V3-BRA +3V3-BRA-FLT +5V

+1V2-BRA-VDDC +1V2-BRA-DR1 B01g

Dual Synchronous 7U02-2 Step-Down Controller 14

12

7T01
IN OUT COM

+2V5-DVBS B07a +V-LNB B08b

B04D
+3V3 B03e 12V/1V1 COVERSION

HDMI
+3V3 5EC0 +3V3-HDMI +3V3-STANDBY +5V-VGA +5V-EDID

12 5T04

7U01

6EC1

9 BL-ON-OFF 10 BL-DIM1 11 BL-I-CTRL 12 POK +24V 13 14

+VSND GND1

7 8

7 8 9 10 11 12 13 14

T 3.0A

B03b,d,e,g, B08b,B09a B02d,B03a

B03e

+3V3

1
7U04

+3V3-STANDBY B03c +5V-VGA

B08B
B08a B03c B08a +12V +V-LNB

DVBS-SUPPLY
+3V3-DVBS +12V +V-LNB

LAMP-ON B02G BACKLIGHT-PWM_BL-VS B06C BACKLIGHT-BOOST B01E POWER-OK B02G


+24V B08a,B09a

23 24
5U01 +1V1 B01I B02h,g,B03e

+3V3-DVBS

B03e

+5V

7FE3
5FE9
IN OUT COM

+2V5-BRA B03e

+5V

+5V 1P04 18 1P03 18 1P02 18

GND1

B03D
+1V8

DC / DC
+1V8 7UA3 +1V2 B02g,h, B03e,B10a

HDMI 3 CONNECTOR HDMI 2 CONNECTOR HDMI 1 CONNECTOR

AIN-5V B03e BIN-5V B03c B03e CIN-5V DIN-5V

B09A
+3V3

CONNECTORS COMP
+3V3 +3V3-STANDBY +5V 1M19 1M20 5 6 8 8

B02A
+3V3 B03e +5V B03e +5V +3V3 B03e +3V3

PNX85500: NANDFLASH CONDITIONAL ACCESS


+3V3

B03b

+3V3-STANDBY +5V

+12V
+5V +5V 3U16 +3V3 B01h

B01A
+3V3 B03e +5V B03e

COMMON INTERFACE
+3V3 +5V 3F01 +T B03b

B02B
+1V8

PNX85500: SDRAM
+1V8

B03e

DIN-5V

TO IR/LED BOARD

7UC0
3U15
IN OUT COM

B03c +2V5 B02d,h CUA0 +2V5-LVDS B03e B02h

+24V 1C87

+24V 1M59 TO 21 AMBILIGHT MODULE +12V

3S20 3S06 +5VCA

DDR2-VREF-CTRL3 DDR2-VREF-CTRL2 +5V5-TUN B03e

B04E
+3V3

HEADPHONE
+3V3 B03c +12V +3V3-STANDBY

T 2.0A

+5V5-TUN B03c 7UA6 +5V-TUN B01f

+3V3-STANDBY

B01B
+3V3 B03e

FLASH
+3V3 B03e

B02C
+3V3

PNX85500: DIGITAL VIDEO IN


+3V3 B03c +12V 3UA0

B10A B05A
DDR
B03e +1V8 3B20 DDR2-VREF-DDR +3V3 +1V8

DVBT2
+3V3 5FJ1 5FJ2 +3V3-DVBT2-D +3V3-DVBT2-R

ENABLE-1V8 7UA0 VOLT. REG.

+12V B03b +2V5-REF

B01C
+3V3 B03e +5V B03e

USB HUB

B02D
+3V3 B03d +5V 3F32 +T +5V-USB2 B03e +2V5 +3V3

PNX85500: AUDIO
+2V5 +3V3 3S11 +3V3-ARC

7FK1
5FK1 +2V5-DVB
IN OUT COM

B06A B03E
+1V1 B03b B03c B02h +12V

DISPLAY INTERFACING-VDISP
+VDISP-INT B03d 1G03 T 3.0A +VDISP B06a +1V2 9FK6

5FJ3 5FJ4

+2V5-DVBT2-A +2V5-DVBT2-X +1V2 +1V2-FE

DC / DC
+VDISP-INT +1V1 +12V B03h B01,a,b,c,d,e, g,j,k, B02a,c,d,e,h, B03c,f,g,h, B04a,c,d,e, B06b,c,d, B08a,B09a, B10a B03d B01,a,c,e,k, B03c,d,e, B04a,b,d, B09a

7S08
IN OUT COM

+2V5-AUDIO +24V-AUDIO-POWER

B03c

+24V-AUDIO-POWER 3S0Z

7UD1
5UD3
IN OUT COM

5FJ5 5FJ6 5FJ7 B01f +5V-TUN-PIN

+1V2-DVBT2-C +1V2-DVBT2-M +1V2-DVBT2-P +5V-TUN-PIN SSB 3139 123 6519.x

5UD2

+3V3

B01D
+3V3 B03e

SD-CARD
+3V3 3F40 +T +3V3-SD B03e B03c

+24V-AUDIO-VDD

7UD0
5UD0 5UD1
IN OUT COM

+5V5-TUN +5V

B02E
+3V3

PNX85500: MIPS
+3V3 +3V3-STANDBY

6UD0

B06B
+3V3 +VDISP

VIDEO OUT - LVDS


+3V3 +VDISP

+3V3-STANDBY

B03e

B03F
+3V3

TEMPSENSOR + AMBILIGHT
B06a +3V3 5UM1 1UM0 T 1.0A B03e V-AMBI

B01E
+3V3 B03e B03c B03e

PNX85500: CONTROL
+3V3 +3V3-STANDBY B03b +5V +3V3-STANDBY B03c +3V3-STANDBY

B02G
+1V1

PNX85500: STANDBY CONTROLLER


+1V1

B03b

+3V3-STANDBY +5V

B06C
+3V3

AMBILIGHT CPLD
+3V3 5GA0 VINT VIO

B03G
+3V3 B03e B03c +12V

FAN - CONTROL
+3V3 +12V

5GA1

B01F
+5V-TUN B03d

TUNER
+5V-TUN 9F71 +5V-TUN-PIN B03b B03d B03b

B02H
B10a +1V1 +1V2 +1V8 +2V5

PNX85500: POWER
+1V1 +1V2 +1V8 +2V5 +2V5-AUDIO +2V5-LVDS +3V3 +3V3-STANDBY B03e B03c B03c

B06D
+3V3 B03e

SPI-BUFFER
+3V3

B03H
+3V3

VDISP - SWITCH
+3V3 +3V3-STANDBY +12VD

+3V3-STANDBY +12VD 7UU0

B07A
B08a B06a B08a

DVBS-FE
+1V-DVBS +2V5-DVBS +3V3-DVBS 5R00 5R01 +3V3-DEMOD +3V3RF

B01G
+3V3 B03e

TOSHIBA SUPPLY
+3V3

B03d B02d B03d B01k B03e B01k B03c

+1V-DVBS +2V5-DVBS +3V3-DVBS

+2V5-AUDIO +2V5-LVDS +3V3 +3V3-STANDBY

+VDISP-INT

7FA3
IN OUT COM

5FA3 5FA4

+1V2-BRA-VDDC +1V2-BRA-DR1

7UU2 LCD-PWR-ONn

B08a

19100_803_110208.eps 100917

2011-Feb-18 back to

div. table

Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 67

10. Circuit Diagrams and PWB Layouts


10-1 B01 393912364954
Common Interface

B01A
3F01 +5V +T

Common Interface
+3V3

TRANSPORT STREAM FROM CAM


7F00 74LVC245A 1 +5VCA 19 CA-MOCLK CA-MOVAL CA-MOSTRT 3F02 100R 3F03-2 2 100R 7 IF03 1 IF01 2 3F03-1 IF02 3 4 5 6 7 8 9 8 100R 2

2F00

CA-RST RES CA-CD1n CA-CD2n CA-DATAENn 4

3F06

100K

B01A
+3V3

3EN1 3EN2 G3 1 18 17 16 15 14 13 12 11 MOCLK MOVAL MOSTRT

22u 16V

0R3

20

100n

RES 2F01

CA-DATADIR

5 10K 3F07-2 2 7 10K 3F07-3 3 6 10K 3F07-1 1 8 10K 1 8 10K 7 10K 3F08-3 3 6 10K 3F08-4 5 4 10K 3F08-2 3F08-1

3F07-4

CA-ADDENn MOCLK MOVAL MOSTRT

10

MDO0 +3V3 2F02 7F01 74LVC245A 1 19 IF05 CA-MDO0 CA-MDO1 CA-MDO2 CA-MDO3 CA-MDO4 CA-MDO5 CA-MDO6 CA-MDO7 3F04-1 1 8 100R IF06 3F04-3 3 3F05-1 1 3F05-3 3 3F04-2 6 100R 3F04-4 8 100R 3F05-2 6 100R 3F05-4 2 4 2 4 7 100R 5 100R 7 100R 5 100R IF07 3 4 5 6 7 8 9 2 2 1 18 17 16 15 14 13 12 11 MDO0 MDO5 MDO1 MDO2 MDO3 MDO4 MDO5 MDO6 MDO7 MDO6 MDO7 MDO1 RES MDO2 MDO3

20

100n

3EN1 3EN2 G3

1 3F09-1 8 10K 2 3F09-2 7 10K 3F09-3 3 6 10K 3F09-4 4 5 10K 8 10K 7 10K 3F10-3 3 6 10K 3F10-4 4 5 10K 2 3F10-2 3F12 10K 2 3F11-2 7 10K 3F11-3 6 3 10K 4 3F11-4 5 10K 3F11-1 1 8 10K 1 3F10-1

IF04

MDO4

CA-RDY

10

+3V3

CA-WAITn +3V3 CA-INPACKn 2F03 RES CA-WP CA-VS1n

IF08

+5VCA

15-BIT ADDRESS
7F02 74LVC245A

20

100n 1 19 2 2 3 4 5 6 7 8 9 CA-ADDENn CA-A00 CA-A01 CA-A02 CA-A03 CA-A04 CA-A05 CA-A06 CA-A07

+3V3

3EN1 3EN2 G3 XIO-A00 XIO-A01 XIO-A02 XIO-A03 XIO-A04 XIO-A05 XIO-A06 XIO-A07 18 17 16 15 14 13 12 11 1

1P00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

CA-D03 CA-D04 CA-D05 CA-D06 CA-D07 CA-CE1n CA-A10 CA-OEn CA-A11 CA-A09 CA-A08 CA-A13 CA-A14 CA-WEn CA-RDY +5VCA

+3V3 2F04 7F03 74LVC245A RES CA-MIVAL CA-MICLK CA-A12 CA-A07 CA-A06 CA-A05 CA-A04 CA-A03 CA-A02 CA-A01 CA-A00 CA-D00 CA-D01 CA-D02 CA-WP

10

20

100n 1 19 2 2 3 4 5 6 7 8 9 CA-ADDENn CA-A08 CA-A09 CA-A10 CA-A11 CA-A12 CA-A13 CA-A14

3EN1 3EN2 G3 XIO-A08 XIO-A09 XIO-A10 XIO-A11 XIO-A12 XIO-A13 XIO-A14 18 17 16 15 14 13 12 11 1

10

+3V3

8-BIT DATA
7F04 74LVC245A

2F05

RES

20

100n 1 19 2 2 3 4 5 6 7 8 9 CA-DATADIR CA-DATAENn CA-D00 CA-D01 CA-D02 CA-D03 CA-D04 CA-D05 CA-D06 CA-D07

3EN1 3EN2 G3 XIO-D00 XIO-D01 XIO-D02 XIO-D03 XIO-D04 XIO-D05 XIO-D06 XIO-D07 18 17 16 15 14 13 12 11 1

CA-CD1n MDO3 MDO4 MDO5 MDO6 MDO7 CA-CE2n CA-VS1n CA-IORDn CA-IOWRn CA-MISTRT CA-MDI0 CA-MDI1 CA-MDI2 CA-MDI3 +5VCA CA-MDI4 CA-MDI5 CA-MDI6 CA-MDI7 MOCLK CA-RST CA-WAITn CA-INPACKn CA-REGn MOVAL MOSTRT MDO0 MDO1 MDO2 CA-CD2n 71 72

+3V3

10

CONTROL
7F05 74LVC245A

2F06

RES

20

100n 1 19 2 2 3 4 5 6 7 8 9 CA-ADDENn CA-REGn CA-CE1n CA-CE2n CA-OEn CA-WEn CA-IORDn CA-IOWRn XIO-D10

3EN1 3EN2 G3 XIO-D11 XIO-D09 XIO-D08 XIO-OEn XIO-WEn XIO-D14 XIO-D15 CA-WAITn 18 17 16 15 14 13 12 11 1

1X07 REF EMC HOLE

1X04 EMC HOLE

1X08 REF EMC HOLE

1X01 REF EMC HOLE

92789-055LF

2010-12-10

SPB SSB TV550 2K11 4DDR EU

10

3139 123 6495


19100_001_110114.eps 110114

2011-Feb-18 back to

div. table

Circuit Diagrams and PWB Layouts


Flash

Q552.2E LA

10.

EN 68

B01B

Flash

B01B

+3V3

2F20

100n 2F21

7F20 H27U4G8F2DTR-BC

100n 12

[FLASH] 4G 16
XIO-D00 XIO-D01 XIO-D02 XIO-D03 XIO-D04 XIO-D05 XIO-D06 XIO-D07 3F20-1 1 3F20-3 3 3F21-1 1 3F21-3 3 8 6 8 6 100R 3F20-2 100R 3F20-4 100R 3F21-2 100R 3F21-4 2 4 2 4 7 5 7 5 100R 100R 100R 100R IF21 3F22-2 +3V3 XIO-OEn XIO-WEn NAND-WPn +3V3 NAND-RDY1n 2K2 IF23 2 100R 3F22-3 3 10K 3F22-1 1 5 100R 3F24 7 16 17 9 8 18 19 7 29 30 31 32 41 42 43 44 0 1 2 3 IO 4 5 6 7

37

VCC

NC

NAND-CE1n NAND-CLE NAND-ALE

6 8

100R 100R IF22

3F23 3F22-4 4

CLE ALE CE RE WE WP R B

10K

3F19

VSS

1 2 3 4 5 6 10 11 14 15 20 21 22 23 24 25 26 27 28 33 34 35 38 39 40 45 46 47 48

+3V3

13

36

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Circuit Diagrams and PWB Layouts


USB Hub

Q552.2E LA

10.

EN 69

B01C

USB Hub

B01C
IF44 +3V3
2F25 100n

IF43

1u0 2F29

100n 2F27

2F28

100n 2F30

100n 2F31

100n 2F32

2F26

100n 2F33

1F25

10K 2F34

4 2

24M
2F35 10p

CR PLL FILT IF33 IF34

36 23 15 5 10 29

14

34

+3V3

3F28

1M0

7F25 USB2513B-AEZG

VDD_3V3

10p

3F35

USB HUB
OSC1 USBDP_DN1|PRT_DIS_P1 USBDM_DN1|PRT_DIS_M1 BC_EN1|PWRTPWR1 13 2 1 12 17 4 3 16

+3V3 IF35

100n

1u0

USB-DP USB-DM

9F25 9F26 RES 9F29 RES 9F30

USB-DP2 USB-DM2 USB-DP3 USB-DM3

33 32 26 11

3F37 10K

XTALIN|CLKIN XTALOUT RESET

RESET-USBn

IF30

IF36 USB-OC2n USB-DP2 USB-DM2 IF37 19 7 6 18 8 9 20 21


0R3 +T

2 USB-DP USB-DM IF31 IF32

3F31-2 10K

IF42

28 31 30 27 35 22 24 25

OSC2 USBDP_DN2|PRT_DIS_P2 USBDM_DN2|PRT_DIS_M2 SUSP_IND|LOCAL_PWR|NON_REM0 BC_EN2|PWRTPWR2 TEST DP USBUP DM VBUS_DET RBIAS SDA|SMBDATA|NON_REM1 SCL|SMBCLK|CFG_SEL0 HS_IND|CFG_SEL1 GND_HS
37

+5V

+3V3 3F30 3 3F31-3 6 10K IF41

OSC3 USBDP_DN3|PRT_DIS_P3 USBDM_DN3|PRT_DIS_M3 BC_EN3|PWRTPWR3

3F32

USB-OC3n USB-DP3 USB-DM3 3F34-4 100K USB-OC2n

12K IF40

FF33

+5V-USB2

IF39 4 3F31-4 5 10K

NC

3 3F34-3 6 100K 3F34-2 100K 1 3F34-1 100K 8

VIA
38 39 40 41

+3V3

3F36 10K

2 USB-OC3n

SIDE USB
1P08 +5V-USB2 1 2 3 4 IF45

USB-DM2 USB-DP2

FF36 FF37

FF32

5401

FF38 USB-DM3 USB-DP3 FF39 +5V

RES 1F24 1 2 3 4 5

FF30 FF31

6 502382-0570

2010-12-10

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Circuit Diagrams and PWB Layouts


SD Card

Q552.2E LA

10.

EN 70

B01D

SD-Card

B01D

3F40 +3V3 +T 22u 16V 2F40 0R3

FF45

+3V3-SD

+3V3

3F41-4 47K

5 3 3F41-3 47K

IF47 SDIO-DAT3 6 SDIO-CMD SDIO-DAT3 SDIO-CMD

3F44-2 100R

7 3 3F43-3 100R 6

FF47 1P09-1 FF48 1 2 3 4 5 6 7 8 9

3F45 RES 10K 2 3F41-2 7 47K 1 3F42-1 8 47K 1 3F41-1 8 47K

SDIO-CLK

SDIO-CLK

3F44-1 100R

+3V3-SD 8 FF49 FF41 1 3F43-1 8 100R FF42 FF43 13 15

SDIO-DAT0 SDIO-DAT1 SDIO-DAT2

SDIO-DAT0 SDIO-DAT1 SDIO-DAT2

2 3F43-2 7 100R 3 3F44-3 6 100R

14 16

FF46

SCDA7A0200

2 3 3F42-3 6 47K

3F42-2 47K

1P09-2 7 SDIO-CDn SDIO-CDn FF44 10 11 12 SCDA7A0200

SDIO-WP

SDIO-WP

FF50

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Circuit Diagrams and PWB Layouts


PNX85500 Control

Q552.2E LA

10.

EN 71

B01E

PNX85500 Control

B01E

+3V3-STANDBY

+3V3-STANDBY

+3V3-STANDBY
2F49 100p 2F52 100n RES

+3V3

+3V3

+3V3

3F52

3F67

10K

7F52 M25P05-AVMN6 IF50 D 5 IF52 6 IF53 1 IF54 3 7 +3V3-STANDBY

10K

3F66

10K RES

BACKLIGHT-BOOST 7F53 RES PDTA114EU +5V

VCC PNX-SPI-SDI IF51 2 Q

512K FLASH C
S W HOLD VSS
4

PNX-SPI-SDO PNX-SPI-CLK PNX-SPI-CSBn PNX-SPI-WPn BOOST-PWM IF55

3F68 RES

7F54-1 RES BC847BPN(COL) 6 IF56 4 2 1

FF29

IF61 SPI-PROG

7F54-2 RES BC847BPN(COL) IF57

FF04

IF62 SDM

5 3 3F53
RES RES

47K

9CH0

FF58

10K
2F53

3F69

3F54

1u0

+3V3

MAIN NVM DEBUG ONLY


IF58 2F58 RES 100n
8

10K

1K0 RES

SCL-SSB SDA-SSB

FF61

3F62

RES 1F52 100R FF62 1 2 3 5

SCL SDA

7F58
10K

3F58 IF59

1 2 3

(8K 8) EEPROM
0 1 2 ADR

FF63 7 6 5 3F59 100R 3F60 100R FF55 FF56 SCL-UP-MIPS SDA-UP-MIPS

3F63

100R

WC SCL

SDA
4

FF57

DEBUG / RS232 INTERFACE


FF65 FF66 3F64 100R 3F65 100R 7 6 FF64 RES 1F51 1 2 3 4 5

LEVEL SHIFTED UP FOR DEBUG USE ONLY

TXD-UP RXD-UP RESET-STBYn SPI-PROG

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Circuit Diagrams and PWB Layouts


Tuner

Q552.2E LA

10.

EN 72

B01F

Tuner

B01F

IF10

FF71

1T01 4MHZ_REF 15 RF_AGC B+_LNA RF_IO TUN 16

IF11

TUNER
I2C_ADR I2C_SDA I2C_SCL B+_TUN

14 IF_OUT1 IF_OUT2 9F02 9F00 13 NC 9F01 +5V-TUN-PIN 10n 7F75 UPC3221GV-E1 1F75 IF75 O1 O2 5 4 IF81 2F74 10n 2F78 10n GND1 GND2 4 VAGC 10n
AGC CONTROL

9F03

2F71

PNX-IF-P

*
VCC OUTPUT1 7 IF78 2F79 IF74 2F75 10n IF76 1 3F79-1 RES 2F76 5F71 220R IF80 4 3F79-4 220R AF72 2p2 2F77

*
2F70 RES

2F65 RES 1p0

10

11

12

2F72

2F73

IF73 2 IF77 3 INPUT2 INPUT1

5F74

2F62

6p8

6p8

6p8

6p8

6p8

6p8

6p8

1 2 3

OUTPUT2

RES 2F99

RES 2F9D

RES 2F9B

RES 2F97

RES 2F98

RES 2F9C

RES 2F9A

X7251M 36M17

AF73 2F80 2F82

TUN-P1

FF74

*
FF76 100n 4n7 AF71 AF70 FF00 2F61 TUN-IF-N TUN-IF-P IF-AGC IF-AGC 100p 100p PNX-IF-AGC IF82 3F77 4K7 FF01 IF72 9F05 9F06 BA591 2F85 3F71 6F72 3F72 1K0 2F92 +5V-TUN-PIN 4K7 10n IF79 3F80 220R 3F81 220R IF86 2F90 3F78 3K3 10n 5F70 +5V-TUN-PIN TUN-IF-N TUN-IF-P 470n 3 4 ATB2012 10n IF89 2F84 15p 2F86 15p 3F76 47R TUN-P6 3F75 47R TUN-P7 IF88 SDA-TUNER IF87 SCL-TUNER SELECT-SAW RES IF90 7F70 PDTC114EU 5F73 2 1 IF14 IF12 2F63 10n 2F64 10n

*
PNX-IF-N

4n7

RES 2F81

RES 2F59

2F60

* 9F04

IF13 IF5F66 680n 2F66 15p

47n

TUN-P6 TUN-P7

FF81 FF82

RES 2F95

RES 2F96

FF75

2F93

100n

IF15

RES 5F76

820R IF+
4 2010-12-10

GND

* For BR NIM Tuner Only

2F91 RES

* For EU Hybrid Tuner Only

9F71 5F72 RES +5V-TUN 30R 2F88 22u +5V-TUN-PIN

2F94

10n

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330n 3F82 RES

I ISWI

IF16

15p

Circuit Diagrams and PWB Layouts


Toshiba Supply

Q552.2E LA

10.

EN 73

B01G

Toshiba supply

B01G

+3V3

+1V2-BRA-DR1 +1V2-BRA-VDDC

5FA3

5FA4 2FA4

7FA3 LD1117DT12 3 IN OUT COM 2 FFAF

2FA2

2FA3

100n

100n

30R

FFA2

10u

30R

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Circuit Diagrams and PWB Layouts


HDMI

Q552.2E LA

10.

EN 74

B01H

HDMI

B01H

HDMI CONNECTOR SIDE


1P05 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 FFB5 21 23 DRX2+ DRX2DRX1+ DRX1DRX0+ 1 3FBF-1 8 DRX-DDC-SCL DRX-DDC-SDA DRX0DRXC+ DRXCPCEC-HDMI FFB1 FFB2 FFB3 FFB4 20 22 FFB6 DIN-5V DRX-HOTPLUG DRX-DDC-SCL DRX-DDC-SDA DIN-5V

47K 2 3FBF-2 7 47K

DIN-5V

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Circuit Diagrams and PWB Layouts


VGA

Q552.2E LA

10.

EN 75

B01I

VGA

B01I
FFC1 CDS4C12GTA 12V 3FC5 18R R-VGA

RES 2FC1

FFC2 CDS4C12GTA 12V

RES 6FC1

1FC1

100p

3FC6 18R

G-VGA

RES 2FC2

1E05 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 FFC6 1216-02D-15L-2EC FFC7

RES 6FC2

1FC2

100p

3FC7 CDS4C12GTA 12V FFC3 RES 2FC3 RES 6FC3 1FC3 100p 18R

B-VGA

VGA CONNECTOR

FFC4 FFC5

9FC5 RES 6FC4 CDS4C12GTA 12V 2FC4 1FC4

H-SYNC-VGA

3FC3

17

4K7

47p

9FC6 CDS4C12GTA 12V RES 6FC5 2FC5 1FC5 3FC4

V-SYNC-VGA

47p

4K7

RES 3FC1 10K

9FC1 FFC8 CDS4C12GTA 12V 9FC2 RES RES 6FC6

VGA-SDA-EDID-HDMI VGA-SDA-EDID

2FC6

47p

RES 3FC2 10K

9FC3 FFC9 CDS4C12GTA 12V 9FC4 RES

VGA-SCL-EDID-HDMI VGA-SCL-EDID

2FC7

RES 6FC7

47p

+5V-VGA RES 6FC8 CDS4C12GTA 12V 2FC8 1FC6

47p

2010-12-10

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Circuit Diagrams and PWB Layouts


Temp sensor & headphone

Q552.2E LA

10.

EN 76

B01J

Temp sensor & headphone

B01J

+3V3 9FD1 RES 9FD2 RES RES 3FD1

1K0

2FD1

3FD2 IFD5 9FD5 1K0

100n

LTST-C190KGKT

RES

6FD1

7FD1 LM75BDP 3 1 2 OS SDA

+VS

A0 A1

7 6 5

IFD1 IFD3

SDA-SSB SCL-SSB 3FD4 100R

3FD3 100R

IFD2 IFD4

GND

SCL

A2

1K0 3FD7

3FD6

RES

1K0

RES 1329 1 2 3

502382-0370

AMP1 AMP2 CDS4C12GTA 12V 1FD3 CDS4C12GTA 12V 2FDC

FFDA

1328 MSJ-035-12D-B-AG-PBT-BRF 2 3 1

FFDB 22n 2FDD 22n FFDC

3FDG-2

1K0 3FDG-1

1FD2

6FD2

RES

RES

6FD3

1K0

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Circuit Diagrams and PWB Layouts


Tuner Brazil

Q552.2E LA

10.

EN 77

B01K

Tuner Brazil

B01K

5FE0 +2V5-BRA 30R

IF63

IF64 +1V2-BRA-VDDC 2FE3

2FE0

100n 2FE4

100n 2FE5

100n 2FF0

100n 2FF1

1u0

1u0

AGND 5FE3 30R 2FE6 100n 2FF3 100n 2FF5 2FF2 100n 2FF4 100n 2FF6 1u0 1u0 IF65 IF66 +3V3-BRA-FLT

+3V3-BRA-FLT

5FE4 +3V3-BRA 30R

AGND 5FE5 30R 2FE8 2FF7 100n 2FF8 100n 2FF9 1u0 1u0 +3V3 30R IF67 IF68 +1V2-BRA-DR1 5FE7 IF48 +3V3-BRA

IF69

5FE8 +2V5-BRA 30R 2FG0 1u0 7FE3 LD3985M25 5FE9 +5V 30R 1 3 IN INH OUT BP 5 4 FF03 +2V5-BRA

2FG2

2FG3

18p

18p

25M4 4

100n 2FG1

1FE0

COM 2FH2 2FH3 2FH4 10n 1u0 AGND AGND AGND 1u0 2 7FE0 TC90517FG 19 18 3 2 IF+ IF2FG4 10n 2FG6 2FG7 AGND 100n 2FG8 100n 2FH6 2FH7 10n IF17 IF18 BFE2 BFE3 100n 100n 30 29 28 27 24 25 26 39 +3V3-BRA-FLT 40 8 3FE6 10K 1 41 10K IF29 7 11 SCL-SSB SDA-SSB 3FE8 100R 3FE9 IF49 100R 45 46 I X O 16 36 56 63 13 35 49 64 22 20 34 48 DR1VDD 32 43 DR2VDD

AD_DVDD

AD_AVDD

PLLVDD

VDDC

VDDS

FIL

21 58 53 54 55 59 52 61 60 38 9 10 51 42 6 5 12 14

2FH5 1n5 DFE6 DFE7 DFE8 3FG6-3 DFE9 3 6 33R TS-BR-SOP 2 AGND 3FG6-4 4 5 33R TS-BR-VALID 1

* To be drawn near PNX85500

PBVAL RERR RLOCK

9F27-1

TS-FE-VALID

0 XSEL 1 P ADI_AI N P ADQ_AI N P AD_VREF N AD_VREF DTCLK DTMB S_INFO 0 TSMD 1 AGCI CKI PLLVSS SCL SDA AD_AVSS AD_DVSS

RSEORF SBYTE SLOCK SRCK SRDT STSFLG1 AGCCNTI AGCCNTR STSFLG0 SYRSTN 0 SLADRS 1 TN VSS 4 15 33 37 44 47 50 57 62 SCL SDA

9F27-2

TS-FE-SOP 5FG0

100n

2FG9

3FG7 3FG6-2 DFF1 2

33R 7

TS-BR-CLOCK 4

9F28 9F27-4 5

* *

TS-FE-CLOCK TS-FE-DATA

30R 5FG2 30R

AGND

33R TS-BR-DATA

AGND

IF27

3FE5 18K

IF28 IF-AGC 2FH8 10n

AGND

DFF2

3FE7

3FG2-1 10K 3FG4-2 4K7 3FG4-1 4K7 3FG2-2 10K +3V3-BRA-FLT

RESET-SYSTEMn

23

31

AGND

AGND

17

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Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 78

10-2 B02 393912364954


NANDflash - conditional access

B02A

PNX85500: NANDflash - conditional access


+3V3

B02A

3S1W

7S00-5 PNX85500

FLASH

NAND-ALE NAND-CLE

D22 ALE NAND C21 CLE J25 J26 H21 H22 H23 H24 H25 H26 G21 G22 G23 G24 G25 G26 F22 F23 00 01 02 03 04 05 06 07 XIO_A 08 09 10 11 12 13 14 15

XIO-A00 XIO-A01 XIO-A02 XIO-A03 XIO-A04 XIO-A05 XIO-A06 XIO-A07 XIO-A08 XIO-A09 XIO-A10 XIO-A11 XIO-A12 XIO-A13 XIO-A14 XIO-A15

00 01 02 03 04 05 06 07 XIO_D 08 09 10 11 12 13 14 15 XIO

D25 D26 C24 D23 C23 B23 A22 E22 F24 F25 F26 E23 E24 E25 E26 D24

10K XIO-D00 XIO-D01 XIO-D02 XIO-D03 XIO-D04 XIO-D05 XIO-D06 XIO-D07 XIO-D08 XIO-D09 XIO-D10 XIO-D11 INPACK XIO-D14 XIO-D15 XIO-OEn XIO-WEn +3V3
NAND-CE1n

INPACK

IS26

3S15 10K

B22 OE_ C22 WE_ B21

CLK_BURST

IS25

E21 CE1_ D21 CE2_ A20 NAND RDY2 F21 RDY1 A21 WP_

3S1V

9S08 IS00

NAND-RDY1n NAND-WPn

+3V3

3S1X

7S00-11 PNX85500 CA-MDI0 CA-MDI1 CA-MDI2 CA-MDI3 CA-MDI4 CA-MDI5 CA-MDI6 CA-MDI7
CA-ADDENn CA-DATADIR CA-DATAENn

3S01-1 33R 3S01-3 6

8 3S01-2 2

3 33R 33R 5 3S02-4 4 33R 7 3S02-2 2 33R 3S02-1 1 3 33R 6 3S02-3 33R 5 3S01-4 4 33R

P21 7 P22 P23 P24 P25 8 P26 N21 N22 J22 K25 K26

0 1 2 3 MDI 4 5 6 7

VIDEO_STREAM

0 1 2 3 MDO 4 5 6 7

N26 M21 M22 M23 M24 M25 M26 L21

10K

10K RES

CA-MDO0 CA-MDO1 CA-MDO2 CA-MDO3 CA-MDO4 CA-MDO5 CA-MDO6 CA-MDO7

ADD_EN DATA_DIR DATA_EN I MCLK O MISTRT MIVAL MOSTRT MOVAL OOB_EN RDY RST VCCEN VPPEN T21 DATA T23 ERR T22 TNR_SER1 MICLK R23 MIVAL R22 SOP
TS-FE-DATA TS-FE-ERR TS-FE-CLOCK TS-FE-VALID TS-FE-SOP

VS

K23 1 K24 2 K21 1 K22 2

9S00

CA-VS1n CA-MOCLK CA-CD1n CA-CD2n

CA-MICLK CA-MOCLK

3S03 10R

N23 L25 N24 3S31

CD

CA
3S1R 3S1S 3S1T 3S1U RES RES TS-FE-DATA TS-FE-CLOCK TS-FE-VALID TS-FE-SOP 3S23 470R 3S24 470R 3S28 470R 3S29 RES RES 470R 560R 560R 560R 560R

+3V3

CA-MIVAL 33R CA-MOSTRT CA-MOVAL

N25 L22 L23 J21

TS-FE-DATA TS-FE-CLOCK TS-FE-VALID TS-FE-SOP

CA-RDY CA-RST

L24 L26 RES 9S01 +3V3 J23 J24

CA-MISTRT

3S04 2S09

100n

33R

7S02 5 1 4 2 3
4 2010-12-10

74LVC1G08GW

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Circuit Diagrams and PWB Layouts


SDRAM

Q552.2E LA

10.

EN 79

B02B

PNX85500: SDRAM

B02B

7S00-8 PNX85500 DDR2-BA0 DDR2-BA1


DDR2-BA2

H1 H2 G1 D1 D5 R3 T5 F3 C2 F2 C3 B4 F1 C1 E1 F4 B2 E5 C5 A4 G5 B3 F5 U3 P2 U2 P3 N1 U1 P1 T1 V4 R5 U5 P5 N3 V3 R4 V5

0 1 BA 2

MEMORY

DDR2-DQM0 DDR2-DQM1 DDR2-DQM2 DDR2-DQM3 DDR2-D0 DDR2-D1 DDR2-D3 DDR2-D2 DDR2-D6 DDR2-D5 DDR2-D4 DDR2-D7 DDR2-D8 DDR2-D9 DDR2-D10 DDR2-D11 DDR2-D12 DDR2-D13 DDR2-D14 DDR2-D15 DDR2-D16 DDR2-D17 DDR2-D19 DDR2-D18 DDR2-D22 DDR2-D23 DDR2-D20 DDR2-D21 DDR2-D24 DDR2-D30 DDR2-D26 DDR2-D25 DDR2-D28 DDR2-D31 DDR2-D27 DDR2-D29

0 1 DM 2 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DQ 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

M0

+1V8

0 1 2 3 4 5 6 7 A 8 9 10 11 12 13 14 N P N P N P N P N P

J1 J3 K1 G4 L3 G3 L2 H5 L1 J5 J2 M3 J4 M2 K5 N5 N4 E2 E3 D3 D4 R1 R2 T3 T4 K3 K4 L5 M4 M1 M5 H3 A2 V1 100p 2S20 100n 2S17 DDR2-VREF-CTRL2 DDR2-VREF-CTRL3 2S24 100n 2S25 100p 1% IS42 261R 3S30 10R 3S33 10R

DDR2-A0 DDR2-A1 DDR2-A2 DDR2-A3 DDR2-A4 DDR2-A5 DDR2-A6 DDR2-A7 DDR2-A8 DDR2-A9 DDR2-A10 DDR2-A11 DDR2-A12 DDR2-A13 DDR2-A14 DDR2-CLK_N DDR2-CLK_P DDR2-DQS0_N DDR2-DQS0_P DDR2-DQS1_N DDR2-DQS1_P DDR2-DQS2_N DDR2-DQS2_P DDR2-DQS3_N DDR2-DQS3_P DDR2-CAS DDR2-CKE DDR2-CS DDR2-ODT DDR2-RAS DDR2-WE 3S6Q 10K 3S6P 10K RES

100u 2.0V

180R 1%

180R 1%

CLK

3S20

3S06

2S12

FS02 DDR2-VREF-CTRL3 180R 1% DDR2-VREF-CTRL2 180R 1% 3S22 FS01

DQS0

DQS1

3S07

DQS2

DQS3

CASB CKE CSB ODT PCAL RASB WEB VREF 1 2

DDR2-CKE

DDR2-ODT

3S0V

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Circuit Diagrams and PWB Layouts


Digital video in

Q552.2E LA

10.

EN 80

B02C

PNX85500: Digital video in

B02C

7S00-6 PNX85500 HDMIA-RX2+ HDMIA-RX2HDMIA-RX1+ HDMIA-RX1HDMIA-RX0+ HDMIA-RX0HDMIA-RXC+ HDMIA-RXC+3V3 3S0W 12K RES 2S2E 10u IS01 W24 RREF T25 T26 P RX0_A N

HDMI_DV

U25 P U26 RX1_A N

DDC_A

V25 P V26 RX2_A N HOT_PLUG_A W25 P W26 RXC_A N

Y26 SCL Y25 SDA T24

DDCA-SCL DDCA-SDA IS10

2010-12-10

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Circuit Diagrams and PWB Layouts


Audio

Q552.2E LA

10.

EN 81

B02D
AUDIO-IN1-L

PNX85500: Audio
3S0Z 3S53-1 100R 3S53-2 1 IS1H 8 1 3S16-1 8 10K 2 3S16-2 100R 3S53-3 100R 2S2R 10u 3S53-4 2S2V 100R 1u0 3S16-3 3 6 10K 3S16-4 5 4 10K 3S13-4 4 22K 3S13-3 6 22K 3S13-1 1 22K 3S13-2 22K 7 1u0 3S10 100R IS1B 8 IS1Q 3S17-2 2 7 10K IS1P 1 3S17-1 8 10K 5 3 3S17-3 6 10K IS0R 4 3S17-4 5 10K IS0V 2S2Z IS1M 1u0 100u 4V 3S51 4R7 2S42 2S41 1u0 2S2Y 1u0 2S31 1u0 2S30 1u0 2S33 1u0 2S32 7S00-2 PNX85500 2 3S36-2 10K 7 10K 3S36-1 2S2G 47p +24V-AUDIO-VDD 2S36 1u0 IS1N 1 3S3G-1 8 33R 3 3S3G-3 33R 6 ADAC(1) ADAC(2) ADAC(2) IS03 10 9 11 ADAC(3) ADAC(4) 4 7S05-3 LM324 8 3S39 100R 1 8 7S08 LD3985M25 FS08 IS12 4 5 OUT BP IN INH 1 10u RES 3 IS13 1u0 RES 4S14 +2V5 ADAC(1) IS02 12 13 11 +2V5-AUDIO +3V3 2S3J 220n +24V-AUDIO-POWER 4R7 +24V-AUDIO-VDD

B02D
2S2W 1u0 FS03 4 7S05-4 LM324 14

3S12-1 22K

2S2T

AUDIO-IN3-L

AUDIO-IN3-R

AUDIO AE10 AC7 L P AF10 AB7 AIN1 ADACL R N


AD10 L AC10 AIN2 R AE9 L AF9 AIN3 R AD9 L AC9 AIN4 R AF8 L AE8 AIN5 R AB9 POS AB8 VR_AADC NEG AD8 AC6 P AB6 ADACR N 1 2 3 ADAC 4 5 6 AD7 AE7 AF7 AD6 AE6 AF6

2S34

22K

100n

AUDIO-IN1-R

2 3S12-2

IS1J 7

7 10K

2S2S

3S38 100R

+AUDIO-L

COM 2

-AUDIO-R

AUDIO-IN4-L

3S3G-2 2 7 4 IS1S 3S3G-4 33R 5 33R

AUDIO-IN4-R

2S2L IS19 1u0

I2S_OUT

AD4 OSCLK AD1 SCK AD2 WS

3 3S3H 33R 3S3U 33R


ADAC(6) ADAC(5)

3S36-3 10K

10K 3S36-4 2S2H 47p +24V-AUDIO-VDD 4 5

IS1A 3S3F 56R 10u 2S3G 100n 2S3H 10u 2S3E 2S3F 100n 9S06 RES DBS8

AE1 1 AF2 VREF_AADC 2 AE3 I2S_OUT_SD 3 AC8 AF3 VCOM_AADC 4 AF5 AE5 SPDIF_OUT SPDIF_IN1

2S3D

1n0 2S3C

1n0 2S3B

1n0 2S3A

1n0 2S39

1n0 2S38

1n0

IS07 ADAC(5) 3 2

7S05-1 LM324

AUDIO-OUT-L

11

3S37 10K

3S6L 22K 2S2K 47p +24V-AUDIO-VDD

+3V3 +3V3-ARC

3S11 1R0 2S3Q

IS1L

100n

ADAC(6) IS06

5 6

7S05-2 LM324 7

AUDIO-OUT-R

SPDIF-OUT-PNX

SPDIF-OUT-PNX

IS1D

7S09-1 74LVC00APW 1 2

11 14

&
3

2S3K 100n

IS1G

1 3S18-1 8 7 3S18-2 3S18-3 6 220R

SPDIF-OUT

3S34 220R 10K

3S32 22K 2S2J 47p

+3V3

220R

+3V3

+3V3-ARC 3S19 10K 7S09-2 74LVC00APW 4 IS1E 5 7 +3V3 10 7 +3V3-ARC 14 7S09-3 74LVC00APW 9

&
6

14

&
8

SEL-HDMI-ARC

2S3L 100n

180R 3S6M

IS1K

2S3M 100n 3S25 68R

IS44
eHDMI+

+3V3-ARC 7S09-4 74LVC00APW 12 +3V3 13 7

14

&
11

2010-12-10

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Circuit Diagrams and PWB Layouts


MIPS

Q552.2E LA

10.

EN 82

B02E
3S45 +3V3 10K +3V3 3S40 10K 3S82 +3V3 +3V3 +3V3 +3V3 10K 3S62 +3V3 10K 3S80 3S81 10K 10K 10K

PNX85500: MIPS

B02E
7S00-3 PNX85500 +3V3

CONTROL
IS05
BOOTMODE BOOTMODE 3D-LR RXD1-MIPS TXD1-MIPS RXD2-MIPS TXD2-MIPS

1 Y21 IS16 Y22 Y23 Y24 W21 W22 W23 V22 V23 U23 GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7 GPIO_10 GPIO_11

C25 SDA C26 SCL

1 100R

3S56

2 1 100R 1 100R 1 100R 1 100R 2 3S57

SDA-UP-MIPS SCL-UP-MIPS SDA-SET SCL-SET SDA-SSB SCL-SSB SDA-TUNER SCL-TUNER EJTAG-TRSTn-PNX85500 EJTAG-TMS-PNX85500 EJTAG-TCK-PNX85500 EJTAG-TDO-PNX85500 EJTAG-TDI-PNX85500

SDA-UP-MIPS SCL-UP-MIPS SDA-SET SCL-SET SDA-SSB SCL-SSB SDA-TUNER SCL-TUNER EJTAG-TRSTn-PNX85500 EJTAG-TMS-PNX85500 EJTAG-TCK-PNX85500 EJTAG-TDO-PNX85500 EJTAG-TDI-PNX85500

3S69 3S6A 4K7 3S6B 3S6C 4K7 3S6D 3S6E 2K2 3S6F 3S6G 2K2 3S6K 1 10K 8 3S6H-1 10K 3 6 3S6H-3 2 10K 10K +3V3-STANDBY 7 3S6H-2 5 3S6H-4 4 10K FS57 +3V3 2K2 2K2 EJTAG-DETECTn FS53 4K7 4K7 EJTAG-TRSTn-PNX85500 EJTAG-TMS-PNX85500 EJTAG-TDO-PNX85500 EJTAG-TCK-PNX85500 EJTAG-TDI-PNX85500 FS44 FS49 FS50 FS51 FS52

RES 1F10 1 2 3 4 5 6 7 8

3D-LR

IS17

9S09

B26 SDA A25 2 SCL 3 B25 SDA A24 SCL

3S58 1 2 100R 1 3S5Y 2 100R 1 100R 3S60 2

2 3S5W

DS52 BOOST-PWM FS10 TXD2-MIPS FS11 RXD2-MIPS IS04 GPIO6

FOR FACTORY USE ONLY

3S5Z

GPIO6
PNX-SPI-CS-BLn BOOST-PWM SELECT-SAW USB-DM USB-DP

B24 SDA A23 4 SCL TRSTN TMS TCK TDO TDI AA25 AA24 AA23 AB26 AB25 AE4 AD5 AC5

10 9

3S61

RES 3S21

PNX-SPI-CS-BLn

R26 DN R25 USB IS4Z R24 DP RREF 3S55 5K6

BM08B-SRSS-TBT

3S00 33R

RESET_SYS BL_PWM CLK_54_OUT

RESET-SYSTEMn BACKLIGHT-PWM

3S64 +3V3 10K

FS64

SELECT-SAW

3S26

3S27

3S6J

3S83 +3V3 10K 3S84 +3V3 10K

RXD1-MIPS 3D-VS TXD1-MIPS BACKLIGHT-PWM 3S4A IS14

RES 10K

10K

+3V3 3S72 47R 100R IS15 3D-VS-DISP 3S4B 100R RES

+3V3 IS40
PXCLK54

10K

RES

+3V3 2S89 100n 7S01 PCA9540B 3 +3V3 3S65

VDD

SC0 SC1

5 8 4 7

SCL-DISP SCL-BL SDA-DISP SDA-BL

SCL-DISP SCL-BL SDA-DISP SDA-BL

SCL-SET SDA-SET

1 2

SCL SDA
INP FIL

I2 C -BUS CTRL

SD0 SD1

1 4K7 1 4K7 3S67 1 4K7 3S68 2 1 4K7 3S66

2 2 2

VSS 6 FS31 9S10 IS08


SCL-SET

SCL-BL

9S11 9S12

FS2W FS2Y

SCL-DISP SDA-DISP SDA-BL

SDA-SET

IS09

9S13

7S00-4 PNX85500
ETH-RXCLK ETH-RXD(0) ETH-RXD(1) ETH-RXD(2) ETH-RXD(3) ETH-RXDV ETH-RXER SDIO-DAT3 SDIO-CLK SDIO-CMD SDIO-DAT0 SDIO-DAT1 SDIO-DAT2 SDIO-CDn SDIO-WP

AA3

RXCLK

ETHERNET
TXCLK 0 1 2 3 TXEN TXER COL CRS MDC MDIO AA2 AA1 AA4 AB1 AB2 AA5 AB3 AC3 Y2 Y3 Y1
ETH-TXCLK ETH-TXD(0) ETH-TXD(1) ETH-TXD(2) ETH-TXD(3) ETH-TXEN ETH-TXER ETH-COL ETH-CRS ETH-MDC ETH-MDIO

IS50

Y5 0 Y6 1 RXD ETH AB4 2 AC1 3 AC2 RXDV Y4 RXER W2 W1 W6 W5 W4 W3 U6 V6

TXD ETH

CC_DAT3 CLK CMD 0 SDIO 1 DAT 2 SDCD SDWP

2010-12-10

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Circuit Diagrams and PWB Layouts


Video out - LVDS

Q552.2E LA

10.

EN 83

B02F

PNX85500: Video out - LVDS

B02F

7S00-7 PNX85500 PX1APX1A+ PX1BPX1B+ PX1CLKPX1CLK+ PX1CPX1C+ PX1DPX1D+ PX1EPX1E+ PX2APX2A+ PX2BPX2B+ PX2CLKPX2CLK+ PX2CPX2C+ PX2DPX2D+ PX2EPX2E+ 9S92 9S93 9S90 9S91 A7 B7 C8 B8 N A P N B P

LVDS
A

N P N P

D7 E7 E8 D8 9S94 9S95

PX3APX3A+ PX3BPX3B+ PX3CLKPX3CLK+ PX3CPX3C+ PX3DPX3D+ PX3EPX3E+ PX4APX4A+ PX4BPX4B+ 9S96 9S97 PX4CLKPX4CLK+ PX4CPX4C+ PX4DPX4D+ PX4EPX4E+

C10 N B10 CLK P A9 B9 N C P LOUT1 LOUT3

CLK

E10 N D10 P N P D9 E9

A11 N B11 D P C12 N B12 E P A14 N B14 A P C15 N B15 B P C17 N B17 CLK P A16 B16 N C P A18 B18 N D P C19 B19 N E P LOUT2 LOUT4

D11 N E11 P E12 N D12 P D14 N E14 P E15 N D15 P E17 N D17 P D16 N E16 P D18 N E18 P E19 N D19 P

CLK

2010-12-10

SPB SSB TV550 2K11 4DDR EU

3139 123 6495


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Circuit Diagrams and PWB Layouts


Standby controller

Q552.2E LA

10.

EN 84

B02G

PNX85500: Standby controller


+1V1 POL

B02G
IS3B RES 5S04 30R

1u0 2S10

2S13 2S37 9S24 RES 1u0 2S11 100n

IS20

100n

DS50 AC17 1 7S00-9 PNX85500 XTAL_IN XTAL_OUT RESET_IN EA ALE PSEN MC AE17 AF17 AA26 AB24 AB23 AC26 3S2F 100R 3S2H 100R 100R

3 1S02 2 4 1 54M

2S4G 10p 2S4F 10p +3V3-STANDBY

AA17

VDDA_ADC2V5

AF26

+3V3-STANDBY 3S1C 3S1E 10K +3V3-STANDBY 3S3M 10K 3S3P 10K RES 3S3S 10K 3S3T +3V3-STANDBY 3S1H 10K 10K RES 10K RES 3S1F 3S3L

3S1B 10K 3S1D 27K 10K

RC TACHO CEC-HDMI BACKLIGHT-PWM-ANA-DISP SDM LCD-PWR-ONn EJTAG-DETECTn LAMP-ON STANDBY FAN-CTRL1 FAN-CTRL2 POWER-OK ENABLE-3V3n RXD-UP TXD-UP DETECT2

2S4D 1n0

RC TACHO CEC-HDMI BACKLIGHT-PWM-ANA-DISP SDM LCD-PWR-ONn EJTAG-DETECTn LAMP-ON STANDBY FAN-CTRL1 FAN-CTRL2 POWER-OK ENABLE-3V3n RXD-UP TXD-UP DETECT2

AD19 0 AE19 1 AF19 2 P1 AA20 3 AB20 7 AC20 0 AD20 1 AE20 2 AF20 3 P2 AA21 4 AB21 5 AC21 6 AD21 7 AE21 0 AF21 1 AA22 2 P3 AB22 3 AC22 4 AD22 5 AD23 0 AE26 1 P5 AE25 2 AE24 3

VDDA_1V1_DCS

VDD_XTAL

RESET-STBYn IS3F EA ALE PSEN SDA-UP-MIPS SCL-UP-MIPS LED1 LED2 PNX-SPI-SDO PNX-SPI-SDI PNX-SPI-CLK PNX-SPI-CSBn IS2V IS2Z CTRL-DISP RESET-DVBS RESET-USBn RESET-ETHERNETn SEL-HDMI-ARC RESET-AVPIP RESET-AUDIO AUDIO-MUTE-UP CTRL-DISP RESET-DVBS RESET-USBn RESET-ETHERNETn SEL-HDMI-ARC RESET-AVPIP RESET-AUDIO AUDIO-MUTE-UP RES 10K RES 3S3Y 10K 10K 3S2S RES 3S3W 4K7 3S2L RES 10K RES 10K 10K 4K7 3S46 3S47 3S2M RES 3S49 +3V3-STANDBY EA ALE PSEN
SDA-UP-MIPS SCL-UP-MIPS

RES 10K 3S3N RES 10K 3S3Q RES 10K 3S3R 10K RES

STANDBY

3S44 10K 10K 3S42 3S6V 4K7 RES 3S1P 10K 10K 4K7 3S43 10K

IS3E IS3D RES

AC23 SDA AC24 SCL

3S2G

3S6W RES

3S1G 10K 3S2A 10K RES

AD26 0 PWM AC25 1 AE23 SDO AF25 SDI SPI AF24 CLK AF23 CSB AB17 0 AA18 1 AD18 2 AE18 3 P0 AF18 4 AA19 5 AB19 6 AC19 7

100R

LED1 LED2

3S2K

3S41

3S1K 10K RES

RESET-SYSTEMn 3S1J 100K RES 3S1L 10K 2S4E 100n SPI-PROG KEYBOARD

VSS_XTAL

RESET-SYSTEMn AV2-BLK AV1-BLK KEYBOARD LIGHT-SENSOR AV1-STATUS AV2-STATUS SPI-PROG PNX-SPI-WPn

AF22 4 P6 AE22 5

AD17

+3V3-STANDBY

+3V3-STANDBY

1 3S2V 2

9S0E

1K0

FS45 1

7S20 NCP303LSN28 2 IS2U 5

FS0Z

RESET-STBYn

INP OUTP CD NC GND 3

9S0D

2S4K

100n

RES

2010-12-10

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Circuit Diagrams and PWB Layouts


Power

Q552.2E LA

10.

EN 85

RES 10u

2S6A

2S5A

100n

B02H

PNX85500: Power

IS3Q 2

5S80 +1V1 30R

B02H

5S81 +2V5 RES 10u 30R 2S5B 100n 2 +1V8 2S26 100n 2S61 100n 2S65 100n 2S63 100u 2S60 2S62 100n 2S64 100n 2S66 100n 2S67 100n 2S68 100n 100n IS3S 2 RES 10u 1 2S6B

5S82 +3V3 30R 2S5C 2S5D 100n

SENSE+1V1

c001 7S00-10 PNX85500 L6 L7 R6 R7 U7 A5 A6 B5 B6 C6 D6 E6 F6 G6 F7 G7

5S93 2 30R 100n 2S6E 2 220u 6.3V 2S4M 100n +2V5

+1V1 8 7 5 8 6 2S5G-1 100n 2S5G-3 100n 2S5G-2 100n 2S5G-4 100n 2S5H-1 2S4Q 22u 2S4R 2S43 2S28 2S27 100n 100n 100n

7S00-12 PNX85500 A1 A10 A12 A15 A17 A19 A26 A3 A8 B1 B20 C20 C4 D2 D20 E13 E20 E4 F10 F12 F14 F16 F18 F20 F8 G10 G12

VSSA

VSS

VSS

VSS

VSSA_1V1_LVDS_PLL

VSSA_2V5_LVDS_BG

2S46

VSSA_USB

VSS G14 G16 G18 G2 G20 G8 H4 H6 H7 J20 K10 K12 K14 K16 K18 K2 K6 K7 L20 L4 M10 M12 M14 M16 M18 M6

+1V1

J7 2

30R 2S4S 10u RES

VDD_1V1_DDR

VDDA_2V5_VDAC VDDA_3V3_USB

Y10 R21

2S5P

2S21

100n

1u0

C13

R20

A13

100n

5S94

U24 V24 HDMI_AGND

M7 N2 N20 P10 P12 P14 P16 P18 P4 P6 P7 T10 T12 T14 T16 T18 T2 T6 T7 U4 V10 V12 V14 V16 V18 V2 Y20

AF1 AE2 AD3 AC4 AB5 H20 F11 G11 F13 G13 F15 G15 F17 G17 F19 G19 J9 J11 J13 J15 J17 L9 L11 L13 L15 L17 N9 N11 N13 N15 N17 R9 R11 R13 R15 R17 U9 U11 U13 U15 U17 J6 AA6 Y7 W7 F9 G9

HDMI_VDDA_1V1

V20 V21 U20 U21 U22 N6 N7 C7 C9 C11 C14 C16 C18 W20 P20 M20 K20 V7 Y8 Y19 Y18 IS3K B13

100n 2S5H-2

100n 2S5H-3

100n 2S5H-4

2S23

100n

100u

22u

VDD

2S6D

VDD_1V8

HDMI_VDDA_2V5 HDMI_VDDA_3V3_TERM VDD_2V5

+2V5-LVDS 2S4N 2S4P

100n

2S5K-1

100n 2S5K-2

100n 2S5K-3

100n 2S5K-4

100n 2S5J-3

100n 2S5J-1

100n 2S5J-2

100n 2S5J-4

100n

220u 2.5V

2S29

10u

VDD_2V5_LVDS

5S85 100n 1 2S6G 2 100n 2S6N 100n 2S6C 2S6P 2S6F 100n 10u 30R +3V3 2 2 2 1

AA16 AA8 Y11 Y14 Y16 Y9

VDD_3V3

+3V3-STANDBY 10u 2S4U 2S4V 100n 5S83 +1V1 RES 1u0 2S4W 2S4Y 100n IS3L 30R 5S84 6.3V 30R 2S4Z 2S50 100n 10u 30R c000
SENSE+1V2

VDD_1V1 VDD_3V3_SBY VDDA_1V1_LVDS_PLL

AA15 Y15 VDDA_1V2 AA13 VDDA_2V5 VDDA_2V5_AADC VDDA_2V5_ADAC VDDA_2V5_DCS VDDA_2V5_LVDS_BG VDDA_2V5_USB VDDA_2V5_VADC Y12 AA9 2S51 AA7 Y17 D13 T20 Y13 2S52 100n

5S95

+2V5

+1V2

10u

POL +2V5-AUDIO

+2V5-AUDIO 2S45 100n

5S87 +2V5 30R 2S55 2S56 100n 1u0 5S88 +2V5-LVDS 2S5M 100n 2S57 10u 30R 5S89 +2V5 100n 2S58 10u 30R 2S6H 2 100n 2S6K 1 2 5S90 +2V5 30R 2S4T 2S53 100n 10u 5S92 +3V3 100n 2S59 1u0 30R
4 2010-12-10

2SHW IS58

100n

2S6M

100n 2S6L

SPB SSB TV550 2K11 4DDR EU

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Circuit Diagrams and PWB Layouts


Analog video

Q552.2E LA

10.

EN 86

B02I
Connectivity

PNX85500: Analog video


AV1-CVBS 22n 3S59 47R 2S87 2S8A 22n 3S5B 47R Y-SVHS

B02I
2S22 22n C-SVHS 3S05 56R

AV1-R 22n 3S4J 56R

2S7J

EU: SCART1
3S5E 22n 3S4L 56R 560R

CVBS-MON-OUT1 AV1-B 2S7K

AP:

IS4V 560R 8K2 2S40 3S08 3S09 YPBPR1-SYNCIN1 2S7M 10n 2S7L 3S4P 56R 22n AV3-Y 2S7N AV3-PR 56R 47p IS4W 7S00-1 PNX85500 2S7P AV3-PB 2S19 2S18 22n 2S16 22n 2S15 22n 3S4T 56R 22n 22n IS5C 2S14 22n AB15 AC13 AD13 AE13 2S8G 22n AF15 AE15 AC15 AD15 AB14 AF14 AE14 AC14 AD14 AF16 AD16 AE16 AB18 AC18 AF4 AD24 AD25 CVBS_Y1 ATV_CVBS_Y3 R C3 B AV1 CVBS_Y7 G C7 SYNCIN1 Y_G1 CVBS1_OUT PR_R_C1 CVBS2_OUT PB_B1 RESREF CVBS_Y2 CURREF SYNCIN2 Y_G2 1 2 PR_R_C2 PB_B2 3 REF 4 R 5 G VGA 6 B HSYNC_IN IF_AGC RF_AGC IN VSYNC OUT P SCL VGA_EDID TUNER N SDA AGND AV4-PR 22n 9S20 2S7U AA14 AC12 AF13 AD11 AC11 AF11 AE11 AB10 AA11 AC16 AB16 AB13 AB12 AA12 AA10 AD12 AB11 AE12 AF12 BS13

2S7H AV1-G 3S4K 3S4R 56R 22n

EU: AP:

YPBPR1 YPBPR1

22n

ANALOG_VIDEO

AV2-CVBS 9S18

IS5E IS5D IS5F IS5G IS5H IS5J

3S5S 10K

3S75 10n BS15 2S75 10K

PNX-IF-AGC

AV4-Y 9S19

2S7R 22n

EU: AP:

SCART2 YPBPR2

BS10

3S76 2S76 10n 47K

IS11 PNX-RF-AGC

+CVBS

2S77 10n

PNX-IF-P

AV4-PB 9S21

2S7E 22n

319803104790 - RST SM0402 47R PMS Col R at 9S18 for Brazil

2S78 10n

PNX-IF-N

2S84 R-VGA 3S50 3S52 3S54 56R 22n

2S85 G-VGA 56R 22n

2S86 B-VGA 56R 22n 5 7 5 7 3S5V-2 2 100R 100R

EU: VGA AP: VGA


H-SYNC-VGA

3S5T-1 100R

V-SYNC-VGA

3 3S5T-3 6 100R RES 3 3S5V-3 100R 3S5V-1 100R 6

VGA-SCL-EDID

VGA-SDA-EDID

RES

3S5V-4

3S5T-4

3S5T-2

100R

100R

2010-12-10

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Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 87

10-3 B03 393912364954


Audio
+AVCC

B03A

Audio
+24V-AUDIO-POWER 3D09 4R7

B03A
7D03-1 BC847BS(COL) 6 1 +24V-AUDIO-POWER FD14 2D06 3D16 2 ID12 10u 35V 220n

5D07

220R 5D08

22K 2D05

220R

ID11

GND-AUDIO

-AUDIO-R

FD01

2D28 1u0

ID14 4 6 7 3D02-2 2 4K7 2 7D15-1 BC847BS(COL) 1

2D24 220u 35V 2D20 2D07 47n 4K7

ID27

ID28 220u 35V

2D19

2D08

220n

220n

3D14-2 22K

3D14-3 22K

3D02-4

3D14-4 22K

3D14-1 220n

A-PLOP

FD08

GND-AUDIO

GND-AUDIO 7D10-1 TPA3123D2PWP

19 20

+AUDIO-L

1 3

3 6 3D02-3 4K7 3 5 7D15-2 BC847BS(COL) 4

3D02-1 8 1

1u0

47n 4K7 ID19 ID18 6 5 18 17

AVCC

10 12

FD03

2D29

ID15

2D23

R PVCC BSR R OUT L 16 15 22 21 ID31 2D09 220n ID32 2D10 ID10 220n 22u ID09 5D01 22u ID05 5D02 ID06 5D05 220R 5D04 220R ID08 ID07 2D12 35V 220u 2D11 35V 220u LEFT-SPEAKER RIGHT-SPEAKER

R IN L 0 GAIN 1 VCLAMP BYPASS MUTE SD

CLASS-D AUDIO AMP

BSL

GND-AUDIO 2D17 1u0 AUDIO-MUTE-UP A-STBY +3V3-STANDBY 6

2D16 1u0

ID29

ID30

11 7 4 2

ID37 FD09

PGND AGND 8 9 L 23 24 R 13 14 GND_HS 25

3D15

4K7

EMC

3D01-3

3D10-3 22K

3D10-2 22K

47K

MAINS SWITCH DETECT

CD10

7D11-1 BC847BS(COL) 1

RES 2D31 +3V3-STANDBY ID35 5 3D01-4 47K 2D03 100p 7D10-2 TPA3123D2PWP 26 27 28 29 40 39 38 GND-AUDIO LEFT-SPEAKER 5 4DETECT2 GND-AUDIO 4n7 GND-AUDIO

3 7D11-2 BC847BS(COL) 4

ID34

EMC 4n7

22K

GND-AUDIO

GND-AUDIO

VIA VIA

GND-AUDIO

GND-AUDIO

GND-AUDIO

GND-AUDIO

VIA 1735 30 31 32 33 5D03 2D01 220R GND-AUDIO 3D06-3 FD07 3 100K 6 7 3D06-2 100K 2 4 RIGHT-SPEAKER ID33 GND-AUDIO RIGHT-SPEAKER 4 3D06-4 100K 2D02 5 10u GND-AUDIO
4 2010-12-10

10n

VIA

V_NOM 2D14

1D50

VIA

37 36 35 34

2D21 220n

2D27 RES

RES 2D30

3D10-4 22K

3D10-1 220n

2D22 220n

2D26 RES

22K

1D38 1 2 3 4 1 2 3 2041145-3

FD05 FD06 10n 2D13 FD02 10n

3 7D03-2 BC847BS(COL) 5

GND-AUDIO

2041145-4

LEFT-SPEAKER

8 3D06-1 1 100K

V_NOM

1D52

SPB SSB TV550 2K11 4DDR EU

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Circuit Diagrams and PWB Layouts


DC/DC

Q552.2E LA

10.

EN 88

B03B

DC/DC

B03B
5U03 RES 30R 5U02 30R 2U23 2U25 2U24 2U19 2U20 10u 10u 10u 10u 1u0 7U02-1 SI4952DY IU10 7 8 2 1

FU05

IU22 +12V

12V/1V8 CONVERSION
FU02 7 5 6 8 5U00 3u6 2U15 2U16 47R 47u 22u

3U11

3R3

2U21 IU11 220p 3U23-4 7U02-2 SI4952DY IU09 5 6 4 3

FU03 +1V8

47R 3U23-3

3U23-2 2

47R 3U23-1 1

47R 2U17 2U18

IU23 1n0 IU15 7U01 SI4778DY 1n0

IU08

3U27 10R

IU12

5 6 7 8 4 1 2 3

2U00

3U14

10u

3U04 IU05

3R3

3R3

2U22 IU06 2U02 100n IU07 3U28 10R IU13 220p

2U01

100n

3R3

7U03 TPS53126PW 2 11 3 10 1 VBST 2 1 EN 2 1 VO 2 1 VFB 2 1 TRIP 2 VIN GND 1 2 1 2 1 2 1 2 1 2

3U05

7U04 SI4778DY IU16 IU14 5 6 78 4 1 2 3

IU24 ENABLE-1V8 1n0 RES 2U03 +1V1 +1V8

DRVL

23 14 1 12 24 13

12V/1V1 CONVERSION
FU06 STPS2L30A 5U01 2u0 3U24-4 47R 3U24-3 3U24-2 47R 3U24-1 3U20 2U12 2U13 10R RES 47R 47R 47u 22u 2U14 FU01 +1V1 RES 100u 2.0V SENSE+1V1

DRVH

4 9 5 8 IU01 21 16 20

SW

RES 7U00 BC847BW IU03 1 2 +3V3-STANDBY 3U00 10K 3U01 10K 2U06 3

GND-SIG 3U02 22K GND-SIG GND-SIG +1V1 12K 3U03

PGND

22 15 7 17 18 19 GND-SIG IU25 2U04 2U05 10u 1u0 FU04

TEST

IU02

6U00

2U11 2U09

100n GND-SIG

IU18 2U10 1n0 1u0

GND-SIG

1n0

V5FILT VREG5

IU17

3U21 IU19 100R 1% 3U17 1% 330R

FU00

RES 2U29

IU20 100p RES

3U19

2U08

3U18

5K6

3U08 +1V8 330R 1%

3U22 1K0 1%

IU04 RES 100p 1K0 1%

FU09

CU00 CU01 CU02 CU03 CU04 CU05

FU08

IU21

3U09

3U10

2U07

22K

GND-SIG

GND-SIG

GND-SIG

GND-SIG

GND-SIG

GND-SIG GND-SIG

1% 1K0

100n

2010-12-10

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3139 123 6495


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Circuit Diagrams and PWB Layouts


DC/DC

Q552.2E LA

10.

EN 89

B03C

DC/DC
+3V3 LED-2 RES 10K +5V +3V3-STANDBY RES 10K 3U75 3U74 +3V3-STANDBY

B03C
9U41 IU43

RES 10K

3U68

3U69

10K

IU44 IU45 9U42 RES 7U42 RES BC847BW IU47

3U41 10K RES

* *

optionally 1M99 is a 9 pin connector

LED2

LED2

3U59 10K RES +3V3

LED-1

7U43 BC847BW

3U70 10K

LED1

LED1

3U53 10K

1M99 1 2 3 4 5 6 7 8 9 10 11 12 13 1-2041145-3 RES 2U56 RES 2U57 1n0 2U48 1n0 GND_AL GND_AL GND_AL FU48 FU49 FU50 FU54 100R +12VIN FU56 FU57 FU74 FU68 100p RES 2U72 RES 100p RES 100p 2U52 RES 100p 100p 3U66 100R BL-SPI-SDO BL-SPI-CSn BL-SPI-CLK RES 3U67 100R RES 3U84 100R RES 3U76 MAINS-OK RES 100R 3U56 +12V_AL +3V3 10K 3U44 FU07 3D-LR 4 3U83-4 5 3U82 1K0 RES 7U48-1 BC857BS(COL) 1 ENABLE-3V3-5V IU64

3U83-1 2 1

8 2U71 +3V3-STANDBY 4 3 100n 5 7U48-2 BC857BS(COL) 3U83-2 100K 6 IU40 7 100K 2

100K IU41

2U51

2U43

3U71 100R

STANDBY

5 10K 6

2U68 1u0 2U47 BZX384-C6V2 1M95 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1-2041145-4 FU58 FU59 FU60 FU61 FU63 FU75 FU67 2U49 100p RES 10n 6U40 +3V3-STANDBY 10n 2U54 +12VIN T 3.0A 32V 3U72 2U50 +24V-AUDIO-POWER 1K0 FU66 10n 1U40 +12V

7U40-2 BC847BPN(COL) IU48 5 4

3U83-3 100K

3U62-4

3U62-3

3 IU61 7 10K 3 3U60-3 6 22K FU73 RES 10K 3U61 ENABLE-1V8

22K

IU51

IU49 6 7U40-1 BC847BPN(COL) 1

10K

3U62-2 2 2

FU72 7U41-2 BC847BS(COL) 5 4 IU52 3U63 RES 10K 8 3U60-1 22K IU57 1

2 1u0 RES IU63

3U60-2 7

DETECT2

3 5 3U80 3U60-4 4 22K 4K7

2U55

ENABLE-3V3n

FU62 FU76 2U58

+24V 1n0 RES

GND-AUDIO FU51 FU52 FU53

+3V3 3U45 100R 100R 100R

3U81 10K

IU56

3U73 +3V3-STANDBY 3K3 LAMP-ON

3U62-1 10K

IU62 IU50 8 2

6 1 7U41-1 BC847BS(COL) 1

3U42 3U43 IU55

BACKLIGHT-PWM_BL-VS BACKLIGHT-BOOST
Optional table for 4U00 and 4U01

100p

4U01 RES 4U00 RES 2U53

FU55 1K0

3U64

POWER-OK

Items 4U00

If 1M99 is not mounted yes yes

If 1M99 is mounted no no

For non-Amblight sets no no Dream Catcher Core Range

2U44 0R 100p

3U43 open 100R

1M95 13 POLE 14 POLE

3U65

GND_AL +12VIN

100K

1n0

**

1n0

10n

4U01

2U44

+12VD
4 2010-12-10

2U45

2U46

SPB SSB TV550 2K11 4DDR EU

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2011-Feb-18 back to

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Circuit Diagrams and PWB Layouts


DC/DC

Q552.2E LA

10.

EN 90

B03D

DC/DC
+3V3 7UC0 LF25ABDT 1 IN OUT COM 2UA4 3UA0 2K2 3

B03D

+12V

*
FUA0 +2V5-REF

1u0

1 7UA0 TS2431 K

2 A

FUA4 +2V5

IUB6 +5V5-TUN +5V-TUN

CUA0

+2V5-LVDS

+12V

+2V5-REF

3UB6-1 1 8 1K0 3UB7-1 8 1 470R

330R 1%

5 7UA7-2 4 BC847BS(COL)

7UA7-1 BC847BS(COL) 3U13 IUB4

2UB0

1u0

7 1K0 IUB2 3UB6-3 3 6 6 1K0 3UB6-4 5 4 1K0 IUB5 3 1

3UB6-2

7UA6 BC817-25W 3U12 IUB3

330R 1%

+1V8 +5V IU26 7UA3 PHD38N02LT 3UB0 22R FUA3 4 +1V2 2UB1 RES 1u0 2UB2 IUA5 2 1

*
3U15-1 100R 3U15-2 100R 3U15-3 100R 3U15-4 100R 7 8

+3V3 +5V

3U16-1 100R

+3V3

3U16-2 100R 3U16-3 100R 3U16-4 100R

1 2 470R 3UB7-3 3 3UB7-4470R 5 4

3UB7-2

2UB8

470R

22u

1u0

NOT FOR 5000 SERIES

ENABLE-1V8 4 3U25-4 5 100K RES 7 IUA6 3UB1 1K0 SENSE+1V2

100K RES 3 3U25-3 6

RESERVED 5UA0 30R

3U25-2 2

100K RES

1 100K RES IU29

3U29-1 470R 3U29-2 470R

RES

+12V

7UA5 LDS3985M50 +5V5-TUN 1 3 IN INH OUT BP 5 4 IUB1 2UB5 100n 2UB6 1u0 +5V-TUN

RES 7UA4 TS431AILT 5 A


NC

3U25-1 3 RES 7U06-2 BC847BS(COL) 4 8 6 5 RES 7U06-1 BC847BS(COL) 1 IU30 2

+3V3

3 3U29-3 6 RES 470R 3U29-4 470R 1 3U26-1 8 RES 470R 3U26-2 470R RES 3UB5 +5V 6 RES 100K RES

3UB2 3

4K7

2UB7

REF

3UB3 4

3UB4 1K0

IUB0

2UB3 22n

+3V3

3U26-3 470R 3U26-4 470R

2UB4 RES 330p RES

4K7

NC

1u0

COM

2010-12-10

SPB SSB TV550 2K11 4DDR EU

3139 123 6495


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Circuit Diagrams and PWB Layouts


DC/DC

Q552.2E LA

10.

EN 91

B03E
+12V

DC/DC

B03E
IUD0 +5V5-TUN 2UD0 2UD1 2UD2 10u 10u 10u 7UD0-1 ST1S10PH ENABLE-3V3-5V RES 1n0 2 5 INH SYNC A 4 1 A SW 6

5UD0 30R

VIN

SW

7 3

IUD3

5UD1 3u6

IUD7

6UD0 SS36

FUD3 +5V RES 2U27 RES 2UE9 220u 16V +1V1 100n

22u 2UD5

2UD3

2UD4

2UD6

VFB GND P HS 8 9

22u

6 7U05-1 BC847BS(COL) RES 1 2

IU27

IUD6 7UD0-2 ST1S10PH 10 11 14 13 15

2UD7 4n7 3UD2 120K

1% 3UD0

68K 3UD1

+12V

5UD3 30R 2UD8 2UD9

IUD1 7UD1-1 ST1S10PH ENABLE-3V3-5V 2 5 INH SYNC A 4

2UE0

10u

10u

10u

SW

VIN

SW

7 3

IUD4

5UD2 3u6

FUD2 +3V3 220u 16V +1V1 RES 2U28 100n 22u 2UE3 2UE1 1% 100K 4n7 3UD3 2UE2 2UE4

VFB GND P HS 8 9

22u

3 7U05-2 RES 4

BC847BS(COL) 5

RES

VIA

12

33K 1%

3U06

IUD2 7UD1-2 ST1S10PH 10 11 14 13 15

3UD4

1M0 3UD5

+5V

7UD2 LD1117DT25 6UD1 S1D 2UE5 100n IUD5 3 IN OUT COM 1 2UE6 2 22u 16V +2V5

() FOR 5000 SERIES ONLY () NOT FOR 5000 SERIES

7UD3 LD1117DT33 3 IN OUT COM 2UE7 1 2UE8 100n 2 22u 16V +3V3

RES

VIA

12

33K 1%

3U07

10K

10K

IU28

22u

2010-12-10

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Circuit Diagrams and PWB Layouts


Temperature sensor & AmbiLight

Q552.2E LA

10.

EN 92

B03F

Temperature sensor & AmbiLight

B03F

5UM1 +3V3 30R

IUM0

1UM0 T 1.0A 63V

FUM0

V-AMBI

2010-12-10

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Circuit Diagrams and PWB Layouts


Fan control

Q552.2E LA

10.

EN 93

B03G

Fan control

B03G
+12V +3V3 1 3US4-1 8 10K +12V

3US5-2

+12V 3 7US1-1 LM339P 14

10K 7

2US3 IUS6 7US2 BC807-25W IUS7 3US9 22R BC807-25W 7US3 IUS9 3US6 47R

3US2

FAN-CTRL1

1K0 IUT1

IUS3 3US5-3 3 6 10K

8 12

+12V +3V3 3US5-1 8

11 IUT2 FAN-CTRL2 10

IUS4 3US5-4 5 4 10K IUS8

12

FAN-DRV +3V3 +12V 10K +12V 7US1-3 LM339P 2 3US4-4 IUS5 3US4-3 6 10K 5

5 4

TACH01

+12V 9US0 RES +12V 3US4-2 7 10K 7US1-4 LM339P 1

7 6

12

TACH02

IUS0

TACHO

12

3US3

10K

7US1-2 LM339P 13

10K

+12V

3US7

100n

10K

2010-12-10

SPB SSB TV550 2K11 4DDR EU

3139 123 6495


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Circuit Diagrams and PWB Layouts


Vdisp switch

Q552.2E LA

10.

EN 94

B03H

Vdisp switch

B03H

1 9UU0-1 RES 2 9UU0-2 RES 3 9UU0-3 RES 4 9UU0-4 RES 1 9UU1-1 RES 2 9UU1-2 RES 3 9UU1-3 RES 4 9UU1-4 RES

8 7 6 5 8 7 6 5 FUU0

7UU0 SI4835DDY +12VD

RES 7UU1 SI3441BDV 2UU2 22n

+VDISP-INT

8 4 PUMD12 7UU2-2 3 3UU1

3UU3-1

1 3UU3-2 IUU3 7 7UU3 RES BC847BW 47K 3 1 IUU4 3UU3-3 IUU5 3UU3-4 6 3 4 5 47K RES 2UU0 RES 100n 2 47K RES

5 IUU0 6 3UU0-3 +3V3-STANDBY 47K 3 2 6 7UU2-1 PUMD12 1

47K RES 2UU1 1u0 1 IUU2

47R IUU1 3UU0-2 7 2 47K

47K RES

3UU0-1 8

+3V3

VDISP-SWITCH

FUU1 3UU2 4K7 RES

+3V3

LCD-PWR-ONn

2010-12-10

SPB SSB TV550 2K11 4DDR EU

3139 123 6495


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Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 95

10-4 B04 393912364954


Analogue externals A

B04A

Analogue externals A
AP-SCART-OUT-R 3E37-4 5 100R 4 CDS4C12GTA 12V 2E01 RES 6E01 1E00 2E87 100p 1n0 7E01-1 6 IEC1 2 1 PUMH7 IE22 AUDIO-IN1-R 4 2E06 100p 3E07-4 CDS4C12GTA 12V 1K0 5 1E31 RES 6E03 2E88 FE71 3EA7-4 IEC2 2EA5 5 1u0 16V AP-SCART-OUT-R IE68 AUDIO-OUT-R 470R 4 FEA1 RES FE70 3EA7-1 IEC0 2EA4 8 1u0 16V AP-SCART-OUT-L IE67 AUDIO-OUT-L

B04A
470R 1 FEA0

1n0

7E01-2 3 5 4 PUMH7 RES

AP-SCART-OUT-L

3E37-1 8 100R 1 CDS4C12GTA 12V RES 6E07 2E10 1E53 2E90 100p 1n0

FE72

3E24 2K2 RES

A-PLOP

IE23 AUDIO-IN1-L 1

3E07-1 1K0 8 CDS4C12GTA 12V 6E09 1E54 2E91 1n0

* EU
AV2-STATUS IE05 +5V 3E17 4K7

2E04

YPBPR1-PB

AP

9E50

9E51 3E74 18R

100p

RES

AV1-B

IE53

5E73 3E75 BEC3 CDS4C12GTA 12V 1u8 2E79 2E80 150p 150p 18R RES 6E23

(AV1)
1E12 2E15 100p 1E01 2EB1 3EA1 9E01 1K0 1 2 100n

1R0

SCART1

3EA2

IE90

3E06

RES * EU
AV1-STATUS 3E32 IE18 3E31

IE89 3E73 39K 2E99 IE51 4p7 2E81 2u2 18K 2 IE59 2E97 39p 5E80 2E98 10u CVBS-MON-OUT1 18p AV2-BLK CVBS-OUT-SC1 3E37-2 2 100R 7 3E37-3 3 6 100R 3E07-2 1K0 3E07-3 3 1K0 6 3EA7-2 2 7 2 3EB6-2 470R 3EB6-3 470R 7 2 470R 7 3EA7-3 3 470R 6 1X06 EMC HOLE 1X02 REF EMC HOLE 3 6 3E18 2

** ** 4E06 ** 4E05
4 7E06-2 5 6 3 BC847BPN(COL)

12K RES 6E22 4K7

CDS4C12GTA 12V

1E55

2E18

100p

AP
YPBPR1-SYNCIN1

9E52

9E53 3E76 18R

FE73 FE74 FE75

7E06-1 IE70 2

6 7 8 9

IE60 1 1 3EB1 2 2 820R BC847BPN(COL) 3EB3 330R

AV1-G

IE54 2E83 150p

5E74 2E84 150p 1u8

3E77 18R RES 6E26 CDS4C12GTA 12V

FE80

** 4E04
RES

1E18

2E14

100p

IE08 RES 9E08 10 11 RES 9E07 9E10 IE16 IE14 12 13 14 15

RES AP
YPBPR1-PR 9E54 9E55 3E78 AV1-R IE55 2E85 150p 5E76 3E79BEC5 2E86 150p 1u8 18R 18R

**

4E03 RES

RES 9E05 FE81 CDS4C12GTA 12V FE82 1E19 2E12 100p 9E09 IE17 RES 9E06 FE83

+5V

2E74

16 17 18 19 20 21

RES 6E28

**

4E02 RES

RES * EU
3E44 4K7 +3V3

IE96

3EB6-1 470R

IE91 8 7E05 BC847BW 5 IE92 3E45 68R 470R

FE84

2E24

100n

**

4E01 RES

3EB6-4 4

FE85 MTJ-505H-01 NI LF

100n

IE48 AV1-BLK 7E09-1 PUMH7 1 3E43 75R 6 2 CDS4C12GTA 12V 6E29

RES 3E48 68R

GND_A

RES 2E75

1E22

IE52 AV1-CVBS

3E62 27R RES 6E32 CDS4C12GTA 12V

RES

1E25

2E44

CVBS-OUT-SC1 CDS4C12GTA 12V RES 6E30 RES 2E76 1E23 100p

100p

100p

GND_A
4 2010-12-10

* 3139803190010 - RSI SM 0402 JUMP 0R05 Col at 2E44 & 2E75 for Brazil ** Provision for ESD

3E19

1u0

2EB3

IE61

SPB SSB TV550 2K11 4DDR EU

4K7

IE13

5K6

+3V3

3139 123 6495


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Circuit Diagrams and PWB Layouts


Analogue externals B

Q552.2E LA

10.

EN 96

B04B

Analogue externals B
YPBPR 1E08-3
MSP-305H-BBB-732-03 NI 2
1E43

SPDIF out
FE54
CDS4C12GTA 12V

B04B

EU
RES 6E40

9E29

IE71

3E87 18R

IE72

AV3-Y SPDIF-OUT YPBPR1-SYNCIN1

IE15

5E06 30R
2E22

FE59
CDS4C12GTA 12V

1E07 MTJ-032-68B-46-NI-FE 1 2 FE41

4E20

AP

9E04

3E88 27R

IE73

AV2-CVBS

GND_A
MTJ-032-21B-45 NI FE (PBT) 1E03 2 1

FE51
CDS4C12GTA 12V

EU
RES 6E51

9E57

IE74

3E89 18R

IE75

AV3-PB YPBPR1-PB

2E67

100p

GND_A
MTJ-032-21B-42 NI FE 2 1E04
2E68 100p

1E28

4E21

FE48
CDS4C12GTA 12V

EU
RES 6E52

9E58

IE76

3E90 18R

IE77

AV3-PR YPBPR1-PR

4E22
RES

1 FE42

GND_A

YPBPR AUDIO
+3V3 MSP-305H-BBB-732-03 NI 6 1E08-1
2E39 1E29

1E39

3E97
CDS4C12GTA 12V

AUDIO-IN3-R IE31
2E72 100p

FE50
RES 6E06 1n0

1K0

RES 1E32 AV3-Y AV1-CVBS 9E15 9E16 RES RES 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 32

4E23
RES

5 RED FE43

AV3-PR RXD1-MIPS 3E96 IE29 AUDIO-IN3-L AV3-PB TXD1-MIPS


2E71 100p

9E19 9E12

RES RES

GND_A

CDS4C12GTA 12V

1E08-2

MSP-305H-BBB-732-03 NI 4
2E40 1E42 1n0

FE49

1K0

9E17 9E14

RES RES

RES 6E38

3 RES 4E24 WHITE

GND_A

AUDIO-IN3-R AV1-B

9E11 9E18

RES RES

AUDIO-IN3-L AV1-G

9E13 9E20

RES RES

VGA ( OR DVI ) AUDIO


1E09 MSJ-035-29D PPO

CVBS-OUT-SC1 AV1-R FE02


CDS4C12GTA 12V

9E21 9E22

RES RES

V_NOM

2 3 1
2E36 1n0 1E37

3E21 1K0
2E35 100p

IE09 AUDIO-IN4-L AP-SCART-OUT-R AV1-STATUS AUDIO-IN1-R AV1-BLK AP-SCART-OUT-L AUDIO-IN1-L 9E23 9E24 9E25 9E26 9E27 9E28 RES RES RES RES RES RES

RES 6E19

RES 6E46

10p 1E44

1 GREEN

2E27

100p

31

FE01 IE10 AUDIO-IN4-R


2E38

DF50-30DP

FE03
CDS4C12GTA 12V

3E20 1K0
100p

V_NOM

1n0 1E38

RES 6E20

2E37

RES 3E54 RES 3E55 RES 1ECB 1481-702-06S-51 6 5 4 FE44


100p

100R 100R RES 3E58 +T 0R3 FE52 FE47 +5V RES 3E56 RES 3E57 100R 100R IE34 IE35 RES 3E36 100R RES 3E41

IE36 RES 3E38 100R RXD2-MIPS 3D-VS 100R TXD2-MIPS 3D-LR

FE53

9 8 7

100n

BZX384-C5V1 RES 6E17

BZX384-C5V1

100p

RES 6E15

RES 6E16

1E78

RES 2E21

RES 2E20

RES 2E26

RES 2E23

RES 2E25

RES 6E18

1E76

1E77

1E75

1E79

FE45

100p

100p

FE46

BZX384-C5V1

BZX384-C5V1

3 2 1

242202606017 - SOC CINCH V 3P 1L3 YEWHRDY at 1E08 for BRZ FOR 3D Provision for ESD
4 2010-12-10

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Circuit Diagrams and PWB Layouts


Ethernet & Service

Q552.2E LA

10.

EN 97

B04C
+3V3

Ethernet & Service


5E08 30R 10u 2E63 2E62 100n 2E66 100n RXD1-MIPS +3V3-ET-ANA +3V3 IE07 +3V3-ET-ANA TXD1-MIPS 7 3E53-2 47R 5 3E53-4 47R BZX384-C5V1 6E43 6E44 4 BZX384-C5V1 IE49 2 IE50 3 3E53-1 47R 3E53-3 47R 1E85 1E86 FE58 FE56 1 FE57 2 3 1

B04C
8 1E06 6

MSJ-035-29D PPO (PHT)

UART SERVICE CONNECTOR

IE32 3E30 1M0 1E70 NX3225GA 25M 10K 3E67 RES 2E54 10p 10p IE33 2E52

IE38

IE06

RES 1E71 1 2 3 5 4

100n 2E53

2E49

2E48

100n

4n7

10u

+3V3

TXD1-MIPS RXD1-MIPS

3E66 RES

502382-0370 7E10-1 LAN8710A-EZK 27 CR 5 4 CLKIN 1 XTAL 2 RST 0 MODE 1 RMIISEL PHYAD2 RXD<0:3> COL CRS_DV MODE2 TXEN 0 1 2 TXD 3 4 INT TXER MDC MDIO VSS 33 TX P N 1A 2A VDD 12 IO 6 1

3E33

2E55

10K

10K

provision for BUH


P RX N 31 30 29 28 20 26 13 IE63 3E64 7 IE64 3E65 3 10K 2 10K 14 32 12K1 1% 3E40 IE39 9E42 3E72 3E34 3E68 RES 3E35 RES RES 10K 10K +3V3
ETH-INTSEL ETH-RXP ETH-RXN ETH-TXP ETH-TXN ETH-TXCLK ETH-RXDV ETH-RXER

RESET-ETHERNETn ETH-RXD(0) ETH-RXD(1) ETH-RXD(2) ETH-RXD(3)

IE26

19 11 10 9 8

TXCLK RXDV RXER RXD4 0 PHYAD 1 RXCLK REGOFF 1 LED 2 INTSEL CRS RBIAS

ETH-COL

3E70 RES

3E69 RES 10K

10K 15 9E43 3E71 RES 10K

10K RES 10K

+3V3
ETH-RXCLK

ETH-TXEN ETH-TXD(0) ETH-TXD(1) ETH-TXD(2)

21 22 23 24 25 18

+3V3
ETH-REGOFF

ETH-TXD(3)
ETH-TXER

+3V3
ETH-CRS

ETH-MDC ETH-MDIO

17 16 3E51 1K5 +3V3

7E10-2 LAN8710A-EZK 34 35

VIA

36 37

+3V3-ET-ANA

+3V3-ET-ANA

CONFIGURATION RESISTOR SETTINGS


49R9 1% 49R9 1% 49R9 1% 49R9 1%

Resistor
3E26 22R 3E98 22R

POP PHYADD(0) = 1 PHYADD(1) = 1 PHYADD(2) = 1 RMII mode selected Internal 1.2V reg. disabled MODE(0) = 0 MODE(1) = 0 MODE(2) = 0 INTERRUPT FUNCTION DISABLED ON nINT/TXER/TXD4 SIGNAL

EMPTY PHYADD(0) = 0 PHYADD(1) = 0 PHYADD(2) = 0 MII mode selected Internal 1.2V reg. enabled MODE(0) = 1 MODE(1) = 1 MODE(2) = 1 INTERRUPT FUNCTION ENABLED ON nINT/TXER/TXD4 SIGNAL

3E22

3E25

3E95

3E99

3E64 ETHERNET CONNECTOR 3E65 3E66 3E67 3E68 3E69 3E70 3E71 3E72

ETH-TXP ETH-TXN

FE27 FE28

1E87 3 ACM2012 2 FE60 4 1 FE30 FE61 1E88 3 ACM2012 2 4 1 CDA5C16GTH 16V RES CDA5C16GTH 16V RES CDA5C16GTH 16V RES CDA5C16GTH 16V 6E47-1 6E47-2 6E47-4 6E47-3

1N00 1 2 3 4 5 6 7 8

ETH-RXP ETH-RXN

FE29 FE31

9 11 10 12 2E60 22n FE34

5E03

5E01

5E02

5E04

RES 27n

RES 27n

RES 27n

RES 27n

RES

5450-323-183-H3

2E05

RES 15p

2E07

2E08

2E09

RES 15p

RES 15p

RES 15p

2E56

2E57

2E58

2E59

15p

15p

15p 3E39

0 ohm

3E27

3E28

0 ohm

3E29

0 ohm

0 ohm

RES

RES

RES

RES

RES

RES

RES

RES

15p

FE32

ETH-INTSEL ETH-REGOFF

FE33
4 2010-12-10

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Circuit Diagrams and PWB Layouts


HDMI

Q552.2E LA

10.

EN 98

B04D
1P04 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 FEC6 21 23

HDMI
5EC0 RES 2EC1 2EC0 FEC0 2ECV 100n 10u 1u0 FEC3 2EC2 MICOM-VCC33

B04D
220u 16V 3ECH ARX2+ ARX2ARX1+ ARX1ARX0+ ARX0ARXC+ ARXCPCEC-HDMI 47K AIN-5V +3V3-HDMI RES 2ECW 2EC6 100n 2EC8 100n 2EC7 2EC3 100n 100n 10u 30R 10K +3V3 30R

HDMI CONNECTOR 3

I2C Address SII9187B = 0xB2


RES 5EC3 +3V3

FECB

FEC7

3EC1-3

VCC33 1 ARX-HOTPLUG AIN-5V


ARX-DDC-SDA ARX-DDC-SCL

MICOM_VCC33

SBVCC33

FEC1 FEC2 FEC4 AIN-5V

ARX-DDC-SCL ARX-DDC-SDA

ARX-DDC-SCL ARX-DDC-SDA 3EC1-1 3ECM-4 10R 1 3ECN-1 1u0 8 100K 2ECM IE42

7EC1 SII9187B

37

9 27 64

38

47K

10K 3ECP-3

3ECP-1

FEC5 20 22

ARX-HOTPLUG

31 32 29 30 65 66 67 68 69 70 71 72 35 36 33 34 1 2 3 4 5 6 7 8 41 42 39 40 11 12 13 14 15 16 17 18 45 46 43 44 19 20 21 22 23 24 25 26

+5V-EDID 8 6 3 10K

(CBUS) HPD0 R0PWR5V DSDA0 DSCL0 N R0XC P N R0X0 P N R0X1 P N R0X2 P (CBUS) HPD1 R1PWR5V DSDA1 DSCL1 N R1XC P N R1X0 P N R1X1 P N R1X2 P (CBUS) HPD2 R2PWR5V DSDA2 DSCL2 N R2XC P N R2X0 P N R2X1 P N R2X2 P (CBUS) HPD3 R3PWR5V DSDA3 DSCL3 N R3XC P N R3X0 P N R3X1 P N R3X2 P

R4PWR5V DSCL4 DSDA4 CEC_D

1P03 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 FECG 21 23

HDMI CONNECTOR 2
BRX2+ BRX2BRX1+ BRX1BRX0+ BRX0BRXC+

AIN-5V

ARXCARXC+ ARX0ARX0+ ARX1ARX1+

48 47 51 9EC2 RES CEC-HDMI

49

VGA-SCL-EDID-HDMI VGA-SDA-EDID-HDMI

BIN-5V BRX-HOTPLUG BIN-5V BRX-DDC-SDA BRX-DDC-SCL 3 3ECM-3 10R 6 2 3ECN-2 1u0

ARX2ARX2+ 7 100K 2ECN IE43

TX2

N P N P N P N P

57 56 59 58 61 60 63 62 3ECJ RES

HDMIA-RX2HDMIA-RX2+ HDMIA-RX1HDMIA-RX1+ HDMIA-RX0HDMIA-RX0+ HDMIA-RXCHDMIA-RXC+ RES 3ECK 4K7 9EC3 RES PCEC-HDMI 3ECL RES 4K7 MICOM-VCC33

3ECA-2

47K

BRXCPCEC-HDMI FECC FECD FECE FECF 20 22 BIN-5V BRX-DDC-SCL BRX-DDC-SDA BRX-DDC-SCL BRX-DDC-SDA

TX1

BRXCBRXC+ 8 3ECA-1 BRX0BRX0+ BRX1BRX1+ BRX2BRX2+ CRX-HOTPLUG CIN-5V 2 3ECM-2 10R 7 3 3ECN-3 1u0 6 100K 2ECP IE44

TX0

TXC

47K

BRX-HOTPLUG

TPWR_CI2CA

55 IE12 FECR

4K7

CEC_A

50

BIN-5V

HDMI CONNECTOR 1
1P02 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 23 CRX2+ CRX2CRX1+ CRX1CRX0+ CRX0CRXC+ CRXCPCEC-HDMI ARC-eHDMI+ CRX-DDC-SCL CRX-DDC-SDA 47K CIN-5V CRX-DDC-SDA CRX-DDC-SCL

INT

52

FECY

+3V3

CRXCCRXC+ CRX0CRX0+ CRX1CRX1+ CRX2CRX2+ DRX-HOTPLUG 6 DIN-5V DRX-DDC-SDA DRX-DDC-SCL eHDMI+ 5EC2 30R CIN-5V ARC-eHDMI+ 2ECC 1 3ECM-1 10R 8 4 3ECN-4 1u0 5 100K 2ECQ IE45

CSCL CSDA

54 53

3EC3 3EC5

100R 100R

SCL-SSB SDA-SSB

RES 2ECX

FECJ FECA FECK FECL FECM FECN 20 22 RES 7E02 BC847BW CIN-5V

CRX-DDC-SCL CRX-DDC-SDA 3ECA-3

3ECA-4

FECP

47K

CRX-HOTPLUG 3E23 22K RES +3V3-STANDBY

DRXCDRXC+ DRX0DRX0+ 10p DRX1DRX1+ DRX2DRX2+

VIA

PCEC-HDMI

3ECD 100R IEC4

7EC0 BC847BW IEC5

IEC6 9EC0 CEC-HDMI

74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89

10p

RSVDL

10p RES 2ECY

10 28

7EC1 NON-INSTAPORT 9187A 9187B 9287B

3ECN 4 3K3 4 100K 4 100K

3ECF 3K3 100K 100K

EPAD 73 IEC7 22K FECW +3V3-STANDBY

NON-INSTAPORT INSTAPORT

3ECE

6EC1 +5V BAT54 IE11 4R7 IE65 2 3ECU-2 10K 2ECU 1u0 DDCA-SCL IE66 4 3ECU-4 5 10K 7 +3V3 +5V-VGA

3ECG 3ECF 100K

DDCA-SDA

FECZ

2010-12-10

+5V-EDID

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Circuit Diagrams and PWB Layouts


Headphone

Q552.2E LA

10.

EN 99

B04E

Headphone

B04E
+3V3-STANDBY

4 PUMD12 7EE0-2 A-PLOP 3

6 FEE0 RESET-AUDIO 2 7EE0-1 PUMD12 1

A-STBY

2EE0 47p 3EE1-1 22K 4 3EE1-4 22K 2EE5 47p +3V3 5

8 3EE1-2 7 3EE1-3 3 22K 6 22K

2EE1

7EE1 TPA6111A2DGN

100n

IEE0 ADAC(3) IEE2 ADAC(4)

2EE3 1u0

IEE1 2EE4 1u0

3EE0-1 10K

IEE3 1 5 3EE0-4 10K 4 IEE4 2EE2 1u0 IEE6 2 6 5 3 1 2

AMPLIFIER
INVO

3 2EE6 4V 100u 7 10 11 2EE7 4V 100u 1 IEE8 2 IEE7

VDD 1 1 4

3EE2-3 33R 3EE2-4 33R 3EE2-2 33R 3EE2-1 33R

6 FE36 5 AMP1

FE35 7 AMP2

SHUTDOWN BYPASS 4

VIA GND GND_HS 9

A-PLOP

3 3EE0-3 6 10K RES 3EE3

IEE5

22K

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Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 100

10-5 B05 393912364954


DDR

B05A

DDR

+1V8

DDR2-VREF-DDR

+1V8

DDR2-VREF-DDR

B05A

2B40

47u 2B00

100n 2B02

100n 2B05

100n 2B06

100n 2B01

100n 2B03

100n 2B04

100n 2B07

100n

2B36 100p 2B08 100n

2B41

47u 2B09

100n 2B10

100n 2B13

100n 2B15

100n 2B11

100n 2B12

100n 2B14

100n 2B16

A9 C1 C3 C7 C9 VDDQ

A1 E9 L1 H9

AT T-POINT
3B22 240R DDR2-CLK_N 3B27 240R DDR2-CLK_N 3B28 240R DDR2-CLK_P DDR2-CLK_N DDR2-CLK_P DDR2-CLK_P

DDR2-A0 DDR2-A1 DDR2-A2 DDR2-A3 DDR2-A4 DDR2-A5 DDR2-A6 DDR2-A7 DDR2-A8 DDR2-A9 DDR2-A10 DDR2-A11 DDR2-A12 DDR2-A13 DDR2-BA0 DDR2-BA1
DDR2-BA2

H8 H3 H7 J2 J8 J3 J7 K2 K8 K3 H2 K7 L2 L8 G2 G3 G1 3B01 RES 240R F9 E8 F8 F2 G8 F7 G7 F3 B3

VDD 0 1 2 3 4 5 6 A 7 8 9 10 11 12 13 0 1 BA 2 ODT CK CKE CS RAS CAS WE DM|RDQS VSS A3 E3 J1 K9

VDDL

VDDQ

VREF 3B00-2 DDR2-A0 DDR2-A1 DDR2-A2 DDR2-A3 DDR2-A4 DDR2-A5 DDR2-A6 DDR2-A7 DDR2-A8 DDR2-A9 DDR2-A10 DDR2-A11 DDR2-A12 DDR2-A13 DDR2-BA0 DDR2-BA1
DDR2-BA2

SDRAM
DQ

0 1 2 3 4 5 6 7

C8 3 C2 D7 1 D3 D1 D9 3B00-4 4 B1 B9 3B00-1 1

2 6 3B02-3 33R 3 8 3B02-1 33R 3B02-2 2 5 3B02-4 4 33R 8 33R

7 33R 6 3B00-3 33R 7 33R 5 33R

DDR2-D16 DDR2-D17 DDR2-D18 DDR2-D19 DDR2-D20 DDR2-D21 DDR2-D22 DDR2-D23

DQS

B7 A8 2B44 RES

3B13 2p2 33R

3B12 33R

DDR2-DQS2_P DDR2-DQS2_N

H8 H3 H7 J2 J8 J3 J7 K2 K8 K3 H2 K7 L2 L8 G2 G3 G1 3B03 RES 240R F9 E8 F8 F2 G8 F7 G7 F3 B3

VDD 0 1 2 3 4 5 6 A 7 8 9 10 11 12 13 0 1 BA 2 ODT CK CKE CS RAS CAS WE DM|RDQS VSS A3 E3 J1 K9

VDDL

E1

VREF 3B04-2 2 7 33R 6 6 33R 33R 33R 2 7 3B05-2 1 8 3B05-1 33R 5 5 3B05-4 33R 4 8 33R 33R 3B14 33R 33R

SDRAM
DQ

E2

7B02 EDE1108AGBG-1J-F

A1 E9 L1 H9

A9 C1 C3 C7 C9

E1

E2

7B03 EDE1108AGBG-1J-F

100n

2B17 100n 2B37 100p

0 1 2 3 4 5 6 7

C8 C2 3B05-3 D7 3B04-3 D3 D1 D9 3B04-4 B1 B9 3B04-1

3 3

4 1

DDR2-D24 DDR2-D25 DDR2-D26 DDR2-D27 DDR2-D28 DDR2-D29 DDR2-D30 DDR2-D31

DQS

B7 A8 2B45

NU|RDQS

A2

3B15 RES 2p2

DDR2-DQS3_P DDR2-DQS3_N

DDR2-ODT DDR2-CLK_P DDR2-CLK_N DDR2-CKE DDR2-CS DDR2-RAS DDR2-CAS DDR2-WE DDR2-DQM2

NU|RDQS

A2

DDR2-ODT DDR2-CLK_P DDR2-CLK_N DDR2-CKE DDR2-CS DDR2-RAS DDR2-CAS DDR2-WE DDR2-DQM3

NC

L3 L7

DDR2-A14

NC

L3 L7

DDR2-A14

3B23 33R

VSSDL E7

VSSQ A7 B2 B8 D2 D8

3B24 33R

VSSDL E7

VSSQ A7 B2 B8 D2 D8 DDR2-VREF-DDR

+1V8

+1V8

DDR2-VREF-DDR

47u 2B18

100n 2B20

100n 2B21

100n 2B23

100n 2B19

100n 2B24

2B42

100n 2B22

100n 2B25

100n

2B26 100n 2B38 100p

100n 2B28

100n 2B30

100n 2B32

100n 2B31

2B43

47u 2B27

100n 2B29

100n 2B33

100n 2B34

A1 E9 L1 H9

A9 C1 C3 C7 C9 VDDQ

E1

DDR2-A0 DDR2-A1 DDR2-A2 DDR2-A3 DDR2-A4 DDR2-A5 DDR2-A6 DDR2-A7 DDR2-A8 DDR2-A9 DDR2-A10 DDR2-A11 DDR2-A12 DDR2-A13 +1V8 DDR2-BA0 DDR2-BA1
DDR2-BA2

H8 H3 H7 J2 J8 J3 J7 K2 K8 K3 H2 K7 L2 L8 G2 G3 G1 3B06 RES 240R F9 E8 F8 F2 G8 F7 G7 F3 B3

VDD 0 1 2 3 4 5 6 A 7 8 9 10 11 12 13 0 1 BA 2 ODT CK CKE CS RAS CAS WE DM|RDQS VSS A3 E3 J1 K9

VDDL

VDDQ

VREF 3B07-2 DDR2-A0 DDR2-A1 DDR2-A2 DDR2-A3 DDR2-A4 DDR2-A5 DDR2-A6 DDR2-A7 DDR2-A8 DDR2-A9 DDR2-A10 DDR2-A11 DDR2-A12 DDR2-A13 DDR2-BA0 DDR2-BA1
DDR2-BA2

SDRAM
DQ

0 1 2 3 4 5 6 7

C8 C23B08-4 4 D7 D3 3B08-2 2 D1 D9 3B07-4 4 B1 B9 3B07-1 1

2 5 33R 7 33R 5 33R 8 33R 3 1 3

7 33R 6 3B07-3 33R 8 3B08-1 33R 6 3B08-3 33R

DDR2-D0 DDR2-D1 DDR2-D3 DDR2-D2 DDR2-D4 DDR2-D5 DDR2-D6 DDR2-D7

DQS

B7 A8 2B46

3B17 RES 2p2

3B16 33R 33R

DDR2-DQS0_P DDR2-DQS0_N

H8 H3 H7 J2 J8 J3 J7 K2 K8 K3 H2 K7 L2 L8 G2 G3 G1 3B09 RES 240R F9 E8 F8 F2 G8 F7 G7 F3 B3

VDD 0 1 2 3 4 5 6 A 7 8 9 10 11 12 13 0 1 BA 2 ODT CK CKE CS RAS CAS WE DM|RDQS VSS A3 E3 J1 K9

VDDL

VREF 2 3B10-2 7 33R 7 3B11-2 8 33R 33R 5 3B11-4 33R

SDRAM
DQ

E2

7B00 EDE1108AGBG-1J-F

A1 E9 L1 H9

A9 C1 C3 C7 C9

E1

E2

7B01 EDE1108AGBG-1J-F

100n

2B35 100n 2B39 100p

0 1 2 3 4 5 6 7

C8 C2 3B11-3 3 D7 3B10-3 33R 3 D3 D1 D93B10-4 4 B1 B9 3B10-1 1

6 6 33R

2 1 5 3B11-1 33R 4 8 33R

DDR2-D8 DDR2-D14 DDR2-D10 DDR2-D11 DDR2-D12 DDR2-D13 DDR2-D9 DDR2-D15

DQS

B7 A8 2B47

NU|RDQS

A2

3B19 RES 2p2

3B18 33R 33R

DDR2-DQS1_P DDR2-DQS1_N

DDR2-ODT 180R 1% DDR2-CLK_P DDR2-CLK_N DDR2-CKE DDR2-CS DDR2-RAS DDR2-CAS DDR2-WE DDR2-DQM0

NU|RDQS

A2

DDR2-ODT DDR2-CLK_P DDR2-CLK_N DDR2-CKE DDR2-CS DDR2-RAS DDR2-CAS DDR2-WE DDR2-DQM1

3B20

FB00 DDR2-VREF-DDR 180R 1%

NC

L3 L7

DDR2-A14

NC

L3 L7

DDR2-A14

3B25 33R

3B21

VSSDL E7

VSSQ A7 B2 B8 D2 D8

3B26 33R

VSSDL E7

VSSQ A7 B2 B8 D2 D8

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Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 101

10-6 B06 393912364954


Display interfacing-Vdisp

B06A

Display interfacing-Vdisp

B06A

1G03 T 3.0A 32V

5G01 +VDISP-INT 30R RES 5G02 30R RES 2G44 22u RES

1G00 2G43 100n T 3.0A 32V RES

FG0H

+VDISP

RES 3G28 2K2

IG11

RES 6G00 LTST-C190KGKT

For Development use only

2010-12-10

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Circuit Diagrams and PWB Layouts


Video out - LVDS

Q552.2E LA

10.

EN 102

B06B

Video out - LVDS

B06B
+3V3

10K

RES

10K

10K

+VDISP

47p

47p

47p

47p

47p

47p

47p

47p

47p

RES 3G33

RES 3G34

RES 3G35

9G0K-4 9G0K-3 9G0K-2 9G0K-1

47p

FI-RE51S-HF 60 61 58 59 56 57 54 55 52 53

5 6 7 8

2G77

2G7A

2G76

2G78

2G75

2G79

2G24

2G25

2G26

2G92 2G93 2G94 2G95

100n 100n 100n 100n FG2J FG30 FG31 FG32 FG33

FI-RE41S-HF 51 50 49 48 46 47 44 45 42 43 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1G50

SDA-DISP SCL-DISP

CTRL-DISP

RES 3G32 3G2W 3G2Y RES 3G38 RES 3G37 RES 3G2Z RES 3G36 RES 3G30 RES 3G31

100R 100R 100R 100R 100R 100R 100R 100R 100R

FG34 FG2H FG2G FG35 FG2R FG2K FG2L FG2M FG2E FG2F FG1Y FG1Z FG20 FG21 FG22 FG23 FG24 FG25 FG26 FG27 2G28 2G29 FG28 FG29 FG2A FG2B FG2C FG2D FG1R FG1S FG1T FG1U FG1W FG1V FG2P 2G91 100n 47p 47p

2G27

4 3 2 1

CTRL-DISP

BACKLIGHT-BOOST 3D-LR 3D-VS-DISP CTRL-DISP CTRL-DISP


PX1APX1A+ PX1BPX1B+ PX1CPX1C+ PX1CLKPX1CLK+ PX1DPX1D+ PX1EPX1E+

FG04

2G96 2G99 2G97 2G98


PX3APX3A+ PX3BPX3B+ PX3CPX3C+ PX3CLKPX3CLK+ PX3DPX3D+ PX3EPX3E+

47p 47p 47p 47p FG1C FG1D FG1E FG1F FG1G FG1H FG11 FG1J FG1K FG1L FG1M FG1N

PX4APX4A+ PX4BPX4B+ PX4CPX4C+ PX4CLKPX4CLK+ PX4DPX4D+ PX4EPX4E+

FG12 FG13 FG14 FG15 FG16 FG17 FG18 FG19 FG1A FG1B FG1Q FG1P

PX2APX2A+ PX2BPX2B+ PX2CPX2C+ PX2CLKPX2CLK+ PX2DPX2D+ PX2EPX2E+

RES 9G0G

FG2N

+VDISP

EMC 100n RES 2G9C

EMC 100n RES 2G9E

EMC 100n RES 2G9D

EMC RES 2G9F

100n

51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

TO DISPLAY

1G51

TO DISPLAY

1X05 REF EMC HOLE

2010-12-10

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div. table

Circuit Diagrams and PWB Layouts


AmbiLight CPLD

Q552.2E LA

10.

EN 103

B06C

AmbiLight CPLD

B06C

5GA0 +3V3 30R 2GA0 2GA1 100n 2GA2 100n 1u0

FGA0 VINT

DEBUG ONLY

5GA1 +3V3 30R 2GA3 2GA5 100n 1u0

FGA1 VIO +3V3

RES 1G37 3GA4 10K RES +3V3 1 2 3 4 5 6 SD51022

2GA6

GCK3 GTS1 GTS2 GSR


10p RES

3GA5-4 3GA5-3 3GA5-2 3GA5-1

4 3 2 1

5 6 100R 7 100R 8 100R 100R

VINT

VIO

7GA0 XC9572XL-10VQG44C0100 PXCLK54 GCK2 GCK3 43 44 1 2 3 39 40 41 42 36 34 33 29 30 31 32 37 38 11 9 24 10

15 35

VCCINT IXO1_43|GCK1 IXO1_44|GCK2 IXO1_1|GCK3 IXO1_2 IXO1_3 IXO1_39 IXO1_40 IXO1_41 IXO1_42 IXO2_36|GTS1 IXO2_34|GTS2 IXO2_33|GSR IXO2_29 IXO2_30 IXO2_31 IXO2_32 IXO2_37 IXO2_38 TCK TDI TDO TMS GND 4 17 25

VCCIO

26

AMBI-SPI-CLK-OUT-R AMBI-SPI-SDI-OUT_G1-R AMBI-SPI-SDO-OUT-R

IGA1 CPLED2 IGA2 CPLED3

PNX-SPI-CS-BLn PNX-SPI-SDO PNX-SPI-SDI PNX-SPI-CLK

3GA3

33R

GTS1 GTS2 GSR AMBI-SPI-CS-OUTn_R2-R AMBI-PWM-CLK_B2 AMBI-SPI-CS-OUTn_R2 AMBI-LATCH1_G2 AMBI-TEMP CPLED3 CPLED2 10p 2G11 RES 10p 2G12 RES 2G10 RES

IXO3_5 IXO3_6 IXO3_7 IXO3_8 IXO3_12 IXO3_13 IXO3_14 IXO3_16 IXO3_18 IXO4_19 IXO4_20 IXO4_21 IXO4_22 IXO4_23 IXO4_27 IXO4_28

5 6 7 8 12 13 14 16 18 19 20 21 22 23 27 28

9GA1 RES

3GA1

RES 47R 5 3 33R 7 3G10-3 33R 3G13 10R 1 6 3G10-1 33R

PNX-SPI-CSBn BACKLIGHT-PWM 3D-LR 3D-VS-DISP BL-SPI-SDO BL-SPI-SDI BL-SPI-CSn BACKLIGHT-PWM_BL-VS BL-SPI-CLK AMBI-PROG_B1 AMBI-BLANK_R1 AMBI-SPI-CS-EXTLAMPSn AMBI-SPI-CLK-OUT AMBI-SPI-SDI-OUT_G1 AMBI-SPI-SDO-OUT AMBI-LATCH2_DIS 10p 2G14 RES 10p 2G19 RES 10p 2G18 RES 10p 2G15 RES 10p 2G16 RES 2G13 RES 10p 2G17 RES

IGA3 GCK2 +3V3 3 GCK3 5 7GA1-2 BC847BS(COL) 4

8 3G11-1

3G14 1 7 33R 3G11-2

33R 2 33R

4 3G10-4 2 3G10-2 3G12 3 3G11-3

+3V3 6 GTS1 2 7GA1-1 BC847BS(COL) 1

6 33R 33R 8 33R

+3V3 3 10p GTS2 5 7GA2-2 BC847BS(COL) 4

10K

3G15 +3V3

10p

+3V3 7 8 6 5 330R 4 3GA6-4 LTST-C190KGKT 3GA6-3 6GA3 LTST-C190KGKT 6GA2 330R 3 6 GSR 2

7GA2-1 BC847BS(COL) 1 330R 2 3GA6-2 3GA6-1 6GA1 330R 1 LTST-C190KGKT

DEBUG ONLY
RES 1G35 1 2 3 4 5 6 7 8 2GA4 3GA2-1 3GA2-2 3GA2-3 3GA2-4 1 2 3 4 8 7 6 5 100R 100R 100R 100R RES 1G36 1 2 3 4 5 6 FGA6 FGA5 FGA3 FGA2 +3V3 FGA4

100n RES

SD51022

BACKLIGHT-PWM

9GA0

BACKLIGHT-PWM_BL-VS

LTST-C190KGKT

6GA0

2010-12-10

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Circuit Diagrams and PWB Layouts


SPI buffer

Q552.2E LA

10.

EN 104

B06D

SPI buffer

B06D

+3V3 +3V3

2GE0

100n

3GE2

7GE1 PDTC114EU

10K

3EN1 3EN2 G3 PNX-SPI-CLK 18 17 16 15 14 13 12 11 10 1 2

7GE0 74LVC245A 1 19 2 3 4 5 6 7 8 9 IGE0 3 3GE0-3 47R 3GE1-3 6 3 47R RES 3GE3 47R 47R 6 1 5 RES 3GE0-1 8 47R 4 3GE1-4 47R RES

20

PNX-SPI-CSBn

BL-SPI-CLK BL-SPI-SDO AMBI-SPI-CLK-OUT-R AMBI-SPI-SDO-OUT-R PNX-SPI-SDI

PNX-SPI-SDO AMBI-SPI-SDI-OUT_G1-R BL-SPI-SDI

3GE4

PNX-SPI-CLK

9GE0-2

BL-SPI-CLK

PNX-SPI-SDO

9GE0-3

BL-SPI-SDO

BL-SPI-SDI

9GE1 9GE2

PNX-SPI-SDI

PNX-SPI-CS-BLn

IGE1

5 9GE0-4

BL-SPI-CSn

Buffer Direct

2010-12-10

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Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 105

10-7 B07 393912364954


DVBS-FE

B07A

DVBS-FE
7R01-1 7R01-2 STV0903BAC +1V-DVBS 2R01 2R00 2R03 2R02 2R10 100n 100n 100n 15 17 22 25 28 31 33 36 39 42 45 48 51 53 57 61 66 69 72 77 81 85 88 93 99 102 105 110 112 21 38 54 76 80 92 96 106 2 3 2R17 100n 5 9 13 114 118 123 127 STV0903BAC

B07A
MAIN I2C-ADDRESS : D0

POWER_VIA

XTAL 1 4 6 10 14 113 117 121 125 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165
NC

122 124 59 104 103 100 11 12

XTALI XTALO DIRCLK CLKI CLKI2 CLKOUT27 N I1 P

VS AGCRF1 0 1 2 3 D 4 5 6 7 CLKOUT STROUT DPN ERROR

52 16 63 64 65 67 68 70 71 73 74 75 78 79 82 83 84 86 87 89 90 91 94 95 108 109 111 115 116 119 120 40 41 101 50 49 47 46 44 43 37 35 34 32 30 55 3R02 1K0 2R53 47n FR00

SENSE+1V0-DVBS AGC

10n

10n

GNDA

NC NC

QM QP

* To be drawn near PNX85500


3R03 3R04 3R05 3R06
NC

GND_HS

+1V-DVBS 2R04 2R06 2R11 2R12 2R05 2R13 100n 100n 100n

10n

10n

10n

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

2R20 RES

VDD1V0

IM IP

8 7

N Q1 P

47R 47R 47R 47R

TS-DVBS-DATA 4 TS-DVBS-CLOCK TS-DVBS-SOP 2 TS-DVBS-VALID 1

9R03-4 * 5 9R04 * 9R03-2 * 7 9R03-1 * 8

TS-FE-DATA TS-FE-CLOCK TS-FE-SOP TS-FE-VALID

60 56 DISECQ-DET F22-DISECQ-TX RES 2R21 1n0 128 20 126 NC 107 NC IR04 47p 97 98 3R00 IR03 19 18

0 CS 1 DISEQCIN1 DISEQCOUT1 FSKRX_IN FSKRX_OUT NC SCL SDA SCLT 1 SDAT

+1V-DVBS 2R14 2R08 2R07 2R09 2R15 100n 100n 100n

10n

10n

RES 2R22 SCL-SSB SDA-SSB SCLT SDAT 100R RES 2R23 3R01 100R 47p

5R00 +3V3-DVBS 30R

IR00 +3V3-DEMOD 2R16 +3V3-DEMOD 2R49 2R50 2R48 2R51 2R46 2R47 2R52 100n 100n 100n 100n VIA

10n

10n

22u

10n

VDD3V3

RESET-DVBS 9R00 RES 3R13 10K

IR02 FR02 FR03 FR04 FR05 FR06 3R10 1K0

62 58 26 23 24 29 27

RESETB STDBY TCK TDI TDO TMS TRST

0 COMP 1 1 2 3 4 5 6 GPIO 7 8 9 10 11 12 13

IR05

3R07 120K DISECQ-RX

NC NC NC NC NC NC NC NC NC NC NC NC

+1V-DVBS

VDDA1V0

3R11 +3V3-DVBS 10K

VDDA2V5

FR07

+2V5-DVBS 2R18 2R19 2R24 2R25 2R26 100n 100n 100n 100n 100n

+3V3RF 3R12 4R7 2R31 1n0 2R33 1n0 2R32 1n0 2R35 1n0 2R34 2R61 1n0 10u IR06

2R37 +3V3RF +3V3RF 10p 3R14 RES 3R15 RES

1R10 NX3225GA 3 4

7R02 STV6110AT 30

11

14

22

27 VCO

28 SYN XTAL_OUT IP IN QP QN RF_OUT 32 18 19 21 20 10p 10p 10p 10p 7 34 35 36 37 38 39 40 41 42


NC

LNA LT XTAL_IN

MIX DIG BB VSS

3R09 1K0

2R40 100p 3 3R08-3 2 3R08-2 4 6 3R08-4 100R 1 7 3R08-1 100R 5 100R 8 100R

XTAL QP QM IP IM

16M

NC

10K

10K

2R38 10p IR07 IR08

31 1 12 13 2

1 2 XTAL_CMD SCL SDA AGC AS NC

SCLT SDAT AGC

SATELLITE TUNER I2C-ADDRESS : C6

2R39

2R41

2R54

2R55

NC

23 24

VIA

1R01 5R01 +3V3-DVBS 220u 6.3V 10u 2R27 2R28 IR01 +3V3RF 1 2R43 27p GND RF LNA LT MIX DIG BB VCO 5 3 9 10 15 17 25 26 SYN HS 29 33 10n 4 RF_IN

5R02

2R62

LNB-RF1

SM15T

6R00

2R29

2R45

100p

1n0

0p56

FR01

27n

2R56

9R02 RES

10p

16

6p8

2010-12-10

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Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 106

10-8 B08 393912364954


DVBS supply

B08A

DVBS supply
5T00 +5V-DVBS 30R 2T00 2T01 2T02 22u 22u 22u IT00 7T00-1 ST1S10PH 2 RES 1n0 5 INH SYNC A 4

B08A
1 A 6 SW SW VFB 7 3 IT01 5T01 2u0 2T04 22u 2T05 22u IT18 FT06 +1V-DVBS +2V5-DVBS 2T03 VIN

GND P HS 8 9

3T00 RES 1K0 1% 2T10 RES 4n7 2T36 4n7 3T21 1K0 1%

7T00-2 ST1S10PH 10 3T03 +3V3-DVBS 2T06 100n 47K IT20

IT02 13 15 1% RES 3T01 12 22K 3T02

VIA
11 14

IT24

SENSE+1V0-DVBS

LD3985M25 7T01 6T01 RES +5V-DVBS BAS316 BAS316 BAS316 2T07 100n 30R 5T02 6T00 RES 6T02 RES IT03 1 3 IN INH OUT BP 5 4 IT19 2T08 2T39 1u0 1u0 FT07 +2V5-DVBS

COM 2T09 2 10n

7T02 LD1117DT33 3 IN OUT COM 2T11 100n 2T12 1 2 16V FT08 +3V3-DVBS

+24V IT04 2T13 100u 35V 2T15 100u 35V 47n 2T14

3T04 3R3

FT00 +5V-DVBS 220u 16V 2T19

5T03 33u

IT05

2T18

SS24

6T03

3T05

22R

22u

7T03 TPS54283PWP IT25 2 3 5 7 9 10 11

2T16

220n 2T17

220n

22u

IT06

PVDD1 BOOT1 SW1 EN1 FB1 ILIM2 SEQ BP

PVDD2 BOOT2 SW2 EN2 FB2 13 12 6 8 16 17 18 19 20 21 22 23 24 25 26

14

2T20 IT26 47n

IT10

3T10 3R3

IT09 IT32 SS24 3T11 6T04 22R

3K3

5T04 +V-LNB RES 2T22 RES 2T37 RES 2T38 100u 25V 33u 2T23 2T24 10u 10u 4u7 4u7

2T21 +24V 2T25

IT07 1n0

1n0

IT11 2T26 2T27 3T29 1K0 1n0 IT12 1n0

100K

RES 3T31

3T06

VIA2

10K

IT08 6 3T07 +3V3 10K 10K IT21

IT27 GND 2T35 10u 4 GND_HS 15

7T04-1 BC847BS(COL) 1

3T08

IT17

IT13

3T23 33K

IT29 RES 2T28 22n 3T12 RES 2T29 47K 5% RES 4u7

2T41 1n0 FT04 +V-LNB

3 6T05 +24V BZX384-C 13V IT22 3T14 2K2 3T17 IT23 5 7T04-2 BC847BS(COL) 4

RES 3T13 3K3

3T15

3T16

IT14 2T30 RES

1K0

22n

RES 3T24 2T40 220p 15K


SENSE+1V0-DVBS

2T31 RES +5V-DVBS 22n 3T20 2T32 RES 2T33 RES 18K 5% 22u

IT15 RES 3T09

3K3 5%

47K

3T25 330K 3T28 100K RES IT16 RES 2T34 22n 3T26 2T43 100n RES RES 10K

V0-CTRL

RES

3K3

2T42 RES 10n

IT30

3T18

3K3 5%

3T19

33K

22u

2010-12-10

FT05

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Circuit Diagrams and PWB Layouts


DVBS supply

Q552.2E LA

10.

EN 107

B08B

DVBS supply

B08B
+12V IT50 +12V +3V3-DVBS

100u 35V

100R

RES

RES IT28

3T22

220R

2T51

2T50

3T50

5T50

100n

22u

V0-CTRL 2T52 220n

IT60 5T52 7T50-1 LNBH23Q 19 18 IT51 BAT54 COL IT53 ISEL LX VORX VOTX DSQOUT 28 4 21 IT54 29 12 13 14 30 5T51 30R 2T56 2T57 470n RES IT57 27 IT58 100u 35V 15 2T58 470n DETIN DSQIN EXTM TTX VCTRL VUP BYP GND_HS NC 22 11 1 2 3 7 8 16 17 23 24 25 26 31 32 3T57 RES 6T51 +3V3-DVBS 10K STPS2L30A IT66 3T62 1R0 IT67 2T60 10u 3T58 RES 2K2 IT55 DISECQ-DET 3T59 RES 2T62 RES 3T52 2T53 6T50 220n 22K 220u 3T53 15R IT52 LNB-RF1

SCL-SSB

100R SDA-SSB 3T60 RES +12V LNB-RF1 DISECQ-DET 3T61 100R

9 6 10

SCL SDA ADDR

10K 3T55 RES 2T54 RES IT61 IT62 10K 3T56 10n 10K 9T50 RES IT63 9T51

VCC_L

VCC

3T51

2K2

STPS2L30A

F22-DISECQ-TX RES RS1D 6T53 IT65

RS1D

6T55

100u 35V

2T55

2T59

470n

IT64 6T54 RES BAS316 RES 1n0 RES IT68 RES 7T51 BC817-25W IT69 22R

A_GND

20

P_GND

33

2T61

7T50-2 LNBH23Q 34 35 36

41 42

3T27

150R

+V-LNB

3T54 RES

IT56

6T52

IT59 9T52 RES DISECQ-RX

VIA VIA VIA

39 40

VIA 37 38

10n

2010-12-10

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Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 108

10-9 B09 393912364954


Connectors comp

B09A

Connectors comp
5C55 30R 1M59 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
3C74 100K RES

+3V3

B09A

AMBI-SPI-CLK-OUT AMBI-SPI-SDO-OUT AMBI-SPI-SDI-OUT_G1 AMBI-PWM-CLK_B2 AMBI-SPI-CS-OUTn_R2 AMBI-LATCH1_G2 AMBI-BLANK_R1 AMBI-PROG_B1 AMBI-LATCH2_DIS AMBI-TEMP FC71

FC70

FC72 FC73 V-AMBI FC74 FC75 V-AMBI FC76 FC78 3C70 100R FC79 FC81
2C70 100n

2C76 FC87 LIGHT-SENSOR 2C93 RC 47n RES IC73 LED-2 IC74 3C75 100R 3C76 100R 3C77 100R +3V3-STANDBY 2C79 LED-1 IC75 3C78 100R 100p 2C80 100p KEYBOARD FC95 3C79
BZX384-C5V6 BZX384-C5V6 RES

100p 2C77 100p


6C02

FC77

2C78 100p

RES BZX384-C5V6

TO LED PANEL
FC88 FC89 FC90 FC91 FC92 FC93 FC94 +5V
2C81 100n

1M19 1 2 3 4 5 6 7 8

GND_AL
NC

FC83 +24V

1C86 T 2.0A 63V

FC82 AMBI-POWER

2C94

2C95

100n RES

100n

+12V_AL T 2.0A 63V RES

100p 2C82

2C96 100n RES GND_AL GND_AL

FH34SJ-26S-0.5SH(50)

6C03 RES

FC84

1C87

10R

6C05

1M21 RES +3V3 FC61

RES 3C90
10K

FAN-CTRL1

RES 3C91
100R RES 3C80 100R RES 3C81 RES 3C82 100R 100R RES 3C83 RES 1M71 FC97 1 2 3 4 SCL-SET SDA-SET TXD2-MIPS RXD2-MIPS 9C00 RES 9C01 RES 9C02 RES 9C03 RES 3C94 3C95 3C96 3C97 RES RES RES RES 47R 47R 47R 47R
10p 2C87 RES 2C86 RES 10p 2C89 RES 10p 2C88 RES

TACH01

FC62

+3V3-STANDBY +5V

SCL-BL TACH02

FC85 FC63

FC96 FC98

RES 2C83

100p RES 2C84

100p

SDA-BL

FC86

2041145-4

2C90

1u0 2C91

FAN-CTRL2

FC64

+3V3 FAN-DRV

RES 3C93
10K +3V3

100R

10p

1u0

RES 3C92

100R

TEMPERATURE SENSOR

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 FH52-18S-0.5SH

FC99
RES 2C85

30R
T 1.0A 63V RES 1C85

HOTEL TV
+12V

RES 5C53 30R

1u0

RES 5C54

Dreamcatcher

IC78

RESERVED
4 2010-12-10

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Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 109

10-10 313912364954 SSB Layout


Overview top side

CXXX

2T14

2U58

2U53

3U43

2U44

4U01

2U45

2D30

2U49

3U76

2U48

3U71

2U68

2U47

2G13

2C70

3C70

2U54

2U46 3U45

5C55 2C96

2C94
3G14 3G12

4U00

3U64

3U65

3U42 3U81

3G10

3G11

3G13

2C95

6T03

5UM1

2T17 5T04
7T03

7T02

7T00
2T01
2T11 5T00

IUD0

2UE8

5UD1

2UE7

2U24

2U25

2U23

2U19

3UD1

IU57

IUS3 IUS4

3UD0

2U20

5U03

5U02

7UD3
3US5 IUT2 IUS6
3US2 3US3

2UD0
2UD3 3U06 2U27 2UD7 3UD2 2U28 3U07

7U05

7UD0
2UD1 2UD2
5UD0

5T03 2T18
2T33 2T19 2T32

2T22

2T12

2T00

3U23

1M71

3US7

5U00

3C80 3C81 3C91 3C83 2C83 2C84 3C93 3C92 3C82 2U09 3C90

IU23 IU18
2U11

IUS5 3U29

IUT1

7US2

IU17

2US3

3U24

7US3

6U00
2U16

2U17

2UD8
3UD5 3UD4 2UE1 3UD3

2UE6

IU15
2U18

2UD9
3U26
5UD3

2C85

1C85
5C54 5C53

2UE3

2UE2

5U01
9UU1 9UU0

2U15

3US9 3US6

IUS9

6GA3

6GA1

6GA0

7UU0

2UE9

3GA6

1G00

1X08
2G43

1G37
7GA2
3GA5

6GA2

2UE4

2UD6 6UD0

IUD2

5UD2

7U01 7U04 7U02

7US1

2UE0

IUD1

7UD1

3US4

9US0

IUD4

2UD4 2UD5

5G02 5G01

2UU2

7GA1

1P00

1X07

2G44 1G03
3G28

1G36
3G15

3GA2

6G00

IG11

1G35
2GA4 9GA0 3GA1

1G50

2F01

7B01
2G98 2G97 2G99 2G96

3B26
2B47

3B11

7GA0
IGA3 IGA2 IGA1

3B18 3B19

5R01
3R15 3R14 2R28 9R02 2R46 2R33 2R32

2D19

3R03 2R20 3R04 3R05 3R06

2D05

3B07

2T57

2R61

2R34

3R12

2R35

2R38

9S00

2R37

2D20

3S31

3S3R

2B44

2S4D

3S1L

3B12 3B13

3S3T 3S3N

3S2A

3S1B

3T22

1X05
1735 1D38
1D50 2D17

9F27
3S1C

3B00

5D07

3S3L
3S4B 3S6K 3S4A

9F28

7B02
2D07

7S00

3S02 3S01

9S01
3S28 3S29 3S23 3S24 3S03

7S02

2S09 3S04

3S3Y

2R40

1R10

3R09

2R39

7B00

5D08

2B46

3B25 3B16 3B17

7R01

2R54

2R41

2R62

7R02

1R01
2R31 2R43

3B08

2R56

2R55

3R08

5R02

2R45

7F20

9S90

9S91

9S92

9S93

2R29

2R27

3B10

2S4P

3B02

3S62 3S21
3S3S 3S1K

2S4E

3B23

3S1J

2T50
5T52
IF62 5T51

6T55
7T50
2T56

2T55 6T52

1X04

3B05

3S3Q

3B24

1D52

2S2W

2S2Z

2S33

2S30

IS13

3S27

2D09

2S2R
2S2T

3E17

3S3W

3S42

7D10
2D10 2D06

3S3H

3S3U

9S06

3B04

3S3G
3S2M

3S00

3S44

7B03

2S4F 3S3F BS15 DS50 2S4G 2B45

3B15 3B14

3S81 3S80 3S52 3S54 3S50 3S43


3S3M

1S02

3S6H

5T50

DBS8

6T51 6T53

IS14

2D08

2D24

2D23

2S32

7S08

2S31

3S26

2S34
4S14

3S6J

2S7K

2S7H

2S7R

2S7E

2S7M

BS10

3S4J 2S7J

3S4L

3S4K

9S21

2S2S

9S19

2S77 2S78 3S84 3S83

2F40
2F58 3F59 3F60 IF61

2S8G

2S7U

2S7N

2S7P

2S7L

3S4R

3S4P

3S4T

9S18

9S20

3S53

3S13 3S12
BS13

2S41

3S59

2S87

1P09

2S2V

2S2Y

2D12 2D11

5D02 5D01

2S4M
9E20 9E18

1F10

1F24 1F75
6F72 3F78
2F92 2F94 2F90 3F71 3F36 3F31 2F33 3F37 2F29

3E31

2E84 3E77 3E76


4E03

6E22
4E05 2E18

4E01

9E22

7F70
2F91 3F72

7F25
1F25
2F35 3F28 2F34 2F32

4E04 2E14

4E02

9E21

6E26

9E05

1E71

5D04

9E24 3E32

2E83

5E74

7F58

3F58

1E00

1E53

1E12

1G51

1E86

1E85
2F9D

5D05
2G29 2G28

1E55

9F00 9F01

9F05 9F06

1E01
1E18 1E22 1E25 2E27
4E22 4E23

1E06 1X06
6E19
9C02 9C03

1E31

1E54

5F73

9F04
2F9C

2E48

3E67

3E69

9E42

2E49

9E43

3E71

3E64

3E70

3E66

3E65

2F93

IF86

1E19

1E23

5F70

1P08

IF89

2G7A 2G79 2G24 2G25 2G26 3G38

5F72

6E06

3E96

3E51

IE09

9F71

9E11

2E72

2E53 2E52

6E40

9E04

2FDD

3E97 6E38

1E70

9E13

3E30

2G78 2G27 2G76 2G75

2F86 3F75

2E35

2E54 1E29 1E42 1E43

3E21 1E37

2E38

IE10
2E37 3E20

2F9A

2G77

IE07

6C02
2C77 3C76 2C93

2E57 2E56 2E07 5E02 3E28

7EE0

2E62

1E28

1E39

5E01
2E05 3E27

IE11

1E38

1M21 1M19

1E88

1E87

2C80 2C78

3C78 3C77

6E51

3ECF

6C03
2C82 3C79

6E47

5E08

2E60

3E98

3E26

9E15

6EC1 6E15

2ECU IC74
3EC3 2E67 3EC5

3ECP
3E36

2F98

1T01
IE35

3ECG

6FD2

IC75

6FD3

3C75

3C74

3E40

2E66

3E25 3E22

1E08
4E21 4E24 4E20 3EE3

1E09
IE34

6E20

2C76

3E34 3E68 3E35 3E72 2E63

2F99

1E03 1E04
9E17 3E89 9E50
9E57

6E17

6C05
2C91 2C90 2C86 3C94

2EE6

6E18 6E16
3E41

3ECN IE42

IE36

2EE4

2EE3

IEE4 IEE5

IEE6 2EE2

1329
2F60 2F97 2F81

1F52
3F623F63

3E38

1FD2

7E10

2E71

2E40

2E36

2FDC

3E33

2E55

3F64

3F65

2E39

1E32

3E87 3E88 9E52 9E29

2F88

1F51

2F9B

3FDG

1328

2C87 3C97 2C89

3C95 3C96 2C88

2EE0

3EE1

2EE5

2C81

2E23

2E21

3E55

1E44
9EC3 5EC2 2ECC

2E26

2E20

3E54

2E25

3E56

3FC7

9FC3

9FC6 2FC3 2FC5

1X02

1E07

1FC1

1N00

1E78

9FC5

3FC6

3FC5

2FC1

1E79

2FC7 3FC2 9FC4

1E75

2FC6

3FC1

2FC4

2FC2

3FC3

6E46

3EE2

2EE1

IEE3

3E57

3E58

2E22

5E06

3FC4

2EE7

7EE1

2EC1 7EC1

2ECP

2ECN 2ECM

3ECM

6FC7 6FC5 6FC3 6FC4 6FC2 6FC1 6FC6 6FC8


2FC8

3EE0

1P05 1X01
4 2011-01-27

1E77

1FC6 1E76

1FC3 1FC4 1FC2

1P04

1P03

1P02

1ECB

1FC5

1E05
LAYOUT SSB TV550 2K11 4DDR EU
3139 123 6495

1FD3

5T01

1UM0

1M95
3U84 2U72 2U51 2U52 3U67

1M99
3U44 3U66 2U50 2U43 3U56 2U56

1C87 1C86

1M59

19100_800_110127.eps 110217

2011-Feb-18 back to

div. table

Circuit Diagrams and PWB Layouts


Overview bottom side

Q552.2E LA

10.

EN 110

FC81

3T11

6T04

2T02

IT11

IT00

2T26

IT19

FC83

FC84 FC77

FC75 2G14 2G12

FC74 2G18 2G11 2G10 2G17 FC71 FUM0 2G16

3T31

7T01

IT01

2T09

IT20

FT00 2G19

6T05

2T15

2T16

2T27

2T39 2T08

3T01

3T03
FT08

3T14 3T17

IT22

FC76 FC78 FC82 FC72 FC79 2G15 FC70

2T04

2T05

IT02

3T02

3T00 3T21
FT06

FT07

5T02

IT18

2T10 2T36

6T01

6T00

6T02

2T07

IT26 IT27 FT05

IT25

FC61 FC64 FU58 IUS0

2U57

2T35
IT32

FU57

1U40

IT24

3T04

IT03

3T05

2T43
IT30

IT09

3T10

IT10

2T20

IT08 IT04

IT17

3T08

3T06

7T04

IT21

IUM0

2T03

IT12

IT23

3T07

2T06

FC73

2T13

FU48 IT05

FU49

FU50

FU54

FU56

FU74 IU51

FU59 3U72

FU60

FU61

FU66

FU67

FU51

FU52

FU53

FU55

FU62

FU76

FT04

3T25 3T28 3T26 2T42

2T41

FU63

FU75

IU56

IU55

FU68

6U40 7U40

2U06

7U00

IT29

3T13 2T34 3T09 3T15 3T19 3T16 3T18

3T23

2T40 3T29
IT07 IT13

FU01 IU22

3U00 FU09 3U01 CU00 2U03 3U10 3U08 3U22 2U07 IU04 3U09 2U08 3U18 IU08 2U02 IU06 3U19 IU20 3U17 FU08

2T23 2T24

2T25

2T21

2T29

2T30

3T12 2T28 3T24

2T31
IT15

IT06 FC85

IUD3

IU03 IU49 IU48

IT14

3T20

2U55 IU27 3U73 IU63 FU73 IU28 IU62 IUD7 FU72 IU11 3U11 3U28

3U62

IU05

2U01

IU24

FC86

IT16

IUD6

3U04

2U21 IU16

3U27 IU13 3U14

IU07

7U41

3U80

FC62

3U60
IU61

IU10 FU04

2F04

FC63 3U63 IUS8 IU52 2UB3 IUB0 3U82 3UB4 3U61 IU09 IU50 FU02

7UA4

IFD4

3FD4

3FD3

FS2W

7U03
2U05 IU25

IU12

2F05

2U22

IFD2

FU07

FU05

7F04

7F03

FU06 FC96 IU14 FU00 3U02 FC98 3U20 IU01 CU01 IU19 2U10 2U29 FC97 3U21

6FD1

IFD1

IF56

3UB3

2UB4

3F68 3F69 2F53

7FD1

3UB2

FS2Y

7F54

FUA0

9CH0

9FD1

3FD6

3FD1

IUA5 IUS7

3UB0 IUA6 3UB1 IU41

IU21 CU04 CU03

3UA0

CU05

IF57

3F53

9FD5

3FD7

7F53
3F67
IF55 FF58

2UA4

3F54 3F66

2U71

3FD2

9FD2

IFD3

3UB7
IU29

2U13 2U12

IC78

3U25
IF04 9U42 3U75 3U69 3U68 IU45 3U70 IU30

2UB8
IUB4

3UB6

7F05

2F06

3U53

7F00

FUD3 3U59

7U43

IUB3 3U13 3U12

IU26

3F11

2F00

7UA7

3U74

3F08

7U06

IUB5

7UC0
FUA4

FU03

2U14
2UU0

IUB2

IU47 IU43

7UA6
2UB7

3U15

9U41

IU44 5UA0

2UB2

3U41

FUD2

IF08

3U16

7UA5
CUA0 IUB1 2UB5 2UB6

IUB6

IF03 IF01

FUA3

2UB1

IF02

7UA3

7U42

7UD2

IUU2

3F02

6UD1

3F03

IUU5 2UB0

3F09

3F10

3F01

3UU3
IUU4 IUU3

7UU1
3UU0

7F01

3UU2

2F02

7UU3
2UU1 3UU1

FUU0

2UE5

IUD5

IUU1

IF06

FGA2

IF05

IF07

7F02

FGA3

7UU2

FUU1

IUU0

3F04

3F05

2G9E

FC99

IFD5

2FD1

7U48

IU40

CU02

7UA0

IU64 3UB5

3U83

3U03

2U00

IU02

2U04

3U05

FG2J

FGA4

FGA6

2F03

2GA2

3GE1

3GE0
FGA5 FG1P FG1Q

3GA4

2GA6

7GE0

2GA5

2GA3

FG0H

FG1B FGA1

FG1A

9GE0
9GA1 9GE2 IGE1

5GA1

FG19 FG17

FG18 FG16

2GE0

5GA0

2B39

2B43
2B32
2B27 2B33 9S95 9S94

FG15

FG14

FG13 FB00

FG12

2GA0

2B35

2B34
FG1K 2G9F

FG1N

FGA0

FG1M

IS17

7GE1
3F07 3F21 3F24
IS15

9GE1 3GE3 3GA3

3GE2 3GE4

2GA1

FG1L

FG11

FG1J

2B29

IGE0 3S68 3S66

FG1H 2B28

FG1G

FS31

2D31

2B30

3B09 2B31

FG1E

FG1F

7S01

9S10

IR05

FG33

3R07

2R48 9R00 IF21 IF23

3F23 2F20 3F22

FG1C

9S11 3S65 3S67 9S12


IS09

2S12

IS08

FG1D

2R10

2F21
FF31 2R04 2R05 2R06 2R11 3R13

9G0K

2R47

9S13

9S97

9S96

IR02

3R11

2G92 2G93 2G94 2G95 2G9C FG32

3F12
IF22

2R03

2R53 3R02 2R00 IR01 2R18 2R19

FR04 FR03

2R49 2R13 2R50

IS00 IF87

3S06

6R00
FR00 IR07 IR08 IR06

FR06 3R10 FR07

FR05 2R02

2B42 3B27
2B22
2B23 2B25 2B38

3F20

3F19

9C01 9C00

3S6B 3S6C

2S89 3S58
3S5W

FG30

FG31

FR02 2R01

2R12

9S08
2S4N

2B24

FS01 2B26

3S07

2S17

3S61
3S6G 3S1V 3S15

2S25

2B21

2R24

2R07 IF88 3S6E 3S5Z

3S60
3S6F 3S6D 3S5Y

2B19

3B06

2R08 2R51 2R52 5S88 IS3K

2R17

2S6P

2R23

IR00

3S2G 3S6A 3S6W 3S6V

2S5H

3S2F

3S1W

2S64

3R00 2R26 2R15 2R25 2R22 IR03 3R01

2S4W 2S4Y

2S5P

2S5J

3S1X

2S6F

5S85
IS58

IS3Q

2R21

2R14

2R09

IR04

3S1E 5S92

5S80 2S5A 2S27

5S89

5S93

2S5G
5S87

3S6P

3B22 3S30 3S33 2B10


2B16 2B14 3S0V IS42

3D01

5S83

2S60

3F06

2S21

3S6Q

3S69

2S57

5S94

2S4S

3S57 3S56

IS25

2S5M

2S62

2S63

2R16

5R00

IS40

IS26

2S26

2B18

2S67

3B20

2S66 2S61

2B20

3B21

2D03

ID35

7D11
ID34

5S81

2S23

2S5D

2S6M

3S1R

3S1U

2T59

3S1S

3S1T

5S82

3T56 9T50 9T51

2S58

2S5C

6T54 9T52
2T61

IS3S

2S6L

2S28

IT59

3S82
IS04

2S59

2S5K 5S95
5S90

2S6E 2S6D

3D15 ID12

2S6H

2S6K

2S43
5S04

3D09

2S53

2S55

2S56

2S2E

2S4V

IT64

2S11

3T54

IT60

3S45

FR01

IT50

2S6C IS05

2S4T

2S51

2S6G

2B11

3T61 3T59 2T62


IT55 IT56 IT52

2B12

IT65

2T51

3T50

IS01

2S6B

2S37

3T51

3S64

9R04

FS02

ID11

2S6N

IT68

2SHW

3S22

2B13
ID14

2D02 3B01 2B09


FD01

3D06
ID33

3S0W

7T51 2T53 6T50


3T27
IT69

2S50

9S09
3S40 IS16 DS52

2S6A

3T57

2T52

FS64

2S5B

2S52

2S20

2S24

IT28

3S20

IT63

IS10

2S68

3D16

IT66 IT58

2B15

2B37 2B17

7D03
3D02
ID15 ID30 CD10

9R03

2S65

FD07

2S4U 2S15 2S4Z IS3L

IT62

IT53

FC95

2S4R

2S46
2S45

2D28
FD08

IT57

3T58 2T54

2T58

3T60 3T52

3S1F

2S13

5S84

3S2V

9S0E

2T38 2T37

3S2H

2S3G

IF51 FF04

IS5E 3S5S

2S29

9S0D

3T55

2T60

2S4K

3S1P

7S20

3S55

2S4Q

3S41

3S2K

IS4Z

IS5F

2B40
IS50 2B03

2D29
FD03

7D15

IT61

IS2U

2S10
FS45 FS51

IS3B

3S09

3T62
IT67

IT54

FS0Z

3S76
3S75 FS11 2S14 FS10 3S1G 3S1H IS5D

2S3H

2S76 2S75

IS1A

IS4W

2S36
C001 IS19

3S5V

2S3L

3B28
2B02 2B08 2B36

2B01
ID37

ID18

2S2L

2S18

3T53

IT51

2S19

IS1L

3S46
3S2S

IS2Z IS5J

2S40

3S08

7S09
2S3K 2S3Q 3S6M 3S11

IS1B

ID19 FD09 ID27

2S85 2S86 2S84 3S5T

IS3D

IS5H

2S3F

3S2L

2D16

3S10

2S3E

2B04

ID29

IS1N

ID28

IS1M 2S16 IS4V

FS08 2B07 IS1S 2B05

3S19
IS1E

IS1G

2B06

IS5G IS3F

2S3D

2S3C

2S3B

2S3A

IS2V IS3E

2S3M

3S25

IS20

IS1K

3F44

3F42

IS06

3S72

FF43

FF50

3S5B

3S18
FS44

FS49

9S24
3S05

IS5C

2S8A

2S39

2S38

3B03

2B00

2S2J

FF44

2S22

FS50 IE05 IS44

2S2K

IS03 IS07 3S51

3S6L

3S37

3S34

FF47

IE67

3S32

2B41
FD05 ID09 ID32 2D01 2D14 ID31 FD14

FF49

IF47

3S47

FF45

3F40
3F43 3F41

IE54

3S16 3S17
IS1J

IS0V FF48

7S05
2S2G 2S2H IS02 3S39

2S3J

3F45

IS12

5D03
ID10 2D13

FD06

2S42

IS1Q IF16

C000

FF46

5F76
2F62 2F70
3S3P 3S49 3S1D

3S5E IS1H IS0R IS1P

3S36 3S38

3S0Z

FF38

FF39

9F30 9F29

FF30

FF41

2F65 3F82
AF72 FF56 IF53

FF42

5F74

IS11

2F95

FS53 FS57 FS52

IS1D

FF55

FF32

IF45

7F52

FF29

2F73 2F80 2F72 2F82 2F77 2F76 AF73


IF58

FD02

FS03

3F32

5F71
3F79

3F52
IF54

IF50

2D27

IF80

FF33

2E10

IF79

2EA5 2F49
IE90 3E06 3EA1 9E01 IF59 3E18 FF57 2E74 IE18 IE53

2EA4

IEC0

2D21

IE15

2E79
FE75 2E90

IE68

3E24

3D10
ID07

2F52

IF35 IF52 IF72 IF37

2F96
9E12

2EB1 IE89 3EA2

IE13

IE91

3F34
9E14 FE57 IF36 IF90 IF75 IF40 FF75 IF81

7E06

6E07

6E30

3EB3

2F27 2F26

IF43

IE96

IE92 3E45

6E28

2E76

2E86

9E55

3E78

FE43

2E12

3E79

9E53

9E51

IE60

2E87

3EB1

9E27

9E06 9E09

6E23
FE74

9E23

2EB3

2E81 5E80
IE59

FE83

2E85

IE61

IE55

BEC5

7E05
IE17

5E73
FE80

IEC2

3EA7 2E01
FEA0

7E01
FEA1 IEC1

ID05

3EB6 3E48

5E76
FE81

IF42

2F31

2E97
IE70

2E99 2E98 3E19

IE08

FE72

FE70

2E80 3E75 9E08

BEC3

3E74 2E15

3E37

6E01
2G91 9G0G FG1V FG1W FG2N

FF71

2F78 2F74

FE85

IF39

IF77

IF73

2F71

FF01

FE56

FF37

7F75

2F85 2F30 9F25 9F26


FF36 IF31 IF30 IF32

FG2P

FG1U

FG1T

2D26

IF10

3F35

9F03 9F02
IF12

IF76

IE49

IE50

2D22

3E53

FG2C

FG1S

FG1R

IF11 AF71 IF13

3D14
ID08

FG2D FG2A FG2B

6E44

6E43

2F75
IF74

IF78

ID06

5F66

2F66

IF34 IF33

2F28

2F63 2F64

IF14

3F80 3F81
IF28 3FE5

2F79 3F77
IF27 IF82 FE58

FG27

FG28

FG29

IF44

2F25 3F30
IF41 AF70

IF15 2FH8

FG26

FG25

FG24

2FE5

3FE7

3FG4
IF29

3FG2

3FE6

2FF3

FG23 FG2M 3G31 IE14 IE16 FE71 3G33 3G34 IE26 IE22 FE50 IE64 IE38 FE49 IE29 IE31 IE63 3G30 3G36 3G2Z FG2K FG2R 3G37 FG2G FG35 FG2L FG2E FG1Y FG21

FG22

5FG2

5FG0

1FE0

2FF6
5FE4 FF00

IF66 2FG2

9E07

9E10

9E16

6E32

6E29

3E62

3E43

IE52

6E09

4E06
2E91 FE73

2E88

FE84

FE82

IF63 FF64 IF48

2FG3

2FF5 2FF0
3FG7

2E44

7E09
3E44

2E75

FG1Z

6E03

IE72 IE71 FE54

IE48

9E26
2E24 3E73 IE51 IE73

5FE0 FF66 FF65 FF82 5FE3 IF65 2FG9 2FH6 5FE7 2FH7

2FE0
2FH5

2FE6

BFE3

7FE0
DFE9 IF18 DFF2 IF49 2FF7 2FF2 2FE3 2FG0 3FE8 3FE9 DFF1 FF62

3FG6

9E28 3E07 2E06 IE23 2E04 9E25

FG2F

IE06

DFE8

3G2Y 3G2W

2FE4

IE32

DFE7 IE33 DFE6 FE31

FG04 IE39

3G32 3G35

FG34

FG2H

BFE2 2FG8

FG20

IF64

2G9D FC89 FE33 FE29 FE42 FE34 FC87 FE32

FFDC

2FG7

2FG6 2FG4 IF17

2F84 3F76

2FE8
FF03

FFDA

2FF8
IF68

2FF4

FF81

5FE5

IF67

3E95
2E08

3E99
2E09

7FE3

3E29 2FA4
FE27 FE28

2E58 2E59

3E39

2FH2

2FH4

FC88

FF61

5FA4

2FF1

5FE8

IF69

2FG1

2FF9

5E03 5E04

IC73 IEE7 IEE8 FE30 IEE0 FE59 FC91 2C79 FE61 FC92 IE77 FE60 FE51 IE75 IE74 FC90

FFDB

FF63

5FE9

2FH3

5FA3

2FA3

FFAF

FE02

2E68 FECZ FE48 2ECY 2ECX

FFB5

2F59

2F61

FECB FF76 FFA2 FE03

IE44 IE45

6E52

2ECW

2FA2

2EC2

FE46

2EC7

3ECJ

FE45 FE52 FE01 FE44

FEC7 5EC3

2EC3 FECY 3ECL FECR 3ECK

IE76

FFB6

FF74

3FBF

FFC9

FFB1

7FA3

2ECQ
3ECH IE43

9E58

FE47

3E90 9E19 9E54

FC93

FEE0 FC94

FE53

FEC3

IE12 9EC2 FE41

IEE1

IEE2

2ECV

FFB2

2EC6

FFC5 9FC2 FFB4 9FC1

FFC7 2EC8 FFC2

2EC0

FFB3

FFC3

FFC4

5EC0 IE66 FEC0 IE65 FE36 IEC7 IEC6 IEC5 3ECE

3ECU

FFC1 FFC6 FFC8 FECW FECA

9EC0

7EC0 7E02 3E23


3ECD IEC4 FECE FEC4

FECJ FE35 FEC2

FEC5 FEC1

FECM

3ECA
FECF FECD FEC6

3EC1

FECK FECP FECN FECL FECC FECG

2011-01-27

LAYOUT SSB TV550 2K11 4DDR EU

3139 123 6495


19100_801_110127.eps 110127

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Circuit Diagrams and PWB Layouts

Q552.2E LA

10.

EN 111

10-11 E 27221719026x IR/LED/Key Board


Leading Edge Module

E
BZ1 B A BUZZER

Leading Edge Module


+3.3V L1 100uH C6 104 R11 100R Q1 R9 1K 2SC8050 VDDHI JP1 10 9 BUZZER ANALOG_VOUT ZD1 5.6V C2 105 R1 1K C3 105 PWM SCL 11 12 13 14 C1 VDD R2 10K VPP C4 104 U1 1 2 3 4 5 6 7 8

E
PIC16LF1933

+3.3V 2 1

MCU
RB7/ICSPDAT RB6/ICSPCLK RB5/AN13/CPS5/T1G RB4/AN11/CPS4 RB3/AN9/CPS3/CCP2(1) RB2/AN8/CPS2 RB1/AN10/CPS1 RB0/AN12/CPS0/INT VDD 28 ICSPDAT 27 ICSPCLK 26 25 24 23 22 21 VDD 20 C5 104

JP2 R3

Proxim ity

4.7uF/16V

BUZZER

VPP/M CLR/RE3 SEG12/Vcap(2)/SS(1)/SRNQ(1)/C2OUT(1)/C12IN0-/AN0/RA0 SEG7/C12IN1-/AN1/RA1 COM2/DACOUT/VREF-/C2IN+/AN2/RA2 SEG15/COM3/VREF+/C1IN+/AN3/RA3 SEG4/CCP5/SRQ/T0CKI/CPS6/C1OUT/RA4 SEG5/VCAP(2)/SS(1)/SRNQ(1)/CPS7/C2OUT(1)/AN4/RA5 VSS SEG1/VCAP(2)/CLKOUT/OSC2/RA6 SEG2/CLKIN/OSC1/RA7 P2B(1)/T1CKI/T1OSO/RC0 P2A(1)/CCP2(1)/T1OSI/RC1 SEG3/P1A/CCP1/RC2 SEG6/SCL/SCK/RC3

100R R4 100R R5 100R R6 100R R7 100R R8 100R

CPS5

CH+ CHHOM E AL VOL+ VOL-

1 1 CPS4 CPS3 CPS2 CPS1 CPS0 1 1 1 1

VSS RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA

19 18 17 16 15

SDA

CONNECTOR
J1 8 7 6 5 4 3 2 1 2.0- 8pin +5V ANALOG_VOUT LED1 LED2 IR LIGHT +3.3V

J2 1 2 3 4 5 6 7 8 9 10 11 12 13 HEADER13

SDA SCL +5V +3.3V IR

IR
+3.3V TVS1 RES ZD4 5.6V

R17 10 R18 100R C10 4.7uF/6.3V

IR ANALOG_VOUT LED2 LED1 LIGHT

3 2 4 1

U2 OUT VDD GND GND TSOP75236

Proximity Sensor
1 2 Proxim 3 ity 1 OUT CX 6 5 4 C7 1u R27 2K VDDHI VSSVDDHI VREG IQS127D

CAP TOUCHSENCE
CX ANTENNA C8 1u C9 104 LIGHT ZD5 3.3V

+5V R10 4.7k / 100

+3.3V R15 47

WHITE LED
WHITE

+5V

D2 RED 1 3

D1

G1

5 6

U3B

8 7 R22 470 LM358 3 2 LM358 C12 R21 100k C11 104 C13 104
Leading Edge Module
2722 171 9026
19100_815_110217.eps 110217

RED LED

LIGHT Sensor

+5V

TEMT6200FX01

U3A 1 R26 100R 4

18k

15k

LED1

R12 10k

2 R13 10k

B E

Q2 BC847

LED2

R14 10k

Q3 BC857 2

1 Q3* BC847 2 B

B ZD3 5.6V E E

R19 47k

R20 22k

R23

R24 R25 100k

104

R16 10k

8 9

2010-07-15 2010-07-15

VSS

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Styling Sheets

Q552.2E LA

11.

EN 112

11. Styling Sheets


11-1 Blockbuster 32"

BLOCKBUSTER 32"

1150

5213 5216

0011

1005

5216 0260

Pos No.

Description Front Cabinet Back Cover Hard Switch bracket Stand Display panel Power Supply Unit Remote Control Keyboard + IR assy Board SSB Loudspeaker box Tweeter Mainscord 1.8m Main (power) switch Cable LVDS FFC Cable LVDS FFC

Remarks

0029 8308

1004 1108 0004

0004 0011 0029 0260 1004 1005 1085 1108 1150 5213 5216 8191 8308 8G50 8G51

Not displayed

Not displayed Not displayed Not displayed


19100_806_110210.eps 110214

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Styling Sheets

Q552.2E LA

11.

EN 113

11-2 Blockbuster 37"

BLOCKBUSTER 37"

1150

5213

0011 1005 5216

5216

0260

Pos No. 0004 0011 0029 0260 1004 1005 1085 1108 1150 5213 5216 8191 8308 8G50 8G51

Description Front Cabinet Back Cover Hard Switch bracket Stand Display panel Power Supply Unit Remote Control Keyboard + IR assy Board SSB Loudspeaker box Tweeter Mainscord 1.8m Main (power) switch Cable LVDS FFC Cable LVDS FFC

Remarks

0029 8308 1004

Not displayed

0004 1108

Not displayed Not displayed Not displayed


19100_810_110214.eps 110217

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div. table

Styling Sheets

Q552.2E LA

11.

EN 114

11-3 Blockbuster 40"& 46"

BLOCKBUSTER 40"- 46"

1150

1005 5216

0011

5213

0260 5216
POS. NO. DESCRIPTION. Front Cabinet Back Cover Hard Switch bracket Stand Display panel Power Supply Unit Remote Control Keyboard + IR assy Board SSB Loudspeaker box Tweeter Mainscord 1.8m Main (power) switch with cable Cable LVDS FFC Cable LVDS FFC REMARKS

0029 1004 8308

1108

0004

0004 0011 0040 0260 1004 1005 1085 1108 1150 5213 5216 8191 8308 8G50 8G51

Not Displayed

Not Displayed Not Displayed Not Displayed

19100_802_110202.eps 110209

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