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1. What is VHDL?

VHDL FAQ'S

Ans : VHDL stands for VHSIC Hardware description language. Where VHSIC stands for Very High Speed Integrated Circuit.

2. List out all IEEE standard libraries available in VHDL?

Ans : a) std_logic_1164.

b)

numeric_std.

c)

numeric_bit .

d)

std_logic_arith .

e)

std_logic_unsigned .

3.

What is Gate-level simulation?

Ans : Simulating sinthesized netlist is called Gate-level simulation.

4. Why we go for Gate-level simulation?

Ans : The main advantage is that the testbench can be re-used with synthesized circuit that means we can apply similar test patterns to gate level model to verify that it has response similar to original model.

5. Which is the tool responsible for mapping the netlists to physical devices?

Ans : Implementation tool.

6. How the “timing verification” will be done?

Ans : This can be done by creating timing model by implementation tool. Where the timing model consist of gate-level primitives augmented with detailed delay information and can be used to verify the timing behavior.

7. List out all strengths of signals in std_logic_1164

Ans : ’U’ --Uninitialized ’X’ --Forcing Unknown ’0’ --Forcing 0 ’1’ --Forcing 1 ’Z’ --High Impedance ’W’ --Weak Unknown ’L’ -- Weak 0 ’H’ -- Weak 1 ’--- don’t care

8. Is that object of type Real is supported in VHDL? and mention the reason?

Ans : No, because floating point numbers cannot be mapped to hardware.

9. Write an architecture syntax?

Ans : architecture architecture_name of entity_name architecture_declarative_part; begin Statements; end architecture_name;

10. What is a configuration?

Ans : It is that block of code which will bind the perticular architecture body to its entity and a component with an entity.

11. Write a configuration syntax?

Ans : configuration configuration_name of entity_name is block_configuration; end configuration_name;

12.

What that block_configuration signifies in configuration block? mention the syntax also?

Ans : Block_configuration in configuration block signifies binding of component in a block. The syntax is as shown below for block_name component_binding; end for;

13. Which is the key word to include library files in our program?

Ans : use.

14. Write an syntax to instantiat component?

Ans : Component_label: component_name port map (signal_list);

15. Is that possible to instantiate one entity to other entity/architecture pair? if no how we can

access other entity in current entity?

Ans : We can't instantiate entity/architecture pair directly Instead we can include component declaration in structural architecture body.

16. List out the objects of VHDL?

Ans : Signal, Variable, Constant.

17. Which are the major data types in VHDL?

Ans : Scalar Types and Composite Types

18. Which are the two composite types?

Ans : Array and Record

19. What is the difference between array and record?

Ans : Array contain many elements of the same type. But Record contains many elements of different types.

20. What is an alias and write its syntax?

Ans : Alias is an alternative name assigned to part of an object. alias alias_name : subtype is name;

21. What is the use of subtype in VHDL?

Ans : Subtype is mainly used for range checking and for imposing additional constraints on types.

22. Write an syntax for subtype?

Ans : subtype subtype_name is base_type range_constraint;

23. What are signals?

Ans : Signals are like a wires which connect design entities together and communicate changes in values within a design.

24. When the computed values will get assign to signal?

Ans : After delta delay

25. What are the properties of signal?

Ans : Type and Type attributes, value, time.

26.

Which is the signal assignment operator?

Ans : “ < = “

27. How the signal acts within a process and outside the process?

Ans : Signal assignment is concurrent outside the process and sequential within a process.

28. Mention the two delays in VHDL?

Ans : Inertial delay and Transport delay

29. How will you spwcify the delay in VHDL?

Ans : using after clause.

30. What is inertial delay?

Ans : This is the delay often found in switching circuits where spikes will not propogate further in circuit.

31. What is propogation delay?

Ans : Transport delay models the behavior of a wire, in which all pulses are propagated irrespective there width

32. Which is the default delay in VHDL?

Ans : delta delay.

33. What is the main functionality of block statements?

Ans : block statements don't have special functionality as such it separates part of the code without adding any functionality.

34. How the processes in program executes and how statements within process executes?

Ans : Processes will be executed concurrently but statements within process will be executed sequentaily.

35. How much time simulator takes to execute all statements in process?

Ans : zero simulation time.

36. Mention two types of process?

Ans : Combinational and Clocked processes.

37. Explain variables,constants?

Ans : variables are key words used to declare and can be used inside a process or subprograms. Variable assignment occurs immediately. Variable retain their variables throughout the entire simulation. Require less memory Constant are identifiers with a fixed value. They should not be assigned any values by the simulation process.

38. List out the differences between signal and variable?

Ans : Signals Connects design entities together. Signals can be declared both inside and out side of the process. It has three properties like type & type attributes, Value, Time. Signals assign its value after delta delay. Signals require more memory. Variable These are the identifiers within process or subprograms. This can only be declared within process can't be used outside a process. It has only two properties like Type,Value. Variable assigned its value immediately. Variable require less memory.

39.

List some the sequential statements?

Ans : if, elsif, else, case, loops,wait statement.

40. List out the different options available for wait statement?

Ans : wait on signal, wait until boolean_expr, wait for time_expr

41. Is “Real” data type is synthesizable?

Ans : Real is not synthesizable.

42. How we can include package in our program ?

Ans : library work; use work.pkg_name.all; Add these lines in code just after the standard library declaration.

43. What do we need to generate hardware from VHDL model?

Ans : We need following tools 1. Simulation tool. 2. Synthesis tool. 3. Implementation tool.

44 . How we come to know that the perticular model reflects intended behavior?

Ans : We use a tool called simulator to simulate the model to verify that the description is working as intended.

45. Which type of language it is?

Ans : Concurrent language and strongly typed language.

46. What is the main difference between software language and HDL?

Ans : Concurrency.

47. How will you test the design?

Ans : By sending different input to design by testbench.

48. How will you justify that it is strongly typed language?

Ans : VHDL allows LHS & RHS operators of same type. Different types in LHS & RHS is illegal in VHDL

49. List out the levels of abstractions in VHDL?

Ans : Data flow level, Structural Level, Behavioral Level

50. Which type of assignment statements will be used in data flow level and behavioral level?

Ans : Concurrent statements will be used in data flow level and Sequential statements will be used in behavioral level.

51. What is the difference between sequential circuit and combinational circuit?

Ans: Sequential circuit uses flip flops. Sequential circuits have state, which means basically they have memory. They compute the output based on input and the state and updated based on clocks. A combinational circuit does not have any states. They are functions of only inputs but not clocks. They are basically used to implement Boolean function.

52.

Why is configuration used?

Ans: To select one of the many architecture bodies that an entity may have.

53. What is generate? What are the types of generate?

Ans: Concurrent statements can be conditionally selected or replicated during the elaboration phase. This is called generate .there are two forms of generate. -for generate -if generate

54. What is access type?

Ans: These provide access to object that contains a sequence of values of a given type. Values belonging to access type are pointers to a dynamically allocated object of some other type.

55. What is generic?

Ans: Generics are used to pass certain type of information into o design description from its environment.

56. While accessing an array, can we give the array index as a variable?

Ans: Yes, we can. But the range of variable should be limited such that it doesn’t access outside the array limits.

57. What is record?

Ans: It is a collection of values that may belong to different types.

58. What is the difference between a latch and flip flop?

Ans: Latches are level sensitive and flip flops are edge sensitive. Latch allows time borrowing where as flip-flop does not allow time borrowing. Latches hold the last logic at output if we put it off. Flip-flops transfer data only at that instant of time and can be changed until next signal change.

59. Define setup time and hold time?

Ans: setup time is the time required for the synchronous inputs of a flip-flop to be stable before a clock pulse is applied. Hold time is the time that the synchronous inputs of a flip- flop remain stable after the active clock transaction is finished.

60. What is metastability?

Ans: Metastability is an unknown state. It is neither 0 or nor 1. If the setup time and hold time are violated, the flip-flop goes into metastability state.

61. How can we overcome metastability?

Ans: 1. Using proper synchronizers. 2. Using faster flip-flops.

62. What are attributes?

Ans: An attribute is a value, function, range, signal, type or constant that can be associated with certain names within VHDL description. These names could be among others, entity name, architecture name.

63. What is a test bench?

Ans: It is a code that generates the stimuli to test out design correctness. It automatically verifies the code accuracy. It also verifies whether the code meets the circuit requirements.

64.

What is the difference between inout and buffer ports?

Ans: A buffer is an OUT port with read capability. A buffer port may have at most one driver within the architecture where as inout port is just bidirectional port.

65. What is signal array?

Ans : A set of signals may also be declared as a signal array which is a concatenated set of signals.

66. How the signal array is declared?

Ans : < type> (< range>)

67. How multi dimentional array is declared?

Ans : type array_name is array (index_range, index_range) of element_type; .

68. Will synthasizer accept multi dimentional array? if not how we can declare that?

Ans : No we can declare the multi dimentional array as two uni dimentional array as shown in below example type byte is array (7 downto 0 ) of std_logic; type mem is array (3 downto 0) of byte;

69. List out the four modes for port in VHDL?

Ans : in,out,inout,buffer.

70. Which is the concatenation operator?

Ans : “&”

71. What is combinational process?

Ans : Process having all inputs in sensitivity list

72. What are constants?

Ans : Are identifiers with a fixed value.

73. What are assertion?

Ans : it is the statement used to report an error when a condition i false.

74. What is the syntax of assertion?

Ans : assert < condition> report < message> severity< level>

75. Which are the severity levels in assertion?

Ans : Warning , Error , Failure.

76. Which is the default severity level?

Ans : Error.

77. Is that assert is sequential statement or concurrent statement ?

Ans : both