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  • Simulation of Half Adder and Full Adder Using Verilog HDL

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    Anjana Jayachandran
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    The document describes simulating a half adder and full adder using Verilog HDL. It includes the procedures to design and test a half adder and full adder module in Verilog, and shows the output waveforms. The aim was to simulate half adder and full adder using Verilog. The procedures include creating a project, writing the code, checking for errors, creating test benches and simulating the output waveforms to verify the designs.

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    Simulation of Half Adder and Full Adder Using Verilog Hdl

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    The document describes simulating a half adder and full adder using Verilog HDL. It includes the procedures to design and test a half adder and full adder module in Verilog, and shows the output waveforms. The aim was to simulate half adder and full adder using Verilog. The procedures include creating a project, writing the code, checking for errors, creating test benches and simulating the output waveforms to verify the designs.

    Copyright:

    Attribution Non-Commercial (BY-NC)
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    3K Ansichten6 Seiten

    Simulation of Half Adder and Full Adder Using Verilog HDL

    Hochgeladen von

    Anjana Jayachandran
    The document describes simulating a half adder and full adder using Verilog HDL. It includes the procedures to design and test a half adder and full adder module in Verilog, and shows the output waveforms. The aim was to simulate half adder and full adder using Verilog. The procedures include creating a project, writing the code, checking for errors, creating test benches and simulating the output waveforms to verify the designs.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Als DOCX, PDF, TXT herunterladen oder online auf Scribd lesen
    Markieren Sie unangemessene Inhalte
    von 6

    SIMULATION OF HALF ADDER AND FULL ADDER USING VERILOG HDL EXPT : DATE: AIM:

    To design and simulate of half adder and full adder using verilog hardware description language.

    APPARATUS REQUIRED: Sl. No. 1. 2. 3. ALGORITHM:


    Declare the inputs and outputs of adder. Declare the intermediate variable as wire. Perform sum and carry operation. Perform the test bench operation of verification of truth table.

    COMPONENTS/ SOFTWARE PERSONAL COMPUTER XILINX ISE 9.1i MODELSIM SE 6.1a

    SPECIFICATION/ RANGE -

    Qty 1 1 1

    PROCEDURE:
    1. Go to start and click program, click EDA tool, and click XILINX ISE 9.1i 2. Select FILE and create new project in the project filed, give your project NAME and select the location. 3. In new project window will appear, then select varying module and specify the file name in approximate field, click next, then click finish. 4. Then a window will appear, you can type your code in the right side of the window. 5. Click check syntax, to verify the text code without any error. 6. Click on the symbol of FPGA device and the click on new source, and click test bench waveform and give the file name and click finish. 7. Select the text bench tool field and processes button by click the simulation behavior. 8. Verify your design in wave window by sending behavior of output signal with respect to input signal.

    PROGRAM FOR HALF ADDER module half_adder(s,c,a,b); input a,b; output s,c; xor a1(s,a,b); and a2(c,a,b); endmodule

    PROGRAM FOR FULL ADDER

    module full_adder(s,c,a,b,cin); input a,b,cin; output s,c; wire n1,n2,n3; xor s1(s,a,b,cin); and s2(n1,a,b); and s3(n2,cin,b); and s4(n3,cin,a); or s5(c,n1,n2,n3); endmodule

    OUTPUT WAVEFORMS: HALF ADDER

    FULL ADDER

    RESULT: Thus the half adder and full adder were designed and simulated using verilog hardware description language.

    SIMULATION OF HALF SUBSTRACTOR AND FULL SUBSTRACTOR USING VERILOG HDL


    AIM: To design and simulate of half substractor and full substractor using verilog hardware description language. APPARATUS REQUIRED: Sl. No. 1. 2. 3. COMPONENTS/ SOFTWARE PERSONAL COMPUTER XILINX ISE 9.1i MODELSIM SE 6.1a SPECIFICATION/ RANGE Qty 1 1 1

    ALGORITHM: Declare the inputs and outputs of substractor. Declare the intermediate variable as wire. Perform sum and carry operation. Perform the test bench operation of verification of truth table.

    PROCEDURE: 1. Go to start and click program, click EDA tool, and click XILINX ISE 9.1i 2. Select FILE and create new project in the project filed, give your project NAME and select the location. 3. In new project window will appear, then select varying module and specify the file name in approximate field, click next, then click finish. 4. Then a window will appear, you can type your code in the right side of the window. 5. Click check syntax, to verify the text code without any error. 6. Click on the symbol of FPGA device and the click on new source, and click test bench waveform and give the file name and click finish. 7. Select the text bench tool field and processes button by click the simulation behavior. 8. Verify your design in wave window by sending behavior of output signal with respect to input signal.

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