:

) (EIA Electronics Industries Association

.

) (mainframe )) (remote computer
.
. ) . (modem
.
) (Analog .
.
. : ) ( ). (RS-232
:
- ) ( Signal voltages,
- Signal timing ,
- Signal (each pin) function
- a protocol for information exchange ,
- Mechanical connectors

) (
) (EIA-232E
RS-232 EIA-232
)(.

IBM : serial
Port Parallel Port .

Parallel Port ) (Bit

.
) (Printer .

 .
.
) (full duplex
.

): (Bi-direction

) (Full-duplex
. .

) (start bit ) (Transmitter

.
). (BAUD
.
) ( ASCII ) (=
) (0 = .
) (stop Bit ) (1 Mark
. (logic one )condition
) ( ) ( ) (.
:
ASCII: American Standard Code for Information Interchange
.

): (Parity Bit

. ) (Parity Bit
.
.
) ( ) Logic (1 ) Logic(0
.
) ( ) (
. Detect one error
:
:
:
01100011 = 0
01101011 .
.
.
)( .

.
.
.

:RS232

) (TIA/EIA )
............. ( .

 D
).(male
.

DTE :DCE

:DCE .
:DTE .
DTE: Data Terminal Equipment :
DCE: Data Communications Equipment
. .DTE:
DCE: : DTE DCE
.
RS232 DTE ) (male .

:
)( RS232


(TD) -
(RD) -
(RTS) -
) ( )(CTS
)(DSR
(CD) -
(DTR ) -
)(RI

5
2
3
7
8
6
1
4
9

 :TD :

DTE .DCE Deceiving

) (DCE . " " .

:RD :

DTE
.

:RTS :

CTS DTE .DCE

DTE .
).(Mark Condition
RTS CTS ) ( .clear to send DCE
) logic(1 DTE .

: DTR

Data Terminal Ready DTR ) Logic (1

.

:CD :

. .

) :Ring Indicator (RI

..

) (BAUD :

) ( )(
.

 . .

Hardware
IBM :UART Universal Asynchronous
Receiver/Transmitter .
. UART
) (UART
CPU .
UART
UART .
UART .
Synchronous & Asynchronous :
Hardware
S . A .
:
UART : Universal Asynchronous Receiver/Transmitter
USART: Universal Synchronous Asynchronous Receiver/Transmitter

) (Clock
.

.
.

Clock .
.

) ( :

clock .

clock

.
UART ) ( UART
) (..
) (start Bit
) (Clock Clock .
Clocks
% .
) (start Bit
) Least Significant Bit (LSB
) (0 ) .(1
:
) (1 ) (0
.....



UART
. Host Processor
Clock
.
UART )
(.

.

8250 UART:

UART 8250
Registers
).(Microprocessor
) (initialize it
). (Built-in

16550 UARTs

Clock


*

D0:D7
RCLK

1:8
9





Active
Low
=
*


Active Low -



Active Low
Driver
disable
)Logic(0 CPU
. UART
Active Low
)(




)(
Active Low


Active
Low
Active
Low
Active
Low
master
Reset
Active Low
Active Low
Active
Low
Active Low

RD
TD
CS0
CS1
NCS2

10
11
12
13
14

nBaudOut

15

Xin
Xout
nWR
WR
Vss
RD
nRD
DDIS

16
17
18
19
20
21
22
23

nTXRDY
nADs

24
25

A0-A2

nRXRDY

26-27-28
29

INTR
nOUT2
nRTs

30
31
32

nDTR

33

nOUT1

34

MR

35

nCTs
nDSR
nDCD

36
37
38

nRI
VDD

39
40

:RS232

RS232 . ) ( Clock .

 Clock Start Bit

.
TTL/CMOS RS232

UART 8N1 .8N1

. .
RS232 idle ) Logic(1 Start Bit
) Logic(0 . )) (LSB
. )Logic(1 )
(
(.
) Logic(0
). (Start Bit
idle ) . Logic(1
) (Break ) Logic(0
.
) Logic(1 idle
.Break Signal
) (Framed )
( ) Logic(0
.
RS232 . UART
)Logic(0 + + )Logic(1
) + ( .
RS232
. .
:RS232
TTL CMOS .Logic Levels
RS232 ) (0 5 .

RS232 1488RS232
.
7.5+ 15.5+ 7.5 15.
+5 .
) ICs ( .
, MAX 232

 MAX232 +10 5 .
10 .
) (IC .
)(.
.

.

.
.
) : MAX232 (. 1F
MAX232 ) ( RS232
.
:
3 25 ) Logic(1 ) Mark Condition ) . (7
( +3 +25 ) Logic(0 ) . (Space Condition 3
+3 ) (Transition region .
) (
) (negative Logic .

RS232 .
. ). (Shielded
).(Unshielded

.
) LEDs (
.
.


.



)(

. Female
. male

)DTE (DCE RS232

.
))Null modem

 : /