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MIT SoC Design Competition

ONE BOARD, ONE MONTH, UNLIMITED POSSIBILITIES....

ARM AMBA3 AHB-Lite*


Karthik Shivashankar ARM LTD., Cambridge, UK

About Me

Sr. Engineer @ ARM Research Based in Cambridge, UK 4+ years at ARM

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Before we start

Have you worked on AMBA before ?

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Why we need Architecture Spec ?

Why we need Architecture Spec ?

Agenda
AMBA Family Introduction to AHB-Lite AHB-Lite System AHB-Lite Signals Master & Slave AHB-Lite Transactions How to build a simple AHB-Lite Slave AHB-Lite Multilayer Design
(2) (6) (8)

(15) (9) (4) (3)

Agenda
AMBA Family Introduction to AHB-Lite AHB-Lite System AHB-Lite Signals Master & Slave AHB-Lite Transactions How to build a simple AHB-Lite Slave AHB-Lite Multilayer Design
(2) (6) (8)

(15) (9) (4) (3)

AMBA Family
AMBA-1 AMBA-2
AHB AMBA-3 AHB-Lite AMBA-4

Acronyms AMBA Advanced Microcontroller Bus Architectures AHB Advanced High-Performance Bus

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Agenda
AMBA Family Introduction to AHB-Lite AHB-Lite System AHB-Lite Signals Master & Slave AHB-Lite Transactions How to build a simple AHB-Lite Slave AHB-Lite Multilayer Design
(2) (6) (8)

(15) (9) (4) (3)

Master-Slave Architecture

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AHB-Lite
Master 0

Slave #1

Slave #2

Slave #3

Slave #4

Single Master Simple slaves Easier module design/debug No arbitration issues


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AHB-Lite transactions
Master Register Read Register Write Burst Read Burst Write Slave Can make Master wait Can give error response

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AHB-Lite Features
Single Clock Edge operation Uni-directional busses No tri-state signals Good for synthesis Pipelined Operation

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An Example AMBA AHB-Lite System

ARM Processor (CM0-DS)

MEM CONTROLLER

AHB-Lite

VGA

UART

GPIO

PS2-KB

TIMER

7SEG

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An Example AMBA AHB-Lite System


DIGILENT NEXYS3
XILINX SPARTAN6
PUSH Buttons

ARM Processor (CM0-DS)

MEM CONTROLLER

PSRAM (16MB)

FLASH (16 MB)

AHB-Lite

VGA

UART

GPIO

PS2-KB

TIMER

7SEG

VGA

UART

Switches & LED

PS2

7-SEG Display

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An Example AMBA AHB-Lite System

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ARM R&D Testchip using CM0-DS

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Agenda
AMBA Family Introduction to AHB-Lite AHB-Lite System AHB-Lite Signals Master & Slave AHB-Lite Transactions How to build a simple AHB-Lite Slave AHB-Lite Multilayer Design
(2) (6) (8)

(15) (9) (4) (3)

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Main Components of AHB Lite System



Master Slaves Address Decoder Multiplexor

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AHB-Lite Master

Transfer Response AHB-Lite Master

Address and Control Write Data

Read Data

Global Signals

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AHB-Lite Slave

Slave Select

Address and Control


Write Data Global Signal

AHB-Lite Slave

Transfer Response

Read Data

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AHB-Lite Master & Slave


Slave Select

Address and Control

Write Data AHB-Lite Master AHB-Lite Slave

Transfer Response

Read Data

Global Signals

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Memory Map Decoder & MUX


Address, Control & Wdata Transfer Response AHB-Lite Master Read Data AHB-Lite Slave ADDR SEL1

Memory Map Decoder

SEL2

AHB-Lite Slave

SEL3

FF
MUX SEL

AHB-Lite Slave

Transfer Response, Rdata 1

Transfer Response, Rdata 2

MUX
Transfer Response, Rdata 2

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Pipelined Transactions (Conceptual Level)


Address phase Data phase N cycles HCLK

Address & Control

Data & Response

Memory Mapped Transactions: READ & WRITE

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Agenda
AMBA Family Introduction to AHB-Lite AHB-Lite System AHB-Lite Signals Master & Slave AHB-Lite Transactions How to build a simple AHB-Lite Slave AHB-Lite Multilayer Design
(2) (6) (8)

(15) (9) (4) (3)

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AHB-Lite Master Signals


Transfer Response Address and Control Write Data

Read Data

AHB-Lite Master

Global Signals

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AHB-Lite Slave Signals


Slave Select Address and Control Write Data Global Signal Transfer Response

AHB-Lite Slave

Read Data

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AHB-Lite Master & Slave

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AHB-Lite Master & Slave

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CM0-DS Doesnt speak the entire language !


CM0-DS do not generate BURST transaction

HBURST[2:0] is always 3b000

CM0-DS never generates locked transactions

HMASTLOCK is always 1b0

All transactions issued are non-sequential transfers

HTRANS[1:0] is either 2b00 (IDLE) or 2b10 (Non Sequential)

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AHB-Lite Master & Slave

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HSIZE[1:0]

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HPROT[3:0] Protection Signal Encoding

Master Generates these signals ! Slaves have the freedom to ignore !!


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HPROT[3:2] For CM0-DS

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HTRANS[1:0]
HTRANS Type Description

00
01

IDLE
BUSY

Master does not wish to perform a transfer


Bus Master is in the middle of a burst but cannot immediately continue with the next transfer Indicates the first transfer of a burst or a single transfer The remaining transfers in the burst are sequential address steps from the previous transfer. Step size is that of data width of transfer (which is shown by HSIZE)

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NON-SEQ

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SEQ

CM0-DS Always generates NON-SEQ Transactions


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Transactions

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Control Signals Recap


HTRANS[1:0] IDLE BUSY NONSEQ SEQ
HBURST[2:0] SINGLE INCR WRAP[4|8|16] INCR[4|8|16] HMASTLOCK UNLOCKED LOCKED

HSIZE[2:0] Byte Halfword Word Doubleword ...

HPROT[3:0] Data/Opcode Privileged/user Bufferable Cacheable

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Transfer Response Signals

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AHB-Lite Master & Slave

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Control Signals to Care about

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Agenda
AMBA Family Introduction to AHB-Lite AHB-Lite System AHB-Lite Signals Master & Slave AHB-Lite Transactions How to build a simple AHB-Lite Slave AHB-Lite Multilayer Design
(2) (6) (8)

(15) (9) (4) (3)

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Basic transfer - Write


Address phase Data phase HCLK

HADDR [31:0]

HWRITE

HWDATA [31:0]

Data (A)

HREADY

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Basic transfer - Read


Address phase Data phase HCLK

HADDR [31:0]

HWRITE

HRDATA [31:0]

Data (A)

HREADY

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AHB Pipelined Transaction


Address Phase A

Data Phase A Address Phase B

Data Phase B Address Phase C Data Phase C Address Phase .

HCLK HADDR HWRITE HWDATA HRDATA HRESP


A B C

OKAY A

OKAY B

HREADY

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Pipelined Operation
Address & Control Wdata Transfer Response AHB-Lite Master Read Data AHB-Lite Slave ADDR SEL1

Memory Map Decoder

SEL2

AHB-Lite Slave

SEL3 MUX SEL

FF
MUX SEL

AHB-Lite Slave

Transfer Response, Rdata 1

Transfer Response, Rdata 2

MUX
Transfer Response, Rdata 2

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AHB basic signal timing Adding wait states


Address Phase A Data Phase A Address Phase B

HCLK HADDR HWRITE HWDATA HREADY HRDATA


A B

HRESP

OKAY A

OKAY A

Master will extend Address Phase B


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HREADY (Inform all)


AHB-Lite Slave 1 AHB-Lite Master

HREADY

AHB-Lite Slave 2

FF
MUX SEL
HREADYOUT 1

AHB-Lite Slave 3

HREADYOUT 2

MUX
HREADYOUT 3

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HRESP Slave Response


HRESP OKAY Event Access completed normally Slave aborts access, (2 cycle response) Master has option of continuing or terminating a burst containing an ERROR Bus Master operation

ERROR

It is permissible to continuously drive HRESP Low in a system which does not wish to generate any errors.
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ERROR Response

HCLK HTRANS HADDR


NONSEQ SEQ

A+4

undef

HREADY

HRESP

ERROR

ERROR

If HRESP = ERROR, CM0-DS takes an exception and you should implement appropriate exception handler to catch the error

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Agenda
AMBA Family Introduction to AHB-Lite AHB-Lite System AHB-Lite Signals Master & Slave AHB-Lite Transactions How to build a simple AHB-Lite Slave AHB-Lite Multilayer Design
(2) (6) (8)

(15) (9) (4) (3)

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AHB2LED TOP LEVEL


Slave Select

Address and Control


Write Data

Transfer Response AHB2LED Read Data LED

Global Signal

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Sampling Address & Control


Data Phase A Address Phase Address Phase B A Data Phase B

HCLK
HADDR HSEL_A HWRITE HTRANS HREADY
A NONSEQ B NONSEQ C NONSEQ

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Sampling Address & Control


Data Phase A Address Phase Address Phase B A Data Phase B

HCLK
HADDR HSEL_A HWRITE HTRANS HREADY HWDATA
A B A NONSEQ B NONSEQ C NONSEQ

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AHB2LED Verilog Module


One way of implementing

Address and Control Sampling Phase

Data Sampling Phase

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BUS MATRIX - ISE

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Agenda
AMBA Family Introduction to AHB-Lite AHB-Lite System AHB-Lite Signals Master & Slave AHB-Lite Transactions How to build a simple AHB-Lite Slave AHB-Lite Advanced

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Shared Slave
Master 0 Master 1

Slave #1

Slave #2

Slave Mux Slave #3

Slave #4

Master 0 can access slaves #1, #2 & #3 Master 1 can access slaves #3 & #4 Contention occurs only if Master 0 & Master 1 try to access slave #3 sametime

Arbitration is at the slave level


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Multi-layer
ARM DMA

Slave Mux

Slave Mux

Slave Mux

Slave Mux

Slave #1

Slave #2

Slave #3

Slave #4

Generalizing on previous slide Contention occurs only if Master 0 & Master 1 try to access same slave at same time

Arbitration is at the slave level


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Typical Multi-layer example


Master 0 Master 1

On-chip RAM

Slave Mux AHB2APB

Slave Mux External Memory I/F GPIO

DMA Slave

UART

Timer

Master 0 can access private RAM, APB and external interface Master 1 can access DMA slave, APB and external interface

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Further Information
ARM IHI 0033 - AMBA 3 AHB-Lite Protocol Specification
http://infocenter.arm.com/

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THE END

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