Sie sind auf Seite 1von 14

This article has been accepted for inclusion in a future issue of this journal.

Content is final as presented, with the exception of pagination.


IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1

Design of Logic Gates and Flip-Flops in High-performance FinFET Technology


Ajay N. Bhoj, Student Member, IEEE, and Niraj K. Jha, Fellow, IEEE
Abstract With the emergence of nonplanar CMOS devices at the 22-nm node and beyond, it is highly likely that multigate device adoption will occur in a high-performance process technology, owing to the increased performance and area benets. In this paper, for the rst time, we evaluate symmetric (Symm- G ) and asymmetric (Asymm- G ) gateworkfunction FinFETs head to head in a high-performance process, using technology computer-aided design 3-D device simulations. We demonstrate that Asymm- G shorted-gate (a-SG) n/p-FinFETs, which use both workfunctions corresponding to typical high-performance metal-gate n/p-FinFETs, are promising, as they can yield over two orders of magnitude lower leakage without excessive degradation in ON-state current, in comparison to Symm- G shorted-gate (SG) FinFETs, placing them in a better position than back-gate biased independentgate (IG) FinFETs for leakage reduction. Thereafter, we explore the design space of FinFET logic gates, latches, and ip-ops, for optimal tradeoffs in leakage versus delay and temperature, using mixed-mode 2-D device simulations. Elementary logic gates (such as INV, NAND2, NOR2, XOR2, and XNOR2) using Asymm- G SG-mode FinFETs appear to be located optimally in the leakagedelay spectrum, in comparison to the most versatile congurations possible by mixing corresponding Symm- G SG- and IG-mode FinFETs. Latches and ip-ops, however, require an astute combination of Symm- G and Asymm- G FinFETs to optimize leakage, delay, and setup time simultaneously. Index Terms Device simulation, FinFETs, ip-ops, leakage power, logic gate, multigate device.

I. I NTRODUCTION LANAR transistor scaling in deep-submicrometer CMOS technology has approached its limits at sub-22-nm nodes, owing to very poor electrostatic integrity, which is manifested as degraded short-channel behavior and high leakage current. Multigate eld-effect transistors (FETs) overcome these problems because of tighter control of the channel potential by multiple gates wrapped around the body. Amongst multigate FETs, FinFETs/ -FETs have emerged as the best candidate structures from a fabrication perspective [1]. The FinFET device structure consists of a silicon n surrounded by shorted or independent gates on either side of the n, typically on a silicon-on-insulator substrate. In the SG mode of operation, the two gates are biased together to
Manuscript received May 14, 2012; revised August 14, 2012; accepted October 23, 2012. This work was supported by SRC under Contract 2010HJ-2079. The authors are with the Department of Electrical Engineering, Princeton University, Princeton, NJ 08544 USA (e-mail: abhoj@princeton.edu; jha@princeton.edu). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TVLSI.2012.2227850

turn on the device, providing maximum gate drive. In the IG mode of operation, the two gates are electrically independent. The back-gate bias can be used to alter the threshold voltage (Vth ) of the front gate, thereby controlling the OFF-current (IOFF ) of the device [2]. IOFF in SG-mode devices is generally much higher than in IG-mode devices [with the back gate held above (below) the rail for p-type (n-type)], and, because of the xed Vth , it cannot be altered electrically. The Vth is typically controlled by directly setting the gate workfunction. If the front and back gates have the same (different) workfunctions, they are referred to as Symm- G (Asymm- G ) FinFETs. While IG-mode devices provide the advantage of controlling the device Vth , and hence delay/leakage, they lead to a complicated transistor layout strategy. This is due to the fact that multin IG-mode FinFETs need larger spacing between the source and drain regions, as well as larger n pitch in order to land a contact to the back gate in comparison to corresponding multin SG-mode FinFETs with compact layouts. The major contributions of this paper are as follows. 1) We evaluate Symm- G and Asymm- G FinFET devices head to head in a high-performance process using 3-D device simulations in Sentaurus technology computer-aided design (TCAD) [3]. 2) We examine the effect of physical device parameters on ON -current (ION ), OFF -current (IOFF ), and gate workfunction uctuations (which are likely to be the largest sources of Vth variation [4]) on FinFET leakage via quasi-Monte Carlo 3-D device simulations. 3) We comprehensively probe the design space of SymmG and Asymm- G FinFET logic gates and ipops along various electrical characteristic dimensions (leakage, delay) and layout complexity/area by suitably mixing SG/a-SG/IG-mode FinFETs, using mixed-mode 2-D device simulations. 4) For the rst time, we also demonstrate that the most versatile Symm- G topologies fail to approach the leakagedelay tradeoffs enjoyed by logic elements based on Asymm- G SG-mode FinFETs. This suggests that it is more practical to use Asymm- G FinFETs for ultralow-leakage designs in a high-performance FinFET technology rather than integrate Symm- G IG-mode FinFETs (which have high area/process overheads and introduce additional CAD/layout design/testing costs), or add a third gate workfunction to the process (which dramatically exacerbates yield control issues and process cost). The rest of this paper is organized as follows. In Section II, we review related work. In Section III, we evaluate key

10638210/$31.00 2013 IEEE

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
2 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

metrics of Symm- G and Asymm- G FinFETs via 3-D/2-D device transport simulations. Thereafter, we employ mixedmode 2-D device simulations in subsequent sections, owing to the rapid increase in computational complexity/time of 3-D device simulations. In Section IV, we characterize various plausible Symm- G and Asymm- G FinFET inverter (INV) and two-input NAND (NAND2) logic gates in detail to determine the most versatile congurations with respect to the electrical characteristics. In Section V, we examine tradeoffs in designing basic latch and ip-op topologies using various combinations of Symm- G SG/IG-mode and AsymmG SG-mode FinFETs, using insights from Sections III and IV. Finally, we conclude in Section VI. II. R ELATED W ORK Circuit design based on low-leakage multigate FETs/FinFETs has garnered signicant attention over the past decade, owing to the explosive increase in leakage power consumption in planar FETs at lower technology nodes. Low-power multigate circuit design has been explored from a device-circuit viewpoint in [5] and [6]. In [7][9], logic styles leveraging the SG and IG modes of FinFET operation have been investigated. FinFET latches and ip-ops have been studied in [10] and [11]. Owing to its small dimensions, a FinFET is likely to suffer from the effects of process and temperature variations. In gate workfunction variation is shown to be the most important contributor to the variation in Vth for metal-gate FinFETs. FinFETs with asymmetric gate workfunctions in the form of n+/p+ polysilicon gates have been engineered and investigated in [12] and [13]. Since multigate adoption is likely to be driven by performance/area benets, in this paper, we comprehensively characterize Symm- G and Asymm- G FinFETs in a highperformance process. We also investigate various possible congurations of logic gates and ip-ops employing such FinFETs through mixed-mode device simulation (taking into account the effect of temperature) from a digital circuit designers perspective. Preliminary results dealing with the latter were presented in [14]. III. S YMMETRIC - G AND A SYMMETRIC FinFET D EVICES
G

SOURCE

GATE

Z Y X

DRAIN

Fig. 1.

SG-mode 3-D FinFET structure simulated in Sentaurus TCAD.

Fig. 2. TCAD.

2-D (X-Y ) cross-section of an n-FinFET simulated in Sentaurus

In this section, we evaluate Symm- G and AsymmFinFETs head to head in a high-performance G process. Owing to the absence of a suitable platform for multigate circuit design exploration, we use FinE3D, an extension of FinE [15]. We utilized the FinFET device structure shown in Fig. 1 for 3-D device transport simulations in Sentaurus TCAD [3]. Also, a 2-D (X-Y ) cross-section of the device structure in Fig. 1 as shown in Fig. 2, was employed for mixed-mode devicecircuit simulations. In Table I, the parameters for a typical n/p-FinFET device are listed, where L GF , L GB , TOXF , TOXB , TSI , HFIN , HGF , HGB, L SPF , L SPB , L UN , NBODY , GF , GB , NSD , and VDD are the physical front- and back-gate lengths, front- and back-gate effective oxide thicknesses, n thickness, n height, front- and back-gate thicknesses,

front- and back-gate spacer thicknesses, gate-drain/source underlap, body doping, front- and back-gate workfunctions, source/drain doping, and the operating voltage, respectively. The Vth of FinFETs is typically tuned by directly adjusting the workfunction of the gate material [16]. The workfunctions for n-FinFET ( GF = GB = Gn = 4.4 eV) and p-FinFET ( GF = GB = Gp = 4.8 eV) devices were chosen corresponding to high-performance logic requirements [17] and yield low-Vth devices whose symbols are shown in Fig. 3. A. ION and IOFF Characteristics We revisit the physics of SG- and IG-mode FinFET devices, to better appreciate the limitations of Symm- G devices and the advantages of Asymm- G FinFETs. Accounting for temperature effects, we performed hydrodynamic mixed-mode 3-D device simulations on carefully dened meshes (for excellent convergence) and invoked the density gradient model for incorporating quantum effects in a thin n. We ignored the

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
BHOJ AND JHA: LOGIC GATES AND FLIP-FLOPS DESIGN IN HIGH-PERFORMANCE FinFET TECHNOLOGY 3

TABLE I FinFET D EVICE PARAMETERS


DRAIN

X
DRAIN

Parameters L GF , L GB (nm) Effective TOXF , TOXB (nm) TSI (nm) HFIN (nm) HGF , HGB (nm) L SPF , L SPB (nm) L UN (nm) NBODY (cm3 ) GF , GB (eV) NSD (cm3 ) VDD (V) VHIGH (V) VLOW (V) 25 1 10 50 20 20 10 1015 : 4.4, Gp : 4.8 Gn 1020 1 1.2 0.2

FRONT GATE

BACK GATE

FRONT GATE

SOURCE

SOURCE

(a)

BACK GATE

(b)

GF

GB

=4.4eV

GF=GB=4.8eV

FRONT GATE

(a)

(b)

(c)

(d)

Fig. 3. Symm- G FinFET symbols. (a) SG-mode n-type. (b) IG-mode n-type. (c) SG-mode p-type. (d) IG-mode p-type.

effects of gate tunneling currents due to the undoped n, and used an effective oxide thickness that can easily be realized using thicker high-k dielectrics to suppress gate leakage. Fig. 4(a) and (b) show the electrostatic potential in the n region (XY plane) of an SG-mode n-FinFET under ON -state (VGFS = VGBS = 1 V, VDS = 1 V) and OFF -state (VGFS = VGBS = 0 V, VDS = 1 V) conditions. In the ON state, both gates contribute to band-bending such that inverted regions [Fig. 4(c)] form beside both gates (and move toward the n center as TSI decreases, due to increased quantum connement), leading to high drain current. In the OFF state, the n center is most susceptible to leakage [Fig. 4(d)], as the barrier height for electrons is higher for paths closer to either gate. In Figs. 5(a)(d), the electrostatic potential and electron density in an IG-mode n-FinFET is shown with VGBS = 0.2 V. The bias on the back gate causes an inverted region to form predominantly near the front gate, which contributes to the drain current in the ON state [Fig. 5(a) and (c)], and leads to leakage paths beside the front gate in the OFF state [Fig. 5(b) and (d)]. The peak electron density in the OFF state (which is tunable using VGBS ) is over an order of magnitude smaller in the IG mode in comparison to the SG mode, indicating that IGmode FinFETs have lower leakage. This suggests that using IG-mode FinFETs (with a strong reverse bias on the back gate) can considerably reduce leakage by up to two orders of magnitude in FinFET standard cells in high-performance processes.

FRONT GATE

BACK GATE

X
(c)

X
(d)

Fig. 4. (a) ON-state electrostatic potential. (b) OFF-state electrostatic potential. (c) ON-state electron density. (d) OFF-state electron density. Electrostatic potential and electron density distributions within the n region of an SG-mode n-FinFET for ON-state (VGFS = VGBS = 1 V, VDS = 1 V) and OFF-state (VGFS = VGBS = 0 V, VDS = 1 V) conditions.

Next, we introduce Asymm- G FinFETs and demonstrate that they possess steep subthreshold characteristics that can be employed in the design of ultralow-leakage logic circuits in high-performance process technologies, thus reducing the need for Symm- G IG-mode FinFET-based back-gate biasing schemes. Asymm- G FinFETs can be formed by adjusting the workfunctions on each side of the SG-mode FinFET using selective implantation for the gate-stack. This has been demonstrated for n+ /p+ polysilicon gates using large-angle tilt implants [12], [13]. If the choice of front/back-gate workfunctions is identical to that of high-performance n/p-FinFET metal-gate workfunctions, as shown in Fig. 6, it would be favorable from a fabrication perspective. All Asymm- G FinFETs, n- or p-channel,

BACK GATE

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
4 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

X
DRAIN
DRAIN

GB

=4.4eV

GB=4.4eV

Y
Y

FRONT GATE

FRONT GATE

BACK GATE

BACK GATE

GF

=4.8eV
(a)

GF

=4.8eV
(b)

Fig. 6. Asymm- G FinFET symbols. (a) a-SG-mode n-type. (b) a-SG-mode p-type.
X

X
DRAIN

SOURCE

SOURCE

DRAIN

(a)

(b)
FRONT GATE (G = 4.8eV) BACK GATE (G = 4.4eV)

FRONT GATE (G = 4.8eV)

FRONT GATE

FRONT GATE

BACK GATE

BACK GATE

SOURCE

SOURCE

(a)

BACK GATE (G = 4.4eV)

(b)

Z
FRONT GATE ( = 4.8eV)

FRONT GATE (G = 4.8eV)

X
(c)

X
(d)

Fig. 5. (a) ON-state electrostatic potential. (b) OFF-state electrostatic potential. (c) ON-state electron density. (d) OFF-state electron density. Electrostatic potential and electron density distributions within the n region of an IGmode n-FinFET for ON-state (VGFS = 1 V, VGBS = 0.2 V, VDS = 1 V) and OFF-state (VGFS = 0 V, VGBS = 0.2 V, VDS = 1 V) conditions.

BACK GATE ( = 4.4eV) G

would have both workfunctions on either side of the n, without the need for complicating the process with a third gate workfunction exclusively for high-Vth devices, and high-performance SG-mode Symm- G n/p-FinFETs would be fabricated along with them using the same gate workfunctions. In Fig. 6, both n-FinFETs and p-FinFETs have 4.4/4.8 eV workfunctions, with the source/drain doping determining the type of majority charge carrier conduction during the ON state. Since the asymmetric-workfunction gates are shorted, they are referred to as a-SG-mode FinFETs. From Fig. 7(a), we see that, during the ON state (VGFS = VGBS = 1 V, VDS = 1 V), the electrostatic potential distribution in an a-SG-mode n-FinFET approaches that of a

X
(c)

X
(d)

Fig. 7. (a) ON-state electrostatic potential. (b) OFF-state electrostatic potential. (c) ON-state electron density. (d) OFF-state electron density. Electrostatic potential and electron density distributions within the n region of an a-SG-mode n-FinFET for ON-state (VGFS = VGBS = 1 V, VDS = 1 V) and OFF-state (VGFS = VGBS = 0 V, VDS = 1 V) conditions.

Symm- G SG-mode n-FinFET [Fig. 4(a)], resulting in a reasonably high drain current. This is also indicated by the volume inversion in the n [Fig. 7(c)]. In the OFF state

BACK GATE (G = 4.4eV)

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
BHOJ AND JHA: LOGIC GATES AND FLIP-FLOPS DESIGN IN HIGH-PERFORMANCE FinFET TECHNOLOGY 5

10

68% I

reduction w.r.t SGmode ON

14 12 10

x 10

SGmode aSGmode IGmode

10

ION (A)
)

10 IDS (A)

8 6

10

26% ION reduction w.r.t SGmode aSGmode (V


GBS

=V

10

10

415X 15X

GFS

IGmode (V

GBS

= 0.2V)

4 2 0.02

SGmode (VGBS = VGFS)

10

12

0.022

0.024

0.026

0.028

0.03

0.2

0.4 V
GFS

0.6 (V)

0.8

LG (m)
(a)
1.4 1.2 x 10
4

Fig. 8. IDS versus VGFS for an a-SG-mode n-FinFET (VDS = 1 V), with corresponding curves for SG-mode and IG-mode n-FinFETs.
10
2

88% ION reduction w.r.t SGmode 41% ION reduction w.r.t SGmode

(A)
ON

10

0.8 0.6 0.4

10
DS

(A)

10

0.2
10
10

SGmode (VGBS = VGFS) IGmode (V


GBS

SGmode aSGmode IGmode 0.008 0.01 0.012 0.014

= 0.2V) =V
GFS

175X 5X 0.2 0

0 0.006

aSGmode (V 10
12

T (m)
SI

GBS

(b)
16 14 12 x 10
5

0.8

0.6 V
GFS

0.4 (V)

Fig. 9. IDS versus VGFS for an a-SG-mode p-FinFET (|VDS | = 1 V), with corresponding curves for SG-mode and IG-mode p-FinFETs.

SGmode aSGmode IGmode

[Fig. 7(b) and (d)], the energy bands bend strongly near the front-gate side (as GF = 4.8 eV), thereby raising the barrier for electrons. The electrostatic potential/electron density distributions are qualitatively identical to those observed in the Symm- G IG-mode FinFETs in the OFF state in Fig. 5(b) and (d), respectively. Therefore, Asymm- G FinFETs combine the advantages offered by Symm- G SG- and IG-mode FinFETs. Fig. 8 quanties the above, showing that Symm- G SGmode (IG-mode) n-FinFETs have 415 (15) higher leakage current compared to a-SG-mode devices at 300 K. Fig. 9 shows that Symm- G SG-mode (IG-mode) p-FinFETs have 175 (5) higher leakage than a-SG-mode p-FinFETs. B. Effect of Device Parameter Variations We also investigated the effect of variations in the parameters L G , TSI and L UN on ION and IOFF . Fig. 10(a) shows that in SG/a-SG-mode and IG-mode FinFETs, ION decreases

ION (A)

10 8 6 4 2 4

10 x 10

12
3

LUN (m)
(c)

Fig. 10. (a) ION versus L G . (b) ION versus TSI . (c) ION versus L UN . ION characteristics versus variations in L G , TSI , and L UN .

almost linearly with an increase in L G . ION increases linearly with an increase in TSI in Fig. 10(b), with higher slopes for SG/IG-mode FETs in comparison to a-SG-mode FETs.

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
6 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Fig. 10(c) shows that ION in SG-mode FETs is very sensitive to reduction in L UN , followed by IG-mode FETs, while a-SG-mode FETs are relatively immune to changes in L UN . IOFF , on the other hand, is greatly affected by all three parameters. Fig. 11(a) shows that IOFF in SG/IG-mode devices has an exp(k/L G ) dependence, while a-SG-mode FETs show a stronger exp(k1 /L G + k2 L G ) dependence, where k, k1 , and k2 are constants. Fig. 11(b) shows that IOFF has an exp(k1 /L G + k2 L G ) dependence in all cases, with different values for k1 and k2 for each device. IOFF appears to roughly have an exp(k1 L 2 + k2 L UN ) dependence on L UN in all cases UN in Fig. 11(c). C. Effect of Gate-Workfunction Fluctuations Since metal-gate FET Vth s are linearly dependent on the gate workfunction, we studied the effect of workfunction uctuations on IOFF (or ILEAK ) in n-FinFETs. In [4], gate workfunction variation is shown to be the major contribution to Vth variation in comparison to L G and TSI , which have minor contributions. Using a quasiMonte Carlo (QMC) sample generator, we performed QMC 3-D device simulations, varying G for SG/a-SG/IG-mode n-FinFETs with G = 50 meV, and limited the total sample count to 100 on account of the prohibitively large runtimes for 3-D device simulation. Fig. 12 shows the ILEAK distributions, with a-SG-mode devices maintaining lower/comparable spreads with respect to SG/IG-mode FinFETs. The above investigation into parametric dependences with respect to L G , TSI , and L UN and variation analysis based on gateworkfunction uctuations suggest that a-SG-mode FinFETs are likely to be very robust to process variations. D. Effect of Temperature on Leakage Fig. 13 suggests that the ILEAK advantage in topologies having SG- and IG-mode FinFETs would reduce relative to those of only SG-mode FinFETs with an increase in temperature. Also, a-SG-mode devices have two (one) orders of magnitude lower IOFF than Symm- G SG-mode (IG-mode) FinFETs. IV. S YMMETRIC G AND

0.02

/1 nA)
10

(I

OFF

0.02

LG log

0.04 SGmode aSGmode IGmode 0.022 0.024


G

0.06

0.08 0.02

0.026

0.028

0.03

L (m)
(a)
0.015 0.01 SGmode aSGmode IGmode

TSI log10 (IOFF/1 nA)

0.005 0 0.005 0.01 0.015 0.02 0.006

0.008

0.01

0.012

0.014

T (m)
SI

(b)
1 0.5 SGmode aSGmode IGmode

(IOFF/1 nA) log


10

0 0.5 1 1.5 2 2.5 4

A SYMMETRIC L OGIC G ATES

FinFET

A signicant problem with logic circuits implemented in high-performance process technologies is the relatively high leakage current that is concomitant with the high ON-state current. Hence, circuit topologies with low leakage that do not compromise on performance constitute the optimal design points. In this section, we explore the design space of SymmG FinFET INV and NAND 2 gates in detail to determine the most versatile topologies that can arise by mixing Symm- G SG- and IG-mode FinFETs. A. 3-D Versus 2-D Device Simulation Owing to the prohibitively high computational costs involved in single-FET 3-D transport simulations, mixedmode 3-D device simulations for FinFET circuits is intractable

10 x 10

12
3

LUN (m)
(c)

Fig. 11. (a) IOFF versus L G . (b) IOFF versus TSI . (c) IOFF versus L UN . IOFF characteristics versus variations in L G , TSI , and L UN .

in practical timeframes. Also, transient simulations, which are necessary to capture logic element delays, are extremely cumbersome to perform via 3-D device simulation on account of which device simulations on a 2-D structure (corresponding to a slice of the 3-D FinFET device) are used hereafter. Since 2-D simulations do not fully capture all physical effects

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
BHOJ AND JHA: LOGIC GATES AND FLIP-FLOPS DESIGN IN HIGH-PERFORMANCE FinFET TECHNOLOGY 7

0.6 0.4
DS, 3D

33%

)/I

aSG IG SG

0.2 24% 0 0.2 0.4 0.6 0.8 0 4.5% 11.2% SGmode IGmode aSGmode 0.2 0.4 0.6 0.8 1 4.3%

(I

DS, 2D

DS, 3D

VGFS (V)
Fig. 12. ILEAK distribution for a-SG/SG/IG-mode n-FinFETs under gate workfunction uctuations. G = 50 meV.
10
7

Fig. 14. Fractional error in IDS versus VGFS for 2-D/3-D device simulations.

10

104X 8X

IOFF (A)

10

(a)
10

(b)

(c)

(d)

640X

10

Fig. 15.

INV gates. (a) SG. (b) LP. (c) IGn. (d) IGp.

10

11

18X 10
12

aSGmode SGmode IGmode (VGBS = 0.2V) 320 340 360 Temperature (K) 380 400

280

300

Fig. 13. IOFF versus temperature for an a-SG-mode n-FinFET, with corresponding curves for SG-mode and IG-mode n-FinFETs.

(e.g., corner effect [17]) on carrier transport, we computed the error percentage from the drain currents, (I D S,2- D I D S,3-D )/I D S,3-D versus VGFS from 2-D/3-D device simulations [Fig. 14]. In general, 2-D device simulation overpredicts IOFF and underestimates ION with respect to corresponding 3-D simulations. Also, a-SG-mode devices have relatively large differences between 2-D and 3-D simulations in the subthreshold regime, in comparison to SG/IG-mode devices. However, IOFF and ION predictions are marginally different (within 33% for IOFF and 11.2% for ION ), suggesting that reasonably accurate comparisons can be made with mixedmode 2-D device circuit simulations. B. SymmG

and Asymm-

Logic Gates

Fig. 15 shows four possible INV congurations with SG/IG-mode FinFETs: SG-, low-power (LP-) [7], IGn-, and IGp-INV. The SG-INV conguration has only SG-mode

n/p-FinFETs with a highly compact layout, as shown in Fig. 16(a). In the LP-INV conguration [Fig. 15(b)], the back gate of PA (NA) in the pull-up (pull-down) network is biased to VHIGH (VLOW ), necessitating a complex layout [Fig. 16(b)] with 36% larger area than size X2 SG-INV, while IGn-INV [Fig. 16(c)] and IGp-INV [Fig. 16(d)] occupy the same area as LP-INV, owing to the multin IG-mode FinFET back-gate contacts. Amongst NAND2 gates [Figs. 17 and 18], while SGNAND 2 has the most compact layout [Fig. 19(a)], LP- NAND 2 [Fig. 19(b)] occupies 27% more area than size X2 SG- NAND2, with a staggered pull-up network of parallel FinFETs, and shared back-gate contacts for the series pull-down FinFETs. Mixed-terminal (MT-) NAND2 [18] is identical to LP-NAND2 in area, with NB in SG mode [Fig. 17(c)]. IG- and IG2NAND 2 combine the parallel FinFETs of the pull-up network into a single p-FinFET, whereby the layout area is the same as SG-NAND2. XT-NAND2 is a variant of MT-NAND2, with both FinFETs of the pull-down network in SG mode and identical layout area (not shown). XT2- NAND2 is also a variant of MT-NAND2, with both parallel FinFETs of the pull-up network in SG mode, which enables a compact layout [Fig. 19] with the same area as SG-NAND2. Fig. 20(a) and (b) show Asymm- G -based SG-mode FinFET INV and NAND2 gates. (Note that any Symm- G based FinFET logic gate schematic/layout can be converted to the corresponding Asymm- G version by replacing the devices with no layout overheads.) For generalized pull-up and pull-down networks, it is possible to mix Asymm- G

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
8 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

(a)

(b)

(c)

(d)

Fig. 16. INV layouts. (a) SG (size X2). (b) LP (size X1). (c) IGn (size X1). (d) IGp (size X1).

(a)

(b)

(c)

Fig. 19. NAND 2 layouts. (a) SG (size X2). (b) LP (size X1). (c) XT2 (size X1).

(a)
Fig. 17.
NAND 2

(b)
gates. (a) SG. (b) LP. (c) MT.

(c)

(a)

(b)
FinFET gates.

(c)
(a) a-SG-INV.

Fig. 20. Asymm- G SG-mode (b) a-SG-NAND2. (c) a-SG-NAND2S.

TABLE II S TANDARD C ELL FinFET INV C HARACTERISTICS , VLOW = 0.2 V AND VHIGH = 1.2 V Topology Area (w.r.t to SG) Avg. ILEAK (nA) t p (ps) SG 1 2.51 3.31 LP 1.36 0.12 12.15 IGn 1.36 0.33 5.55 IGp 1.36 2.31 9.66

(a)

(b)

C. LeakageDelay Characteristics: Symm-

Logic

(c)
Fig. 18.
NAND 2

(d)

gates. (a) IG. (b) IG2. (c) XT. (d) XT2.

FinFETs for leakage reduction with Symm- G FinFETs for speed. This strategy was applied to the NAND2 gate to yield the NAND2S gate shown in Fig. 20(c).

Table II and Fig. 21 show the leakagedelay characteristics of the Symm- G FinFET INV standard cells. The leakage current ILEAK is an average over all input vectors, and delay t p is the fanout-of-four (FO4) delay. All comparisons below are drawn with respect to SG-INV (size X2), as it is the largest SG-INV that can be accommodated for the chosen standard cell height. In Fig. 21, VHIGH and VLOW are varied (if permitted by the topology), in order to sweep the design space. SG-INV (size X2) has the smallest delay t p = 3.31 ps, with the largest average ILEAK [SG-INV (size X1) was found to have t p = 5.75 ps]. LP-INV shows over an order of magnitude reduction in mean ILEAK with a 267% (111%) increase in t p with respect to SG-INV size X2 (size X1). From Fig. 21, it is clear that the dominant factor affecting t p , for the current

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
BHOJ AND JHA: LOGIC GATES AND FLIP-FLOPS DESIGN IN HIGH-PERFORMANCE FinFET TECHNOLOGY 9

Fig. 21.

Leakagedelay spectrum for FinFET INV congurations. TABLE III S TANDARD C ELL FinFET NAND 2 C HARACTERISTICS Topology SG LP MT IG IG2 XT XT2

Fig. 22.

Leakagedelay spectrum for FinFET NAND2 congurations.

Area (w.r.t to SG) Avg. ILEAK (nA) t p (Toggle A) (ps) t p (Toggle B) (ps) t p (Toggle AB) (ps)

1 1.27 1.27 1 1 1.27 1 2.76 0.15 1.05 2.76 1.16 2.72 1.16 5.47 22.60 20.80 8.77 11.40 17.50 8.04 5.07 22.82 19.66 8.56 10.26 18.17 7.01 4.41 15.33 13.66 4.41 6.85 10.50 6.85

choice of Gn and Gp , is VHIGH . For IGp-INV, lowering VHIGH increases t p and only marginally reduces average ILEAK . For LP-INV, varying VLOW (with VHIGH = 1.2 V) presents a lower slope on the leakagedelay plot in comparison to varying VHIGH (with VLOW = 0.2 V), which reafrms the above. IGn-INV appears to provide the best leakage delay tradeoff, with upto an order of magnitude reduction in average ILEAK at the cost of 66% increase in t p with respect to SG-INV (size X2) and marginally better t p than SG-INV (size X1). Table III and Fig. 22 show the leakagedelay spectrum for the various FinFET NAND2 gates. All comparisons below are drawn with respect to SG-NAND2 (size X2), as it is the largest SG-NAND2 that can be accommodated in the chosen standard cell height. In Fig. 22, LP-NAND2 (VLOW = 0.2 V, VHIGH = 1.2 V) shows over an order of magnitude reduction in mean cell leakage with around 4 higher t p in comparison to SGNAND 2. Varying VHIGH presents a steep slope in the leakage delay plot for our choice of Gp and Gn , suggesting that pull-up FinFETs should be in SG mode. This is also seen for XT-NAND2 and MT-NAND2 gates, where varying VHIGH could only increase delay and does not decrease the average ILEAK . IG-NAND2 does not gain in average ILEAK in spite of combining the parallel pull-up FinFETs into a single p-FinFET. Instead, the rising delay, t p L H , degrades for IG-NAND2, which increases t p . IG2-NAND2 has a larger t p compared to IG-NAND2 over the entire spectrum of VLOW variation due

to higher falling delay, t p H L , (owing to a slower pulldown stack). However, decreasing VLOW enables over 50% reduction in average ILEAK . XT2-NAND2 presents a similar tradeoff in average ILEAK reduction, with the benet of lower t p L H , owing to a fast parallel SG-mode pull-up. Overall, XT2-NAND2 lies closest to SG- NAND2 in the leakagedelay spectrum, offering the best way to leverage back-gate biasing to reduce average ILEAK without a signicant degradation in delay. We see from Table III that, unlike traditional planar bulk CMOS NAND2 gates, t p (Toggle A) t p (Toggle B) for many of the FinFET logic styles [e.g., Figs. 23(a) and 24(a)]. This is dependent on the input slew rate, intermediate node capacitance (CINT )/node voltage (VINT ) of the pulldown stack, output load capacitance (COUT ), and modes of FinFET operation in the logic gate. In Figs. 23(a) and 24(a), the transient behavior of SG-NAND2 is shown, with VGFS across FinFET NA rising slightly faster for the Toggle B condition in comparison to Toggle A. Hence, t p (Toggle A) > t p (Toggle B). This is exacerbated in XT2- NAND2 [Fig. 24(a) and (b)], as VINT does not rise to VDD when VOUT = V A = VDD , owing to the IG-mode FinFET NA, which loses gate drive very quickly when VINT increases, and VGFS is nonzero in the dc condition. The latter, along with the fact that CINT COUT (CINT mainly consists of source/drain body depletion capacitances which are negligible in FinFETs), helps VGFS develop very quickly across NA in the Toggle B condition in comparison to Toggle A [Fig. 24(b)]. From the above analysis, introducing a single IG-mode n-FinFET in the pull-down series stack with only SG-mode p-FinFETs in the pull-up network, as with XT2-NAND2, appears to be the best method to leverage the leakagedelay tradeoff using back-gate biasing in high-performance SymmG FinFET standard cells.

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
10 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

1.2

1.2 1 0.8

0.8

Voltage (V)

Voltage (V)

0.6

0.6 VA, VB 0.4 0.2 0 VOUT, Toggle A V


OUT

V ,V
A

0.4

VOUT, Toggle A VOUT, Toggle B VINT, Toggle A VINT, Toggle B

, Toggle B

VINT, Toggle A V
INT

0.2

, Toggle B

0
0.2 0 1 2 3 4 5 x 10 6
10

0.2 0

5 x 10

6
10

Time (s) (a)

Time (s) (a)

1.2 1 Toggle A, B=1 Toggle B, A=1

1.2 1

VGFS (V), FinFET NA

Toggle A, B=1 Toggle B, A=1

0.8 0.6 0.4 0.2 0

VGFS, FinFET NA

0.8 0.6 0.4 0.2 0

0.2 0

2
(b)

5 x 10

6
10

0.2 0

Time (s)
1 2
(b)

5 x 10

6
10

Time (s)

Fig. 23. SG- NAND2 transient charactertistics. Input rise time has been increased from 10 to 50 ps to improve visibility. (a) Node voltages, and (b) VG F S on FInFET NA.

Fig. 24. XT2-NAND2 transient charactertistics. Input rise time has been increased from 10 to 50 ps to improve visibility. (a) Node voltages, and (b) VG F S on FInFET NA.

D. LeakageDelay Characteristics: Asymm-

Logic

V. S YMMETRIC - G AND A SYMMETRIC L ATCHES AND F LIP - FLOPS

FinFET

Fig. 25 shows the leakagedelay characteristics of the Asymm- G gates compared to their corresponding SymmG SG-mode counterparts as well as IGn-INV and XT2-NAND2 gates, which were the best Symm- G gates. a-SG-INV gates are 60% slower than their SG-INV counterparts, with average leakage that is 238 lower, while a-SG-NAND2 gates are 65% slower than SG-NAND2 gates, with 235 lower leakage. (a-SG- NOR2, a-SG-XOR2, and a-SG-XNOR2) gates had (234, 206, and 234) lower average leakage compared to (SG-NOR2, SG-XOR2, and SGXNOR2) with (34%, 20%, and 10%) higher delay, respectively. The NAND2S gate, which introduces a Symm- G SG-mode n-FinFET to reduce delay, has SG- NAND2-like leakage for the 10 vector, thereby increasing overall average ILEAK . From Fig. 25, it is also clear that the best IG-mode congurations such as IGn-INV and XT2-NAND2 are not as well placed as their a-SG-mode counterparts in the leakagedelay spectrum.

Next, we investigate simple latches and ip-ops that leverage combinations of Symm- G and Asymm- G FinFETs, using insights from earlier sections. We modied four template congurations, namely, the brute-force transmission gate [TGL, Fig. 26(b)] and half-swing clocked FinFET latches [HSL, Figs. 27 and 28], and the corresponding ip-ops [TGF, Fig. 27 and HSF, Fig. 28], in order to demonstrate the importance of choosing the appropriate kinds of FinFETs to optimize leakage, propagation delay, and setup time. Tables IV and V show the various possible cases of interest for TGL, TGF, HSL, and HSF using SG-, a-SG-, and IG-mode FinFETs along with their n counts. TGL1 and TGF1 have only SG-mode FinFETs, which necessitates a larger I 1 gate in order to overcome I 3 and force the data into the cross-coupled inverter conguration. TGL2 and TGF2 employ a-SG-mode FinFETs to implement a weaker I 3 gate, hence, permitting a smaller I 1 gate. By replacing I 1/I 2 with a-SG-mode FinFETs

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
BHOJ AND JHA: LOGIC GATES AND FLIP-FLOPS DESIGN IN HIGH-PERFORMANCE FinFET TECHNOLOGY 11

14

x 10

12

TABLE IV TG L ATCH AND F LIP -F LOP C ASES , xPyN = x-n p-FinFET, y-n

aSGXOR2 12 Average FO4 delay (s) aSGNOR2 10 aSGNAND2

SGXOR2
Case TGL1

n-FinFET, T2 = SG(1P1N) I 1/I 2 SG 4P2N/2P1N TGL2 TGL3 TGL4 SG a-SG SG 2P1N/2P1N I3 SG 1P1N a-SG a-SG IG 1P1N SG 1P1N a-SG a-SG IG 1P1N T1 SG 2P2N SG SG SG 1P1N SG 2P2N SG SG SG 1P1N I4 SG 1P1N SG a-SG IG 1P1N I5 SG 1P1N a-SG a-SG IG 1P1N I6 SG 2P1N SG a-SG SG 2P1N

XT2NAND2 aSGNAND2S IGnINV SGNOR2

6 aSGXNOR2 4 aSGINV

SGNAND2

SGXNOR2 SGINV

TGF1

SG 4P2N/2P1N

TGF2

SG a-SG SG 2P1N/2P1N

2 11 10

10

10

Average I
Fig. 25.

LEAK

10 (A)

10

TGF3 TGF4

Leakagedelay spectrum for Asymm- G FinFET logic gates.

(a)
Fig. 26.

(b)

FinFET latch templates. (a) TG latch (TGL). (b) HS latch (HSL).

Fig. 27.

TG ip-op (TGF).

Fig. 28.

HS ip-op (HSF).

as well, TGL3 and TGF3 push the limits of operation. TGL4 and TGF4 use IG-mode FinFETs (with n-FinFET back gate tied to ground and p-FinFET back gate tied to VDD ) to weaken I 3.

For the HS latches and ip-ops, HSL1 and HSF1 constitute the base cases with only SG-mode FinFETs. A half-swing clock is employed, which toggles between 0 and VDD /2, thereby reducing dynamic clock power dissipation considerably. However, the switched clock load capacitance doubles, as N1N7 are sized-up to two ns to be able to ip the cross-coupled inverters. Therefore, the effective clock power dissipation is halved with respect to TG congurations using T 1/T 2 gates with single-n FinFETs. (HSL2, HSL3, HSL4) and (HSF2, HSF3, HSF4) introduce a-SG-mode FinFETs at all possible locations except N1, N3, and N7, which are driven by the half-swing clock. HSL5 and HSF5 use IGmode FinFETs (with n-FinFET back gate tied to ground and p-FinFET back gate tied to VDD ) for I 1/I 2 and I 3/I 4. This carries over to HSL6 and HSF6 as well, but N2/N4/N5/N6 are a-SG-mode FinFETs. With respect to layout area, all versions of TGL occupy the same area with standard cell height consisting of four ns for the p-FinFETs and two ns for the n-FinFETs. The same is true for all versions of TGF, HSL, and HSF. Both TGFs and HSFs are negative edge-triggered, for TGL and TGF congurations, when the clock is high, data value D is forced into I 2/I 3 through T 1, while T 2 is off and I 4/I 5 are in the hold mode. When the clock goes low, T 1 shuts off and T 2 forces the value at the output of I 2 into I 4/I 5 for TGF. In HSL (HSF) congurations, when both clock and D are high, Q B (I N B) is pulled low, forcing Q (I N) high. For HSF, when the clock goes low, N7 is active, and depending on the polarity of I N and I N B, Q is pulled either low or high. Table VI shows the hold static noise margins of the cross-coupled inverter pairs used in Tables IV and V. a-SG (1P1N) outperforms the rest of the congurations, including IG (1P1N), suggesting that a-SG-mode FinFETs are ideal for keeper inverters in latches/ip-ops as well. Quasistationary/dc simulations were used to measure average leakage over all possible legal combinations of

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
12 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

TABLE V HS L ATCH AND F LIP -F LOP C ASES , xPyN = x-n p-FinFET, y-n n-FinFET, N1/N3/N7 = SG(2N), I5 = SG(2P1N)

x 10

HSF1 HSF5

Case HSL1 HSL2 HSL3 HSL4 HSL5 HSL6 HSF1 HSF2 HSF3 HSF4 HSF5 HSF6

I 1/I 2 SG SG a-SG a-SG IG IG 1P1N/1P1N SG SG a-SG a-SG IG IG 1P1N/1P1N

N 2/N 4 SG a-SG SG a-SG SG a-SG 2N/2N SG a-SG a-SG SG SG a-SG 2N/2N

I 3/I 4 SG SG a-SG a-SG IG IG 1P1N/1P1N

N 5/N 6 SG a-SG a-SG SG SG a-SG 2N/2N


6 TGF1
Average ILEAK (A)

HSF2 TGF4

HSF4

HSF6

TGF2 HSF3

TGF3

10

TABLE VI H OLD S TATIC N OISE M ARGINS , xPyN = x-n p-FinFET, y-n n-FinFET INV1 (SG, 2P1N) (SG, 1P1N) (SG, 2P1N) (a-SG, 2P1N) (a-SG, 2P1N) (a-SG, 1P1N) (IG, 1P1N)
9

Fig. 30.

Average ILEAK for FinFET ip-ops.


11

INV2 (SG, 1P1N) (SG, 1P1N) (IG, 1P1N) (SG, 1P1N) (a-SG, 1P1N) (a-SG, 1P1N) (IG, 1P1N)

SNM (mV) 310 315 325 320 375 400 375

3.5 x 10

TGL3 HSL4 HSL5 HSL6 HSL3

Average propagation delay (s)

2.5 TGL2 2 TGL1 1.5 TGL4 HSL2 HSL1

x 10

HSL1

HSL2 HSL5
0.5

4
(A)

TGL1 HSL6 3 HSL3


0 1 2 3 4 5 6 7 8 9 10

Average I

LEAK

TGL4 TGL2

Fig. 31.
HSL4

Average propagation delay for FinFET latches.

TGL3

10

Fig. 29.

Average ILEAK for FinFET latches.

input/output vectors and internal states. From Fig. 29, TGL3, which employs a-SG-mode FinFETs (except for T 1), can be seen to have over 10 lower leakage than TGL1. Similarly, HSL4, with mostly a-SG-mode FinFETs, has nearly 3

lower leakage compared to HSL1. From Fig. 30, TGF3 and HSF3 can be seen to follow similar trends. The introduction of IG-mode FinFETs results in a marginal reduction in average leakage in (TGL4, TGF4), (HSL5, HSF5), and (HSL6, HSF6). Propagation delay was averaged for 1 0 as well as 0 1 transitions, assuming an output load of four size-X1 SG-INVs for both latches and ip-ops. From Fig. 31, TGL3 can be seen to have nearly 2 larger delay compared to TGL1 owing to the weaker a-SG-mode FinFETs. Similar observations hold good for (HSL1, HSL2) and (HSL3HSL6). However, from Fig. 32, TGF3 and TGF1 can be seen to have almost identical delays. This is due to the fact that forcing data into I 4/I 5 in TGF1, when the clock is low, is harder

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
BHOJ AND JHA: LOGIC GATES AND FLIP-FLOPS DESIGN IN HIGH-PERFORMANCE FinFET TECHNOLOGY
11

13

x 10

TGF4 5 TGF1 Average propagation delay (s) HSF3 HSF4 4 HSF1 HSF2 TGF2 3 TGF3 HSF5 HSF6

mode FinFET conguration, owing to the large I 1 dataforcing inverter. (TGF2, TGF3) and (HSF3, HSF4) have considerably larger setup times, as they employ weaker a-SG-mode FinFETs. Similar trends were also observed for latches. In summary, (TGF3, HSF3), which are implemented using a combination of a-SG-mode and SG-mode FinFETs, have the best tradeoffs in leakage, delay, and setup time for (TG, HS) ip-op congurations. VI. C ONCLUSION

10

Fig. 32.

Average propagation delay for FinFET ip-ops.


11

3.5

x 10

HSF3 HSF4

3 TGF2 TGF3 HSF2 HSF1 HSF5 TGF4 HSF6

2.5 Setup time (s)

2 TGF1 1.5

0.5

Unlike prior fragmented approaches to FinFET logic/sequential circuit design, in this paper, we evaluated Symm- G SG/IG-mode FinFETs and Asymm- G SG-mode FinFETs head to head in a high-performance process. We also investigated the design space of logic gates, latches, and ip-ops employing them in a unied manner, which resulted in the following key insights. 1) Asymm- G SG-mode FinFETs with high-performance targets provide very steep subthreshold slopes, ultralow off-currents, and reasonably high ON-currents in comparison to Symm- G SG/IG-mode FinFETs, and maintain their advantage at high temperature. This suggests that they could be widely used (in combination with Symm- G SG-mode FinFETs when necessary) in off-critical paths, with the same layout as SymmG SG-mode devices and without the routing and process-related problems of integrating IG-mode backgate biased devices. 2) While it is possible to trade off leakage versus delay using IG-mode FinFETs, indiscriminate use of backgate biasing could impact area, performance, and leakage, as IG-mode devices need extra area to land back-gate contacts and have degraded subthreshold slopes. In this regard, using a single IG-mode device at the top of a series stack is sufcient to reduce leakage considerably without too much degradation in delay. R EFERENCES
[1] E. J. Nowak, I. Aller, T. Ludwig, K. Kim, R. V. Joshi, C.-T. Chuang, K. Bernstein, and R. Puri, Turning silicon on its edge, IEEE Circuits Devices Mag., vol. 20, no. 1, pp. 2031, Jan.Feb. 2004. [2] W. Zhang, J. G. Fossum, L. Mathew, and Y. Du, Physical insights regarding design and performance of independent-gate FinFETs, IEEE Trans. Electron Devices, vol. 52, no. 10, pp. 21982206, Oct. 2005. [3] Sentaurus TCAD Manuals. (2008) [Online]. Available: http://www.synopsys.com [4] H. Dadgour, K. Endo, V. De, and K. Banerjee, Modeling and analysis of grain-orientation effects in emerging metal-gate devices and implications for SRAM reliability, in Proc. Int. Electron. Device Meeting, 2008, pp. 705708. [5] K. von Arnim, E. Augendre, A. C. Pacha, T. Schulz, K. T. San, F. Bauer, A. Nackaerts, R. Rooyackers, T. Vandeweyer, B. Degroote, N. Collaert, A. Dixit, R. Singanamalla, W. Xiong, A. Marshall, C. R. Cleavelin, K. Schrufer, and M. Jurczak, A low-power multi-gate FET CMOS technology with 13.9 ps inverter delay, large-scale integrated high performance digital circuits and SRAM, in Proc. Int. Symp. VLSI Technol., 2007, pp. 106107. [6] C. Pacha, K. von Arnim, F. Bauer, T. Schulz, W. Xiong, K. T. San, A. Marshall, T. Baumann, C.-R. Cleavelin, K. Schruefer, and J. Berthold, Efciency of low-power design techniques in multi-gate FET CMOS circuits, in Proc. Eur. Conf. Solid-State Circuits, 2007, pp. 111114.

10

Fig. 33.

Setup time for FinFET ip-ops.

because of the stronger SG-mode keeper FinFETs, thereby increasing the CLK Q delay. The poor leakagedelay behavior for TGF4 suggests that IG-mode FinFETs are best suited for the weaker inverters (I 3/I 5) and should not be used for I 2/I 4 in TGF congurations. For (HSF3HSF6), the introduction of IG/a-SG-mode FinFETs results in roughly 30% increase in average propagation delay with respect to (HSF1, HSF2). The maximum of the setup periods of legal 0 1 and 1 0 output transitions (for corresponding input transitions before the clock edge) is reported as the setup time for ip-ops in Fig. 33. TGF4 has the smallest setup time owing to the IG-mode FinFETs, which weaken I 3. TGF1 has a comparatively low setup time for an all-SG-

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
14 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

[7] A. Muttreja, N. Agarwal, and N. K. Jha, CMOS logic design with independent gate FinFETs, in Proc. Int. Conf. Comput. Design, Oct. 2007, pp. 560567. [8] M. Rostami and K. Mohanram, Dual-Vth independent-gate FinFETs for low power logic circuits, IEEE Trans. Comput.-Aided Design, vol. 30, no. 3, pp. 337349, Mar. 2011. [9] A. Datta, A. Goel, R. T. Cakici, H. Mahmoodi, D. Lakshmanan, and K. Roy, Modeling and circuit synthesis for independently controlled double gate FinFET devices, IEEE Trans. Comput.-Aided Design, vol. 26, no. 11, pp. 19571966, Nov. 2007. [10] S. A. Tawk and V. Kursun, Low-power and compact sequential circuits with independent-gate FinFETs, IEEE Trans. Electron Devices, vol. 55, no. 1, pp. 6070, Jan. 2008. [11] S. Tawk and V. Kursun, Characterization of new static independentgate biased FinFET latches and ip-ops under process variations, in Proc. Int. Symp. Qual. Electron. Design, Mar. 2008, pp. 311316. [12] J. Kedzierski, D. M. Fried, E. J. Nowak, T. Kanarsky, J. H. Rankin, H. Hana, W. Natzle, D. Boyd, Y. Zhang, R. A. Roy, J. Newbury, C. Yu, Q. Yang, P. Saunders, C. P. Willets, A. Johnson, S. P. Cole, H. E. Young, N. Carpenter, D. Rakowski, B. A. Rainey, P. E. Cottrell, M. Ieong, and H.-S. P. Wong, High-performance symmetric-gate and CMOS-compatible Vt asymmetric-gate FinFET devices, in Proc. Int. Electron. Device Meeting, 2001, pp. 19.5.119.5.4. [13] L. Mathew, M. Sadd, B. E. White, A. Vandooren, S. Dakshina-Murthy, J. Cobb, T. Stephens, R. Mora, D. Pham, J. Conner, T. White, Z. Shi, A. V.-Y. Thean, A. Barr, M. Zavala, J. Schaeffer, M. J. Rendon, D. Sing, M. Orlowski, B.-Y. Nguyen, and J. Mogab, FinFET with isolated n+ and p+ gate regions strapped with metal and polysilicon, in Proc. Int. SOI Conf., Nov. 2003, pp. 109110. [14] A. N. Bhoj and N. K. Jha, Design of ultra-low-leakage logic gates and ip-ops in high-performance FinFET technology, in Proc. Int. Symp. Qual. Electron. Design, Mar. 2011, pp. 18. [15] A. N. Bhoj and N. K. Jha, Gated-diode FinFET DRAMs: Device and circuit design considerations, ACM J. Emerg. Technol. Comput. Syst., vol. 6, no. 4, pp. 12:112:32, 2010. [16] D. Ha, H. Takeuchi, Y.-K. Choi, and T.-J. King, Molybdenum gate technology for ultrathin-body MOSFETs and FinFETs, IEEE Trans. Electron Devices, vol. 51, no. 12, pp. 19891996, Dec. 2004. [17] J. Colinge, FinFETs and Other Multi-Gate Transistors. New York: Springer-Verlag, 2008. [18] M. Alioto, Comparative evaluation of layout density in 3T, 4T, and MT FinFET standard cells, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 5, pp. 751762, May 2011.

Ajay N. Bhoj (S07) received the B.Tech. degree from the Indian Institute of Technology, Chennai, India, in 2007, and the M.A. degree from Princeton University, Princeton, NJ, in 2009, where he is currently pursuing the Ph.D. degree, all in electrical engineering. His current research interests include interesting problems in device modeling, simulation of multigate transistors, SRAM/eDRAMs as well as low power digital circuit design, and computer architecture/VLSI implementations of architectural ideas.

Niraj K. Jha (S85M85SM93F98) received the B.Tech. degree in electronics and electrical communication engineering from the Indian Institute of Technology, Kharagpur, India, in 1981, the M.S. degree in electrical engineering from State University of New York at Stony Brook, Stony Brook, in 1982, and the Ph.D. degree in electrical engineering from the University of Illinois at UrbanaChampaign, Urbana, in 1985. He is a Professor of electrical engineering with Princeton University, Princeton, NJ. He has coauthored or co-edited ve books titled the Testing and Reliable Design of CMOS Circuits (Kluwer, 1990), High-Level Power Analysis and Optimization (Kluwer, 1998), Testing of Digital Systems (Cambridge University Press, 2003), Switching and Finite Automata Theory, 3rd edition (Cambridge University Press, 2009), and Nanoelectronic Circuit Design (Springer, 2010). He has authored 12 book chapters. He has authored or co-authored more than 390 technical papers. He has co-authored 14 award-winning papers. He holds 13 U.S. patents. He has given several keynote speeches in the area of nanoelectronic design and test. His current research interests include FinFETs, low power hardware/software design, computer-aided design of integrated circuits and systems, digital system testing, and secure computing. Dr. Jha is a fellow of ACM. He has served as the Editor-in-Chief of the IEEE T RANSACTIONS ON V ERY L ARGE S CALE I NTEGRATION (VLSI) S YSTEMS and an Associate Editor of the IEEE T RANSACTIONS ON C IRCUITS AND S YSTEMS I: R EGULAR PAPERS and the IEEE T RANSACTIONS ON C IRCUITS AND S YSTEMS II: E XPRESS B RIEFS , the IEEE T RANSACTIONS ON C OMPUTER -A IDED D ESIGN OF I NTEGRATED C IRCUITS AND S YSTEMS the IEEE T RANSACTIONS ON V ERY L ARGE S CALE I NTEGRATION (VLSI) S YSTEMS , and the Journal of Electronic Testing: Theory and Applications. He is currently serving as an Associate Editor of the IEEE T RANSACTIONS ON C OMPUTERS , the Journal of Low Power Electronics, and the Journal of Nanotechnology. He has served as the Program Chairman of the 1992 Workshop on Fault-Tolerant Parallel and Distributed Systems, the 2004 International Conference on Embedded and Ubiquitous Computing, and the 2010 International Conference on VLSI Design. He has served as the Director of the Center for Embedded System-on-a-Chip Design funded by the New Jersey Commission on Science and Technology. He is a recipient of the AT&T Foundation Award and NEC Preceptorship Award for research excellence, the NCR Award for Teaching Excellence, and the Princeton University Graduate Mentoring Award. He was a recipient of the Best Paper Award at ICCD93, FTCS97, ICVLSID98, DAC99, PDCS02, ICVLSID03, CODES06, ICCD09, and CLOUD10. His paper was selected for The Best of ICCAD: A Collection of the Best IEEE International Conference on Computer-Aided Design papers of the past 20 years, two papers by IEEE Micro Magazine as one of the top picks from the 2005 and 2007 Computer Architecture Conferences, and two others as being among the most inuential papers of the last ten years at the IEEE Design Automation and Test in Europe Conference. He has co-authored six other papers that have been nominated for Best Paper Awards.