Combination Logic Circuits

In general form , a combination logic circuit, or gate,

performing a Boolean function can be represented as a
multiple-input, single-output system
Two input NMOS NOR Gate

Assuming VGS,K = VGS for k=1,2,3….,n

 NOR Gate (contd.)

Equivalent inverter circuit

Generalized n-input NOR gate corresponding to n-input NOR gate

A multiple-input NOR gate can also be reduced to equivalent inverter shown for static analysis
Two input NMOS NAND Gate
 NAND Gate (contd.)

Equivalent inverter circuit

corresponding to n-input NAND gate
Generalized n-input NAND gate
 Two input CMOS NOR Gate

Either the nMOS network (n-net) is on and pMOS is off,

or the pMOS network (p-net)is on and the nMOS network
is off.
 CMOS NOR Gate (contd.)

Inverter equivalent of CMOS Nor gate

Note that the length of the pMOS transistor is doubled whereas the
width of the nMOS transistor is doubled.
 Two input CMOS NAND Gate

Inverter equivalent of CMOS NAND gate

Note that the width of the pMOS transistor is doubled whereas the
length of the nMOS transistor is doubled.
 Complex logic circuits
Q. Realize the following Boolean function using nMOS logic & Determine
the equivalent W/L factor.
Z = A(D+E)+BC
 Complex logic circuits (contd.)
Q. Realize the following Boolean function using CMOS logic.
Z = A(D+E)+BC
 XOR Gate

Note that two additional inverters are also needed to obtain the inverse of both
input variables. With these inverters, the CMOS XOR circuit requires total of 12
transistors
 AND OR INVERT Gates (AOI)

Sum of products realization of Boolean function in one logic stage

 OR AND INVERT Gate(OAI)

Product of sums realization of Boolean function in one logic stage

 Pseudo – nMOS Gates
The problem of high density design in complex CMOS gates is over come by
Pseudo nMOS. In this logic a single pMOS transistor(with gate tied to ground) is
used instead of pMOS Pull up network of CMOS.
Since the channel sheet resistance of p-pull up is
about 2.5 times that of a n-pull down, the pseudo
MOS circuit offers more resistance as compared to 4:1
nMOS device. Thus power dissipation is reduced
tremendously.
The most significant disadvantage of using Pseudo
nMOS is the non zero static power dissipation, since
always-on pMOS load device conducts a steady state
current when output voltage is lower than VDD.

Owing to higher pull up resistance, the inverter pair

delay is larger than that of 4:1 minimum size nMOS
inverter.
 Dynamic CMOS logic
To overcome the disadvantage of pseudo nMOS logic, dynamic logic
CMOS is developed.
When p-transistor is on it is called pre-charging the output node
capacitance and when n-transistor is on it is called evaluating the output
level according to the applied inputs
 Dynamic CMOS logic problems
• Charge sharing may be the problem unless the
inputs are constrained not to change during
the on period of the clock.
• Single phase dynamic logic structures cannot
be cascaded since, owing to circuit delay, an
incorrect input to the next stage may be
present when evaluation begins, so that its
output is instantly discharged and wrong
output results.
 CMOS Domino Logic
To achieve reliable , high speed, compact circuits, using the least complicated clocking
scheme possible some modification is done in dynamic logic, an inverter is inserted
between two cascaded stages. The logic thus developed is called domino logic
 CMOS Domino Logic (contd.)
The problem in cascading conventional dynamic CMOS stages occurs when one or
more inputs of a stage makes a 1 to 0 transition during evaluation phase.
Whereas cascading domino CMOS, all input transistors in subsequent logic blocks
will be turned off during pre-charge phase, since all buffer output are 0.
 CMOS Transmission Gate
Transmission gate (TG) also called Pass Gate consists of one nMOS & one pMOS
transistor, connected in parallel.

If the control signal C is

logic-high, then both
transistors are turned
on a, providing a low-
resistance current path
between the node A&B.
MUX using Pass Gate

Operation: if the control

input S is logic-high,
then the bottom TG will
conduct, and the output
will be equal to B. If the
control signal is low, the
bottom TG will turn off
and the top TG will
connect the input A to
the output node.
 XOR Gate using Pass Gate

Eight transistor implementation of the logic XOR function, using two CMOS TGs and two
inverters