GATE LEVEL SIMULATION

What is GLS??
Gate level to present your circuit with

target library after synthesis.

Simulation is a design validation process for

checking a circuits function, timing.

Why we use GLS?

To check if reset release, initialization

sequence are proper. Insertion of scan chains. STA never the functionality of the design Checks IF you have any un-initialized outputs. Checks IF the design works at the targeted FREQUENCY. Checks IF you have any timing violations.

Requirements for GLS

Gate Level Netlist Gate Level Simulation Library SDF (Standard Delay Format) Test bench For Gate Level Simulation

TYPES OF SIMULATIONS

ZERO DELAY SIMULATION (Without SDF).

SIMULATION WITH SDF (Standard Delay

Format).

ZERO DELAY SIMULATION

Gate Level Simulation Without DELAY. Check Only Functionality NOT Frequency. Check Mapping Of RTL To Gates. Much Easier To Debug.

SIMULATION WITH SDF.

Gate Level Simulation With DELAY. SDF File Includes All The Delay For Gates. Check Functionality At Given Frequency. Identify Timing Issues. Check Multicycle Path. Check False Path.

Problems with GLS

Simulation Time. Gate Level Debug.

Thank you!

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