Practical Examination Quiz (Digital Electronic Lab) Set3

Max Mks: 10 Univ. Roll No (in fig.) : Univ. Roll No (in words.) : Subject: Code: Signature of Student: (To be filled by examiners) Marks Obtained: Grade Obtained: Time: 10 mins

Date of Examination: Day:

Signature of Internal Examiner

Signature of External

Examiner

Q1.Sum of A and B I a half adder can be implemented by using k NAND gates.value of k is a.3 b.4 c.5 d.none Q2.no of bits required for representing 35 in binary is a.6 b.5 c.4 d.33 Q3.In 2s compliment N is written as 1011.+N is written as a.0100 b.0101 c.0110 d.0011 Q4.What is O/P Z of an Ex-OR gate ,whose all input are set at 1 a.Z=A b.Z=1 c.Z=0 Q5.Expression for sum A,B in half adder is given by a.AB b.A+B c.A+B d.none Q6.1s compliment of 1101 is a.1101 b.0010 c.0000 d.0011 Q7.Which flip flop is used as a latch a.JK b.D c.RS d.T Q8.A gate in which all I/P must be low to get a high o/p is called a.inverter b.NOR c.AND d.NAND Q9.a 4 bit no is given as 0110.its 2 compliment is a.1001 b.1000 c.1010 d.none Q10.Value of binary 1111 is a.23-1 b.24-1 c24 d.none