D Flip Flop module dflipflop(D,Q,clk,clr); output Q; reg Q; input D; input clk,clr; always @(posedge clk) begin if(clr) Q<=1'b0;

else Q<=D; end endmodule JK Flip Flop module jk_ff(q,j,k,clr,clk); input j,k; input clr,clk; output q; reg q; always @(posedge clk or posedge clr) begin if(clr) q<=1'b0; else begin if(!j) begin if(k) q<=1'b0; else q<=q; end else begin if(!k) q<=1'b1; else q<=!q; end end end endmodule

Modulo 10 Counter module mod10counter(Q,clk,rst); parameter n=4; input clk,rst; output [n-1:0]Q; reg [n-1:0]Q; always @(posedge clk or posedge rst) begin if(rst==1) Q<=4'b0; else if (Q==9) Q<= 4'b0; else Q<=Q+1; end endmodule Ring Counter module ringcounter(count, enable, clock, reset); output [7:0] count; input enable, reset, clock; reg count; always @ (posedge reset or clock) if(reset==1'b1) count <= 8'b0000_0001; else if(enable==1'b1) count <= {count[6:0],count[7]}; endmodule Shift register module sh_reg(ip,direction,clk,op); parameter size = 4; input ip,clk,direction; output [size-1:0] op; reg [size-1:0] temp; always @ (posedge clk) //If dir == 1 , makes left shift else right shift if(direction)

temp <= {temp[size-2:0],ip}; else temp <= {ip,temp[size-1:1]}; assign op = temp; endmodule SR FLIP FLOP module srflipflop(q,q1,r,s,clk); output q,q1; input r,s,clk; reg q,q1; initial begin q=1'b0; q1=1'b1; end always @(posedge clk) begin case({s,r}) {1'b0,1'b0}: begin q=q; q1=q1; end {1'b0,1'b1}: begin q=1'b0; q1=1'b1; end {1'b1,1'b0}: begin q=1'b1; q1=1'b0; end {1'b1,1'b1}: begin q=1'bx; q=1'bx; end endcase end endmodule T FLIP FLOP module tflipflop(q,t,clk,clr); output q; input t; input clr,clk; reg q; always @(posedge clk or posedge clr) begin if(clr) q<=1'b0; else q<=!t; end endmodule