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Copyright (C) 1991-2009 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. "Quartus II" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web "Tue Nov 06 18:53:05 2012"

-- PROGRAM -- VERSION Edition" -- CREATED ON

LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY work; ENTITY divfreq IS PORT ( CLK : IN STD_LOGIC; CLOCK : OUT STD_LOGIC ); END divfreq; ARCHITECTURE bdf_type OF divfreq IS SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL BEGIN SYNTHESIZED_WIRE_64 : STD_LOGIC; TFF_inst : STD_LOGIC; TFF_inst9 : STD_LOGIC; TFF_inst10 : STD_LOGIC; TFF_inst11 : STD_LOGIC; TFF_inst12 : STD_LOGIC; TFF_inst13 : STD_LOGIC; TFF_inst14 : STD_LOGIC; SYNTHESIZED_WIRE_65 : STD_LOGIC; TFF_inst16 : STD_LOGIC; TFF_inst17 : STD_LOGIC; TFF_inst18 : STD_LOGIC; TFF_inst1 : STD_LOGIC; TFF_inst19 : STD_LOGIC; TFF_inst20 : STD_LOGIC; TFF_inst21 : STD_LOGIC; TFF_inst2 : STD_LOGIC; TFF_inst3 : STD_LOGIC; TFF_inst4 : STD_LOGIC; TFF_inst5 : STD_LOGIC; TFF_inst6 : STD_LOGIC; TFF_inst7 : STD_LOGIC; TFF_inst8 : STD_LOGIC;

SYNTHESIZED_WIRE_64 <= '1';

PROCESS(CLK,SYNTHESIZED_WIRE_64,SYNTHESIZED_WIRE_64) VARIABLE TFF_inst_synthesized_var : STD_LOGIC; BEGIN IF (SYNTHESIZED_WIRE_64 = '0') THEN TFF_inst_synthesized_var := '0'; ELSIF (SYNTHESIZED_WIRE_64 = '0') THEN TFF_inst_synthesized_var := '1'; ELSIF (RISING_EDGE(CLK)) THEN TFF_inst_synthesized_var := TFF_inst_synthesized_var XOR SYNTHESIZED_WIR E_64; END IF; TFF_inst <= TFF_inst_synthesized_var; END PROCESS; PROCESS(TFF_inst,SYNTHESIZED_WIRE_64,SYNTHESIZED_WIRE_64) VARIABLE TFF_inst1_synthesized_var : STD_LOGIC; BEGIN IF (SYNTHESIZED_WIRE_64 = '0') THEN TFF_inst1_synthesized_var := '0'; ELSIF (SYNTHESIZED_WIRE_64 = '0') THEN TFF_inst1_synthesized_var := '1'; ELSIF (RISING_EDGE(TFF_inst)) THEN TFF_inst1_synthesized_var := TFF_inst1_synthesized_var XOR SYNTHESIZED_W IRE_64; END IF; TFF_inst1 <= TFF_inst1_synthesized_var; END PROCESS; PROCESS(TFF_inst9,SYNTHESIZED_WIRE_64,SYNTHESIZED_WIRE_64) VARIABLE TFF_inst10_synthesized_var : STD_LOGIC; BEGIN IF (SYNTHESIZED_WIRE_64 = '0') THEN TFF_inst10_synthesized_var := '0'; ELSIF (SYNTHESIZED_WIRE_64 = '0') THEN TFF_inst10_synthesized_var := '1'; ELSIF (RISING_EDGE(TFF_inst9)) THEN TFF_inst10_synthesized_var := TFF_inst10_synthesized_var XOR SYNTHESIZED _WIRE_64; END IF; TFF_inst10 <= TFF_inst10_synthesized_var; END PROCESS; PROCESS(TFF_inst10,SYNTHESIZED_WIRE_64,SYNTHESIZED_WIRE_64) VARIABLE TFF_inst11_synthesized_var : STD_LOGIC; BEGIN IF (SYNTHESIZED_WIRE_64 = '0') THEN TFF_inst11_synthesized_var := '0'; ELSIF (SYNTHESIZED_WIRE_64 = '0') THEN TFF_inst11_synthesized_var := '1'; ELSIF (RISING_EDGE(TFF_inst10)) THEN TFF_inst11_synthesized_var := TFF_inst11_synthesized_var XOR SYNTHESIZED _WIRE_64; END IF;

TFF_inst11 <= TFF_inst11_synthesized_var; END PROCESS; PROCESS(TFF_inst11,SYNTHESIZED_WIRE_64,SYNTHESIZED_WIRE_64) VARIABLE TFF_inst12_synthesized_var : STD_LOGIC; BEGIN IF (SYNTHESIZED_WIRE_64 = '0') THEN TFF_inst12_synthesized_var := '0'; ELSIF (SYNTHESIZED_WIRE_64 = '0') THEN TFF_inst12_synthesized_var := '1'; ELSIF (RISING_EDGE(TFF_inst11)) THEN TFF_inst12_synthesized_var := TFF_inst12_synthesized_var XOR SYNTHESIZED _WIRE_64; END IF; TFF_inst12 <= TFF_inst12_synthesized_var; END PROCESS; PROCESS(TFF_inst12,SYNTHESIZED_WIRE_64,SYNTHESIZED_WIRE_64) VARIABLE TFF_inst13_synthesized_var : STD_LOGIC; BEGIN IF (SYNTHESIZED_WIRE_64 = '0') THEN TFF_inst13_synthesized_var := '0'; ELSIF (SYNTHESIZED_WIRE_64 = '0') THEN TFF_inst13_synthesized_var := '1'; ELSIF (RISING_EDGE(TFF_inst12)) THEN TFF_inst13_synthesized_var := TFF_inst13_synthesized_var XOR SYNTHESIZED _WIRE_64; END IF; TFF_inst13 <= TFF_inst13_synthesized_var; END PROCESS; PROCESS(TFF_inst13,SYNTHESIZED_WIRE_64,SYNTHESIZED_WIRE_64) VARIABLE TFF_inst14_synthesized_var : STD_LOGIC; BEGIN IF (SYNTHESIZED_WIRE_64 = '0') THEN TFF_inst14_synthesized_var := '0'; ELSIF (SYNTHESIZED_WIRE_64 = '0') THEN TFF_inst14_synthesized_var := '1'; ELSIF (RISING_EDGE(TFF_inst13)) THEN TFF_inst14_synthesized_var := TFF_inst14_synthesized_var XOR SYNTHESIZED _WIRE_64; END IF; TFF_inst14 <= TFF_inst14_synthesized_var; END PROCESS; PROCESS(TFF_inst14,SYNTHESIZED_WIRE_64,SYNTHESIZED_WIRE_64) VARIABLE SYNTHESIZED_WIRE_65_synthesized_var : STD_LOGIC; BEGIN IF (SYNTHESIZED_WIRE_64 = '0') THEN SYNTHESIZED_WIRE_65_synthesized_var := '0'; ELSIF (SYNTHESIZED_WIRE_64 = '0') THEN SYNTHESIZED_WIRE_65_synthesized_var := '1'; ELSIF (RISING_EDGE(TFF_inst14)) THEN SYNTHESIZED_WIRE_65_synthesized_var := SYNTHESIZED_WIRE_65_synthesized_v ar XOR SYNTHESIZED_WIRE_64; END IF;

SYNTHESIZED_WIRE_65 <= SYNTHESIZED_WIRE_65_synthesized_var; END PROCESS; PROCESS(SYNTHESIZED_WIRE_65,SYNTHESIZED_WIRE_64,SYNTHESIZED_WIRE_64) VARIABLE TFF_inst16_synthesized_var : STD_LOGIC; BEGIN IF (SYNTHESIZED_WIRE_64 = '0') THEN TFF_inst16_synthesized_var := '0'; ELSIF (SYNTHESIZED_WIRE_64 = '0') THEN TFF_inst16_synthesized_var := '1'; ELSIF (RISING_EDGE(SYNTHESIZED_WIRE_65)) THEN TFF_inst16_synthesized_var := TFF_inst16_synthesized_var XOR SYNTHESIZED _WIRE_64; END IF; TFF_inst16 <= TFF_inst16_synthesized_var; END PROCESS; PROCESS(TFF_inst16,SYNTHESIZED_WIRE_64,SYNTHESIZED_WIRE_64) VARIABLE TFF_inst17_synthesized_var : STD_LOGIC; BEGIN IF (SYNTHESIZED_WIRE_64 = '0') THEN TFF_inst17_synthesized_var := '0'; ELSIF (SYNTHESIZED_WIRE_64 = '0') THEN TFF_inst17_synthesized_var := '1'; ELSIF (RISING_EDGE(TFF_inst16)) THEN TFF_inst17_synthesized_var := TFF_inst17_synthesized_var XOR SYNTHESIZED _WIRE_64; END IF; TFF_inst17 <= TFF_inst17_synthesized_var; END PROCESS; PROCESS(TFF_inst17,SYNTHESIZED_WIRE_64,SYNTHESIZED_WIRE_64) VARIABLE TFF_inst18_synthesized_var : STD_LOGIC; BEGIN IF (SYNTHESIZED_WIRE_64 = '0') THEN TFF_inst18_synthesized_var := '0'; ELSIF (SYNTHESIZED_WIRE_64 = '0') THEN TFF_inst18_synthesized_var := '1'; ELSIF (RISING_EDGE(TFF_inst17)) THEN TFF_inst18_synthesized_var := TFF_inst18_synthesized_var XOR SYNTHESIZED _WIRE_65; END IF; TFF_inst18 <= TFF_inst18_synthesized_var; END PROCESS; PROCESS(TFF_inst18,SYNTHESIZED_WIRE_64,SYNTHESIZED_WIRE_64) VARIABLE TFF_inst19_synthesized_var : STD_LOGIC; BEGIN IF (SYNTHESIZED_WIRE_64 = '0') THEN TFF_inst19_synthesized_var := '0'; ELSIF (SYNTHESIZED_WIRE_64 = '0') THEN TFF_inst19_synthesized_var := '1'; ELSIF (RISING_EDGE(TFF_inst18)) THEN TFF_inst19_synthesized_var := TFF_inst19_synthesized_var XOR SYNTHESIZED _WIRE_65; END IF;

TFF_inst19 <= TFF_inst19_synthesized_var; END PROCESS; PROCESS(TFF_inst1,SYNTHESIZED_WIRE_64,SYNTHESIZED_WIRE_64) VARIABLE TFF_inst2_synthesized_var : STD_LOGIC; BEGIN IF (SYNTHESIZED_WIRE_64 = '0') THEN TFF_inst2_synthesized_var := '0'; ELSIF (SYNTHESIZED_WIRE_64 = '0') THEN TFF_inst2_synthesized_var := '1'; ELSIF (RISING_EDGE(TFF_inst1)) THEN TFF_inst2_synthesized_var := TFF_inst2_synthesized_var XOR SYNTHESIZED_W IRE_64; END IF; TFF_inst2 <= TFF_inst2_synthesized_var; END PROCESS; PROCESS(TFF_inst19,SYNTHESIZED_WIRE_64,SYNTHESIZED_WIRE_64) VARIABLE TFF_inst20_synthesized_var : STD_LOGIC; BEGIN IF (SYNTHESIZED_WIRE_64 = '0') THEN TFF_inst20_synthesized_var := '0'; ELSIF (SYNTHESIZED_WIRE_64 = '0') THEN TFF_inst20_synthesized_var := '1'; ELSIF (RISING_EDGE(TFF_inst19)) THEN TFF_inst20_synthesized_var := TFF_inst20_synthesized_var XOR SYNTHESIZED _WIRE_65; END IF; TFF_inst20 <= TFF_inst20_synthesized_var; END PROCESS; PROCESS(TFF_inst20,SYNTHESIZED_WIRE_64,SYNTHESIZED_WIRE_64) VARIABLE TFF_inst21_synthesized_var : STD_LOGIC; BEGIN IF (SYNTHESIZED_WIRE_64 = '0') THEN TFF_inst21_synthesized_var := '0'; ELSIF (SYNTHESIZED_WIRE_64 = '0') THEN TFF_inst21_synthesized_var := '1'; ELSIF (RISING_EDGE(TFF_inst20)) THEN TFF_inst21_synthesized_var := TFF_inst21_synthesized_var XOR SYNTHESIZED _WIRE_65; END IF; TFF_inst21 <= TFF_inst21_synthesized_var; END PROCESS; PROCESS(TFF_inst21,SYNTHESIZED_WIRE_64,SYNTHESIZED_WIRE_64) VARIABLE CLOCK_synthesized_var : STD_LOGIC; BEGIN IF (SYNTHESIZED_WIRE_64 = '0') THEN CLOCK_synthesized_var := '0'; ELSIF (SYNTHESIZED_WIRE_64 = '0') THEN CLOCK_synthesized_var := '1'; ELSIF (RISING_EDGE(TFF_inst21)) THEN CLOCK_synthesized_var := CLOCK_synthesized_var XOR SYNTHESIZED_WIRE_65; END IF; CLOCK <= CLOCK_synthesized_var;

END PROCESS;

PROCESS(TFF_inst2,SYNTHESIZED_WIRE_64,SYNTHESIZED_WIRE_64) VARIABLE TFF_inst3_synthesized_var : STD_LOGIC; BEGIN IF (SYNTHESIZED_WIRE_64 = '0') THEN TFF_inst3_synthesized_var := '0'; ELSIF (SYNTHESIZED_WIRE_64 = '0') THEN TFF_inst3_synthesized_var := '1'; ELSIF (RISING_EDGE(TFF_inst2)) THEN TFF_inst3_synthesized_var := TFF_inst3_synthesized_var XOR SYNTHESIZED_W IRE_64; END IF; TFF_inst3 <= TFF_inst3_synthesized_var; END PROCESS; PROCESS(TFF_inst3,SYNTHESIZED_WIRE_64,SYNTHESIZED_WIRE_64) VARIABLE TFF_inst4_synthesized_var : STD_LOGIC; BEGIN IF (SYNTHESIZED_WIRE_64 = '0') THEN TFF_inst4_synthesized_var := '0'; ELSIF (SYNTHESIZED_WIRE_64 = '0') THEN TFF_inst4_synthesized_var := '1'; ELSIF (RISING_EDGE(TFF_inst3)) THEN TFF_inst4_synthesized_var := TFF_inst4_synthesized_var XOR SYNTHESIZED_W IRE_64; END IF; TFF_inst4 <= TFF_inst4_synthesized_var; END PROCESS; PROCESS(TFF_inst4,SYNTHESIZED_WIRE_64,SYNTHESIZED_WIRE_64) VARIABLE TFF_inst5_synthesized_var : STD_LOGIC; BEGIN IF (SYNTHESIZED_WIRE_64 = '0') THEN TFF_inst5_synthesized_var := '0'; ELSIF (SYNTHESIZED_WIRE_64 = '0') THEN TFF_inst5_synthesized_var := '1'; ELSIF (RISING_EDGE(TFF_inst4)) THEN TFF_inst5_synthesized_var := TFF_inst5_synthesized_var XOR SYNTHESIZED_W IRE_64; END IF; TFF_inst5 <= TFF_inst5_synthesized_var; END PROCESS; PROCESS(TFF_inst5,SYNTHESIZED_WIRE_64,SYNTHESIZED_WIRE_64) VARIABLE TFF_inst6_synthesized_var : STD_LOGIC; BEGIN IF (SYNTHESIZED_WIRE_64 = '0') THEN TFF_inst6_synthesized_var := '0'; ELSIF (SYNTHESIZED_WIRE_64 = '0') THEN TFF_inst6_synthesized_var := '1'; ELSIF (RISING_EDGE(TFF_inst5)) THEN TFF_inst6_synthesized_var := TFF_inst6_synthesized_var XOR SYNTHESIZED_W IRE_64; END IF;

TFF_inst6 <= TFF_inst6_synthesized_var; END PROCESS; PROCESS(TFF_inst6,SYNTHESIZED_WIRE_64,SYNTHESIZED_WIRE_64) VARIABLE TFF_inst7_synthesized_var : STD_LOGIC; BEGIN IF (SYNTHESIZED_WIRE_64 = '0') THEN TFF_inst7_synthesized_var := '0'; ELSIF (SYNTHESIZED_WIRE_64 = '0') THEN TFF_inst7_synthesized_var := '1'; ELSIF (RISING_EDGE(TFF_inst6)) THEN TFF_inst7_synthesized_var := TFF_inst7_synthesized_var XOR SYNTHESIZED_W IRE_64; END IF; TFF_inst7 <= TFF_inst7_synthesized_var; END PROCESS; PROCESS(TFF_inst7,SYNTHESIZED_WIRE_64,SYNTHESIZED_WIRE_64) VARIABLE TFF_inst8_synthesized_var : STD_LOGIC; BEGIN IF (SYNTHESIZED_WIRE_64 = '0') THEN TFF_inst8_synthesized_var := '0'; ELSIF (SYNTHESIZED_WIRE_64 = '0') THEN TFF_inst8_synthesized_var := '1'; ELSIF (RISING_EDGE(TFF_inst7)) THEN TFF_inst8_synthesized_var := TFF_inst8_synthesized_var XOR SYNTHESIZED_W IRE_64; END IF; TFF_inst8 <= TFF_inst8_synthesized_var; END PROCESS; PROCESS(TFF_inst8,SYNTHESIZED_WIRE_64,SYNTHESIZED_WIRE_64) VARIABLE TFF_inst9_synthesized_var : STD_LOGIC; BEGIN IF (SYNTHESIZED_WIRE_64 = '0') THEN TFF_inst9_synthesized_var := '0'; ELSIF (SYNTHESIZED_WIRE_64 = '0') THEN TFF_inst9_synthesized_var := '1'; ELSIF (RISING_EDGE(TFF_inst8)) THEN TFF_inst9_synthesized_var := TFF_inst9_synthesized_var XOR SYNTHESIZED_W IRE_64; END IF; TFF_inst9 <= TFF_inst9_synthesized_var; END PROCESS; END bdf_type;