1

ESE 570 SEMICONDUCTOR MEMORIES

Kenneth R. Laker, University of Pennsylvania

 2

Semiconductor Memories

Read/Write (R/W) Memory

Read-only Memory (ROM) or Random Access Memory (ROM)

1. Mask programmed
2. Programmable ROM (PROM) Static RAM Dynamic RAM
b. Fuse ROM (SRAM) (DRAM)
a. Erasable PROM (EPROM)
c. Electrically Erasable PROM
(EEPROM)
d. Flash Memory
e. Ferroelectric RAM (FRAM)
Kenneth R. Laker, University of Pennsylvania
 3

MEMORY DEVICE CHARACTERISTICS

DRAM SRAM UV EPROM EEPROM FLASH FRAM

Data volatility Yes Yes No No No No
Data Refresh Op Required No No No No No
Cell Structure 1T-1C 6T 1T 2T 1T (2 G) 1T-1C
Cell Density High Low High Low High High
Power Consm High High/low High Low Low High
Read Speed ≈50ns ≈10/70ns ≈50ns ≈50ns ≈50ns ≈100ns
Write Speed ≈40ns ≈5/40ns ≈10µs ≈5ms ≈10µs-1ms ≈100ns
Cost per Bit Low High Low High Low Low
Application Ex Main Cashe/PDAs Game ID Card Memory Smart
Memory Machines Card, Card,
Solid-State Digital
Disk Camera

Kenneth R. Laker, University of Pennsylvania

 TYPICAL RANDOM ACCESS MEMORY ARRAY ORGANIZATION 4

BIT LINES (2M)

Col 1 Col 2 Col 2M
A1
A2 Row 1
A3
Row 2
MEMORY
CELL
2N x 2M cells

Row 2N
AN
Memory
DATA DATA LINE CONTROL CKTS
Block
COLUMN ADDRESS DECODER
CHIP
CNTL I/O B1 B2 B3 BM
N+M
COLUMN ADDRESS BITS
Kenneth R. Laker, University of Pennsylvania
 ROM CIRCUITS 4 X 4 BIT NOR BASED ROM ARRAY 5

VDD VDD VDD VDD

WORD BIT
LINES LINES
R1 R2 R3 R4 C1 C2 C3 C4
R1 1 0 0 0 0 1 0 1
0 1 0 0 0 0 1 1
0 0 1 0 1 0 0 1
R2 0 0 0 1 0 1 1 0
default “0” default “1”
All word lines Ri are kept
R3 at logic “0” level, except
the selected line is pulled
up to “1” level.

R4 Absent Xstr => store “1”

Present Xstr => store “0”

C1 C2 C3 C4
Kenneth R. Laker, University of Pennsylvania
 6

LAYOUT OF CONTACT - MASK PROGRAMMABLE NOR ROM

metal column
(bit) lines to
poly row load devices metal metal
(word)
lines
poly
R1
diffusion
to GND
R2 poly

To Outputs contact NO contact

(0 bit) (1 bit)

Kenneth R. Laker, University of Pennsylvania

 7

R1 LAYOUT OF CONTACT -MASK

PROGRAMMABLE 4 X 4 BIT NOR ROM
R2

R3

R4 metal metal metal metal

C1 C2 C3 C4
R1 poly

diffusion to GND
R2 poly
metal-diff
contact
R3 poly

diffusion to GND
R4 poly

Kenneth R. Laker, University of Pennsylvania

C1 C2 C3 C4
 IMPLANT - MASK PROGRAMMABLE NOR ROM ARRAY 8

Absent Xstr => store “1”

Present Xstr => store “0”
metal columns (bit)

poly
rows (word)

threshold voltage implant to activate 1 bit

VT0 > VDD
permanent OFF transistor <=> contact disconnect
Kenneth R. Laker, University of Pennsylvania
 4 X 4 BIT NAND BASED ROM ARRAY 9

VDD VDD VDD VDD

WORD BIT
C1 C2 C3 C4
LINES LINES
R1 R1 R2 R3 R4 C1 C2 C3 C4
0 1 1 1 0 1 0 1
1 0 1 1 0 0 1 1
R2 1 1 0 1 1 0 0 1
1 1 1 0 0 1 1 0
default “1” default “0”

R3 All word lines are kept at

logic “1” level, except the
selected line is pulled
R4 down by “0” level.
Absent Xstr => store “0”
Kenneth R. Laker, University of Pennsylvania
Present Xstr => store “1”
 10

IMPLANT - MASK PROGRAMMABLE 4 X 4 BIT NAND ROM LAYOUT

VDD Absent Xstr => store “0” (short)
Present Xstr => store “1”
diffusion to LOAD devices
C1 C2 C3 C4
C1 C2 C3 C4
R1
poly
R2 R1

R3
poly
R4 R2

poly
R3

poly
R4

diffusion to GND
threshold voltage
implant to make VT0
Kenneth R. Laker, University of Pennsylvania negative to store “0”
 DESIGN OF ROW AND COLUMN DECODERS 11

ROW ADDRESS DECODER FOR 2 ADDRESS

BITS AND 4 WORD LINES EXAMPLE

RA1 R1
ROW R2
DECODER R3
RA2 R4

RA1 RA2 R1 R2 R3 R4
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
2 address bits plus Select 1 of 4 rows or
complements word lines

Kenneth R. Laker, University of Pennsylvania

 NOR BASED IMPLEMENTATION FOR A 12

ROW DECODER WITH 2 ADDRESS BITS

AND 4 WORD LINES VDD

R1
VDD
off off
(2N) nMOS + (N )pMOS =
(2N + N) Xstrs
R2
VDD PLUS 2N INVERTERS
on off

R3
VDD
off on

R4
0 0
on on For N = 2
RA2 1 RA1 1 RA1 RA2 R1 R2 R3 R4
0 0 1 0 0 0
0 0 1 0 1 0 0
0
RA2 RA1 1 0 0 0 1 0
Kenneth R. Laker, University of Pennsylvania
1 1 0 0 0 1
 13
REALIZATION OF ROW DECODER AND ROM ARRAY AS
TWO ADJACENT NOR PLANES
2N ROWS (WORD LINES)
R1
R2
NOR ROW NOR ROM
DECODER ARRAY
R2N

RA1 RA2 RAN C1 C2 C2M

N ROW ADDRESS BITS 2M COLUMNS (BIT LINES)

For N = 2
RA1 RA2 R1 R2 R3 R4
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
Kenneth R. Laker, University of Pennsylvania 1 1 0 0 0 1
 REALIZATION OF ROW DECODER AND ROM ARRAY AS 14

TWO ADJACENT NAND PLANES

2N ROWS (WORD LINES)
R1
NAND R2 NAND
ROW ROM
DECODER ARRAY
R2N

RA1 RA2 RAN C1 C2 C2M

N ROW ADDRESS BITS 2M COLUMNS (BIT LINES)
RA1 RA2 R1 R2 R3 R4
0 0 0 1 1 1 ROW DECODER
0 1 1 0 1 1 TRUTH TABLE
1 0 1 1 0 1 FOR A 4X4 NAND
1 1 1 1 1 0 ROM ARRAY

Kenneth R. Laker, University of Pennsylvania

 COLUMN DECODER SCHEME USING NOR ADDRESS 15

DECODER AND nMOS PASS TRANSISTORS

ROM ARRAY

C1
CA1 NOR
C2 2M pass
CA2 COLUMN transistors
ADDRESS C3
DECODER
(2M+M)Transistors

CAM C2M

M column DATA
address bits SAME AS ROW OUTPUT
DECODER serial (as
shown)
Kenneth R. Laker, University of Pennsylvania
COLUMN DECODER FOR 8 BIT LINES IMPLEMENTED AS BINARY16
TREE
C1 C2 C3 C4 C5 C6 C7 C8

COLUMN
ADDRESS BITS DATA OUTPUT
serial or parallel
ADVG: Decoding is realized by tree structure; much reduced Xstr count.
DISADVG: Large number of series connected nMOS pass Xstrs.
Fix with buffers or use of a combined tree and pass-transistor design.
Kenneth R. Laker, University of Pennsylvania
EXAMPLE 10.1: 17

Consider the design of a 32 - kbit implant-mask programmable NOR

ROM (215 = 32,768 individual memory cells) and the design issues that
relate to ACCESS TIME. 4µ/1.5µ

NOTE: row address bits + col address bits = 15 R1

2µ/1.5µ
ASSUME: row access bits = 7 i.e. 27 = 128 rows,
col access bits = 8, i.e. 28 = 256 cols. R2
Estimate: row access time, column access R127
time and total access time.
row R128
4µ
2µ C1 C2 C255 C256
column
n+ diffusion
2µ high threshold imp Process Params
4µ “unit” memory cell µnCox = 20µA/V2
(W = 2µm, L = 1.5µm) Cox = 3.47fF/µm2
6µ Rsheet-poly = 20Ω/sq
n+ diffusion Cgdn+Cdbn = 0.0118pF
1. Calculate Rrow, Crow for Unit Memory Cell:
Crow = Cox W L = 3.47 fF (2 x 1.5) = 10.4 fF per cell
Rrow = Rsheet-poly (Lp/Wp) = 20 Ω (3) = 60 Ω per cell
Kenneth R. Laker, University of Pennsylvania
 18
row R128

R, C for Unit Memory Cell, i.e. per Bit C1 C2 C255 C256

Crow = Cox W L = 3.47 fF (2 x 1.5) = 10.4 fF per cell

Rrow = Rsheet-poly (L/W) = 20 Ω (3) = 60 Ω per cell

RC TRANSMISSION LINE MODEL FOR POLY WORD LINE (ROW) WITH

UP TO 256 TRANSISTORS (# OF COLUMNS)
R1 R2 R255 R256
Vin VG256 R = R
i row
C1 C2 C255 C256 Ci = Crow

2. Calculate row access time trow -> delay associated with selecting and
activating 1 of 128 word lines in ROM array
V
VOH Emperical Delay Formulas
Vin V256
V50%

t
trow = 15.5 ns (at VG256)
Kenneth R. Laker, University of Pennsylvania
 19
3. Calculate column access time tcolumn -> worst case delay τPHL associated with
discharging the precharged bit line when a row is activated.

R1

R2
Up to 128-input NOR gate VDD
rep of column in the ROM R127
array. (4/1.5) column output CJ R128

C1
Ccolumn
R1 R2 R3 R128 (2/1.5)

Ccolumn = 128 x (Cgd,n + Cdbn) = 1.5 pF

where it is estimated that Cgdn + Cdbn = 0.0118 pF per word line

Kenneth R. Laker, University of Pennsylvania

Ccolumn = 128 x (Cgd,n + Cdbn) = 1.5 pF 20

where it is estimated that Cgdn + Cdbn = 0.0118 pF per word line

Since only one word-line (row) is activated at a time, tcolumn = τPHL (falling
output voltage) is determined by the inverter circuit. Output capacitance Ccolumn
is assumed pre-charged to near VDD before each row access operation.
VDD

(4/1.5)
column output CJ

R1 (2/1.5) Ccolumn = 1.5 pF

tcolumn = τPHL = 18 ns
CC  2 VT 0 n  4(VOH − VT 0 n )  
τ PHL =  + ln  − 1  = 18 ns
column load
k n (VOH − VT 0 n )  VOH − VT 0 n  VOH + VOL  

taccess = trow + tcolumn = 15.5 ns + 18 ns = 33.5 ns

Kenneth R. Laker, University of Pennsylvania

 21
STATIC READ-WRITE MEMORY (SRAM) CIRCUITS
bit line bit line
(column) (column)

1 - BIT SRAM CELL

Complementary Column arrangement achieves more reliable operation.
VDD
bit line bit line
(column) (column)
load load

word line word line

(row) (row)
BASIC REQUIREMENTS THAT DICTATE DESIGN:
1. DATA-WRITE OP -> MODIFY STORED DATA IN SRAM CELL
2. DATA-READ OP -> NOT MODIFY STORED DATA IN SRAM CELL
Kenneth R. Laker, University of Pennsylvania
 22

RESISTIVE-LOAD SRAM CELL

VDD
bit line bit line
R R
SRAM cell is accessed
via two bit (column)
word line word line lines C and its
complement for more
reliable and much
faster operation
pass transistors to
activated by a row select basic cross-coupled
(RS) signal to enable 2-inverter latch with 2
read/write ops stable op points for
storing one-bit

Kenneth R. Laker, University of Pennsylvania

 23

VDD
bit line bit line

Full CMOS SRAM

Cell
word line
word line

Kenneth R. Laker, University of Pennsylvania

 SRAM OPERATION PRINCIPLES 24

VDD pull-up transistors VDD

(one per column)
MP1 VDD MP2
bit line
bit line
R R
VC M3 V1 V2 M4 VNOT-C

CC M1 M2 CNOT-C

RS
word line
1. WHEN THE WORD LINE NOT SELECTED, i.e. RS = 0: M3 & M4 are OFF
a. One data-bit is HELD, i.e. latch preserves one of its two stable states.
b. If RS = 0 for ALL rows, the bit lines capacitances CC and CNOT-C are
charged-up to near VDD by pull-up of MP1 and MP2 (both in SAT).
VNOT-C =

EX: VC = VNOT-C = 3.5 V for VDD = 5 V, VT0 = 1 V, |2φF| = 0.6 V, γ = 0.4 V1/2.
Kenneth R. Laker, University of Pennsylvania
 25
VDD pull-up transistors VDD
(one per column)
MP1 VDD MP2
bit line
bit line
R R
VC M3 V1 V2 M4 VNOT-C

CC M1 M2 CNOT-C

RS
2. WHEN THE WORD LINE IS SELECTED, i.e. RS = 1: M3 & M4 are ON
Four basic ops can be performed in this SRAM Mode:
a. WRITE “1” OP (@ t = 0− V1n-1 = VOL, V2n-1 = VOH) RS -> 1 at t = 0:
VNOT-C -> VOL by the DATA-WRITE CIRCUITRY. Hence V2n -> VOL, then
M1 turns OFF => V1n -> VOH and M2 turns ON pulling V2n -> VOL.
b. READ “1” OP (@ t = 0− V1n-1 = VOH, V2n-1 = VOL) RS -> 1 at t = 0:
VC retains precharge level, while VNOT-C -> VOL by ON M2. DATA-READ
CIRCUITRY detects small voltage difference VC - VNOT-C > 0, and amplifies
it as a “1” data output.
Kenneth R. Laker, University of Pennsylvania
 26
VDD pull-up transistors VDD
(one per column)
MP1 VDD MP2
bit line
bit line
R R
VC M3 V1 V2 M4 VNOT-C

CC M1 M2 CNOT-C

RS
2. WHEN THE WORD LINE IS SELECTED, i.e. RS = 1: M3 & M4 are ON
Four basic ops can be performed in this SRAM Mode:
c. WRITE “0” OP (@ t = 0− V1n-1 = VOH, V2n-1 = VOL) RS -> 1 at t = 0:
VC -> VOL by the DATA-WRITE CIRCUITRY. Since V1 -> VOL, M2 turns
OFF => V2 -> VOH and M1 turns ON pulling V1n -> VOL.
d. READ “0” OP (@ t = 0− V1n-1 = VOL, V2n-1 = VOH) RS -> 1 at t = 0:
VNOT-C retains precharge level, while VC -> VOL by ON M1. DATA-READ
CIRCUITRY detects small voltage difference VC - VNOT-C < 0, and amplifies
it as a “0” data output.
Kenneth R. Laker, University of Pennsylvania
 VDD pull-up transistors VDD 27

(one per column)

MP1 VDD MP2
bit line
bit line
R R
VC M3 V1 V2 M4 VNOT-C

CC M1 M2 CNOT-C

RS

write “1” read “1” write “0” read “0”

hold hold V1 = VOH hold hold hold
RS V1 = VOL
V2 = VOL V2 = VOH
VC ≈ 3.5 V
Precharge Precharge Precharge
≈0V ≈ 3.0 V
≈ 3.5 V Precharge Precharge Precharge
VNOT-C ≈ 3.5 V
≈ 3.0 V
≈0V
Kenneth R. Laker, University of Pennsylvania
 28
STATIC OR “STANDBY” POWER CONSUMPTION
VDD pull-up transistors VDD
(one per column)
MP1 VDD MP2
bit line
bit line
R R
VC M3 V1 V2 M4 VNOT-C

CC M1 M2 CNOT-C

RS
ASSUME: 1 bit is stored in the cell => M1 OFF, M2 ON => V1 = VOH, V2 = VOL.
i.e. ONE LOAD RESISTOR IS ALWAYS CONDUCTING NON-ZERO
CURRENT.

with R = 100 MΩ (undoped poly), Pstandby < 0.25 µW per cell for VDD = 5V

Kenneth R. Laker, University of Pennsylvania

 29
CIRCUIT FOR CMOS SRAM CELL
psedo-nMOS pull-up
VDD VDD
transistors
(one per column)
VDD MP2
MP1
bit line
bit line
M5 M6
M4 VNOT-C
VC M3
CC M2 CNOT-C
M1

RS
word line
-> VERY LOW STANDBY POWER CONSUMPTION
-> LARGER NOISE MARGINS THAN R-LOAD SRAMS
-> OPERATE AT LOWER SUPPLY VOLTAGES THAN R-LOAD SRAMS

-> LARGER DIE AREA

-> CMOS MORE COMPLEX FAB PROCESS
Kenneth R. Laker, University of Pennsylvania
 CMOS SRAM DESIGN STRATEGY 30

BASIC REQUIREMENTS THAT DICTATE (W/L) RATIOS:

1. DATA-WRITE OP -> MODIFY STORED DATA IN SRAM CELL
2. DATA-READ OP -> NOT MODIFY STORED DATA IN SRAM CELL
1. CONSIDER DATA-READ OP with “0” STORED IN CELL:
VDD
VDD

VDD MP2
MP1
bit line
bit line M6
M5 VDD M4
M3 0V V2
V1
CC M2 CNOT-C
M1

RS
RS = VDD
a. @ t = 0−: M3, M4 OFF; M2, M5 OFF & M1, M6 LIN
b. @ t = 0: M3 SAT, M4 LIN; M2, M5 OFF & M1, M6 LIN
slow discharge of large Cc and V1 increases
REQUIRE V1 < VT02 => LIMITS M3 W/L wrt M1 W/L
Kenneth R. Laker, University of Pennsylvania
 VDD 31
VDD

VDD MP2
MP1
bit line
bit line M6
M5 VDD M4
M3 0V V2
V1
CC M2 CNOT-C
M1

RS
RS = VDD
DESIGN CONSTRAINT: i.e. KEEP M2 OFF
M3 SAT, M1 LIN =>
kn 3
2
2 k n1
( VDD − V1 − VT 0 n ) =
2
(
2( VDD − VT 0 n ) V1 − V12 )
SYMMETRY:
kn 4
SAME for
kn 2
(M1 & M6 OFF
Kenneth R. Laker, University of Pennsylvania for Read ‘1”)
 32
2. CONSIDER DATA-WRITE “0” OP with “1” STORED IN CELL:
VDD
VDD
0V bit line
bit line M6
M5
V 0V M4
0V M3 DD V2
V1
CC M2 CNOT-C
M1

RS
RS = VDD at t =0
VC IS SET “0” BY DATA-WRITE CIRCUIT
a. @ t = 0−: M3, M4 OFF; M2, M5 LIN & M1, M6 OFF (“1” stored)
b. @ t = 0: M3 SAT, M4 SAT; M2, M5 LIN & M1, M6 OFF
WRITE “0” => V1: VDD -> 0 (< VT0n) AND V2: 0 -> VDD (M2 -> OFF)
DESIGN CONSTRAINT: i.e. KEEP M2 OFF
WHEN V1 = VT0n: M3 LIN & M5 SAT =>
( ) ( )
kp 5 2 kn 3
0 − VDD − VT 0 p = 2( VDD − VT 0 n ) VT 0 n − VT 0n 2
2 2
Kenneth R. Laker, University of Pennsylvania
 33
V1 < VT0n, i.e. M2 (M1) forced OFF

kp 5 kp 6 2(VDD −1.5VT 0 n ) VT 0 n
= < =>
kn 3 kn 4 (VDD + VT 0p ) 2

BY SYMMETRYto WRITE “1” when “0” is stored in cell.

 W  W
 L  5  L  6 µ n 2( VDD − 1.5VT 0 n ) VT 0 n
= <
 
W  
W
 L 3  L 4
µp (
VDD + VT 0 p )
2

Kenneth R. Laker, University of Pennsylvania

 VDDSRAM WRITE CIRCUIT
34
VDD

MP1 VDD MP2

bit line VNOT-C bit line
SHARED BY VC 1 - bit
SEVERAL SRAM Cell
COLUMNS RS
WB word line
M2

DATA M1

from COLUMN M3
DECODER
Write OP: force VC or VNOT-C to a logic low level when W = 0.
NOT-W DATA NOT-WB WB OPERATION (M3 ON)
0 1 0 1 M1 OFF, M2 ON ->VNOT-C LOW
0 0 1 0 M1 ON, M2 OFF ->VC LOW
1 X 0 0 M1 OFF, M2 OFF ->VC = VNOT-C HIGH
Kenneth R. Laker, University of Pennsylvania
 SRAM READ CIRCUIT 35

VDD

R R
SOURCE Vo1 Vo2
COUPLED
DIFFERENTIAL VNOT-C
VC M1 Vx M2
AMPLIFIER

ISS

Asense = Increase R ->

Use active loads
Use cascode

Kenneth R. Laker, University of Pennsylvania

 36
FAST SENSE AMPLIFIERS
VDD pMOS
VDD
current
M4 M5 nirror
Vo VoN
VC M1 M2 VNOT-C

CC CNOT-C
CK M3

bit line bit line

Asense = -gm2 (ro2||ro5)

Kenneth R. Laker, University of Pennsylvania

 DYNAMIC READ-WRITE MEMORY (DRAM) CIRCUITS 37

SRAM -> 4 - 6 TRANSISTORS PER BIT

3 - 5 LINES CONNECTING EACH CELL
DRAM -> DATA BIT IS STORED AS CHARGE ON CAPACITOR
REDUCED DIE AREA VS. SRAM
REQUIRES PERIODIC REFRESH
bit line 2 parasitic storage bit line
capacitors 4 - Transistor
DRAM Cell
C C (earliest cell,
word word based on 6 Xstr
line line SRAM cell)
CC and CNOT-C >> C
RS (read select)
bit line (write)
1 parasitic storage
capacitor bit line (read) 3 - Transistor
DRAM Cell
C
(first widely
WS (write select) used cell)
Kenneth R. Laker, University of Pennsylvania
 38

word line
(read/write select)
1 - Transistor
explicit DRAM Cell
C storage (most widely
bit line capacitor used cell)
(data read/write)

-> INDUSTRY STANDARD FOR HIGH DENSITY DRAM ARRAYS

-> SMALLEST COMPONET COUNT & SILICON AREA PER BIT
-> SEPARATE OR “EXPLICIT” CAPACITOR (DUAL POLY) PER CELL

Kenneth R. Laker, University of Pennsylvania

 39
OPERATION OF 3 - TRANSISTOR DRAM CELL

VDD
Precharge devices
MP1 MP2
PC 1 - Bit
read select
DRAM Cell
(RS)

M1 M3
CC M2 CNOT-C
C
write select
(WS)
bit line
DATA Data_in bit line
Data_out

CC, CNOT-C >> C (> 10 C)

Uses two-phase non-overlapping clock scheme where φ1 = PC = precharge
and φ2 = RS = read or WS = write.
Kenneth R. Laker, University of Pennsylvania
 VDD 40

Precharge devices
MP1 MP2
1 - Bit
read select PC DRAM Cell
(RS)

M1 M3
CC M2 CNOT-C
C
write select
(WS)
bit line
bit line
DATA Data_in
Data_out write read write read
PC “1” PC “1” PC “0” PC “0”
1 2 3 4 5 6 7 8
PC
WS
DATA
Data_in
Stored Data
RS
Data_out
Kenneth R. Laker, University of Pennsylvania
 41
VDD
Precharge devices
MP1 MP2
PRECHARGE CYCLE
PC

CC CNOT-C

RS
VDD - VTMP1
M1 M3 WRITE “1” OP
CC M2 C3
DATA = 0
C WS = 1; RS = 0
WS CC, C SHARE
bit line CHARGE DUE TO
DATA Data_in bit line M1 ON
Data_out

Kenneth R. Laker, University of Pennsylvania

 42
RS
VDD - VTMP1
M1 M3 READ “1” OP
C2 M2 CNOT-C
DATA = 0
C WS = 0; RS = 1
WS CNOT-C DISCHARGES
bit line THROUGH M2 AND
DATA Data_in bit line M3
Data_out

RS
VDD - VTMP1
M1 M3 WRITE “0” OP
CC M2 C3
DATA = 1
C WS = 1; RS = 0
WS CC, C DISCHARGED
bit line TO 0 THROUGH M1
DATA Data_in bit line AND DATA-IN nMOS
Data_out
Kenneth R. Laker, University of Pennsylvania
 43
RS
VDD - VTMP1
M1 0V M3 READ “0” OP
C2 M2 CNOT-C
DATA = 1
C WS = 0; RS = 1
WS CNOT-C DOES NOT
bit line DISCHARGE
DATA Data_in bit line DUE TO M2 OFF
Data_out

Kenneth R. Laker, University of Pennsylvania

 1 - TRANSISTOR DRAM Cell 44

R (R/W select)
Bit-line
1-Bit
M1
CC C DRAM
Cell

D (data in/out)
CC >> C
Uses two-phase non-overlapping clock scheme where φ1 = bit-line is
precharged and φ2 = R = read/write.
WRITE “1” OP: D = 1, R = 1 (M1 ON) => C CHARGES TO “1”
WRITE “0” OP: D = 0, R = 1 (M1 ON) => C DISCHARGES TO “0”
READ OP: DESTROYS STORED CHARGE ON C => REFRESH IS
NEEDED AFTER EVERY DATA READ OP

Kenneth R. Laker, University of Pennsylvania

 45

SRAM vs. DRAM

+
trans
+
o
+

+ trans

o
o

Kenneth R. Laker, University of Pennsylvania