module sub1(a,b,c,d,e,g8);

input a,b,c;
output d,e,g8 ;
wire s1,s2,s3,g,g3,g2,g4,g5,g6,g7,x,y,u,v,p,q,r;
not N1(s1,a);
not N2(s2,b);
not N3(s3,c);
and N4(g,s1,b,s3);
and N5(g2,a,s2,s3);
and N6(g3,s1,s2,c);
and N7(g4,a,b,c);
and N8(g5,s1,b);
and N9(g6,s1,c);
and N0(g7,b,c);
and N10(g8,a,b,c);
nor N11(x,g,g2);
nor N12(y,x,x);
nor N13(u,g3,g4);
nor N14(v,u,u);
nor N15(z,y,v);
nor N16(d,z,z);
nor N17(p,g5,g6);
nor N18(q,p,p);
nor N19(r,g7,q);
nor N20(e,r,r);
endmodule