8086 Address/Data buses

RD WR M/IO
ADO-AD15 A16-A19 BHE 74LS373
STB

Control
ADDR

ALE

MEM
OE

I/O

8086

DT/R

T 8286 Transcei ver

DATA

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Buffered Systems

Address, Data and control bus buffered to provide sufficiently strong signals to drive multiple devices. Unidirectional/bidirectional
C

A
74LS244 C

74LS245
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Memory Chip
Memory location D E C O D E R

ADD Bus

DATA Bus
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8086 Address/Data buses

ADO-AD15

A0AN

A0AN

A16-A19 BHE ALE RD WR M/IO

D0D7 ___K x 8 RD

D0D7 ___Kx 8 RD

8086

WR

WR

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Interface using 2K Memory chips 8 K bytes of Memory to the 8086 CPU - Address Space - No of Memory chips - Decoding logic

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A19 A18A17A16A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1 A0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 00000H 00001H 00002H 00003H

0 0

0 0

0 0

0 0 0 0

0 0

0 0

0 0

1 1 1 1

1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1

00FFEH 00FFFH

4K (2K+2K)
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ADDRESS DATA TYPE

BHE

A0

BUS CYCLES

DATA LINES USED

00000 00000 00001 00001

BYTE WORD BYTE WORD

1 0 0 0 1

0 0 1 1 0

ONE ONE ONE FIRST

D0-D7 D0-D15 D8-D15 D8-D15 SECOND D0-D7

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A19 A18A17A16A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1 A0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 01000H 01001H 01002H 01003H

0 0

0 0

0 0

0 0 0 0

0 0

0 0

1 1

1 1 1 1

1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1

01FFEH 01FFFH

4K (2K+2K)

Total 8K
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MEMW
MEMR Data Bus Of CPU A1-A11 of CPU

WR RD

WR
RD

A0-A10

A0-A10

Remaining Add lines Of CPU

ADD Decoding Logic

CS

CS

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RD WR M/IO LOGIC CIRCUIT

MEMR
MEMW IOR IOW

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Ex: Interface 1M of SRAM to 8086. Chips available are of size 256K each.

A19 A18A1 A0 0 0 1 1 0 0 0 1 .1 1 0 .0 0 1 .1 1 512KB 512KB

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A18

A17 256K

D15-D8

A18

A17 256K

D7-D0

A1 VCC GND 7 C 4 B 1 3 A 8

A0

CS
VCC GND

A1

A0

CS

A19

1 0

A19

7 C 4 B 1 3 A 8

1 0

BHE GND

A0 GND
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Ex: Interface 4K of ROM to 8086 starting at 80000H. Chips available are 2716.

A19 A18A11 A10A1 A0

1 1 0 ..0.0 0 0 0 ..1.1.1 1

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Ex: Interface 16K of ROM to 8086 starting at 80000H. Chips available are 1KB each.

A19 A18A11 A10A1 A0 1 1 1 1 0 ..0.0 0 0 0 ..0.1 1 1 0 ..1.0 0 0 0 ..1.1.1 1 2KB

2KB

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Ex: Interface 8K of RAM to 8086 starting at 00000H. Chips available are 1KB(4 Chips) and 2KB (2 Chips).

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Ex: Interface 4K 2716 (ROM) starting at 00000H 8K 6116 (SRAM) starting at 08000H

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Input Device: Ex: Switch

VCC

S1

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VCC

S1

B U F F E R E

To data lines Of CPU

From Add Decoding Logic

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IN AL, 00H ROR AL, 1 JC SWITCH OPEN

I/O MAPPED I/O

MOV AL, [0000H] ROR AL, 1

JC SWITCH OPEN

MEMORY MAPPED I/O

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Output Device Ex: LED

R

BITS Pilani, Pilani Campus

From CPU Data line

L A T O C H
E

From Add Decoding logic

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To turn the LED on

MOV AL, 01H OUT 00H, AL

To turn the LED OFF

MOV AL, 00H OUT 00H, AL

Add Decoding Logic

I/O Mapped I/O

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 Interfacing input devices like switches require buffers Interfacing output devices like LEDs require latches. Programmable Peripheral Interface ( PPI) provide these features.

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8255

- Three 8 bit ports Port A, Port B, Port C

- Can act as output port / input port - 8 bit data bus

- 8 bit control register used to program 8255

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RD WR PORT A PA0-PA7

D0 D7 PORT B PB0-PB7

CS
A0 A1 PORT C PC0-PC7 CONTROL REG

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BITS Pilani, Pilani Campus

8255 Can Operate in Different Modes

- I/O Modes

MODE 0 - Simple I/O Mode

MODE 1 - Hand shaked I/O Mode MODE 2 - Bi-directional I/O

- BSR ( Bit Set Reset) Mode Port A can operate in Modes 0,1,2 Port B can operate in Modes 0,1 Port C can operate in Mode0, BSR mode
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Port C divided into Port C0-PC3 lower port & PC4- PC7 upper port

Port A and Port C Upper grouped Group A

Port B and Port C lower grouped - Group B

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Programming is done by writing a control word in control register.

Control Word

D7 D6 D5 D4 D3 D2 D1 D0

A1A0 A1A0 A1A0 A1A0 -

11 00 01 10

Control Register Port A Port B Port C

BITS Pilani, Pilani Campus

Control Register
There are two groups of control blocks in the 8255A control register
D7 D6 D5 D4

D3

D2

D1

D0

Mode Set Flag 0 - bit set/reset 1 I/O mode Group A Mode 00 - mode 0 01 - mode 1 1x - mode 2 PORT A 0 - output 1 - input

Group B Mode 0 - mode 0 1 - mode 1

PORT B 0 - output 1 - input PORT C (upper) 0 - output 1 - input PORT C (lower) 0 - output 1 - input

Write the Initialization routine to initialize 8255 as per the following specifications:

Port APort BPort Cupper Port C lower

Input Port

Mode 0

Output Port - Mode 0 Input Port Mode 0

Output Port Mode 0

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BITS Pilani, Pilani Campus

vcc

O U T P O R T

VCC

O U T IN PORT

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VCC C S C

VCC S C

VCC S C

VCC S

P O R T

7447

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BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus

Interfacing Analog to Digital Converter

8-bit ADC
Vin D0 D7 Vref

Start

EOC To start conversion send 2S active high pulse at start AD 570

Conversion time 20 S EOC = 1 indicates end of conversion

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Interfacing Analog to Digital Converter

8-bit ADC
D0 D7

I0 I7 ALE
A B C

EOC Start ADC 0809

OE

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