Sie sind auf Seite 1von 86

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.


2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

REV

1
ECN

DESCRIPTION OF REVISION

DATE
2010-08-05

SCHEM,FLYING_CLOUD,MLB,K90i
"EVT3"
D

11/22/10

(.csa)

Date

Page
TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

CK
APPD

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45

Contents

Sync

Table of Contents

(.csa)

MASTER

TABLE_TABLEOFCONTENTS_HEAD

06/30/2009

TABLE_TABLEOFCONTENTS_ITEM

06/30/2009

TABLE_TABLEOFCONTENTS_ITEM

MASTER

System Block Diagram

K17_REF

Power Block Diagram

K17_REF

3
4

Revision History

MASTER

TABLE_TABLEOFCONTENTS_ITEM

05/28/2009

TABLE_TABLEOFCONTENTS_ITEM

07/20/2009

TABLE_TABLEOFCONTENTS_ITEM

05/15/2010

TABLE_TABLEOFCONTENTS_ITEM

05/15/2010

TABLE_TABLEOFCONTENTS_ITEM

MASTER

BOM Configuration

K17_REF

FUNC TEST

K24_MLB

Power Aliases

K91_MLB

Signal Aliases

K91_MLB

9
10

CPU DMI/PEG/FDI/RSVD

TABLE_TABLEOFCONTENTS_ITEM

06/28/2010

TABLE_TABLEOFCONTENTS_ITEM

06/18/2010

TABLE_TABLEOFCONTENTS_ITEM

ANNE_K90I

11

CPU CLOCK/MISC/JTAG

ANNE_K90I

CPU DDR3 INTERFACES

ANNE_K90I

CPU POWER

ANNE_K90I

12
13
14

CPU GROUNDS

06/22/2010

06/18/2010

TABLE_TABLEOFCONTENTS_ITEM

06/18/2010

TABLE_TABLEOFCONTENTS_ITEM

06/28/2010

TABLE_TABLEOFCONTENTS_ITEM

06/28/2010

TABLE_TABLEOFCONTENTS_ITEM

06/18/2010

TABLE_TABLEOFCONTENTS_ITEM

06/18/2010

TABLE_TABLEOFCONTENTS_ITEM

06/10/2010

TABLE_TABLEOFCONTENTS_ITEM

ANNE_K90I

16

CPU DECOUPLING-I

JACK_K90I

17

CPU DECOUPLING-II

JACK_K90I

18

PCH SATA/PCIE/CLK/LPC/SPI

K91_MLB

19

PCH DMI/FDI/GRAPHICS

K91_MLB

PCH PCI/FLASHCACHE/USB

K91_MLB

PCH MISC

K91_MLB

20
21
22

PCH POWER

06/18/2010

TABLE_TABLEOFCONTENTS_ITEM

06/25/2010

TABLE_TABLEOFCONTENTS_ITEM

05/27/2010

TABLE_TABLEOFCONTENTS_ITEM

06/25/2010

TABLE_TABLEOFCONTENTS_ITEM

06/22/2010

TABLE_TABLEOFCONTENTS_ITEM

06/08/2010

TABLE_TABLEOFCONTENTS_ITEM

06/21/2010

TABLE_TABLEOFCONTENTS_ITEM

K91_MLB

23

PCH GROUNDS

K91_MLB

24

PCH DECOUPLING

K91_MLB

25

CPU & PCH XDP

ANNE_K90I

26

USB HUBS

K91_MLB

Clock (CK505)

K91_MLB

27
28

Chipset Support

07/08/2010

TABLE_TABLEOFCONTENTS_ITEM

MASTER

TABLE_TABLEOFCONTENTS_ITEM

06/22/2010

TABLE_TABLEOFCONTENTS_ITEM

MASTER

TABLE_TABLEOFCONTENTS_ITEM

06/22/2010

TABLE_TABLEOFCONTENTS_ITEM

06/01/2010

TABLE_TABLEOFCONTENTS_ITEM

05/15/2010

TABLE_TABLEOFCONTENTS_ITEM

LINDA_K90I

29

DDR3 SO-DIMM Connector A

MASTER

30

DDR3 Byte/Bit Swaps

ANNE_K90I

31

DDR3 SO-DIMM Connector B

MASTER

32

CPU Memory S3 Support

ANNE_K90I

33

FSB/DDR3/FRAMEBUF Vref Margining

K91_MLB

X19/ALS/CAMERA CONNECTOR

K91_MLB

34
35

SD READER CONNECTOR

TABLE_TABLEOFCONTENTS_ITEM

10/12/2010

TABLE_TABLEOFCONTENTS_ITEM

10/12/2010

TABLE_TABLEOFCONTENTS_ITEM

10/12/2010

TABLE_TABLEOFCONTENTS_ITEM

05/26/2010

TABLE_TABLEOFCONTENTS_ITEM

K91_MLB

36

T29 Host (1 of 2)

05/26/2010

T29

37

T29 Host (2 of 2)

T29

38

T29 Power Support

T29

ETHERNET PHY (CAESAR IV)

K91_MLB

39
40

Ethernet Connector

05/26/2010

TABLE_TABLEOFCONTENTS_ITEM

07/20/2009

TABLE_TABLEOFCONTENTS_ITEM

12/15/2009

TABLE_TABLEOFCONTENTS_ITEM

07/28/2009

TABLE_TABLEOFCONTENTS_ITEM

05/15/2010

TABLE_TABLEOFCONTENTS_ITEM

K91_MLB

41

FireWire LLC/PHY (FW643E)

T27_MLB

42

FireWire Port & PHY Power

T27_MLB

43

FireWire Connector

T27_MLB

45

SATA/IR/SIL Connectors

K91_MLB

External USB Connectors

K91_MLB

Front Flex Support

K91_MLB

SMC

LINDA_K90I

46

46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86

Date

Page

Contents

Sync
07/08/2010

50

SMC Support

LINDA_K90I

51

05/15/2010

LPC+SPI Debug Connector

K91_MLB

SMBus Connections

K91_MLB

Voltage & Load Side Current Sensing

LINDA_K90I

High Side Current Sensing

LINDA_K90I

Thermal Sensors

LINDA_K90I

52

05/26/2010

53

10/22/2010
10/22/2010

54

10/22/2010

55
56

07/20/2009

Fan

K24_MLB

WELLSPRING 1

LINDA_K90I

WELLSPRING 2

LINDA_K90I

Digital Accelerometer

LINDA_K90I

SPI ROM

K91_MLB

AUDIO: CODEC/REGULATOR

LENG_K90I

AUDIO: LINE INPUT FILTER

LENG_K90I

AUDIO: HEADPHONE FILTER

LENG_K90I

AUDI0: SPEAKER AMP

LENG_K90I

AUDIO: JACK

LENG_K90I

AUDIO: JACK TRANSLATORS

LENG_K90I

DC-In & Battery Connectors

JACK_K90I

PBus Supply & Battery Charger

JACK_K90I

System Agent Supply

JACK_K90I

5V/3.3V SUPPLY

JACK_K90I

1.5V DDR3 Supply

JACK_K90I

CPU IMVP7 & AXG VCore Regulator

JACK_K90I

CPU IMVP7 & AXG VCore Output

JACK_K90I

CPUVCCIO (1.05V) Power Supply

JACK_K90I

Misc Power Supplies

JACK_K90I

Power FETs

JACK_K90I

Power Control 1/ENABLE

JACK_K90I

LVDS CONNECTOR

K24_MLB

DisplayPort/T29 A MUXing

T29

DisplayPort/T29 A Connector

T29

LCD Backlight Driver

VEMURI_K90I

CPU Constraints

ANNE_K90I

Memory Constraints

ANNE_K90I

PCH Constraints 1

K91_MLB

PCH Constraints 2

K91_MLB

Ethernet/FW Constraints

K91_MLB

T29 Constraints

Master

SMC Constraints

K91_MLB

Project Specific Constraints

ANNE_K90I

PCB Rule Definitions

ANNE_K90I

57

07/12/2010

58

07/12/2010

59

07/08/2010

61

05/15/2010

62

08/10/2010

63

08/10/2010

65

08/10/2010

66

08/10/2010

67

08/10/2010

68

08/10/2010

69

08/20/2010

70

10/11/2010

71

08/19/2010

72

10/04/2010

73

10/11/2010

74

10/14/2010

75

09/03/2010

76

08/19/2010

77

08/19/2010

78

10/22/2010

79

10/22/2010

90

07/20/2009

93

10/16/2010

94

10/16/2010

97

06/25/2010

100

06/08/2010

101

05/28/2010

102

05/15/2010

103

05/15/2010

104

05/15/2010

105

06/21/2010

106

05/15/2010

108

06/08/2010

109

06/08/2010

06/01/2010

48

05/15/2010

49

07/07/2010

TABLE_TABLEOFCONTENTS_ITEM

ALIASES RESOLVED

A
DRAWING TITLE

SCHEM,FLYING CLOUD,MLB,K90i
DRAWING NUMBER

Schematic / PCB #s
PART NUMBER

QTY

Apple Inc.

DESCRIPTION

REFERENCE DES

CRITICAL

051-8658

SCHEM,MLB,K90i

SCH

CRITICAL

820-2936

PCBF,MLB,K90i

PCB

CRITICAL

BOM OPTION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING
TITLE=MLB
ABBREV=DRAWING
LAST_MODIFIED=Mon Nov 22 19:21:11 2010

SIZE

D
REVISION

BRANCH

PAGE

1 OF 109
SHEET

1 OF 86

U1000
J2500

XDP CONN

INTEL CPU

PG 23

2.2 GHZ
J3100

SANDYBRIDGE SFF 2C+2


PG 28
J2900

2 DIMMs
PG 9-13

DDR3-1067/1333MHZ

DIMM

J6900, J6950
PG 27

POWER SUPPLY

DC/BATT

PG 64-74
PG 63

GPIO

FDI

DMI

RTC

PG 19

PG 17

PG 17

PG 16

U5510, U5520

TEMP SENSOR
PG 51

U5920

Sudden Motion Sensor


U2800
PG 55

MISC

SYSTEM
CLOCK

CLK

PG 26

BUFFER

U5400, U5410, U5420, U5360


PG 19

POWER SENSE

U6100

PG 49, 50

SPI
Boot ROM

PG 16

J5601

FAN CONN AND CONTROL

SPI
J4501

PG 52

PG 56

SATA
CONN
HDD

PG 16

1.05V/3GHZ.

INTEL

PG 42

U4900

BSB

SATA

DP/TMDS

SMS

ADC

Fan

Ser
J5100

Prt

LPC+SPI Conn
Port80,serial

SMC
LPC

PG 16

SATA
CONN
ODD

J9400

B,0

COUGAR POINT-MPCH

J4500

PG 45
1.05V/3GHZ.

PG 47
PG 16

U1800

PG 42
U9390

Display Port
/ T29

MUX
U3600
PG 75

4 LANEs

PWR
PG 16-21

HDMI OUT

CTRL

CIO

TRACKPAD/
KEYBOARD

USB
PG 43

PG 32

PG 54, 53

RGB OUT

T29 Router
PG 34,35

J5800, J5713

EXTERNAL A

X19
Bluetooth

eDP OUT

PCIe x4

PG 76

J4600

J3401

CONN

PG 17

DP

DP OUT
U5701

TMDS OUT

PG 17

TP/KB
PSOC
U2650

P1

P3

P2

PG 42

PG 32

USB
U4800

IR
Controller

PG 24

PG 18

HUB-2

PG 44
P1

P2

P3

USB

IR

PG 53

U2600
PG 18

LVDS
CONN

CAMERA

USB

PCI

(UP TO 14 DEVICES)

PG 18

J4501

J3402

EXTERNAL B
USB
PG 43

LVDS OUT

J9000

J4610

10 11 12 13

DVI OUT

HUB-1

PCI-E

PG 74

PG 24

J2550
PG 16

SMBUS

JTAG

From PCH

PCH XDP

PG 16

CONN

PG 16

PCI-E

PEG

DIMMs

HDA

PG 23

(UP TO 8 LINES)
PG 16

PG 16

PG 16

U6201

AUDIO
Codec
PG 57
LINEIN

HPOUT

EXT MIC

SPDIFOUT

CLK

SDA

LINEOUT

U6500

U4100

U3900

E-NET

FW643E

LINE INPUT
FILTER

J3500

BCM57765

SD Card
CONN

U6610, U6620, U6630

HP/LO
AMP
PG 59

PG 58

SPEAKER
AMPs

U6700

SYNC_MASTER=K17_REF

PG 37

System Block Diagram

AUDIO IO SWITCH

PG 33

DRAWING NUMBER

PG 61

J4310

J3401

SYNC_DATE=06/30/2009

PAGE TITLE

PG 60
PG 39

Apple Inc.

J4000

X19

FW

E-NET

AirPort

CONN

CONN

PG 41

PG 32

J6701

J6700

J6702, J6703

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

AUDIO
CONNs

PG 38

PG 61

SIZE

D
REVISION

BRANCH

PAGE

2 OF 109
SHEET

2 OF 86

D6990

K9OI POWER SYSTEM ARCHITECTURE

ENABLE
PPDCIN_G3H

SMC PWRGD

3.425V G3HOT

PPDCIN_S5_P3V42G3H

R6990

PP3V42_G3H

PM6640

SMC_RESET_L

SN0903048
U5010
(PAGE 44)

U6990
(PAGE 63)
SMC_PBUS_VSENSE

J6900

PP5V_S0_CPUVCCIOS0

PPBUS_G3H

F6905
6A FUSE

AC

SMC_CPU_HI_ISENSE

R7020

DCIN(16.5V)

ADAPTER

U7000

R7640

R5400

F7040

CPUVCCIOS0_EN

ISL95870
U7600

EN

PPVBAT_G3H

VIN

(PAGE 70)

SMC_CPU_FSB_ISENSE
PGOOD

U4202

PBUS SUPPLY/
BATTERY CHARGER

R7050

CPU VCORE
VIN

SMC_RESET_L

ISL95231

SMC_BATT_ISENSE

SMC_CPU_ISENSE

U7400

CPUIMVP7_VR_ON

(PAGE 64)
J6950

VOUT

VR_ON

VOUT

Q7055

FW_PWR_EN

SMC_GFX_VSENSE

PPVCORE_S0_AXG

(PAGE 68)

PPVBAT_G3H_CHGR_R

PPVBATT_G3H_CONN

EN

PPVCORE_S0_CPU

PP1V0_FW_FWPHY

(PAGE 38)

SMC_CPU_VSENSE

ISL6259HRTZ
SMC_DCIN_ISENSE

3S2P

TPS22924

CPUVCCIOS0_PGOOD

VOUT

IN

(9 TO 12.6V)

PPCPUVCCIO_S0

1.05V VOUT

VCC

CHGR_BGATE

IMON

CPUIMVP_IMON

IMONG

CPUIMVP_IMONG

COUGAR-POINT
(PCH) PWRBTN#

PM_PWRBTN_L

SYS_RERST#

PM_SYSRST_L

RSMRST#

PM_RSMRST_L

CPUIMVP7_PGOOD

PGOOD

U1800
CPUIMVP7_AXG_PGOOD

PGOODG

PLT_RERST_L

PM_PCH_PWRGD

PLTRST#

CPU_PWRGD
VIN

S5

SMC

PROCPWRGD

VLDOIN

1.5V

DDRREG_EN

PM_MEM_PWRGD

PP1V5_S3

DRAMPWROK

VOUT1

U2850

MEMVTT_EN

S3

0.75V

(PAGE 16~21)

PP0V75_S0_DDRVTT

VOUT2

U4900
RC

P60

TPS51916
U7300

P3V3S5_EN

DELAY

SMC_PM_G2_EN

TP_DDRREG_PGOOD
PGOOD

(PAGE 67)

(PAGE 44)
SM_DRAMPWROK

PPBUS_S5_HS_OTHER_ISNS

COUGAR-POINT
(PCH)

VCC

PVCCSA_EN

VOUT

U1000

ISL95870A
U7100

EN

(PAGE 65)
PM_SLP_S5_L

CPU

PPVCCSA_S0_CPU

PP5V_S0

R5410

PVCCSA_PGOOD

PGOOD

UNCOREPWRGOOD

(PAGE 9~13)

RESET*

PG 17

SLP_S5#(E4)
VIN
5V

P5VS3_EN_L
EN1

RC

P5VS3_EN

VOUT1

Q7860

PP5V_S3

(L/H)

PG71

PP5V_S0

DELAY

PP3V3_S5

3.3V

P3V3S5_EN_L

PP3V3_S5

VOUT2

EN2

(R/H)

RC

DDRREG_EN

PG71

P3V3S3_EN

PG71

PP3V3_S5_PWRCTL

TPS51125
U7200

DELAY

U1800

EN

SMC

PP1V2_ENET_PHY

BCM57765

PP3V3_ENET

(PAGE 66)
PGOOD

Q9706
F9700

PM_SLP_S3_L_R

Q7922

U7980

PWRGD(P12)

CAESAR IV
(PAGE 35)

P5V3V3_PGOOD

RSMRST_PWRGD

RSMRST_IN(P13)

PM_SLP_S3_L&&WOL_EN||SMC_ADAPTER_EN

PM_SLP_S4_L

PG 17

RSMRST_OUT(P15)

PM_RSMRST_L

LCD_BKLT_EN

SLP_S4#(H4)

SMC_ONOFF_L

SLP_S3#(F4)

U7740
SYSRST(PA2)

(PAGE 71)

U9701

PPBUS_SW_LCDBKLT_PWR

IMVP_VR_ON(P16)

PP1V05_S5

TPS720105

VIN
LP8550

(PAGE 16~21)

99ms DLY
PWR_BUTTON(P90)

&& BKLT_PLT_RST_L
PM_SLP_S3_L PG 17

CPUVCCIOS0_PGOOD
PPVOUT_SW_LCDBKLT

EN

P17(BTN_OUT)

VOUT

PVCCSA_PGOOD

CPUIMVP_VR_ON

PM_SYSRST_L

PM_PWRBTN_L

PM_SLP_S5_L
SLP_S5_L(P95)

(PAGE 77)
R7978

ALL_SYS_PWRGD

U3900

Q7810

P1V8S0_PGOOD

SMC_RESET_L

PM_SLP_S4_L

RES*
SLP_S4_L(P94)

PP3V3_S3

PG71

P5V3V3_PGOOD

PM_SLP_S3_L
SLP_S3_L(P93)

S0PGOOD_PWROK
Q4260
F4260
P3V3S3_EN

PPVP_FW

U4900
(PAGE 43)

PP3V3_S5_VMON
6

Q7830
PP3V3_S0

PM_SLP_S3_L_R

PG71

PP3V3_S0
VMON_Q2

PP3V3_S0 && FWPORT_PWR_EN

RC

P1V8S0_EN

PG71

PM_SLP_S3_L_R

P5VS0_EN

PP1V05_S0

RC

MAX15053EWL

P1V8_S0_EN

EN

DELAY

U7760

VMON_Q4

PP1V8_S0

(PAGE 73)
SYNC_MASTER=K17_REF

Power Block Diagram

T29_A_HV_EN

DRAWING NUMBER

CPUVCCIOS0_EN PG71

DELAY

VIN
LT3957

PBUSVSENS_EN

TPS22924

FW_PWR_EN

EN

U3890

U4201

Apple Inc.
PP3V3_FW_FWPHY

NOTICE OF PROPRIETARY PROPERTY:

PP24V_T29

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SIZE

D
REVISION

(PAGE 40)

VOUT
(PAGE 36)

SYNC_DATE=06/30/2009

PAGE TITLE

(PAGE 71)
P3V3S0_EN

VMON_Q3

Q3880

Q7970
ASMCC0179

PP1V5_S3RS0

BRANCH

PAGE

3 OF 109
SHEET

3 OF 86

PROTO:

SYNC_MASTER=MASTER

SYNC_DATE=MASTER

PAGE TITLE

Revision History
DRAWING NUMBER

Apple Inc.
R

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SIZE

D
REVISION

BRANCH

PAGE

4 OF 109
SHEET

4 OF 86

BOM Variants

Bar Code Labels / EEEE #s


TABLE_BOMGROUP_HEAD

BOM NUMBER

BOM NAME

BOM OPTIONS

639-1294

PCBA,2.5G,K90i

K90i_COMMON,CPU_2_5GHZ,EEEE_DDRQ

639-1581

PCBA,2.7G,K90i

K90i_COMMON,CPU_2_7GHZ,EEEE_DH78

639-1698

PCBA,2.6G,K90i

K90i_COMMON,CPU_2_6GHZ,EEEE_DH8F

639-1699

PCBA,2.3G,K90i

K90i_COMMON,CPU_2_3GHZ,EEEE_DH8G

085-1998

K90i MLB DEVELOPMENT BOM

K90i_DEVEL:ENG

PART NUMBER

DESCRIPTION

REFERENCE DES

826-4393

QTY
1

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE:DDRQ]

CRITICAL
CRITICAL

BOM OPTION
EEEE_DDRQ

826-4393

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE:DH78]

CRITICAL

EEEE_DH78

826-4393

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE:DH8F]

CRITICAL

EEEE_DH8F

826-4393

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE:DH8G]

CRITICAL

EEEE_DH8G

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

D
K90i BOM GROUPS
TABLE_BOMGROUP_HEAD

BOM GROUP

BOM OPTIONS

K90i_COMMON

ALTERNATE,COMMON,K90i_COMMON1,K90i_COMMON2,K90i_DEBUG:ENG,K90i_PROGPARTS,USBHUB_2513B,T29BST:Y

K90i_COMMON1

BATT_3S,CPUMEM_S0,SMC_DEBUG_YES,HUB1_2NONREM,HUB2_3NONREM,T29:YES,DP_SDRV:A2,SDRV_PD,SDRVI2C:MCU

Alternate Parts

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR
PART NUMBER

138S0603

BOM OPTION

REF DES

COMMENTS:

138S0602

ALL

Murata alt to Samsung

157S0058

157S0055

ALL

Delta alt to TDK Magnetics

516S0805

516S0806

ALL

Molex alt to Foxconn

128S0303

128S0282

ALL

Panasonic alt to Sanyo

138S0676

138S0691

ALL

Murata alt to Samsung

152S0778

152S0693

ALL

Cyntec alt to Vishay

376S0855

376S0613

ALL

Diodes alt to Toshiba

376S0977

376S0859

ALL

Diodes alt to Toshiba

376S0972

376S0612

ALL

Rohm alt to Toshiba

376S0927

376S0966

ALL

Fairchild alt to Renesas

376S0927

376S0790

ALL

Fairchild alt to CICLON

376S0960

376S0801

ALL

Renesas alt to Renesas

376S0790

376S0928

ALL

CICLON alt to Fairchild

376S0928

376S0895

ALL

Fairchild alt to Renesas

TABLE_BOMGROUP_ITEM

K90i_COMMON2

MIKEY,KB_BL

K90i_PROGPARTS

BOOTROM_PROG,SMC_PROG,TPAD_PROG,ENET_PROG,T29ROM:PROG,T29MCU:PROG

K90i_DEVEL:ENG

BKLT:ENG,BMON:ENG,XDP_CONN,XDP_CPU:BPM,XDP_PCH,LPCPLUS,VREFMRGN,S0PGOOD_ISL,IMVPISNS_ENG

K90i_DEVEL:PVT

LPCPLUS,XDP_CONN,XDP_PCH

K90i_DEBUG:ENG

DEVEL_BOM,SMC_DEBUG_YES,XDP

K90i_DEBUG:PVT

DEVEL_BOM,BKLT:PROD,BMON:PROD,SMC_DEBUG_YES,XDP,VREFMRGN_NOT

K90i_DEBUG:PROD

BKLT:PROD,BMON:PROD,SMC_DEBUG_YES,XDP,VREFMRGN_NOT,LPCPLUS

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

Module Parts

TABLE_ALT_ITEM

TABLE_ALT_ITEM

PART NUMBER

QTY

DESCRIPTION

REFERENCE DES

CRITICAL

BOM OPTION

TABLE_ALT_ITEM

337S3934

SNB,2C,QXXX,ES1,2.2,35W,B2,3M,GT1,BGA

U1000

CRITICAL

CPU_2_2GHZ

337S4058

SNB,Q1RA,QS,J1,2.5,35W,2+2,1.30,3M,BGA

U1000

CRITICAL

CPU_2_5GHZ

337S4057

SNB,Q1R3,QS,J1,2.7,35W,2+2,1.30,4M,BGA

U1000

CRITICAL

CPU_2_7GHZ

337S4024

SNB,Q1R9,QS,J1,2.3,35W,2+2,1.30,3M,BGA

U1000

CRITICAL

CPU_2_3GHZ

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

337S4064

SNB,Q1R7,QS,J1,2.6,35W,2+2,1.30,3M,BGA

U1000

CRITICAL

337S4029

IC,PCH,COUGARPOINT,SLH9D,PRQ,BD82HM65

U1800

CRITICAL

343S0534

IC,BCM57765B0,ENET&SD,8X8

U3900

CRITICAL

338S0753

IC,FW643-E2,1394B PHY/OHCI LINK/PCI-E,12

U4100

CRITICAL

338S0921

IC,T29-C0,220 FCBGA,15x15MM

U3600

CRITICAL

353S3055

IC,PI3VEDP212,X2 DISPLAYPORT 2:1 MUX,QFN

U9390

CRITICAL

CPU_2_6GHZ

376S0937

376S0845

ALL

Fairchild alt to Renesas

376S0777

376S0761

ALL

AON alt to Siliconix

376S0957

376S0958

ALL

Fairchild alt to Fairchild

376S0953

376S0958

ALL

Fairchild alt to Renesas

353S3085

353S1658

ALL

STmicro alt to LT

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

T29:YES

Programmable Parts
PART NUMBER

QTY

DESCRIPTION

REFERENCE DES

CRITICAL

BOM OPTION

335S0663

IC,FLASH,SERIAL,SPI,!MBIT,2V7,8P,SOIC

U3990

CRITICAL

341S3026

IC ENET,1!MBITFLAH,CIV REV01,K60/K62

U3990

CRITICAL

ENET_PROG

335S0777

IC,EEPROM,SERIAL,SPI,1Kx8,1.8V,MLP8,LF

U3690

CRITICAL

T29ROM:BLANK

341T0317

IC,T29 ASSY

U3690

CRITICAL

T29ROM:PROG

337S3997

IC,MCU,32B,LPC1112A,16KB/2KB,HVQFN25

U9330

CRITICAL

T29MCU:BLANK

341S2939

IC,PROGRMD,LPC1112A,T29 PORT MCU,HVQFN25

U9330

CRITICAL

T29MCU:PROG

338S0895

IC,SMC,HS8/2117/9MMx9MM,TLP

U4900

CRITICAL

SMC_BLANK

341T0300

IC,SMC,K90i

U4900

CRITICAL

SMC_PROG

ENET_BLANK

335S0770

64 MBIT SPI SERIAL DUAL I/O FLASH

U6100

CRITICAL

BOOTROM_BLANK

335S0769

64 MBIT SPI SERIAL DUAL I/O FLASH

U6100

CRITICAL

BOOTROM_BLANK

341T0299

IC,EFI ROM,K90i

U6100

CRITICAL

BOOTROM_PROG

341S2384

IR,ENCORE II, CY7C63803-LQXC

U4800

CRITICAL

341S3024

IC,TP PSOC,K90,K90i,K91,K91F,K92

U5701

CRITICAL

TPAD_PROG

SYNC_MASTER=K17_REF

SYNC_DATE=05/28/2009

PAGE TITLE

BOM Configuration
DRAWING NUMBER

Apple Inc.
R

Development BOM
PART NUMBER

QTY
1

085-1998

NOTICE OF PROPRIETARY PROPERTY:

DESCRIPTION

REFERENCE DES

K90i MLB DEVELOPMENT

DEVEL

CRITICAL
CRITICAL

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BOM OPTION
DEVEL_BOM

SIZE

D
REVISION

BRANCH

PAGE

5 OF 109
SHEET

5 OF 86

Functional Test Points

NC_EDP_TXP<0..3>
MAKE_BASE=TRUE
NC_EDP_TXN<0..3>
MAKE_BASE=TRUE
NC_EDP_AUXP
MAKE_BASE=TRUE
NC_EDP_AUXN

NC NO_TESTs

9 6

NO_TEST

X19 CONN
I303
I301

Fan Connectors

I12
I15
I16

TRUE
TRUE
TRUE

I302
I300

PP5V_S0
FAN_RT_PWM
FAN_RT_TACH

6 7 22 42 47 52 54 65
68 70 72 73 77
I299
52
I298

52
I293

(NEED TO ADD 1 GND TP)


I288

I554
I553
I555

MIC FUNC_TEST
BI_MIC_LO
TRUE
BI_MIC_HI
TRUE
BI_MIC_SHIELD
TRUE

I292
I296

61 62
I291

61 62
I295

61 62
I290

(NEED TO ADD 1 GND TP)


I271
I289

I595

I227
I226
I228
I230
I229
I231

SPEAKER FUNC_TEST
SPKRAMP_L_N_OUT
TRUE
SPKRAMP_L_P_OUT
TRUE
SPKRAMP_R_N_OUT
TRUE
SPKRAMP_R_P_OUT
TRUE
SPKRAMP_SUB_N_OUT
TRUE
SPKRAMP_SUB_P_OUT
TRUE

I594
I593

I407
I262
I261
I256
I257
I255
I252
I253
I254
I250
I251
I313
I246
I247
I248
I249

I370

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

(NEED 2 TP)

PP3V3_LCDVDD_SW_F
PP3V3_S0_LCD_F
PPVOUT_SW_LCDBKLT (NEED
BKL_VSYNC
LVDS_DDC_CLK
LVDS_DDC_DATA
LVDS_IG_A_DATA_N<0>
LVDS_IG_A_DATA_P<0>
LVDS_IG_A_DATA_N<1>
LVDS_IG_A_DATA_P<1>
LVDS_IG_A_DATA_N<2>
LVDS_IG_A_DATA_P<2>
LVDS_CONN_A_CLK_F_N
LVDS_CONN_A_CLK_F_P
LED_RETURN_1
LED_RETURN_2
LED_RETURN_3
LED_RETURN_4
LED_RETURN_5
LED_RETURN_6

I369

6 74
6 74

I368

2 TP)
74 77
74 77

I361
I366

8 18 74

I365

8 18 74

I363

18 74 80

I364

18 74 80

I362

18 74 80

I360

18 74 80

I359

18 74 80

I357

18 74 80

I358

74 85

I377

74 85

I564

74 77

74 77
I354

74 77
I355

I349

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

PP5V_SW_ODD
SMC_ODD_DETECT
SATA_ODD_D2R_UF_P
SATA_ODD_D2R_UF_N
SATA_ODD_R2D_P
SATA_ODD_R2D_N

(NEED 2 TP)

6 42

I350

42 45

I352

42 85

I351

42 85

I353

42 80

I327

42 80

I328

I343
I342
I341

I318
I317
I307
I309
I311

I278
I270

I416
I273
I274
I275

I417

I418

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

PP5V_S0_HDD_FLT
SATA_HDD_R2D_P
SATA_HDD_R2D_N
SATA_HDD_D2R_C_P
SATA_HDD_D2R_C_N
SYS_LED_ANODE_R
IR_RX_OUT
PP5V_S3_IR_R

PP3V3_S5
PP18V5_S5
Z2_CS_L
Z2_DEBUG3
Z2_MOSI
Z2_MISO
Z2_SCLK
Z2_BOOST_EN
Z2_HOST_INTN
Z2_CLKIN
Z2_KEY_ACT_L
Z2_RESET
PSOC_MISO
PSOC_MOSI
PSOC_SCLK
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_A_S3_SCL
PSOC_F_CS_L
PICKB_L

76 85
6 7 8 17 19 20 22 23 24
26 30 46 56 66 72 73 74

I383

6 54

I419

53 54

I382

53 54

I565

53 54

I380

(NEED 2 TP)

6 42

I339

42 80

I340

42 80

I338

42 80
42 80
42
42 44
42

I336
I337
I333
I335
I334

(NEED TO ADD 3 GND TP)


I332
I330
I331

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

PPVCORE_S0_CPU
PPVCORE_S0_AXG
PP1V2_S3_ENET_INTREG
PP1V05_S0
PP1V5_S3RS0
PP1V8_S0
PP3V3_S0
PP5V_S0
PP3V3_S3
PP5V_S3
PPVCCSA_S0_CPU
PP3V3_S5
PP3V42_G3H
PPBUS_G3H
PP3V3_ENET
PP3V3_WLAN
PP5V_SW_ODD
PP5V_S0_HDD_FLT
PP18V5_S5
PP3V3_S0_LCD_F
PP3V3_LCDVDD_SW_F
PP4V5_AUDIO_ANALOG
PP1V5_S3
SMC_PM_G2_EN
PM_SLP_S4_L
PM_SLP_S3_L

17 6

NC_CRT_IG_DDC_CLK
NC_CRT_IG_DDC_DATA

NC_CRT_IG_DDC_CLK
TRUE
MAKE_BASE=TRUE
NC_CRT_IG_DDC_DATA
TRUE

7 10 12 15 30 72 73
85

NC_CRT_IG_HSYNC
NC_CRT_IG_VSYNC

I320

I305

TRUE
TRUE
TRUE
TRUE

SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
SYS_DETECT_L
PPVBAT_G3H_CONN

18 6
18 6

NC_PCI_PME_L
NC_PCI_CLK33M_OUT3

KBDLED_ANODE

TRUE

SMC_KDBLED_PRESENT_L

I394

63

(NEED 5 TP)
63 64

(NEED TO ADD 5 GND TP)

NC_CPU_THERMDC
MAKE_BASE=TRUE

6 17

NC_PCI_PME_L
NC_PCI_CLK33M_OUT3

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

6
17

16 6
16 6

7 27 29 30 67
16 6
72
45 73
16 6

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

NC_PCIE_CLK100M_PEBN
NC_PCIE_CLK100M_PEBP

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

17 30 45 73

39 6
39 6
39 6
39 6
39 6

NC_FW643_SDA
NC_FW643_SM
NC_FW643_TCK
NC_FW643_TMS
NC_FW643_FW620_L
NC_FW643_VBUF
NC_FW643_OCR10_CTL

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

53 54
39 6

53 54

39 6

53 54

6 32 45 48 54 55 84
53 54
23 6

TRUE
TRUE

23 6

(NEED 3 TP)

PP18V5_DCIN_FUSE
ADAPTER_SENSE

63
23 6
63
23 6

16 6

6 7 8 17 19 20 22 23 24 26 30
46 56 66 72 73 74 76 85

16 6

6 7 26 43 45 46 47 48 53 63 64
73
53

LPC+SPI DEBUG_CONN

16 6
16 6

53

I598
53

I597
53

I596
53

I599
53

I600
53

I601
53

I602
53

I603
53

I604
53

I605
53

I606
53

I607
53

I608
53

I609
53

I610
53

I611
53

I612
53

I614
53

I613
53

I615
53

I617
53

I616
53

I618
53

I620
53

I619
53

I622

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
LPC_CLK33M_LPCPLUS
LPC_FRAME_L
LPC_PWRDWN_L
LPC_SERIRQ
LPCPLUS_GPIO
LPCPLUS_RESET_L
PM_CLKRUN_L
PP3V42_G3H
PP5V_S0
SMC_MD1
SMC_RX_L
SMC_TCK
SMC_TDI
SMC_TDO
SMC_TMS
SMC_TRST_L
SMC_TX_L
SPI_ALT_CLK
SPI_ALT_CS_L
SPI_ALT_MISO
SPI_ALT_MOSI
SPIROM_USE_MLB

TRUE

=PEG_R2D_C_P<0..7>

TRUE

=PEG_R2D_C_N<0..7>

TRUE

=PEG_D2R_P<0..7>

TRUE

=PEG_D2R_N<0..7>

TRUE

=PEG_R2D_C_P<12..15>

MAKE_BASE=TRUE

NC_PEG_D2RN<0..7>
NC_PEG_R2D_CP<12..15>

6 9
16

MAKE_BASE=TRUE

6 16
9
6 16

NC_PEG_R2D_CN<12..15>

NC_FW643_AVREG
NC_FW643_TDI

NC_PEG_D2RP<12..15>

=PEG_R2D_C_N<12..15>

NC_PEG_D2RN<12..15>

=PEG_D2R_P<12..15>

TRUE

=PEG_D2R_N<12..15>

MAKE_BASE=TRUE
MAKE_BASE=TRUE

6 18

NC_CLINK_CLK
NC_CLINK_DATA
NC_CLINK_RESET_L

NC_PCIE_CLK100M_PE4N
NC_PCIE_CLK100M_PE4P
NC_PCIE_CLK100M_PE5N
NC_PCIE_CLK100M_PE5P
NC_PCIE_CLK100M_PE6N
NC_PCIE_CLK100M_PE6P
NC_PCIE_CLK100M_PE7N
NC_PCIE_CLK100M_PE7P
NC_PSOC_P1_3
NC_SATA_B_D2RN
NC_SATA_B_D2RP
NC_SATA_B_R2D_CN
NC_SATA_B_R2D_CP
NC_SATA_D_D2RN
NC_SATA_D_D2RP
NC_SATA_D_R2D_CN
NC_SATA_D_R2D_CP
NC_SATA_E_D2RN
NC_SATA_E_D2RP
NC_SATA_E_R2D_CN
NC_SATA_E_R2D_CP
NC_SATA_F_D2RN
NC_SATA_F_D2RP
NC_SATA_F_R2D_CN
NC_SATA_F_R2D_CP

6 16 6
16
6 16 6
16
6 19 6
16
19 6
6 16
19 6
6 16
19 6

NC_PCIE_CLK100M_PEBN
NC_PCIE_CLK100M_PEBP

NC_FW643_SDA
NC_FW643_SM
NC_FW643_TCK
NC_FW643_TMS
NC_FW643_FW620_L
NC_FW643_VBUF
NC_FW643_OCR10_CTL

NC_FW643_AVREG
TRUE
MAKE_BASE=TRUE
NC_FW643_TDI
TRUE
MAKE_BASE=TRUE

6
6
6
6
6
6
6

16
39
16
39
16
39
16
39
16
39
16
39
16
39
16

6
6
6
6
6
6
6
6

16 6
16 6

TP_XDP_PCH_OBSFN_A<0..1>
TP_XDP_PCH_OBSFN_B<0..1>
NC_TP_XDPPCH_HOOK2
NC_TP_XDPPCH_HOOK3
TP_XDP_PCH_OBSFN_D<0..1>
NC_TP_XDP_PCH_HOOK4
NC_TP_XDP_PCH_HOOK5

NC_TP_XDP_PCH_OBSFN_A<0..1> 23
TRUE
MAKE_BASE=TRUE
NC_TP_XDP_PCH_OBSFN_B<0..1> 23
TRUE
MAKE_BASE=TRUE
NC_TP_XDPPCH_HOOK2
TRUE
6 23
MAKE_BASE=TRUE
NC_TP_XDPPCH_HOOK3
TRUE
6 23
MAKE_BASE=TRUE
NC_TP_XDP_PCH_OBSFN_D<0..1> 23
TRUE
MAKE_BASE=TRUE
NC_TP_XDP_PCH_HOOK4
TRUE
6 23
MAKE_BASE=TRUE
NC_TP_XDP_PCH_HOOK5
TRUE
6 23
MAKE_BASE=TRUE

NC_PCH_GPIO64_CLKOUTFLEX0
NC_PCH_GPIO65_CLKOUTFLEX1
NC_PCH_GPIO66_CLKOUTFLEX2
NC_PCH_GPIO67_CLKOUTFLEX3

NC_PCH_GPIO64_CLKOUTFLEX0
TRUE
MAKE_BASE=TRUE
NC_PCH_GPIO65_CLKOUTFLEX1
TRUE
MAKE_BASE=TRUE
NC_PCH_GPIO66_CLKOUTFLEX2
TRUE
MAKE_BASE=TRUE
NC_PCH_GPIO67_CLKOUTFLEX3
TRUE
MAKE_BASE=TRUE

16 45 47 81

TRUE
TRUE

MAKE_BASE=TRUE

6 18

6 32 45 48 54 55 84

DC POWER CONN

TP_CPU_RSVD<8..27>

NC_PEG_D2RP<0..7>

16 6

53 54

TRUE

MAKE_BASE=TRUE

6 18

53 6

39 6

53 54

TP_CPU_RSVD<30..45>

NC_PEG_R2D_CN<0..7>

17 30 45 73

53 54

NC_CPU_THERMDC

TRUE

NC_PEG_R2D_CP<0..7>

6
18
6 18

53 54

NC_CPU_RSVD<8..27>

NC_CLINK_CLK
NC_CLINK_DATA
NC_CLINK_RESET_L

16 6

53 54

NC_CPU_THERMDA

6 9

6 17

6 54

57

6 9

TRUE

TRUE

NC_CPU_RSVD<30..45>

6 17

6 42

6
16
6
16
6
16
6
16
6
16

6 16

6
6 16
6
6 16
6
6
6

16 45 47 81

16 45 47 81

NC_PCIE_CLK100M_PE4N
NC_PCIE_CLK100M_PE4P
NC_PCIE_CLK100M_PE5N
NC_PCIE_CLK100M_PE5P
NC_PCIE_CLK100M_PE6N
NC_PCIE_CLK100M_PE6P
NC_PCIE_CLK100M_PE7N
NC_PCIE_CLK100M_PE7P
NC_PSOC_P1_3
NC_SATA_B_D2RN
NC_SATA_B_D2RP
NC_SATA_B_R2D_CN
NC_SATA_B_R2D_CP
NC_SATA_D_D2RN
NC_SATA_D_D2RP
NC_SATA_D_R2D_CN
NC_SATA_D_R2D_CP
NC_SATA_E_D2RN
NC_SATA_E_D2RP
NC_SATA_E_R2D_CN
NC_SATA_E_R2D_CP
NC_SATA_F_D2RN
NC_SATA_F_D2RP
NC_SATA_F_R2D_CN
NC_SATA_F_R2D_CP

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

NC_PCH_TP18
NC_PCH_TP17
NC_PCH_TP16
NC_PCH_TP15
NC_PCH_TP14
NC_PCH_TP13
NC_PCH_TP12

6
6 16

16 45 47 81

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

NC_PCH_TP18
NC_PCH_TP17
NC_PCH_TP16
NC_PCH_TP15
NC_PCH_TP14
NC_PCH_TP13
NC_PCH_TP12

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

NC_PCH_TP10
NC_PCH_TP9
NC_PCH_TP8
NC_PCH_TP7
NC_PCH_TP6
NC_PCH_TP5
NC_PCH_TP4
NC_PCH_TP3
NC_PCH_TP2
NC_PCH_TP1

6
6
6 16
6 16
6 19
6 19
6 19
6 19
6 53
6 16
6 16

6 16
6 16
6 16
6 16
6 16
6 16
6 16
6 16
6 16
6 16
6 16
6 16
6 16
6 16

6
6
6
6
6
6
6

26 47 81

NC_PCH_TP10
NC_PCH_TP9
NC_PCH_TP8
NC_PCH_TP7
NC_PCH_TP6
NC_PCH_TP5
NC_PCH_TP4
NC_PCH_TP3
NC_PCH_TP2
NC_PCH_TP1

16 45 47 81

17 45 47

16 45 47

19 47

26 47 81

17 45 47

NO_TEST

6 7 26 43 45 46 47 48 53 63 64
73

45 47

I500

TRUE

43 45 46 47

I499

TRUE

45 46 47

I498

TRUE

45 46 47

I497

TRUE

I495

TRUE

45 46 47

NC NO_TESTs

6
6

6 7 22 42 47 52 54 65 68 70 72
73 77

45 46 47

I496

TRUE

45 47

I494

TRUE

43 45 46 47

I493

TRUE

NC_FW2_TPBP
NC_FW2_TPBN
NC_FW2_TPBIAS
NC_FW2_TPAP
NC_FW2_TPAN
NC_FW0_TPBP
NC_FW0_TPBN
NC_FW0_TPAP

39 41

39 41

39 41
39 41

I522

TRUE

39 41

I521

TRUE

39 41 82

I520

39 41 82

I519

TRUE

I518

TRUE

I517

47
47

I492

TRUE

I491

TRUE

I581

TRUE

I580

TRUE

I582

TRUE

I583

TRUE

I584

TRUE

I585

TRUE

I586

TRUE

I588

TRUE

I587

TRUE

47
19 47 56

(NEED TO ADD 2 GND TP)

54

54

(NEED TO ADD 1 GND TP)

TRUE

PCH_VSS_NCTF<1>
PCH_VSS_NCTF<2>
PCH_VSS_NCTF<5>

I547

TRUE

I546

TRUE

I545

TRUE

I544

TRUE

I543

TRUE

I542

TRUE

I541

TRUE

I540

TRUE

81
81
81

39 41 82

47

KBD BACKLIGHT CONN


TRUE

6 17

7 26 37 71 73

(NEED TO ADD 4 GND TP)

I356

NC_HDA_SDIN1
NC_HDA_SDIN2
NC_HDA_SDIN3

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

7 8 36 40 49 50 63 64 77

6 74

NC_EDP_AUXN

MAKE_BASE=TRUE

NC_HDA_SDIN1
NC_HDA_SDIN2
16 6
47 48 53 63 64 73
6 7 26
NC_HDA_SDIN3
43 45 46 16 6

6 45 48 63 64 84
6 45 48 63 64 84

NC_CRT_IG_HSYNC
NC_CRT_IG_VSYNC

NC_LVDS_IG_CTRL_CLK
TRUE
MAKE_BASE=TRUE
NC_LVDS_IG_CTRL_DATA
TRUE
MAKE_BASE=TRUE
NC_PCH_LVDS_VBG
TRUE
MAKE_BASE=TRUE

7 12 15
16 6
65

6 74

NC_EDP_AUXP

TRUE

MAKE_BASE=TRUE

7 30 32 42 43 44 46 57 59 60 61
66 67 72

6 42

TP_EDP_TX_N<0..3>

TRUE

MAKE_BASE=TRUE

NC_LVDS_IG_CTRL_CLK
NC_LVDS_IG_CTRL_DATA
NC_PCH_LVDS_VBG

BATT POWER CONN

I321

NC_CPU_THERMDA

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

7 14 17 20 22 26 71
29 33 36 37 40 18 6
7 8 12 16 1750
18 19 20 22 23 26 27
41 42 46 48 49 18 6
51 52 54 57 61 62 71 72 73
74 75 77 85
18 6
7 8 18 24 26
30 31 32 33 48 50 54 55 72 73

6 32 46

TP_EDP_TX_P<0..3>

TRUE

MAKE_BASE=TRUE

45 68 70 73
17 6
7 9 10 12 14
16 17 20 22 23 36 40

54

(NEED TO ADD 2 GND TP)

I322

6 17

TRUE

MAKE_BASE=TRUE

6 17

MAKE_BASE=TRUE

39 6

I304

PP3V3_S5
PP3V42_G3H
WS_KBD1
WS_KBD2
WS_KBD3
WS_KBD4
WS_KBD5
WS_KBD6
WS_KBD7
WS_KBD8
WS_KBD9
WS_KBD10
WS_KBD11
WS_KBD12
WS_KBD13
WS_KBD14
WS_KBD15_CAP
WS_KBD16_NUM
WS_KBD17
WS_KBD18
WS_KBD19
WS_KBD20
WS_KBD21
WS_KBD22
WS_KBD23
WS_KBD_ONOFF_L
WS_LEFT_SHIFT_KBD
WS_LEFT_OPTION_KBD
WS_CONTROL_KBD

NC_CRT_IG_BLUE
NC_CRT_IG_GREEN
NC_CRT_IG_RED

37 71

(NEED TO ADD 6 GND TP)

53 54

17 6

7 9 12 14 49
69
7 9 12 15 49
69

53 54

74 77

SATA HDD/IR/SIL

I315

32 80
32 80

KEYBOARD CONN

I329

I314

I376

I312

(NEED TO ADD 3 GND TP)

I319

I283

45 48 51 84

74 77

I348

I266

I282

(NEED TO ADD 2 GND TP)

SATA ODD CONN

I265

I281

26 32
45 48 51 84

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

74 77

I347

I267

I280

I386

I346

I269

85

IPD_FLEX_CONN

I345

I268

I414

I388

I344

I285

85

I390

(NEED TO ADD 5 GND TP)

I264

81

60 61 85

I371

I245

I287

60 61 85

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE

81

60 61 85

60 61 85

17 6

NC_CRT_IG_BLUE
NC_CRT_IG_GREEN
NC_CRT_IG_RED

9 6

81

I391

LVDS FUNC_TEST

I260

DEBUG VOLTAGE

81

60 61 85

I372

17 6

32 46

I392

I374

I258

17 6

(NEED 3 TP) 6
PP3V3_WLAN
PCIE_AP_D2R_PI_P
32
PCIE_AP_D2R_PI_N
32
PCIE_AP_R2D_P
32
PCIE_AP_R2D_N
32
PCIE_CLK100M_AP_CONN_P 32
PCIE_CLK100M_AP_CONN_N 32
PP3V3_S3_BT_F
32
PCIE_WAKE_L
17
SMBUS_SMC_0_S0_SCL
32
SMBUS_SMC_0_S0_SDA
32
USB_BT_P
24
USB_BT_N
24
AP_CLKREQ_Q_L
32
AP_RESET_CONN_L
32
AP_TEMP_SMB_SDA_R
32
AP_TEMP_SMB_SCL_R
32
WIFI_EVENT_L_R
32
(NEED TO ADD 5 GND TP)

60 61 85

I375

I259

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

XDP_PCH_AP_PWR_EN
XDP_PCH_USB_HUB_SOFT_RST_L 23
XDP_PCH_SDCONN_STATE_RST_L 23
XDP_PCH_ENET_PWR_EN
23
XDP_PCH_SDCONN_DET_L
23
XDP_PCH_S5_PWRGD
23
XDP_PCH_PWRBTN_L
23
XDP_PCH_ISOLATE_CPU_MEM_L 23
XDP_FW_CLKREQ_L
23
XDP_AP_CLKREQ_L
23
XDP_PCH_AUD_IPHS_SWITCH_EN 23

TRUE

PCH_VSS_NCTF<9>
PCH_VSS_NCTF<11>
PCH_VSS_NCTF<12>

81
81
81

TP_LVDS_IG_B_CLKN
TP_LVDS_IG_B_CLKP
NC_LVDS_IG_BKL_PWM

80 18 8
80 18 8
6

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

NC_SMC_BS_ALRT_L

PCH_VSS_NCTF<15>
PCH_VSS_NCTF<17>
PCH_VSS_NCTF<19>
PCH_VSS_NCTF<19>
PCH_VSS_NCTF<21>
PCH_VSS_NCTF<25>
PCH_VSS_NCTF<27>
PCH_VSS_NCTF<29>

6
6

6
6
6
6
6
6
6

81
81
6 81
6 81
81
81
81
81

NC_LVDS_IG_B_CLKN
NC_LVDS_IG_B_CLKP
NC_LVDS_IG_BKL_PWM

TRUE
MAKE_BASE=TRUE

NC_SMC_BS_ALRT_L

SYNC_MASTER=K24_MLB
PAGE TITLE

FUNC TEST
CAMERA/ALS CONN

BIL CONN
I326
I323
I324
I325
I308

TRUE
TRUE
TRUE
TRUE
TRUE

PP3V42_G3H
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
SMC_BIL_BUTTON_L
SMC_LID_R

I408
6 7 26 43 45 46 47
48 53 63 64 73

I409

6 45 48 63 64 84

I410
6 45 48 63 64 84
I297

45 46 63
I294

63

(NEED TO ADD 2 GND TP)

TRUE
TRUE
TRUE
TRUE
TRUE

PP5V_S3_ALSCAMERA_F
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA
USB_CAMERA_CONN_P
USB_CAMERA_CONN_N

DRAWING NUMBER

17 6
6 32 45 48 54 55 84
17 6
6 32 45 48 54 55 84
32 80

17 6

32 80

17 6

17 6

NC_SDVO_TVCLKINN
NC_SDVO_TVCLKINP

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

NC_SDVO_TVCLKINN
NC_SDVO_TVCLKINP

NC_SDVO_STALLN
NC_SDVO_STALLP

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

NC_SDVO_STALLN
NC_SDVO_STALLP

NC_SDVO_INTN
NC_SDVO_INTP

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

NC_SDVO_INTN
NC_SDVO_INTP

(NEED TO ADD 2 GND TP)


17 6

Apple Inc.

32

6 17
R
6 17

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

6 17
6 17

6 17
6 17

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SIZE

D
REVISION

PAGE

7 OF 109
SHEET

6 OF 86

"G3Hot" (Always-Present) Rails


77 64 63
36 8 7 6
50 49 40

PPBUS_G3H

PPBUS_G3H

VOLTAGE=12.8V

70
65 50 7
69 68 67

6 7 8 36 40 49
50 63 64 77

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.8V
MAKE_BASE=TRUE

PPVIN_SW_T29BST

36

PPBUS_S5_HS_COMPUTING_ISNS

PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

6 7 8 36 40 49 50 63 64 77
6 7 8 36 40 49 50 63 64 77
6 7 8 36 40 49 50 63 64 77
6 7 8 36 40 49 50 63 64 77
6 7 8 36 40 49 50 63 64 77

PPBUS_S5_HS_COMPUTING_ISNS

PPBUS_S5_HS_OTHER_ISNS

PPBUS_S5_HS_OTHER_ISNS
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=12.8V
MAKE_BASE=TRUE

7 50 65 67 68 69 70

PPBUS_S5_HS_OTHER_ISNS
PPBUS_S5_HS_OTHER_ISNS

63 49 7
64

PPDCIN_G3H

PPDCIN_G3H

PP3V42_G3H

PP3V42_G3H
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.42V
MAKE_BASE=TRUE

PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H

17 16 7
26 20

7 50 65 67 68 69 70
7 50 65 67 68 69 70

7 50 66

PP3V3_SUS

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM

PPVRTC_G3H

PPVRTC_G3H

7 50 66

7 49 63 64

7 49 63 64
7 49 63 64
73
6 7 26 43 45 46
47 48 53 63 64

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM

PP5V_S5

PP5V_S5
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
MAKE_BASE=TRUE

PP5V_S5
PP5V_S5
PP5V_S5

72 22 7

PP5V_SUS

6 7 26 43 45 46 47 48 53 63 64
73
26 24 18 8 7 6
73 72 55 54 50 48 33 32 31 30

PP3V3_S3

6 7 26 43 45 46 47 48 53 63 64
73

6 7 26 43 45 46 47 48 53 63 64
73

72 67 66 61 60
42 32 30 7 6
59 57 46 44 43

PP5V_S3

6 7 26 43 45 46 47 48 53 63 64
73
6 7 26 43 45 46 47 48 53 63 64
73
6 7 26 43 45 46 47 48 53 63 64
73

7 16 17 20 26

7 16 17 20 26

74
7 54 66 72 49
23 22 20 19 18 17 16 12 8 7
46 42 41 40 37 36 33 29 27
72 71 62 61 57 54 52 51
85 77

73
48
6
26
50
75

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.20MM

6 7 30 32 42 43 44 46 57 59 60
61 66 67 72
6 7 30 32 42 43 44 46 57 59 60
61 66 67 72
6 7 30 32 42 43 44 46 57 59 60
61 66 67 72
6 7 30 32 42 43 44 46 57 59 60
61 66 67 72

PP5V_S3
PP5V_S3
PP5V_S3
PP5V_S3
PP5V_S3
PP5V_S3

6 7 30 32 42 43 44 46 57 59 60
61 66 67 72
6 7 30 32 42 43 44 46 57 59 60
61 66 67 72
6 7 30 32 42 43 44 46 57 59 60
61 66 67 72
6 7 30 32 42 43 44 46 57 59 60
61 66 67 72
6 7 30 32 42 43 44 46 57 59 60
61 66 67 72

PP5V_S3
PP5V_S3
PP5V_S3
PP5V_S3

77 73 72
47 42 22 7 6
70 68 65 54 52

PP5V_S0

6 7 30 32 42 43 44 46 57 59 60
61 66 67 72
6 7 30 32 42 43 44 46 57 59 60
61 66 67 72
6 7 30 32 42 43 44 46 57 59 60
61 66 67 72

PP5V_S0
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
MAKE_BASE=TRUE

PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0

6 7 22 42 47 52 54 65 68 70 72
73 77

6 7 22 42 47 52 54 65 68 70 72
73 77
6 7 22 42 47 52 54 65 68 70 72
73 77
6 7 22 42 47 52 54 65 68 70 72
73 77
6 7 22 42 47 52 54 65 68 70 72
73 77
6 7 22 42 47 52 54 65 68 70 72
73 77
6 7 22 42 47 52 54 65 68 70 72
73 77
6 7 22 42 47 52 54 65 68 70 72
73 77
6 7 22 42 47 52 54 65 68 70 72
73 77

23
76
23
76

72
17
56
17
67
17
66

73
19
66
19
30
19
72

74
20
72
20
29
20
73

76
22
73
22
27
22
74

17
66
17
66

19
72
19
72

20
73
20
73

22
74
22
74

85
23 24 26 30
46
74 76 85
23 24
7 6
23 24 26 30
76 85

PP1V5_S3

23
76
23
76

PPVP_FW

PPVP_FW

PPVP_FW
PPVP_FW

7 40 41

6 7 14 17 20 22 26 71
41 40 39 7
6 7 14 17 20 22 26 71

PP3V3_FW_FWPHY
PP3V3_FW_FWPHY

6 7 14 17 20 22 26 71

6 7 27 29 30
67 72

PP1V0_FW_FWPHY

7 39 40

6 7 27 29 30 67 72
6 7 27 29 30 67 72
6 7 27 29 30 67 72

T29 Rails (off when no cable)

6 7 10 12 15 30 72 73 85
76 36 8 7

PP15V_T29

PP15V_T29

7 8 36 76

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=17.8V
MAKE_BASE=TRUE

PP1V5_S3RS0
PP1V5_S3RS0

7 16 17 18 19 20 22 46 71 72 73

7 39 40

6 7 27 29 30 67 72

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.5V
MAKE_BASE=TRUE

7 16 17 18 19 20 22 46 71 72 73

7 39 40 41

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.0V
MAKE_BASE=TRUE

6 7 27 29 30 67 72

PP1V5_S3RS0

7 16 17 18 19 20 22 46 71 72 73

7 39 40 41

PP1V0_FW_FWPHY

PP1V0_FW_FWPHY

40 39 7

7 16 17 18 19 20 22 46 71 72 73

7 16 17 18 19 20 22 46 71 72 73

7 39 40 41

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE

6 7 14 17 20 22 26 71

PP1V5_S3
PP1V5_S3
PP1V5_S3
PP1V5_S3
PP1V5_S3

PP1V5_S3RS0

PP3V3_FW_FWPHY

PP3V3_FW_FWPHY

6 7 14 17 20 22 26 71

PP1V5_S3

6 7 8 17 19 20 22 23 24 26 30
46 56 66 72 73 74 76 85

7 40 41

6 7 14 17 20 22 26 71

MIN_LINE_WIDTH=0.8 MM
MIN_NECK_WIDTH=0.1 MM
VOLTAGE=1.5V
MAKE_BASE=TRUE

24 26 30
85
24 26 30
85

7 40 41

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=12.8V
MAKE_BASE=TRUE

6 7 14 17 20 22 26 71

PP1V8_S0
PP1V8_S0
PP1V8_S0
PP1V8_S0
PP1V8_S0
PP1V8_S0

24 26 30
85
24 26 30
85

VOLTAGE=3.3V
MAKE_BASE=TRUE

PP15V_T29

6 7 10 12 15 30 72 73 85

7 8 36 76

6 7 10 12 15 30 72 73 85

7 16 17 18 19 20 22 46 71 72 73
7 16 17 18 19 20 22 46 71 72 73

PP3V3_T29

PP3V3_T29

36 35 34 26 19 16 7
71 72 73
7 16 17 18 19 20 22 46
71 57 42 26 22 20 16 7

PP1V5_S0

PP1V5_S0

6 7 8 18 24 26 30 31 32 33 48
50 54 55 72 73

PP1V5_S0
PP1V5_S0
PP1V5_S0
PP1V5_S0

6 7 8
50 54
6 7 8
33 48

PPVTTDDR_S3

7 46 53 54 72
7 46 53 54 72

VOLTAGE=3.3V
MAKE_BASE=TRUE

18
55
18
50

24
72
24
54

26 30 31 32 33 48
73
26 30 31 32
55 72 73 7
6 7 8 18 24 26 30 67 31
31 32 33 48 50 54 55 72 73

PP0V75_S0_DDRVTT

24
72
24
72

7 16 20 22 26 42 57 71
36 35 7
7 16 20 22 26 42 57 71

PP1V05_T29

PP1V05_T29

7 35 36

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE

C
7 35 36

7 31 67

PP0V75_S0_DDRVTT

7 27 29 30 67

1V05 S0 LDO

7 27 29 30 67
7 27 29 30 67

PP1V05_S0_PCH_VCCADPLL

PP1V05_S0_PCH_VCCADPLL

7 27 29 30 67 71 20 7

30 31 32 33 48
72 73

PPVCCSA_S0_CPU

12 7 6
33 48 50 54 55

PPVCCSA_S0_CPU

6 7 12 15 65

PP1V05_S0_PCH_VCCADPLL

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0.9V
MAKE_BASE=TRUE

48 49 50 51 52 54 57 61 62 71
6 7 8 12 16 17 18 19 20 22 23
26 27 29 33 36 37 40 41 42 46
72 73 74 75 77 85

PP1V05_SUS

PPVCCSA_S0_CPU

6 7 12 15 65

PP1V05_SUS

7 23 71

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
7 23 71
69 49 14 12 9 7 6

PP1V05_S0

48 49 50 51 52 54 57 61 62 71
6 7 8 12 16 17 18 19 20 22 23
26 27 29 33 36 37 40 41 42 46
72 73 74 75 77 85
6
26 27 29 33
7 8 12 16 17 18 19 20 22 23
36 37 40 41 42 46 48 49 50
51 52 54 57 61 62 71 72 73
7374
75 77 85
48
6 7 8 12 16 17 18 19 20 22 23
26 27 29 33 36 37 40 41 42 46
498 50 51 52 54 57 61 62 71 72
746 75 77 85
7
27 29 33 36 37 40
8 12 16 17 18 19 20 22 23 26
6 41 42 46 48 49 50 51 52 54
7 57 61 62 71 72 73 74 75
1277 85
16
33 36 37 40 41 42
178 18 19 20 22 23 26 27 2975
466 48 49 50 51 52 54 5750 51 52
61 62 71 72 73 74 75 7727 29
857
12 16 17 18 19 20 22 23 26
6 33 36 37 40 41 42 46 48 49
7 54 57 61 62 71 72 73 74
8 77 85
12
48 49 50 51 52 54
16 17 18 19 20 22 23 26 27
29 33 36 37 40 41 42 46
57 61 62 71 72 73 74 75
77 85
6 7 8
73 71 37 26 7 6
12 16 17 18 19 20 22 23 26 27
29 33 36 37 40 41 42 46 48 49
50 51 52 54 57 61 62 71 72
73 74 75 77 85

6 7 9 12
14 49 69

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.25V
MAKE_BASE=TRUE

PPVCORE_S0_CPU
PPVCORE_S0_CPU

PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0

48 49 50 51 52 54 57 61 62 71
6 7 8 12 16 17 18 19 20 22 23
26 27 29 33 36 37 40 41 42 46
72 73 74 75 77 85
6
26 27 29 33
7 8 12 16 17 18 19 20 22 23
36 37 40 41 42 46 48 49 50
51 52 54 57 61 62 71 72 73
74 75 77 85

PPVCORE_S0_CPU

PPVCORE_S0_CPU

6 7 9 10 12 14 16 17 20 22 23
36 40 45 68 70 73

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE

? mA

7 20 71

Chipset "VCore" Rails

PP1V05_SUS

PP1V05_S0

7 20 71

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE

30 31 32 33 48

48 49 50 51 52 54 57 61 62 71
6 7 8 12 16 17 18 19 20 22 23
26 27 29 33 36 37 40 41 42 46
72 73 74 75 77 85
85
48 49 50 51 52 71 23 7
6 7 8 12 16 17 18 19 20 22 23
26 27 29 33 36 37 40 41 42 46
54 57 61 62 71 72 73 74 75 77
6
167 8 12 16 17 18 19 20 22 23
8 26 27 29 33 36 37 40 41 42
6 46 48 49 50 51 52 54 57 61
7 62 71 72 73 74 75 77 85
12
17 18 19 20 22 23 26 27 29
33 36 37 40 41 42 46 48 49
50 51 52 54 57 61 62 71
72 73 74 75 77 85
23 22 20 17 16 14 12 10 9 7 6
6 7 8 73 70 68 45 40 36
12 16 17 18 19 20 22
23 26 27 29 33 36 37
40 41 42 46 48 49 50 51 52
54 57 61 62 71 72 73 74 75 61
776 85 26 27 29 33 36 37 40 41
297 8 12 16 17 18 19 20 22 23
8 42 46 48 49 50 51 52 54 57
6 62 71 72 73 74 75 77 85
50
7
12 16 17 18 19 20 22 23 26 27
33 36 37 40 41 42 46 48 49
51 52 54 57 61 62 71 72 73 85
54
74 75 77 85
6
26 27 29 33 36 37
297 8 12 16 17 18 19 20 22 23
8 40 41 42 46 48 49 50 51 52
6 57 61 62 71 72 73 74 75 77
7
12 16 17 18 19 20 22 23 26 27
33 36 37 40 41 42 46 48 49 77
50 51 52 54 57 61 62 71 72
736 74 75 77 85 26 27 29 33 52
36
167 8 12 16 17 18 19 20 22 23
8 37 40 41 42 46 48 49 50 51
6 54 57 61 62 71 72 73 74 75
7 85
12
33 36 37 40 41 42 46 48
17 18 19 20 22 23 26 27 29 75
49 50 51 52 54 57 61 62 71
726 73 74 75 77 85 26 27 29 51
33
7 8 12 16 17 18 19 20 22 23
36 37 40 41 42 46 48 49 50
52 54 57 61 62 71 72 73 74
77 85
72 73 74 75 77 85
48 49 50 51 52 54 57 61 62 71
26 27 29 33 36 37 40 41 42 46
6 7 8 12 16 17 18 19 20 22 23
48 49 50 51 52 54 57 61 62 71
6 7 8 12 16 17 18 19 20 22 23
26 27 29 33 36 37 40 41 42 46
72 73 74 75 77 85
6
26 27 29 33
7 8 12 16 17 18 19 20 22 23
36 37 40 41 42 46 48 49 50
51 52 54 57 61 62 71 72 73
74 75 77 85

6 7 9
14 49
6 7 9
14 49

6 7 9 10 12 14 16 17 20 22 23
36 40 45 68 70 73

12
69
12
69

6 7 9 10 12 14 16 17 20 22 23
36 40 45 68 70 73
69 49 15 12 9 7 6

PPVCORE_S0_AXG

PPVCORE_S0_AXG

6 7 9
36 40
6 7 9
36 40
6 7 9
36 40
6 7 9
36 40

10
45
10
45
10
45
10
45

12
68
12
68
12
68
12
68

14
70
14
70
14
70
14
70

16
73
16
73
16
73
16
73

17 20 22 23

10
45
10
16
73
10

12
68
14
17
36
12

14
70
12
20
40
14

16
73
10
22
45
16

PPVCORE_S0_AXG
PPVCORE_S0_AXG

17 20 22 23
17 20 22 23

20 22 23

PP1V5_S3_CPU_VCCDQ

PP1V5_S3_CPU_VCCDQ

20 22 23

17 20 22 23

PP1V05_S0_CPU_VCCPQE

PP1V05_S0_CPU_VCCPQE

7
23 36 40 45
68 70 73
17 20 22 23

6 7 9
36 40
6 7 9
36 40
6 7 9
36 40

16 17 20 22 23
73
16 17 20 22 23
73
16 17 20 22 23
73

7 10 12
14

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE

PP1V8_S0_CPU_VCCPLL_R

68 70 73
16 17 20 22 23
16 17 20 22 23
73

14
70
14
70
14
70

7 12 15

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.5V
MAKE_BASE=TRUE

20 22 23

6 7 9 10 12 14
14 16 17 20 22
70 73
6
36 40 45
7 9 10 12 14
6 7 9 10 12 14
36 40 45 68 70
12
68
12
68
12
68

12
69
12
69

73

6 7 9 10 12 14 16 17 20 22 23
36 40 45 68 70 73
6 7 9 10 12 14 16 17 20 22 23
36 40 45 68 70 73

10
45
10
45
10
45

6 7 9
15 49
6 7 9
15 49

17 20 22 23

6 7 9 10 12 14 16 17
36 40 45 68 70 73
70
6 7 9 10 12 14 16 17
20 22 23 36 40 45 68
6 7 9 10 12 14 16 17
36 40 45 68 70 73
6 7 9 10 12 14 16 17
36 40 45 68 70 73
6 7 9
36 40
6 7 9
12 14
68 70
6
7 9

6 7 9 12
15 49 69

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE

6 7 9 10 12 14 16 17 20 22 23
36 40 45 68 70 73

PP1V8_S0_CPU_VCCPLL_R

12 7
23 36 40 45 68

7 12 14

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.8V
MAKE_BASE=TRUE

SYNC_DATE=05/15/2010

PAGE TITLE

Power Aliases
DRAWING NUMBER

Apple Inc.

ENET Rails
PP3V3_ENET

6 7 26 37 71 73

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE

48 49 50 51 52 54 57 61 62 71
6 7 8 12 16 17 18 19 20 22 23
26 27 29 33 36 37 40 41 42 46
72 73 74 75 77 85
6
26 27 29 33
167 8 12 16 17 18 19 20 22 23
8 36 37 40 41 42 46 48 49 50
6 51 52 54 57 61 62 71 72 73
7 74 75 77 85
33 36 37 40 41
12
17 18 19 20 22 23 26 27 29
42 46 48 49 50 51 52 54 57
61 62 71 72 73 74 75 77 85

6 7 26 37 71 73
6 7 26 37 71 73
6 7 26 37 71 73

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:

PP3V3_ENET
PP3V3_ENET
PP3V3_ENET

6 7 9 10 12 14 16 17 20 22 23
36 40 45 68 70 73

SYNC_MASTER=K91_MLB

PP3V3_ENET

7 16 19 26 34 35 36

7 16 20 22 26 42 57 71

PP0V75_S0_DDRVTT
PP0V75_S0_DDRVTT
PP0V75_S0_DDRVTT

6 7 8 18 24 26 30 31 32 33 48
50 54 55 72 73
6 7 8 18 24 26 30 31 32 33 48
50 54 55 72 73

VOLTAGE=3.3V
MAKE_BASE=TRUE

7 16 19 26 34 35 36

MIN_LINE_WIDTH=2 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=0.75V
MAKE_BASE=TRUE

26 30 31 32 33 48
73
26 30 31 32 33 48
73

6 7 8 18 24 26
50 54 55 72 73
6 7 8 18 24 26
50 54 55
72 73
6 7 8 18 65 15
24 26 30 31 32

7 16 20 22 26 42 57 71

7 16 19 26 34 35 36

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0.75V
MAKE_BASE=TRUE

6 7 8 18 24 26 30 31 32 33 48
50 54 55 72 73
54 55 72 73
6 7 8 18 24 26 30 31 32
33 48 50 67 30 29 27 7
6 7 8 18 24 26 30 31 32 33 48
50 54 55 72 73
18
55
18
55

PP3V3_T29
PP3V3_T29
PP3V3_T29

PP1V05_T29

PPVTTDDR_S3

6 7 8 18 24 26 30 31 32 33 48
50 54 55 72 73

6 7 8
50 54
6 7 8
50 54

7 16 20 22 26 42 57 71

MIN_LINE_WIDTH=2 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=1.5V
MAKE_BASE=TRUE

7 46 53 54 72

VOLTAGE=3.3V
MAKE_BASE=TRUE

7 16 19 26 34 35 36

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE

7 16 17 18 19 20 22 46 71 72 73

PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0

6 7 22 42 47 52 54 65 68 70 72
73 77
6 7 22 42 47 52 54 65 68 70 72
73 77

PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0

6 7 30 32 42 43 44 46 57 59 60
61 66 67 72

6 7 30 32 42 43 44 46 57 59 60
61 66 67 72
6 7 30 32 42 43 44 46 57 59 60
61 66 67 72

PP5V_S3
PP5V_S3
PP5V_S3

6 7 8
46 56
6 7 8
46 56

PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0

7 22 72

PP5V_S3

22
74
22
74

6 7 8 17 19 20 22 23 24 26 30
46 56 66 72 73 74 76 85
6 7 8 17 19 20 22 23 24 26 30
46 56 66 72 73 74 76 85

PP3V3_S0

PP3V3_S0

7 22 72

PP5V_S3

20
73
20
73

6 7 8 17 19 20 22 23 24 26 30
46 56 66 72 73 74 76 85

PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3

7 54 66 72

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
MAKE_BASE=TRUE

56 66
6 7 8
30 46
6 7 8
26 72
6 7 8
46 56

PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3

6 7 26 43 45 46 47 48 53 63 64
73

7 54 66 72

PP5V_SUS

19
72
19
72

6 7 8 17 19 20 22 23 24 26 30
46 56 66 72 73 74 76 85

PP3V3_S3
PP3V3_S3

6 7 26 43 45 46 47 48 53 63 64
73

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
MAKE_BASE=TRUE

17
66
17
66

6 7 8 17 19 20 22 23 24 26 30
46 56 66 72 73 74 76 85

PP3V3_S3
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM

6 7 26 43 45 46 47 48 53 63 64
73

7 54 66 72

PP5V_SUS

6 7 8
46 56
6 7 8
46 56

PP3V3_S4
PP3V3_S4

6 7 26 43 45 46 47 48 53 63 64
73

5V Rails
72 66 54 7

PP1V8_S0

2A max supply

PP3V3_S4

PP3V3_S4

"FW" (FireWire) Rails

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.8V
MAKE_BASE=TRUE

6 7 8 17 19 20 22 23 24 26 30
46 56 66 72 73 74 76 85
6 7 8 17 19 20 22 23 24 26 30
46 56 66 72 73 74 76 85

PP3V3_SUS
PP3V3_SUS
PP3V3_SUS
PP3V3_SUS
PP3V3_SUS
PP3V3_SUS
PP3V3_SUS
PP3V3_SUS

7 50 66

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3V
MAKE_BASE=TRUE

PPVRTC_G3H

PP1V8_S0

85 73 72 30 15 12 10 7 6

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=18.5V
MAKE_BASE=TRUE

PPDCIN_G3H
PPDCIN_G3H
73 64 63
46 45 43 26 7 6
53 48 47

7 50 65 67 68 69 70

2
41 40 7

26 30 46 56 66 72 73 74 76 85
6 7 8 17 19 20 22 23 24
71 26 22 20 17 14 7 6

PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_SUS

7 50 65 67 68 69 70

6 7 8 17 19 20 22 23 24 26 30
46 56 66 72 73 74 76 85

PP3V3_S5

7 50 65 67 68 69 70

72 71 46 22 20 19 18 17 16 7
73

VOLTAGE=3.3V
MAKE_BASE=TRUE

PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5

6 7 8 36 40 49 50 63 64 77

PPBUS_S5_HS_COMPUTING_ISNS
PPBUS_S5_HS_COMPUTING_ISNS
PPBUS_S5_HS_COMPUTING_ISNS
PPBUS_S5_HS_COMPUTING_ISNS
PPBUS_S5_HS_COMPUTING_ISNS

66 50 7

4
1.8V/1.5V/1.2V/1.05V Rails

PP3V3_S5

PP3V3_S5

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.8V
MAKE_BASE=TRUE

5
3.3V Rails

BRANCH

PAGE

8 OF 109
SHEET

7 OF 86

HEATSINK STANDOFFS

MEMVTT_EN

67 30 8

MEMVTT_EN

8 30 67

=PEG_R2D_C_P<11..8>
=PEG_R2D_C_N<11..8>
=PEG_D2R_P<11..8>
=PEG_D2R_N<11..8>

MAKE_BASE=TRUE
9

Z0902

DP_EXTA_ML_C_P<3..0>

81 75

STDOFF-4.5OD.98H-1.1-3.48-TH

80

DP_IG_ML_P<3..0>

TP_DP_IG_B_MLP<3..0>

80

DP_IG_ML_N<3..0>

TP_DP_IG_B_MLN<3..0>

17

DP_EXTA_AUXCH_C_P

DP_EXTA_AUXCH_C_P

8 17 75 80 81

17

MAKE_BASE=TRUE

DP_EXTA_ML_C_N<3..0>

81 75

PEG_R2D_C_P<11..8>
PEG_R2D_C_N<11..8>
PEG_D2R_P<11..8>
PEG_D2R_N<11..8>

78
78
78
78

PCIE_T29_R2D_C_P<3..0>
PCIE_T29_R2D_C_N<3..0>
PCIE_T29_D2R_P<3..0>
MAKE_BASE=TRUE
PCIE_T29_D2R_N<3..0>

34
81

MAKE_BASE=TRUE

81 80
75 17 8

34 81

83 34 17 8

DP_EXTA_AUXCH_C_N

81 80
75 17 8

DP_EXTA_AUXCH_C_N

DP_EXTA_AUXCH_C_N

71 62 61 57 54 52 51 50 49 48
23 22 20 19 18 17 16 12 8 7 6
46 42 41 40 37 36 33 29 27 26
85 77 75 74 73 72

8 17 75 80 81

MAKE_BASE=TRUE

PP3V3_S0

83 34 17 8

Z0904
STDOFF-4.5OD.98H-1.1-3.48-TH

FW_PLUG_DET_L

40 39 8

FW643_WAKE_L

FW_PLUG_DET_L

8 19 40

FW643_WAKE_L

8 39 40

MAKE_BASE=TRUE
17 8

BELOW CPU

17 8

MAKE_BASE=TRUE
17 8

TP_SMC_EXCARD_PWR_EN

TP_SMC_EXCARD_PWR_EN

17 8

DP_IG_C_CTRL_CLK
DP_IG_C_CTRL_DATA
DP_IG_D_CTRL_CLK
DP_IG_D_CTRL_DATA

34 17 8

5%
1/16W
MF-LF
402 2

17

R0921

R0922

R0923

2.2K

2.2K

2.2K

2.2K

5%
1/16W
MF-LF
402 2

5%
1/16W
MF-LF
402 2

DP_T29SNK0_ML_C_P<3..0>
DP_T29SNK0_ML_C_N<3..0>
DP_T29SNK0_AUXCH_C_P
MAKE_BASE=TRUE
DP_T29SNK0_AUXCH_C_N

34 83

MAKE_BASE=TRUE

34 83

MAKE_BASE=TRUE

8 17 34 83

DP_T29SNK1_HPD

8 17 34 83

DP_T29SNK1_HPD

8 17 34

MAKE_BASE=TRUE

TP_DP_IG_D_MLP<3..0>
TP_DP_IG_D_MLN<3..0>
DP_T29SNK1_AUXCH_C_P
DP_T29SNK1_AUXCH_C_N

17
83 34 17 8
8 17
83 34 17 8
8 17

DP_IG_C_CTRL_CLK
DP_IG_C_CTRL_DATA
MAKE_BASE=TRUE
DP_IG_D_CTRL_CLK
MAKE_BASE=TRUE
DP_IG_D_CTRL_DATA
MAKE_BASE=TRUE

MAKE_BASE=TRUE

Z0920

R0920

5%
1/16W
MF-LF
402 2
40 19 8

8 17 34

MAKE_BASE=TRUE

TP_DP_IG_C_MLP<3..0>
TP_DP_IG_C_MLN<3..0>
DP_T29SNK0_AUXCH_C_P
DP_T29SNK0_AUXCH_C_N

17

MAKE_BASE=TRUE

MAKE_BASE=TRUE

DP_T29SNK0_HPD
MAKE_BASE=TRUE

34 81

17

DP_EXTA_AUXCH_C_P

81 80 75 17 8

DP_T29SNK0_HPD

34 17 8

34 81

MAKE_BASE=TRUE

MAKE_BASE=TRUE
81 80 75 17 8

1
T29 DP Ports

CPU signals

DP_T29SNK1_ML_C_P<3..0>
DP_T29SNK1_ML_C_N<3..0>
DP_T29SNK1_AUXCH_C_P
MAKE_BASE=TRUE
DP_T29SNK1_AUXCH_C_N

34 83

MAKE_BASE=TRUE

34 83

MAKE_BASE=TRUE

8 17 34 83
8 17 34 83

MAKE_BASE=TRUE

8 17
8 17

MAKE_BASE=TRUE

TP_BCM57765_TRAFFICLED_L

37 8

TP_BCM57765_TRAFFICLED_L

8 37

NC_BCM57765_CE_L_MS_INS_L

8 37

TP_LVDS_IG_B_CLKP

6 8 18 80

TP_LVDS_IG_B_CLKN

6 8 18 80

MAKE_BASE=TRUE

STDOFF-4.5OD.98H-1.1-3.48-TH

16 8

16 8
16 8
16 8
81 16 8

FAN STANDOFF

LEFT OF CPU

81 16 8

Z0905
STDOFF-4.5OD.98H-1.1-3.48-TH
1

81 16 8
81 16 8

NC_PCIE_EXCARD_D2RN
NC_PCIE_EXCARD_D2RP
NC_PCIE_EXCARD_R2D_CN
NC_PCIE_EXCARD_R2D_CP
NC_PCIE_CLK100M_EXCARDN
NC_PCIE_CLK100M_EXCARDP

NC_PCIE_EXCARD_D2RN
TRUE
MAKE_BASE=TRUE
NC_PCIE_EXCARD_D2RP
TRUE
MAKE_BASE=TRUE
NC_PCIE_EXCARD_R2D_CN
TRUE
MAKE_BASE=TRUE
NC_PCIE_EXCARD_R2D_CP
TRUE
MAKE_BASE=TRUE
NC_PCIE_CLK100M_EXCARDN
TRUE
MAKE_BASE=TRUE
NC_PCIE_CLK100M_EXCARDP
TRUE
MAKE_BASE=TRUE

PCIE_PCH_D2R_N<5..8>
PCIE_PCH_D2R_P<5..8>
PCIE_PCH_R2D_C_N<5..8>
PCIE_PCH_R2D_C_P<5..8>
NC_PEG_CLK100MP
NC_PEG_CLK100MN

8 16
8 16

MAKE_BASE=TRUE

PP3V3_S0
1

8 16 81

DP_EXTA_DDC_CLK

MAKE_BASE=TRUE

R0924

R0925

2.2K

2.2K

5%
1/16W
MF-LF
402 2

8 16 81

75 17 8

NC_BCM57765_CE_L_MS_INS_L

37 8

8 16
8 16

NC_PCIE_PCH_D2RN<5..8>
NC_PCIE_PCH_D2RP<5..8>
NC_PCIE_PCH_R2D_CN<5..8>
NC_PCIE_PCH_R2D_CP<5..8>
NC_PEG_CLK100MP
NC_PEG_CLK100MN

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

71 62 61 57 54 52 51 50 49 48
23 22 20 19 18 17 16 12 8 7 6
46 42 41 40 37 36 33 29 27 26
85 77 75 74 73 72

5%
1/16W
MF-LF
402 2

TP_LVDS_IG_B_CLKP

80 18 8 6

MAKE_BASE=TRUE

DP_EXTA_DDC_CLK

8 17 75

DP_EXTA_DDC_DATA

8 17 75

TP_LVDS_IG_B_CLKN

80 18 8 6

MAKE_BASE=TRUE
75 17 8

MAKE_BASE=TRUE

DP_EXTA_DDC_DATA
MAKE_BASE=TRUE

75 17 8

18

DP_EXTA_HPD

8 16 81

8 17 75
18

100K
5%
1/16W
MF-LF
402 2

LVDS_IG_B_DATA_N<0..3>

80

NO_TEST=TRUE

NC_LVDS_IG_A_DATAP<3>

80 18 8

NC_LVDS_IG_A_DATAN<3>

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATAP<3>

8 18 80

NC_LVDS_IG_A_DATAN<3>

8 18 80

LVDS_DDC_CLK

6 8 18 74

LVDS_DDC_DATA

6 8 18 74

LCD_BKLT_PWM

8 18 77

LCD_IG_PWR_EN

8 18 74

LCD_BKLT_EN

8 18 77

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

LVDS_DDC_CLK

74 18 8 6

80

NO_TEST=TRUE

80 18 8

MLB MOUNTING (TO C. BRACKET) SCREW HOLES

LVDS_IG_B_DATA_P<0..3>

NC_LVDS_IG_B_DATAN<0..3>
MAKE_BASE=TRUE

R09081

8 16 81

NC_LVDS_IG_B_DATAP<0..3>
MAKE_BASE=TRUE

DP_EXTA_HPD

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

OMIT

OMIT

Z0906

Z0907

3R2P5

16 8

NC_PCH_CLKOUT_DPN

NC_PCH_CLKOUT_DPN
TRUE
MAKE_BASE=TRUE

8 16

16 8

NC_PCH_CLKOUT_DPP

NC_PCH_CLKOUT_DPP
TRUE
MAKE_BASE=TRUE

8 16

3R2P5

LVDS_DDC_DATA

74 18 8 6

77

TP_ISSP_SCLK_P1_1

PPBUS_SW_LCDBKLT_PWR
MAKE_BASE=TRUE

53 8

8 53

TP_ISSP_SDATA_P1_0

8 53

LCD_BKLT_PWM

77 18 8

MAKE_BASE=TRUE

PPBUS_SW_BKL

8 77

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.375 MM
VOLTAGE=12.6V
MAKE_BASE=TRUE

5%
1/16W
MF-LF
402

LCD_IG_PWR_EN

74 18 8

MAKE_BASE=TRUE

LCD_BKLT_EN

77 18 8

PPBUS_SW_BKL

TP_ISSP_SCLK_P1_1

MAKE_BASE=TRUE

R0910

MAKE_BASE=TRUE

8 77

MAKE_BASE=TRUE

TP_ISSP_SDATA_P1_0

53 8

NC_USB_HUB1_OCS4

24 8

MAKE_BASE=TRUE

MLB MOUNTING (TO TOPCASE) SCREW HOLES

NC_USB_HUB1_OCS4

8 24

NC_USB_HUB2_OCS4

8 24

PU_USB_HUB2_PRT4_P

8 24

PU_USB_HUB2_PRT4_N

8 24

MAKE_BASE=TRUE

NC_USB_HUB2_OCS4

24 8

MAKE_BASE=TRUE

OMIT

Z0908
3R2P5

OMIT

OMIT

Z0909

Z0910

3R2P5

80 8

NC_FSB_CLK133M_PCH_P
MAKE_BASE=TRUE

3R2P5

80 8

8 80

NC_FSB_CLK133M_PCH_N

8 80

NO_TEST=TRUE

PU_USB_HUB2_PRT4_P

24 8

NC_FSB_CLK133M_PCH_N
MAKE_BASE=TRUE

NC_FSB_CLK133M_PCH_P

DPA PWR SW : Nostuff, Backup

MAKE_BASE=TRUE

NO_TEST=TRUE

PU_USB_HUB2_PRT4_N

24 8

MAKE_BASE=TRUE

U0950

TPS2553
T29BST:N

OMIT

OMIT

Z0911

Z0912

R0960

3R2P5

3R2P5

77 64 63 50 49 40 36 7 6
1

PPBUS_G3H

30 26 24 23 22 20 19 17 7 6
85 76 74 73 72 66 56 46

PP3V3_S5

SOT-23

1 IN

PP15V_T29

ILIM 5

5%
1/8W
MF-LF
805

SMC_S4_WAKESRC_EN

76 73 46 45

3 EN

ZS0900

ZS0901

ZS0902

1.4DIA-SHORT-EMI-MLB-K19-K24

1.4DIA-SHORT-EMI-MLB-K19-K24

SM

SM

SM

1.4DIA-SHORT-EMI-MLB-K19-K24

1.4DIA-SHORT-EMI-MLB-K19-K24

1.4DIA-SHORT-EMI-MLB-K19-K24

SM

20K

5%
1/16W
MF-LF

2 402

0.01UF

10%
10V 2
X5R
201

10%
10V 2
X5R
201

B
PP3V3_S3

R0915 1

ZS0909

SM
1

75

T29_A_BIAS_R2DN0

75

R0971 201
T29_A_BIAS

76 75 8

201
1/20W

51
1

2 5%

MF

C0970

VOLTAGE=3.3V

80 75

T29_A_BIAS_R2DN1
VOLTAGE=3.3V

MF

80 75

T29_A_RSVD_N
T29_A_RSVD_P

R0917 201
R09181/20W
201

0
1
0
1

2 5%
MF

2 5%

1/20W

T29_A_BIAS_R2DP0

2 5%

5%
1/16W
MF-LF
402

NO STUFF

1/20W

51

R0970

10K

T29_A_BIAS_R2DP1

SM

R0950

C0964 1

ZS0908

DP_A_BIAS2

48 33 32 31 30 26 24 18 7 6
73 72 55 54 50

ZS0903

75

0.01UF

10%
10V 2
X5R
201

1.4DIA-SHORT-EMI-MLB-K19-K24

C0962

0.01UF

EMI IO (SHORT) POGO PINS

DP_A_BIAS0

36 75 76

NOSTUFF

C0960

75

T29_A_HV_EN

FAULT* 4
GND

T29_A_BIAS

75 76

DPAPWR_ILIM

7 36 76

76 75 8

PP3V3_SW_DPAPWR

OUT 6

NOSTUFF

NO STUFF1

R0916

NO STUFF

R0903

10K

10K

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

USB_T29A_N
USB_T29A_P

NO STUFF1

R0904

10K

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

USB_EXTC_N
USB_EXTC_P

24 80
24 80

NO STUFF

R0905

10K

R0906
10K

5%
1/16W
MF-LF
402

PU_USB_HUB2_PRT4_N
PU_USB_HUB2_PRT4_P

24 80
24 80

8 24
8 24

MF

75

C0971 1

NO STUFF

0.01UF

10%
10V
X5R 2
201

0.01UF

10%
10V
X5R 2
201

TP_CPU_VTT_SELECT

TP_CPU_VTT_SELECT

MAKE_BASE=TRUE

Digital Ground
EMI TALL POGO PINS

Unused T29 Ports


R0973 201

ZS0904

ZS0905

ZS0906

ZS0907

2.0DIA-TALL-EMI-MLB-M97-M98

2.0DIA-TALL-EMI-MLB-M97-M98

2.0DIA-TALL-EMI-MLB-M97-M98

2.0DIA-TALL-EMI-MLB-M97-M98

SM

SM

SM

SM

R0972

51
1

2 5%

1/20W

51

201
1/20W

T29_A_BIAS_D2RP1

2 5%
MF

VOLTAGE=3.3V

C0972

GND
76

VOLTAGE=3.3V

OUT

T29_D2R_P<2..3>

OUT

T29_D2R_N<2..3>

83

IN

T29_R2D_C_P<2..3>

83

IN

T29_R2D_C_N<2..3>

34

IN

34

IN

T29_LSEO<2>
T29_LSEO<3>

83

NC_T29_D2RP<2..3>
MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V

34

NO_TEST=TRUE

83

C0973 1

NC_T29_D2RN<2..3>
MAKE_BASE=TRUE

34

NO_TEST=TRUE

0.01UF

10%
10V
X5R 2
201

0.01UF

10%
10V
X5R 2
201

T29_A_BIAS_D2RN1

MF
76

Heat Spreader Holes for T29, PCH

NC_T29_R2D_CP<2..3>
MAKE_BASE=TRUE

34

NO_TEST=TRUE

NC_T29_R2D_CN<2..3>
MAKE_BASE=TRUE

34

NO_TEST=TRUE

T29_LSOE<2>
T29_LSOE<3>

MAKE_BASE=TRUE
MAKE_BASE=TRUE

OUT

34

OUT

34

SYNC_MASTER=K91_MLB

SYNC_DATE=05/15/2010

PAGE TITLE

Signal Aliases
DRAWING NUMBER

Z0950

Z0951

Z0952

STDOFF-4.0OD1.85H-SM

STDOFF-4.0OD1.85H-SM

STDOFF-4.0OD1.85H-SM

T29 JTAG

34 23 19 8

IN

34 19 8

IN

OUT

JTAG_ISP_TCK

JTAG_ISP_TCK

OUT

8 19 23 34

JTAG_ISP_TDI

OUT

8 19 34

MAKE_BASE=TRUE

JTAG_ISP_TDI
MAKE_BASE=TRUE

JTAG_ISP_TDO

JTAG_ISP_TDO

MAKE_BASE=TRUE

72 8

TP_P1V5S3RS0_RAMP_DONE

TP_P1V5S3RS0_RAMP_DONE

IN

8 72

TP_DDRREG_PGOOD

IN

8 67

MAKE_BASE=TRUE
67 8

TP_DDRREG_PGOOD
MAKE_BASE=TRUE

IN

8 19 34

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SIZE

D
REVISION

34 19 8

Apple Inc.

Unused PGOOD signal

BRANCH

PAGE

9 OF 109
SHEET

8 OF 86

OMIT_TABLE

NOTE:

CRITICAL

IN

78 17

IN

78 17

IN

78 17

IN

78 17

IN

78 17

OUT

78 17

OUT

78 17

OUT

78 17

OUT

78 17

OUT

78 17

OUT

78 17

OUT

78 17

OUT

78 17

OUT

78 17

OUT

78 17

OUT

78 17

OUT

78 17

OUT

78 17

OUT

78 17

OUT

78 17

70 68 45
22 20 17
10 9 7 6
16 14 12
40 36 23
73

OUT

78 17

OUT

78 17

OUT

24.9
1

DMI_TX_0
DMI_TX_1
DMI_TX_2
DMI_TX_3

FDI_DATA_N<4>
FDI_DATA_N<5>
FDI_DATA_N<6>
FDI_DATA_N<7>

W6
V4
Y2
AC9

FDI_DATA_P<0>
FDI_DATA_P<1>
FDI_DATA_P<2>
FDI_DATA_P<3>

U6
W10
W3
AA7

FDI0_TX_0
FDI0_TX_1
FDI0_TX_2
FDI0_TX_3

FDI_DATA_P<4>
FDI_DATA_P<5>
FDI_DATA_P<6>
FDI_DATA_P<7>

W7
T4
AA3
AC8

FDI1_TX_0
FDI1_TX_1
FDI1_TX_2
FDI1_TX_3

OUT

78 17

OUT

78 17

OUT

78 17

OUT

78 17

IN

78 17

IN

FDI_FSYNC<0>
FDI_FSYNC<1>

78 17

IN

FDI_INT

78 17

IN

78 17

IN

AA11
AC12
U11

FDI_LSYNC<0>
FDI_LSYNC<1>
EDP_COMP

EDP_HPD

FDI0_TX_0*
FDI0_TX_1*
FDI0_TX_2*
FDI0_TX_3*
FDI1_TX_0*
FDI1_TX_1*
FDI1_TX_2*
FDI1_TX_3*

FDI0_FSYNC
FDI1_FSYNC
FDI_INT

AA10
AG8

FDI0_LSYNC
FDI1_LSYNC

AD2
AF3

EDP_ICOMPO
EDP_COMPIO

PLACE_NEAR=U1000.AF3:12.7MM

AG11

BGA
(1 OF 9)

DMI_TX_0*
DMI_TX_1*
DMI_TX_2*
DMI_TX_3*

U7
W11
W1
AA6

OUT

78

K3
M7
P4
T3

EDP_HPD

EDP

R1031
1

10K

1%
1/16W
MF-LF
402

NC_EDP_AUXN
NC_EDP_AUXP

AG4
AF4

PLACE_NEAR=U1000.AG11:12.7MM

6
6
6
6

6
6
6

PEG_ICOMPI G3
PEG_ICOMPO G1
PEG_RCOMPO G4

SANDY-BRIDGE
MOBILE-2C-35W

DMI_RX_0
DMI_RX_1
DMI_RX_2
DMI_RX_3

FDI_DATA_N<0>
FDI_DATA_N<1>
FDI_DATA_N<2>
FDI_DATA_N<3>

78 17

2
1%
1/16W
MF-LF
402

DMI_N2S_N<0>
DMI_N2S_N<1>
DMI_N2S_N<2>
DMI_N2S_N<3>

K1
M8
N4
R2

78 17

PP1V05_S0
R1030

N3
P7
P3
P11

DMI_N2S_P<0>
DMI_N2S_P<1>
DMI_N2S_P<2>
DMI_N2S_P<3>

OUT

78 17

DMI_S2N_P<0>
DMI_S2N_P<1>
DMI_S2N_P<2>
DMI_S2N_P<3>

U1000

DMI_RX_0*
DMI_RX_1*
DMI_RX_2*
DMI_RX_3*

PCI EXPRESS BASED INTERFACE SIGNALS

IN

78 17

M2
P6
P1
P10

DMI

78 17

DMI_S2N_N<0>
DMI_S2N_N<1>
DMI_S2N_N<2>
DMI_S2N_N<3>

INTEL FLEXIBLE DISPLAY INTERFACE SIGNALS

IN

EMBEDDED DISPLAY PORT

IN

78 17

EDP_AUX*
EDP_AUX

NC_EDP_TXN<0>
NC_EDP_TXN<1>
NC_EDP_TXN<2>
NC_EDP_TXN<3>

AC3
AC4
AE11
AE7

EDP_TX_0*
EDP_TX_1*
EDP_TX_2*
EDP_TX_3*

NC_EDP_TXP<0>
NC_EDP_TXP<1>
NC_EDP_TXP<2>
NC_EDP_TXP<3>

AC1
AA4
AE10
AE6

EDP_TX_0
EDP_TX_1
EDP_TX_2
EDP_TX_3

Intel Doc 438297 Huron River SFF DG rev1.0 section 2.2.1 recommendation.

NOTE: eDP_COMPIO and eDP_ICOMPO can not be left floating


even if internal Graphics is disabled since they are
shared with other interfaces.

NOTE: The EDP_HPD processor input is a low voltage active low signal.
Therefore, an inverting level shifter is required on the motherboard
to convert the active high signal from Embedded DisplayPort sink device
to low voltage signals for the processor
(refer to latest Processor EDS for DC specifications).
If HPD is disabled while eDP interface is still enabled,
connect it to CPU VCCIo via a 10-kOhm pull-up resistor on the motherboard.
This signal can be left as no-connect if entire eDP interface is disabled.

78 23 9
78 23 9
78 23 9
78 23 9
78 23 9

23 9

CPU_CFG<7>
CPU_CFG<6>
CPU_CFG<5>
CPU_CFG<4>
CPU_CFG<2>
NOSTUFF

R1042

78 23

R1044

R1045

1K

1K

5%

5%

5%

1/16W

402

402

1/16W

MF-LF

MF-LF

CRITICAL

PP1V05_S0

6 7 9 10 12 14 16 17 20 22 23
36 40 45 68 70 73

PLACE_NEAR=U1000.G3:12.7MM

1%
1/16W
MF-LF
402

=PEG_D2R_N<0>
=PEG_D2R_N<1>
=PEG_D2R_N<2>
=PEG_D2R_N<3>
=PEG_D2R_N<4>
=PEG_D2R_N<5>
=PEG_D2R_N<6>
=PEG_D2R_N<7>
=PEG_D2R_N<8>
=PEG_D2R_N<9>
=PEG_D2R_N<10>
=PEG_D2R_N<11>
NC_PEG_D2RN<12>
NC_PEG_D2RN<13>
NC_PEG_D2RN<14>
NC_PEG_D2RN<15>

PEG_RX_0*
PEG_RX_1*
PEG_RX_2*
PEG_RX_3*
PEG_RX_4*
PEG_RX_5*
PEG_RX_6*
PEG_RX_7*
PEG_RX_8*
PEG_RX_9*
PEG_RX_10*
PEG_RX_11*
PEG_RX_12*
PEG_RX_13*
PEG_RX_14*
PEG_RX_15*

H22
J21
B22
D21
A19
D17
B14
D13
A11
B10
G8
A8
B6
H8
E5
K7

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

K22
K19
C21
D19
C19
D16
C13
D12
C11
C9
F8
C8
C5
H6
F6
K6

=PEG_D2R_P<0>
=PEG_D2R_P<1>
=PEG_D2R_P<2>
=PEG_D2R_P<3>
=PEG_D2R_P<4>
=PEG_D2R_P<5>
=PEG_D2R_P<6>
=PEG_D2R_P<7>
=PEG_D2R_P<8>
=PEG_D2R_P<9>
=PEG_D2R_P<10>
=PEG_D2R_P<11>
NC_PEG_D2RP<12>
NC_PEG_D2RP<13>
NC_PEG_D2RP<14>
NC_PEG_D2RP<15>

PEG_TX_0*
PEG_TX_1*
PEG_TX_2*
PEG_TX_3*
PEG_TX_4*
PEG_TX_5*
PEG_TX_6*
PEG_TX_7*
PEG_TX_8*
PEG_TX_9*
PEG_TX_10*
PEG_TX_11*
PEG_TX_12*
PEG_TX_13*
PEG_TX_14*
PEG_TX_15*

G22
C23
D23
F21
H19
C17
K15
F17
F14
A15
J14
H13
M10
F10
D9
J4

=PEG_R2D_C_N<0> OUT
=PEG_R2D_C_N<1> OUT
=PEG_R2D_C_N<2> OUT
=PEG_R2D_C_N<3> OUT
=PEG_R2D_C_N<4> OUT
=PEG_R2D_C_N<5> OUT
=PEG_R2D_C_N<6> OUT
=PEG_R2D_C_N<7> OUT
=PEG_R2D_C_N<8> OUT
=PEG_R2D_C_N<9> OUT
=PEG_R2D_C_N<10> OUT
=PEG_R2D_C_N<11> OUT
NC_PEG_R2D_CN<12> OUT
NC_PEG_R2D_CN<13> OUT
NC_PEG_R2D_CN<14> OUT
NC_PEG_R2D_CN<15> OUT

PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

F22
A23
D24
E21
G19
B18
K17
G17
E14
C15
K13
G13
K10
G10
D8
K4

=PEG_R2D_C_P<0> OUT
=PEG_R2D_C_P<1> OUT
=PEG_R2D_C_P<2> OUT
=PEG_R2D_C_P<3> OUT
=PEG_R2D_C_P<4> OUT
=PEG_R2D_C_P<5> OUT
=PEG_R2D_C_P<6> OUT
=PEG_R2D_C_P<7> OUT
=PEG_R2D_C_P<8> OUT
=PEG_R2D_C_P<9> OUT
=PEG_R2D_C_P<10> OUT
=PEG_R2D_C_P<11> OUT
NC_PEG_R2D_CP<12> OUT
NC_PEG_R2D_CP<13> OUT
NC_PEG_R2D_CP<14> OUT
NC_PEG_R2D_CP<15> OUT

IN

78 23 9

IN

78 23 9

IN

78 23 9

IN

78 23 9

IN

78 23 9

IN

78 23 9

IN

78 23 9

IN

78 23 9

IN

78 23

IN

78 23

IN

78 23

IN

78 23

IN

6 7 12 15 49 78 23
69
78 23

IN

78 23

IN

78 23

IN

23 9

IN

23

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

R1064

IN

49.9

49.9

IN

IN

1%
1/16W
MF-LF
402

1%
1/16W
MF-LF
402

IN

IN

IN

IN

IN

Note. VOLTAGE=1.05V

IN

Note. VOLTAGE=0V

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

PLACE_NEAR=U1000.H43:50.8MM
PLACE_SIDE=BOTTOM

PPVCORE_S0_CPU

6 7 12 14 49 69

PPVCORE_S0_AXG
NOSTUFF

NOSTUFF

R1070

2
PLACE_NEAR=U1000.H45:50.8MM
PLACE_SIDE=BOTTOM
Note. VOLTAGE=1.25V
Note. VOLTAGE=0V

NOSTUFF

IN

CPU_CFG<0>
CPU_CFG<1>
CPU_CFG<2>
CPU_CFG<3>
CPU_CFG<4>
CPU_CFG<5>
CPU_CFG<6>
CPU_CFG<7>
CPU_CFG<8>
CPU_CFG<9>
CPU_CFG<10>
CPU_CFG<11>
CPU_CFG<12>
CPU_CFG<13>
CPU_CFG<14>
CPU_CFG<15>
CPU_CFG<16>
CPU_CFG<17>

B50
C51
B54
D53
A51
C53
C55
H49
A55
H51
K49
K53
F53
G53
L51
F51
D52
L53

RSVD_28 BE7
RSVD_29 BG7

U1000

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17

BGA
(5 OF 9)
RESERVED

CPU_MEM_VREFDQ_A 9
CPU_MEM_VREFDQ_B 9

RSVD_30
RSVD_31
RSVD_32
RSVD_33

N42
NC
L42
NC
L45
NC
L47

RSVD_34
RSVD_35
RSVD_36
RSVD_37
RSVD_38

M13
NC
M14
NC
U14
NC
W14
NC
P13

NC

NC

RSVD_39 AT49
NC
RSVD_40 K24 NC
RSVD_41
RSVD_42
RSVD_43
RSVD_44

CPU_VCC_VALSENSE_P
CPU_VCC_VALSENSE_N

H43 VCC_VAL_SENSE
K43 VSS_VAL_SENSE

CPU_AXG_VALSENSE_P
CPU_AXG_VALSENSE_N

H45 VAXG_VAL_SENSE
K45 VSSAXG_VAL_SENSE

TP_CPU_VCC_DIE_SENSE

F48 VCC_DIE_SENSE

AH2
NC
AG13
NC
AM14
NC
AM15

NC

RSVD_45 N50 NC

NOSTUFF

R1065

R1071

49.9

49.9

1%
1/16W
MF-LF
402

1%
1/16W
MF-LF
402

85 51

OUT

85 51

OUT

DC_TEST_A4
DC_TEST_C4
DC_TEST_D3
DC_TEST_D1
DC_TEST_A58
DC_TEST_A59
DC_TEST_C59
DC_TEST_A61
DC_TEST_C61
DC_TEST_D61
DC_TEST_BD61
DC_TEST_BE61
DC_TEST_BE59
DC_TEST_BG61
DC_TEST_BG59
DC_TEST_BG58
DC_TEST_BG4
DC_TEST_BG3
DC_TEST_BE3
DC_TEST_BG1
DC_TEST_BE1
DC_TEST_BD1

H48 RSVD_6
K48 RSVD_7

CPU_THERMD_P
CPU_THERMD_N

BA19 RSVD_8
RSVD_9
RSVD_10
RSVD_11
RSVD_12
RSVD_13
RSVD_14
RSVD_15
RSVD_16
RSVD_17
RSVD_18
RSVD_19
RSVD_20
RSVD_21
RSVD_22
RSVD_23
RSVD_24
RSVD_25
RSVD_26
RSVD_27

NC
AV19
NC
AT21
NC
BB21
NC
BB19
NC
AY21
NC
BA22
NC
AY22
NC
AU19
NC
AU21
NC
BD21
NC
BD22
NC
BD25
NC
BD26
NC
BG22
NC
BE22
NC
BG26
NC
BE26
NC
BF23
NC
BE24
NC

PLACE_NEAR=U1000.K45:50.8MM
PLACE_SIDE=BOTTOM

PLACE_NEAR=U1000.K43:50.8MM
PLACE_SIDE=BOTTOM

NOTE: Intel validation sense lines per


doc 439028 rev1.0 HR_PPDG sections 6.2.1 and 6.3.1.

6
6
6
6
6
6
6
6
8
8
8
8

A4
TP_CPU_DC_TEST_A4
C4
CPU_DC_TEST_C4_D3
D3
D1
TP_CPU_DC_TEST_D1
A58 TP_CPU_DC_TEST_A58
A59 CPU_DC_TEST_C59_A59
C59
A61 CPU_DC_TEST_C61_A61
C61
D61 TP_CPU_DC_TEST_D61
BD61 TP_CPU_DC_TEST_BD61
BE61 CPU_DC_TEST_BE59_BE61
BE59
BG61 CPU_DC_TEST_BG59_BG61
BG59
BG58 TP_CPU_DC_TEST_BG58
BG4
TP_CPU_DC_TEST_BG4
BG3
CPU_DC_TEST_C4_BE3_BG3
BE3
BG1
CPU_DC_TEST_C4_BE1_BG1
BE1
BD1
TP_CPU_DC_TEST_BD1

6
6

NOTE: Intel is investigating future processor VREF_DQ generation to replace M1 and M2.
This would require routing processor signal balls BE7 and BG7 for Sandy Bridge 2-core
to SO-DIMM connectors directly. FETs are needed in order to avoid potential leakage while system is in S3 state.
NOSTUFF

6
6

6
6

R1021

6
31 27

PP0V75_S3_MEM_VREFDQ_A

CPU_MEM_VREFDQ_A

5%
1/16W
MF-LF
402

1K

NOSTUFF

R1023
31 29

PP0V75_S3_MEM_VREFDQ_B

0
5%
1/16W
MF-LF
402

6
6

R1020

1 NOSTUFF
1%
1/16W
MF-LF
402

CPU_MEM_VREFDQ_B

1 NOSTUFF

R1022
1K
1%
1/16W
MF-LF

6
6

2 402

CPU_CFG<16>

CPU_CFG<3>
CPU_CFG<1>
9 CPU_CFG<0>

78 23 9

1K
1/16W

OMIT_TABLE

24.9
1

78 23 9

EDP
1

CPU_PEG_COMP

Intel provides an internal pull-up OF 5-15k to VCCIO on all CFG signals.

R1010
78

78 17

SANDY-BRIDGE

MOBILE-2C-35W

402

NOSTUFF

R1046

R1047

1K

1K

1K

1K

1K

1K

5%

5%

5%

5%

5%

5%

1/16W

MF-LF

NOSTUFF

402

R1040

1/16W

402

NOSTUFF
1

1/16W

MF-LF

MF-LF
2

NOSTUFF
1

402

R1043

1/16W

MF-LF
2

NOSTUFF

R1041

402

R1049

MF-LF
402

1/16W

1/16W

MF-LF
2

NOSTUFF
1

MF-LF
402

PAGE TITLE

CPU DMI/PEG/FDI/RSVD
DRAWING NUMBER
These can be Placed close to J2500 and Only for debug access

Apple Inc.
FOR SANDYBRIDGE PROCESSOR
CFG [7] :PEG DEFER TRAINING

1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB

CFG [6:5] :PCIE BIFURCATION

11 = 1 X16 (DEFAULT)

CFG [4] :eDP ENABLE/DISABLE

1 = DISABLED

CFG [3] :PCIE x4 LANE REVERSAL

1 = NORMAL OPERATION

0 = LANES REVERSED

CFG [2] :PCIE x16 LANE REVERSAL

1 = NORMAL OPERATION

0 = LANES REVERSED

SIZE

REVISION

10 = 2 X8

NOTICE OF PROPRIETARY PROPERTY:

0 = WAIT FOR BIOS

01 = RSVD

00 = X8, X4, X4

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

0 = ENABLED

BRANCH

PAGE

10 OF 109
SHEET

9 OF 86

14 12 7

PP1V05_S0_CPU_VCCPQE

OMIT_TABLE

PP1V05_S0

CRITICAL

23 22 20 17 16 14 12 10 9 7 6
73 70 68 45 40 36

R1140

U1000
NOSTUFF

R1100

1K

R1101

51

5%

402

1/16W

402

MF-LF

OUT

CPU_PROC_SEL_L

F49 PROC_SELECT*

OUT

CPU_CATERR_L

C49 CATERR*

C
78

78 45 19

R1103
CPU_PROCHOT_L

78 19

78 30 17

IN

78 17

R1121

PM_MEM_PWRGD

130

78 23 19

PM_THRMTRIP_L

D45 THERMTRIP*

IN

PM_SYNC

C48 PM_SYNC

IN

CPU_PWRGD

B46 UNCOREPWRGOOD

PM_MEM_PWRGD_R

1%
1/16W
MF-LF
402

BE45 SM_DRAMPWROK

PLT_RESET_LS1V1_L
30

OUT

D44 RESET*

CPU_MEM_RESET_L

AT30 SM_DRAMRST*

CPU_SM_RCOMP<0>
CPU_SM_RCOMP<1>
CPU_SM_RCOMP<2>

78
78
78

23 22 20 17 16 14 12 10 9 7 6
73 70 68 45 40 36

BF44 SM_RCOMP_0
BE43 SM_RCOMP_1
BG43 SM_RCOMP_2

PP1V05_S0

R1126 1
1%
1/16W
MF-LF
402

IN

PLT_RST_BUF_L

2
2

R1112

140

75

26 23

IN

16 78

IN

16 78

DPLL_REF_CLKP
DPLL_REF_CLKN

DPLL_REF_CLK AG3
DPLL_REF_CLK* AG1

ITPCPU_CLK100M_P
ITPCPU_CLK100M_N

BCLK_ITP N59
BCLK_ITP* N58
(IPU)
(IPU)

PRDY* N53
PREQ* N55

XDP_CPU_PRDY_L
XDP_CPU_PREQ_L

(IPU)
(IPU)
(IPU)

TCK L56
TMS L55
TRST* J58

XDP_CPU_TCK
XDP_CPU_TMS
XDP_CPU_TRST_L

(IPU)

TDI M60
TDO L59

Unused eDP CLK


IN

16 78

IN

16 78

OUT

23 78

IN

23 78

IN

23 78

IN

23 78

IN

23 78

IN

23 78

R1141
1K

5%
1/16W
MF-LF
2 402

200
1%
1/16W
MF-LF
402

OUT

C45 PROCHOT*

R1113

25.5

R1114

1%

1%

1/16W

1/16W

1/16W

MF-LF

MF-LF

MF-LF

402

402

200

1%

402

JTAG & BPM

R1120

A48 PECI

CPU_PROCHOT_R_L

5%
1/16W
MF-LF
402

PP1V5_S3RS0

CPU_PECI

PWR MGMT

85 73 72 30 15 12 7 6

BI

BI

DDR3 MISC

78 68 46

56

CLOCKS

C57 PROC_DETECT*
NC

402

17

5%
1/16W
MF-LF
2 402

402

MF-LF
2

DMI_CLK100M_CPU_P
DMI_CLK100M_CPU_N

BCLK J3
BCLK* H2

BGA
(2 OF 9)

1/16W

MF-LF

R1102
5%

1/16W

MF-LF

5%

1K

SANDY-BRIDGE
MOBILE-2C-35W

NOSTUFF
1K

5%

1/16W

62

R1104

THERMAL

NOSTUFF

DBR* K58
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)

BPM_0*
BPM_1*
BPM_2*
BPM_3*
BPM_4*
BPM_5*
BPM_6*
BPM_7*

XDP_CPU_TDI
XDP_CPU_TDO

OUT

23 78

XDP_DBRESET_L

OUT

23 26 78

XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>
XDP_BPM_L<4>
XDP_BPM_L<5>
XDP_BPM_L<6>
XDP_BPM_L<7>

G58
E55
E59
G55
G59
H60
J59
J61

BI

23 78

BI

23 78

BI

23 78

BI

23 78

BI

23

BI

23

BI

23

BI

23

R1111

10K
5%
1/16W
MF-LF

402

R1125
43.2
2

1
1%
1/16W
MF-LF
402

A
PAGE TITLE

CPU CLOCK/MISC/JTAG
DRAWING NUMBER

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

11 OF 109
SHEET

10 OF 86

OMIT_TABLE

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28 27

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 27

OUT

79 27

OUT

79 27

OUT

79 27

OUT

79 27

OUT

79 27

OUT

MEM_A_BA<0>
MEM_A_BA<1>
MEM_A_BA<2>

BD37
BF36
BA28

MEM_A_CAS_L
MEM_A_RAS_L
MEM_A_WE_L

BE39
BD39
AT41

U1000
BGA
(3 OF 9)

SANDY-BRIDGE

79 28

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

MOBILE-2C-35W

BI

AG6
AJ6
AP11
AL6
AJ10
AJ8
AL8
AL7
AR11
AP6
AU6
AV9
AR6
AP8
AT13
AU13
BC7
BB7
BA13
BB11
BA7
BA9
BB9
AY13
AV14
AR14
AY17
AR19
BA14
AU14
BB14
BB17
BA45
AR43
AW48
BC48
BC45
AR45
AT48
AY48
BA49
AV49
BB51
AY53
BB49
AU49
BA53
BB55
BA55
AV56
AP50
AP53
AV54
AT54
AP56
AP52
AN57
AN53
AG56
AG53
AN55
AN52
AG55
AK56

CRITICAL
SA_CK_0 AU36
SA_CK_0* AV36

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>

SA_CKE_0 AY26

MEM_A_CKE<0>

SA_CK_1 AT40
SA_CK_1* AU40
SA_CKE_1 BB26
SA_CS_0* BB40
SA_CS_1* BC41
SA_ODT_0 AY40
SA_ODT_1 BA41

MEMORY CHANNEL A

BI

79 28

MEM_A_DQ<0>
MEM_A_DQ<1>
MEM_A_DQ<2>
MEM_A_DQ<3>
MEM_A_DQ<4>
MEM_A_DQ<5>
MEM_A_DQ<6>
MEM_A_DQ<7>
MEM_A_DQ<8>
MEM_A_DQ<9>
MEM_A_DQ<10>
MEM_A_DQ<11>
MEM_A_DQ<12>
MEM_A_DQ<13>
MEM_A_DQ<14>
MEM_A_DQ<15>
MEM_A_DQ<16>
MEM_A_DQ<17>
MEM_A_DQ<18>
MEM_A_DQ<19>
MEM_A_DQ<20>
MEM_A_DQ<21>
MEM_A_DQ<22>
MEM_A_DQ<23>
MEM_A_DQ<24>
MEM_A_DQ<25>
MEM_A_DQ<26>
MEM_A_DQ<27>
MEM_A_DQ<28>
MEM_A_DQ<29>
MEM_A_DQ<30>
MEM_A_DQ<31>
MEM_A_DQ<32>
MEM_A_DQ<33>
MEM_A_DQ<34>
MEM_A_DQ<35>
MEM_A_DQ<36>
MEM_A_DQ<37>
MEM_A_DQ<38>
MEM_A_DQ<39>
MEM_A_DQ<40>
MEM_A_DQ<41>
MEM_A_DQ<42>
MEM_A_DQ<43>
MEM_A_DQ<44>
MEM_A_DQ<45>
MEM_A_DQ<46>
MEM_A_DQ<47>
MEM_A_DQ<48>
MEM_A_DQ<49>
MEM_A_DQ<50>
MEM_A_DQ<51>
MEM_A_DQ<52>
MEM_A_DQ<53>
MEM_A_DQ<54>
MEM_A_DQ<55>
MEM_A_DQ<56>
MEM_A_DQ<57>
MEM_A_DQ<58>
MEM_A_DQ<59>
MEM_A_DQ<60>
MEM_A_DQ<61>
MEM_A_DQ<62>
MEM_A_DQ<63>

OMIT_TABLE

CRITICAL

79 28

MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
MEM_A_CKE<1>
MEM_A_CS_L<0>
MEM_A_CS_L<1>
MEM_A_ODT<0>
MEM_A_ODT<1>

SA_DQS_0*
SA_DQS_1*
SA_DQS_2*
SA_DQS_3*
SA_DQS_4*
SA_DQS_5*
SA_DQS_6*
SA_DQS_7*

AL11
AR8
AV11
AT17
AV45
AY51
AT55
AK55

MEM_A_DQS_N<0>
MEM_A_DQS_N<1>
MEM_A_DQS_N<2>
MEM_A_DQS_N<3>
MEM_A_DQS_N<4>
MEM_A_DQS_N<5>
MEM_A_DQS_N<6>
MEM_A_DQS_N<7>

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7

AJ11
AR10
AY11
AU17
AW45
AV51
AT56
AK54

MEM_A_DQS_P<0>
MEM_A_DQS_P<1>
MEM_A_DQS_P<2>
MEM_A_DQS_P<3>
MEM_A_DQS_P<4>
MEM_A_DQS_P<5>
MEM_A_DQS_P<6>
MEM_A_DQS_P<7>

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
SA_MA_15

BG35
BB34
BE35
BD35
AT34
AU34
BB32
AT32
AY32
AV32
BE37
BA30
BC30
AW41
AY28
AU26

MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_A<15>

OUT

27 79

79 28

BI

OUT

27 79

79 28

BI

79 28
27 79

BI

OUT

OUT

27 79

OUT

27 79

OUT

27 79

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

OUT

27 79

79 28

BI

OUT

27 79

79 28

BI

79 28

BI

OUT

27 79

79 28

BI

OUT

27 79

79 28

BI

79 28

BI

BI

27 28 79

79 28

BI

BI

28 79

79 28

BI

BI

28 79

79 28

BI

BI

28 79

79 28

BI

BI

28 79

79 28

BI

BI

28 79

79 28

BI

BI

28 79

79 28

BI

BI

28 79

79 28

BI

79 28

BI

BI

27 28 79

79 28

BI

BI

28 79

79 28

BI

BI

28 79

79 28

BI

BI

28 79

79 28

BI

BI

28 79

79 28

BI

BI

28 79

79 28

BI

BI

28 79

79 28

BI

BI

28 79

79 28

BI

79 28

BI

OUT

27 79

79 28

BI

OUT

27 79

79 28

BI

OUT

27 79

79 28

BI

OUT

27 79

79 28

BI

OUT

27 79

79 29 28

BI

OUT

27 79

79 28

BI

OUT

27 79

79 28

BI

OUT

27 79

79 28

BI

OUT

27 79

79 28

BI

OUT

27 79

79 28

BI

OUT

27 79

79 28

BI

OUT

27 79

79 28

BI

OUT

27 79

79 28

BI

OUT

27 79

79 28

BI

OUT

27 79

79 28

BI

OUT

27 79

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

79 28

BI

SA_BS_0
SA_BS_1
SA_BS_2

79 29

OUT

79 29

OUT

79 29

OUT

SA_CAS*
SA_RAS*
SA_WE*

79 29

OUT

79 29

OUT

79 29

OUT

MEM_B_DQ<0>
MEM_B_DQ<1>
MEM_B_DQ<2>
MEM_B_DQ<3>
MEM_B_DQ<4>
MEM_B_DQ<5>
MEM_B_DQ<6>
MEM_B_DQ<7>
MEM_B_DQ<8>
MEM_B_DQ<9>
MEM_B_DQ<10>
MEM_B_DQ<11>
MEM_B_DQ<12>
MEM_B_DQ<13>
MEM_B_DQ<14>
MEM_B_DQ<15>
MEM_B_DQ<16>
MEM_B_DQ<17>
MEM_B_DQ<18>
MEM_B_DQ<19>
MEM_B_DQ<20>
MEM_B_DQ<21>
MEM_B_DQ<22>
MEM_B_DQ<23>
MEM_B_DQ<24>
MEM_B_DQ<25>
MEM_B_DQ<26>
MEM_B_DQ<27>
MEM_B_DQ<28>
MEM_B_DQ<29>
MEM_B_DQ<30>
MEM_B_DQ<31>
MEM_B_DQ<32>
MEM_B_DQ<33>
MEM_B_DQ<34>
MEM_B_DQ<35>
MEM_B_DQ<36>
MEM_B_DQ<37>
MEM_B_DQ<38>
MEM_B_DQ<39>
MEM_B_DQ<40>
MEM_B_DQ<41>
MEM_B_DQ<42>
MEM_B_DQ<43>
MEM_B_DQ<44>
MEM_B_DQ<45>
MEM_B_DQ<46>
MEM_B_DQ<47>
MEM_B_DQ<48>
MEM_B_DQ<49>
MEM_B_DQ<50>
MEM_B_DQ<51>
MEM_B_DQ<52>
MEM_B_DQ<53>
MEM_B_DQ<54>
MEM_B_DQ<55>
MEM_B_DQ<56>
MEM_B_DQ<57>
MEM_B_DQ<58>
MEM_B_DQ<59>
MEM_B_DQ<60>
MEM_B_DQ<61>
MEM_B_DQ<62>
MEM_B_DQ<63>

AL4
AL1
AN3
AR4
AK4
AK3
AN4
AR1
AU4
AT2
AV4
BA4
AU3
AR3
AY2
BA3
BE9
BD9
BD13
BF12
BF8
BD10
BD14
BE13
BF16
BE17
BE18
BE21
BE14
BG14
BG18
BF19
BD50
BF48
BD53
BF52
BD49
BE49
BD54
BE53
BF56
BE57
BC59
AY60
BE54
BG54
BA58
AW59
AW58
AU58
AN61
AN59
AU59
AU61
AN58
AR58
AK58
AL58
AG58
AG59
AM60
AL59
AF61
AH60

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

MEM_B_BA<0>
MEM_B_BA<1>
MEM_B_BA<2>

BG39
BD42
AT22

SB_BS_0
SB_BS_1
SB_BS_2

MEM_B_CAS_L
MEM_B_RAS_L
MEM_B_WE_L

AV43
BF40
BD45

SB_CAS*
SB_RAS*
SB_WE*

U1000
BGA
(4 OF 9)

SANDY-BRIDGE
MOBILE-2C-35W

MEMORY CHANNEL B

SB_CK_0 BA34
SB_CK_0* AY34

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>

SB_CKE_0 AR22

MEM_B_CKE<0>

SB_CK_1 BA36
SB_CK_1* BB36

MEM_B_CLK_P<1>
MEM_B_CLK_N<1>

SB_CKE_1 BF27

MEM_B_CKE<1>

SB_CS_0* BE41
SB_CS_1* BE47
SB_ODT_0 AT43
SB_ODT_1 BG47

OUT

29 79

OUT

29 79

OUT

29 79

OUT

29 79

OUT

29 79

OUT

29 79

MEM_B_CS_L<0>
MEM_B_CS_L<1>

OUT

29 79

OUT

29 79

MEM_B_ODT<0>
MEM_B_ODT<1>

OUT

29 79

OUT

29 79

SB_DQS_0*
SB_DQS_1*
SB_DQS_2*
SB_DQS_3*
SB_DQS_4*
SB_DQS_5*
SB_DQS_6*
SB_DQS_7*

AL3
AV3
BG11
BD17
BG51
BA59
AT60
AK59

MEM_B_DQS_N<0>
MEM_B_DQS_N<1>
MEM_B_DQS_N<2>
MEM_B_DQS_N<3>
MEM_B_DQS_N<4>
MEM_B_DQS_N<5>
MEM_B_DQS_N<6>
MEM_B_DQS_N<7>

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7

AM2
AV1
BE11
BD18
BE51
BA61
AR59
AK61

MEM_B_DQS_P<0>
MEM_B_DQS_P<1>
MEM_B_DQS_P<2>
MEM_B_DQS_P<3>
MEM_B_DQS_P<4>
MEM_B_DQS_P<5>
MEM_B_DQS_P<6>
MEM_B_DQS_P<7>

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
SB_MA_15

BF32
BE33
BD33
AU30
BD30
AV30
BG30
BD29
BE30
BE28
BD43
AT28
AV28
BD46
AT26
AU22

MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
MEM_B_A<15>

BI

28 29 79

BI

28 79

BI

28 79

BI

28 79

BI

28 79

BI

28 79

BI

28 79

BI

28 79

BI

28 29 79

BI

28 79

BI

28 79

BI

28 79

BI

28 79

BI

28 79

BI

28 79

BI

28 79

OUT

29 79

OUT

29 79

OUT

29 79

OUT

29 79

OUT

29 79

OUT

29 79

OUT

29 79

OUT

29 79

OUT

29 79

OUT

29 79

OUT

29 79

OUT

29 79

OUT

29 79

OUT

29 79

OUT

29 79

OUT

29 79

SYNC_DATE=06/18/2010
PAGE TITLE

CPU DDR3 INTERFACES


DRAWING NUMBER

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

12 OF 109
SHEET

11 OF 86

69 49 15 12 9 7 6

PPVCORE_S0_AXG

OMIT_TABLE

CRITICAL

AG51
AJ17

AB53 VAXG_6
AB55 VAXG_7

AJ21

AB56 VAXG_8
AB58 VAXG_9
AB59 VAXG_10

AJ25
AJ43

AL15
AL16

AD50 VAXG_14
AD51 VAXG_15
AD52 VAXG_16

AL20
AL22

AD53 VAXG_17
AD55 VAXG_18

AL26

AD56 VAXG_19
AD58 VAXG_20
AD59 VAXG_21

AL14

AL45
AL48

AE46 VAXG_22
N45 VAXG_23
P47 VAXG_24

AM16
AM17
AM21

AN42
AN45

P52 VAXG_28
P53 VAXG_29

AN48

P55 VAXG_30
P56 VAXG_31
P61 VAXG_32
T48 VAXG_33
T58 VAXG_34
T59 VAXG_35

AB20
AC13
AD16

T61 VAXG_36
U46 VAXG_37
V47 VAXG_38

AD18
AD21
AE15
AF16
AF20
AG15
AG17
AG20

PP3V3_S0

AG21
AJ14

R1320

49 50 51 52 54 57 61 62 71 72
6 7 8 16 17 18 19 20 22 23 26
27 29 33 36 37 40 41 42 46 48
73 74 75 77 85

402

R1302
130 PLACE_NEAR=U1000.C44:2.54mm

W17
For Future Compatibility

AM25

PLACE_NEAR=R1310.2:2.54mm
1

MF-LF

CPU_VCCIO_SEL

1%
1/16W
MF-LF
402

402 1/16W

PP1V05_S0_CPU_VCCPQE

AN22

R1311
402 1/16W

A44
B43
C44

CPU_VIDALERT_L_R
CPU_VIDSCLK_R
CPU_VIDSOUT_R

VCC_SENSE
VSS_SENSE

F43
G43

CPU_VCCSENSE_P
CPU_VCCSENSE_N

IN

0 1

68 78

R1312
402 1/16W

OUT

68 78

78 68

OUT

Y48 VAXG_55
Y61 VAXG_56

OUT

CPU_AXG_SENSE_P
CPU_AXG_SENSE_N
14 7

CPU_VIDSOUT

2 5% MF-LF

BI

Note. VOLTAGE=1.05V

F45 VAXG_SENSE
G45 VSSAXG_SENSE

Note. VOLTAGE=0V

PP1V8_S0_CPU_VCCPLL_R

68 78

BB3 VCCPLL_1
BC1 VCCPLL_2
BC4 VCCPLL_3

VCCIO_SENSE
VSS_SENSE_VCCIO

AN16
AN17

NOSTUFF

PPVCORE_S0_CPU
PP1V05_S0

CPU_VCCIOSENSE_P
CPU_VCCIOSENSE_N

6 7 9 12 14 49 69

R1360
PLACE_NEAR=U1000.F43:50.8mm
PLACE_SIDE=BOTTOM

NOSTUFF

R1362

100
1%
1/16W
MF-LF
402

100

1%
1/16W
MF-LF
402

PLACEMENT NOTE:

Note. VOLTAGE=0V
Note. VOLTAGE=1.05V
Note. VOLTAGE=0V

NOSTUFF

R13611

PLACE_NEAR=U1000.G43:50.8mm
PLACE_SIDE=BOTTOM

AR26
AR28

PPVCCSA_S0_CPU
65 15 12 7 6

AR30
AR32
AR34
85 73 72 30 15 12 10 7 6

AR36

OUT

68 78

OUT

68 78

OUT

70 78

OUT

70 78

PP1V5_S3RS0

R13821

AR40
AV41

100

PLACE_NEAR=U1000.U10:50.8mm

1%
1/16W
MF-LF
402

AW26

R13801

BA40
BB28

PLACE_NEAR=U1000.BC43:50.8mm 100
1%
PLACE_SIDE=BOTTOM
1/16W
MF-LF
402

BG33

PP1V5_S3_CPU_VCCDQ

7 15

AN26

CPU_VDDQ_SENSE_P
Note.
CPU_VDDQ_SENSE_N

VCCSA_SENSE

U10

CPU_VCCSASENSE

VCCSA_VID_0
VCCSA_VID_1

D48
D49

CPU_VCCSA_VID<0>
CPU_VCCSA_VID<1>

VOLTAGE=1.05V

Note. VOLTAGE=0V
OUT

OUT

CPU_DDR_VREF
12
VOLTAGE=0.75V

AY43

65

65

R13811

1 1

5%
1/16W
MF-LF
402

1/16W
MF-LF
402

R1313

10K

2 2

5%
1/16W
MF-LF
402

PLACEMENT NOTE:

Please place all sense line resistors on BOTTOM side.

PP1V5_S3RS0
SM_VREF_EXT
1

R1330

PLACE_NEAR=U1000.BJ44:2.54mm

100
5%
1/16W
MF-LF
402

SM_VREF_EXT
1

100

PLACE_NEAR=U1000.BJ44:2.54mm 100

1%
1/16W
MF-LF
402

N16 VCCSA_3
N20 VCCSA_4

5%
1/16W
MF-LF
402

Please place all sense line resistors on BOTTOM side.

N22 VCCSA_5
P17 VCCSA_6
P20 VCCSA_7
R16 VCCSA_8
R18 VCCSA_9

CPU_DDR_VREF

PPVCCSA_S0_CPU

R1331

12

SM_VREF_EXT
1

C1330
0.1UF
10%
16V

2 X5R
2

402

PLACE_NEAR=U1000.BJ44:2.54mm

R21 VCCSA_10
U15 VCCSA_11
V16 VCCSA_12
V17 VCCSA_13
V18 VCCSA_14
V21 VCCSA_15
W20 VCCSA_16

NOSTUFF
1

R1363

100
1%
1/16W
MF-LF
402 2

15 12 7 6
65

PLACE_NEAR=U1000.AN16:50.8mm
PLACE_SIDE=BOTTOM

Note. VOLTAGE=1.25V

AN34
AN38

L17 VCCSA_1
L21 VCCSA_2

R13711

70 73
6 7 9 10 12 14 16 17 20 22 23
36 40 45 68 PLACE_NEAR=U1000.G45:50.8mm

PLACE_SIDE=BOTTOM

NOSTUFF

AN30

85 73 72 30 15 12 10 7 6
78 68

CPU_VIDSCLK

2 5% MF-LF

AM36
AM40

10K

PLACE_NEAR=U1000.A44:38mm

7 10
14

VIDALERT*
VIDSCLK
VIDSOUT

PLACE_NEAR=U1000.F45:50.8mm
PLACE_SIDE=BOTTOM

CPU_VIDALERT_L

2 5% MF-LF

100
1%
1/16W
MF-LF
402 2

R13701

75

43

R1310

W55 VAXG_52
W56 VAXG_53
W61 VAXG_54

NOSTUFF

R1300
1%
1/16W
MF-LF
402

AM33

W52 VAXG_50
W53 VAXG_51

5%
1/16W

VCCPQE_1
VCCPQE_2

6 7 9 10 12 14 16 17 20 22 23 12 9 7 6
69 49 15
36 40 45 68 70 73

10K

AJ15

AL38
AL42

R1314

V59 VAXG_47
W50 VAXG_48
W51 VAXG_49

PPVCORE_S0_AXG

PP1V05_S0

AL34

PLACE_NEAR=U1000.BA43:50.8mm 100
1%
PLACE_SIDE=BOTTOM

V55 VAXG_44
V56 VAXG_45
V58 VAXG_46

AG16

AJ40
AL30

BA43

SM_VREF

V51 VAXG_41
V52 VAXG_42
V53 VAXG_43

AF18

BC22

(IPU)

V48 VAXG_39
V50 VAXG_40

AE14

VCCIO_SEL

VDDQ_SENSE
VSS_SENSE_VDDQ

BC43

SENSE
LINE

W16

AA15
AB17

6 7 10 12 15 30 72 73 85

AJ33
AJ36

SENSE
LINE

VCCIO_50
VCCIO_51

AM28

QUIET
RAIL

AM47
AN20

AA14

VCCDQ_1
VCCDQ_2

(IPU)

P48 VAXG_25
P50 VAXG_26
P51 VAXG_27

AM43

VCCIO_30
VCCIO_31
VCCIO_32
VCCIO_33
VCCIO_34
VCCIO_35
VCCIO_36
VCCIO_37
VCCIO_38
VCCIO_39
VCCIO_40
VCCIO_41
VCCIO_42
VCCIO_43
VCCIO_44
VCCIO_45
VCCIO_46
VCCIO_47
VCCIO_48
VCCIO_49

GRPHICS

AK50
AK51

AJ28

DDR3-1.5V RAILS

AC61 VAXG_11
AD47 VAXG_12
AD48 VAXG_13

AJ47

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12
VDDQ_13
VDDQ_14
VDDQ_15
VDDQ_16
VDDQ_17
VDDQ_18
VDDQ_19
VDDQ_20
VDDQ_21
VDDQ_22
VDDQ_23
VDDQ_24
VDDQ_25
VDDQ_26

MOBILE-2C-35W

AB50 VAXG_3
AB51 VAXG_4
AB52 VAXG_5

SANDY-BRIDGE

AG48
AG50

AF46

1.8V
RAIL

SANDY-BRIDGE

MOBILE-2C-35W
PEG AND DDR

CORE SUPLLY

VCCIO_1
VCCIO_3
VCCIO_4
VCCIO_5
VCCIO_6
VCCIO_7
VCCIO_8
VCCIO_9
VCCIO_10
VCCIO_11
VCCIO_12
VCCIO_13
VCCIO_14
VCCIO_15
VCCIO_16
VCCIO_17
VCCIO_18
VCCIO_19
VCCIO_20
VCCIO_21
VCCIO_22
VCCIO_23
VCCIO_24
VCCIO_25
VCCIO_26
VCCIO_27
VCCIO_28
VCCIO_29

(NOT controlled by VCCIO_SEL)


Fixed at 1.05V

BGA
(7 OF 9)

SA RAIL

U1000
BGA
(6 OF 9)

QUIET
RAIL

VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_60
VCC_61
VCC_62
VCC_63
VCC_64
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
VCC_74
VCC_75
VCC_76

U1000

AA46 VAXG_1
AB47 VAXG_2

6 7 9 10 12 14 16 17 20 22 23
36 40 45 68 70 73

SVID

A26
A29
A31
A34
A35
A38
A39
A42
C26
C27
C32
C34
C37
C39
C42
D27
D32
D34
D37
D39
D42
E26
E28
E32
E34
E37
E38
F25
F26
F28
F32
F34
F37
F38
F42
G42
H25
H26
H28
H29
H32
H34
H35
H37
H38
H40
J25
J26
J28
J29
J32
J34
J35
J37
J38
J40
J42
K26
K27
K29
K32
K34
K35
K37
K39
K42
L25
L28
L33
L36
L40
N26
N30
N34
N38

PP1V5_S3RS0

PP1V05_S0

CRITICAL

SENSE
LINES

14 12 9 7 6
69 49

OMIT_TABLE

PPVCORE_S0_CPU

100

1%
1/16W
MF-LF
402

PLACE_NEAR=U1000.AN17:50.8mm
PLACE_SIDE=BOTTOM

SYNC_MASTER=ANNE_K90I

SYNC_DATE=06/18/2010

PAGE TITLE

CPU POWER
DRAWING NUMBER

PLACEMENT NOTE:

Apple Inc.

Please place all sense line resistors on BOTTOM side.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

13 OF 109
SHEET

12 OF 86

OMIT_TABLE

CRITICAL

CRITICAL

BG21 VSS
BG24 VSS
BG28 VSS

BG37 VSS
BG41 VSS
BG45 VSS
BG49 VSS
BG53 VSS
C29 VSS
C35 VSS
C40 VSS

U1000
BGA
(9 OF 9)
VSS

SANDY-BRIDGE
MOBILE-2C-35W

BG13 VSS
BG17 VSS

D4 VSS
D6 VSS
D10 VSS
D14 VSS
D18 VSS
D22 VSS
D26 VSS
D29 VSS
D35 VSS
D40 VSS
D43 VSS
D46 VSS
D50 VSS
D54 VSS
D58 VSS
E3 VSS
E25 VSS
E29 VSS
E35 VSS

E40 VSS
F13 VSS
F15 VSS
F19 VSS
F29 VSS
F35 VSS
F40 VSS
F55 VSS
G6 VSS
G48 VSS
G51 VSS
G61 VSS
H4 VSS
H10 VSS
H14 VSS
H17 VSS
H21 VSS
H53 VSS
H58 VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9 VSS
A13 VSS

M11
M15

A17 VSS
A21 VSS
A25 VSS

M58
N1
N17

A28 VSS
A33 VSS
A37 VSS

N21
N25

A40 VSS
A45 VSS

N28
N33
N36

A49 VSS
A53 VSS
AA1 VSS

N40
N43
N47

AA8 VSS
AA13 VSS
AA50 VSS

N48
N51
N52

AA51 VSS
AA52 VSS
AA53 VSS

N56
N61

AA55 VSS
AA56 VSS

P9
P14
P16

AB16 VSS
AB18 VSS
AB21 VSS

P18
P21
P58

AB48 VSS
AB61 VSS
AC6 VSS

P59
R4
R17

AC10 VSS
AC14 VSS
AC46 VSS

R20
R46

AD4 VSS
AD17 VSS

T1
T47
T50

AD20 VSS
AD61 VSS
AE8 VSS

T51
T52
T53

AE13 VSS
AF1 VSS
AF17 VSS

T55
T56
U8

AF21 VSS
AF47 VSS
AF48 VSS

U13
V20

AF50 VSS
AF51 VSS

V61
W8
W13

AF52 VSS
AF53 VSS
AF55 VSS

W15
W18
W21

AF56 VSS
AF58 VSS
AF59 VSS

W46
Y4
Y47

AG7 VSS
AG10 VSS
AG14 VSS

Y58
Y59

AG18 VSS
AG47 VSS

J1 VSS
J49 VSS
J55 VSS

AG52 VSS
AG61 VSS
AH4 VSS

K8 VSS
K11 VSS
K21 VSS

VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF

K51 VSS
L16 VSS
L20 VSS
L22 VSS
L26 VSS
L30 VSS
L34 VSS
L38 VSS
L43 VSS
L48 VSS
L61 VSS
M4 VSS
M6 VSS

AH58 VSS
AJ7 VSS
AJ13 VSS

A5
A57
BC61
BD3

AJ16 VSS
AJ20 VSS
AJ22 VSS

BD59
BE4

AJ26 VSS
AJ30 VSS

BE58
BG5
BG57

AJ34 VSS
AJ38 VSS
AJ42 VSS

C3
C58
D59

AJ45 VSS
AJ48 VSS
AK1 VSS

E1
E61

AK52 VSS
AL10 VSS
AL13 VSS
AL17 VSS
AL21 VSS
AL25 VSS
AL28 VSS
AL33 VSS
AL36 VSS
AL40 VSS
AL43 VSS
AL47 VSS
AL61 VSS
AM4 VSS

AM13 VSS
AM20 VSS
AM22 VSS
AM26 VSS
AM30 VSS

U1000
BGA
(8 OF 9)
VSS

SANDY-BRIDGE
MOBILE-2C-35W

OMIT_TABLE

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AM34
AM38
AM42
AM45
AM48
AM58

AN1
AN21
AN25
AN28
AN33
AN36
AN40
AN43
AN47
AN50
AN54
AP7
AP10
AP51
AP55
AR7
AR13
AR17
AR21
AR41
AR48
AR61
AT4
AT14
AT19
AT36
AT45

AT52
AT58
AU1
AU7
AU11
AU28
AU32
AU51
AV17
AV21
AV22
AV34
AV40
AV48
AV55
AW7
AW13
AW43
AW61
AY4
AY9
AY14
AY19
AY30
AY36
AY41
AY45

AY49
AY55
AY58
BA1
BA11
BA17
BA21
BA26
BA32
BA48
BA51
BB53
BC5
BC13
BC57
BD8
BD12
BD16
BD19
BD23
BD27
BD32
BD36
BD40
BD44

BD48
BD52

PAGE TITLE

CPU GROUNDS

BD56
BE5
BG9

DRAWING NUMBER

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

14 OF 109
SHEET

13 OF 86

All INTEL recommendations from Intel doc #4439028 Huron River Platform Power Design Guide

CPU VCORE DECOUPLING


Intel recommendation (Section 6.2): 35x 2.2uF, 25x 22uF, 4x 470uF

69 49 12 9 7 6

CRITICAL

PPVCORE_S0_CPU

CRITICAL

CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL


NOSTUFF

NOSTUFF

C1600

2.2UF

2.2UF

20%
4V
2 X5R
402

C1601

2.2UF

20%
4V
2 X5R
402

CRITICAL

20%
4V
2 X5R
402

2.2UF

20%
4V
2 X5R
402

CRITICAL CRITICAL

2.2UF

2.2UF

20%
2 4V
X5R
402

20%
2 4V
X5R
402

CRITICAL

C1650

2.2UF

C1651
2.2UF

20%
2 4V
X5R
402

20%
2 4V
X5R
402

CRITICAL
1

CRITICAL

2.2UF

CRITICAL

2.2UF

20%
2 4V
X5R
402

C1632

CRITICAL
1

2.2UF

20%
2 4V
X5R
402

20%
2 4V
X5R
402

C1609

20%
4V
2 X5R
402

CRITICAL
1

C1610
2.2UF

CRITICAL
1

CRITICAL

CRITICAL

CRITICAL

2.2UF

20%
2 4V
X5R
402

C1634

2.2UF

C1613 1 C1614

CRITICAL

2.2UF

2.2UF

20%
4V
2 X5R
402

CRITICAL

20%
4V
2 X5R
402

CRITICAL CRITICAL

CRITICAL

CRITICAL CRITICAL

NOSTUFF
1

C1615
2.2UF

20%
4V
2 X5R
402

C1616
2.2UF

20%
4V
2 X5R
402

CRITICAL

CRITICAL

NOSTUFF
1

C1617
2.2UF

20%
4V
2 X5R
402

CRITICAL

CRITICAL

NOSTUFF

2.2UF

2.2UF

20%
4V
2 X5R
402

CRITICAL

NOSTUFF

C1618 1 C1619

2.2UF

20%
4V
2 X5R
402

C1635

2.2UF

20%
2 4V
X5R
402

C1622
2.2UF

20%
4V
2 X5R
402

CRITICAL

CRITICAL

CRITICAL

NOSTUFF

C1621
2.2UF

20%
4V
2 X5R
402

CRITICAL CRITICAL

CRITICAL

NOSTUFF

C1620

20%
4V
2 X5R
402

CRITICAL

NOSTUFF
1

2.2UF

20%
2 4V
X5R
402

C1612

20%
4V
2 X5R
402

CRITICAL

NOSTUFF

C1633

20%
4V
2 X5R
402

CRITICAL

CRITICAL

NOSTUFF

C1611
2.2UF

20%
4V
2 X5R
402

CRITICAL

NOSTUFF

2.2UF

20%
2 4V
X5R
402

2.2UF

20%
4V
2 X5R
402

NOSTUFF

2.2UF

C1608

C1623
2.2UF

20%
4V
2 X5R
402

CRITICAL

2.2UF

20%
4V
2 X5R
402

CRITICAL

2.2UF

C1637

2.2UF

20%
2 4V
X5R
402

C1638 1 C1639
2.2UF

20%
2 4V
X5R
402

2.2UF

20%
2 4V
X5R
402

20%
2 4V
X5R
402

C1640

2.2UF

20%
2 4V
X5R
402

C1641
2.2UF

20%
2 4V
X5R
402

C1642
2.2UF

20%
2 4V
X5R
402

C1643 1 C1644
2.2UF

2.2UF

20%
2 4V
X5R
402

C1645

2.2UF

20%
2 4V
X5R
402

20%
2 4V
X5R
402

C1646
2.2UF

20%
2 4V
X5R
402

CRITICAL

NOSTUFF

C1636

C1624

NOSTUFF
1

C1647

2.2UF

20%
2 4V
X5R
402

C1648

2.2UF

20%
2 4V
X5R
402

C1649
2.2UF

20%
2 4V
X5R
402

CRITICAL CRITICAL

C1652 C1653 1 C1654


1

2.2UF

20%
2 4V
X5R
402

20%
4V
2 X5R
402

C1627 1 C1628 1 C1629 1 C1630 1 C1631


2.2UF

C1607
2.2UF

20%
4V
2 X5R
402

CRITICAL CRITICAL CRITICAL CRITICAL

2.2UF

20%
2 4V
X5R
402

CRITICAL
1

2.2UF

2.2UF

20%
4V
2 X5R
402

NOSTUFF

C1626

CRITICAL

NOSTUFF

2.2UF

20%
4V
2 X5R
402

NOSTUFF

C1625

CRITICAL

NOSTUFF

NOSTUFF

C1602 1 C1603 1 C1604 1 C1605 1 C1606

20%
2 4V
X5R
402

2.2UF

20%
2 4V
X5R
402

2.2UF

20%
2 4V
X5R
402

PLACEMENT_NOTE (C1655-C1666):
Place close to U1000 on top side.

CRITICAL
1

CRITICAL

OMIT

C1655

22UF

22UF

20%
6.3V
2 X5R-CERM-1
603

CRITICAL

NOSTUFF

C1656

CRITICAL

NOSTUFF

C1657

22UF

CRITICAL
NOSTUFF

C1659

22UF

20%
6.3V
2 X5R-CERM-1
603

20%
6.3V
2 X5R-CERM-1
603

NOSTUFF

C1658

22UF

20%
6.3V
2 X5R-CERM-1
603

CRITICAL
1

CRITICAL

OMIT

C1660

22UF

20%
6.3V
2 X5R-CERM-1
603

CRITICAL

OMIT

C1661

22UF

CRITICAL

OMIT

C1662

22UF

20%
20%
6.3V
6.3V
2 X5R-CERM-1 2 X5R-CERM-1
603
603

CRITICAL

OMIT

C1663

22UF

20%
6.3V
2 X5R-CERM-1
603

CRITICAL

OMIT

C1664

22UF

20%
6.3V
2 X5R-CERM-1
603

22UF

20%
6.3V
2 X5R-CERM-1
603

PART NUMBER

CRITICAL

OMIT

C1665

138S0691

16

22UF

20%
6.3V
2 X5R-CERM-1
603

QTY

DESCRIPTION

REFERENCE DES

CRITICAL

BOM OPTION

OMIT

C1666

CRITICAL

CAP,CER,X5R,22uF,20%,6.3V,0603,SAMSUNG

C1655,C1660,C1661,C1662,C1663,C1664,C1665,C1666,C1667,C1670,C1671,C1674,C1676,C1677,C1678,C1679

20%
6.3V
2 X5R-CERM-1
603

PLACEMENT_NOTE (C1667-C1679):
Place close to U1000 on bottom side.

CRITICAL

CRITICAL

OMIT

C1667

22UF

CRITICAL

NOSTUFF

C1668

22UF

20%
6.3V
2 X5R-CERM-1
603

CRITICAL
OMIT

NOSTUFF

C1669

22UF

20%
6.3V
2 X5R-CERM-1
603

CRITICAL
OMIT

C1670

C1671

22UF

20%
6.3V
2 X5R-CERM-1
603

CRITICAL
1

22UF

20%
6.3V
2 X5R-CERM-1
603

CRITICAL

NOSTUFF

C1672

22UF

20%
6.3V
2 X5R-CERM-1
603

CRITICAL

CRITICAL

OMIT

NOSTUFF

C1673

22UF

C1674

22UF

20%
20%
6.3V
6.3V
2 X5R-CERM-1 2 X5R-CERM-1
603
603

CRITICAL
OMIT

NOSTUFF

C1675

22UF

20%
6.3V
2 X5R-CERM-1
603

CRITICAL
OMIT

C1676

22UF

20%
6.3V
2 X5R-CERM-1
603

CRITICAL
OMIT

C1677

22UF

20%
6.3V
2 X5R-CERM-1
603

CRITICAL
OMIT

C1678

22UF

20%
6.3V
2 X5R-CERM-1
603

C1679
22UF

20%
6.3V
2 X5R-CERM-1
603

20%
6.3V
2 X5R-CERM-1
603

PLACEMENT_NOTE (C1640-C1645):
Place near inductors on bottom side.

C1680

C1681

C1682

470UF-4MOHM

470UF-4MOHM

470UF-4MOHM

20%
2.0V
POLY-TANT
D2T-SM

20%
2.0V
POLY-TANT
D2T-SM

20%
2.0V
POLY-TANT
D2T-SM

C1683
470UF-4MOHM

20%
2.0V
POLY-TANT
D2T-SM

CPU VCCIO/VCCPQ DECOUPLING


CPU VCCPLL DECOUPLING

Intel recommendation (Section 6.5): 26x 1uF, 10x 10uF, 2x 330uF

Intel recommendation (section 6.4): 2x 1uF, 1x 330uF

PLACEMENT_NOTE (C1684-C167F):

PLACEMENT_NOTE (C1646-C1671):

Place on bottom side of U1000


U100.

45 40 36 23
12 10 9 7 6 PP1V05_S0
22 20 17 16
73 70 68

Place near U1000 on top side


R1600
1

C1684

C1685

C1686

C1687

C1688

C1689

C1690

C1691

C1692

C1693

C1694

C1695

C1696

1UF

1UF

1UF

1UF

1UF

1UF

1UF

1UF

1UF

1UF

1UF

1UF

1UF

10%
10V
X5R
402

10%
10V
X5R
402

10%
10V
X5R
402

10%
10V
X5R
402

10%
10V
X5R
402

10%
10V
X5R
402

10%
10V
X5R
402

10%
10V
X5R
402

10%
10V
X5R
402

10%
10V
X5R
402

10%
10V
X5R
402

10%
10V
X5R
402

10%
10V
X5R
402

PP1V8_S0_CPU_VCCPLL_R

7 12

0
71 26 22 20 17 7 6 PP1V8_S0

2
5%
1/16W
MF-LF
402

PLACE_NEAR=U1000.AK61:5mm

2
PLACE_NEAR=U1000.AK63:2.54 mm:NO_VIA

C160X

C160Y

1UF

1UF

10%
10V
X5R
402

10%
10V
X5R
402

C160Z

330UF-0.006OHM

20%
2 2V
POLY
CASE-D2-SM

PLACE_NEAR=U1000.AK65:2.54 mm:NO_VIA

C1697

1UF
2

C1698

C1699

1UF

10%
10V
X5R
402

C169A

1UF

10%
10V
X5R
402

10%
10V
X5R
402

1UF

1UF

10%
10V
X5R
402

C169B

C169C

1UF

10%
10V
X5R
402

C169D

1UF

10%
10V
X5R
402

C169E

1UF

10%
10V
X5R
402

C169F

1UF

10%
10V
X5R
402

C161A

1UF

10%
10V
X5R
402

10%
10V
X5R
402

C161B

1UF
2

10%
10V
X5R
402

C161C

1UF
2

10%
10V
X5R
402

C161D

CPU VCCPLL Low pass filter

1UF
2

10%
10V
X5R
402

PLACEMENT_NOTE (C1672-C1681):
Place near U1000 on bottom side
1

C161E

C162A

C162B

C162C

C162D

C162E

C167A

C167B

10UF

10UF

10UF

10UF

10UF

10UF

10UF

10UF

20%
6.3V
X5R
603

20%
6.3V
CERM-X5R
0402-1

20%
6.3V
CERM-X5R
0402-1

20%
6.3V
CERM-X5R
0402-1

20%
6.3V
CERM-X5R
0402-1

20%
6.3V
CERM-X5R
0402-1

20%
6.3V
CERM-X5R
0402-1

20%
6.3V
CERM-X5R
0402-1

20%
6.3V
CERM-X5R
0402-1

C167D

330UF-0.006OHM

C167C
10UF

20%
6.3V
CERM-X5R
0402-1

C167E

330UF-0.006OHM

20%
2 2V
POLY
CASE-D2-SM

C161F

10UF

20%
2 2V
POLY
CASE-D2-SM

SYNC_MASTER=JACK_K90I

SYNC_DATE=06/28/2010

PAGE TITLE

CPU DECOUPLING-I

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

DRAWING NUMBER

R1601

Apple Inc.

0.010
1

PP1V05_S0_CPU_VCCPQE

7 10 12

SIZE

D
REVISION

1%
1/4W
MF
0603

C167F

NOTICE OF PROPRIETARY PROPERTY:

1UF
2

10%
10V
X5R
402

Note:The smallest 10mOhm available in the library are 0805s

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

16 OF 109
SHEET

14 OF 86

VAXG DECOUPLING
Intel recommendation (section 6.3): 21x 1uF, 6x 10uF, 6x 22uF, 2x 470uF

69 49 12 9 7 6

PLACEMENT_NOTE (C1700-C1710):

PPVCORE_S0_AXG

Place on bottom side of U1000


U100.

CRITICAL

CRITICAL

C1700

C1701

1UF

1UF

10%
10V
X5R
402

CRITICAL

C1703

1UF

10%
10V
X5R
402

CRITICAL

C1702

1UF

10%
10V
X5R
402

CRITICAL

C1704
1UF

10%
10V
X5R
402

CRITICAL
1

C1705
1UF

10%
10V
X5R
402

CRITICAL
1

C1706

1UF

10%
10V
X5R
402

CRITICAL

CRITICAL

C1707

1UF

10%
10V
X5R
402

CRITICAL

C1708

1UF

10%
10V
X5R
402

C1709

CRITICAL
1

1UF

10%
10V
X5R
402

C1710
1UF

10%
10V
X5R
402

10%
10V
X5R
402

PLACEMENT_NOTE (C1711-C1716):

CRITICAL
1

C1711

CRITICAL

CRITICAL

C1712

CRITICAL
1

C1713

CRITICAL
1

C1714

C1715

10UF

10UF

10UF

10UF

10UF

20%
6.3V
CERM-X5R
0402-1

20%
6.3V
CERM-X5R
0402-1

20%
6.3V
CERM-X5R
0402-1

20%
6.3V
CERM-X5R
0402-1

20%
6.3V
CERM-X5R
0402-1

CRITICAL
1

C1716
10UF

20%
6.3V
CERM-X5R
0402-1

PLACEMENT_NOTE (C1717-C1722):

CRITICAL

CRITICAL

OMIT

C1717

22UF

CRITICAL

OMIT

C1718

22UF

20%
6.3V
2 X5R-CERM-1
603

CRITICAL

OMIT

C1719

22UF

20%
6.3V
2 X5R-CERM-1
603

OMIT

C1720
22UF

20%
6.3V
2 X5R-CERM-1
603

CRITICAL
1

CRITICAL

OMIT

C1721

22UF

20%
6.3V
2 X5R-CERM-1
603

OMIT

PART NUMBER

C1722
22UF

20%
6.3V
2 X5R-CERM-1
603

QTY

138S0691

20%
6.3V
2 X5R-CERM-1
603

DESCRIPTION

REFERENCE DES

CAP,CER,X5R,22uF,20%,6.3V,0603,SAMSUNG

C1717,C1718,C1719,C1720,C1721,C1722

CRITICAL

BOM OPTION

CRITICAL

PLACEMENT_NOTE (C1723-C1724):
Place near inductors on bottom side.

C1723
470UF-4MOHM

C1724

470UF-4MOHM

20%
2.0V
POLY-TANT
D2T-SM

20%
2.0V
POLY-TANT
D2T-SM

CPU VDDQ/VCCDQ DECOUPLING


Intel recommendation (Section 6.5): 10x 1uF, 8x 10uF, 1x 330uF
PLACEMENT_NOTE (C1738-C1747):
85 73 72 30 12 10 7 6

PP1V5_S3RS0
Place on bottom side of U100.
U1000

CPU VCCSA DECOUPLING


C1747

Intel recommendation (Section 6.6): 6x 1uf, 5x 10uf, 1x 330uf

1UF

1UF

1UF

1UF

1UF

1UF

1UF

1UF

1UF

1UF

10%
10V
X5R
402

10%
10V
X5R
402

10%
10V
X5R
402

10%
10V
X5R
402

10%
10V
X5R
402

10%
10V
X5R
402

10%
10V
X5R
402

10%
10V
X5R
402

10%
10V
X5R
402

PLACEMENT_NOTE (C1758-C1762):

10%
10V
X5R
402

C1752

C1738

C1739

C1740

C1741

C1742

C1743

C1744

C1745

C1746

65 12 7 6

PPVCCSA_S0_CPU

Place on bottom side of U1000


U100.

Place close to U1000 on bottom side


1

C1748

C1749

C1750

C1751

C1753

C1754

C1755

10UF

10UF

10UF

10UF

10UF

10UF

10UF

10UF

20%
6.3V
CERM-X5R
0402-1

20%
6.3V
CERM-X5R
0402-1

20%
6.3V
X5R
603

20%
6.3V
CERM-X5R
0402-1

20%
6.3V
CERM-X5R
0402-1

20%
6.3V
CERM-X5R
0402-1

20%
6.3V
X5R
603

20%
6.3V
CERM-X5R
0402-1

C1756

R1702
2
1%
1/4W
MF
0603

C1760

C1761

1UF

1UF

1UF

10%
10V
X5R
402

10%
10V
X5R
402

10%
10V
X5R
402

C1763

C1764

C1765

10UF

10UF

10UF

20%
6.3V
CERM-X5R
0402-1

20%
6.3V
CERM-X5R
0402-1

20%
6.3V
CERM-X5R
0402-1

20%
6.3V
CERM-X5R
0402-1

C1762
1UF

C1766

10UF

10%
10V
X5R
402

C1767

10UF
2

20%
6.3V
CERM-X5R
0402-1

C1768

330UF-0.006OHM

20%
2 2V
POLY
CASE-D2-SM

0.010
1

C1759

10%
10V
X5R
402

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

1UF

330UF-0.006OHM

20%
2 2V
POLY
CASE-D2-SM

C1758

PP1V5_S3_CPU_VCCDQ

7 12

C1757
1UF

10%
10V
X5R
402

SYNC_MASTER=JACK_K90I

SYNC_DATE=06/28/2010

PAGE TITLE

CPU DECOUPLING-II
DRAWING NUMBER

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

17 OF 109
SHEET

15 OF 86

6
6
36

PP1V05_S0

6
26
51
75

PP3V3_S0

402

6 45 47 81

NC

C20

BI

6 45 47 81

FCBGA

(1 OF 10)

PCH_INTRUDER_L

K22

INTRUDER*

PCH_INTVRMEN_L

C17

INTVRMEN

N34

81 16

HDA_SYNC_R

L34

81 16

HDA_SDIN0

E34

NC_HDA_SDIN1

G34

NC_HDA_SDIN2

C34

NC_HDA_SDIN3

A34

81 16

26

23

23

23

23

81 47

81 47

K34

HDA_RST_R_L

IN

IN

T10

PCH_SPKR

A36

HDA_SDOUT_R

JTAG_T29_TMS

C36

ENET_MEDIA_SENSE_RDIV

N32

IN

XDP_PCH_TCK

IN

XDP_PCH_TMS

J3
H7

HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
HDA_SDO

HDA_DOCK_EN*/GPIO33
HDA_DOCK_RST*/GPIO13

JTAG_TCK
JTAG_TMS

K5

JTAG_TDI

H1

OUT

XDP_PCH_TDO

JTAG_TDO

OUT
OUT

SPI_CS0_R_L

SPI_CLK

Y14

SPI_CS0*

T1

SPI_CS1*

TP_SPI_CS1_L

81 47

SPI_MOSI_R

V4

OUT

SPI_MOSI

81 47

SPI_MISO

U3

IN

SPI_MISO

MF-LF

R1863

402

LPC_AD<2>

6 45 47 81

BI

402

402

BI

6 45 47 81

R1864

LPC_FRAME_L

33

1/16W

MF-LF

402

OUT

6 45 47 81

1/16W

MF-LF
402

81 37

PCIE_ENET_D2R_N

BG34

IN

81 37

IN

PCIE_ENET_D2R_P

BJ34

1/16W
MF-LF
402

81 37

OUT

PCIE_ENET_R2D_C_N

AV32

81 37

PCIE_ENET_R2D_C_P

AU32

OUT

PCIE_AP_D2R_N

BE34

IN

81 32

PCIE_AP_D2R_P

BF34

IN

81 32

PCIE_AP_R2D_C_N

BB32

OUT

81 32

PCIE_AP_R2D_C_P

AY32

OUT

81 39

PCIE_FW_D2R_N

BG36

IN

81 32

T29_PWR_EN

V5

LPC_SERIRQ

AM3

MF-LF

OUT

36

(IPU)
BI

SATA_HDD_D2R_N

IN

42 80

6 45 47

AM1

SATA_HDD_D2R_P

42 80

81 39

IN

PCIE_FW_D2R_P

BJ36

IN

AP7

SATA_HDD_R2D_C_N

42 80

81 39

OUT

PCIE_FW_R2D_C_N

AV34

OUT

AP5

SATA_HDD_R2D_C_P

OUT

42 80

81 39

OUT

PCIE_FW_R2D_C_P

AU34

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

AM10

NC_SATA_B_D2RN

BF36

IN

NC_PCIE_EXCARD_D2RN

AM8

NC_SATA_B_D2RP

NC_PCIE_EXCARD_D2RP

BE36

IN

AP11

NC_SATA_B_R2D_CN

NC_PCIE_EXCARD_R2D_CN

AY34

OUT

AP10

NC_SATA_B_R2D_CP

OUT

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

AD7

SATA_ODD_D2R_N

AD5

SATA_ODD_D2R_P

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

AB8

AH5

SATA_ODD_R2D_C_N

AH4

SATA_ODD_R2D_C_P

NC_PCIE_EXCARD_R2D_CP

BB34

NC_PCIE_5_D2RN

BG37

IN

42 80
42 80

NC_PCIE_5_D2RP

BH37

IN

42 80

NC_PCIE_5_R2D_CN

AY36

42 80

NC_PCIE_5_R2D_CP

BB36

OUT
OUT

NC_SATA_D_D2RN

NC_PCIE_6_D2RN

BJ38

AB10

NC_SATA_D_D2RP

NC_PCIE_6_D2RP

BG38

AF3

NC_SATA_D_R2D_CN

NC_PCIE_6_R2D_CN

AU36

AF1

NC_SATA_D_R2D_CP

NC_PCIE_6_R2D_CP

AV36

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

Y7

NC_SATA_E_D2RN

NC_PCIE_7_D2RN

BG40

Y5

NC_SATA_E_D2RP

NC_PCIE_7_D2RP

BJ40

AD3

NC_SATA_E_R2D_CN

NC_PCIE_7_R2D_CN

AY40

AD1

NC_SATA_E_R2D_CP

NC_PCIE_7_R2D_CP

BB40

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

Y3

NC_SATA_F_D2RN

NC_PCIE_8_D2RN

BE38

Y1

NC_SATA_F_D2RP

NC_PCIE_8_D2RP

BC38

AB3
AB1

Y11

SATAICOMPO
SATAICOMPI

SATA0GP/GPIO21
SATA1GP/GPIO19

NC_PCIE_8_R2D_CN

NC_SATA_F_R2D_CP

NC_PCIE_8_R2D_CP

AY38

81 37

OUT

PCIE_CLK100M_ENET_N

81 37

Y40

TIE THEM TOGETHER VERY CLOSE TO PINS. PLACE THE RESISTOR LESS THAN 200MILS FROM THE PINS

PP1V05_S0

P3

SATALED*

NC_SATA_F_R2D_CN

AW38

80 PCH_SATAICOMP

Y10

PCH_SATALED_L

16

V14

DP_AUXCH_ISOL

16 23 75

P1

SATARDRVR_EN

16 23 42

R1831

Y39

OUT

PCIE_CLK100M_ENET_P

6 7 9 10 12 14 16 17 20
22 23 36 40 45 68 70 73
81 32

AB49

OUT

PCIE_CLK100M_AP_N
PCIE_CLK100M_AP_P

AB47

OUT

81 39

PCIE_CLK100M_FW_N

AA48

OUT

AA47

OUT

PCIE_CLK100M_FW_P
FW_CLKREQ_L

V10

IN

81 8

NC_PCIE_CLK100M_EXCARDN

Y37

OUT

81 8

NC_PCIE_CLK100M_EXCARDP

Y36

OUT

49.9
1%

81 39

1/16W

PCH_SATA3COMP

AH1

PCH_SATA3RBIAS

R1832

PP3V3_T29

40 23 16

81 34

PCIE_CLK100M_T29_N

Y43

OUT

81 34

PCIE_CLK100M_T29_P

Y45

OUT
6

NC_PCIE_CLK100M_PE5N

V45

NC_PCIE_CLK100M_PE5P

V46

PCIECLKRQ5_L_GPIO44

L14

750
71 62 61 57 54 52 51 50 49 48
23 22 20 19 18 17 16 12 8 7 6
46 42 41 40 37 36 33 29 27 26
85 77 75 74 73 72

PLACE_NEAR=U1800.AH1:2.54mm

1%

PP3V3_S0

1/16W

R1843

R1846

10K

R1878

402

R1869

R1876

1/20W

MF-LF
402

201

H14

SMBUS_PCH_CLK

C9

SMBUS_PCH_DATA

SML0ALERT*/GPIO60

A12

SML_PCH_0_ALERT_L

C8

SML_PCH_0_CLK

G12

SML_PCH_0_DATA

C13

SML_PCH_1_ALERT_L

E14

SML_PCH_1_CLK

M16

SML_PCH_1_DATA

FCBGA

OMIT

PERN2
PERP2
PETN2
PETP2

SML0CLK
SML0DATA

PERN3
PERP3
PETN3
PETP3

SML1ALERT*/PCHHOT*/GPIO74

PERN4
PERP4
PETN4
PETP4
PERN5
PERP5
PETN5
PETP5

SML1CLK/GPIO58
SML1DATA/GPIO75

PERN6
PERP6
PETN6
PETP6
PERN7
PERP7
PETN7
PETP7
PERN8
PERP8
PETN8
PETP8

R1803
5%

5%

CLKOUT_PCIE0N
CLKOUT_PCIE0P
CLKOUT_PCIE1N
CLKOUT_PCIE1P
CLKOUT_PCIE2N
CLKOUT_PCIE2P

330K

MF-LF
2

37 16

ENET_CLKREQ_L

J2

IN

AP_CLKREQ_L

M1

IN
IN

EXCARD_CLKREQ_L

A8

36 16

L12

IN

T29_CLKREQ_L

16

PEG_CLKREQ_L

M10

IN

16 34

PCH_SPKR

16

FW_CLKREQ_L

16 23 40

AP_CLKREQ_L

16 23 32

PCH_SATALED_L

16

EXCARD_CLKREQ_L

16

T29_CLKREQ_L

16 36

PEG_CLKREQ_L

16

ENET_CLKREQ_L

16 37

OUT

8 81

NC_PEG_CLK100MP

OUT

8 81

CLKOUT_DMI_N
CLKOUT_DMI_P

AV22

DMI_CLK100M_CPU_N

OUT

10 78

AU22

DMI_CLK100M_CPU_P

OUT

10 78

CLKOUT_DP_N
CLKOUT_DP_P

AM12

NC_PCH_CLKOUT_DPN

OUT

AM13

NC_PCH_CLKOUT_DPP

OUT

CLKIN_DMI_N
CLKIN_DMI_P

BF18

PCIE_CLK100M_PCH_N

IN

25 80

BE18

PCIE_CLK100M_PCH_P

IN

25 80

PCH_CLK96M_DOT_N

IN

25 80

CLKIN_DOT_96N
CLKIN_DOT_96P

PCH_CLK96M_DOT_P

IN

25 80

CLKIN_SATA_N
CLKIN_SATA_P

AK7

PCH_CLK100M_SATA_N

IN

25 80

AK5

PCH_CLK100M_SATA_P

IN

25 80

REFCLK14IN

K45

PCH_CLK14P3M_REFCLK

IN

25 80

CLKIN_PCILOOPBACK

H45

PCH_CLK33M_PCIIN

IN

26 80

MF-LF

201

DOES THIS NEED LENGTH MATCH???

PCIECLKRQ2*/GPIO20

PLACE_NEAR=U1800.V47:5.1mm R1885

CLKOUT_PCIE3N
CLKOUT_PCIE3P

XTAL25_IN
XTAL25_OUT

V47

81

V49

604

SYSCLK_CLK25M_SB_R

402

NC

1%

SYSCLK_CLK25M_SB

1/16W

MF-LF

1.5V -> 1.1V

CLKOUT_PCIE4N
CLKOUT_PCIE4P

XCLK_RCOMP

Y47

PCH_XCLK_RCOMP

CLKOUT_PCIE5N
CLKOUT_PCIE5P

CLKOUTFLEX0/GPIO64

K43

NC_PCH_GPIO64_CLKOUTFLEX0

CLKOUTFLEX1/GPIO65

F47

NC_PCH_GPIO65_CLKOUTFLEX1

CLKOUTFLEX2/GPIO66

H47

NC_PCH_GPIO66_CLKOUTFLEX2

CLKOUTFLEX3/GPIO67

K49

NC_PCH_GPIO67_CLKOUTFLEX3

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

AK14

ITPXDP_CLK100M_N

16 23 78

AK13

ITPXDP_CLK100M_P

16 23 78

CLKIN_GND1_N
CLKIN_GND1_P

BJ30

PCH_CLKIN_GNDN1

BG30

PCH_CLKIN_GNDP1

M7

NC_CLINK_CLK

CL_DATA1

T11

NC_CLINK_DATA

CL_RST1*

P10

NC_CLINK_RESET_L

IN

26 81

PLACE_NEAR=R1885.1:2.54mm

PCIECLKRQ5*/GPIO44
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P

R1886
1K
1%
1/16W
MF-LF

E6

PEG_B_CLKRQ_L_GPIO56

16

PCIECLKRQ0*/GPIO73
PCIECLKRQ1*/GPIO18
PCIECLKRQ3*/GPIO25
PCIECLKRQ4*/GPIO26

2 402

PEG_A_CLKRQ*/GPIO47
PEG_B_CLKRQ*/GPIO56

CL_CLK1

78 23 16
71 62 61 57 54 52 51 50 49 48
23 22 20 19 18 17 16 12 8 7 6
46 42 41 40 37 36 33 29 27 26
85 77 75 74 73 72
16

5%

MF

48 81

BI

R1801
1/16W

48 81

OUT

NC_PEG_CLK100MN

402

1M

5%
1/20W

BI

16

AB38

R1840

R1800

48 81

AB37

NOSTUFF
1

D
48 81

OUT

1/16W

MF-LF

BI

16

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

E24

23 27 29 31 42 48
62 77 81
23 27 29 31 42 48
62 77 81

OUT

G24

20K

20K
1/16W
402

NC_PCIE_CLK100M_PEBP

AB40

32 23 16
16

PPVRTC_G3H

R1802

AB42

MF

JTAG_T29_TMS
26 20 17 7

NC_PCIE_CLK100M_PEBN

5%

1/16W

16

SMBCLK
SMBDATA

16

10K

5%

MF
201

4.7K

1/20W

MF
201

R1877

5%

1/20W

10K

5%

MF-LF

10K

1/16W

MF
201

R1842

5%

1/20W

4.7K

5%

MF
201

10K

1/20W

MF
201

R1844

5%

1/20W

MF

10K

5%

1/20W
201

R1845

10K

5%

PCH_GPIO11

(2 OF 10)

MF-LF
402

E12

COUGAR-POINT
MOBILE

CLOCK
FLEX

36 35 34 26 19 7

402

PLACE_NEAR=U1800.AB12:2.54mm

AB12

402

SMBALERT*/GPIO11

U1800

PERN1
PERP1
PETN1
PETP1

MF-LF

AB13

SATA3COMPI
SATA3RCOMP0
SATA3RBIAS

1%

1/16W

TP_LPC_DREQ0_L

K36

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

LPC_AD<3>

33

1/16W

90.9
MF-LF

1%

R1820
10K

LPC_FRAME_R_L

SERIRQ

HDA_RST*

XDP_PCH_TDI

T3

E36

SPKR

IN

SPI_CLK_R

D36

HDA_SYNC

MF-LF

33

37.4

5%

LPC_R_AD<3>

LDRQ0*
LDRQ1*/GPIO23

HDA_BCLK

1/16W

1/16W

LPC_AD<1>

33

C37

FWH4/LFRAME*

JTAG

HDA_BIT_CLK_R

5%

5%

16

16

34 16

SRTCRST*

16

81 16

81 57

RTCRST*

RTC
LPC

G22

IHDA

PCH_SRTCRST_L

R1862

5%

SATA

RTC_RESET_L

16

5%

LPC_R_AD<2>

B37

R1861

A38

OMIT

SPI

16

D20

LPC_R_AD<1>

R1890

PLACE THIS RESISTOR NEAR THE PCH PIN

C38

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

COUGAR-POINT
MOBILE

PP1V05_S0

PLACE_NEAR=U1800.Y11:2.54mm

SMBUS

MF-LF

BI

PEG

1/16W

LPC_AD<0>

33

R1830

U1800

RTCX1
RTCX2

1
PLACE_NEAR=U1800.Y47:2.54mm

R1860
5%

A20

SYSCLK_CLK32K_RTC

IN

2
23 22 20 17 16 14 12 10 9 7 6
73 70 68 45 40 36

LPC_R_AD<0>

81 26

FROM CLK BUFFER

23 22 20 17 16 14 12 10 9 7
73 70 68 45 40
74 50 49 48
23 22 20 19 18 17 16 12 8 7
46 42 41 40 37 36 33 29 27
73 72 71 62 61 57 54 52
85 77

PCI-E*

RTC_RESET_L

C1802

NOSTUFF
16

R1833

PCH_INTRUDER_L

16

10K
PP3V3_SUS

1UF

402

R1848

1UF

10%
10V
X5R

C1803

R1847

10K

10%
10V
2

5%

201

R1834

1
78 23 16

ITPXDP_CLK100M_P

10K

5%

5%

1/20W

1/20W

MF

MF

201

ITPCPU_CLK100M_P

R1870

10 78

MF

402

SATARDRVR_EN

16 23 42

5%
1/16W

MF-LF

R1871
10K

1/16W

201

16 23 75

5%

1/20W

DP_AUXCH_ISOL

10K

5%

MF-LF

402

PLACE_NEAR=U1800.N34:1.27mm

5%
1/20W

MF

402

R1841

201

10K

1/20W

X5R

10 78

NOSTUFF

MF

201
1

ITPCPU_CLK100M_N

5%

PCH_SRTCRST_L

18 17 16 7
73 72 71 46 22 20 19

1/20W

402

PCH_INTVRMEN_L

ITPXDP_CLK100M_N

PP3V3_S0

R1810

MF
201

33

81 16

HDA_BIT_CLK_R

HDA_BIT_CLK

OUT

72 71 46 22 20 19 18 17 16 7 PP3V3_SUS
73
57 81

5%

PCIECLKRQ5_L_GPIO44

MF

16

R1811

201

PEG_B_CLKRQ_L_GPIO56

HDA_SYNC_R

PLACE_NEAR=R1813.1:2.54mm

R1880
1

HDA_SYNC

OUT

SPI_DESCRIPTOR_OVERRIDE_L

OUT

81 16

HDA_RST_R_L

5%

1/20W

1/20W

MF

MF

201

1/20W

201

R1853
10K
5%
1/20W
MF

201

SYNC_MASTER=K91_MLB

PP1V5_S0

MF

OUT

PCH SATA/PCIE/CLK/LPC/SPI
Apple Inc.

16 SML_PCH_0_ALERT_L

10K

R1849

81 16

HDA_SDOUT_R

OUT

NOSTUFF

R1888

201

45 19

MF

201

NOTICE OF PROPRIETARY PROPERTY:

16 SML_PCH_1_ALERT_L

57 81

MF

1/20W

MF

HDA_SDOUT

1/20W

5%

1/20W

5%

10K

5%

201

NOSTUFF

IN

SMC_SCI_L

0
5%

HDA_SYNC_R
HDA_SDOUT_R

REVISION

33

R1866

1/20W

16 81
16 81

MF

2 PCH_GPIO11

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

18 OF 109
SHEET

16 OF 86

201

SIZE

57 81

R1813

NOSTUFF
NOSTUFF

SYNC_DATE=06/18/2010

PAGE TITLE

DRAWING NUMBER

HDA_RST_L

PLACE_NEAR=U1800.A36:1.27mm

201

PD needed for BCM_MEDIA_SENSE?

10K

201
2

MF

Pullup needed for SPI_DESCRIPTOR_OVERRIDE_L?

R1855

33

45

5%

71 57 42 26 22 20 7

5%

MF

5%
1/20W
201

57 81

1/20W

R1812

0
HDA_SDOUT_R

5%

PLACE_NEAR=U1800.K34:1.27mm

R1854
10K

33

16
81 16

81 16

PLACE_NEAR=U1800.L34:1.27mm

1/20W

7
PP3V3_SUS
PP1V05_S0

7 16 17 18 19 20 22 46 71 72 73
6 7 9 10 12 14 16 20 22 23 36
40 45 68 70 73

R1905

R1900

10K

49.9

5%
1/20W

PLACE_NEAR=U1800.BJ24:12.7mm

1%

MF

1/16W
MF-LF

402

78 9

DMI_N2S_N<0>

BC24

IN

78 9

DMI_N2S_N<1>

BE20

IN

78 9

DMI_N2S_N<2>

BG18

IN
IN

DMI_N2S_N<3>

BG20

78 9

BE24

IN

DMI_N2S_P<0>

78 9

DMI_N2S_P<1>

BC20

IN

78 9

DMI_N2S_P<2>

BJ18

IN

78 9

DMI_N2S_P<3>

BJ20

IN

78 9

OUT

DMI_S2N_N<0>

AW24

78 9

DMI_S2N_N<1>

AW20

OUT

78 9

DMI_S2N_N<2>

BB18

OUT

78 9

DMI_S2N_N<3>

AV18

OUT

78 9

78 9

OUT

DMI_S2N_P<0>

AY24

DMI_S2N_P<1>

AY20

OUT

78 9

AY18

OUT

DMI_S2N_P<2>

78 9

DMI_S2N_P<3>

AU18

OUT

78 9

BH21

PCH_DMI2RBIAS

U1800

DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

COUGAR-POINT
MOBILE
FCBGA

(3 OF 10)
OMIT

DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP
DMI2RBIAS

R1920

BJ24

PCH_DMI_COMP

750

BG25

1%
1/16W
MF-LF
402

DMI_ZCOMP
DMI_IRCOMP

9 78

FDI_DATA_N<1>

9 78

BE14

FDI_DATA_N<2>

9 78

BH13

FDI_DATA_N<3>

9 78

BC12

FDI_DATA_N<4>

9 78

BJ12

FDI_DATA_N<5>

9 78

BG10

FDI_DATA_N<6>

9 78

BG9

FDI_DATA_N<7>

9 78

BG14

FDI_DATA_P<0>

9 78

BB14

FDI_DATA_P<1>

9 78

BF14

FDI_DATA_P<2>

9 78

BG13

FDI_DATA_P<3>

9 78

BE12

FDI_DATA_P<4>

9 78

BG12

FDI_DATA_P<5>

9 78

BJ10

FDI_DATA_P<6>

9 78

BH9

FDI_DATA_P<7>

9 78

FDI_INT

AW16

FDI_LSYNC0
FDI_LSYNC1

FDI_INT

AT1

OUT

9 78

AV12

FDI_FSYNC<0>

OUT

9 78

BC10

FDI_FSYNC<1>

OUT

9 78

AV14
BB10

FDI_LSYNC<0>

OUT

9 78

FDI_LSYNC<1>

OUT

9 78

=T29_WAKE_L
45 26

26 23

26 17

K3

PM_SYSRST_L

PM_PCH_SYS_PWROK

P12

IN
IN

PM_PCH_PWROK

L22

PWROK

B13

DRAMPWROK
DPWROK

OUT

PM_MEM_PWRGD

45

PM_DSW_PWRGD

E22

IN

26 17

PM_PCH_PWROK

L10

IN

73

PM_RSMRST_L

C21

IN

78 30 10

17

45 23 17

73 46 45

46 17

SYS_RESET*

IN

OUT

PCH_SUSWARN_L

IN

PM_PWRBTN_L

K16
E20

IN

SMC_ADAPTER_EN

H20
E10

IN

PM_BATLOW_L

A10

PCH_RI_L

SYS_PWROK

APWROK
RSMRST*

SYSTEM POWER
MANAGEMENT

FDI_DATA_N<0>

AY14

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

FDI_FSYNC0
FDI_FSYNC1

PLACE_NEAR=U1800.BH21:2.54mm

BJ14

WAKE*

B9

CLKRUN*/GPIO32

N3

IN

PM_CLKRUN_L

BI

6 17 45 47

LPC_PWRDWN_L

OUT

6 45 47

SUSCLK/GPIO62

N14

PM_CLK32K_SUSCLK_R

OUT

46

SLP_S5*/GPIO63

D10

PM_SLP_S5_L

OUT

45 73

PM_SLP_S4_L

OUT

6 30 45 73

SLP_S4*

SUSWARN*/SUSPWRDNACK/GPIO30
PWRBTN*

SLP_S3*
SLP_A*

ACPRESENT/GPIO31
BATLOW*/GPIO72

F4

PM_SLP_S3_L

G10

COUGAR-POINT
MOBILE
FCBGA

(4 OF 10)

TP23

TP_PCH_TP23

AP14

PM_SYNC

R1981

6 7
14 20 22 26 71

R1915

2.2K

K14

OUT

GPIO29_SLP_LAN_L

AY1

PCH_DF_TVS

10 78

5%
1/16W
MF-LF
402

17

R1980

390K

NC_CRT_IG_BLUE

N48

5%
1/20W
MF

NC_CRT_IG_GREEN

P49

NC_CRT_IG_RED

T49

201

CRT_BLUE
CRT_GREEN
CRT_RED

1K
2

100K

5%

1/16W

MF-LF

CPU_PROC_SEL_L

10
6

NC_CRT_IG_DDC_CLK

T39

5%

NC_CRT_IG_DDC_DATA

M40

CRT_DDC_CLK
CRT_DDC_DATA

1/20W

DSWVRMEN

A18

PCH_DSWVRMEN

NC_CRT_IG_HSYNC

M47

NC_CRT_IG_VSYNC

M49

G16

SLP_SUS*
SUSACK*

NC_SDVO_TVCLKINN

AP45

NC_SDVO_TVCLKINP

SDVO_STALLN
SDVO_STALLP

AM42

NC_SDVO_STALLN

AM40

NC_SDVO_STALLP

SDVO_INTN
SDVO_INTP

AP39

NC_SDVO_INTN

AP40

NC_SDVO_INTP

P38

DP_EXTA_DDC_CLK

8 75

M39

DP_EXTA_DDC_DATA

8 75

DDPB_AUXN
DDPB_AUXP
DDPB_HPD

AT49

DP_EXTA_AUXCH_C_N

8 75 80 81

AT47

DP_EXTA_AUXCH_C_P

8 75 80 81

AT40

DP_EXTA_HPD

8 75

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

AV42

TP_DP_IG_B_MLN<0>

AV40

TP_DP_IG_B_MLP<0>

AV45

TP_DP_IG_B_MLN<1>

AV46

TP_DP_IG_B_MLP<1>

AU48
AU47

TP_DP_IG_B_MLN<2>

TP_DP_IG_B_MLP<2>

AV47

TP_DP_IG_B_MLN<3>

AV49

TP_DP_IG_B_MLP<3>

P46

DP_IG_C_CTRL_CLK

P42

DP_IG_C_CTRL_DATA

DDPC_AUXN
DDPC_AUXP
DDPC_HPD

AP47

DP_T29SNK0_AUXCH_C_N

8 34 83

AP49

DP_T29SNK0_AUXCH_C_P

8 34 83

AT38

DP_T29SNK0_HPD

8 34

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

AY47

TP_DP_IG_C_MLN<0>

AY49

TP_DP_IG_C_MLP<0>

AY43

TP_DP_IG_C_MLN<1>

AY45

TP_DP_IG_C_MLP<1>

BA47

TP_DP_IG_C_MLN<2>

BA48

TP_DP_IG_C_MLP<2>

BB47

TP_DP_IG_C_MLN<3>

BB49

TP_DP_IG_C_MLP<3>

M43

DP_IG_D_CTRL_CLK

M36

DP_IG_D_CTRL_DATA

DDPD_AUXN
DDPD_AUXP
DDPD_HPD

AT45

DP_T29SNK1_AUXCH_C_N

8 34 83

AT43

DP_T29SNK1_AUXCH_C_P

8 34 83

BH41

DP_T29SNK1_HPD

8 34

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

BB43

TP_DP_IG_D_MLN<0>

BB45

TP_DP_IG_D_MLP<0>

BF44

TP_DP_IG_D_MLN<1>

BE44

TP_DP_IG_D_MLP<1>

BF42

TP_DP_IG_D_MLN<2>

BE42

TP_DP_IG_D_MLP<2>

BJ42

TP_DP_IG_D_MLN<3>

BG42

TP_DP_IG_D_MLP<3>

DDPC_CTRLCLK
DDPC_CTRLDATA

DDPD_CTRLCLK
DDPD_CTRLDATA

402

MF

AP43

SDVO_CTRLCLK
SDVO_CTRLDATA

6 30 45 73

R1909

201

SDVO_TVCLKINN
SDVO_TVCLKINP

OMIT

PPVRTC_G3H

PP1V8_S0

PMSYNCH

DF_TVS

OUT

26 20 16 7

U1800

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

TP_PM_SLP_A_L

AY16

SLP_LAN*/GPIO29

H4

75

6 17 26 32

G8

SUS_STAT*/GPIO61

RI*

PCIE_WAKE_L

IN

NC
AT3
NC
AT4
NC
AT5
NC
AT8
NC
AT10
NC
AT12
NC
AU2
NC
AU3
NC
AV1
NC
AV3
NC
AV5
NC
AV7
NC
AV10
NC
AY3
NC
AY5
NC
AY7
NC
BA2
NC
BA3
NC
BB1
NC
BB3
NC
BB5
NC
BB7
NC
BC8
NC
BD4
NC
BE8
NC
BF3
NC
BF6
NC
BG4
NC

DIGITAL DISPLAY INTERFACE

PM_SLP_SUS_L
C12

73

PCH_SUSACK_L

IN

17

PCH_DAC_IREF

T43
T42

DF_TVS:DMI & FDI Term Voltage


Set to Vss when Low
Set to Vcc when High

CRT_HSYNC
CRT_VSYNC
DAC_IREF
CRT_IRTN

CRT

DMI
FDI

201

R1951
1K

PLACE_NEAR=U1800.T43:2.54mm

5%
1/16W
MF-LF
402

R1986
0
2

PCH_SUSWARN_L

17

PCH_SUSACK_L

5%
1/20W
MF
201

17

71 62 61 57 54 52 51 50 49
26 23 22 20 19 18 16 12 8 7 6 PP3V3_S0
48 46 42 41 40 37 36 33 29 27
85 77 75 74 73 72

R1991

8.2K
5%
1/16W
MF-LF
402

72 71 46 22 20 19 18 17 16 7 PP3V3_SUS
73

PM_CLKRUN_L

6 17 45 47

46 30 26 24 23 22 20 19 8 7 6 PP3V3_S5
85 76 74 73 72 66 56
72 71 46 22 20 19 18 17 16 7 PP3V3_SUS
73

R1925
1%
1/20W
MF
201

NOSTUFF

R1985 R1984

1K

1K

1%
1/20W
MF
201

10K

1/16W

MF-LF

402

5%

1/16W

MF

R1983
10K

5%

1/20W
201

R1982
10K

5%

MF-LF

402

PAGE TITLE
PCH_SUSWARN_L

17

GPIO29_SLP_LAN_L

17

PM_BATLOW_L

17 46

PM_PWRBTN_L

17 23 45

PCIE_WAKE_L

6 17 26 32

PCH DMI/FDI/GRAPHICS
DRAWING NUMBER

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

19 OF 109
SHEET

17 OF 86

8
72 71 62 61 57 54 52 51 50 49
26 23 22 20 19 17 16 12 8 7 6
48 46 42 41 40 37 36 33 29 27
85 77 75 74 73

PP3V3_S0

R2010
R2011

10K

10K

R2012

10K

R2013

10K

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

PCI_INTA_L

K40

PCI_INTB_L

K38

PCI_INTC_L

H38

PCI_INTD_L

G38

JTAG_GMUX_TMS

C46

T29_A_HV_EN_L

C44

PCI_REQ3_L

E40

U1800

PIRQA*
PIRQB*
PIRQC*
PIRQD*

COUGAR-POINT
MOBILE
FCBGA

(5 OF 10)

USBP0N
USBP0P

C24

USB_HUB1_UP_N

BI

24 80

A24

USB_HUB1_UP_P

BI

24 80

USBP1N
USBP1P

C25

NC_USB_1N

B25

NC_USB_1P

USBP2N
USBP2P

C26

NC_USB_2N

A26

NC_USB_2P

USBP3N
USBP3P

K28

NC_USB_3N

H28

NC_USB_3P

USBP4N
USBP4P

E28

NC_USB_4N

D28

NC_USB_4P

USBP5N
USBP5P

C28

NC_USB_5N

A28

NC_USB_5P

USBP6N
USBP6P

C29

NC_USB_6N

B29

NC_USB_6P

USBP7N
USBP7P

N28

NC_USB_7N

M28

NC_USB_7P

USBP8N
USBP8P

L30

USB_HUB2_UP_N

BI

24 80

K30

USB_HUB2_UP_P

BI

24 80

USBP9N
USBP9P

G30

USB_CAMERA_N

BI

32 80

E30

USB_CAMERA_P

BI

32 80

USBP10N
USBP10P

C30

NC_USB_10N

A30

NC_USB_10P

USBP11N
USBP11P

L32

NC_USB_11N

K32

NC_USB_11P

USB HUB 1

Unused

OMIT
2

R2017
R2018

10K

10K

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

18

PCH_PCI_GNT1_L

D47

18

PCH_PCI_GNT2_L

E42

PCH_PCI_GNT3_L

F46

18

R2030

10K

R2031

10K

402

402

R2015

10K

5%

1/16W

1/16W

PCI_INTE_L

G42

AUD_IP_PERIPHERAL_DET

G40

MF-LF

62
5%

IN

MF-LF

75

T29_MCU_INT_L

C42

IN

62

AUD_I2C_INT_L

D44

IN

402

5%

1/16W

C6

OUT

PLT_RESET_L

81 26

LPC_CLK33M_SMC_R

H49

OUT

26

LPC_CLK33M_LPCPLUS_R

H43

OUT

TP_PCI_CLK33M_OUT2

J48

NC_PCI_CLK33M_OUT3

K42
H40

6
26

OUT

PCH_CLK33M_PCIOUT

80 74 6

OUT

LVDS_IG_A_DATA_N<0>

80 74 6

LVDS_IG_A_DATA_N<1>

AM47

OUT

80 74 6

LVDS_IG_A_DATA_N<2>

AK47

OUT

80 8

NC_LVDS_IG_A_DATAN<3>

AJ48

OUT

AN47

OUT

LVDS_IG_A_DATA_P<0>
LVDS_IG_A_DATA_P<1>

AM49

80 74 6
80 74 6
80 74 6

OUT
OUT

LVDS_IG_A_DATA_P<2>

AN48

AK49

80 8

NC_LVDS_IG_A_DATAP<3>

AJ47

OUT

80 74

LVDS_IG_A_CLK_N

AK39

OUT

80 74

LVDS_IG_A_CLK_P

AK40

OUT

AH45

OUT

NC_LVDS_IG_B_DATAN<0>

NC_LVDS_IG_B_DATAN<1>

AH47

OUT
OUT

NC_LVDS_IG_B_DATAN<2>

AF49

OUT

NC_LVDS_IG_B_DATAN<3>
NC_LVDS_IG_B_DATAP<0>

AH43

OUT

8
8

AF45

OUT

NC_LVDS_IG_B_DATAP<1>

AH49

NC_LVDS_IG_B_DATAP<2>

AF47

OUT

OUT

NC_LVDS_IG_B_DATAP<3>

AF43

80 8 6

OUT

TP_LVDS_IG_B_CLKN

AF40

80 8 6

TP_LVDS_IG_B_CLKP

AF39

OUT

R2050

K10

NC_PCI_PME_L

MF-LF

40 36 33 30 26

REQ1*/GPIO50
REQ2*/GPIO52
REQ3*/GPIO54

PCH_LVDS_IBG

AF37

NC_PCH_LVDS_VBG

AF36

GNT1*/GPIO51
GNT2*/GPIO53
GNT3*/GPIO55
PIRQE*/GPIO2
PIRQF*/GPIO3
PIRQG*/GPIO4
PIRQH*/GPIO5
PME*
PLTRST*
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
LVDSA_DATA0*
LVDSA_DATA1*
LVDSA_DATA2*
LVDSA_DATA3*

USB

PCI

10K

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
LVDSA_CLK*
LVDSA_CLK
LVDSB_DATA0*
LVDSB_DATA1*
LVDSB_DATA2*
LVDSB_DATA3*
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

USBP12N
USBP12P

Unused

D
Unused

Unused

Unused

Unused

Unused

USB HUB 2

Camera

Unused

Unused
1

G32

NC_USB_12N

E32

NC_USB_12P

R2065

R2061

USBP13N
USBP13P

C32
A32

NC_USB_13P

R2060

10K

USBRBIAS*
USBRBIAS

C33

80 PCH_USB_RBIAS

B33

R2062
5%
1/20W

MF

MF

201

5%
MF

5%

R2064
1/20W
MF

PUs TO S0 INSTEAD?

1/20W

10K

201

MF

201

5%

7 16 17 19 20 22 46 71 72 73

R2068

1/20W

10K

10K

5%
1/20W
201

6 7 8 24 26 30 31 32 33 48 50
54 55 72 73

PP3V3_SUS

10K

R2067

MF
201

201
1

Unused

1/20W

1/20W

NC_USB_13N

5%

5%

PP3V3_S3

10K

10K
Unused

MF

LVDS

R2016

201

R2069

10K
5%
1/20W
MF
201

OC0*/GPIO59
OC1*/GPIO40
OC2*/GPIO41
OC3*/GPIO42
OC4*/GPIO43
OC5*/GPIO9
OC6*/GPIO10
OC7*/GPIO14

A14

AP_PWR_EN

K20

32 73

USB_HUB_SOFT_RESET_L

23 24

B17

SDCONN_STATE_RST_L

C16

ENET_PWR_EN

23

L16

PCH_GPIO43_OC4_L

23

23

A16

SDCONN_STATE_CHANGE

23 33

D14

PCH_GPIO10_OC6_L

23

C14

PCH_GPIO14_OC7_L

23

LVDSB_CLK*
LVDSB_CLK
R2070

LVD_IBG
LVD_VBG

22.6
1%
1/20W

PLACE_NEAR=U1800.AF37:2.54mm

AE48

2.37K
1%

AE47

1/16W

PLACE_NEAR=U1800.B33:2.54mm

MF

LVD_VREFH
LVD_VREFL

201

MF-LF
402

77 8

LCD_BKLT_PWM

P45

OUT

77 8

LCD_BKLT_EN

J47

OUT

74 8

OUT

LCD_IG_PWR_EN

M45

NC_LVDS_IG_CTRL_CLK

T45

NC_LVDS_IG_CTRL_DATA

P39

74 8 6

LVDS_DDC_CLK

T40

OUT

74 8 6

LVDS_DDC_DATA

K47

OUT

L_BKLTCTL
L_BKLTEN
L_VDD_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA

R2055
100K
5%
1/16W
MF-LF
402

18

PCH_PCI_GNT3_L

18

PCH_PCI_GNT2_L

18

PCH_PCI_GNT1_L

NOSTUFF
NOSTUFF

R2052

201

1/20W

MF

MF

R2054
5%

1/20W

5%

NOSTUFF
10K

5%

1/20W
201

R2053
10K

10K

MF

201

SYNC_MASTER=K91_MLB

SYNC_DATE=06/10/2010

PAGE TITLE

PCH PCI/FLASHCACHE/USB
DRAWING NUMBER

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

20 OF 109
SHEET

18 OF 86

23 19

D
34 23 19 8

42 19

19

85 77 75
51 50 49 48 46 42 41
19 18 17 16 12 8 7 6 PP3V3_S0
40 37 36 33 29 27 26 23 22 20
74 73 72 71 62 61 57 54 52

T7

SMC_IG_THROTTLE_L

U1800

BMBUSY*/GPIO0

40 19 8

FW_PLUG_DET_L

A42

IN

TACH1/GPIO1

COUGAR-POINT
MOBILE

19

GMUX_INT

H36

IN

TACH2/GPIO6

(6 OF 10)

SMC_RUNTIME_SCI_L

E38

IN

NC_GPIO8

C10

JTAG_ISP_TCK
ODD_PWR_EN_L

IN

46 45 19

PP3V3_S0

CLKOUT_PCIE6N
CLKOUT_PCIE6P

V40

NC_PCIE_CLK100M_PE6N

V42

NC_PCIE_CLK100M_PE6P

CLKOUT_PCIE7N
CLKOUT_PCIE7P

V38

NC_PCIE_CLK100M_PE7N

FCBGA

OMIT

TACH3/GPIO7

R2190

(IPU)

19

C4

PCH_GPIO12

100K
NC_GPIO15

5%

(IPU)

MISC

GPIO8

V37

NC_PCIE_CLK100M_PE7P

10K

10K

5%

5%

5%

1/20W

1/20W

MF-LF

MF

MF

402

201

201

47 6

OUT AUD_IPHS_SWITCH_EN

62 23

BI
42 19

OUT
19

45 19 16

30 23

G2

A20GATE

PCH_A20GATE

GPIO15

34 23 19 8

76 74 73 72
24 23 22 20 17 8 7 6 PP3V3_S5
66 56 46 30 26
85

34 19 8

U2

SATA4GP/GPIO16

R2194

10K

100K

10K

10K
5%

5%

5%

5%

1/20W

1/20W

1/20W

1/20W

MF

MF

MF

MF

201

201

201

LPCPLUS_GPIO

D40

ODD_PWR_EN_L

T5

TACH0/GPIO17

5%

AU16

PCH_PECI

E8

PCH_GPIO24

E16

GPIO24/MEM_LED

OUT
36 19

T29_SW_RESET_L

K1

STP_PCI*/GPIO34

NC_GPIO35

K4

GPIO35

PCH_GPIO36_SATA2GP

V8

SATA2GP/GPIO36

JTAG_ISP_TCK

M5

OUT

SATA3GP/GPIO37

N2

IN

JTAG_ISP_TDO

SLOAD/GPIO38

201

PCH_GPIO12

19

SPIROM_USE_MLB

6 19 47 56

PCH_GPIO24

19

SMC_SCI_L

16 19 45

(PU necessary?)

WOL_EN

23 19

PCH_GPIO46

K12

40 19

FW_PWR_EN

V13

37 33 23 19

56 47 19 6

T13

73 19

V3

ENET_LOW_PWR
SPIROM_USE_MLB

BI
19

PCH_GPIO68_TACH4

D6
C40

SDATAOUT0/GPIO39
PCIECLKRQ6*/GPIO45
PCIECLKRQ7*/GPIO46
SDATAOUT1/GPIO48
SATA5GP/GPIO49
GPIO57
TACH4/GPIO68

(PUs necessary?)

PCH_GPIO70_TACH6

C41

19

PCH_GPIO71_TACH7

A40

A4
75 74 73
57 54 52 PP3V3_T29
46 42 41
29 27 26
18 17 16 12 8 7 6 PP3V3_S0
23 22 20 19
40 37 36 33
51 50 49 48
72 71 62 61
85 77

A44
A45
A46
A5
A6

R2160

R2184

R2185

10K

10K

R2186

10K

5%

5%

5%

5%

1/20W

1/20W

1/20W

1/20W

MF

MF

MF

MF

201

201

201

B3

B47

10K

201

BD1
BD49
2

BE1
BE49

BF1
BF49
JTAG_ISP_TDO

8 19 34

FW_PLUG_DET_L

8 19 40

FW_PWR_EN

BG2
BG48
BH3

19 40

SMC_IG_THROTTLE_L

BH47

19 23

BJ4
BJ44
BJ45
BJ46
73 19

WOL_EN

46 22 20 19 18 17 16 7
73 72 71

BJ5

PP3V3_SUS

BJ6
C2

R2114

R2115

10K

10K

5%

5%

1/20W

1/20W

MF

MF

201

C48

201

D1
D49
E1

2
E49
PCH_GPIO46

F1

19 23

F49
77 75 74 73 72
57 54 52 51 50
42 41 40 37 36
26 23 22 20 19
12 8 7 6 PP3V3_S0
18 17 16
33 29 27
49 48 46
71 62 61
85

AH8
AK11
AH10
AK10

R2175

R2174

R2173

R2172

10K

10K

10K

10K

5%

5%

5%

5%

1/20W

1/20W

1/20W

1/20W

MF

MF

MF

MF

201

201

201

201

U47

TACH5/GPIO69
TACH6/GPIO70
TACH7/GPIO71

RSVD

PCH_GPIO69_TACH5

19

VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF

NCTF

19

B41

402

CPU_PECI

10 45 78

MF-LF
5%
402

P5

19

PCH_INIT3V3_L

PCH_RCIN_L

R2140
PROCPWRGD

AY11

PCH_PROCPWRGD

THRMTRIP*

AY10

TP1

BG26

NOSTUFF

1/16W

CPU_PWRGD

OUT

MF-LF

10 23 78

R2130

TP2

BJ26

TP3

BH25

TP4

BJ16

TP5

BG16

TP6

AH38

TP7

AH37

TP8

AK43

TP9

AK45

TP10

C18

TP11

N30

TP12

H3

TP13

AH12

TP14

AM4

TP15

AM5

TP16

Y13

TP17

K24

TP18

L24

TP19

AB46

TP20

AB45

TP21

B21

TP22

M20

TP24

BG46

TP25

BE28

TP26

BC30

TP27

BE32

TP28

BJ32

TP29

BC28

TP30

BE30

TP31

BF32

TP32

BG32

TP33

AV26

TP34

BB26

TP35

AU28

TP36

AY30

NC_1

P37

INIT3_3V*

T14

TP38
TP37
TP39
TP40

TS_VSS1
TS_VSS2
TS_VSS3
TS_VSS4

NC

1K

5%

390

402

5%

PM_THRMTRIP_L

MF-LF

IN

10 78

1/20W
MF

5%
402

GPIO28

JTAG_ISP_TDI

MF-LF

1/16W

GPIO27

P8

34 19 8

1/16W

R2156

ISOLATE_CPU_MEM_L

M3

RCIN*

SCLOCK/GPIO22

R2193

R2155
10K

43
1/16W

SMC_SCI_L

23 19

R2192

NOSTUFF

PECI

IN

(NC-ed per Intel chklist)

73
19 18 17 16 7 PP3V3_SUS
72 71 46 22 20

5%

R2170

2
(PU necessary?)

R2191

402

P4

LAN_PHY_PWR_CTRL/GPIO12

GPIO

20K

402

R2113

1/16W

1/16W

CPU

MF-LF

R2112

48 49 50 51 52 54 57 61 62 71
6 7 8 12 16 17 18 19 20 22 23
26 27 29 33 36 37 40 41 42 46
72 73 74 75 77 85

10K

1/16W

R2150

MF-LF

GMUX_INT

R2111

201

ALL RSVD TPs NC-ed per INTEL approval


PM_THRMTRIP_L_R

NC

IN

46

57 54 52 51 50 49 48
23 22 20 19 18 17 16 12 8 7 6
46 42 41 40 37 36 33 29 27 26
85 77 75 74 73 72 71 62 61

NC

PP3V3_S0

NC

R2196

NOSTUFF

R2197

10K

NC

5%

1/20W

1/20W

MF

NC

201

10K

5%

MF
201

NC

T29_SW_RESET_L

19 36

SMC_RUNTIME_SCI_L

19 45 46

NC
NC
NC
36 35 34 26 19 16 7 PP3V3_T29

NC
NC
NC

R2199

10K

NC

5%
1/16W

NC

MF-LF
402

NC
NC
NC
NC

JTAG_ISP_TDI

8 19 34

PCH_GPIO36_SATA2GP

19 23

ENET_LOW_PWR

NC
R2198

NC

NOSTUFF

R2110

10K

NC

10K

5%

5%

1/20W

1/20W

MF
201

NC

19 23 33 37

MF
201

NC
NC

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
PCH_INIT3V3_L

19

This has internal pull up and should not pulled low.


THIS SIGNAL IS INTENDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.

AY26

NC
AU26
NC
AV28
NC
AW30
NC

VSSADAC
SYNC_MASTER=K91_MLB

SYNC_DATE=06/18/2010

PAGE TITLE
2

PCH MISC
DRAWING NUMBER

Apple Inc.

PCH_GPIO68_TACH4

19

PCH_GPIO69_TACH5

19

PCH_GPIO70_TACH6

19

PCH_GPIO71_TACH7

19

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

21 OF 109
SHEET

19 OF 86

AA21
AA24
AA26
AA27
AA29
AA31
AC26
AC27
AC29
AC31
AD29
AD31
W21
W23
W24
W26
W29
W31
W33

22

PP3V3_SUS

7 16 17 18 19 20 22 46 71 72 73

VCCASW_6_CLK
VCCASW_7_CLK
VCCASW_8_CLK
VCCASW_9_CLK
VCCASW_10_CLK
VCCASW_11_CLK
VCCASW_12_CLK
VCCASW_13_CLK
VCCASW_14_CLK
VCCASW_15_CLK
VCCASW_16_CLK
VCCASW_17_CLK
VCCASW_18_CLK
VCCASW_19_CLK
VCCASW_20_CLK
VCCASW_21_CLK
VCCASW_22_CLK

VCCIO_5_PLLSATA

AF13

VCCIO_15_SATA3
VCCIO_16_SATA3

AH13

VCCIO_9_PLLSATA3

AF14

VCCAPLLSATA

Y49

VCCVRM_0_CLK

PP1V05_S0_PCH_VCCADPLLA

BD47

PP1V05_S0_PCH_VCCADPLLB

BF47

PP1V05_S0
PP1V05_S0
55mA Max, 5mA Idle

23 22 20 17 16 14 12 10 9 7 6
73 70 68 45 40 36

AF17

VCCIO_13_CLK

AF33

VCCDIFFCLKN_0
VCCDIFFCLKN_1
VCCDIFFCLKN_2

AF34
AG34

PLACE_NEAR=U1800.V16:2.54mm

23 22 20 17 16 14 12 10 9 7 6
73 70 68 45 40 36

PP1V05_S0

PPVOUT_S0_PCH_DCPSST
MIN_LINE_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.2 mm

NC
NC

NC-ed per DG

0.1UF
2

23 22 20 17 16 14 12 10 9 7 6
73 70 68 45 40 36

PP1V05_S0

26 17 16 7 PPVRTC_G3H

C2231
1UF

PLACE_NEAR=U1800.A22:2.54mm

AG33

VCCSSC

V16

DCPSST

C2232

0.1UF

10%
6.3V
CERM
402

10%
16V
X5R-CERM
0201

T17
V19

DCPSUS_1_CLK
DCPSUS_2_CLK

BJ8

V_PROC_IO

A22

VCCRTC

AC23

1.44 A Max, 474mA Idle

T34

AD21
AD23

AJ2

48 49 50 51 52 54 57 61 62 71
6 7 8 12 16 17 18 19 20 22 23
26 27 29 33 36 37 40 41 42 46
72 73 74 75 77 85

PP3V3_S0

AF21
AF23
AG21

PP1V05_S0

AG23

6 7 9 10 12 14 16 17 20 22 23
36 40 45 68 70 73

AH14

AG24

AG27
AK1

NC

AG29

VCCAPLLSATA pin left as NC per DG

AF11

PP1V8_S0

6 7 14 17 20 22 26 71

VCCIO_6_SATA
VCCIO_7_SATA
VCCIO_8_SATA

AC16

PP1V05_S0

6 7 9 10 12 14 16 17 20 22 23
36 40 45 68 70 73

AJ26
AJ27

AC17

AJ29

AD17

AJ31

T21

PP1V05_S0

6 7 9 10 12 14 16 17 20 22 23
36 40 45 68 70 73

23 22 20 17 16 14 12 10 9 7 6
73 70 68 45 40 36

VCCIO_0_USB
VCCIO_1_USB
VCCIO_2_USB
VCCIO_3_USB
VCCIO_4_USB

T19

N26

U1800
COUGAR-POINT
MOBILE
FCBGA

(7 OF 10)

PP1V05_S0

TP_1V05_S0_PCH_VCCAPLLEXP

BJ22

PP1V05_S0

AN16
AN17

6 7 9 10 12 14 16 17 20 22 23
36 40 45 68 70 73

AN21
P28
AN26
T27
AN27
T29
AP21

VCCIO_14_PLLUSB

T26

PP1V05_S0

6 7 9 10 12 14 16 17 20 22 23
36 40 45 68 70 73

V5REF_SUS

M26

PP5V_SUS_PCH_V5REFSUS

22

PP3V3_SUS

AP23

7 16 17 18 19 20 22 46 71 72 73

T24

AP24

V23

AP26

V24

AT24

VCCAPLLEXP
VCCIO_17_FDI
VCCIO_18_FDI

P24
AN33

DCPSUS_3_SUS

AN23

VCCSUS3_3_0_SUS

AN24

PP3V3_SUS

P32

PP1V5_S0

NC

AN34
71 62 61 57 54 52 51 50 49 48
23 22 20 19 18 17 16 12 8 7 6
46 42 41 40 37 36 33 29 27 26
85 77 75 74 73 72

BH29

PP3V3_S0

VCCIO_27_DP
VCCIO_28_DP

AK36

VSSALVDS

AK37

VCCTX_LVDS
VCCTX_LVDS
VCCTX_LVDS
VCCTX_LVDS

AM37

42 46 48 49 50 51 52 54 57
6 7 8 12 16 17 18 19 20 22
23 26 27 29 33 36 37 40 41
61 62 71 72 73 74 75 77 85

PP3V3_S0

AT16
AT20

VCCCLKDMI

AB36

VCCDFTERM
VCCDFTERM
VCCDFTERM
VCCDFTERM

AG16

VCCADAC

VCCAFDIPLL

PP3V3_S0

42 46 48 49 50 51 52 54 57
6 7 8 12 16 17 18 19 20 22
23 26 27 29 33 36 37 40 41
61 62 71 72 73 74 75 77 85

AP37

VCCVRM_3_DMI

VCCVRM_2_FDI

22

AP36

VCCDMI_1_DMI

VCCSPI

PP1V8_S0_PCH_VCCTX_LVDS_F

AM38

VCC3_3_6_HVCMOS
VCC3_3_7_HVCMOS

VCCIO_11_PLLPCIE

VCCIO_19_PCIE
VCCIO_20_PCIE
VCCIO_21_PCIE
VCCIO_22_PCIE
VCCIO_23_PCIE
VCCIO_24_PCIE
VCCIO_25_PCIE
VCCIO_26_PCIE

VCCALVDS

OMIT

P26

T23

VCCSUSHDA

AN19

PP1V05_S0

VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE

V21

VCCSUS3_3_1_USB
VCCSUS3_3_2_USB
VCCSUS3_3_3_USB
VCCSUS3_3_4_USB
VCCSUS3_3_9_USB

VOLTAGE=3.3V

C2222
20%
10V
CERM
402

VCCADPLLA
VCCADPLLB

CPU

23 22 20 17 16 14 12 10 9 7 6
73 70 68 45 40 36

PLACE_NEAR=U1800.N16:2.54mm

20
20

RTC

20%
10V
CERM
402

AA23

PP1V05_S0

23 22 20 17 16 14 12 10 9 7 6
73 70 68 45 40 36

23 22 20 17 16 14 12 10 9 7 6
73 70 68 45 40 36

0.1UF
2

48 49 50 51 52 54 57 61 62 71
6 7 8 12 16 17 18 19 20 22 23
26 27 29 33 36 37 40 41 42 46
72 73 74 75 77 85

PP3V3_S0

W16

VCCVRM_1_SATA

VCCASW_2_MISC
VCCASW_1_MISC
VCCASW_0_MISC

MIN_LINE_WIDTH=0.2 mm

71 26 22 20 17 14 7 6 PP1V8_S0

AA16

AJ23

USB

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

C2210

DCPRTC

P22

HDA

N16

P20

AG26

PCH output, for decoupling only


PPVOUT_G3_PCH_DCPRTC

N22

LVDS

AA19

23 22 20 17 16 14 12 10 9 7 6 PP1V05_S0
73 70 68 45 40 36

PP5V_S0_PCH_V5REF

N20

HVCMOS

NC

AL24

P34

DMI

AL24 left as NC per DG

V5REF
FCBGA
(8 OF 10)
OMIT VCCSUS3_3_5_GPIO
VCC3_3_4_CLK
VCCSUS3_3_6_GPIO
VCCSUS3_3_7_GPIO
VCCAPLLDMI2
VCCSUS3_3_8_GPIO
VCCIO_12_PLLCLK
VCC3_3_2_GPIO
DCPSUS_0_CLK
VCC3_3_3_GPIO
VCC3_3_1_GPIO
VCCASW_3_CLK
VCCASW_4_CLK
VCC3_3_0_SATA
VCCASW_5_CLK

DFT/SPI

AL29

U1800
COUGAR-POINT
MOBILE

CRT

BH23

FDI

DCPSUSBYP

VCC CORE

NC

PP1V05_S0

23 22 20 17 16 14 12 10 9 7 6
73 70 68 45 40 36

V12

VCCIO

VCCAPLLDMI2 pin left as NC per DG

VCCDSW3_3

T38

22 PP3V3_S0_PCH_VCC3_3_CLK_F

VCCACLK

T16

PCI/GPIO/
LPC

TP_PPVOUT_PCH_DCPSUSBYP

AD49

SATA

NC
PP3V3_S5

30 26 24 23 22 20 19 17 8 7 6
85 76 74 73 72 66 56 46

CLK/MISC

VCCACLK pin left as NC per DG

MISC

V33
V34

PP1V8_S0

6 7 14 17 20 22 26 71

PP1V05_S0

6 7 9 10 12 14 16 17 20 22
23 36 40 45 68 70 73

PP1V05_S0_PCH_VCCCLKDMI_F

22

PP1V8_S0

6 7 14 17 20 22 26 71

PP3V3_S5

6 7 8 17 19 20 22 23 24 26
30 46 56 66 72 73 74 76 85

PP3V3_S0_PCH_VCCA_DAC_F

22

AG17
AJ16
AJ17
V1

U48

AP16
BG6

PP1V8_S0
VCCAFDIPLL pin left as NC per DG

NC

VCCIO_10_PLLFDI

AP17

VCCDMI_0_FDI

AU20

6 7 14 17 20 22 26 71

PP1V05_S0

6 7 9 10 12 14 16 17 20 22
23 36 40 45 68 70 73

PP1V05_S0

6 7 9 10 12 14 16 17 20 22
23 36 40 45 68 70 73

VCC3_3_5_PCI

NC-ed per DG
7 16 17 18 19 20 22 46 71 72 73

7 16 22 26 42 57 71

10 mA Max, 1mA Idle

C2233
0.1UF

10%
16V
X5R-CERM
0201

PLACE_NEAR=U1800.A22:2.54mm
PLACE_NEAR=U1800.A22:2.54mm

B
0
71 7

PP1V05_S0_PCH_VCCADPLL

PCH VCCADPLLA Filter


(PCH DPLLA PWR)

R2260

PP1V05_S0_PCH_VCCADPLLA

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

5%
1/16W

20

68 mA

MF-LF
402

1 C2260

20%
10V
CERM
402

PLACE_NEAR=U1800.BD47:2.54MM

10%
6.3V
CERM
402

PCH VCCADPLLB Filter


(PCH DPLLB PWR)

R2265
0
1

C2261
1UF

0.1UF

PP1V05_S0_PCH_VCCADPLLB

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

5%
1/16W

20

69 mA

MF-LF
402

1 C2265

20%
10V
CERM
402

C2266

PLACE_NEAR=U1800.BF47:2.54MM

1UF

0.1UF

10%
6.3V
CERM
402

A
PAGE TITLE

PCH POWER
DRAWING NUMBER

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

22 OF 109
SHEET

20 OF 86

AJ3
N24
BG29
H5
AA17

AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD14
AD16
AD19
AD24
AD26

AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD47
AD8
AE2
AE3
AF10
AF12
AF16
AF19
AF24
AF26
AF27
AF29
AF31

AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3

AK38
AK4
AK42

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

U1800
COUGAR-POINT
MOBILE
FCBGA

(9 OF 10)
VSS
OMIT

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AK46
B35
AK8
B39
AL16
B43
AL17
B7
AL19
BB12
AL2
BB16
AL21
BB20
AL23
BB22
AL26
BB24
AL27
BB28
AL31
BB30
AL33
BB38
AL34
BB4
AL48
BB46
AM11
BC14
AM14
BC18
AM36
BC2
AM39
BC22
AM43
BC26
AM45
BC32
AM46
BC34
AM7
BC36
AN2
BC40
AN29
BC42
AN3
BC48
AN31
BD3
AP12
BD46
AP13
BD5
AP19
BE10
AP28
BE22
AP30
BE26
AP32
BE40
AP38
BF10
AP4
BF12
AP42
BF16
AP46
BF20
AP8
BF22
AR2
BF24
AR48
BF26
AT11
BF28
AT13
BF30
AT18
BF38
AT22
BF40
AT26
BF8
AT28
BG17
AT30
BG21
AT32
BG22
AT34
BG24
AT39
BG33
AT42
BG41
AT46
BG44
AT7
BG8
AU24
BH11
AU30
BH15
AV11
BH17
AV16
BH19
AV20
BH27
AV24
BH31
AV30
BH33
AV38
BH35
AV4
BH39
AV43
BH43
AV8
BH7
AW14
C22
AW18
D12
AW2
D16
AW22
D18
AW26
D22
AW28
D24
AW32
D26
AW34
D3
AW36
D30
AW40
D32
AW48
D34
AY12
D38
AY22
D42
AY28
D8
AY4
E18
AY42
E26
AY46
F3
AY8
F45
B11
G14
B15
G18
B19
G20
B23
G26
B27
G28
B31
G36

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

U1800
COUGAR-POINT
MOBILE
FCBGA

(10 OF 10)
VSS
OMIT

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

G48
H10
H12
H16

H18
H22
H24
H26
H30
H32
H34
H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
M14
M18
M22
M24
M30
M32

M34
M38
M4
M42
M46
M8
N18
N47
P11
P16
P18
P30
P40
P43
P47
P7
R2
R48
T12
T31
T33
T36
T37
T4
T46
T47

T8
V11
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W34
W48
Y12
Y38
Y4
Y42
Y46
Y8
V17
AP3
AP1
BE16
BC16
BG28

SYNC_MASTER=K91_MLB

SYNC_DATE=05/27/2010

PAGE TITLE
BJ28

PCH GROUNDS
DRAWING NUMBER

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

23 OF 109
SHEET

21 OF 86

PCH VCCSUS3_3 BYPASS

L2406
73 70 68 45
17 16 14 12 10 9 7 6
40 36 23 22 20

PP1V05_S0

(PCH SUSPEND USB 3.3V PWR)

R2415
1

2 PP1V05_S0_PCH_VCCCLKDMI_R

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=1.05V

0603

PP1V05_S0_PCH_VCCCLKDMI_F

72 71 46 22 20 19 18 17 16 7
73

20

PP3V3_SUS
1

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=1.05V
MAKE_BASE=TRUE

5%
1/16W
MF-LF
402

C2411

PLACE_NEAR=U1800.AB36:2.54mm

20%
6.3V
CERM-X5R
0402-1

C2484

10UF
2

C2413

0.1UF

0.1UF

10%
16V
X5R
402

10%
16V
X5R
402

PP1V5_S0

20 PP1V8_S0_PCH_VCCTX_LVDS_F

23 22 20 17 16 14 12 10 9 7 6
73 70 68 45 40 36

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=1.8V

C2441

72 71 46 22 20 19 18 17 16 7
73

23 22 20 17 16 14 12 10 9 7 6 PP1V05_S0
73 70 68 45 40 36

PP1V05_S0

20%
10V
CERM
402

1
1

PLACE_NEAR=U1800.AG33:2.54mm

C2406

C2408

C2416

0.01UF

0.01UF

4.7UF

20%
6.3V
CERM
805

10%
16V
CERM
402

10%
16V
CERM
402

20%
6.3V
X5R
402

PLACE_NEAR=U1800.BJ8:2.54mm
PLACE_NEAR=U1800.BJ8:2.54mm
PLACE_NEAR=U1800.BJ8:2.54mm

C2417
0.1UF

74
62
52
48
40
29
22
17
6
12
19
26
36
42
50
57
72
77

PLACE_NEAR=U1800.P22:2.54mm

10%
6.3V
CERM
402

10%
16V
X5R
402

PP3V3_S5
1

C2442
1UF

PLACE_NEAR=U1800.V1:2.54mm

R2450

0
1

C2430

PLACE_NEAR=U1800.AM37:2.54mm
PLACE_NEAR=U1800.AM37:2.54mm
PLACE_NEAR=U1800.AM37:2.54mm

PP3V3_S0

C2476
1UF

10%
6.3V
CERM
402

0.1UF

10%
16V
X5R
402

30 26 24 23 22 20 19 17 8 7 6
85 76 74 73 72 66 56 46
75
71
54
49
41
33
23
18
8 7
16
20
27
37
46
51
61
73
85

C2475
1UF

22UF

PP3V3_SUS

0.1UF

PLACE_NEAR=U1800.P32:2.54mm

PLACE_NEAR=U1800.AC17:2.54mm

PCH VCCSUSHDA BYPASS

0.1UH

C2400

10%
6.3V
CERM
402

(PCH HD Audio 3.3V/1.5V PWR)

L2407
2

1UF

10%
6.3V
CERM
402

PLACE_NEAR=U1800.AH13:2.54mm

71 57 42 26 20 16 7

0805

C2452

1UF

20%
10V
CERM
402

PLACE_NEAR=U1800.P24:2.54mm

D
1

C2444

C2440
0.1UF

PLACE_NEAR=U1800.AJ16:2.54mm

PLACE_NEAR=U1800.V24:2.54mm

22 20 17 14 7 6 PP1V8_S0
71 26

23 22 20 17 16 14 12 10 9 7 6 PP1V05_S0
73 70 68 45 40 36

PP1V8_S0

71 26 22 20 17 14 7 6

10UH-0.12A-0.36OHM

PP3V3_S0_PCH_VCCA_DAC_F

20

10%
6.3V
CERM
402

23 22 20 17 16 14 12 10 9 7 6 PP1V05_S0
73 70 68 45 40 36

MAKE_BASE=TRUE
5%

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

1/16W
MF-LF

PCH VCCIO BYPASS

C2434
1UF

402

23 22 20 17 16 14 12 10 9 7 6
73 70 68 45 40 36

PP1V05_S0

10%
6.3V
CERM
402

PLACE_NEAR=U1800.AF34:2.54mm
2
1

C2419
1UF

C2450

C2451

C2455

10UF

0.1UF

0.01UF

20%
6.3V
X5R
603

10%
16V
X5R
402

10%
16V
CERM
402

1
2

10%
6.3V
CERM
402

30 26 24 23 22 20 19 17 8 7 6
85 76 74 73 72 66 56 46

PP3V3_S5

C2499

PLACE_NEAR=U1800.U48:2.54mm
PLACE_NEAR=U1800.U48:2.54mm
PLACE_NEAR=U1800.U48:2.54mm

0.1UF

PLACE_NEAR=U1800.T16:2.54mm

20%
10V
CERM
402

PCH VCC3_3 BYPASS


(PCH PCI 3.3V PWR)

PCH VCCIO BYPASS

PLACE_NEAR=U1800.AT20:2.54mm
(PCH USB 1.05V PWR)
23 22 20 17 16 14 12 10 9 7 6
73 70 68 45 40 36

71 62 61 57 54 52 51 50 49 48
23 22 20 19 18 17 16 12 8 7 6
46 42 41 40 37 36 33 29 27 26
85 77 75 74 73 72
6
77 73
72 70 68 65 54 52 47 42 7

PP3V3_S0

PP1V05_S0

L2451

PP5V_S0

PCH V5REF Filter & Follower

1 mA

R2451

(PCH Reference for 5V Tolerance on PCI)

R2405

D2400

100

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

0603

C2453

402

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

C2454

20%
6.3V
CERM-X5R
0402-1

20 22

10%
10V
X5R
402

<1 MA

PLACE_NEAR=U1800.T38:2.54mm
PLACE_NEAR=U1800.T38:2.54mm

PP5V_S0_PCH_V5REF

20 22

72 7

23 22 20 17 16 14 12 10 9 7 6 PP1V05_S0
73 70 68 45 40 36

C2481

C2482

C2483

C2460

1UF

1UF

1UF

10UF

10%
6.3V
CERM
402

10%
6.3V
CERM
402

10%
6.3V
CERM
402

20%
6.3V
X5R
603

PP3V3_SUS
PP5V_SUS

PCH V5REF_SUS Filter & Follower

1 mA S0-S5

BAT54DW-X-G
SOT-363

NEED PWR CONSTRAINT

PP5V_SUS_PCH_V5REFSUS

C2438
PLACE_NEAR=U1800.M26:2.54mm

<1 MA S0-S5

C2414

C2407

C2463

C2401

1UF

1UF

1UF

1UF

10UF

10%
6.3V
CERM
402

10%
6.3V
CERM
402

10%
6.3V
CERM
402

10%
6.3V
CERM
402

20%
6.3V
X5R
603

23 22 20 17 16 14 12 10 9 7 6
73 70 68 45 40 36

PP1V05_S0
1

20 22
2

PLACE_NEAR=U1800.AN27:2.54mm
PLACE_NEAR=U1800.AN27:2.54mm
PLACE_NEAR=U1800.AN27:2.54mm
PLACE_NEAR=U1800.AN27:2.54mm
PLACE_NEAR=U1800.AN27:2.54mm

C2469
10%
6.3V
CERM
402

PLACE_NEAR=U1800.AF17:2.54mm

PP3V3_S0

C2421

0.1UF
2

C2429

1UF

PP5V_SUS_PCH_V5REFSUS

71 62 61 57 54 52 51 50 49 48
23 22 20 19 18 17 16 12 8 7 6
46 42 41 40 37 36 33 29 27 26
85 77 75 74 73 72

PP3V3_S0

20 22

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=5V
MAKE_BASE=TRUE

0.1UF
20%
10V
CERM
402

PLACE_NEAR=U1800.AD21:2.54mm
PLACE_NEAR=U1800.AG24:2.54mm
PLACE_NEAR=U1800.AJ27:2.54mm
PLACE_NEAR=U1800.AG26:2.54mm

D2400

NC

NC

5%
1/16W
MF-LF
402

PP1V05_S0

10

23 22 20 17 16 14 12 10 9 7 6
73 70 68 45 40 36

(PCH Reference for 5V Tolerance on USB)

R2404

71 62 61 57 54 52 51 50 49 48
23 22 20 19 18 17 16 12 8 7 6
46 42 41 40 37 36 33 29 27 26
85 77 75 74 73 72

PCH VCCCORE BYPASS


(PCH 1.05V CORE PWR)

10%
6.3V
CERM
402

1UF

72 71 46 22 20 19 18 17 16 7
73

C2446
1UF

10UF

NEED PWR CONSTRAINT


MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=5V
MAKE_BASE=TRUE

PLACE_NEAR=U1800.P28:2.54mm

2 20 PP3V3_S0_PCH_VCC3_3_CLK_F

MF-LF

BAT54DW-X-G

10%
10V
X5R
402

PP3V3_S0_PCH_VCC3_3_CLK_R

5%

SOT-363

1UF

PLACE_NEAR=U1800.P34:2.54mm

6
1

PP5V_S0_PCH_V5REF

C2439

1
1

PP3V3_S0

1/16W

NC

NC

5%
1/16W
MF-LF
402

71 62 61 57 54 52 51 50 49 48
23 22 20 19 18 17 16 12 8 7 6
46 42 41 40 37 36 33 29 27 26
85 77 75 74 73 72

10UH-0.12A-0.36OHM

C2423
0.1UF

10%
16V
X5R
402

PLACE_NEAR=U1800.AJ2:2.54mm

10%
16V
X5R
402

23 22 20 17 16 14 12 10 9 7 6 PP1V05_S0
73 70 68 45 40 36

PLACE_NEAR=U1800.BH29:2.54mm

A
1

61 57 54 52 51 50 49 48 46
23 22 20 19 18 17 16 12 8 7 6
42 41 40 37 36 33 29 27 26
85 77 75 74 73 72 71 62

PP3V3_S0

C2424

71 62 61 57 54 52 51 50 49 48
23 22 20 19 18 17 16 12 8 7 6
46 42 41 40 37 36 33 29 27 26
85 77 75 74 73 72

0.1UF
2

10%
16V
X5R
402

PP3V3_S0

C2486
0.1UF

C2456

C2496

C2428

C2420

1UF

1UF

22UF

22UF

10%
6.3V
CERM
402

10%
6.3V
CERM
402

10%
6.3V
CERM
402

20%
6.3V
CERM
805

20%
6.3V
CERM
805

SYNC_MASTER=K91_MLB

SYNC_DATE=06/25/2010

PAGE TITLE

PCH DECOUPLING
2

DRAWING NUMBER

C2485

SIZE

D
REVISION

0.1UF

10%
25V
X5R
402

10%
25V
X5R
402

NOTICE OF PROPRIETARY PROPERTY:


PLACE_NEAR=U1800.AA16:2.54mm

PLACE_NEAR=U1800.AC27:2.54mm
PLACE_NEAR=U1800.AC27:2.54mm
PLACE_NEAR=U1800.AC27:2.54mm
PLACE_NEAR=U1800.AC27:2.54mm
PLACE_NEAR=U1800.AC27:2.54mm

PLACE_NEAR=U1800.T34:2.54mm

1UF

Apple Inc.

PLACE_NEAR=U1800.V33:2.54mm

C2426

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

24 OF 109
SHEET

22 OF 86

PROCESSOR MINI XDP

DESIGN NOTE:
ODT AVAILABLE ON JTAG

72 71 62 61 57 54 52 51 50 49
26 22 20 19 18 17 16 12 8 7 6
48 46 42 41 40 37 36 33 29 27
85 77 75 74 73

PP3V3_S0

CRITICAL

5%

IN

78 10

IN

78 10
10

IN

10

IN

10

IN

10

XDP_BPM_L<4>R2560
XDP_BPM_L<5>R2561
XDP_BPM_L<6>R2562
XDP_BPM_L<7>R2563

IN

5%

1/16W

1/16W

0
0
2

IN

78 10

IN

XDP_CPU:BPM

MF-LF

402

78 9

CPU_CFG<12>R2564
CPU_CFG<13>R2565
CPU_CFG<14>R2566
CPU_CFG<15>R2567

IN

78 9

IN

78 9

IN

78 9

IN

0
1

5%

5%

0
2

1/16W

1/16W

XDP_CPU:CFG

402

OBSFN_C0

OBSFN_A1

OBSFN_C1

OBSDATA_A0

10

OBSDATA_C0

OBSDATA_A1

11

12

OBSDATA_C1

13

14

OBSDATA_A2

15

16

OBSDATA_C2

OBSDATA_A3

17

18

OBSDATA_C3

19

20

21

22

MF-LF

24
26

27

28

XDP_OBSDATA_B<2>
XDP_OBSDATA_B<3>

402

29

30

31

32

OBSDATA_B2

33

34

OBSDATA_D2

OBSDATA_B3

35

36

OBSDATA_D3

37

XDP
PLACE_NEAR=U1000.B46:1MM

78 19 10

IN

XDP_CPU_PWRGD
XDP_CPU_PWRBTN_L

R2500

CPU_PWRGD

1K
5%

XDP_CPU_CFG<0>
XDP_VR_READY

XDP

402

PLACE_NEAR=U4900.D10:2.54MM

OUT

R2502
1

5%

81
29
42
29
62

XDP
PLACE_NEAR=U100.B50:2.54MM

OUT

CPU_CFG<0>

R2501

77
27
31
27
48

62
23
81
23
42

48
16
77
16
31

IN

SMBUS_PCH_DATA
SMBUS_PCH_CLK

OUT

XDP_CPU_TCK

BI

1/16W

78 23 10

9 78

78 23 10

CPU_CFG<8>
CPU_CFG<9>

78 23 10

IN

9 78

IN

9 78

IN

OBSDATA_D1

XDP_CPU_TDO
XDP_CPU_TDI
XDP_CPU_TMS
XDP_CPU_TCK
XDP_CPU_TRST_L
PLACE_NEAR=U1000.L56:2.54MM

9 78

IN

9 78

IN

9 78

IN

9 78

XDP

R2514

51

51

5%

5%

1/16W

IN

9 78

IN

9 78

1/16W
MF-LF
402

PLACEMENT NOTE:
PLACE TCK/TDI/TMS/TRST*
TERM NEAR CPU

XDP

5%

PLACE_NEAR=R1841.1:2.54MM

1/16W

ITPXDP_CLK100M_P

IN

16 78

IN

16 78

IN

10 26

MF-LF
402

38

XDP

XDP_CPU_CLK100M_P
XDP_CPU_CLK100M_N

78
78

VCC_OBS_AB

43

44

VCC_OBS_CD

HOOK2

45

46

RESET#/HOOK6

HOOK3

47

48

DBR#/HOOK7

49

50

NOTE: XDP_DBRESET_L pulled-up to 3.3V on P. 28

51

52

53

54

TRSTn

55

56

TDI

57

58

TMS

59

60

PLACE_NEAR=R1840.1:2.54MM

R2516
0
5%

1/16W

ITPXDP_CLK100M_N

MF-LF

78

XDP_CPURST_L
XDP_DBRESET_L
XDP_CPU_TDO
XDP_CPU_TRST_L
XDP_CPU_TDI
XDP_CPU_TMS

TDO

402

XDP

OUT

PLACE_NEAR=R1125.1:2.54MM

R2505

10 23 26 78

1K
5%

IN

10 23 78

OUT

10 23 78

OUT

10 23 78

OUT

10 23 78

1/16W

PLT_RST_BUF_L

MF-LF
402

C
PP1V05_SUS

7 71

XDP_PRESENT#

XDP

R2504

PM_PCH_SYS_PWROK

XDP

CPU_CFG<6>
CPU_CFG<7>

ITPCLK#/HOOK5

NC

402

PLACE_NEAR=U1000.J58:2.54MM

R2515

ITPCLK/HOOK4

SCL

MF-LF

402

402

40

TCK0

5%
1/16W

MF-LF

402

MF-LF

CPU_CFG<4>
CPU_CFG<5>

OBSDATA_D0

42

SDA

5%
1/16W

MF-LF

XDP

402

OUT

78 23 10

IN

41

MF-LF

26 17

9 23 78

39

TCK1

1K
5%

IN

HOOK1

1/16W

402

78 23 9

CPU_CFG<0>
CPU_CFG<1>

PWRGD/HOOK0

PM_PWRBTN_L

MF-LF

IN

1/16W

MF-LF

45 23 17

CPU_CFG<2>
CPU_CFG<3>

OBSFN_D1

51

5%
1/16W

R2513

25

OBSDATA_B1

IN

78 23 10

OBSFN_D0

XDP 1

R2512

PLACE_NEAR=U1000.L59:2.54MM

CPU_CFG<16>
CPU_CFG<17>

78 23 10

23

OBSFN_B1

OBSDATA_B0

XDP_CPU:CFG

402

MF-LF
5%

1/16W

OBSFN_A0

OBSFN_B0

XDP_OBSDATA_B<0>
XDP_OBSDATA_B<1>

XDP_CPU:CFG

402

MF-LF

IN

1/16W

CPU_CFG<10>
CPU_CFG<11>

IN

XDP_CPU:CFG

MF-LF
5%

XDP_BPM_L<2>
XDP_BPM_L<3>

1/16W

78 9

78 9

IN

78 10

XDP_CPU:BPM

402

XDP_BPM_L<0>
XDP_BPM_L<1>

XDP_CPU:BPM

402

MF-LF
5%

402

MF-LF
5%

1/16W

MF-LF
5%

XDP_CPU:BPM

51

F-ST-SM-HF

XDP_CPU_PREQ_L
XDP_CPU_PRDY_L

BI

R2511

51

2
1

XDP 1

R2510

DF40C-60DS-0.4V

1/16W
MF-LF

78 10

XDP 1

J2500

1K

402

PLACE_NEAR=U1000.L55:2.54MM
PLACE_NEAR=U1000.M60

PLACE TDO TERM NEAR


SNB XDP CONN

XDP_CONN

R2540

78 10

22 23 36 40
6 7 9 10 12
14 16 17 20
45 68 70 73

PLACEMENT NOTE:
NOSTUFF1

PP1V05_S0

PP1V05_S0

73
23 22 20 17 16 14 12 10 9 7 6
70 68 45 40 36

C2500

910
5%

1/16W

517S0774

0.1uF

402

X5R

PLACEMENT NOTE:

C2501

PLACE TDO TERM NEAR


PCH XDP CONN

0.1uF

XDP 1

10%
16V

10%
16V

MF-LF

XDP

402

XDP 1

R2550

R2551

51

51

5%

5%

X5R
402

1/16W
402

51
5%

1/16W

MF-LF

402

PLACE_NEAR=U1800.H7:2.54MM

1/16W

MF-LF

XDP 1

R2552

MF-LF
402

PLACE_NEAR=J2550.52:2.54MM.
PLACE_NEAR=U1800.K5:2.54MM

XDP_PCH_TDO
XDP_PCH_TDI
XDP_PCH_TMS
XDP_PCH_TCK

23 16
23 16
23 16
23 16

PLACE_NEAR=U1800.J3:2.54MM

PCH MINI XDP

XDP

R2556
46 30 26 24 22 20 19 17 8 7 6
85 76 74 73 72 66 56

PP3V3_S5

51
5%
1/16W
MF-LF

CRITICAL

402

XDP_CONN

J2550
DF40C-60DS-0.4V
F-ST-SM-HF

XDP
PLACE_NEAR=U1800.K12:2.54MM

B
19

IN

PCH_GPIO46

R2582
0
5% 1
MF-LF

NC_TP_XDP_PCH_OBSFN_A<0>
NC_TP_XDP_PCH_OBSFN_A<1>

1/16W
402

OBSFN_C0

OBSFN_A1

OBSFN_C1

XDP
PLACE_NEAR=U1800.K20:2.54MM

24 18

IN

USB_HUB_SOFT_RESET_L

R2580
0
5% 1
MF-LF

1/16W
402

XDP
PLACE_NEAR=U1800.B17:2.54MM

18

IN

SDCONN_STATE_RST_L

R2586
0

5% 1
MF-LF

18

IN

ENET_PWR_EN

5% 1
MF-LF

1/16W
402
18

SDCONN_STATE_CHANGE

5% 1
MF-LF

1/16W
402

XDP

IN

ALL_SYS_PWRGD

PCH_GPIO43_OC4_L
XDP_PCH_SDCONN_DET_L

18

IN

18

IN

PCH_GPIO10_OC6_L
PCH_GPIO14_OC7_L

10

OBSDATA_C0

12

OBSDATA_C1

14

15

16

OBSDATA_C2

OBSDATA_A3

17

18

OBSDATA_C3

19

20

OBSFN_B0

21

22

OBSFN_D0

OBSFN_B1

23

24

OBSFN_D1

25

26

OBSDATA_B0

27

28

OBSDATA_D0

OBSDATA_B1

29

30

OBSDATA_D1

31

32

33

34

35

36

37

38

OBSDATA_B3

R2584
1K
5% 1
MF-LF

1/16W
402

6
6

XDP_PCH_S5_PWRGD
XDP_PCH_PWRBTN_L

45 23 17

OUT

PM_PWRBTN_L

R2585
0
5% 1
MF-LF

1/16W
402

81 77 62 48 42 31 29 27 23 16

BI

81 77 62 48 42 31 29 27 23 16

IN

23 16

OUT

NC_TP_XDPPCH_HOOK2
NC_TP_XDPPCH_HOOK3
SMBUS_PCH_DATA
SMBUS_PCH_CLK
XDP_PCH_TCK

OBSDATA_D3

NC_TP_XDP_PCH_HOOK4
NC_TP_XDP_PCH_HOOK5

40

ITPCLK/HOOK4

42

ITPCLK#/HOOK5

43

44

VCC_OBS_CD

HOOK2

45

46

RESET#/HOOK6

HOOK3

47

48

DBR#/HOOK7

49

50

NOTE: XDP_DBRESET_L pulled-up to 3.3V on P. 28

SDA

51

52

TDO

SCL

53

54

TRSTn

TCK1

55

56

TDI

57

58

59

60

TMS

X5R

1/16W
402

XDPPCH_PLTRST_L
XDP_DBRESET_L
XDP_PCH_TDO
TP_XDP_PCH_TRST_L
XDP_PCH_TDI
XDP_PCH_TMS

FW_CLKREQ_L

PLACE TCK/TDI/TMS/TRST*
TERM NEAR PCH

IN

16 40

16 75

IN

16 42

5% 1
MF-LF

IN

16 32

PLACE_NEAR=U1800.M1:2.54MM

AP_CLKREQ_L

6
6

IN

19

IN

8 19 34

XDP
PLACE_NEAR=U1800.U2:2.54MM

0
5% 1
MF-LF

2 1/16W
402

AUD_IPHS_SWITCH_EN

IN

19 62

37

6
6

IN
OUT

26

1K series R on PCH Support P. 28

10 23 26 78

IN

16 23

OUT

16 23

OUT

16 23

SYNC_MASTER=ANNE_K90I

SYNC_DATE=06/22/2010

PAGE TITLE

CPU & PCH XDP


DRAWING NUMBER

XDP
1

517S0774

0.1uF
10%
16V

1/16W
402

XDP_PRESENT#

XDP

C2580

IN

XDP_PCH_AUD_IPHS_SWITCH_EN
ENET_LOW_PWR
IN 19 33

41

NC

PCH_GPIO36_SATA2GP
JTAG_ISP_TCK

39

19 30

XDP

NC_TP_XDP_PCH_OBSFN_D<0>
NC_TP_XDP_PCH_OBSFN_D<1>

IN

PLACEMENT NOTE:

R2579
OBSDATA_D2

ISOLATE_CPU_MEM_L
PLACE_NEAR=U1800.V10:2.54MM

0
5% 1
MF-LF

DP_AUXCH_ISOL
SATARDRVR_EN

HOOK1

TCK0

1/16W
402

XDP

XDP_FW_CLKREQ_L
XDP_AP_CLKREQ_L

VCC_OBS_AB

PWRGD/HOOK0

XDP
PLACE_NEAR=U4900.D10:2.54MM

R2577

13

OBSDATA_A2

OBSDATA_B2

5% 1
MF-LF

R2576

11

PLACE_NEAR=J2550.39:2.54MM

73 45 26

IN

R2581

PLACE_NEAR=U1800.P8:2.54MM

XDP_PCH_ISOLATE_CPU_MEM_L
SMC_IG_THROTTLE_L
IN 19

OBSDATA_A1

XDP

IN

NC_TP_XDP_PCH_OBSFN_B<0>
NC_TP_XDP_PCH_OBSFN_B<1>

R2587

PLACE_NEAR=U1800.A16:2.54MM

33 18

XDP_PCH_SDCONN_STATE_RST_L
XDP_PCH_ENET_PWR_EN

OBSDATA_A0

1/16W
402

XDP
PLACE_NEAR=U1800.C16:2.54MM

XDP_PCH_GPIO46
XDP_PCH_USB_HUB_SOFT_RST_L

XDP

R2578

OBSFN_A0

C2581

Apple Inc.

0.1uF

402

10%
16V

X5R

NOTICE OF PROPRIETARY PROPERTY:

402

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SIZE

REVISION

BRANCH

PAGE

25 OF 109
SHEET

23 OF 86

1
TABLE_BOMGROUP_HEAD

BOM GROUP

BOM OPTIONS

HUB1_ALLREM

HUB1_NONREM1_0,HUB1_NONREM0_0

HUB1_1NONREM

HUB1_NONREM1_0,HUB1_NONREM0_1

HUB1_2NONREM

HUB1_NONREM1_1,HUB1_NONREM0_0

HUB1_3NONREM

HUB1_NONREM1_1,HUB1_NONREM0_1

HUB2_ALLREM

HUB2_NONREM1_0,HUB2_NONREM0_0

HUB2_1NONREM

HUB2_NONREM1_0,HUB2_NONREM0_1

HUB2_2NONREM

HUB2_NONREM1_1,HUB2_NONREM0_0

HUB2_3NONREM

HUB2_NONREM1_1,HUB2_NONREM0_1

TABLE_BOMGROUP_ITEM

PP3V3_S3

32 31 30 26 24 18 8 7 6
73 72 55 54 50 48 33

C2602

BYPASS=U2600.5::5mm
BYPASS=U2600.34::2mm
BYPASS=U2600.23::2mm
1
1
1 BYPASS=U2600.15::2mm

4.7UF
20%
6.3V
X5R
603

C2603

C2611

C2612

0.1UF

0.1UF

0.1UF

10%
16V
X7R-CERM
402

10%
16V
X7R-CERM
402

10%
16V
X7R-CERM
402

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

2
TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BYPASS=U2600.23::5mm
BYPASS=U2600.29::2mm
BYPASS=U2600.5::2mm
BYPASS=U2600.10::2mm

C2608

C2609

0.1UF

20%
6.3V
X5R
603

10%
16V
X7R-CERM
402

0.1UF
10%
16V
X7R-CERM
402

C2610

PPUSB_HUB1_CRFILT

10%
16V
X7R-CERM
402

VOLTAGE=1.8V
2

CRFILT

VDD33

Y2600
24.000M-60PPM-16PF
2

CRITICAL

CRITICAL

SYM VER 1

HUB1_NONREM1_1

HUB1_NONREM0_1

R2601 1

10K
5%
1/16W
MF-LF
402

R2602

1M

5%
1/16W
MF-LF
402

R2603

5%
50V
CERM
402

R2605

20%
6.3V
X5R
603

QFN
OMIT

USB_HUB_RESET_L

26

RESET*

USB_HUB1_XTAL1
USB_HUB1_XTAL2

33
32

XTALIN/CLKIN
XTALOUT

USB_HUB1_NONREM0

28

USB_HUB1_NONREM1

22

USBDM_DN3/PRT_DIS_M3
SUSP_IND/LOCAL_PWR/NON_REM0
USBDP_DN3/PRT_DIS_P3
SDA/SMBDATA/NON_REM1
NC
SCL/SMBCLK/CFG_SEL0
NC

USB_HUB1_CFG_SEL0

24

USB_HUB1_CFG_SEL1

25

R2606

USBDM_DN1/PRT_DIS_M1 1
USBDP_DN1/PRT_DIS_P1 2

USB_T29A_N
USB_T29A_P

BI

8 80

BI

8 80

USBDM_DN2/PRT_DIS_M2 3
USBDP_DN2/PRT_DIS_P2 4

USB_IR_N
USB_IR_P

BI

44 80

BI

44 80

6
7

USB_EXTB_N
USB_EXTB_P

BI

43 80

8
9

USB_EXTC_N
USB_EXTC_P

HS_IND/CFG_SEL1

R2607

10K

10K

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

C2653

C2661

C2662

0.1UF

0.1UF

0.1UF

10%
16V
X7R-CERM
402

BOM TABLE
QTY

10%
16V
X7R-CERM
402

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION

U2600,U2650

CRITICAL

USBHUB_2514
USBHUB_2514B
USBHUB_2513B

TABLE_5_ITEM

TEST

PRTPWR1/BC_EN1*
PRTPWR2/BC_EN2*
PRTPWR3/BC_EN3*
NC

12
16
18
20

TP_USB_HUB1_PRTPWR1
NC_USB_HUB1_PRTPWR2
NC_USB_HUB1_PRTPWR3
NC_USB_HUB1_PRTPWR4

OCS1*
OCS2*
OSC3*
NC

13
17
19
21

TP_USB_HUB1_OCS1
NC_USB_HUB1_OCS2
USB_EXTB_OC_L
NC_USB_HUB1_OCS4

IPU
IPU
IPU
IPU

BYPASS=U2650.5::5mm
BYPASS=U2650.23::2mm
BYPASS=U2650.34::2mm
1
1
1 BYPASS=U2650.15::2mm

4.7UF

10%
16V
X5R
402

SMSC USB2514

10%
16V
X7R-CERM
402

338S0824

SMSC USB2514B

U2600,U2650

CRITICAL

338S0923

SMSC USX2513B

U2600,U2650

CRITICAL

TABLE_5_ITEM

T29

IR Receiver

External B

BI

43 80

BI

8 80

BI

8 80

External C

PP3V3_S3

6 7 8 18 24 26 30 31 32 33 48
50 54 55 72 73

R2620
10K

IN

43

IN

5%
1/16W
MF-LF
402

48 33 32 31 30 26 24 18 8 7 6 PP3V3_S3
73 72 55 54 50

USB_HUB1_RBIAS

VBUS_DET 27

USB_HUB1_VBUS_DET

USBDM_UP 30
USBDP_UP 31

USB_HUB1_UP_N
USB_HUB1_UP_P

R2640

18 80

BI

18 80

20K

46 30 26 23 22 20 19 17 8 7 6 PP3V3_S5
85 76 74 73 72 66 56

CRITICAL
BI

12K
1%
1/16W
MF
402

2
5%
1/16W
MF-LF
402

R2600

THRM_PAD
37

C2652

1UF
2

338S0720

RBIAS 35

PP3V3_S3

10%
16V
X5R
402

TABLE_5_HEAD

11

24

R2604

31 30 26 24 18 8 7 6
73 72 55 54 50 48 33 32

10%
16V
X7R-CERM
402

1UF

10%
16V
X7R-CERM
402

C2616

DESCRIPTION
All ports are removable
Port 1 is non removable
Port 1 and 2 are non removable
Port 1, 2, and 3 are non removable

PART#

10K

0.1UF
2

USB_HUB1_TEST

2
5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

C2615

0
1
0
1

TABLE_5_ITEM

100
1

CRITICAL

5%
1/16W
MF-LF
402

NON_REM0

0
0
1
1

C2618

USB2513B

18PF

HUB1_NONREM0_0

10K
5%
1/16W
MF-LF
402

C2620

10K

HUB1_NONREM1_0

5%
50V
CERM
402

R2630

18PF

0.1UF

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.8V

U2600

5X3.2X1.4-SM

C2619

C2617

PPUSB_HUB1_PLLFILT

CRITICAL

NON_REM1

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM

0.1UF
2

5
10
15
23
29
36

34

4.7UF

14

C2607

TABLE_BOMGROUP_ITEM

PLLFILT

R2641
10K

R2642

1
1

100K
5%
1/16W
MF-LF
402

5%
1/16W
MF-LF

NOSTUFF

C2641

2 402

100PF
2

5%
50V
CERM
402

USB_HUB_RESET

USB_HUB_RESET_L

6
3
D

BYPASS=U2650.23::5mm
BYPASS=U2650.10::2mm
2

BYPASS=U2650.29::2mm
BYPASS=U2650.5::2mm
20%
6.3V
X5R
603

0.1UF
2

10%
16V
X7R-CERM
402

0.1UF
10%
16V
X7R-CERM
402

C2660
10%
16V
X7R-CERM
402

CRFILT

VDD33

Y2650
1

CRITICAL

SYM VER 1

R2680

18PF
HUB2_NONREM1_1

HUB2_NONREM0_1

R2651 1

10K
5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

5%
50V
CERM
402

5%
1/16W
MF-LF
402

R2655
1

100

5%
1/16W
MF-LF
402

10K

24

R2654

USB_HUB2_TEST

11

TEST

USB_HUB_RESET_L

26

RESET*

33
32

USB_HUB2_XTAL1
USB_HUB2_XTAL2

CRITICAL

HUB2_NONREM0_0

R2652 1

QFN
OMIT

5%
1/16W
MF-LF
402

VOLTAGE=1.8V

C2665

0.1UF
2

10%
16V
X7R-CERM
402

C2666

SOT-363

C2668

0.1UF

1UF

10%
16V
X7R-CERM
402

10%
16V
X5R
402

10%
6.3V
CERM-X5R
402

1UF
2

10%
16V
X5R
402

D2600
SOD-523

XTALIN/CLKIN
XTALOUT

USB_BT_N
USB_BT_P

USBDM_DN2/PRT_DIS_M2 3
USBDP_DN2/PRT_DIS_P2 4

USB_HUB2_NONREM0

28

USB_HUB2_NONREM1

22

USB_HUB2_CFG_SEL0

24

USB_HUB2_CFG_SEL1

25

HS_IND/CFG_SEL1

R2656

5%
1/16W
MF-LF
402

R2657
10K

5%
1/16W
MF-LF
402

PRTPWR1/BC_EN1*
PRTPWR2/BC_EN2*
PRTPWR3/BC_EN3*
NC

12
16
18
20

OCS1*
OCS2*
OSC3*
NC

13
17
19
21

IPU
IPU
IPU
IPU

BI

6 32 80

BI

6 32 80

USB_TPAD_N
USB_TPAD_P

BI

53 80

USB_HUB_SOFT_RESET_L

IN

BI

53 80

USB_EXTA_N
USB_EXTA_P

BI

43 80

BI

43 80

BI

BI

PU_USB_HUB2_PRT4_N
PU_USB_HUB2_PRT4_P

Bluetooth

Trackpad/Keyboard

External A

SD Card/Express Card

TP_USB_HUB2_PRTPWR1
NC_USB_HUB2_PRTPWR2
NC_USB_HUB2_PRTPWR3
NC_USB_HUB2_PRTPWR4

PP3V3_S3

TP_USB_HUB2_OCS1
NC_USB_HUB2_OCS2
USB_EXTA_OC_L
NC_USB_HUB2_OCS4

IN

R2670

5%
1/16W
MF-LF
402

SYNC_MASTER=K91_MLB

SYNC_DATE=06/08/2010

PAGE TITLE

USB HUBS

USB_HUB2_RBIAS

DRAWING NUMBER

VBUS_DET 27

USB_HUB2_VBUS_DET

USBDM_UP 30
USBDP_UP 31

USB_HUB2_UP_N
USB_HUB2_UP_P

Apple Inc.

CRITICAL
BI
BI

18 80

R2650

SIZE

D
REVISION

12K

18 80

37

6 7 8 18 24 26 30 31 32 33 48
50 54 55 72 73

10K
IN

43

THRM_PAD

2N7002DW-X-G
S

BAT54XV2T1

RBIAS 35

C2640

23 18

USBDM_DN3/PRT_DIS_M3 6
SUSP_IND/LOCAL_PWR/NON_REM0
USBDP_DN3/PRT_DIS_P3 7
SDA/SMBDATA/NON_REM1
NC 8
SCL/SMBCLK/CFG_SEL0
NC 9

10K

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM

USBDM_DN1/PRT_DIS_M1 1
USBDP_DN1/PRT_DIS_P1 2

10K

USB2513B

18PF

1M
2

C2670

10K

HUB2_NONREM1_0

5%
1/16W
MF-LF
402

R2653

5%
50V
CERM
402

U2650

5X3.2X1.4-SM

C2669

C2667

PPUSB_HUB2_PLLFILT

24.000M-60PPM-16PF

SOT-363

0.47UF

VOLTAGE=1.8V
2

CRITICAL

CRITICAL

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM

0.1UF
2

Q2640

2N7002DW-X-G
S
1

PPUSB_HUB2_CRFILT

5
10
15
23
29
36

C2659

34

4.7UF

C2658

14

PLLFILT

C2657

Q2640
P3V3S3_EN_RC

NOTICE OF PROPRIETARY PROPERTY:

1%
1/16W
MF
402

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

26 OF 109
SHEET

24 OF 86

UNUSED clock terminations for FCIM MODE

80 16

PCH_CLK14P3M_REFCLK

80 16

PCIE_CLK100M_PCH_N

80 16

PCIE_CLK100M_PCH_P

80 16

PCH_CLK100M_SATA_N

80 16

PCH_CLK100M_SATA_P

80 16

PCH_CLK96M_DOT_N

80 16

PCH_CLK96M_DOT_P

R2757

R2756

SYNC_MASTER=K91_MLB

10K

10K

PAGE TITLE

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

R2755

10K

5%
1/16W
MF-LF
402

R2754

10K

5%
1/16W
MF-LF
402

R2753

10K

5%
1/16W
MF-LF
402

R2752

10K

5%
1/16W
MF-LF
402

R2751

10K

SYNC_DATE=06/21/2010

Clock (CK505)
DRAWING NUMBER

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

27 OF 109
SHEET

25 OF 86

System RTC Power Source & 32kHz / 25MHz Clock Generator

Platform Reset Connections


Unbuffered

64 63 53 48 47 46 45 43 7 6
73

R2881

PP3V42_G3H
Coin-Cell:
VBAT (300-ohm & 10uF RC)
No Coin-Cell: 3.42V G3Hot (no RC)

30 26 24 23 22 20 19 17 8 7 6
85 76 74 73 72 66 56 46

6
71
7
36

PP3V3_ENET
PP3V3_ENET
PP1V8_S0
PP3V3_T29

C2824

C2822

0.1UF

C2820

0.1UF

0.1UF

C2802

10%

10%

10%

10%

16V

16V

10V

X5R-CERM
0201

X5R-CERM
0201

NO STUFF
1

X2
X1

GND

5%
1/20W
MF
201

SMC_LRESET_L

OUT

45

PLT_RESET_L

OUT

18 26 30 33 36 40

AP_RESET_L

OUT

32

PCA9557D_RESET_L

OUT

31

XDPPCH_PLTRST_L

OUT

23

PLT_RESET_L

OUT

18 26 30 33 36 40

BKLT_PLT_RST_L

OUT

77

25MHZ_A 9
25MHZ_B 8
25MHZ_C 15

SYSCLK_CLK25M_SB
SYSCLK_CLK25M_ENET
SYSCLK_CLK25M_T29
PPVRTC_G3H

OUT

16 81

PLT_RESET_L

OUT

18 26 30 33 36 40

R2889
1K

OUT

16 81

OUT

37 81

OUT

34 81

Series R is R3803

7 16 17 20

For SB RTC Power

THRM
PAD

R2893
0

1
1

C2810

5%
1/16W
MF-LF
402

1UF
2

5%
1/16W
MF-LF
402

10%
6.3V
CERM
402

NOTE: 30 PPM crystal required

5%
50V
CERM
402

XDP

SYSCLK_CLK32K_RTC

SYSCLK_CLK25M_X1

0
5%
1/16W
MF-LF
402

32KHZ_A 12

VDD_RTC_OUT 1

R2806

7
10
16

3
SM-3.2X2.5MM

12PF
1

VDDIO_25M_A
VDDIO_25M_B
VDDIO_25M_C

1M

25.000MHZ-12PF-30PPM

C2806

CRITICAL

3
4

5%
1/16W
MF-LF
402

R2871
1

+V3.3A should be first


available ~3.3V power
to reduce VBAT draw.

TQFN

SYSCLK_CLK25M_X2_R

2
5%
1/20W
MF
201

Y2805

NC
NC

33

17

SYSCLK_CLK25M_X2
1

5%
50V
CERM
402

6 26 47 81

R2888

SLG3NB148V

X5R
402-1

R2805

12PF

6 26 47 81

OUT

R2883

CRITICAL

C2805

OUT

MAKE_BASE=TRUE

VBAT and +V3.3A are


internally ORed to
create VDD_RTC_OUT.

U2800
11
6
14

MAKE_BASE=TRUE

LPCPLUS_RESET_L
LPCPLUS_RESET_L

5%
1/16W
MF-LF
402

1UF

16V
X5R-CERM
0201

VBAT 13

6
26

PP3V3_S5

+V3.3A 2

Ethernet XTAL Power


7
73 71 37
SB XTAL Power 22 20 17 14 7
T29 XTAL Power 35 34 19 16

33

PLT_RESET_L

5%
1/16W
MF-LF
402

VDD_25M 5

7 6
73 71 37 26

IN

Coin-Cell & G3Hot:


3.42V G3Hot
Coin-Cell & No G3Hot: 3.3V S5
No Coin-Cell:
3.3V S5
No bypass necessary

D
GreenClk 25MHz Power

40 36 33 30 26 18

Series R is R4283
71 62 61 57 54 52 51 50 49 48
23 22 20 19 18 17 16 12 8 7 6
46 42 41 40 37 36 33 29 27 26
85 77 75 74 73 72

PP3V3_S0

Buffered
U2880
74LVC1G07
SC70
4

ENET_MEDIA_SENSE ISOLATION CIRCUIT


R2810
IN

ENET_MEDIA_SENSE

12K

402 MF-LF

73 72 55
50 48 33 32 31 30 24 18 8 7 6
54

Ethernet WAKE# Isolation

Q2830

OUT

G
S

PCIE_WAKE_L
3

20%
10V
CERM
402

NC

R2880
100K

PLT_RST_BUF_L

5%
1/16W
MF-LF
2 402

OUT

10 23 26

LPC_CLK33M_SMC

OUT

45 81

LPC_CLK33M_LPCPLUS

OUT

6 47 81

PCH_CLK33M_PCIIN

OUT

16 80

VTT voltage divider on CPU page

R2819 1
10K
5%
1/20W
MF
201

SOT563
1

100K
5%
1/20W
MF
201

6 7 26 37 71 73

ENET_MEDIA_SENSE_EN_L

R2827

5%
1/16W
MF-LF
402
71 57 42 22 20 16 7

ENET_WAKE_L

37 26

ENET_WAKE_L

81 18

SSM6N37FEAPE

PP1V5_S0

PLACE_NEAR=U1800.H49:5.1mm

LPC_CLK33M_SMC_R

IN

R2812

SOT563

22
1

2
5%
1/16W
MF-LF
402

Q2810

26 37

IN

MAKE_BASE=TRUE

0.1UF

16

R2830

SOD-VESM-HF

32 17 6

OUT

1/16W

Q2810

10K

SSM3K15FV

ENET_MEDIA_SENSE_RDIV

CRITICAL
SSM6N37FEAPE3
D

PP3V3_S3

R2811
PP3V3_ENET

C2880

5%

PLT_RST_BUF_L

MAKE_BASE=TRUE
1

PLACE_NEAR=U1800.N32:5mm
37

26
23 10

NC

6
18

R2826

PLACE_NEAR=U1800.H43:5.1mm

LPC_CLK33M_LPCPLUS_R

IN

22
1

2
5%
1/16W
MF-LF
402

5%
1/16W
MF-LF 2
402
2

ENET_MEDIA_SENSE_EN

R2829
18

PLACE_NEAR=U1800.H40:2.54MM:5.1mm

PCH_CLK33M_PCIOUT

IN

22

5%
1/16W
MF-LF
402

NO STUFF

PCH S0 PWRGD

R2863
0

1
85 76 74 73 72 66 56
30 26 24 23 22 20 19 17 8 7
71 62 61 57 54 52 51 50 49
23 22 20 19 18 17 16 12 8 7
46 42 41 40 37 36 33 29 27
85 77 75 74 73

46
6
48
6
26
72

IN

IN

6 7 8 17 19 20 22 23 24 26
30 46 56 66 72 73 74 76 85

PP3V3_S0

ALL_SYS_PWRGD
CPUIMVP_PGOOD

C2860

0.1UF
2

XDP

R2896
78 23 10

SC70-HF

PM_S0_PGOOD

SC70-HF

IN

XDP_DBRESET_L

3.0K

SYS_PWROK_R

5%
1/16W
MF-LF
402

3
3

PM_PCH_SYS_PWROK

OUT

17 23

R2860
SMC_DELAYED_PWRGD

BI

17 45

SYNC_MASTER=LINDA_K90I

Chipset Support
DRAWING NUMBER

R2897

Apple Inc.

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
402

SILK_PART=SYS RESET
PM_PCH_PWROK
PM_PCH_PWROK

OUT

17 26

OUT

17 26

SYNC_DATE=07/08/2010

PAGE TITLE

R2861

MAKE_BASE=TRUE

5%
1/16W
MF-LF
402

PM_SYSRST_L

NO STUFF
0

45 36

5%
1/16W
MF-LF
402

OMIT

PLACE_NEAR=U1800.L22:5.54mm
1

5%
1/16W
MF-LF
402

R2862

MC74VHC1G08

U2860

R2895
10K

20%
10V
CERM
402

MC74VHC1G08

U2850
68

20%
10V
CERM
402

5
73 45 23

71 62 61 57 54 52 51 50 49 48
23 22 20 19 18 17 16 12 8 7 6
46 42 41 40 37 36 33 29 27 26
85 77 75 74 73 72

0.1UF

1K
5%
1/16W
MF-LF
402

PCH Reset Button

PP3V3_S5

C2850

R2850 1

5%
1/16W
MF-LF
402

PP3V3_S5
PP3V3_S0

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

28 OF 109
SHEET

26 OF 86

DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)

Page Notes
72 67 30 29 7 6

PP1V5_S3

Power aliases required by this page:


- =PP1V5_S0_MEM_A

- =PP1V5_S3_MEM_A

C2910

- =PP0V75_S0_MEM_VTT_A

- =PPSPD_S0_MEM_A (2.5 - 3.3V)

Signal aliases required by this page:

- =I2C_SODIMMA_SCL

BOM options provided by this page:

C2912

C2913

C2914

C2915

C2916

C2917

C2918

C2919

C2920

C2921

C2922

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

20%
10V
CERM
402

20%
10V
CERM
402

20%
10V
CERM
402

20%
10V
CERM
402

20%
10V
CERM
402

20%
10V
CERM
402

20%
10V
CERM
402

20%
10V
CERM
402

20%
10V
CERM
402

20%
10V
CERM
402

20%
10V
CERM
402

C2923
0.1UF

20%
10V
CERM
402

C2901
10UF

20%
6.3V
X5R
603

20%
6.3V
X5R
603

31 9 PP0V75_S3_MEM_VREFDQ_A
(NONE)

C2930

C2931

2.2UF

0.1UF
20%
10V

20%
6.3V
2

CERM

CERM
402

402-LF

1
3
73

MEM_A_CKE<0>

75

NC
79 11

IN

77
79

MEM_A_BA<2>

81
79 11

IN

MEM_A_A<12>

83

79 11

IN

MEM_A_A<9>

85
87

79 11

IN

MEM_A_A<8>

89

79 11

IN

MEM_A_A<5>

91
93

79 11

IN

MEM_A_A<3>

95

79 11

IN

MEM_A_A<1>

97
99

79 11

IN

MEM_A_CLK_P<0>

101

79 11

IN

MEM_A_CLK_N<0>

103
105

IN

MEM_A_A<10>

107

IN

MEM_A_BA<0>

109

79 11

IN

MEM_A_WE_L

113

79 11

IN

MEM_A_CAS_L

115

79 11
79 11

111

117
79 11
79 11

IN

MEM_A_A<13>

119

IN

MEM_A_CS_L<1>

121
123

NC

125
127

28

BI

=MEM_A_DQ<32>

129

28

BI

=MEM_A_DQ<33>

131
133

28
28

BI

=MEM_A_DQS_N<4>

135

BI

=MEM_A_DQS_P<4>

137
139

28
28

BI

=MEM_A_DQ<34>

141

BI

=MEM_A_DQ<35>

143
145

28
28

BI

=MEM_A_DQ<40>

147

BI

=MEM_A_DQ<41>

149

IN

GND

151
153
155

28

BI

=MEM_A_DQ<42>

157

28

BI

=MEM_A_DQ<43>

159
161

28

BI

=MEM_A_DQ<48>

163

28

BI

=MEM_A_DQ<49>

165
167

28

BI

=MEM_A_DQS_N<6>

28

BI

=MEM_A_DQS_P<6>

169
171
173

28
28

BI

=MEM_A_DQ<50>

175

BI

=MEM_A_DQ<51>

177
179

28

BI

=MEM_A_DQ<56>

181

28

BI

=MEM_A_DQ<57>

183
185

IN

187

GND

189
28

BI

=MEM_A_DQ<58>

191

28

BI

=MEM_A_DQ<59>

193
195

MEM_A_SA<0>
73 72 71 62 61
42 41 40 37 36
17 16 12 8 7 6 PP3V3_S0
33 29 26 23 22 20 19 18
57 54 52 51 50 49 48 46
85 77 75 74

197
199

MEM_A_SA<1>

201
203

1
1

C2940
20%
6.3V
CERM
402-LF

74

MEM_A_CKE<1>

IN

11 79

28

78

MEM_A_A<15>

IN

11 79

80

MEM_A_A<14>

IN

11 79

5%

1/16W

1/16W

MF-LF

MF-LF
2

BI
BI

=MEM_A_DQ<0>

=MEM_A_DQ<1>

7
9
11

GND

IN

82

13

84

MEM_A_A<11>

IN

11 79

28

86

MEM_A_A<7>

IN

11 79

28

BI

=MEM_A_DQ<2>

15

BI

=MEM_A_DQ<3>

17

88

19

90

MEM_A_A<6>

IN

11 79

28

BI

=MEM_A_DQ<8>

21

92

MEM_A_A<4>

IN

11 79

28

BI

=MEM_A_DQ<9>

23

94

25

96

MEM_A_A<2>

IN

11 79

28

BI

=MEM_A_DQS_N<1>

27

98

MEM_A_A<0>

IN

11 79

28

BI

=MEM_A_DQS_P<1>

29

100

31

102

MEM_A_CLK_P<1>

IN

11 79

28

BI

=MEM_A_DQ<10>

33

104

MEM_A_CLK_N<1>

IN

11 79

28

BI

=MEM_A_DQ<11>

35

106

37

108

MEM_A_BA<1>

110

MEM_A_RAS_L

114
116

BI

=MEM_A_DQ<16>

39

BI

=MEM_A_DQ<17>

41

28

BI

=MEM_A_DQS_N<2>

45

28

BI

=MEM_A_DQS_P<2>

47

IN

11 79

28

IN

11 79

28

MEM_A_CS_L<0>

IN

11 79

MEM_A_ODT<0>

IN

11 79

112

43

118

49

120
122

MEM_A_ODT<1>

IN

28

11 79

NC

28

BI

=MEM_A_DQ<18>

51

BI

=MEM_A_DQ<19>

53

124

55

126

28

128

28

130

=MEM_A_DQ<36>

BI

28

132

MEM_A_DQ<37>

BI

11 28 79

BI

=MEM_A_DQ<24>

57

BI

=MEM_A_DQ<25>

59
61
63

GND

IN

65

134
136

GND

IN

138
140

=MEM_A_DQ<38>

BI

28

142

=MEM_A_DQ<39>

BI

28

146

=MEM_A_DQ<44>

BI

28

148

=MEM_A_DQ<45>

BI

28

152

=MEM_A_DQS_N<5>

BI

28

154

=MEM_A_DQS_P<5>

BI

28

158

=MEM_A_DQ<46>

BI

28

160

=MEM_A_DQ<47>

BI

28

164

=MEM_A_DQ<52>

BI

28

166

=MEM_A_DQ<53>

BI

28

GND

IN

174

=MEM_A_DQ<54>

BI

28

176

=MEM_A_DQ<55>

BI

28

180

=MEM_A_DQ<60>

BI

28

182

=MEM_A_DQ<61>

BI

28

28

BI

=MEM_A_DQ<26>

28

BI

=MEM_A_DQ<27>

67
69
71

VREFDQ
VSS
VSS
DQ4
DQ5
DQ0
CRITICAL
VSS
DQ1
VSS
DQS0*
J2900 DQS0
DM0
F-RT-THB
VSS
VSS
DQ2
DQ6
DQ3
DQ7
VSS
VSS
DQ12
DQ8
DQ13
DQ9
VSS
VSS
DQS1*
DM1
RESET*
DQS1
VSS
VSS
DQ14
DQ10
DQ15
DQ11
VSS
VSS
DQ20
DQ16
DQ17
DQ21
VSS
VSS
DQS2*
DM2
DQS2
VSS
DQ22
VSS
DQ18
DQ23
VSS
DQ19
DQ28
VSS
DQ24
DQ29
VSS
DQ25
DQS3*
VSS
DQS3
DM3
VSS
VSS
DQ30
DQ26
DQ31
DQ27
VSS
VSS

2
4

=MEM_A_DQ<4>

BI

28

=MEM_A_DQ<5>

BI

28

10

MEM_A_DQS_N<0>

BI

11 28 79

12

MEM_A_DQS_P<0>

BI

11 28 79

16

=MEM_A_DQ<6>

BI

28

18

=MEM_A_DQ<7>

BI

28

22

=MEM_A_DQ<12>

BI

28

24

=MEM_A_DQ<13>

BI

28

28

GND

IN

30

14

20

26

MEM_RESET_L

IN

34

=MEM_A_DQ<14>

BI

28

36

=MEM_A_DQ<15>

BI

28

40

=MEM_A_DQ<20>

BI

28

42

=MEM_A_DQ<21>

BI

28

29 30

32

38

44
46

GND

IN

50

=MEM_A_DQ<22>

BI

28

52

=MEM_A_DQ<23>

BI

28

56

=MEM_A_DQ<28>

BI

28

58

=MEM_A_DQ<29>

BI

28

62

=MEM_A_DQS_N<3>

BI

28

64

=MEM_A_DQS_P<3>

BI

28

68

=MEM_A_DQ<30>

BI

28

70

=MEM_A_DQ<31>

BI

28

48

54

60

66

72

KEY

144

516-0229

150

156

162

168
170
172

PP0V75_S3_MEM_VREFCA_A

31

178

2.2UF

186

20%
6.3V

188

=MEM_A_DQS_N<7>

BI

28

C2935

184

20%
10V

CERM

BI

28

192

=MEM_A_DQ<62>

BI

28

194

=MEM_A_DQ<63>

BI

28

CERM
402

402-LF

=MEM_A_DQS_P<7>

C2936
0.1UF

190

196
198

MEM_EVENT_L

OUT

29 45

200

SMBUS_PCH_DATA

BI

202

SMBUS_PCH_CLK

IN

"Factory" (top) slot

16 23 29 31 42 48 62 77 81
16 23 29 31 42 48 62 77 81

204

PP0V75_S0_DDRVTT

7 29 30 67

R2941

5%

402

28

76

10K

10K

2.2UF
2

R2940

CKE0
CKE1
VDD
VDD
NC
J2900 A15
BA2
A14
F-RT-THB
VDD
VDD
A12/BC*
A11
A9
A7
VDD
VDD
A8
A6
A5
A4
VDD
VDD
A3
A2
A1
A0
VDD
VDD
CK1
CK0
CK0*
CK1*
VDD
VDD
A10/AP
BA1
RAS*
BA0
VDD
VDD
WE*
S0*
CAS*
ODT0
VDD
VDD
ODT1
A13
S1*
NC
VDD
VDD
TEST
VREFCA
VSS
VSS
DQ32
DQ36
DQ33
DQ37
VSS
VSS
DM4
DQS4*
DQS4
VSS
DQ38
VSS
DQ39
DQ34
DQ35
VSS
VSS
DQ44
DQ45
DQ40
DQ41
VSS
VSS
DQS5*
DM5
DQS5
VSS
VSS
DQ42
DQ46
DQ43
DQ47
VSS
VSS
DQ48
DQ52
DQ49
DQ53
VSS
VSS
DQS6*
DM6
VSS
DQS6
DQ54
VSS
DQ50
DQ55
DQ51
VSS
VSS
DQ60
DQ56
DQ61
DQ57
VSS
VSS
DQS7*
DM7
DQS7
VSS
VSS
DQ58
DQ62
DQ59
DQ63
VSS
VSS
SA0
EVENT*
VDDSPD
SDA
SCL
SA1
VTT
VTT
(SYMBOL 2 OF 2)

IN

DDR3-SODIMM-DUAL-K6

79 11

KEY

(SYMBOL 1 OF 2)

DDR3-SODIMM-DUAL-K6

C2900
10UF

- =I2C_SODIMMA_SDA

C2911

0.1UF

516-0229
SPD ADDR=0xA0(WR)/0xA1(RD)

402

C2950

C2951

C2952

1UF

1UF

1UF

10%
10V
X5R
402

10%
10V
X5R
402

10%
10V
X5R
402

C2953
1UF

SYNC_MASTER=MASTER

10%
10V
X5R
402

PAGE TITLE

SYNC_DATE=MASTER

DDR3 SO-DIMM Connector A


DRAWING NUMBER

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

29 OF 109
SHEET

27 OF 86

79 28 27 11

MEM_A_DQS_N<0>
MEM_A_DQS_P<0>

MAKE_BASE=TRUE
MAKE_BASE=TRUE

79 11
79 11
79 11
79 11
79 11
79 11
79 11

79 11

MEM_A_DQ<7>
MEM_A_DQ<6>
MEM_A_DQ<5>
MEM_A_DQ<4>
MEM_A_DQ<3>
MEM_A_DQ<2>
MEM_A_DQ<1>
MEM_A_DQ<0>

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MEM_A_DQS_N<0>
MEM_A_DQS_P<0>
GND
=MEM_A_DQ<3>
=MEM_A_DQ<6>
=MEM_A_DQ<1>
=MEM_A_DQ<5>
=MEM_A_DQ<2>
=MEM_A_DQ<7>
=MEM_A_DQ<0>
=MEM_A_DQ<4>

11 27 28 79 79 29 28 11
11 27 28 79 79 29 28 11

MEM_B_DQS_N<0>
MEM_B_DQS_P<0>

27

79 11

27

79 11

27

79 11

27

79 11

27

79 11

27

79 11

27

79 11

27

79 11

79 11

MAKE_BASE=TRUE
MAKE_BASE=TRUE

79 11
79 11
79 11
79 11
79 11
79 11
79 11
79 11

MEM_A_DQ<15>
MEM_A_DQ<14>
MEM_A_DQ<13>
MEM_A_DQ<12>
MEM_A_DQ<11>
MEM_A_DQ<10>
MEM_A_DQ<9>
MEM_A_DQ<8>

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MEM_B_DQ<7>
MEM_B_DQ<6>
MEM_B_DQ<5>
MEM_B_DQ<4>
MEM_B_DQ<3>
MEM_B_DQ<2>
MEM_B_DQ<1>
MEM_B_DQ<0>

=MEM_A_DQS_N<1>
=MEM_A_DQS_P<1>
GND
=MEM_A_DQ<11>
=MEM_A_DQ<10>
=MEM_A_DQ<12>
=MEM_A_DQ<9>
=MEM_A_DQ<15>
=MEM_A_DQ<14>
=MEM_A_DQ<13>
=MEM_A_DQ<8>

27

79 11

27

79 11

MEM_A_DQS_N<2>
MEM_A_DQS_P<2>

MAKE_BASE=TRUE
MAKE_BASE=TRUE

79 11
79 11
79 11
79 11
79 11
79 11
79 11
79 11

MEM_A_DQ<23>
MEM_A_DQ<22>
MEM_A_DQ<21>
MEM_A_DQ<20>
MEM_A_DQ<19>
MEM_A_DQ<18>
MEM_A_DQ<17>
MEM_A_DQ<16>

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MEM_B_DQS_N<1>
MEM_B_DQS_P<1>

27

79 11

27

79 11

27

79 11

27

79 11

27

79 11

27

79 11

27
27

79 11
79 11

MEM_B_DQ<15>
MEM_B_DQ<14>
MEM_B_DQ<13>
MEM_B_DQ<12>
MEM_B_DQ<11>
MEM_B_DQ<10>
MEM_B_DQ<9>
MEM_B_DQ<8>

79 11

MEM_A_DQS_N<3>
MEM_A_DQS_P<3>

MAKE_BASE=TRUE
MAKE_BASE=TRUE

79 11
79 11
79 11
79 11
79 11
79 11
79 11
79 11

MEM_A_DQ<31>
MEM_A_DQ<30>
MEM_A_DQ<29>
MEM_A_DQ<28>
MEM_A_DQ<27>
MEM_A_DQ<26>
MEM_A_DQ<25>
MEM_A_DQ<24>

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

=MEM_A_DQS_N<2>
=MEM_A_DQS_P<2>
GND
=MEM_A_DQ<23>
=MEM_A_DQ<22>
=MEM_A_DQ<21>
=MEM_A_DQ<20>
=MEM_A_DQ<18>
=MEM_A_DQ<19>
=MEM_A_DQ<16>
=MEM_A_DQ<17>

27

79 11

27

79 11

MEM_B_DQS_N<2>
MEM_B_DQS_P<2>

27

79 11

27

79 11

27

79 11

27

79 11

27

79 11

27

79 11

27

79 11

27

79 11

MEM_A_DQS_N<4>
MEM_A_DQS_P<4>

MAKE_BASE=TRUE
MAKE_BASE=TRUE

79 11
79 11
79 28 27 11
79 11
79 11
79 11
79 11
79 11

MEM_A_DQ<39>
MEM_A_DQ<38>
MEM_A_DQ<37>
MEM_A_DQ<36>
MEM_A_DQ<35>
MEM_A_DQ<34>
MEM_A_DQ<33>
MEM_A_DQ<32>

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MEM_B_DQ<23>
MEM_B_DQ<22>
MEM_B_DQ<21>
MEM_B_DQ<20>
MEM_B_DQ<19>
MEM_B_DQ<18>
MEM_B_DQ<17>
MEM_B_DQ<16>

=MEM_A_DQS_N<3>
=MEM_A_DQS_P<3>
GND
=MEM_A_DQ<26>
=MEM_A_DQ<24>
=MEM_A_DQ<28>
=MEM_A_DQ<25>
=MEM_A_DQ<31>
=MEM_A_DQ<27>
=MEM_A_DQ<30>
=MEM_A_DQ<29>

27

79 11

27

79 11

79 11

MEM_A_DQS_N<5>
MEM_A_DQS_P<5>

MAKE_BASE=TRUE
MAKE_BASE=TRUE

79 11
79 11
79 11
79 11
79 11
79 11
79 11
79 11

MEM_A_DQ<47>
MEM_A_DQ<46>
MEM_A_DQ<45>
MEM_A_DQ<44>
MEM_A_DQ<43>
MEM_A_DQ<42>
MEM_A_DQ<41>
MEM_A_DQ<40>

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MEM_B_DQS_N<3>
MEM_B_DQS_P<3>

27

79 11

27

79 11

27

79 11

27

79 11

27

79 11

27

79 11

27
27

79 11
79 11

MEM_B_DQ<31>
MEM_B_DQ<30>
MEM_B_DQ<29>
MEM_B_DQ<28>
MEM_B_DQ<27>
MEM_B_DQ<26>
MEM_B_DQ<25>
MEM_B_DQ<24>

MEM_A_DQS_N<6>
MEM_A_DQS_P<6>

MAKE_BASE=TRUE
MAKE_BASE=TRUE

79 11
79 11
79 11
79 11
79 11
79 11
79 11
79 11

MEM_A_DQ<55>
MEM_A_DQ<54>
MEM_A_DQ<53>
MEM_A_DQ<52>
MEM_A_DQ<51>
MEM_A_DQ<50>
MEM_A_DQ<49>
MEM_A_DQ<48>

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

=MEM_A_DQS_N<4>
=MEM_A_DQS_P<4>
GND
=MEM_A_DQ<38>
=MEM_A_DQ<39>
MEM_A_DQ<37>
=MEM_A_DQ<33>
=MEM_A_DQ<34>
=MEM_A_DQ<35>
=MEM_A_DQ<32>
=MEM_A_DQ<36>

27

79 11

27

79 11

MEM_B_DQS_N<4>
MEM_B_DQS_P<4>

27

79 11

27

79 11

11 27 28 79 79 29 28 11
27
27

79 11
79 11

27

79 11

27

79 11

27

79 11

79 11

MEM_A_DQS_N<7>
MEM_A_DQS_P<7>

MAKE_BASE=TRUE
MAKE_BASE=TRUE

79 11
79 11
79 11
79 11
79 11
79 11
79 11
79 11

MEM_A_DQ<63>
MEM_A_DQ<62>
MEM_A_DQ<61>
MEM_A_DQ<60>
MEM_A_DQ<59>
MEM_A_DQ<58>
MEM_A_DQ<57>
MEM_A_DQ<56>

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

29
29
29
29

29

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

=MEM_B_DQS_N<1>
=MEM_B_DQS_P<1>
GND
=MEM_B_DQ<15>
=MEM_B_DQ<14>
=MEM_B_DQ<13>
=MEM_B_DQ<8>
=MEM_B_DQ<11>
=MEM_B_DQ<10>
=MEM_B_DQ<12>
=MEM_B_DQ<9>

29
29

29
29
29
29
29
29
29
29

MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

=MEM_B_DQS_N<2>
=MEM_B_DQS_P<2>
GND
=MEM_B_DQ<23>
=MEM_B_DQ<18>
=MEM_B_DQ<16>
=MEM_B_DQ<17>
=MEM_B_DQ<22>
=MEM_B_DQ<19>
=MEM_B_DQ<21>
=MEM_B_DQ<20>

29
29

29
29
29
29
29
29
29
29

MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

=MEM_B_DQS_N<3>
=MEM_B_DQS_P<3>
GND
=MEM_B_DQ<26>
=MEM_B_DQ<30>
=MEM_B_DQ<28>
=MEM_B_DQ<29>
=MEM_B_DQ<27>
=MEM_B_DQ<31>
=MEM_B_DQ<25>
=MEM_B_DQ<24>

29
29

29
29
29
29
29
29
29
29

MAKE_BASE=TRUE

MEM_B_DQ<39>
MEM_B_DQ<38>
MEM_B_DQ<37>
MEM_B_DQ<36>
MEM_B_DQ<35>
MEM_B_DQ<34>
MEM_B_DQ<33>
MEM_B_DQ<32>

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

=MEM_B_DQS_N<4>
=MEM_B_DQS_P<4>
GND
=MEM_B_DQ<38>
=MEM_B_DQ<39>
MEM_B_DQ<37>
=MEM_B_DQ<37>
=MEM_B_DQ<34>
=MEM_B_DQ<35>
=MEM_B_DQ<32>
=MEM_B_DQ<36>

29
29

29
29
11 28 29 79
29
29
29
29
29

CPU CHANNEL B DQS 5 -> DIMM B DQS 5

=MEM_A_DQS_N<5>
=MEM_A_DQS_P<5>
GND
=MEM_A_DQ<46>
=MEM_A_DQ<43>
=MEM_A_DQ<45>
=MEM_A_DQ<41>
=MEM_A_DQ<47>
=MEM_A_DQ<42>
=MEM_A_DQ<40>
=MEM_A_DQ<44>

27

79 11

27

79 11

MEM_B_DQS_N<5>
MEM_B_DQS_P<5>

MAKE_BASE=TRUE
MAKE_BASE=TRUE

27

79 11

27

79 11

27

79 11

27

79 11

27

79 11

27

79 11

27
27

79 11
79 11

MEM_B_DQ<47>
MEM_B_DQ<46>
MEM_B_DQ<45>
MEM_B_DQ<44>
MEM_B_DQ<43>
MEM_B_DQ<42>
MEM_B_DQ<41>
MEM_B_DQ<40>

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

=MEM_B_DQS_N<5>
=MEM_B_DQS_P<5>
GND
=MEM_B_DQ<43>
=MEM_B_DQ<46>
=MEM_B_DQ<40>
=MEM_B_DQ<45>
=MEM_B_DQ<47>
=MEM_B_DQ<42>
=MEM_B_DQ<41>
=MEM_B_DQ<44>

29

29

29
29
29
29
29
29
29
29

MAKE_BASE=TRUE

CPU CHANNEL B DQS 6 -> DIMM B DQS 6

=MEM_A_DQS_N<6>
=MEM_A_DQS_P<6>
GND
=MEM_A_DQ<51>
=MEM_A_DQ<54>
=MEM_A_DQ<49>
=MEM_A_DQ<53>
=MEM_A_DQ<50>
=MEM_A_DQ<55>
=MEM_A_DQ<48>
=MEM_A_DQ<52>

27

79 11

27

79 11

MEM_B_DQS_N<6>
MEM_B_DQS_P<6>

MAKE_BASE=TRUE
MAKE_BASE=TRUE

27

79 11

27

79 11

27

79 11

27

79 11

27

79 11

27

79 11

27

79 11

27

79 11

MEM_B_DQ<55>
MEM_B_DQ<54>
MEM_B_DQ<53>
MEM_B_DQ<52>
MEM_B_DQ<51>
MEM_B_DQ<50>
MEM_B_DQ<49>
MEM_B_DQ<48>

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

=MEM_B_DQS_N<6>
=MEM_B_DQS_P<6>
GND
=MEM_B_DQ<54>
=MEM_B_DQ<55>
=MEM_B_DQ<53>
=MEM_B_DQ<49>
=MEM_B_DQ<51>
=MEM_B_DQ<50>
=MEM_B_DQ<48>
=MEM_B_DQ<52>

29
29

29
29
29
29
29
29
29
29

MAKE_BASE=TRUE

CPU CHANNEL B DQS 7 -> DIMM B DQS 7

=MEM_A_DQS_N<7>
=MEM_A_DQS_P<7>
GND
=MEM_A_DQ<58>
=MEM_A_DQ<59>
=MEM_A_DQ<60>
=MEM_A_DQ<57>
=MEM_A_DQ<63>
=MEM_A_DQ<62>
=MEM_A_DQ<61>
=MEM_A_DQ<56>

MAKE_BASE=TRUE

NOTE:

29

MAKE_BASE=TRUE

CPU CHANNEL A DQS 7 -> DIMM A DQS 7


79 11

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

29

CPU CHANNEL B DQS 4 -> DIMM B DQS 4

CPU CHANNEL A DQS 6 -> DIMM A DQS 6


79 11

MAKE_BASE=TRUE

29

MAKE_BASE=TRUE

MAKE_BASE=TRUE

79 11

MAKE_BASE=TRUE

MAKE_BASE=TRUE

CPU CHANNEL A DQS 5 -> DIMM A DQS 5


79 11

MAKE_BASE=TRUE

11 28 29 79

CPU CHANNEL B DQS 3 -> DIMM B DQS 3

MAKE_BASE=TRUE

MAKE_BASE=TRUE

11 28 29 79

MAKE_BASE=TRUE

CPU CHANNEL A DQS 4 -> DIMM A DQS 4


79 11

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

79 11

MAKE_BASE=TRUE

MEM_B_DQS_N<0>
MEM_B_DQS_P<0>
GND
=MEM_B_DQ<3>
=MEM_B_DQ<2>
=MEM_B_DQ<0>
=MEM_B_DQ<4>
=MEM_B_DQ<7>
=MEM_B_DQ<6>
=MEM_B_DQ<5>
=MEM_B_DQ<1>

CPU CHANNEL B DQS 2 -> DIMM B DQS 2

CPU CHANNEL A DQS 3 -> DIMM A DQS 3


79 11

27

79 11

27

79 11

MEM_B_DQS_N<7>
MEM_B_DQS_P<7>

MAKE_BASE=TRUE
MAKE_BASE=TRUE

27

79 11

27

79 11

27

79 11

27

79 11

27

79 11

27

79 11

27

79 11

27

79 11

MEM_B_DQ<63>
MEM_B_DQ<62>
MEM_B_DQ<61>
MEM_B_DQ<60>
MEM_B_DQ<59>
MEM_B_DQ<58>
MEM_B_DQ<57>
MEM_B_DQ<56>

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

=MEM_B_DQS_N<7>
=MEM_B_DQS_P<7>
GND
=MEM_B_DQ<56>
=MEM_B_DQ<59>
=MEM_B_DQ<61>
=MEM_B_DQ<60>
=MEM_B_DQ<63>
=MEM_B_DQ<58>
=MEM_B_DQ<57>
=MEM_B_DQ<62>

29
29

SYNC_MASTER=ANNE_K90I

DDR3 Byte/Bit Swaps

29

DRAWING NUMBER

29
29

Apple Inc.

29

SIZE

D
REVISION

R
29

NOTICE OF PROPRIETARY PROPERTY:

29

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

29

MAKE_BASE=TRUE

SYNC_DATE=06/22/2010

PAGE TITLE

29

Sandybridge does not use DM signals per doc 438297 Huron River SFF DG rev1.0 Section 2.6.13

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

CPU CHANNEL A DQS 2 -> DIMM A DQS 2


79 11

CPU CHANNEL B DQS 1 -> DIMM B DQS 1

MAKE_BASE=TRUE

79 11

MAKE_BASE=TRUE

CPU CHANNEL A DQS 1 -> DIMM A DQS 1


MEM_A_DQS_N<1>
MEM_A_DQS_P<1>

MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE

79 11

CPU CHANNEL B DQS 0 -> DIMM B DQS 0

CPU CHANNEL A DQS 0 -> DIMM A DQS 0


79 28 27 11

BRANCH

PAGE

30 OF 109
SHEET

28 OF 86

DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)

Page Notes
72 67 30 27 7 6

PP1V5_S3

Power aliases required by this page:


- =PP1V5_S0_MEM_B

- =PP1V5_S3_MEM_B
- =PP0V75_S0_MEM_VTT_B

Signal aliases required by this page:

C3100

- =I2C_SODIMMB_SCL

BOM options provided by this page:

C3112

C3113

C3114

C3115

C3116

C3117

C3118

C3119

C3120

C3121

C3122

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

20%
10V
CERM
402

20%
10V
CERM
402

20%
10V
CERM
402

20%
10V
CERM
402

20%
10V
CERM
402

20%
10V
CERM
402

20%
10V
CERM
402

20%
10V
CERM
402

20%
10V
CERM
402

20%
10V
CERM
402

C3123
0.1UF

20%
10V
CERM
402

10UF

20%
6.3V
X5R
603

0.1UF

20%
10V
CERM
402

C3101

10UF

- =I2C_SODIMMB_SDA

C3111

0.1UF
2

- =PPSPD_S0_MEM_B (2.5 - 3.3V)

20%
6.3V
X5R
603

31 9 PP0V75_S3_MEM_VREFDQ_B
(NONE)

C3130

C3131

2.2UF

0.1UF
20%
10V

20%
6.3V
2

CERM
402-LF

CERM
402

1
3

75

NC
79 11

79

MEM_B_BA<2>

IN

77

81
79 11

IN

MEM_B_A<12>

83

79 11

IN

MEM_B_A<9>

85
87

79 11

IN

MEM_B_A<8>

89

79 11

IN

MEM_B_A<5>

91
93

79 11

IN

MEM_B_A<3>

95

79 11

IN

MEM_B_A<1>

97
99

79 11

IN

MEM_B_CLK_P<0>

101

79 11

IN

MEM_B_CLK_N<0>

103
105

IN

MEM_B_A<10>

107

IN

MEM_B_BA<0>

109

79 11

IN

MEM_B_WE_L

113

79 11

IN

MEM_B_CAS_L

115

79 11
79 11

111

117
79 11
79 11

IN

MEM_B_A<13>

119

IN

MEM_B_CS_L<1>

121
123

NC

125
127

28

BI

=MEM_B_DQ<32>

129

79 28 11

BI

MEM_B_DQ<37>

131
133

28
28

BI

=MEM_B_DQS_N<4>

135

BI

=MEM_B_DQS_P<4>

137
139

28
28

BI

=MEM_B_DQ<34>

141

BI

=MEM_B_DQ<35>

143
145

28
28

BI

=MEM_B_DQ<40>

147

BI

=MEM_B_DQ<41>

149

IN

GND

151
153
155

28

BI

=MEM_B_DQ<42>

157

28

BI

=MEM_B_DQ<43>

159
161

28

BI

=MEM_B_DQ<48>

163

28

BI

=MEM_B_DQ<49>

165
167

28

BI

=MEM_B_DQS_N<6>

28

BI

=MEM_B_DQS_P<6>

169
171
173

28
28

BI

=MEM_B_DQ<50>

175

BI

=MEM_B_DQ<51>

177
179

28

BI

=MEM_B_DQ<56>

181

28

BI

=MEM_B_DQ<57>

183
185
187

GND

IN

189
28

BI

=MEM_B_DQ<58>

191

28

BI

=MEM_B_DQ<59>

193
195

MEM_B_SA<0>
85 77 75 74 73
49 48 46 42 41 40
18 17 16 12 8 7 6 PP3V3_S0
37 36 33 27 26 23 22 20 19
72 71 62 61 57 54 52 51 50

197
199

MEM_B_SA<1>

201
203

1
1

C3140
20%
6.3V

CERM
402-LF

R3140
10K

2.2UF

R3141
10K

5%

5%

1/16W

1/16W

MF-LF

MF-LF

402

402

205
207
209
211

CKE0
CKE1
VDD
VDD
NC
A15
A14
BA2
J3100
VDD
VDD
F-RT-BGA6
A11
A12/BC*
A9
A7
VDD
VDD
A8
A6
A5
A4
VDD
VDD
A3
A2
A1
A0
VDD
VDD
CK1
CK0
CK0*
CK1*
VDD
VDD
A10/AP
BA1
RAS*
BA0
VDD
VDD
S0*
WE*
CAS*
ODT0
VDD
VDD
ODT1
A13
S1*
NC
VDD
VDD
TEST
VREFCA
VSS
VSS
DQ36
DQ32
DQ37
DQ33
VSS
VSS
DQS4*
DM4
DQS4
VSS
VSS
DQ38
DQ34
DQ39
DQ35
VSS
DQ44
VSS
DQ40
DQ45
DQ41
VSS
VSS
DQS5*
DM5
DQS5
VSS
VSS
DQ42
DQ46
DQ47
DQ43
VSS
VSS
DQ52
DQ48
DQ53
DQ49
VSS
VSS
DQS6*
DM6
DQS6
VSS
VSS
DQ54
DQ50
DQ55
DQ51
VSS
VSS
DQ60
DQ56
DQ61
DQ57
VSS
DQS7*
VSS
DM7
DQS7
VSS
VSS
DQ58
DQ62
DQ59
DQ63
VSS
VSS
EVENT*
SA0
VDDSPD
SDA
SA1
SCL
VTT
VTT
(2 OF 2)

73

MEM_B_CKE<0>

IN

DDR3-SODIMM

79 11

KEY

MTG PINS

MTG PIN
MTG PIN
MTG PIN
MTG PIN

74

MEM_B_CKE<1>

IN

11 79

28

76

28

78

MEM_B_A<15>

IN

11 79

80

MEM_B_A<14>

IN

11 79

BI
BI

=MEM_B_DQ<0>

=MEM_B_DQ<1>

7
9

IN

11

GND

82

13

84

MEM_B_A<11>

IN

11 79

28

86

MEM_B_A<7>

IN

11 79

28

BI

=MEM_B_DQ<2>

15

BI

=MEM_B_DQ<3>

17

88

19

90

MEM_B_A<6>

IN

11 79

28

BI

=MEM_B_DQ<8>

21

92

MEM_B_A<4>

IN

11 79

28

BI

=MEM_B_DQ<9>

23

94

25

96

MEM_B_A<2>

IN

11 79

28

BI

=MEM_B_DQS_N<1>

27

98

MEM_B_A<0>

IN

11 79

28

BI

=MEM_B_DQS_P<1>

29

100

31

102

MEM_B_CLK_P<1>

IN

11 79

28

BI

=MEM_B_DQ<10>

33

104

MEM_B_CLK_N<1>

IN

11 79

28

BI

=MEM_B_DQ<11>

35

106

37

108

MEM_B_BA<1>

110

MEM_B_RAS_L

114
116

BI

=MEM_B_DQ<16>

39

BI

=MEM_B_DQ<17>

41

28

BI

=MEM_B_DQS_N<2>

45

28

BI

=MEM_B_DQS_P<2>

47

IN

11 79

28

IN

11 79

28

MEM_B_CS_L<0>

IN

11 79

MEM_B_ODT<0>

IN

11 79

112

43

118

49

120
122

MEM_B_ODT<1>

IN

28

11 79

NC

28

BI

=MEM_B_DQ<18>

51

BI

=MEM_B_DQ<19>

53

124

55

126

28

128

28

130

=MEM_B_DQ<36>

BI

28

132

=MEM_B_DQ<37>

BI

28

BI

=MEM_B_DQ<24>

57

BI

=MEM_B_DQ<25>

59
61

IN

63

GND

65

134
136

GND

IN

138
140

=MEM_B_DQ<38>

BI

28

142

=MEM_B_DQ<39>

BI

28

146

=MEM_B_DQ<44>

BI

28

148

=MEM_B_DQ<45>

BI

28

152

=MEM_B_DQS_N<5>

BI

28

154

=MEM_B_DQS_P<5>

BI

28

158

=MEM_B_DQ<46>

BI

28

160

=MEM_B_DQ<47>

BI

28

164

=MEM_B_DQ<52>

BI

28

166

=MEM_B_DQ<53>

BI

28

GND

IN

174

=MEM_B_DQ<54>

BI

28

176

=MEM_B_DQ<55>

BI

28

180

=MEM_B_DQ<60>

BI

28

182

=MEM_B_DQ<61>

BI

28

28

BI

=MEM_B_DQ<26>

28

BI

=MEM_B_DQ<27>

67
69
71

VREFDQ
VSS
VSS
DQ4
DQ5
DQ0
CRITICAL
DQ1
VSS
VSS
DQS0*
J3100 DQS0
DM0
F-RT-BGA6
VSS
VSS
DQ2
DQ6
DQ3
DQ7
VSS
VSS
DQ8
DQ12
DQ9
DQ13
VSS
VSS
DQS1*
DM1
DQS1
RESET*
VSS
VSS
DQ14
DQ10
DQ11
DQ15
VSS
VSS
DQ16
DQ20
DQ17
DQ21
VSS
VSS
DQS2*
DM2
DQS2
VSS
DQ22
VSS
DQ18
DQ23
VSS
DQ19
VSS
DQ28
DQ29
DQ24
VSS
DQ25
DQS3*
VSS
DM3
DQS3
VSS
VSS
DQ26
DQ30
DQ27
DQ31
VSS
VSS
(1 OF 2)

DDR3-SODIMM

C3110

2
4

=MEM_B_DQ<4>

BI

28

=MEM_B_DQ<5>

BI

28

10

MEM_B_DQS_N<0>

BI

11 28 79

12

MEM_B_DQS_P<0>

BI

11 28 79

16

=MEM_B_DQ<6>

BI

28

18

=MEM_B_DQ<7>

BI

28

22

=MEM_B_DQ<12>

BI

28

24

=MEM_B_DQ<13>

BI

28

28

GND

IN

30

14

20

26

MEM_RESET_L

IN

34

=MEM_B_DQ<14>

BI

28

36

=MEM_B_DQ<15>

BI

28

40

=MEM_B_DQ<20>

BI

28

42

=MEM_B_DQ<21>

BI

28

27 30

32

38

44
46

GND

IN

50

=MEM_B_DQ<22>

BI

28

52

=MEM_B_DQ<23>

BI

28

56

=MEM_B_DQ<28>

BI

28

58

=MEM_B_DQ<29>

BI

28

62

=MEM_B_DQS_N<3>

BI

28

64

=MEM_B_DQS_P<3>

BI

28

68

=MEM_B_DQ<30>

BI

28

70

=MEM_B_DQ<31>

BI

28

48

54

60

66

72

KEY

144

516S0806

150

156

162

168
170
172

PP0V75_S3_MEM_VREFCA_B

31

178

2.2UF

186

20%
6.3V

188

=MEM_B_DQS_N<7>

BI

28

C3135

184

20%
10V

CERM

BI

28

192

=MEM_B_DQ<62>

BI

28

194

=MEM_B_DQ<63>

BI

28

CERM
402

402-LF

=MEM_B_DQS_P<7>

C3136
0.1UF

190

196
198

MEM_EVENT_L

OUT

27 45

200

SMBUS_PCH_DATA

BI

202

SMBUS_PCH_CLK

IN

16 23 27 31 42 48 62 77 81

"Expansion" (bottom) slot


16 23 27 31 42 48 62 77 81

204

MTG PIN

206

MTG PIN

208

MTG PIN

210

MTG PIN

212

PP0V75_S0_DDRVTT

C3150

C3151

C3152

1UF

1UF

1UF

10%
10V
X5R
402

10%
10V
X5R
402

10%
10V
X5R
402

7 27 30 67

C3153
1UF

SYNC_MASTER=MASTER

10%
10V
X5R
402

PAGE TITLE

SYNC_DATE=MASTER

DDR3 SO-DIMM Connector B


DRAWING NUMBER

516S0806

Apple Inc.

SPD ADDR=0xA4(WR)/0xA5(RD)

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

31 OF 109
SHEET

29 OF 86

The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well
as isolating the CPUs SM_DRAMRST# output from the SO-DIMMs when necessary.
ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.

WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated.

WHEN LOW:

CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.

P1V5CPU_EN

= (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L

MEMVTT_EN

= (ISOLATE_CPU_MEM_L + PLT_RST_L)

1V5 S0 "PGOOD" for CPU

* PM_SLP_S3_L

MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L

PP3V3_S5

46 26 24 23 22 20 19 17 8 7 6
85 76 74 73 72 66 56

73 45 17 6

IN

PM_SLP_S4_L

PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page


CPUMEM_S0
1

R3205

85 73 72 15 12 10 7 6

PP1V5_S3RS0

PM_MEM_PWRGD
1

10K
5%
1/16W
MF-LF
2 402

OUT

R3220 1

72

5%
1/16W
MF-LF
402

CRITICAL

27.4K

PP3V3_S3

CPUMEM_S0

Q3205

CPUMEM_S0

1%
1/16W
MF-LF
402

SSM6N37FEAPE

R3201 1

10 17 78

10K

P1V5CPU_EN
50 48 33 32 31 26 24 18 8 7 6
73 72 55 54

OUT

R3222

Q3220
DMB53D0UV
SOT-563

PM_MEM_PWRGD_L
2

SOT563

100K
5%
1/16W
MF-LF
402

CRITICAL

3
2

P1V5_S0_DIV
1

Q3220

DMB53D0UV

SOT-563

P1V5CPU_EN_L
4

CPUMEM_S0

CPUMEM_S0

Q3200

SSM6N37FEAPE

IN

1%
1/16W
MF-LF
402

SOT563

NO STUFF

C3220

33.2K

SSM6N37FEAPE

SOT563

23 19

R3221

Q3205

0.001UF
20%
50V
CERM
402

ISOLATE_CPU_MEM_L

PM_SLP_S3_L

IN

6 17 45 73

CPUMEM_S0
1

R3210
10K

5%
1/16W
MF-LF
2 402

MEMVTT_EN

PP5V_S3

59 57 46 44 43 42 32 30 7 6
72 67 66 61 60

OUT

8 30 67

MEMVTT Clamp

CPUMEM_S0
CPUMEM_S0

R3215

Q3210

CPUMEM_S0

R3202

100K

100K

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

Ensures CKE signals are held low in S3

SSM6N37FEAPE

SOT563

67 29 27 7

PP0V75_S0_DDRVTT
CPUMEM_S0

MEMVTT_EN_L

R3250
CPUMEM_S0

CPUMEM_S0

Q3200

Q3215

5%
1/10W
MF-LF
603

Q3210

SSM6N37FEAPE

SSM6N37FEAPE

SOT563

SOT563

SSM6N37FEAPE

75mA max load @ 0.75V


60mW max power
2

VTTCLAMP_L

SOT563

10

CPUMEM_S0

59 57 46 44 43 42 32 30 7 6
72 67 66 61 60

PP5V_S3

CPUMEM_S0

Q3250

CPUMEM_S0

PLT_RESET_L

IN

18 26 33 36 40

SSM6N37FEAPE

R3251 1

SOT563

100K
5%
1/16W
MF-LF
402

PP1V5_S3
CPUMEM_S0

Q3215

SSM6N37FEAPE

C3216

CPUMEM_S0

0.1UF

5%
1/16W
MF-LF
402

Q3250

10%
16V
X5R
402

OUT

20%
50V
CERM
402

27 29

67 30 8

CPUMEM_S3

IN

0.001UF

SOT563

MEM_RESET_L

NO STUFF

C3251

SSM6N37FEAPE

CPU_MEM_RESET_L
MAKE_BASE=TRUE

R3216

30
10

CPU_MEM_RESET_L

IN

CPUMEM_S0

20K

SOT563

2
30 10

VTTCLAMP_EN

CPUMEM_S0

MEMRESET_ISOL_LS5V_L

6 7 27 29 67 72

MEMVTT_EN

R3217
1

5%
1/16W
MF-LF
402

Step

S0
to

S3
to
S0

PM_SLP_S3_L

PM_SLP_S4_L

CPU_MEM_RESET_L

0
1
2
3

ISOLATE_CPU_MEM_L
1
0
0
0

PLT_RESET_L
1
1
0
0

1
1
1
0

1
1
1
1

1
1
1
X

CPU_MEM_RESET_L
1
1
1

MEM_RESET_L

MEMVTT_EN
1
1
0
0

P1V5CPU_EN
1
1
1
0

4
5
6
7

0
0
0
1

0
1
1
1

1
1
1
1

1
1
1
1

X
0 (*)
1
1

1
1
1
CPU_MEM_RESET_L

0
1
1
1

1
1
1
1

SYNC_MASTER=ANNE_K90I

CPU Memory S3 Support


DRAWING NUMBER

Apple Inc.
(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.

NOTICE OF PROPRIETARY PROPERTY:

Rails will power-up as if from S3, but MEM_RESET_L will not properly assert.

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

Software

must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.

SIZE

D
REVISION

NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0
transition.

SYNC_DATE=06/22/2010

PAGE TITLE

BRANCH

PAGE

32 OF 109
SHEET

30 OF 86

NOTE: Must not enable more than two SO-DIMM margining


50 48 33 32 30 26 24 18 8 7 6
73 72 55 54

buffers at once or VRef source may be overloaded.

PP3V3_S3

VREFMRGN

OMIT

R3318
SHORT
1

67 7

10mA max load

PP3V3_S3_VREFMRGN_DAC
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

NONE
NONE
NONE
402

VREFMRGN

C3300
20%
6.3V
CERM
402-LF

C3301

C3303

CRITICAL
VREFMRGN

20%
10V
CERM
402

U3300

SMBUS_PCH_CLK

6 SCL

SMBUS_PCH_DATA

7 SDA

MSOP

9 A0

Addr=0x98(WR)/0x99(RD)

VOUTA

VREFMRGN_SODIMMA_DQ

VOUTB

VREFMRGN_SODIMMB_DQ

VOUTC

VREFMRGN_SODIMMS_CA

VOUTD

V+

VREFMRGN

U3302

B1
A2

MAX4253

A1
A3

VREFMRGN_DQ_SODIMMA_BUF

10 A1

A4

V-

R3305
1

VREFMRGN
1

5%
1/16W
MF-LF
402

OMIT

VREFMRGN

U3302
MAX4253

VREFMRGN

C3302

20%
10V
CERM
402

U3301
(OD)

Addr=0x30(WR)/0x31(RD)

81 77 62 48 42 31 29 27 23 16

IN
BI

SMBUS_PCH_CLK
SMBUS_PCH_DATA

1
2

A0
A1
A2

SCL
SDA
THRM

200
1

P0
P1
P2
P3
P4
P5
P6
P7

RESET*

NC
VREFMRGN_DQ_SODIMMA_EN
VREFMRGN_DQ_SODIMMB_EN
VREFMRGN_CA_SODIMMA_EN
VREFMRGN_CA_SODIMMB_EN
VREFMRGN_MEMVREG_EN
VREFMRGN_FRAMEBUF_EN

7
9
10
11
12
13

5%
1/16W
MF-LF
402

1%
1/16W
MF-LF
402

VREFMRGN

C3304

VREFMRGN

20%
10V
CERM
402

A2

V+

MAX4253
A1

A3

VREFMRGN_CA_SODIMMA_BUF

VREFMRGN

R3311

PCA9557D_RESET_L
2

RST* on platform reset so that system


watchdog will disable margining.

R3307

VREFMRGN
C2

V+

CRITICAL

R3303,R3305

RES,MTL FILM,0,5%,0402,SM,LF

R3308
100K

VREFMRGN_NOT

R3309,R3311

RES,MTL FILM,0,5%,0402,SM,LF

UCSP

VREFMRGN_CA_SODIMMB_BUF

2
1%
1/16W
MF-LF
402

V-

PLACE_NEAR=R3311.2:1mm

VREFMRGN

C3305

5%
1/16W
MF-LF
402

VREFMRGN

0.1UF
20%
10V
CERM
402

VREFMRGN_NOT

C2

V+

VREFMRGN

U3304

B1
2

C3

MAX4253

R3314

UCSP

VREFMRGN_MEMVREG_BUF

Page Notes

VREFMRGN

Power aliases required by this page:


- =PP3V3_S3_VREFMRGN
- =PPVTT_S3_DDR_BUF

V-

Signal aliases required by this page:


- =I2C_VREFDACS_SCL
- =I2C_VREFDACS_SDA
- =I2C_PCA9557D_SCL
- =I2C_PCA9557D_SDA

33.2K

DDRREG_FB

OUT

67

PLACE_NEAR=R7315.2:1mm

VREFMRGN_FRAMEBUF_BUF

R3313

VREFMRGN

100K

U3304

B1

5%
1/16W
MF-LF
402

1%
1/16W
MF-LF
402

C4
B4

A2

V+

MAX4253
UCSP
A1

A3

A4

VB4

BOM options provided by this page:


VREFMRGN
- Stuffs VREF Margining
Circuitry.
VREFMRGN_NOT - Bypasses VREF Margining
Circuitry.

VREFMRGN
1

R3315
100K

MEM A VREF DQ

MEM B VREF DQ

MEM A VREF CA

MEM B VREF CA

5%
1/16W
MF-LF
402

MEM VREG

GPU Frame Buffer (1.8V, 70% VRef)

DAC Channel:

PCA9557D Pin:

Nominal value

DRAWING NUMBER

1.267V (DAC: 0x8B)

Margined target:

0.300V - 1.200V (+/- 450mV)

1.998V - 1.002V (+/- 498mV)

1.056V - 1.442V (+/- 180mV)

DAC range:

0.000V - 1.501V (0x00 - 0x74)

0.000V - 1.501V (0x00 - 0x74)

0.000V - 3.300V (0x00 - 0xFF)

VRef current:

+3.4mA - -3.4mA (- = sourced)

DAC step size:

7.69mV / step @ output

-33uA (- = sourced)

+6.0mA - -5.0mA (- = sourced)

8.59mV / step @ output

1.51mV / step @ output

SYNC_DATE=06/01/2010

PAGE TITLE

Apple Inc.

1.5V (DAC: 0x3A)

+33uA -

SYNC_MASTER=K91_MLB

FSB/DDR3/FRAMEBUF Vref Margining

0.75V (DAC: 0x3A)

133
1

C4

C1

29

VREFMRGN
1

BOM OPTION
2

116S0004

PP0V75_S3_MEM_VREFCA_B
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V

R3312

B4

Required zero ohm resistors when no VREF margining circuit stuffed

116S0004

MAX4253
C1

C3

REFERENCE DES

PLACE_NEAR=J3100.126:2.54mm

VREFMRGN

U3303

B1

5%
1/16W
MF-LF
402

NOTE: Margining will be disabled across all


soft-resets and sleep/wake cycles.

DESCRIPTION

200
1%
1/16W
MF-LF
402

100K

QTY

PLACE_NEAR=R3309.2:1mm

NC

VREFMRGN

PART NUMBER

2
1%
1/16W
MF-LF
402

A4

V-

15

IN

133
1

B4
14

27

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V

R3310

UCSP

PP0V75_S3_MEM_VREFCA_A

VREFMRGN

U3303

B1

0.1UF

26

PLACE_NEAR=J2900.126:2.54mm

100K

GND

17

PAD

PLACE_NEAR=R3305.2:1mm

R3309

R3302

VREFMRGN

PCA9557
QFN

81 77 62 48 42 31 29 27 23 16

V-

VREFMRGN
1

133
1%
1/16W
MF-LF
402

CRITICAL
VREFMRGN

VCC

0.1UF

B4

16

NONE
NONE
NONE
402

PP3V3_S3_VREFMRGN_CTRL

VREFMRGN_DQ_SODIMMB_BUF

C4

9 29

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V

R3306

UCSP
C1

C3
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

PLACE_NEAR=J3100.1:2.54mm

PP0V75_S3_MEM_VREFDQ_B

VREFMRGN
B1
C2

V+

200
1%
1/16W
MF-LF
402

R3301

R3319
1

PLACE_NEAR=R3303.2:1mm

VREFMRGN

100K

SHORT

1%
1/16W
MF-LF
402

VREFMRGN_MEMVREG_FBVREF
NOTE: MEMVREG and FRAMEBUF share
a DAC output, cannot enable
both at the same time!

GND

133

9 27

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V

R3304

UCSP

B4

DAC5574

IN
BI

PLACE_NEAR=J2900.1:2.54mm

PP0V75_S3_MEM_VREFDQ_A

VREFMRGN

0.1UF
20%
10V
CERM
402

200
1%
1/16W
MF-LF
402

VREFMRGN

0.1UF

VDD

81 77 62 48 42 31 29 27 23 16

R3303
1

VREFMRGN

2.2UF

81 77 62 48 42 31 29 27 23 16

PPVTTDDR_S3

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

33 OF 109
SHEET

31 OF 86

L3470

OMIT

0.6NH+/-0.1NH-0.85A

PLACE_NEAR=J3401.15:2.54mm

C3431
1

NOSTUFF 1

2
0201

81

NOSTUFF 1

C3470
1.0PF

C3471

10%

1.0PF

+/-0.1PF
25V
2 C0G
201

PCIE_AP_R2D_PI_P

10%

0.1UF

0.1UF

PCIE_AP_R2D_C_P

IN

16 81

16V X5R-CERM0201

PCIE_AP_R2D_C_N

IN

16 81

16V X5R-CERM0201

C3430

+/-0.1PF
25V
2 C0G
201

PLACE_NEAR=J3401.17:2.54mm

L3471

0.6NH+/-0.1NH-0.85A

OMIT

NOSTUFF

2
0201

C3472

81

NOSTUFF 1

1.0PF

2
0201

C3474

MF-LF 402

BI

10%
16V
X5R-CERM
0201

6 45 48 51 84

L3473

SMBUS_SMC_0_S0_SCL

MF-LF 402

P-TYPE
20-30 MOHM @2.5V

IN

6 45 48 51 84

NOSTUFF
OUT

45 46

NOSTUFF 1

CRITICAL

C3477

0.1UF

0.1UF

10%
16V
X5R-CERM
0201

10%
16V
X5R-CERM
0201

Q3450
155S0367

L3404

PP3V3_WLAN

46 6

PCIE_AP_R2D_N

C3422

516S0582
CRITICAL

J3401

81 6

CRITICAL

81 6

PP3V3_WLAN_F

0603

C3421

0.1uF

0.1uF

20%
10V
CERM
402

20%
10V
CERM
402

PLACE_NEAR=Q3450.6:2.54mm

PCIE_AP_D2R_PI_N

C3451

10UF
2

10%
16V
X5R
402

C3450
0.1UF
1

R3450

P3V3WLAN_SS

33K

5%
1/16W
MF-LF
402

PM_WLAN_EN_L

IN

73

5%
1/16W
MF-LF
402

10%
16V
X5R
402-1

90-OHM-100MA
DLP11S

R3451
10K

0.033UF

20%
10V
X5R
805

AIRPORT

L3401

50 54 55 72 73
6 7 8 18 24 26
30 31 32 33 48

PP3V3_S3

C3420

PLACE_NEAR=J3401.29:2.54mm

PCIE_AP_D2R_PI_P

500913-0302
F-ST-SM
32
31

32

PCIE_AP_R2D_P

23V1K-SM

MIN_NECK_WIDTH=0.4 mm
MIN_LINE_WIDTH=1 mm

FERR-120-OHM-3A
MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.2 mm

81 6

TPCP8102

2
727 MA PEAK

81 6

0.727 A (EDP)

2
0201

C3476 1

WIFI_EVENT_L

MF-LF 402

LOADING

OMIT 0.6NH+/-0.1NH-0.85A

606 MA NOMINAL MAX

TPCP8102

CHANNEL

5% 1/16W

WIFI_EVENT_L_R

MOSFET

0.1UF
10%
16V
X5R-CERM
0201

RDS(ON)

R3402
6

3V S3 WLAN FET

16 81

4 G

5% 1/16W

16 81

OUT

AP_TEMP_SMB_SCL_R

OUT

PCIE_AP_D2R_N

PCIE_AP_D2R_P

C3475

R3401
0

NOSTUFF 1

0.1UF

SMBUS_SMC_0_S0_SDA

BOM OPTION

6 7

5% 1/16W

CRITICAL

L3470,L3471,L3472,L3473

0.6NH+/-0.1NH-0.85A

NOSTUFF
1

R3400

REFERENCE DES

RES, 0ohm, 0201

+/-0.1PF
25V
2 C0G
201

DESCRIPTION

L3472

OMIT

AP_TEMP_SMB_SDA_R

QTY

117S0002

1.0PF

+/-0.1PF
25V
2 C0G
201

PART NUMBER

PCIE_AP_R2D_PI_N

C3473

SYM_VER-1

85 6

PCIE_CLK100M_AP_CONN_P

85 6

PCIE_CLK100M_AP_CONN_N

10

12

11

14

13

16

15

18

17

20

19

22

21

24

23

26

25

28

27

PCIE_CLK100M_AP_P

IN

16 81

PCIE_CLK100M_AP_N

IN

16 81

PLACE_NEAR=J3401.11:2.54mm

BLUETOOTH

PP3V3_S3_BT_F

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm

29

Delay = 60 ms +/- 20%

USB_BT_P

BI

6 24 80

USB_BT_N

BI

6 24 80

PP3V3_WLAN_F

PP3V3_S3
32

1 C3432

33

Supervisor & CLKFREG # ISolation

L3406
2

0.01UF

34

10%
16V
CERM
402

PP3V3_S3

6 7 8 18 24 26 30 31 32 33 48
50 54 55 72 73

6 7 8 18 24 26 30 31 32 33 48
50 54 55 72 73

FERR-120-OHM-1.5A

0402-LF

R3453

1%
1/16W
MF-LF

402

CRITICAL

R3454

VDD

232K

100K

PLACE_NEAR=J3401.27:2.54mm

30

U3440

1%
1/16W
MF-LF
402

TDFN

P3V3WLAN_VMON
2

SENSE +
0.7V -

RESET*

C3440
0.1uF

SLG4AP016V

20%
10V
CERM
402

DLY

AP_CLKREQ_Q_L
7

PCIE_WAKE_L

OUT

6 17 26

518S0815

IN

R3455

MR*

EN
OUT

AP_RESET_L
IN

26

IN

18 73

OUT

16 23

AP_PWR_EN
8

(OD)

AP_CLKREQ_L

THRM
PAD

GND
5

AP_RESET_CONN_L

100K
1%
1/16W
MF-LF

CRITICAL

J3402

402

819Q-3506-K281
F-RT-SM1
8
6

6
5
4

80 6

80 6

PP5V_S3_ALSCAMERA_F
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA
USB_CAMERA_CONN_P
USB_CAMERA_CONN_N

IN
BI

6 45 48 54 55 84

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm

275 mA peak
206 mA nominal max

6 45 48 54 55 84

PLACE_NEAR=J3402.6:2.54MM

ALS

L3408
FERR-120-OHM-1.5A

CAMERA

CRITICAL

PP5V_S3

SYNC_MASTER=K91_MLB
6 7 30 42 43 44 46 57 59 60 61
66 67 72

L3407

90-OHM
DLP0NS

X19/ALS/CAMERA CONNECTOR

C3452

DRAWING NUMBER

0.1uF

SYM_VER-1

USB_CAMERA_P

BI

18 80

USB_CAMERA_N

BI

18 80

Apple Inc.

20%
10V
CERM
402

NOTICE OF PROPRIETARY PROPERTY:

SIZE

D
REVISION

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

PLACE_NEAR=J3402.2:2.54MM

SYNC_DATE=05/15/2010

PAGE TITLE

0402-LF

BRANCH

PAGE

34 OF 109
SHEET

32 OF 86

SD CARD 3.3V OVERCURRENT PROTECTION CHIP WITH ACTIVE LOAD DISCHARGE


TPS2065-1 (1.0A limit) has active load discharge so R4810 is NOSTUFF.

CRITICAL

U3500

PP3V3_S0_SW_SD_PWR

33

TPS2065-1
DGN OUT0

37

PP3V3_S0

ENET_CR_PWREN

C3500
10UF

0.1UF

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

1
1

C3502
10UF

R3500

C3503

47K

0.1UF

5%
1/16W
MF-LF
2 402

10%
2 16V
X7R-CERM
402

20%
2 6.3V
X5R
603

10%
2 16V
X7R-CERM
402

20%
2 6.3V
X5R
603

33

MAKE_BASE=TRUE

NOSTUFF

THRM
PAD

GND

C3501

PP3V3_S0_SW_SD_PWR

71 62 61 57 54 52 51 50 49 48
23 22 20 19 18 17 16 12 8 7 6
46 42 41 40 37 36 33 29 27 26
85 77 75 74 73 72

6
OUT1 7
OUT2 8
353S0004
EN
OC* 5

2 IN0
3 IN1

48 49 50 51 52 54 57 61 62 71
6 7 8 12 16 17 18 19 20 22 23
26 27 29 33 36 37 40 41 42 46
72 73 74 75 77 85

PP3V3_S0
1

R3501
10K

5%
1/16W
MF-LF
402 2

R3502
SDCONN_OC_L_R

SDCONN_OC_L

5%
1/16W
MF-LF
402

SDCONN DETECT DEBOUNCE. ENET_RESET AND DETECT-CHANGED PCH GPIO PULSE GENERATION.
50 48 32 31 30 26 24 18 8 7 6
73 72 55 54

PP3V3_S3

C3510

1UF
10%
10V
X5R
402-1

CRITICAL

VDD

U3511
SLG4AP014V
TDFN
2

ENET_LOW_PWR

IN

RST
LOGIC

R3511
40 36 30 26 18

IN

PLT_RESET_L

5%
1/16W
MF-LF
402

-> FROM PCH GPIO

SLG_ENET_RESET_L

NOSTUFF
33

R3510
10K

5%
1/16W
MF-LF
402

SDCONN_DETECT

RST_IN*

DET_IN
(IPU)

R3514

LOW_PWR

DLY

RST_OUT*

(OD)
DET_CHNGD*
(OD)

FROM SD CONN ->

SLG_ENET_RESET_R_L

8
7

ENET_CR_DETECT_L

OUT

37 82

NOSTUFF 1

R3512

OUT

18 23

OUT

37

5%
1/16W
MF-LF
402 2

-> TO PCH GPIO


-> TO ENET CHIP

ENET_RESET_L

*** Need to confirm with SW whether LATCH is required.


(SDCONN_STATE_RST_L will be required with LATCH)

THRM
PAD

GND

SDCONN_STATE_CHANGE

DET_OUT
2

5%
1/16W
MF-LF
402

XOR

37 23 19

DLY block is 20ms nominal


When ENET_LOW_PWR deasserts, RST_OUT# deasserts for >80ms, then asserts for 10ms
regradless of RST_IN# state. Otherwise RST_OUT# follows RST_IN#

SD CARD CONNECTOR
PLACE_NEAR=U3900.26:5.1MM
PLACE_NEAR=U3900.25:5.1MM
PLACE_NEAR=U3900.24:5.1MM
PLACE_NEAR=U3900.23:5.1MM
PLACE_NEAR=U3900.22:5.1MM
PLACE_NEAR=U3900.52:5.1MM
PLACE_NEAR=U3900.53:5.1MM
PLACE_NEAR=U3900.55:5.1MM
PLACE_NEAR=U3900.55:5.1MM

516-0225

J3500
SD-CARD-K19-K24

CRITICAL

F-RT-TH

L3579

L3500

FERR-10-OHM-300MA
82 37

IN

82 37

OUT

82 37

BI

82 37

BI

82 37

BI

82 37

BI

82 37

BI

82 37

BI

82 37

BI

82 37

BI

ENET_CR_CLK
ENET_CR_CMD
ENET_CR_DATA<0>
ENET_CR_DATA<1>
ENET_CR_DATA<2>
ENET_CR_DATA<3>
ENET_CR_DATA<4>
ENET_CR_DATA<5>
ENET_CR_DATA<6>
ENET_CR_DATA<7>

R3561
R3571
R3572
R3573
R3574
R3575
R3576
R3577
R3578

2
0402

47NH-1.3OHM
82

33
33

5%

1/16W

MF-LF

402

82

5%

1/16W

MF-LF

402

82

33

5%

1/16W

MF-LF

402

82

33
33

5%

1/16W

MF-LF

402

82

5%

1/16W

MF-LF

402

82

33
33

5%

1/16W

MF-LF

402

82

5%

1/16W

MF-LF

402

82

33

5%

1/16W

MF-LF

402

82

33

5%

1/16W

MF-LF

402

82

33

SDCONN_CLK_L
SDCONN_CMD
SDCONN_DATA<0>
SDCONN_DATA<1>
SDCONN_DATA<2>
SDCONN_DATA<3>
SDCONN_DATA<4>
SDCONN_DATA<5>
SDCONN_DATA<6>
SDCONN_DATA<7>
SDCONN_DETECT

6
82

SDCONN_CLK

0402

5
2
7
8
9
1
10
11
12
13
14
15

37

SDCONN_WP
PP3V3_S0_SW_SD_PWR

OUT

33

NOSTUFF
1

NOSTUFF

C3572

10PF

C3574

10PF

5%
50V
2 COG-CERM
0201

C3576

C3578

10PF

5%
50V
2 COG-CERM
0201

C3577
10PF

5%
50V
2 COG-CERM
0201

+/-0.25PF
50V
2 CERM
402

NOSTUFF
1

C3579
10PF

5%
50V
2 COG-CERM
0201

C3571
8.2PF

5%
50V
2 COG-CERM
0201

NOSTUFF

C3575

C3580
10PF

5%
50V
2 COG-CERM
0201

NOSTUFF
1

NOSTUFF

10PF

5%
50V
2 COG-CERM
0201

NOSTUFF

C3573

NOSTUFF

10PF

5%
50V
2 COG-CERM
0201

NOSTUFF

10PF

5%
50V
2 COG-CERM
0201

16

C3570

17

8.2PF

18

+/-0.25PF
2 50V
CERM
402

19
20

VSS
VSS
CLK
CMD
DAT0
DAT1
DAT2

(CARD INSERTED = OPEN)


CAESAR-IV CARD DETECT IS PROGRAMMABLE, BUT A SILICON BUG
MAKES THE ACTIVE-HIGH CASE UNUSABLE.

CD/DAT3
DAT4
DAT5
DAT6
DAT7
CARD_DETECT_SW
CARD_DETECT_GND
WRITE_PROTECT_SW
VDD
SHLD_PIN
SHLD_PIN
SHLD_PIN
SHLD_PIN

SYNC_MASTER=K91_MLB

SYNC_DATE=05/26/2010

PAGE TITLE

SD READER CONNECTOR
DRAWING NUMBER

NOSTUFF
1

C3581

Apple Inc.

10PF

5%
50V
2 COG-CERM
0201

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SIZE

REVISION

BRANCH

PAGE

35 OF 109
SHEET

33 OF 86

CRITICAL
81 8

IN

PCIE_T29_R2D_C_P<0>

C3600

81 8

IN

PCIE_T29_R2D_C_N<0>

C3601

OMIT_TABLE

10%

0.1UF
1

16V

X5R-CERM
0201

81
81

10%

0.1UF

16V

V19
T19

PCIE_T29_R2D_P<0>
PCIE_T29_R2D_N<0>

U3600

PER_0_P
PER_0_N

PET_0_P
PET_0_N

T29

V21
T21

81
81

C3640

PCIE_T29_D2R_C_P<0>
PCIE_T29_D2R_C_N<0>

FCBGA

X5R-CERM
0201

0.1UF

C3641

0.1UF

PCIE_T29_D2R_P<0>

10%

16V

PCIE_T29_D2R_N<0>

X5R-CERM
0201

10%

16V

PCIE_T29_D2R_P<1>

X5R-CERM
0201

OUT

8 81

OUT

8 81

OUT

8 81

OUT

8 81

OUT

8 81

OUT

8 81

OUT

8 81

OUT

8 81

10%

0.1UF

C3603

10%

0.1UF
PCIE_T29_R2D_C_P<2>

C3604

81 8

IN

PCIE_T29_R2D_C_N<2>

C3605

IN

PCIE_T29_R2D_C_P<3>

C3606

IN

PCIE_T29_R2D_C_N<3>

C3607

16V

X5R-CERM
0201

16V

X5R-CERM
0201

10%

81

10%

16V

C3615

TP_T29_MONOBSP

5%

C3616

TP_T29_MONOBSN

3.3K

5%
1/16W
MF-LF
402 2

R3691
3.3K

5%
1/16W
MF-LF
2 402

C3690 1

R36921

1UF

10%
6.3V 2
CERM
402
8
VCC

CRITICAL
OMIT_TABLE

U3690

(T29_SPI_CLK)

M95160
2KX8-1.8V

5%
1/16W
MF-LF
402 2

5%
1/16W
MF-LF
402 2

R3622
10K

5%

10%

16V

(T29_SPI_MISO)

10%

16V

S_L

W_L

T29ROM_HOLD_L

HOLD_L

0.1UF

C3643

0.1UF
PET_2_P
PET_2_N

PET_3_P
PET_3_N

K21
H21

81
81

C3644

PCIE_T29_D2R_C_P<2>
PCIE_T29_D2R_C_N<2>

0.1UF

C3645

F21
D21

81
81

C3646

PCIE_T29_D2R_C_P<3>
PCIE_T29_D2R_C_N<3>

0.1UF

C3647

MF

201

1/20W

MF

201

MONOBSP

M17

MONOBSN

X5R-CERM
0201

16V

PCIE_T29_D2R_N<1>

10%

16V

X5R-CERM
0201
X5R-CERM
0201

PCIE_T29_D2R_P<2>

10%

16V

PCIE_T29_D2R_N<2>

10%

16V

PCIE_T29_D2R_P<3>

X5R-CERM
0201
X5R-CERM
0201

10%

16V

PCIE_T29_D2R_N<3>

10%

16V

WAKE*

F1

T29_PCIE_WAKE_L

PERST*

E6

T29_RESET_L

RSENSE

E14

T29_RSENSE

R36512

1
5%

10K

K17

X5R-CERM
0201

10%
2

X5R-CERM
0201
X5R-CERM
0201

PP3V3_T29

IN

36

IN

8 19

1/20W

MF

7 16 19 26 34 35 36

201

R36551
1.0K

E16

T29_RBIAS

PCIE_RST_0*
PCIE_RST_1*
PCIE_RST_2*
PCIE_RST_3*

K1
J2
K3
J4

Not used in host mode.


TP_T29_PCIE_RESET0_L
TP_T29_PCIE_RESET1_L
TP_T29_PCIE_RESET2_L
TP_T29_PCIE_RESET3_L

TDI
TMS
TCK
TDO

T3
R4
R2
T1

JTAG_ISP_TDI
JTAG_T29_TMS
JTAG_ISP_TCK
JTAG_ISP_TDO

REFCLK_100_IN_P
REFCLK_100_IN_N

H17
G16

PCIE_CLK100M_T29_P
PCIE_CLK100M_T29_N

XTAL_25_IN
XTAL_25_OUT

P17
R16

TMU_CLK_OUT
TMU_CLK_IN

U2
E2

RBIAS

R3621
10K

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402
OUT

R3693
3.3K

83

83

VSS

C3642

PCIE_T29_D2R_C_P<1>
PCIE_T29_D2R_C_N<1>

0.1UF

83

T29ROM_WP_L

MONDC1

PER_3_P
PER_3_N

81

0.5%
1/16W
MF-LF
603 2

5%
1/16W
MF-LF
2 402

MLP

MONDC0

A20

1/20W

T29_MONOBSN

1
Q

T29_MONDC0

B21

T29_MONOBSP

36

(T29_SPI_MOSI)
(T29_SPI_CS_L)

10K

0.1UF

PP3V3_T29

R36231

3.3K

F19
D19

T29_MONDC1

0.1UF

DEBUG: For monitoring clock

R36901

PCIE_T29_R2D_P<3>
PCIE_T29_R2D_N<3>

81

0.1UF

0
NO STUFF

36 35 34 26 19 16 7

PER_2_P
PER_2_N

P21
M21

X5R-CERM
0201

R3611

TP_T29_MONDC1

K19
H19

PCIE_T29_R2D_P<2>
PCIE_T29_R2D_N<2>

PET_1_P
PET_1_N

NO STUFF

R3610

TP_T29_MONDC0

81

0.1UF
DEBUG: For monitoring current/voltage

81
81

10%

0.1UF
81 8

X5R-CERM
0201

0.1UF
81 8

16V

10%

0.1UF

X5R-CERM
0201

PER_1_P
PER_1_N

83

THM
PAD
9

85 51

T29_CLKREQ_ISOL_L
T29_GPIO<1>
T29_GPIO<2>
T29_RSVD

P3
N4
M3
L4

PCIE_CLKREQ_0*
PCIE_CLKREQ_1*
PCIE_CLKREQ_2*
PCIE_CLKREQ_3*

T29_SPI_MOSI
T29_SPI_MISO
T29_SPI_CS_L
T29_SPI_CLK

P1
M1
N2
L2

EE_DI
EE_DO
EE_CS*
EE_CLK

T29_THERMD_P

A2

THERM_DP

E4
P5
N6
M5
L6

TEST_EN
TEST_POINT_0
TEST_POINT_1
TEST_POINT_2
TEST_POINT_3

Use B1 GND ball for THERM_DN

T29_TEST_EN
TP_T29_TEST_POINT_0
TP_T29_TEST_POINT_1
TP_T29_TEST_POINT_2
T29_TEST_POINT_3

R3625
0

5%
1/16W
MF-LF
2 402

JTAG

IN

16V

P19
M19

PCIE_T29_R2D_P<1>
PCIE_T29_R2D_N<1>

POWER ON RESET

81 8

81

CLOCKS

PCIE_T29_R2D_C_N<1>

81

MISC

IN

X5R-CERM
0201

CLK REQUEST

81 8

16V

TRANSMIT

C3602

TEST PORT

PCIE_T29_R2D_C_P<1>

RECEIVE

IN

EEPROM

81 8

PCIE GEN2

(SYM 1 OF 2)

81

IN

16

IN

8 19 23

OUT

PP3V3_T29

R3698

8 19

IN

16 81

IN

16 81

7 16 19 26 34 35 36

10K

5%
1/16W
MF-LF
2 402

R3695

SYSCLK_CLK25M_T29_R
TP_T29_XTAL25OUT

R36961

T29_TMU_CLK_OUT
T29_TMU_CLK_IN
NO STUFF

1K

806

SYSCLK_CLK25M_T29

IN

26 81

1%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402 2

R36991
10K

0.1UF
83 8

IN

DP_T29SNK0_ML_C_P<1>

C3622

83 8

IN

DP_T29SNK0_ML_C_N<1>

C3623

0.1UF
1

0.1UF

DP_T29SNK0_ML_N<0>

83 34

34 83

10% 16V
X5R-CERM
0201
2

83 34

DP_T29SNK0_ML_P<1>

34 83

DP_T29SNK0_ML_N<1>

34 83

83 34

10% 16V
X5R-CERM
0201
2

83 34

10% 16V
X5R-CERM
0201

83 34
83 34

83 8

IN

DP_T29SNK0_ML_C_P<2>

C3624

0.1UF
83 8

IN

DP_T29SNK0_ML_C_N<2>

C3625

0.1UF
83 8

IN

DP_T29SNK0_ML_C_P<3>

C3626

0.1UF
83 8

IN

DP_T29SNK0_ML_C_N<3>

C3627

0.1UF

DP_T29SNK0_ML_P<2>

34 83

10% 16V
X5R-CERM
0201

17 8

DP_T29SNK0_ML_N<2>

34 83

10% 16V
X5R-CERM
0201

R36301
100K

DP_T29SNK0_ML_P<3>

DP_T29SNK0_ML_N<3>

83 34

5%
1/16W
MF-LF
402 2

34 83

10% 16V
X5R-CERM
0201
2

OUT

83 34

83 34

34 83

10% 16V
X5R-CERM
0201

83 34

83 34
83 17 8

BI

DP_T29SNK0_AUXCH_C_P

C3628

0.1UF
83 17 8

BI

DP_T29SNK0_AUXCH_C_N

C3629

0.1UF

DP_T29SNK0_AUXCH_P

34 83

DP_T29SNK0_AUXCH_N

34 83

83 34

10% 16V
X5R-CERM
0201
2

83 34

10% 16V
X5R-CERM
0201

83 34

83 34

SNK1 AC Coupling
2
DP_T29SNK1_ML_C_P<0> C3630 1
10% 16V

83 8

IN

83 8

IN

DP_T29SNK1_ML_C_N<0>

C3631

83 8

IN

DP_T29SNK1_ML_C_P<1>

C3632

IN

DP_T29SNK1_ML_C_N<1>

0.1UF
1

0.1UF
1

0.1UF
83 8

C3633

0.1UF

83 8

IN

DP_T29SNK1_ML_C_P<2>

C3634

0.1UF
83 8

IN

DP_T29SNK1_ML_C_N<2>

C3635

0.1UF
83 8

IN

DP_T29SNK1_ML_C_P<3>

C3636

0.1UF
83 8

IN

DP_T29SNK1_ML_C_N<3>

C3637

0.1UF
83 17 8

BI

DP_T29SNK1_AUXCH_C_P

C3638

BI

DP_T29SNK1_AUXCH_C_N

C3639

0.1UF
83 17 8

0.1UF

DP_T29SNK0_ML_P<2>
DP_T29SNK0_ML_N<2>

AA6
Y5

DPSNK0_ML_LANE_2P
DPSNK0_ML_LANE_2N

DP_T29SNK0_ML_P<1>
DP_T29SNK0_ML_N<1>

AA8
Y7

DPSNK0_ML_LANE_1P
DPSNK0_ML_LANE_1N

DP_T29SNK0_ML_P<0>
DP_T29SNK0_ML_N<0>

AA10
Y9

DPSNK0_ML_LANE_0P
DPSNK0_ML_LANE_0N

DP_T29SNK0_AUXCH_P
DP_T29SNK0_AUXCH_N

V1
W2

DPSNK0_AUX_CHP
DPSNK0_AUX_CHN

DP_T29SNK0_HPD

V5

DPSNK0_HOT_PLUG_DET

83 34

DP_T29SNK1_ML_P<0>

34 83

17 8

DP_T29SNK1_ML_N<0>

34 83

R36311

DP_T29SNK1_ML_P<1>

34 83

OUT

DP_T29SNK1_ML_P<3>
DP_T29SNK1_ML_N<3>

V9
U8

DPSNK1_ML_LANE_3P
DPSNK1_ML_LANE_3N

DP_T29SNK1_ML_P<2>
DP_T29SNK1_ML_N<2>

V11
U10

DPSNK1_ML_LANE_2P
DPSNK1_ML_LANE_2N

DP_T29SNK1_ML_P<1>
DP_T29SNK1_ML_N<1>

V13
U12

DPSNK1_ML_LANE_1P
DPSNK1_ML_LANE_1N

DP_T29SNK1_ML_P<0>
DP_T29SNK1_ML_N<0>

V15
U14

DPSNK1_ML_LANE_0P
DPSNK1_ML_LANE_0N

DP_T29SNK1_AUXCH_P
DP_T29SNK1_AUXCH_N

V7
U6

DPSNK1_AUX_CHP
DPSNK1_AUX_CHN

DP_T29SNK1_HPD

U4

DPSNK1_HOT_PLUG_DET

T29_R2D_C_P<0>
T29_R2D_C_N<0>

A6
A4

PRT0_T29T_P
PRT0_T29T_N

T29_D2R_P<0>
T29_D2R_N<0>

C4
C2

PRT0_T29R_P
PRT0_T29R_N

T29_LSEO<0>
T29_LSOE<0>

J6
K5

T29_0_LSEO
T29_0_LSOE

DPSRC0_ML_LANE_3P
DPSRC0_ML_LANE_3N

AA18
Y17

TP_DP_T29SRC_ML_CP<3>
TP_DP_T29SRC_ML_CN<3>

DPSRC0_ML_LANE_2P
DPSRC0_ML_LANE_2N

AA16
Y15

TP_DP_T29SRC_ML_CP<2>
TP_DP_T29SRC_ML_CN<2>

DPSRC0_ML_LANE_1P
DPSRC0_ML_LANE_1N

AA14
Y13

TP_DP_T29SRC_ML_CP<1>
TP_DP_T29SRC_ML_CN<1>

DPSRC0_ML_LANE_0P
DPSRC0_ML_LANE_0N

AA12
Y11

TP_DP_T29SRC_ML_CP<0>
TP_DP_T29SRC_ML_CN<0>

W16
U16

TP_DP_T29SRC_AUXCH_CP
TP_DP_T29SRC_AUXCH_CN

V3

DP_T29SRC_HPD

Y19
Y21
AA20

T29_DP_ATEST

DPSRC0_AUX_CHP
DPSRC0_AUX_CHN
DPSRC0_HOT_PLUG_DET
DP_ATEST
DP_RES_0
DP_RES_1

100pF SRF > 40MHz


BYPASS=U3600.Y19::2mm
BYPASS=U3600.Y19::5.08mm

C3685

T29_DP_RES

100PF
1

R3685
14.0K

1%
1/16W
MF-LF
402 2

R3632
100K

5%
50V
CERM 2
402

C3686
0.01UF

10%
2 16V
CERM
402

5%
1/16W
MF-LF
2 402

X5R-CERM
0201
2

10% 16V
X5R-CERM
0201
2

100K

10% 16V
X5R-CERM
0201

DP_T29SNK1_ML_N<1>

5%
1/16W
MF-LF
402 2

DP_T29SNK1_ML_P<2>
DP_T29SNK1_ML_N<2>
DP_T29SNK1_ML_P<3>
DP_T29SNK1_ML_N<3>

DP_T29SNK1_AUXCH_P
DP_T29SNK1_AUXCH_N

75

OUT

75

IN

83 75

OUT

83 75

OUT

83 75

IN
IN

75

OUT

75

IN

83 75 48

BI

83 75 48

OUT

A10
A8

PRT1_T29T_P
PRT1_T29T_N

T29_D2R_P<1>
T29_D2R_N<1>

C8
C6

PRT1_T29R_P
PRT1_T29R_N

T29_LSEO<1>
T29_LSOE<1>

G6
H5

T29_1_LSEO
T29_1_LSOE

I2C_T29_SDA
I2C_T29_SCL

F3
F5

T29_SDA
T29_SCL

T29_R2D_C_P<1>
T29_R2D_C_N<1>

PRT2_T29T_P
PRT2_T29T_N

A14
A12

NC_T29_R2D_CP<2>
NC_T29_R2D_CN<2>

PRT2_T29R_P
PRT2_T29R_N

C12
C10

NC_T29_D2RP<2>
NC_T29_D2RN<2>

G4
H3

PRT3_T29T_P
PRT3_T29T_N
PRT3_T29R_P
PRT3_T29R_N

T29_2_LSEO
T29_2_LSOE

OUT

OUT

IN

IN

T29_LSEO<2>
T29_LSOE<2>

OUT

IN

A18
A16

NC_T29_R2D_CP<3>
NC_T29_R2D_CN<3>

OUT

OUT

C16
C14

NC_T29_D2RP<3>
NC_T29_D2RN<3>

IN

IN

G2
H1

T29_LSEO<3>
T29_LSOE<3>

OUT

IN

34 83

SYNC_MASTER=T29

SYNC_DATE=10/12/2010

PAGE TITLE

T29_3_LSEO
T29_3_LSOE

34 83

10% 16V
X5R-CERM
0201

IN

83 75

10% 16V
X5R-CERM
0201
2

83 75

34 83

10% 16V
X5R-CERM
0201
2

IN

34 83

10% 16V
X5R-CERM
0201
2

83 75

34 83

10% 16V
X5R-CERM
0201
2

OUT

34 83

10% 16V
X5R-CERM
0201
2

OUT

83 75

34 83

10% 16V
X5R-CERM
0201
2

83 75

PORT2

C3621

83 34

PORT3

DP_T29SNK0_ML_C_N<0>

83 34

X5R-CERM
0201

SOURCE PORT 0

IN

83 34

5%
1/16W
MF-LF
402 2

34 83

SINK PORT 0

83 8

DP_T29SNK0_ML_P<0>

5%
1/16W
MF-LF
402 2

DISPLAY

0.1UF

DPSNK0_ML_LANE_3P
DPSNK0_ML_LANE_3N

PORTS

AA4
Y3

PORT0

IN

SNK0 AC Coupling
C3620
10% 16V

DP_T29SNK0_ML_C_P<0>

DP_T29SNK0_ML_P<3>
DP_T29SNK0_ML_N<3>

PORT1

83 8

83 34

SINK PORT 1

R36291

NOTE: All unused LSOE/EO pairs should be aliased


together. Other signals okay to float (TP/NC).

T29 Host (1 of 2)
DRAWING NUMBER

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

36 OF 109
SHEET

34 OF 86

PP3V3_T29
7 16 19 26
135 mA (Single-Port)
152 mA (Dual-Port)
EDP: 200 mA

CRITICAL
PP1V05_T29
2100 mA (Single Port)
2250 mA (Dual Port)
EDP: 3000 mA

OMIT_TABLE

C3700

10UF

20%
6.3V 2
X5R
603

C3701
10UF

20%
6.3V 2
X5R
603

C3705
1UF

10%
6.3V
2 CERM
402

C3710
1UF

10%
6.3V
2 CERM
402

C3706
1UF

10%
6.3V
2 CERM
402

C3711
1UF

10%
6.3V
2 CERM
402

C3707
1UF

10%
6.3V
2 CERM
402

C3712
1UF

10%
6.3V
2 CERM
402

C3708
1UF

10%
6.3V
2 CERM
402

C3713
1UF

10%
6.3V
2 CERM
402

C3709
1UF

10%
6.3V
2 CERM
402

C3714
1UF

10%
6.3V
2 CERM
402

R3720
1

5%
1/16W
MF-LF
402

PP1V05_T29_VDD_DP
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V

C3720
1UF

10%
2 6.3V
CERM
402

C3721
1UF

10%
2 6.3V
CERM
402

C3722

H9
H11
H13
K9
K11
K13
M9
M11
M13

VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0

U3600

VCC3P3
VCC3P3
VCC3P3

T29
FCBGA
(SYM 2 OF 2)

H15
K15
M15
E8
E10
E12
G14

VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE

R8
R10
R12

VDD1P0_DP_RX1
VDD1P0_DP_TXRX
VDD1P0_DP_TXRX

VCC3P3_T29
VCC3P3_T29

H7
M7
K7

C3744 1

C3743 1

C3745 1

10%
6.3V 2
CERM
402

10%
6.3V 2
CERM
402

10%
6.3V 2
CERM
402

1UF

G10
G12

1UF

1UF

C3746
10UF

20%
2 6.3V
X5R
603

P7
R6

C3747
10UF

20%
2 6.3V
X5R
603

PP3V3_T29_DP

VCC3P3_DP_TXRX
VCC3P3_DP_TXRX

P9
P11

VDD3P3DP_PLL

P13

C3753

1UF

10%
6.3V 2
CERM
402

C3752
1UF

C3751

10%
6.3V 2
CERM
402

1UF

10%
6.3V 2
CERM
402

C3750

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

5%
1/16W
MF-LF
402

1UF

0-ohms are placeholders for now, replace


with proper values after characterization.

10%
6.3V 2
CERM
402

R3760
PP3V3_T29_PLL

C3760

1UF

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

5%
1/16W
MF-LF
402

2.2UF

10%
2 6.3V
CERM
402

20%
6.3V 2
CERM
402-LF

L3730

L3770

FERR-120-OHM-1.5A
1
2
PP1V05_T29_VDD_DPPLL

FERR-120-OHM-1.5A
R14

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V

VCC3P3_DP_TXRXBIAS

P15

C3730
2.2UF

20%
2 6.3V
CERM
402-LF

VDD1P0_DP_PLL

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

B1
B3
B5
B7
B9
B11
B13
B15
B17
B19
C18
C20
D1
D3
D5
D7
D9
D11
D13
D15
D17
E18
E20
F7

VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE

VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP

T5
T7
T9
T11
T15
T17
V17
W4
W6
W8
W10
W12
W14
Y1
AA2

VSSDP_PLL

T13

VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE

F9
F11
F13
F15
F17
G18
G20
J16
J18
J20
L16
L18
L20
N16
N18
N20
R18
R20
U18
U20
W18
W20

PP3V3_T29_DPBIAS

C3770 1
G8
J8
J10
J12
J14
L8
L10
L12
L14
N8
N10
N12
N14

GND

0402

34 36

R3750
VCC3P3_DP_RX1
VCC3P3_DP_RX1

VCC

36 7

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

2
0402

2.2UF

20%
6.3V 2
CERM
402-LF

SYNC_MASTER=T29

SYNC_DATE=10/12/2010

PAGE TITLE

T29 Host (2 of 2)
DRAWING NUMBER

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

Current numbers from Vendor slide (<REDACTED> power measure 1.ppt), emailed 6/21/2010, TDP @ 90C.

BRANCH

PAGE

37 OF 109
SHEET

35 OF 86

Page Notes
Q3880

PPBUS_G3H
8-13V Input
Changes required
for 2S.
T29BST:Y

L3895

T29BST:Y

T29BST:Y

C3890

C3891

R3891

T29BST_SNS1
T29BST:Y

1%
1/16W
MF-LF
402 2

T29BST_PWREN_DIV_L

VIN

<R1> T29BST_EN_UVLO

R3881

25 EN/UVLO

330K

5%
1/16W
MF-LF
402 2

C3892

T29_A_HV_EN

5%
2 50V
CERM
402

T29BST:Y
1

R3892

C3893
0.01UF

1%
1/16W
MF-LF
2 402

10K
1%
1/16W
MF-LF
402 2

10%
2 50V
X7R
402

LT3957

SNS2

30 VC

T29BST_RT

33 RT

41.2K

NC

SGND

C3889
100PF

GND

5%
2 50V
CERM
402

GND_T29BST_SGND
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=0V

SGND shorted to
GND inside package,
no XW necessary.

MF-LF
402 2

<Ra>

T29BST_FBX
T29BST:Y
NO STUFF
1

31

C3894

10%
2 6.3V
CERM-X5R
402

DFLS230L

PLACE_NEAR=C3895.1:2 mm

T29BST_VSNS
T29BST:Y
NO STUFF R38951
137K
C3888
1%
100PF
1/16W

5%
2 50V
CERM
402

34 SYNC

0.33UF

1%
1/16W
MF-LF
402 2

D3895
POWERDI-123

XW3895
SM

32 SS

T29BST:Y

R3894

1
2
10
35
36

CRITICAL
T29BST:Y

T29BST_SNS2

QFN

FBX

UVLO(falling) = 1.22 * (R1 + R2) / R2


UVLO(rising) = UVLO(falling) + (2uA * R1)
UVLO = 4.55V (falling), 4.95 (rising)

Supervisor & CLKREQ# Isolation

T29BST_VC

T29BST_SS

<R2>

R3896
15.8K

1%
1/16W
MF-LF
402 2

<Rb>

PP15V_T29
T29BST:Y
1

T29BST:Y

C3895

4.7UF

C3897
4.7UF

10%
2 50V
X7R-CERM
1206

10%
2 50V
X7R-CERM
1206

T29BST:Y

T29BST:Y

C3896

C3898

4.7UF

4.7UF

10%
50V
X7R-CERM 2
1206

10%
50V
X7R-CERM 2
1206

7 8 76

Vout = 18.3V
Max Current = 0.8A
Freq = 300KHz
T29BST:Y
1

C3899
0.001UF

10%
50V
2 X7R
402

Vout = 1.6V * (1 + Ra / Rb)

PP3V3_S0
PP3V3_T29

T29BST:Y

7 16 19 26 34 35 36

6 D

0.1UF
PLT_RESET_L

SLG4AP016V

PP1V05_T29

TDFN

R38032

1 S
7 35 36

G 2

R3887

IN

T29_SW_RESET_L

3 MR*

16

OUT

T29_CLKREQ_L

6 EN
8 OUT

5%
1/20W
MF
2 201

T29BST:Y
3 D

330K
RESET* 4

IN 7

(OD)

Pull-up provided by SB page.

R3888

T29BST_SHDN_DIV
T29BST:Y

DLY

19

T29BST:Y
1

330K

Max Vgs: 10V

5%
1/16W
MF-LF
402 1

T29_RESET_L
DLY = 60 ms +/- 20%
T29_CLKREQ_ISOL_L
T29_CLKREQ_ISOL_L

SOT563

4 S
IN

Q3888
SSM6N37FEAPE

5%
1/20W
MF
2 201

34

OUT

MAKE_BASE=TRUE

THRM
PAD

34 36

G 5

SMC_DELAYED_PWRGD

34 36

IN

26 45

GND
5

SOT563

+ SENSE 2
- 0.7V

10K
Open-Drain GPIO

R3807

5%
1/16W
MF-LF
2 402

U3800

Q3888
SSM6N37FEAPE

100K

VDD

10%
25V 2
X5R
402

Platform (PCIe) Reset

CRITICAL

C3800 1
IN

SNS1

NC

R38931

T29BST_VC_RC
T29BST:Y
T29BST:Y
1

S 2

73.2K

33 30 26 18
40

U3890

5%
1/16W
MF-LF
402 2

SW

T29BST:Y

C3887
100PF

10%
10V 2
X5R
805

SOD-VESM-HF
1

NO STUFF

4.7UF

SSM3K15FV

71 62 61 57 54 52 51 50 49 48
23 22 20 19 18 17 16 12 8 7 6
46 42 41 40 37 36 33 29 27 26
85 77 75 74 73 72

CRITICAL
T29BST:Y

4
23
24
37

T29BST:Y
D 3

Q3805

R38891

T29BST:Y

IN

28 INTVCC

T29BST_INTVCC
T29BST_PWREN_L

76 75 8

T29BST_BOOST
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE
DIDT=TRUE

10%
25V
X5R 2
805

200K

T29BST:Y

PCMB063T-100MS

10UF

10%
25V
X5R 2
805

10%
25V
2 X5R
402

10UF

T29BST:Y

0.1UF

5%
1/16W
MF-LF
402 2

10UH-4A-68-MOHM
1

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
Voltage not specified here,
add property on another page.

CRITICAL
T29BST:Y

PPVIN_SW_T29BST

C3880

470K

BOM options provided by this page:


T29BST:Y - Stuffs 18V boost circuitry.

T29BST:Y

R38801

Signal aliases required by this page:


- =T29_CLKREQ_L
- =T29_RESET_L

BGA

77 64 63 50 49 40 8 7 6

SI8409DB

T29 15V Boost Regulator

-30V
+/-12V
-1.4V
46mOhm @ 4.5V Vgs
3.7A @ 70C

SI8409DB:
Vds(max):
Vgs(max):
Vgs(th):
Rds(on):
Id(max):

CRITICAL
T29BST:Y

Power aliases required by this page:


- =PPVIN_SW_T29BST
(8-13V Boost Input)
- =PP18V_T29_REG
(18V Boost Output)
- =PP3V3_T29_P3V3T29FET
(3.3V FET Input)
- =PP3V3_T29_FET
(3.3V FET Output)
- =PP3V3_S0_T29PWRCTL
- =PP1V05_T29_P1V05T29FET
(1.05V FET Input)
- =PP1V05_T29_FET
(1.05V FET Output)

8
9
20
21
38

12
13
14
15
16
17

27

3.3V T29 Switch

85 77 75
57 54 52 51
40 37 36 33
19 18 17 16 12 8 7
27 26 23 22
49 48 46 42
73 72 71 62

74
50
29
6
20
41
61

U3810

TPS22924

PP3V3_S0
A2
B2

CSP

VIN

VOUT

PP3V3_T29
7 16 19 26 34 35
Max Current = 1.7A (85C)

A1
B1

U3810 & U3815/U3816

CRITICAL
C2 ON

1UF

GND

Part

TPS22924C

10%
6.3V 2
CERM
402

C1

C3810 1

36

Type

Load Switch

R(on)

18 mOhm Typ
50 mOhm Max

Max Output: 2A per IC

1.05V T29 Switch


U3815

73 70 68
17 16 14 12 10 9 7 6
45 40 23 22 20

TPS22924

PP1V05_S0
A2
B2

C3815 1
10%
6.3V
CERM 2
402

VOUT

A1
B1

PP1V05_T29
7 35 36
Max Current = 3.4A (85C)

CRITICAL
C2 ON
GND
C1

1UF

CSP

VIN

SYNC_MASTER=T29

SYNC_DATE=10/12/2010

PAGE TITLE

T29 Power Support

U3816

TPS22924
A2
B2

CSP

VIN

VOUT

DRAWING NUMBER

A1
B1

Apple Inc.

T29_PWR_EN

C2 ON

NOTICE OF PROPRIETARY PROPERTY:

U3816.A2: PLACE_NEAR=U3815.B2:3 mm
GND

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

C1

IN

Pull-up provided by SB page.

CRITICAL
16

SIZE

REVISION

BRANCH

PAGE

38 OF 109
SHEET

36 OF 86

BCM57765 ENET SR pins are internal 1.2V switching regulator. See note for SR_DISABLE below.
If disabled: Okay to float VDD, VDDP & LX pin. VFB must always connect to =PP1V2_S3_ENET_PHY.
If enabled: VDD/VDDP connect to =PP3V3_S3_ENET_PHY (add bypassing), LX connects to inductor.
Special Star routing needed on these pins. Decoupling on Pg 37.

PP1V2_S3_ENET_INTREG

6 71

???mA (1000base-T, Caesar V)


73 71 37 26 7 6

PP3V3_ENET

281mA (1000base-T max power, Caesar IV)


37

VDD for Card Reader I/O


PP3V3R1V8_ENET_LR_OUT_REG

CRITICAL

ENET_SR_LX

71

ENET_SR_VFB

71

Internal 1.2V Switching Regulator pins.

L3900
FERR-600-OHM-0.5A

CRITICAL

L3920
PP3V3_S3_ENET_PHY_XTALVDDH

FERR-600-OHM-0.5A

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

SM

C3900

PP1V2_ENET_PHY_AVDDL

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.2V

0.1UF
10%
16V
X7R-CERM
402

CRITICAL

C3921

CRITICAL

C3926

R3910 1

81

81

C3956

(See note)

IN

16

AVDDL

35
61

GPHY_PLLVDDL 36

29
32

39
45
51

SR_LX 16

SR_VFB 13

7
20
56
62

58 VMAIN_PRSNT (IPD)

PCIE_ENET_D2R_C_N
PCIE_ENET_D2R_C_P

27 PCIE_TXD_N
28 PCIE_TXD_P

PCIE_ENET_R2D_P
PCIE_ENET_R2D_N

33 PCIE_RXD_P
34 PCIE_RXD_N

33 23 19

PCIE_CLK100M_ENET_P
PCIE_CLK100M_ENET_N

IN

ENET_RESET_L

11 PERST*

(IPD)

OUT

ENET_CLKREQ_L

12 CLKREQ*

(OD)

L3930

TRD0_P
TRD0_N
TRD1_P
TRD1_N
TRD2_P
TRD2_N
TRD3_P
TRD3_N

6 SMB_CLK
10 SMD_DATA

OUT

IN

SYSCLK_CLK25M_ENET

18 XTALI
19 XTALO

BI

81 26

BI

10%
6.3V
X5R-CERM
603

NC
BCM57765_RDAC

C3935
10UF
10%
6.3V
X5R
805

40
41
44
43
46
47
50
49

ENET_MDI_P<0>
ENET_MDI_N<0>
ENET_MDI_P<1>
ENET_MDI_N<1>
ENET_MDI_P<2>
ENET_MDI_N<2>
ENET_MDI_P<3>
ENET_MDI_N<3>

73 71 37 26 7 6

SCLK
SI/LINKLED*
SO
CS*

(OD)
(OD)

38 RDAC
69

BI

38 82

BI

38 82

BI

38 82

BI

38 82

BI

38 82

BI

38 82

BI

38 82

BI

38 82

PP3V3R1V8_ENET_LR_OUT_REG

37

37

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.8V
MAKE_BASE=TRUE
1

C3970

C3971

4.7UF

0.1UF

10%
6.3V
X5R-CERM
603

10%
16V
X7R-CERM
402

C3972
0.1UF

10%
16V
X7R-CERM
402

NC
ENET_MEDIA_SENSE

o1

ENET_CR_DETECT_L

OUT

26

IN

33

CR_CMD/CLE 26

ENET_CR_CMD

IN

33 82

ENET_CR_CLK

OUT

33 82

CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3
CR_DATA4
CR_DATA5
CR_DATA6
CR_DATA7

25
24
23
22
52
53
54
55

CE*/MS_INS*
CR_LED/ALE
CR_WP*/XD_WP*
XD_DETECT

59
60
57
68

ENET_CR_DATA<0>
ENET_CR_DATA<1>
ENET_CR_DATA<2>
ENET_CR_DATA<3>
ENET_CR_DATA<4>
ENET_CR_DATA<5>
ENET_CR_DATA<6>
ENET_CR_DATA<7>

R3965

BI

33 82

BI

33 82

BI

33 82

BI

33 82

BI

33 82

BI

33 82

BI

33 82

BI

33 82

NO_TEST=TRUE

NC_BCM57765_CE_L_MS_INS_L
ENET_CR_PWREN

OUT

33

R3980

BDM57765_SR_DISABLE

No MS (Memory Stick) Insert feature needed.


Control signal to light LED or control SD bus power.
SDCONN_WP
1K
1
2
5%

THRM_PAD

PHY Non-Volatile Memory

LR_OUT/GPIO1 is used as a 3.3V/1.8V internal LDO out for


the card reader on-chip I/O.
Connect only to U3900 pin 20.

CR_CLK/RY_BY* 21

(IPU)

(IPD)

2 SPD100LED*/SERIAL_DO
67 TRAFFICLED*/SERIAL_DI

37
37

(IPD)

TP_BCM57765_SPD100LED_L
TP_BCM57765_TRAFFICLED_L

IN

C3930
4.7UF

10%
16V
X7R-CERM
402

GPIO_0 5
GPIO_1/CR_BUS_PWR 8
RE*/GPIO_2 9

(IPx)
SD_DETECT/WE*
SD_DETECT can only be used active low due to errata.

66
64
65
63

37

2
SM

PP3V3R1V8_ENET_LR_OUT_REG

BCM57765

BCM57765_SCLK
BCM57765_MISO
BCM57765_MOSI
BCM57765_CS_L

BI

0.1UF

(OD)

4 LOW_PWR

BCM57765_SMB_CLK
BCM57765_SMB_DATA
37

NOTE: "IPx" == Programmable pull-up/down

3 WAKE*

ENET_LOW_PWR

IN

C3936

VDDC

31 PCIE_REFCLK_P
30 PCIE_REFCLK_N

BCM57765_WAKE_R_L

Must isolate from PCIe WAKE# if PHY


is powered-down in S3/S5. Standard
N-channel FET isolation suggested.
If PHY is always powered then alias
=ENET_WAKE_L to PCIE_WAKE_L.

IN

81 16

82 33

10%
16V
X5R
402

5%
1/16W
MF-LF
402

WAKE#

81 16

0.1uF
1

ENET_WAKE_L

VDDO

QFN-8X8

PCIE_ENET_R2D_C_N

AVDDH

(IPU)

OUT

10%
16V
X7R-CERM
402

BCM57765_VMAIN_PRSNT

81

R3943
26

0.1UF

(IPD)

IN

10%
16V
X5R
402

10%
16V
X5R
402
81 16

OMIT

81

CRITICAL

C3916

0.1uF
1

PCIE_ENET_R2D_C_P

U3900

0.1uF
IN

10%
6.3V
X5R-CERM
603

Current
Limiting
Resistor

C3951

PCIE_ENET_D2R_P

C3955
81 16

4.7UF

SR_VDD 14

10%
16V
X7R-CERM
402

C3915

0.1UF

SR_VDDP 15

C3931

(IPU)

OUT

5%
1/16W
MF-LF
402

PCIE_PLLVDDL

5%
1/16W
MF-LF
402

81 16

10%
6.3V
X5R-CERM
603

PP1V2_ENET_PHY_GPHYPLL

1K

10%
16V
X5R
402

4.7UF

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.2V

(IPU)

4.7K

10%
16V
X7R-CERM
402

R3941

5%
1/16W
MF-LF
402

0.1UF

R3942

0.1uF
OUT

C3911

10%
16V
X7R-CERM
402

XTALVDDH 17

PP3V3_S0

4.7K

0.1UF

BIASVDDH 37

R3940 1

C3910

42
48

5%
1/16W
MF-LF
402

C3950

C3925

FERR-600-OHM-0.5A

4.7K

PCIE_ENET_D2R_N

2
SM

PP3V3_S3_ENET_PHY_AVDDH

SM

81 16

0.1UF
10%
16V
X7R-CERM
402

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

L3925
1

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.2V

10%
16V
X7R-CERM
402

FERR-600-OHM-0.5A

CRITICAL

PP1V2_ENET_PHY_PCIEPLL

C3905

L3910

72 71 62 61 57 54 52 51 50 49
23 22 20 19 18 17 16 12 8 7 6
48 46 42 41 40 36 33 29 27 26
85 77 75 74 73

10%
6.3V
X5R-CERM
603

FERR-600-OHM-0.5A

0.1UF

C3920

PP3V3_S3_ENET_PHY_BIASVDDH
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

SM

2
SM

4.7UF

10%
16V
X7R-CERM
402

FERR-600-OHM-0.5A
2

0.1UF

L3905
1

1/16W

MF-LF

IN

33

402

ENET 1.2V SR IS ENABLED IF SR_DISABLE is PULLed-DOWN.

1.24K

ROM contains MAC address, PCIe config


info as well as code for Bonjour proxy.
Required for proper PHY operation.
(Required ROM size TBD)
PP3V3_ENET

1%
1/16W
MF-LF
2 402

ENET_CR Signals
BCM requests SD CR[0:7], CMD, CLK termination.

ENET supports both active-levels for WP.

C3990
0.1UF

VCC

U3990

AT45DB011D

10%
16V
X7R-CERM
402

SOIC-8S1
37

37

IN

BCM57765_SCLK

IN

BCM57765_CS_L

CS*

WP*

RESET*

SCK

OMIT

SI

BCM57765_MOSI

IN

37

SO

BCM57765_MISO

OUT

37

SYNC_MASTER=K91_MLB

ETHERNET PHY (CAESAR IV)

NOSTUFF
1

GND

R3990

DRAWING NUMBER

R3997

4.7K

4.7K

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SIZE

D
REVISION

NOTE: Pull-down on SO plus internal pull-ups on


other 3 SPI pins configures ENET for the
Atmel AT45DB011D (1Mbit) ROM. If a different
ROM is used then the straps must change.
NOTE: ENETM requires SI pull-down instead of SO.

SYNC_DATE=05/26/2010

PAGE TITLE

BRANCH

PAGE

39 OF 109
SHEET

37 OF 86

Page Notes
Power aliases required by this page:
(NONE)
Signal aliases required by this page:
(NONE)
BOM options provided by this page:
(NONE)

Place one of 0.1uf cap close to each centertap pin of transformer

ENETCONN_CTAP
1

C4000

0.1UF

C4002
0.1UF

10%
2 16V
X5R-CERM
0201

10%
2 16V
X5R-CERM
0201

C4004
0.1UF

10%
2 16V
X5R-CERM
0201

C4006
0.1UF

10%
2 16V
X5R-CERM
0201

CRITICAL
82 37

BI

ENET_MDI_P<0>

82 37

BI

ENET_MDI_N<0>

T4000
SM

12

85

11

85

10

ENET_CTAP0

ENET_CTAP1

ENETCONN_P<0>
ENETCONN_N<0>

CRITICAL

J4000
RJ45-M97-3

TX

F-RT-TH

TLA-6T213HF

10

82 37

BI

ENET_MDI_P<1>

85

ENETCONN_P<1>

82 37

BI

ENET_MDI_N<1>

85

ENETCONN_N<1>

1
2
3

RX

4
5

CRITICAL
82 37

82 37

BI

ENET_MDI_P<3>

BI

ENET_MDI_N<3>

T4001
SM

6
7

12

85

ENETCONN_P<3>

11

85

ENETCONN_N<3>

11
12

10

ENET_CTAP2

ENET_CTAP3

ENET_MDI_N<2>

85

ENETCONN_N<2>

ENET_MDI_P<2>

85

ENETCONN_P<2>

TX
514-0636

TLA-6T213HF

82 37

82 37

BI

BI

RX

Transformers should be
mirrored on opposite
sides of the board

R40001 R40011
75

5%
1/16W
MF-LF
402 2

75

5%
1/16W
MF-LF
402 2

R4002
75

5%
1/16W
MF-LF
2 402

R4003
75

CRITICAL

5%
1/16W
MF-LF
2 402

1000PF
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

PLACE_NEAR=T4001.1:5mm
4

2 10

GND

D4001
RCLAMP0524P
SLP2510P8

CRITICAL

10%
2KV
CERM
1206

PLACE_NEAR=T4000.5:5mm
6

2 10

D4000
RCLAMP0524P

GND

NC
IO
NC
IO
NC
IO
NC
IO

NC
IO
NC
IO
NC
IO
NC
IO

C4008
ENET_BOB_SMITH_CAP

SLP2510P8
3

NOSTUFF

CRITICAL

NOSTUFF

SYNC_MASTER=K91_MLB

SYNC_DATE=05/26/2010

PAGE TITLE

Ethernet Connector
DRAWING NUMBER

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

40 OF 109
SHEET

38 OF 86

PP3V3_FW_FWPHY

7 39 40 41

7 mA I/O

C4120

C4121

138 mA

C4122

C4123

C4124

1UF

1UF

1UF

1UF

1UF

10%
6.3V
CERM
402

10%
6.3V
CERM
402

10%
6.3V
CERM
402

10%
6.3V
CERM
402

10%
6.3V
CERM
402

L4130
120-OHM-0.3A-EMI

114 mA FireWire PHY

C4130

PP3V3_FW_FWPHY_VDDA

C4131

1UF

1UF

1UF

10%
6.3V
CERM
402

10%
6.3V
CERM
402

C4132
10%
6.3V
CERM
402

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

L4110
40 7

L4135

120-OHM-0.3A-EMI

PP1V0_FW_FWPHY

135 mA

120-OHM-0.3A-EMI

25 mA PCIe SerDes

PP1V0_FW_FWPHY_AVDD
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.0V

0402-LF

C4110

1UF
2

10%
6.3V
CERM
402

17 mA PCIe SerDes

C4111

C4135

1UF

1UF

10%
6.3V
CERM
402

10%
6.3V
CERM
402

110 mA Digital Core

C4100

PP3V3_FW_FWPHY_VP25

C4136

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

2
0402-LF

1UF
10%
6.3V
CERM
402

0 mA VReg PWR

C4101

C4102

C4103

C4104

C4105

C4106

C4141

1UF

1UF

1UF

1UF

1UF

1UF

1UF

0.1UF

10%
6.3V
CERM
402

10%
6.3V
CERM
402

10%
6.3V
CERM
402

10%
6.3V
CERM
402

10%
6.3V
CERM
402

10%
6.3V
CERM
402

10%
6.3V
CERM
402

20%
10V
CERM
402

2
0402-LF

C4140
1UF
10%
6.3V
CERM
402

K12

L9

L6

L10

L5

D8

D6

D5

A12

M2

L11

L3

J1

G12

F1

C12

C1

N11

N3

M12

L1

K2

H12

H2

E10

E2

C13

B12

B1

A1

PLACEMENT_NOTE=Place C4170 close to U1400


PLACEMENT_NOTE=Place C4171 close to U1400

C4170

0.1UF

VDD10

TP_FW643_NAND_TREE
FW643_REXT
FW_CLK24P576M_XO_R
FW_CLK24P576M_XI

191

1%
1/16W
MF-LF
402
6

5%
50V
CERM
402

6
6

R4162 1

470K
5%
1/16W
MF-LF
402

TP_FW643_SE
NC_FW643_SM
TP_FW643_MODE_A
TP_FW643_CE
NC_FW643_FW620_L
TP_FW643_JASI_EN
NC_FW643_AVREG
NC_FW643_VBUF
FW643_PU_RST_L

N13
J2
L13
D12
D1
A10
H13
K13

NC_FW643_OCR10_CTL

C4162

J12

NC

0.33UF
2

M13

J13

WAKE*
REGCLT
VAUX_DETECT
VAUX_DISABLE
(OD) CLKREQN

NAND_TREE
REXT
XO
XI NT-9

NT-OUT
NOTE: NT-xx notes show
NAND tree order.

SE (IPD)
SM (IPD)
MODE_A (IPD) NT-1
CE (IPD)
FW620* (IPU)
JASI_EN (IPD) NT-11
AVREG
VBUF
FW_RESET* (IPU) NT-8

SERIAL EEPROM
CONTROLLER

NT-7 SCL
NT-6 SDA

CHIP RESET

NT-5 PERST*

M1

16 81

IN

16 81

10%
2

0.1UF

X5R

16V

X5R

16V

X5R

IN

16 81

OUT

16 81

OUT

16 81

402

402

PCIE_FW_D2R_P
10%

16 81

402

PLACEMENT_NOTE=Place C4175 close to U4100


PLACEMENT_NOTE=Place C4176 close to U4100

6
6

PP3V3_FW_FWPHY

7 39 40 41

FW643_LDO

C2
D13
E1
D2
L2

R4165 1

FW643_WAKE_L
FW643_REGCTL
FW643_VAUX_DETECT
TP_FW643_VAUX_ENABLE
FW_CLKREQ_PHY_L

G2
G1

OUT

8 40

OUT

40

H1
F2

M11

FW643_SCL
NC_FW643_SDA

N4

FW_RESET_L

N12

R4166

10K

10K

5%
1/16W
MF-LF
402 2

5%
1/16W
MF-LF
2 402

R4164

TP_FW643_SCIFCLK
TP_FW643_SCIFDAIN
TP_FW643_SCIFDOUT
TP_FW643_SCIFMC

NOTE: FW_PME_L and FW_CLKREQ_L are


isolated for systems that use
1394B physical plug detect.
WITH PLUG DETECT:
- Gate CLKREQ# based on PHY power
- TP (or NC) PME#
WITHOUT PLUG DETECT:
- Alias both signals to drop = prefix

IN
1

40

R4163
10K

OCR_CTL_V10
OCR_CTL_V12 (Reserved)
VSS

10%
6.3V
CERM-X5R
402

N2

IN

16V

IN

402

MISCELLANEOUS

VREG_VSS
K6

1%
1/16W
MF-LF
402

R4170

FW643_TRST_L

K10

2.94K

G13

N1

NT-16 (IPD) SCIFCLK


NT-14 (IPD) SCIFDAIN
NT-17 SCIFDOUT
NT-15 (IPD)
SCIFMC

SCIF

L7

R4161 1

L8
F13

R0
TPCPS

K9

SM-3.2X2.5MM

K1

NT-19 (IPU) TRST*

N10

X5R

PCIE_FW_D2R_N

5%
1/16W
MF-LF
2 402

K8

24.576MHZ

B10

0.1UF

16V

PCIE_FW_R2D_C_P
10%

10K

K7

Y4150

B11

TPBIAS0
TPBIAS1
TPBIAS2

K5

NC
NC

A2

FW643_R0
FW643_TPCPS

2
1%
1/16W
MF-LF
402

C3

K4

412
1

22PF
1

BI

B7

M3

POWER MANAGEMENT
NT-12 (IPD)
NT-13

J10

FW_CLK24P576M_XO
CRITICAL

C4151

41 6

NC_FW0_TPBIAS
FW_P1_TPBIAS
NC_FW2_TPBIAS

C4175

PCIE_CLK100M_FW_N
PCIE_CLK100M_FW_P

NT-21 (IPU) TCK


NT-20 (IPU) TDI
(IPU) TDO
NT-18 (IPU) TMS

FIXME!!! - TYPO IN SYMBOL REGCTL

J9

2
5%
50V
CERM
402

BI

R4150

22PF
1

BI

A4

J5

C4150

41
41 40

B4

J4

1%
1/16W
MF-LF
402

BI

H10

200K

BI

41 6

H8

R4160 1

41 6

81

NC_FW643_TCK
NC_FW643_TDI
TP_FW643_TDO
NC_FW643_TMS

(OD)
NT-10 (IPD)

H7

PPVP_FW_CPS

A6

B2

41

BI

B6

81

N6

M4

1394 PHY

H6

82 41

BI

A9

H4

82 41

B9

G10

BI

G8

BI

G7

BI

82 41 6

A3

G6

41 6
82 41 6

B3

81

N5

0.1UF

PCIE_FW_R2D_N
PCIE_FW_R2D_P
PCIE_FW_D2R_C_N
PCIE_FW_D2R_C_P

N9

TEST CONTROLLER

G4

BI

A5

F10

41 6

B5

TPA0N
TPA0P
TPA1N
TPA1P
TPA2N
TPA2P
TPB0N
TPB0P
TPB1N
TPB1P
TPB2N
TPB2P

F8

BI

A8

F7

BI

82 41

B8

F6

82 41

NC_FW0_TPAN
NC_FW0_TPAP
FW_PORT1_TPA_N
FW_PORT1_TPA_P
NC_FW2_TPAN
NC_FW2_TPAP
NC_FW0_TPBN
NC_FW0_TPBP
FW_PORT1_TPB_N
FW_PORT1_TPB_P
NC_FW2_TPBN
NC_FW2_TPBP

81

N7

REFCLKN
REFCLKP

PCI EXPRESS PHY

F4

BI

N8

BGA

E9

BI

E13

E5

82 41
82 41 6

E12

PCIE_RXD0N
PCIE_RXD0P
PCIE_TXD0N
PCIE_TXD0P

10%

C4176

E4

IN

C4171

VREG_PWR

FW643E

DS0 (IPD) NT-2


DS1 (IPD) NT-3
DS2 (IPD) NT-4

D10

IN

41

F12

VP25

U4100

D9

41

FWPHY_DS0
FWPHY_DS1
FWPHY_DS2

A11

ATBUSB
ATBUSH
ATBUSN

D7

IN

A13

D4

41

B13

VP

5%
1/16W
MF-LF
402

L12

NC
NC
NC

VDDH

VDD33
OMIT
CRITICAL

PCIE_FW_R2D_C_N

SYNC_MASTER=T27_MLB

SYNC_DATE=07/20/2009

PAGE TITLE

FireWire LLC/PHY (FW643E)


DRAWING NUMBER

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

41 OF 109
SHEET

39 OF 86

Page Notes

Power aliases required


- =PPBUS_S5_FWPWRSW
- =PPBUS_FW_FET
- =PP3V3_FW_P3V3FWFET
- =PP3V3_FW_FET
- =PP3V3_FW_FWPHY
- =PP3V3_S0_FWLATEVG
- =PP3V3_S0_FWPWRCTL
- =PP1V05_S0_FWPWRCTL
- =PP1V05_FW_P1V0FWFET
- =PP1V0_FW_FET_R
- =PP1V0_FW_FWPHY

FireWire Port Power Switch

by this page:
(FW VP FET Input)
(FW VP FET Output)
(3.3V FET Input)
(3.3V FET Output)
(PHY 3.3V Power)

CRITICAL

Q4260

CRITICAL

FDC638P_G
77 64 63 50 49 36 8 7 6

Q4262 provides for fast-off of Q4260 in S0 (Late-VG detection)

PPBUS_FW_FWPWRSW_F
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V

5
4
2

(5KPD Bias Rail)


(1.0V FET Input)
(1.0V FET Output)
(PHY 1.0V)

R4262

R4260

10K

FWPORT_FASTOFF_L_DIV

Signal aliases required by this page:


- =FW_CLKREQ_L
- =FW_PME_L

(SYM-VER2)

SOT-363

PPVP_FW

7 41

CRS08-1.5A-30V

10%
25V 2
X5R
402

Q4262

R4263

10

BOM options provided by this page:


(NONE)

FWPORT_PWREN_L_DIV

BSS8402DW

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
MINISMDC110H24 VOLTAGE=12.6V

0.1UF

5%
1/16W
MF-LF
2 402

PPBUS_FW_FWPWRSW_D

C4260 1

300K

5%
1/16W
MF-LF
402 2

D4260
SM

1.1A-24V
6

PPBUS_G3H

CRITICAL

F4260

SM

5%
1/16W
MF-LF
402 2

FWPORT_FASTOFF_L
1

R4261

5%
1/16W
MF-LF
2 402

Q4262

PP3V3_S0

BSS8402DW

FWPORT_PWREN_L

SOT-363

D 3

Q4261

0.1UF

0.1UF

SOD-VESM-HF
1

C4290 1

NO STUFF

C4261 1

SSM3K15FV

41

PP3V3_S0

(SYM-VER1)

S 2

10%
25V 2
X5R
402

36 33 30 26 18

IN

SLG4AP016V

5%
1/16W
MF-LF
1 402

40 19

IN

23 16

OUT

7 39 40

2
+ SENSE
- 0.7V

10K
DLY

FW_RESET_R_L

RESET* 4

3 MR*

FW_PWR_EN
FW_CLKREQ_L

6 EN
8 OUT

FW_RESET_L
OUT
DLY = 60 ms +/- 20%
FW_CLKREQ_PHY_L
FW_CLKREQ_PHY_L

IN 7

(OD)

Pull-up provided by another page.

GND
5

PP1V05_S0

PP1V0_FW_FWPHY

TDFN

R4283

73
17 16 14 12 10 9 7 6
70 68 45 40 36 23 22 20

R4290

5%
1/16W
MF-LF
2 402

U4290

FWPORT_PWR_EN

IN

100K

VDD

10%
25V 2
X5R
402

PLT_RESET_L

CRITICAL

71 62 61 57 54 52 51 50 49 48
23 22 20 19 18 17 16 12 8 7 6
46 42 41 40 37 36 33 29 27 26
85 77 75 74 73 72

MAKE_BASE=TRUE

THRM
PAD

IN

39

39 40

39 40

71 62 61 57 54 52 51 50 49 48
23 22 20 19 18 17 16 12 8 7 6
46 42 41 40 37 36 33 29 27 26
85 77 75 74 73 72

Supervisor & CLKREQ# Isolation

470K

FireWire Port 5K Pull-Down Detect


R42751

All FireWire devices require 5K pull-down on TPB pair.


Host can detect as load on TPBIAS signal.
Current source only active when FW_PWR_EN is low.

1K

5%
1/16W
MF-LF
402 2

3.3V FW Switch

FW_PWR_EN_L

U4201

330K

Q4275
SOT-563

IN

FW_PWR_EN

2 G

CRITICAL

5%
1/16W
MF-LF
402 2

Q4270

BC847CDXV6TXG
SOT563

FWDET_MIRROR

CRITICAL

C4270

R42721

R42731

5%
1/16W
MF-LF
402 2
PLACE_NEAR=C4360.1:2 mm

5%
1/16W
MF-LF
402 2

10%
16V
X5R 2
402

1.0V FW Switch
23 22 20 17 16 14 12 10 9 7 6
73 70 68 45 40 36

TPS22924

PP1V05_S0
A2
B2

CSP

VIN

VOUT

TPS22924C

Type

Load Switch

R(on)

18 mOhm Typ
50 mOhm Max

1UF

10%
6.3V 2
CERM
402

C2 ON

R4202

GND

0.549

1%
1/16W
MF
2 402

R4276

FW_PLUG_DET_L
8 19
OUT
Pull-up provided on another page.
3 CRITICAL

100K

5%
1/16W
MF-LF
2 402

FW_WAKE
NO STUFF

6
D

FW643_WAKE_L

C4276

Q4276

DMB53D0UV
SOT-563

SYNC_MASTER=T27_MLB

0.1UF

10%
16V
X5R 2
402

SYNC_DATE=12/15/2009

PAGE TITLE

FireWire Port & PHY Power


DRAWING NUMBER

2 G

MAKE_BASE=TRUE

Apple Inc.

CRITICAL

Q4276
S

SIZE

D
REVISION

DMB53D0UV

NOTICE OF PROPRIETARY PROPERTY:

SOT-563

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

TEXT NOTE FOR 3.3V RAIL CURRENT CHANGED TO EDP NUMBER.

7 39 40

1) 5K Pull-down Detect when FW_PWR_EN is low.


2) FW643 WAKE# (PME#) when PHY is powered.

10K

FW643_WAKE_L

LSI FireWire PHY requires 1.0V.


To avoid an extra power supply,
1.05V is used with a series R
to reduce voltage.

Dual-purpose output:

5%
1/16W
MF-LF
402 2

IN

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V

PP1V0_FW_FWPHY

PP3V3_FW_FWPHY

R42771

40 39 8

Max Output: 2A

PP1V05_FW_FET
A1
B1

CRITICAL

C4202 1

FireWire PHY WAKE# Support

Part

U4202

12K

FW_P1_TPBIAS

41 40 39 7

41

U4201 & U4202

When PHY is powered, FW_5KPD_DET_L acts as legacy PME# signal.

PP3V3_FW_FWPHY 7 39 40
EDP = 0.14A (85C)

A1
B1

GND

10%
6.3V
CERM 2
402

SOT-563

0.1UF

BC847CDXV6TXG
SOT563

VOUT

C2 ON

1UF

DMB53D0UV
1

CSP

VIN

CRITICAL

C4201 1

Q4275

FWDET_EMIT

1K

IN

A2
B2

FW_P1_TPBIAS_R

41 39

CRITICAL

Q4270

TPS22924

PP3V3_S0

MAKE_BASE=TRUE

FW_5KPD_DET_RC

71 62 61 57 54 52 51 50 49 48
23 22 20 19 18 17 16 12 8 7 6
46 42 41 40 37 36 33 29 27 26
85 77 75 74 73 72

FW_5KPD_DET_L

56K

5%
1/16W
MF-LF
2 402

DMB53D0UV
40 19

R42711

R4270

C1

CRITICAL

C1

BRANCH

PAGE

42 OF 109
SHEET

40 OF 86

8
Page Notes

FW643 TPCPS Leakage Protection

Power aliases required by this page:


- =PPVP_FW_PORT1
- =PPVP_FW_PHY_CPS_FET (From Port)
- =PPVP_FW_PHY_CPS
(To PHY)
- =PP3V3_FW_FWPHY
- =PP3V3_S0_FWLATEVG

Unused FireWire Ports

FW643 has internal leakage path from TPCPS pin to VDD33.


FET blocks current to TPCPS until VDD33 is powered.

Configures PHY for:


- Port "1" Bilingual (1394B)

BSS8402DW

SOT-363

470K
5%
1/16W
MF-LF
402

PPVP_FW_CPS

R4311

IN

NC_FW0_TPBIAS

BI

NC_FW0_TPAP

BI

NC_FW0_TPAN

82 41 39 6

BI

NC_FW0_TPBP

82 41 39 6

BI

NC_FW0_TPBN

IN

NC_FW2_TPBIAS

BI

NC_FW2_TPAP

BI

NC_FW2_TPAN

BI

NC_FW2_TPBP

39 41

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=12.6V
MAKE_BASE=TRUE

From Port

41 39

82 41 39 6

82 41 39

PPVP_FW_CPS

PPVP_FW
4

41 40 7

Q4300

(SYM-VER2)

41 40 39 7

Signal aliases required by this page:


- =FW_PHY_DS0
- =FW_PHY_DS1
- =FW_PHY_DS2
NOTE: This page is expected to contain
the necessary aliases to map the
FireWire TPA/TPB pairs to their
appropriate connectors and/or to
properly terminate unused signals.

39 41

NC_FW0_TPBIAS
MAKE_BASE=TRUE

PP3V3_FW_FWPHY

39 41

R4382 1

NO_TEST=TRUE

NC_FW0_TPAP

6 39 41 82

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_FW0_TPAN

39 41 82

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_FW0_TPBP

10K

1%
1/16W
MF-LF
402 2

1%
1/16W
MF-LF
2 402

6 39 41 82

MAKE_BASE=TRUE

FWPHY_DS0

39
41

NO_TEST=TRUE

NC_FW0_TPBN

41 39

NO_TEST=TRUE

FWPHY_DS0

MAKE_BASE=TRUE

6 39 41 82

MAKE_BASE=TRUE

R4380

10K

FWPHY_DS1

FWPHY_DS1

MAKE_BASE=TRUE

To FW643
41 39 6

41 39 6

BOM options provided by this page:


(NONE)

FireWire PHY Config Straps

Disabled per LSI instructions


(All unused port signals TP/NC)

CPS_EN_L_DIV

1394b implementation based on Apple


FireWire Design Guide (FWDG 0.6, 5/14/03)

41 39 6

R4312

41 39 6

330K

41 39 6

5%
1/16W
MF-LF
402 2

BI

NC_FW2_TPBIAS
MAKE_BASE=TRUE

NC_FW2_TPAP

NO_TEST=TRUE

NC_FW2_TPAN
NO_TEST=TRUE

NC_FW2_TPBP

6 39 41

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_FW2_TPBN

39 41

OUT

39 41

OUT

39 41

R4381
10K

6 39 41

MAKE_BASE=TRUE

FWPHY_DS2

FWPHY_DS2
MAKE_BASE=TRUE

6 39 41

MAKE_BASE=TRUE

NC_FW2_TPBN

41
39

6 39 41

NO_TEST=TRUE

D
OUT

1%
1/16W
MF-LF
402

6 39 41

MAKE_BASE=TRUE

NO_TEST=TRUE

CPS_EN_L

D
41 40 39 7

Q4300

PP3V3_FW_FWPHY
2

BSS8402DW

SOT-363

(SYM-VER1)

C
CRITICAL

Cable Power

Termination
Place close to FireWire PHY

41 40 7

L4310

PPVP_FW

1
40 39

IN

Note: Trace PPVP_FW_PORT1 must handle up to 5A

FERR-250-OHM
2

FW_P1_TPBIAS

SM
1

PPVP_FW_PORT1_F
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=33V

C4314
0.01UF

C4360

0.33UF
2

10%
6.3V
CERM-X5R
402

10%
50V
X7R
402

(FW_PORT1_TPA_P)
(FW_PORT1_TPA_N)

"Snapback" & "Late VG" Protection


85 77 75 74
50 49 48 46 42 40 37
18 17 16 12 8 7
33 29 27 26 23 22 20
72 71 62 61 57 54 52

SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
1
1

R4361

56.2

82 41 39

PLACE_NEAR=U4350.1:2 mm

1%
1/16W
MF-LF
402 2

C4350

J4310

0.1UF
82 41
39

BI

FW_PORT1_TPA_P

BI

FW_PORT1_TPA_N

82 41
39

FW_PORT1_TPB_P
FW_PORT1_TPB_N

10%
16V
X5R
402

FW_PORT1_TPA_P
MAKE_BASE=TRUE

FW_PORT1_TPA_N

1394B-M97
F-RT-TH

VCC

U4350

TPD4S1394
3

TP_FWLATEVG_VCLMP

LLP

VCLMP

MAKE_BASE=TRUE

82 41 39

BI

FW_PORT1_TPB_P

82 41
39

82 41 39

BI

FW_PORT1_TPB_N

82 41
39

40

MAKE_BASE=TRUE
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
1
1

R4362

R4350

MAKE_BASE=TRUE

FWPWR_EN

GND

100K
5%
1/16W
MF-LF
402

56.2

1%
1/16W
MF-LF
2 402

FWPORT_PWR_EN

CRITICAL

R4363

56.2

OUT

1%
1/16W
MF-LF
402 2

D1+

D1-

D2+

D2-

NC

220pF
2

5%
25V
CERM
402

VP

OUTPUT

TPB+

VP

SC/NC

NC
VG

TPA-

VG

TPATPA<R>

TPA+

TPA(R)

INPUT

TPA+

10
PLACE_NEAR=J4310.5:2 mm

10%
50V
X7R
603-1

4.99K
1%
1/16W
MF-LF
402

TPB<R>

(FW_PORT1_TPA_P)

C4319

R4364

TPB-

TPB+

11

(FW_PORT1_TPB_P)
(FW_PORT1_TPB_N)

13
2

514S0605

R4319
1M

5%
1/16W
MF-LF
2 402

CHASSIS
GND

12

0.1uF

C4364

TPB(R)

(GND)
(FW_PORT1_TPA_N)
FW_PORT1_AREF

FW_PORT1_TPB_C

TPB-

(PINS 5/6 AND 7/8 ARE


SWAPPED FOR BETTER ROUTING)

(FW_PORT1_TPB_N)
(FW_PORT1_BREF)
(FW_PORT1_TPB_P)

82 41 39

BILINGUAL
CRITICAL

56.2

1%
1/16W
MF-LF
2 402

PORT 1

PP3V3_S0

R4360

73
36
6
19
51

AREF needs to be isolated from all


local grounds per 1394b spec
When a bilingual device is connected to a
beta-only device, there is no DC path
between them (to avoid ground offset issue)
BREF should be hard-connected to logic
ground for speed signaling and connection

SYNC_MASTER=T27_MLB

SYNC_DATE=07/28/2009

PAGE TITLE

FireWire Connector
DRAWING NUMBER

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

CANNOT SYNC THIS PAGE FROM T27, TPA AND TPB FOR U4350 IS SWAPPED

BRANCH

PAGE

43 OF 109
SHEET

41 OF 86

ODD Power Control

SATA ODD Connector


D

CRITICAL

Q4590
TPCP8102

PP5V_S3
6

23V1K-SM

7
62 61 57 54 52 51 50 49 48
23 22 20 19 18 17 16 12 8 7 6
46 42 41 40 37 36 33 29 27 26
85 77 75 74 73 72 71

PP3V3_S0

Q4596

100K

G
0.01UF
1

ODD_PWR_SS

5%
1/16W
MF-LF
402

F-ST-SM

C4596

R4595
ODD_PWR_EN_LS5V_L

10%
16V
CERM
402
71 62 61 57 54 52 51 50 49 48
23 22 20 19 18 17 16 12 8 7 6
46 42 41 40 37 36 33 29 27 26
85 77 75 74 73 72

SOT563

100K
5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402
45 6

IN

80 6

10

85 6

12

11

85 6

14

13

16

15

16V

10%

16V

10%

16V

10%

16V

CERM

IN

16 80

IN

16 80

OUT

16 80

402

SATA_ODD_R2D_C_P

0.01UF

SATA_ODD_R2D_P
SATA_ODD_R2D_N

SATA_ODD_R2D_C_N
10%

CERM

402

SATA_ODD_D2R_UF_N
SATA_ODD_D2R_UF_P

C4525

516S0616

SATA_ODD_D2R_P
402

SATA_ODD_D2R_N

0.01UF

CERM

CERM

OUT

16 80

402

SMC_ODD_DETECT

OUT

Indicates disc presence

SOT563

19

80 6

33K

SSM6N37FEAPE

C4526

0.01UF

ODD_PWR_EN

Q4596

C4521

PP3V3_S0

R4590 1

SSM6N37FEAPE

R4597 1

0.01UF

NOTE: 3.3V must be S0 if 5V is S3 or S5 to


ensure the drive is unpowered in S3/S5.

C4520

J4500

10%
10V
CERM
402

CRITICAL
54722-0164

0.068UF

100K
5%
1/16W
MF-LF
402

1
1

R4596

C4595

PP5V_SW_ODD
MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.4mm
VOLTAGE=5V

59 57 46 44 43 42 32 30 7 6
72 67 66 61 60

ODD_PWR_EN_L

71 57 42 26 22 20 16 7

PP1V5_S0
NO STUFF

R4515 1

R4513 1

4.7K

4.7K

5%
1/16W
MF-LF
402 2

5%
1/16W
MF-LF
402 2
SATARDRVR_I2C_ADDR0

42

SATARDRVR_I2C_ADDR1

42

PLACE_NEAR=J4501.9:3mm

CRITICAL

Internally PD ~150K
Write:0xB6 Read:0xB7

L4500
FERR-70-OHM-4A

PLACE_NEAR=L4500.1:2mm
6

PP5V_S0_HDD_FLT

MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.4mm
VOLTAGE=5V

PP5V_S0

PLACE_NEAR=L4500.2:2mm

0603
2

6 7 22 47 52 54 65 68 70 72 73
77

C4501

C4502

0.1UF

0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

71 57 42 26 22 20 16 7

C4514

0.1UF
71 57 42 26 22 20 16 7

PP1V5_S0

D2R values for 3dB de-emphasis

C4536

SYS_LED_ANODE

1 SYS_LED_ANODE_R

5%
1/16W
MF-LF
402

C4531

10
5%
1/16W
MF-LF
402

GND_VOID=TRUE

80 6

80 6

10

11

12

80 6

13

14

80 6

15

16

17

18

44 6

41.2

SATA_HDD_D2R_C_N
SATA_HDD_D2R_C_P

20

21

22

GND_VOID=TRUE

MF-LF 1%

2 402

GND_VOID=TRUE

SATA_HDD_R2D_N
SATA_HDD_R2D_P

41.2

0.1UF
10%
16V
X7R-CERM
402

2
10%

16V

CERM

C4515

SATA_HDD_D2R_RC_N

0.01UF

85 SATA_HDD_D2R_RDRVR_IN_N
10%

CERM

CRITICAL

15

B_INN
B_INP

12

REXT

20

14

EN

42

SATARDRVR_I2C_ADDR0

B_PRE0/I2C_ADDR0

A_PRE1/SCL_CTL

19

42

SATARDRVR_I2C_ADDR1

APRE0/I2C_ADDR1

B_PRE1/SDA_CTL

17

IN

SATA_HDD_R2D_RDRVR_OUT_P

SATARDRVR_I2C_EN_L

10

I2C_EN*

SATARDRVR_TEST

18

TEST

85 SATA_HDD_R2D_RDRVR_IN_N

5%

50V

80 SATA_HDD_R2D_RC_N

1/16W

SATA HDD / IR / SIL Connector

C4511

0.01UF

10%

16V

CERM

402

C4517

C4513

11

85 SATA_HDD_R2D_RDRVR_IN_P

C4512
0.01UF

SATA_HDD_D2R_P

OUT

16 80

SATA_HDD_D2R_N

OUT

16 80

SATA_HDD_R2D_C_N

IN

16 80

SATA_HDD_R2D_C_P

IN

16 80

SMBUS_PCH_CLK

IN

16 23 27 29 31 48 62 77 81

SMBUS_PCH_DATA

BI

10%

16V

CERM

402

10%

16V

CERM

402

10%

16V

CERM

402

10%

16V

CERM

402

SATARDRVR_REXT

16 23 27 29 31 48 62 77 81

R4512 1

R4511
0

GND_VOID=TRUE

MF-LF 1%

2 402

0.01UF

4.99K

GND THRM
PAD
CERM
402

0.01UF

402

41.2

85 SATA_HDD_D2R_RDRVR_OUT_N

A_OUTP
A_OUTN

85

R4534
1

16

6
2

A_INP
A_INN

C4518
0.01UF

SATARDRVR_EN

2
23 16

16V

SATA_HDD_R2D_RDRVR_OUT_N

15PF

GND_VOID=TRUE

GND_VOID=TRUE

85 SATA_HDD_D2R_RDRVR_OUT_P

B_OUTN
B_OUTP

GND_VOID=TRUE85

CERM
5%
402 50V

GND_VOID=TRUE

5%
1/16W
MF-LF
402
2

1%
1/16W
MF-LF
402

338S0907
SYNC_MASTER=K91_MLB

41.2

MF-LF 1%
402
80
1/16W

C4533
15PF
1
GND_VOID=TRUE

SATA_HDD_R2D_RC_P

C4510

SATA/IR/SIL Connectors

0.01UF

10%

16V

CERM

DRAWING NUMBER

402

Apple Inc.

GND_VOID=TRUE

SIZE

D
REVISION

CERM
5%
402 50V

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=05/15/2010

PAGE TITLE

R4533
GND_VOID=TRUE

(All 4 Cs)

PLACE_SIDE=TOP

PS8521A

402

C4534
1

0x96/0x97
0x98/0x99
0xB6/0xB7
0xB8/0xB9

20%
16V
CERM
402

U4510

85 SATA_HDD_D2R_RDRVR_IN_P

R2D values for 3dB de-emphasis

516S0687

TQFN

15PF
GND_VOID=TRUE

L
H
L
H

0.01UF

20%
10V
CERM
402

VDD

MF-LF 1%
2 402
80
1/16W

C4535

C4532

0.01UF

MIN_LINE_WIDTH=0.5mm
MIN_NECK_WIDTH=0.2mm
VOLTAGE=5V

C4516

80 SATA_HDD_D2R_RC_P

R4535

1
19

5%
1/16W
MF-LF
402 2

5%
50V

1/16W

IR_RX_OUT

4.7K
CERM
402

R4536

6 PP5V_S3_IR_R

10%
50V
CERM
402

R4532
2

0.001UF

NC

59 57 46 44 43 42 32 30 7 6 PP5V_S3
72 67 66 61 60

1
GND_VOID=TRUE

F-ST-SM

L
L
H
H

C4519

21

46

4.7

Address (W/R)

R4510 1

J4501
54722-0224

R4531

ADD0

NO STUFF

15PF

13

CRITICAL

ADDR1
PP1V5_S0

BRANCH

PAGE

45 OF 109
SHEET

42 OF 86

USB Port Power Switch


Left USB Port A
CRITICAL
CRITICAL

U4600

L4605

TPS2561DR
SON
60 59 57 46 44 42 32 30 7 6
72 67 66 61

PP5V_S3

24

OUT

24

OUT

10

USB_EXTA_OC_L
USB_EXTB_OC_L

6
4

73 67

DDRREG_EN

C4690

20%
6.3V
X5R
603

C4691

10UF
2

EN1
EN2
GND

C4696

0.1UF
2

FAULT1* ILIM
FAULT2*

IN_0
IN_1

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
VOLTAGE=5V

USB_ILIM

C4605

PP5V_S3_RTUSB_B_ILIM

PP5V_S3_RTUSB_A_F
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
VOLTAGE=5V

0603
1

CRITICAL

J4600

0.01uF

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
VOLTAGE=5V

20%
16V
CERM
402

USB

CRITICAL
2

F-RT-TH-M97-4
5

L4600
90-OHM-100MA
DLP11S

SYM_VER-1

R4600 1
23.2K
1%
1/16W
MF-LF
402

220UF-35MOHM

20%
10V
CERM
402

PP5V_S3_RTUSB_A_ILIM

THRM
PAD

CRITICAL

OUT1
OUT2

11

FERR-120-OHM-3A

20%
2 6.3V
POLY-TANT
CASE-B2-SM

C4695

10UF
2

20%
6.3V
X5R
603

C4617

85

USB2_EXTA_MUXED_N

USB2_EXTA_MUXED_P

10UF
2

20%
6.3V
X5R
603

USB2_LT1_N
85 USB2_LT1_P

85

85

3
4

6 VBUS

4
7

NC
IO
NC
IO

1 GND

Current limit per port (R4600): 2.18A min / 2.63A max

D4600
RCLAMP0502N
SLP1210N6

CRITICAL

CRITICAL

L4615

We can add protection to 5V if we want, but leaving NC for now

FERR-120-OHM-3A
1

C4615

Place L4605 and L4615 at connector pin

PP5V_S3_RTUSB_B_F

2
0603

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
VOLTAGE=5V

0.01uF
20%
16V
CERM
402

CRITICAL

USB/SMC Debug Mux

J4610
USB
F-RT-TH-M97-4
5

CRITICAL
90-OHM-100MA
DLP11S

SMC_DEBUG_YES
1

SMC_DEBUG_YES
1

0.1UF

47 46 45 6

IN
OUT

SMC_RX_L
SMC_TX_L

20%
10V
CERM
402

SYM_VER-1

R4650

80 24

BI

USB_EXTB_N

85

10K
9

C4650

47 46 45 6

L4610

PP3V42_G3H

VCC
2

2
5

M+

M-

U4650

Y+

Y-

85

5%
1/16W
MF-LF
402

BI

80 24

BI

USB_EXTA_P
USB_EXTA_N

D+

D-

2
3
4

80 24

BI

USB_EXTB_P

PI3USB102ZLE
80 24

USB_LT2_N
USB_LT2_P

6 VBUS

TQFN

CRITICAL

NC
IO
NC
IO

47 46 45 26 7 6
73 64 63 53 48

1 GND

SMC_DEBUG_YES
OE*
SEL

USB_DEBUGPRT_EN_L

10

IN

45

D4610

SEL=0 Choose SMC


SEL=1 Choose USB

GND

RCLAMP0502N
SLP1210N6

CRITICAL

SMC_DEBUG_NO

SYNC_MASTER=K91_MLB

R4651

Left USB Port B

0
1

2
5%
1/16W
MF-LF
402

DRAWING NUMBER

R4652
1

Apple Inc.

SIZE

D
REVISION

5%
1/16W
MF-LF
402

External USB Connectors

SMC_DEBUG_NO
0

SYNC_DATE=06/01/2010

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

46 OF 109
SHEET

43 OF 86

IR SUPPORT
D

PP5V_S3

60 59 57 46 43 42 32 30 7 6
72 67 66 61

C4801
0.1UF
10%
16V
X7R-CERM
402
14

VCC

U4800
CY7C63803-LQXC
QFN
80 24
80 24

BI
BI

DIFFERENTIAL_PAIR=USB2_IR
DIFFERENTIAL_PAIR=USB2_IR

12 P1.0/D+
USB_IR_P
13 P1.1/DUSB_IR_N
IR_VREF_FILTER 15 P1.2/VREG
16 P1.3/SSEL
17 P1.4/SCLK
1
C4803
18 P1.5/SMOSI
1UF
10%
19 P1.6/SMISO
10V
2

X5R
402-1

P0.0
P0.1
INT0/P0.2
INT1/P0.3
INT2/P0.4
TIO0/P0.5
TIO1/P0.6

7
6
5
4

R4800

3
2

100

IR_RX_OUT_RC

CRITICAL
OMIT

1
10

P/N 338S0633

IR_RX_OUT

IN

6 42

C4804
0.001UF

20
21

2
5%
1/16W
MF-LF
402

NC

10%
50V
CERM
402

22

23

VSS
11

THRML
PAD
25

24

SYNC_MASTER=K91_MLB

SYNC_DATE=05/15/2010

PAGE TITLE

Front Flex Support


DRAWING NUMBER

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

48 OF 109
SHEET

44 OF 86

C4903

0.1UF
20%
10V
CERM
402

4.7

73

IN

17

OUT

A12
B13

NC
36 26

OUT

23 17

OUT

46

C12
D10
D13

TP_SMC_P20

NC
NC
NC
46

BI

81 47 16 6

BI

81 47 16 6

BI

81 47 16 6

BI

81 47 16 6

IN

26

IN

81 26
47 16 6

IN
BI

B7
A8
D8
D7
D6

46

OUT
OUT

47 46 45 43 6

OUT

47 46 45 43 6

IN

84 51 48 32 6

BI

(OC)

OUT

26 17

OUT

43

OUT

29 27

BI

46 32

BI

63

BI

73 46

OUT

46 19

OUT

A1

42 6

SMC_TX_L
SMC_RX_L
SMBUS_SMC_0_S0_SCL

G2

(OC)

SMC_PA0_PU
SPI_DESCRIPTOR_OVERRIDE_L
PM_SYSRST_L
USB_DEBUGPRT_EN_L
MEM_EVENT_L
WIFI_EVENT_L
SYS_ONEWIRE
SMC_BATLOW_L

(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)

F3

46

IN

52

OUT

46

OUT

46

OUT

46

OUT

52

IN

46

IN

46

IN

46

IN

46

IN

49 46

IN

50 46

IN

49 46

IN

50 46

IN

50 46

IN

46
50 46

IN
IN

E4

(1 OF 3)
OMIT

P30
P31
P32
P33
P34
P35
P36
P37
P40
P41
P42
P43
P44
P45
P46
P47

P70
P71
P72
P73
P74
P75
P76
P77

N10

P80
P81
P82
P83
P84
P85
P86

A7

P90
P91
P92
P93
P94
P95
P96
P97

J4

K12
K11
J12
K13
J10

C4920

20%
10V
CERM
402

6 73

AVCC

VCC

VCL AVREF

R4909

U4900

N11
N12
M13
N13
L12

OUT

SMC_SCI_L

17 46 73

IN

46

OMIT

IN

6 46 63

IN

46 49

IN

46 49

IN

46

IN

46

IN

46 49

64 47 46

IN
46

IN

46 49

IN

46

IN

46 49

OUT

16 19

OUT

6 17 47

46

SMC_RESET_L

D3

RES*

SMC_XTAL
SMC_EXTAL

A3
A2

XTAL
EXTAL

(OC)

(OC)

SMC_ONOFF_L
SMC_BC_ACOK
SMC_PME_S4_WAKE_L
PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_S5_L
SMC_CLK32K
SMBUS_SMC_0_S0_SDA

A6
B5

G3
H2
G1
H4
G4
F4

IN

5%
1/16W
MF-LF
402

6 43 45 46 47

IN

6 43 45 46 47

BI
IN

E3

H1

ETRST*

H3

AVSS

L9

R4901
10K

5%
1/16W
MF-LF
402

SMC_MD1

IN

6 47

SMC_NMI

IN

47

SMC_TRST_L

IN

6 47

SMC_KBC_MDE

NO STUFF
1

R4902

R4998

10K

10K

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

R4903
0

5%
1/16W
MF-LF
2 402

PLACE_NEAR=U4900.L3:4mm

GND_SMC_AVSS

46 49 50

48 84

46 49 63 64

IN

46 53
6 17 30 73

IN

6 17 30 73

IN

17 73

IN

46

BI

NMI

46 53

IN

IN

D1

SM

6 17 47

OUT

MD1
MD2

10K

NC

XW4900
2

PM_CLKRUN_L
LPC_PWRDWN_L
SMC_TX_L
SMC_RX_L
SMBUS_SMC_MGMT_SCL

D5

E5

VSS

NC

C7

NC

(3 OF 3)

SMC_CPU_VSENSE
SMC_CPU_ISENSE
TP_SMC_ADC2
TP_SMC_ADC3
SMC_GFX_VSENSE
SMC_GFX_ISENSE
TP_SMC_P1V5S3_ISENSE
SMC_CPUVCCIO_ISENSE

L10

TLP-145V

SMC_PROCHOT_3_3_L
SMC_BIL_BUTTON_L

0.47UF
10%
6.3V
CERM-X5R
402

0.1UF

DF2117RVPLP20HV

SMC_ADAPTER_EN

M11

F1

C4907

NC

H12

C6

PP3V3_S5_SMC_AVCC
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.1 MM
VOLTAGE=3.3V

PLACE_NEAR=U4900.E1:3mm

SMC_VCL

PLACE_NEAR=U4900.M12:3mm
PLACE_NEAR=U4900.M12:3mm

NC
NC
NC

J11

B6

OUT

20%
10V
CERM
402

6 32 48 51 84

P50
P51
P52

N3
N1
M3
M2
N2
L1
K3
L2
B8

B9
A10
C10
B10
C11

SMC_DP_HPD_L
SMC_GFX_OVERTEMP_L

TLP-145V

P20
P21
P22
P23
P24
P25
P26
P27

C9

NC
IN

B2

C3

SMC_RUNTIME_SCI_L
SMC_ODD_DETECT
IN
SMC_S4_WAKESRC_EN
OUT
SMC_PB4
46

46

C2

C1

NC

76 73 46 8

B4

TP_SMC_GFX_THROTTLE_L
SMC_SYS_KBDLED

46
16

D4
A5

NC
NC
54

E10

C8

NC
BI

E12

D9

46
84 48

F11

A9

LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
LPC_FRAME_L
SMC_LRESET_L
LPC_CLK33M_SMC
LPC_SERIRQ

TP_SMC_P41
SMBUS_SMC_MGMT_SDA
TP_SMC_P43
46

D12

F13

SMC_BMON_MUX_SEL

NC
81 47 16 6

E11

E13

TP_SMC_P24

NC
50 46

D11
C13

PM_DSW_PWRGD
SMC_DELAYED_PWRGD
PM_PWRBTN_L

DF2117RVPLP20HV

SMC_PM_G2_EN

C4906
0.1UF

C5

IN

A13

L13

B11

73 26 23

F10

OUT

P60
P61
P62
P63
P64
P65
P66
P67

C4905

20%
10V
CERM
402

D2

46

U4900
P10
P11
P12
P13
P14
P15
P16
P17

0.1UF

5%
1/16W
MF-LF
402

B12

C4904

20%
10V
CERM
402

R4999
1

0.1UF

L11

E1

20%
6.3V
CERM
805

H10

22UF

TP_SMC_P10
TP_SMC_RSTGATE_L
ALL_SYS_PWRGD
S5_PWRGD

PP3V3_S5_AVREF_SMC
PP3V42_G3H

C4902

46

M1

46
64 63 53 48 47 46 43 26 7 6
73

B1

M12

L3

8
NOTE: Unused pins have "SMC_Pxx" names. Unused
pins designed as outputs can be left floating,
those designated as inputs require pull-ups.

A11

SMC_FAN_0_CTL
NC_SMC_FAN_1_CTL
NC_SMC_FAN_2_CTL
NC_SMC_FAN_3_CTL
SMC_FAN_0_TACH
NC_SMC_FAN_1_TACH
NC_SMC_FAN_2_TACH
NC_SMC_FAN_3_TACH

G11

TP_SMC_SA_ISENSE
SMC_DCIN_VSENSE
SMC_DCIN_ISENSE
SMC_PBUS_VSENSE
SMC_BMON_ISENSE
SMC_CPU_HI_ISENSE
TP_SMC_ADC14
SMC_OTHER_HI_ISENSE

M10

G13
F12
H13
G10
G12
H11
J13

N9
K10
L8
M9
N8
K9
L7

U4900
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7

DF2117RVPLP20HV
TLP-145V

(2 OF 3)
OMIT

PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7

PE0
PE1
PE2
PE3
PE4
PF0

K1

PF1
PF2
PF3
PF4
PF5
PF6
PF7

N5

PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7

M8

PH0
PH1
PH2

E2

PECI/PH3

A4

PEVREF/PH4
PEVSTP/PH5

B3

SMC_CASE_OPEN
SMC_TCK
SMC_TDI
SMC_TDO
SMC_TMS
G3_POWERON_L

J3
K2
J1
K4
K5

L5
M5

M4

K7
K6
N6
M7
L6

TP_SMC_PF5

C4

6 46 47

IN

6 46 47

IN

46

OUT

46

IN

46 53 63

IN

46 55

46

NC
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)

SMS_INT_L
SMBUS_SMC_BSA_SDA
SMBUS_SMC_BSA_SCL
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_A_S3_SCL
SMBUS_SMC_B_S0_SDA
SMBUS_SMC_B_S0_SCL

BI

6 48 63 64 84

BI

6 48 63 64 84

BI

NC

NOTE: SMS Interrupt can be active high or low, rename net accordingly.
If SMS interrupt is not used, pull up to SMC rail.

6 32 48 54 55 84

BI

6 32 48 54 55 84

BI

48 51 84

BI

SMC_PROCHOT
SMC_THRMTRIP

F2
J2

6 46 47

NC
NC

N7
K8

6 46 47

IN

NC
NC

N4
L4

46

IN

OUT

SMC_SYS_LED
SMC_LID

M6

IN

48 51 84

OUT

46

OUT

46

R4910
43

CPU_PECI_R
PVCCIO_S0_SMC_R
PM_PECI_PWRGD_R

CPU_PECI

10 19 78

5%
1/16W
MF-LF
402

R4911
C4910

0.1UF
20%
10V
CERM
402

PP1V05_S0

6 7 9 10 12 14 16 17 20 22 23
36 40 68 70 73

SYNC_MASTER=LINDA_K90I

5%
1/16W
MF-LF
402

SMC

R4912
1

SYNC_DATE=07/07/2010

PAGE TITLE

DRAWING NUMBER

PM_PECI_PWRGD

73

Apple Inc.

5%
1/16W
MF-LF
402

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SIZE

REVISION

BRANCH

PAGE

49 OF 109
SHEET

45 OF 86

SMC Reset "Button", Supervisor & AVREF Supply


53 48 47 46 45 43 26 7 6
73 64 63
53 48 47 46 45 43 26 7 6
73 64 63

46 45

46 45

V+

U5010
VREF-3.3V-VDET-3.0V

SMC_TPAD_RST_L
SMC_ONOFF_L

MR1*

(IPU)
SN0903048

MR2*

(IPU)

SMC_MANUAL_RST_L

DELAY

OMIT

NC_SMC_FAN_3_CTL

NC_SMC_FAN_3_CTL
NC_SMC_FAN_3_TACH

REFOUT
THRM

55 46 45

5%
1/16W
MF-LF
402

45 46
72 71 62 61 57 54 52 51 50 49
23 22 20 19 18 17 16 12 8 7 6
48 42 41 40 37 36 33 29 27 26
85 77 75 74 73

45 46

PP3V3_S0

45 46

45 46 49 63 64

SMS_INT_L

SMS_INT_L

49 46 45

SMC_CPU_VSENSE

49 46 45

SMC_CPU_ISENSE

100K

45 46 55

SMC_CPU_VSENSE

45 46 49

SMC_RESET_L

OUT

SMC_CPU_ISENSE

D
SMC_GFX_VSENSE

SMC_GFX_VSENSE

45

IN

45

IN

45

C5026

49 46 45

SMC_GFX_ISENSE

SMC_GFX_ISENSE

Q5060
DMB53D0UV

45 46 49

SOT-563
2

CPU_PROCHOT_BUF

45 46 49

confirm if K90 needs Isense on DDR rail


TP_SMC_P1V5S3_ISENSE
45 46
TO CPU

MAKE_BASE=TRUE

10%
16V
CERM
402

46 45

TP_SMC_P1V5S3_ISENSE

R5062

MAKE_BASE=TRUE
49 46 45

SMC_CPUVCCIO_ISENSE

SMC_CPUVCCIO_ISENSE

45 46 49

78 68 10

MAKE_BASE=TRUE
45 49 50

46 45

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=0V

MR1* and MR2* must both be low to cause manual reset.


Used on mobiles to support SMC reset via keyboard.

OUT

GND_SMC_AVSS

PLACEMENT_NOTE=Place R5001 on BOTTOM side

TO SMC

SMC_PROCHOT_3_3_L
45 46 49

45

0.01UF

20%
6.3V
X5R
603

5%
1/16W
MF-LF
402

MAKE_BASE=TRUE

45 47 64

49 46 45

C5025

SILK_PART=SMC_RST

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=3.3V

R5060
10K

5%
1/16W
MF-LF
402

MAKE_BASE=TRUE

R5061

MAKE_BASE=TRUE

10uF

10%
16V
CERM
402

SMC_BC_ACOK

SMC FSB to 3.3V Level Shifting

45 46

MAKE_BASE=TRUE

PAD

0.01UF

5%
1/10W
MF-LF
2 603

SMC_BC_ACOK

C5001

NC_SMC_FAN_3_TACH

R5000

PP3V3_S5_AVREF_SMC

GND

R5001

RESET*

NC_SMC_FAN_2_TACH

MAKE_BASE=TRUE

100K

VIN

64 63 49 46 45

DFN

IN

MAKE_BASE=TRUE

10%
6.3V
CERM-X5R
402

53 46 45

NC_SMC_FAN_2_CTL

MAKE_BASE=TRUE

0.47UF

NC_SMC_FAN_2_TACH

MAKE_BASE=TRUE

PP3V42_G3H
PP3V42_G3H

C5020

IN

NC_SMC_FAN_2_CTL

MAKE_BASE=TRUE

Desktops: 5V
Mobiles: 3.42V

53

46 45

46 45

TP_SMC_SA_ISENSE

TP_SMC_SA_ISENSE

BI

CPU_PROCHOT_L

3.3K

SMC_DCIN_VSENSE

SMC_DCIN_VSENSE

45 46 49

MAKE_BASE=TRUE
50 46 45

SMC_DCIN_ISENSE

49 46 45

SMC_PBUS_VSENSE

SMC_DCIN_ISENSE

SMC_PBUS_VSENSE

S
1

SOT-563
4

Q5059
SSM6N37FEAPE

45 46 50

SOT563

MAKE_BASE=TRUE

NOTE: Internal pull-ups are to VIN, not V+.

Q5060
DMB53D0UV

5%
1/16W
MF-LF
402

45 46

MAKE_BASE=TRUE
49 46 45

3
5

CPU_PROCHOT_L_R

45 46 49

MAKE_BASE=TRUE

SMC_BMON_ISENSE

50 46 45

SMC_BMON_ISENSE

50 46 45

SMC_CPU_HI_ISENSE

45 46 50

MAKE_BASE=TRUE

SMC_CPU_HI_ISENSE

SMC_PROCHOT

45 46 50

MAKE_BASE=TRUE

50 46 45

SMC_OTHER_HI_ISENSE

SMC_OTHER_HI_ISENSE

19
45 46 50

OUT

PM_THRMTRIP_L_R

MAKE_BASE=TRUE
46 45

TP_SMC_P10

46 45

TP_SMC_P20

TP_SMC_P10

45 46

MAKE_BASE=TRUE

Debug Power "Buttons"

TP_SMC_P20

Q5059
SSM6N37FEAPE

45 46

SOT563

MAKE_BASE=TRUE

SMC_ONOFF_L
OMIT

R5016
5%
1/10W
MF-LF
603

46 45

45 46 53

TP_SMC_P24

50 46 45

SMC_BMON_MUX_SEL

45 46 50

MAKE_BASE=TRUE

PLACE_SIDE=TOP
5%
1/10W
MF-LF
603

SILK_PART=PWR_BTN

45 46

SMC_BMON_MUX_SEL

R5015
0

TP_SMC_P24

MAKE_BASE=TRUE

OMIT

PLACE_SIDE=BOTTOM

OUT

46 45

TP_SMC_P41

TP_SMC_P41

SMC_THRMTRIP

45 46

MAKE_BASE=TRUE
46 45

TP_SMC_P43

46 45

TP_SMC_PF5

TP_SMC_P43

45 46

MAKE_BASE=TRUE

SILK_PART=PWR_BTN

TP_SMC_PF5

45 46

MAKE_BASE=TRUE

46 45

TP_SMC_RSTGATE_L

TP_SMC_RSTGATE_L

45 46

MAKE_BASE=TRUE
63 53 48 47 46 45 43 26 7 6
73 64

R5012
17

PLACE_NEAR=U1800.N14:5.1mm

PM_CLK32K_SUSCLK_R

IN

22
1

SMC_CLK32K

OUT

45

53 46 45

5%
1/16W
MF-LF
402

45
63 53 45
47 45 43 6
47 45 43 6

PP3V3_S4

7 46 53 54 72

47 45 6
47 45 6

SMC Crystal Circuit


45

SMC_XTAL

15pF
1

SMC_XTAL_R

100K

47 45 6

5%
1/16W
MF-LF
402

R5011
1M
5%
1/16W
MF-LF

63 45 6

PP3V3_S4

Y5010

5%
50V
CERM
402

20.00MHZ

OUT

45

Q5020
SSM3K15FV

D 3
2
53 46 45

5%
50V
CERM
402

75

IN

SMC_PME_S4_WAKE_L

IN

5%
1/16W
MF-LF
402

45
45 19

SMC_PME_S4_WAKE_L

PP3V42_G3H

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%
1/16W
NOSTUFF
5%
1/16W

MF-LF

402

MF-LF

402

MAKE_BASE=TRUE

SMC_PA0_PU
SMC_RUNTIME_SCI_L

R5091
R5094

100K
100K

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

5%

1/16W

MF-LF

402

MF-LF

402

NOSTUFF

OUT

45 46 53

S 2
73 45 17

DP_A_EXT_HPD

45

45

System (Sleep) LED Circuit


60 59 57 44
7 6
43 42 32 30
72 67 66 61

10K
10K
10K
10K
10K
470K
10K

100K

15pF

SMC_EXTAL

R5077
R5078
R5079
R5080
R5081
R5087
R5093

R5076

C5011

SMC_TMS
SMC_TDO
SMC_TDI
SMC_TCK
SMC_BIL_BUTTON_L
SMC_BC_ACOK
SMS_INT_L

10K
10K
100K
10K
100K

SOD-VESM-HF

5X3.2-SM

2 402

64 63 49 46 45
55 46 45

SMC_DP_HPD_L

CRITICAL

7 46 53 54 72

NO STUFF
1

45

47 45 6

5%
1/16W
MF-LF
2 402

C5010

R5010

R5020

R5070
R5072
R5071
R5073
R5074

SMC_ONOFF_L
G3_POWERON_L
SMC_LID
SMC_TX_L
SMC_RX_L

76 73 45 8

SMC_ADAPTER_EN
SMC_CASE_OPEN
SMC_PB4
SMC_S4_WAKESRC_EN

R5085
R5086
R5088
R5090

10K
10K
10K
100K

PP5V_S3

R5031 1

523

BATLOW# Isolation

R5030
20

1%
1/16W
MF-LF
402 2

1%
1/16W
MF-LF
2 402

PP3V3_WLAN

32 6

45 32

R5089

WIFI_EVENT_L

10K

2
5%

PP3V3_S5

PP3V3_SUS

30 26 24 23 22 20 19 17 8 7 6
85 76 74 73 72 66 56

1/16W

7 16 17 18 19 20 22 71 72 73

SYS_LED_ILIM

5%
1/20W
MF
201 2

1%
1/16W
MF-LF
402 2

Below connections are different from K91

Q5040

SSM3K15FV

46 45

NC_SMC_FAN_1_CTL

46 45

NC_SMC_FAN_1_TACH

46 45

TP_SMC_ADC2

R5041

46 45

TP_SMC_ADC3

46 45

TP_SMC_ADC14

46 45

TP_SMC_GFX_THROTTLE_L

SOD-VESM-HF

Q5030

73 45

IN

SMC_BATLOW_L
3

SYS_LED_L
Q2
G

OUT

SYNC_MASTER=LINDA_K90I

TP_SMC_ADC2

45 46

5%
1/16W
MF-LF
402

TP_SMC_ADC3

SMC_SYS_LED

DRAWING NUMBER

TP_SMC_ADC14

Apple Inc.

TP_SMC_GFX_THROTTLE_L

45 46

MAKE_BASE=TRUE

SMC_GFX_OVERTEMP_L

R5095

10K

42

SIZE

45 46

MAKE_BASE=TRUE

NOSTUFF

REVISION

63 53 48 47 46 45 43 26 7 6
73 64

OUT

SMC Support

MAKE_BASE=TRUE

PP3V42_G3H

NOTICE OF PROPRIETARY PROPERTY:

Internal 20K pull-up on PM_BATLOW_L in PCH.

SYS_LED_ANODE

SYNC_DATE=07/08/2010

PAGE TITLE

45 46

2
5%

IN

45 46

MAKE_BASE=TRUE

17

45

45

45 46

NC_SMC_FAN_1_TACH
MAKE_BASE=TRUE

SOT-563

PM_BATLOW_L

DMB54D0UV

Q1

NC_SMC_FAN_1_CTL
MAKE_BASE=TRUE

CRITICAL

1.47K

CRITICAL

R5032

100K

R50401

SYS_LED_L_VDIV

1/16W

MF-LF

402

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

50 OF 109
SHEET

46 OF 86

LPC+SPI Connector
CRITICAL
LPCPLUS

J5100
55909-0374
M-ST-SM
64 63 53 48 46 45 43 26 7 6
73
72 70 68 65 54 52 42 22 7 6
77 73

81 45 16 6
81 45 16 6

BI

47 6

IN
OUT

OUT

46 45 6

OUT

81 26 6

IN

46 45 6

OUT

45 6

SPI_ALT_MOSI
SPI_ALT_MISO
LPC_FRAME_L
PM_CLKRUN_L
SMC_TMS
LPCPLUS_RESET_L
SMC_TDO
SMC_TRST_L
SMC_MD1
SMC_TX_L

IN

45 17 6

45 6

LPC_AD<0>
LPC_AD<1>

BI

47 6
81 45 16 6

IN
OUT

46 45 43 6

31

PP3V42_G3H
PP5V_S0

IN

32

LPC_CLK33M_LPCPLUS
LPC_AD<2>
LPC_AD<3>

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

33

34

IN

SPIROM_USE_MLB
SPI_ALT_CLK
SPI_ALT_CS_L
LPC_SERIRQ
LPC_PWRDWN_L
SMC_TDI
SMC_TCK
SMC_RESET_L
SMC_NMI
SMC_RX_L
LPCPLUS_GPIO

6 26 81

BI

6 16 45 81

BI

6 16 45 81

OUT

6 19 56

IN

6 47

IN

6 47

BI

6 16 45

IN

6 17 45

OUT

6 45 46

OUT

6 45 46

OUT

45 46 64

OUT

45

OUT

6 43 45 46

OUT

6 19

516S0573

SPI Bus Series Termination


SPI_ALT_MISO
SPI_ALT_MOSI
SPI_ALT_CLK
SPI_ALT_CS_L
LPCPLUS
1

PLACE_NEAR=U1800.Y14:5mm
81 16

IN

B
81 16

IN

PLACE_NEAR=U1800.V4:5mm
81 16

IN

R5111

SPI_MOSI_R

15

OUT

81

47

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

81

SPI_MOSI

R5123
1

15
5%
1/16W
MF-LF
402

47
5%
1/16W
MF-LF
402

SPI_MLB_CS_L

OUT

56

OUT

56

SPI_MLB_MOSI

OUT

56

SPI_MLB_MISO

IN

56

PLACE_NEAR=R5125.2:5mm

B
SPI_MLB_CLK

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

47

SPI_CLK

R5122

SPI_MISO

6 47

PLACE_NEAR=J5100.14:5mm
PLACE_NEAR=J5100.12:5mm
PLACE_NEAR=J5100.9:5mm
PLACE_NEAR=J5100.11:5mm

47

SPI_CS0_L

R5121
81

R5125

47

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402
81 16

R5126

47

5%
1/16W
MF-LF
402

6 47

LPCPLUS
1

5%
1/16W
MF-LF
402

15
1

R5112

R5127

6 47

R5120

15
1

SPI_CLK_R

R5128

LPCPLUS
1

R5110

SPI_CS0_R_L
PLACE_NEAR=U1800.T3:5mm

LPCPLUS
1

6 47

PLACE_NEAR=R5126.2:5mm

PLACE_NEAR=R5127.2:5mm

PLACE_NEAR=U6100.2:5mm

SYNC_MASTER=K91_MLB

SYNC_DATE=05/15/2010

PAGE TITLE

LPC+SPI Debug Connector


DRAWING NUMBER

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

51 OF 109
SHEET

47 OF 86

PCH SMBus "0" Connections


62 61 57 54 52 51 50 49 48
23 22 20 19 18 17 16 12 8 7 6
46 42 41 40 37 36 33 29 27 26
85 77 75 74 73 72 71

62 61 57 54 52 51 50 49 48
23 22 20 19 18 17 16 12 8 7 6
46 42 41 40 37 36 33 29 27 26
85 77 75 74 73 72 71

R5200 1

1K
5%
1/16W
MF-LF
402

U1800
(MASTER)

R5201

81 77
29 27 23 16
62 48 42 31 MAKE_BASE=TRUE

SMBUS_PCH_CLK

81 77
29 27 23 16
62 48 42 31 MAKE_BASE=TRUE

SMBUS_PCH_DATA

SMBUS_PCH_DATA

64 63 53 47 46 45 43 26 7 6
73

R5250 1

U4900
(MASTER)

48
16
29
81
48
16
29
81

62 77
23 27
31 42

48 45 32 6
84 51

62 77
23 27
31 42

48 45 32 6
84 51

SMBUS_SMC_0_S0_SCL

R5251

4.7K

4.7K

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

PP3V42_G3H

R5280 1

SMC
U4900
(MASTER)

SMBUS_SMC_0_S0_SCL

63 48 45 6
84 64

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_0_S0_SDA

SMC "Battery A" SMBus Connections

PP3V3_S0

SMC

J2900
(Write: 0xA0 Read: 0xA1)

5%
1/16W
MF-LF
402

SMBUS_PCH_CLK

SO-DIMM "A"

1K

SMC "0" SMBus Connections

PP3V3_S0

Cougar-Point

63 48 45 6
84 64

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SCL

R5281

2.0K

2.0K

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

Battery Charger
ISL6258 - U7000
(Write: 0x12 Read: 0x13)

SMBUS_SMC_BSA_SCL

SMBUS_SMC_BSA_SCL

6 45 48
63 64 84

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SDA

SMBUS_SMC_BSA_SDA

SMBUS_SMC_BSA_SDA

6 45 48
63 64 84

MAKE_BASE=TRUE

T29 Temp
VRef DACs

SO-DIMM "B"
J3100
(Write: 0xA4 Read: 0xA5)

U3300
(Write: 0x98 Read: 0x99)
77 62 48
27 23 16
42 31 29
81
77 62 48
27 23 16
42 31 29
81

SMBUS_PCH_CLK

SMBUS_PCH_CLK

SMBUS_PCH_DATA

SMBUS_PCH_DATA

Margin Control

48
16
29
81
48
16
29
81

62 77
23 27
31 42

SMBUS_SMC_0_S0_SCL

84
6 32
45 48 51

SMBUS_SMC_0_S0_SDA

84
6 32
45 48 51

62 77
23 27
31 42

J6955
(See Table)

Battery
Battery Manager - (Write: 0x16 Read: 0x17)
Battery LED Driver - (Write: 0x36 Read: 0x37)
Battery Temp - (Write: 0x90 Read: 0x91)

U9701

SMBUS_PCH_CLK

SMBUS_PCH_DATA

SMBUS_PCH_DATA

62 77
23 27
31 42

SMBUS_SMC_0_S0_SCL

84
6 32
45 48 51

62 77
23 27
31 42

SMBUS_SMC_0_S0_SDA

84
6 32
45 48 51

48 33 32 31 30 26 24 18 8 7 6
73 72 55 54 50

PP3V3_S3

R5290

U6800
(Write: 0x72 Read: 0x73)
SMBUS_PCH_CLK

J2600 & J2650


(MASTER)
81 77
29 27 23 16
62 48 42 31

SMBUS_PCH_CLK

81 77
29 27 23 16
62 48 42 31

SMBUS_PCH_DATA

SMBUS_PCH_DATA

62 77
23 27
31 42

SMC "A" SMBus Connections

62 77
23 27
31 42

NOTE: SMC RMT bus remains powered and may be active in S3 state
48 33 32 31 30 26 24 18 8 7 6
73 72 55 54 50

SMBUS_PCH_DATA

84 48 45

SMBUS_SMC_MGMT_SCL

84 48
45

84 48 45

SMBUS_SMC_MGMT_SDA

84 48
45

R5291
4.7K

5%
1/16W
MF-LF
2 402

SMBUS_SMC_MGMT_SCL

R5270 1

62 77
23 27
31 42

48 45 32 6
84 55 54
48 45 32 6
84 55 54

1K

R5271

Trackpad

1K

5%
1/16W
MF-LF
402 2

U4900
(MASTER)
62 77
23 27
31 42

SMBUS_SMC_MGMT_SDA

MAKE_BASE=TRUE

PP3V3_S3

SMC

U4510
(Write: 0xB6 Read: 0xB7)
48
16
29
81
48
16
29
81

5%
1/16W
MF-LF
402 2

MAKE_BASE=TRUE

48
16
29
81
48
16
29
81

SATA_Redriver

SMBUS_PCH_CLK

4.7K

U4900
(MASTER)

Mikey
XDP Connectors

6 45 48
63 64 84

(Write: 0x90 Read: 0x91)

48
16
29
81
48
16
29
81

SMC

6 45 48
63 64 84

SMBUS_SMC_BSA_SDA

SMC "Management" SMBus Connections

(WRITE: 0x58 READ: 0x59)

SMBUS_PCH_CLK

SMBUS_SMC_BSA_SCL

X19

LED BACKLIGHT

U3301
(Write: 0x30 Read: 0x31)
77 62 48
27 23 16
42 31 29
81
77 62 48
27 23 16
42 31 29
81

Battery

EMC1414-A: U5520
(Write: 0x98 Read: 0x99)

5%
1/16W
MF-LF
2 402

J5800
(Write: 0x90 Read: 0x91)

SMBUS_SMC_A_S3_SCL

SMBUS_SMC_A_S3_SCL

SMBUS_SMC_A_S3_SCL

55 84
6 32
45 48 54

SMBUS_SMC_A_S3_SDA

55 84
6 32
45 48 54

MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SDA

SMBUS_SMC_A_S3_SDA
MAKE_BASE=TRUE

T29 I2C Connections

ALS
71 62 61 57 54 52 51 50 49 48
23 22 20 19 18 17 16 12 8 7 6
46 42 41 40 37 36 33 29 27 26
85 77 75 74 73 72

J3402
(Write: 0x72 Read: 0x73)
SMBUS_SMC_A_S3_SCL

55 84
6 32
45 48 54

SMBUS_SMC_A_S3_SDA

55 84
6 32
45 48 54

PP3V3_S0

R5230 1
4.7K

T29 IC

5%
1/16W
MF-LF
402

U3600
(MASTER)

Digital SMS

PCH "SMLink 0" Connections


62 61 57 54 52 51 50 49 48
23 22 20 19 18 17 16 12 8 7 6
46 42 41 40 37 36 33 29 27 26
85 77 75 74 73 72 71

R5210

U1800
(MASTER)
81 16

8.2K

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

83 75 48 34

55 84
6 32
45 48 54

SMBUS_SMC_A_S3_SDA

55 84
6 32
45 48 54

SML_PCH_0_DATA

SMC "B" SMBus Connections


62 61 57 54 52 51 50 49 48
23 22 20 19 18 17 16 12 8 7 6
46 42 41 40 37 36 33 29 27 26
85 77 75 74 73 72 71

PCH "SMLink 1" Connections

R5237

U1800
(Write: 0x88 Read: 0x89)
81 16

R5221

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

SML_PCH_1_CLK

84 51 48 45

R5260 1

84 51 48
45

SMBUS_SMC_B_S0_SCL

R5223
84 51 48 45

84 51 48
45

SMBUS_SMC_B_S0_SDA

5%
1/16W
MF-LF
402
1

R5261

4.7K

4.7K

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

DP Re-driver

I2C_DPSDRVA_SCL

MAKE_BASE=TRUE

U9310

75 48

1/20W
201

I2C_DPSDRVA_SDA

MAKE_BASE=TRUE

I2C_DPSDRVA_SCL

SML_PCH_1_DATA

SMBUS_SMC_B_S0_SCL

SMBUS_SMC_B_S0_SCL

SMBUS_SMC_B_S0_SDA

SMBUS_SMC_B_S0_SDA

MAKE_BASE=TRUE

45 48 51
84
45 48 51
84

SYNC_MASTER=K91_MLB

SYNC_DATE=05/26/2010

PAGE TITLE
2

48
75

CPU Temp

SMBus Connections

MAKE_BASE=TRUE
81 16

48
75

EMC1414-A: U5570
(Write: 0x98 Read: 0x99)

MAKE_BASE=TRUE

75 48

5%
1/20W
MF

2 201

I2C_DPSDRVA_SDA

U4900
(MASTER)

NO STUFF
8.2K

PP3V3_S0

SMC

PP3V3_S0

R5235

(Write: 0x94 Read: 0x95)

SDRVI2C:SB
0 1
2
5%
MF

8.2K

1/20W
201

DRAWING NUMBER

MAKE_BASE=TRUE

R5222

Apple Inc.

0
5%
1/16W
MF-LF
402

SMLink 1 is slave port to

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SIZE

D
REVISION

access PCH & CPU via PECI.

75
34
48
83
75
34
48
83

SDRVI2C:MCU

R52341

5%
MF

R5220 1

J9400
(Write: 0xA0 Read: 0xA1)

I2C_T29_SCL

SDRVI2C:MCU

MAKE_BASE=TRUE

NO STUFF

T29 Plug uC

I2C_T29_SDA

I2C_T29_SCL

R5236

Cougar-Point

5%
1/16W
MF-LF
402

I2C_T29_SDA

For Compliance Testing


SDRVI2C:SB
0 1
2

SML_PCH_0_CLK

62 61 57 54 52 51 50 49 48
23 22 20 19 18 17 16 12 8 7 6
46 42 41 40 37 36 33 29 27 26
85 77 75 74 73 72 71

5%
1/20W
MF
201 2

MAKE_BASE=TRUE
81 16

4.7K

MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SCL

R5211

8.2K

Microcontroller abstracts
actual CDR(s) in plug.

R5231

MAKE_BASE=TRUE

LIS331DLH: U5920
(Write: 0x30 Read: 0x31)

PP3V3_S0

Cougar-Point

83 75 48 34

BRANCH

PAGE

52 OF 109
SHEET

48 OF 86

PBUS Voltage Sense Enable & Filter


PLACE_NEAR=R7510.4:5MM

Q5300
NTUD3169CZ

85 69 68

73 72

IN

PM_SLP_S3_R_L

1%
1/16W
MF-LF
402 2

1
3

5
77 64 63 50 40 36 8 7 6

IN

85 69

1%
1/16W
MF-LF
402 2

2.21K2

CPUIMVP_ISNS_P 1

PLACE_NEAR=U4900.L8:5MM
1

5.49K

85 69

IN

20%
2 6.3V
X5R
402

GND_SMC_AVSS

2.21K2
0.1%
1/16W
MF
0402

EDP: 53A

IMVPISNS_ENG

715K

470PF

0.1%
1/16W
MF
2 402

10%
50V
CERM 2
402

NOSTUFF

0.1%
1/16W
MF
402

C5345
470PF
1

64 63 46 45

IN

SMC_BC_ACOK

Enables DC-In VSense


1
divider when AC present.

64 63 7

IN

CPUIMVP_ISNS1G_N

1%
1/16W
MF-LF
402 2

RTHEVENIN = 4573 Ohms


SMC_DCIN_VSENSE

R5311

PLACE_NEAR=U4900.N9:5MM

R53141

100K

1%
1/16W
MF-LF
402 2

PDCINVSENS_EN_L_DIV

SMC_GFX_ISENSE

1%
1/16W
MF-LF
402

Sense R is R7550
Sense R is 0.75mOhm C5354
470PF
10%
EDP: 26A
TDP: 21.5A
50V

R5354

NOSTUFF

715K

C5355

0.1%
1/16W
MF
2 402

CERM 2
402

470PF
1

715K 2
0.1%
1/16W
MF
402

20%
2 6.3V
X5R
402

GND_SMC_AVSS

R5355

SIGNAL_MODEL=EMPTY

45 46

C5351
0.22UF

IMVPISNS_ENG
IMVPISNS_ENG

OUT

PLACE_NEAR=U4900.M13:5MM
1

IMVPISNS_ENG

45 46 49 50

Gain:161.765x
Scale: 8.24A / V
Max VOut: 3.3V at 27.2A

10% SIGNAL_MODEL=EMPTY
50V
CERM
402

C5314
0.22UF

20%
2 6.3V
X5R
402

GND_SMC_AVSS

4.53K2

PLACE_NEAR=U4900.N9:5MM
1

5.49K

1%
1/16W
MF-LF
402 2

45 46

OUT

PLACE_NEAR=U4900.M13:5MM

R5351

CPUIMVP_ISUMG_IOUT

VTHRM

NOSTUFF

PLACE_NEAR=U4900.N9:5MM

V+

4.42K2 CPUIMVP_ISUMG_R_N

IMVPISNS_ENG

OPA2333
DFN

0.1%
1/16W
MF
0402

P-CHANNEL
1

CPUIMVP_ISUMG_R_P

27.4K

Scale: 16.48A / V
Max VOut: 3.3V at 54.4A

U5340
8

85

0.1%
1/16W
MF
0402

R53131

Gain:161.765x

SIGNAL_MODEL=EMPTY

IMVPISNS_ENG
CRITICAL

R5353
85 69

PPDCIN_G3H

4.42K2

IMVPISNS_ENG

Max VOut: 3.3V at 19.77V Input

DCIN_S5_VSENSE

IN

CPUIMVP_ISNS1G_P

100K

1%
1/16W
MF-LF
402 2

45 46 49 50

10% SIGNAL_MODEL=EMPTY
50V
CERM
402

R5352
85 69

R53121

GND_SMC_AVSS

GFX/IG VCore Load Side Current Sense / Filter

DCINVSENS_EN_L

C5341

20%
6.3V
2 X5R
402

IMVPISNS_ENG
6

45 46

0.22UF

715K 2
1

Q5310

R5345

NTUD3169CZ
SOT-963
N-CHANNEL

OUT

PLACE_NEAR=U4900.M11:5MM

IMVPISNS_ENG

R5344

(Effective Sense R is 0.375mOhm


due to averaging of the 2 cores)

SMC_CPU_ISENSE

1%
1/16W
MF-LF
402

TDP :36A

DC-In Voltage Sense Enable & Filter

CPUIMVP_ISUM_IOUT

IMVPISNS_ENG

NOSTUFF

C5344

4.53K2
1

V-

CPUIMVP_ISUM_R_N

Sense R is R7510 & R7520


Sense R is 0.75mOhm
45 46 49 50

V+
THRM

85

PLACE_NEAR=U4900.M11:5MM

R5341

DFN

IMVPISNS_ENG

OPA2333

8
3

CPUIMVP_ISNS_N 1

0.1%
1/16W
MF
0402

C5304

CPUIMVP_ISUM_R_P

R5343
85

4.42K2
CPUIMVP_ISNS2_N 1

0.22UF

1%
1/16W
MF-LF
402 2

PBUSVSENS_EN_L_DIV

4.42K2

R5349

45 46

OUT

PLACE_NEAR=U4900.L8:5MM

R53041

1%
1/16W
MF-LF
402 2

R5348

CPUIMVP_ISNS1_N 1

U5340
85

0.1%
1/16W
MF
0402

IMVPISNS_ENG

0.1%
1/16W
MF
IMVPISNS_ENG 0402

RTHEVENIN = 4573 Ohms


SMC_PBUS_VSENSE

100K

IN

PLACE_NEAR=U4900.L8:5MM

P-CHANNEL

R53011

R5342
85

0.1%
1/16W
MF
0402

20%
2 10V
CERM
402

IMVPISNS_ENG
CRITICAL

IMVPISNS_ENG

4.42K2
CPUIMVP_ISNS2_P 1

PLACE_NEAR=R7510.3:5MM

27.4K

C5340
0.1UF

R5347

Max VOut: 3.3V at 19.77V Input

R53031

PLACE_NEAR=U5340.5:3MM
1

IMVPISNS_ENG

PPBUS_G3H

85 69 68

PBUS_S0_VSENSE

IMVPISNS_ENG

PP3V3_S0

R5346

4.42K2
CPUIMVP_ISNS1_P 1

PLACE_NEAR=R7520.3:5MM

100K

85 77
52 51 50 49 48 46 42 41 40
20 19 18 17 16 12 8 7 6
37 36 33 29 27 26 23 22
75 74 73 72 71 62 61 57

0.1%
1/16W
MF
IMVPISNS_ENG 0402

R53021

Enables PBUS VSense


divider when in S0.

IN

PBUSVSENS_EN_L

CPU VCore Load Side Current Sense / Filter


IMVPISNS_ENG 54

SOT-963
N-CHANNEL

45 46 49 50

B
CPU 1.05V VCCIO Current Sense / Filter
CPU Vcore Voltage Sense / Filter
XW5320
SM
PPVCORE_S0_CPU

PP3V3_S0

CPUVSENSE_IN

4.53K2

SMC_CPU_VSENSE

1%
1/16W
MF-LF
402

PLACE_NEAR=R7510.2:5 MM

PLACE_NEAR=U4900.N10:5MM

OUT

45 46

PLACE_NEAR=U4900.N10:5MM
1

20%
2 6.3V
X5R
402

85 70

45 46 49 50

85 70

IN

IN

CPUVCCIOS0_CS_N
CPUVCCIOS0_CS_P

20%
2 10V
CERM
402

U5360

PLACE_NEAR=R7640.4:5MM

0.22UF

5 IN4

INA210
SC70

C5360
0.1uF

V+

C5320

GND_SMC_AVSS

69 14 12 9 7 6

71 62 61 57 54 52 51 50 49 48
23 22 20 19 18 17 16 12 8 7 6
46 42 41 40 37 36 33 29 27 26
85 77 75 74 73 72

R5320

OUT 6

CRITICAL
IN+ (200V/V) REF

PLACE_NEAR=U4900.L12:5MM

R5361

CPUVCCIO_IOUT

1%
1/16W
MF-LF
402

EDP: 17.5A

Gain: 200x

TDP :13.1A

GFX/IG Vcore Voltage Sense / Filter

XW5330
SM
69 15 12 9 7 6

PPVCORE_S0_AXG

SMC_CPUVCCIO_ISENSE

OUT

45 46

PLACE_NEAR=U4900.L12:5MM
1

C5361
0.22UF

20%
2 6.3V
X5R
402

GND

Sense R is R7640, 1mOhm

4.53K2

GND_SMC_AVSS

45 46 49 50

Scale: 5A / V
Max VOut: 3.3V at 16.5A

R5330
GFXVSENSE_IN

PLACE_NEAR=R7550.2:5 MM

4.53K2

SMC_GFX_VSENSE

1%
1/16W
MF-LF
402

PLACE_NEAR=U4900.N12:5MM

OUT

45 46

SYNC_MASTER=LINDA_K90I

PLACE_NEAR=U4900.N12:5MM
1

SYNC_DATE=10/22/2010

PAGE TITLE

C5330

Voltage & Load Side Current Sensing

0.22UF

20%
2 6.3V
X5R
402

DRAWING NUMBER

Apple Inc.

GND_SMC_AVSS

45 46 49 50

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

NOTICE OF PROPRIETARY PROPERTY:

SIZE

REVISION

BRANCH

PAGE

53 OF 109
SHEET

49 OF 86

COMPUTING High Side Current Sense / Filter

PP3V3_S0

71 62 61 57 54 52 51 50 49 48
23 22 20 19 18 17 16 12 8 7 6
46 42 41 40 37 36 33 29 27 26
85 77 75 74 73 72

2
69 68 67 65 7
70

OUT

V+

PPBUS_S5_HS_COMPUTING_ISNS

CRITICAL

85

ISNS_HS_COMPUTING_P

4.53K

66 7

SMC_CPU_HI_ISENSE

OUT
PLACE_NEAR=U4900.N8:5MM

1%
1/16W
MF-LF
402

Gain: 50x

OUT

R5410 1

45 46

3 ISNS_HS_OTHER_N

0.01

0.5%
1W
MF
0612-3

C5403
0.22UF
20%
6.3V

85

2 X5R
402

77 64 63 50 49 40 36 8 7 6

IN

EDP: 15.5A

TDP :11.1A

GND_SMC_AVSS

5 IN4 IN+

PLACE_NEAR=U4900.L7:5MM

R5413

INA213

OUT 6
CRITICAL
(50V/V) REF 1

HS_OTHER_IOUT

SC70

4.53K

1%
1/16W
MF-LF
402

SMC_OTHER_HI_ISENSE

OUT
PLACE_NEAR=U4900.L7:5MM

45 46

C5413
0.22UF
20%
6.3V
X5R

Scale: 2A / V
Max VOut: 3.3V at 6.6A

GND

EDP: 10.0A

Gain: 50x

2 4 ISNS_HS_OTHER_P

PPBUS_G3H

45 46 49 50

20%
10V
CERM
402

U5410

CRITICAL

Scale: 4A / V
Max VOut: 3.3V at 13.2A

GND

PPBUS_G3H

HS_COMPUTING_IOUT

V+

PPBUS_S5_HS_OTHER_ISNS

IN

4 IN+

C5411
0.1UF

R5403

49 40 36 8 7 6
77 64 63 50

10%
16V
X5R-CERM
0201

PLACE_NEAR=U4900.N8:5MM

OUT 6
CRITICAL
(50V/V) REF 1

0.005

R5400 1

0.1UF

INA213
SC70

PP3V3_S0

C5401

U5400

0612 2 4
85 ISNS_HS_COMPUTING_N
MF
5 IN1W
1%

OTHER High Side Current Sense / Filter

71 62 61 57 54 52 51 50 49 48
23 22 20 19 18 17 16 12 8 7 6
46 42 41 40 37 36 33 29 27 26
85 77 75 74 73 72

2 402

TDP :5.2A

GND_SMC_AVSS

45 46 49 50

DC-IN (AMON) Current Sense Filter


CHARGER BMON High Side (BATTERY DISCHAEGE) Current Sense, MUX & Filter
48 33 32 31 30 26 24 18 8 7 6
73 72 55 54

BMON:ENG
1

Sense R is R7050, 10mOhm

V+

85 64

IN

CHGR_CSO_R_P

85 64

IN

CHGR_CSO_R_N

U5420

PLACE_NEAR=R7050.3:5MM

C5420
0.1uF

CRITICAL

Charger/Load side

20%
10V
CERM
402

C5421

BMON:ENG

ININ+

SC70

OUT

BMON_INA_OUT

SC70

B1

GND

SEL 6

SMC_BMON_MUX_SEL

VCC 5

NOTE: Monitoring current from


battery to PBUS (battery discharge)
across R7050

B0

BMON:PROD

R5423
100K

CHGR_BMON

SMC_BMON_ISENSE
PLACE_NEAR=U4900.M9:5MM

1%
1/16W
MF-LF
402

BMON:ENG

R5420
From charger

BMON_AMUX_OUT

VER 1

Scale: 2A / V
Max VOut: 3.3V at 6.6A

45.3K

PLACE_NEAR=U5421.1:5MM 5%

45 46

C5431
0.22UF
20%
6.3V
X5R
402
45 46 49 50

Scale: 2.5A / V
Max VOut: 3.3V at 8.25A

R5422

OUT

PLACE_NEAR=U4900.K10:5MM
1

DC-In AMON
ISL6259 Gain: 20x

45 46

IN

PLACE_NEAR=U4900.M9:5MM

INA Solution
Gain: 50x

GND

SMC_DCIN_ISENSE

2
1%
1/16W
MF-LF
402

GND_SMC_AVSS

NC7SB3157P6XG
1

REF

Battery side

(50V/V)

4.53K
1

U5421

INA213
6

CHGR_AMON

0.1uF
20%
10V
CERM
402

IN

Sense R is R7020, 20mOhm

BMON:ENG

BMON:ENG

IN

R5431
64

PP3V3_S3

64

PLACE_NEAR=U4900.K10:5MM

OUT

45 46

C5422
0.022UF
10%
16V

CERM-X5R
2 402

5%
1/16W
MF-LF
402

GND_SMC_AVSS

45 46 49 50

1/16W
MF-LF
402

For engineering, stuff BMON_ENG


For production, stuff BMON_PROD

INA (Engineering) Solution


Gain: 50x

Charger BMON (Production) Solution


ISL6259 Gain: 36x

Scale: 2A / V
Max VOut: 3.3V at 6.6A

Scale: 2.78A / V
Max VOut: 3.3V at 9.167A

SYNC_MASTER=LINDA_K90I

SYNC_DATE=10/22/2010

PAGE TITLE

High Side Current Sensing


DRAWING NUMBER

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

54 OF 109
SHEET

50 OF 86

CPU Proximity/CPU Die/5V-3.3V Proximity

R5510
71 62 61 57 54 52 51 50 49 48
23 22 20 19 18 17 16 12 8 7 6
46 42 41 40 37 36 33 29 27 26
85 77 75 74 73 72

PP3V3_S0

47

PP3V3_S0_CPUTHMSNS_R

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V

5%
1/16W
MF-LF
402

C5510
0.1uF

1
VDD

U5510

20%
10V
CERM
402

R5511 1

EMC1413

5%
1/16W
MF-LF
402

DFN
85 9

SIGNAL_MODEL=EMPTY

C5511

Detect CPU Die Temperature

85 9

2 DP1

CPU_THERMD_P

BI

PLACE_NEAR=U5510.2:5mm
PLACE_NEAR=U5510.3:5mm

3 DN1

0.0022uF
10%
50V
CERM
402

85

R5512
10K

5%
1/16W
MF-LF
402

7 CPUTHMSNS_THM_L

ALERT*

8 CPUTHMSNS_ALERT_L

4 DP2/DN3

SMDATA

SMBUS_SMC_B_S0_SDA

BI

45 48 84

5 DN2/DP3
GND
6

SMCLK

10

SMBUS_SMC_B_S0_SCL

BI

45 48 84

CPU_THERMD_N

BI

THERM*/ADDR

CRITICAL

10K

THRM_PAD
11

Placement note:

CPUTHMSNS_D2_P

Place U5510 under CPU


SIGNAL_MODEL=EMPTY

C5512

Q5510

0.0022uF

10%
50V
CERM
402

PLACE_NEAR=U5510.4:5mm
PLACE_NEAR=U5510.5:5mm

BC846BMXXH
SOT732-3
2
85

Write Address: 0x98


Read Address: 0x99

CPUTHMSNS_D2_N

Detect DDR/5V/3.3V Proximity Temperature

Placement note:
Place Q5510 next to DDR/5V/3.3V supply on TOP side

T29 Die
85 51 34

PCH-T29 Proximity/FinStack

BI

T29_THERMD_P

85 51 34

T29_THERMD_P

MAKE_BASE=TRUE

Detect T29 Die Temperature

NOSTUFF1
R5523
10K
PLACE_SIDE=BOTTOM 5%
1/10W
MF-LF
603 2

PLACE_NEAR=U3600.B1:2mm

R5520
PP3V3_S0

47

5%
1/16W
MF-LF
402

20%
10V
CERM
402

R5521 1

EMC1412-A
TQFN
2 DP
3 DN

SIGNAL_MODEL=EMPTY

C5522

Q5520

0.0022uF

PLACE_NEAR=U5520.2:5mm
PLACE_NEAR=U5520.3:5mm

BC846BMXXH
SOT732-3
85

10%
50V
CERM
402

Detect Fin Stack Temperature


84 48 45 32 6

84 48 45 32 6

BI

SMBUS_SMC_0_S0_SDA

BI

SMBUS_SMC_0_S0_SCL

5%
1/16W
MF-LF
402 2

R5522
10K

5%
1/16W
MF-LF
402

4 T29THMSNS_THM_L
6 T29THMSNS_ALERT_L

7 SMDATA
8 SMCLK

T29THMSNS_D2_N

Placement note:

ALERT*

THRM
GND PAD
5

THERM*/ADDR

CRITICAL

10K

T29THMSNS_D2_P

T29_THERMD_N

C5520
0.1uF

U5520
85

85

SM

VDD

XW5520

Use GND pin B1 on U3600 for N leg

PP3V3_S0_T29THMSNS_R
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V

71 62 61 57 54 52 51 50 49 48
23 22 20 19 18 17 16 12 8 7 6
46 42 41 40 37 36 33 29 27 26
85 77 75 74 73 72

Placement note:
Place U5520 between PCH and T29 on TOP side

Place Q5520 on BOTTOM side close to finstack

Write Address: 0x98


Read Address: 0x99

SYNC_MASTER=LINDA_K90I

SYNC_DATE=10/22/2010

PAGE TITLE

Thermal Sensors
DRAWING NUMBER

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

55 OF 109
SHEET

51 OF 86

PP5V_S0

72 70 68 65 54 47 42 22 7 6
77 73

PP3V3_S0

71 62 61 57 54 51 50 49 48
23 22 20 19 18 17 16 12 8 7 6
46 42 41 40 37 36 33 29 27 26
85 77 75 74 73 72

CRITICAL

R5660 1

47K

45

5%
1/16W
MF-LF
402

R5665
47K 2
1

SMC_FAN_0_TACH

J5601

78171-0004
NC

M-RT-SM
5

2
1

FAN_RT_TACH

5V DC
TACH

5%
1/16W
MF-LF
402

NC

MOTOR CONTROL
GND

R5661 1
100K

518S0521

45

FAN_RT_PWM

SOD-VESM-HF
2

SMC_FAN_0_CTL

Q5660
SSM3K15FV

2
S

5%
1/16W
MF-LF
402

SYNC_MASTER=K24_MLB

SYNC_DATE=07/20/2009

PAGE TITLE

Fan
DRAWING NUMBER

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

56 OF 109
SHEET

52 OF 86

PSOC USB CONTROLLER


-

R5704

1.5

BYPASS=U5701.49:50:11 mm
BYPASS=U5701.49:50:8 mm
BYPASS=U5701.49:50:5 mm

PP3V3_S3_PSOC

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

54 6
54 6
54 6
54 6

337S2983

TP_PSOC_SCL
TP_PSOC_SDA
NC_PSOC_P1_3
TP_ISSP_SCLK_P1_1
ISSP SCLK/I2C SCL
1

24

85

P2_2
P2_0
P4_6
P4_4
P4_2
P4_0
P3_6
P3_4
P3_2
P3_0
P5_6
P5_4
P5_2
P5_0
THRML
PAD

42
41
40
39
38
37
36
35
34
33
32
31
30
29

24

PSOC

VDD

8MA (TYP) 1.5 OHM


14MA (MAX)

0.012
0.021

V
V

96E-6 W
294E-6 W

18V BOOSTER

VIN

4MA (MAX) 4.7 OHM

0.0188 V

75.2E-6 W

72 54 53 46 7
63 53 48 47 46 45 43 26 7 6
73 64

USB_TPAD_R_N

5%
1/16W
MF-LF
402

PP3V3_S4
PP3V42_G3H

NC

C5702

30

29

WS_KBD1
WS_KBD2
6
WS_KBD3
6
WS_KBD4
6
WS_KBD5
6
WS_KBD6
6
WS_KBD7
6
WS_KBD8
6
WS_KBD9
6
WS_KBD10
6
WS_KBD11
6
WS_KBD12
6
WS_KBD13
6
WS_KBD14
6
6 WS_KBD15_CAP
6 WS_KBD16_NUM
WS_KBD17
6
WS_KBD18
6
WS_KBD19
6
WS_KBD20
6
WS_KBD21
6
WS_KBD22
6
WS_KBD23
6
6 WS_KBD_ONOFF_L

28

53 6

53
53
53

53
6 53
53
6 53
53
6 53

R5714

6 53
6 53

53

WS_KBD15_C

470

53
53

53

1%
1/16W
MF-LF
402

6 53

53

6 53

53

WS_KBD16N

10K

53
53

53

1%
1/16W
MF-LF
402

53
53

53
53

6 53
53

R5710

6 53
6 53
46 45
6 53

OUT

SMC_ONOFF_L

C5710

6 53

1
1

0.1UF

6 53

1K

53

6 53
6 53

26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4

5%
1/16W
MF-LF
402

53 6
53 6

20%
10V
CERM 2
402

6 53

27

53 6

WS_LEFT_SHIFT_KBD
WS_LEFT_OPTION_KBD
WS_CONTROL_KBD

PLACEMENT_NOTE=NEAR J5713

NC

6 53

31
F-RT-SM

6 53

J5713
CRITICAL

100PF

5%
2 50V
CERM
402

32

FF14-30A-R11B-B-3H

Z2_CLKIN
TP_P7_7

1
85

36E-3 W
0.72E-3 W

53

518S0637

6 53
6 53
6 53
8

SMC Manual Reset & Isolation

6 54

Left shift, option & control keys combined with power button cause SMC RESET# assertion.

(PP3V3_S3_PSOC)

V
V

57

USB_TPAD_R_P

R5702
USB_TPAD_N

0.6
0.012

4.7UF

WS_KBD17
WS_KBD16N
WS_KBD15_C
WS_KBD14
WS_KBD13
WS_KBD12
WS_KBD11
WS_KBD10
WS_KBD9
WS_KBD8
WS_KBD7
WS_KBD1
WS_KBD2
WS_KBD3

5%
1/16W
MF-LF
402

80 24

10 OHM
60MA (MAX)
60MA (MAX) 0.2 OHM

20%
2 6.3V
X5R
603

WS_KBD4
WS_KBD5
WS_KBD6
TP_ISSP_SDATA_P1_0
ISSP SDATA/I2C SDA
2

VDD
VOUT

R5715

R5701
USB_TPAD_P

80 24

Keyboard Connector

43

45

46

47

48

49

50

51

52

53

54

P2_5
P2_7
P0_1
P0_3
P0_5
P0_7
VSS
VDD
P0_6
P0_4
P0_2
P0_0
P2_6
P2_4
(SYM-VER2)

P7_7
24
P7_0
25
P1_0
26
P1_2
27 P1_4
28
P1_6

54 6

3V3 LDO

23

54 6

MLF

22 VDD

54 6

CY8C24794

21 D-

54 6

U5701

20 D+

54 6

CRITICAL
OMIT

19 VSS

54 6

NC

PSOC_VBUS_EN
Z2_DEBUG3
Z2_RESET
PSOC_MISO
PSOC_F_CS_L
PSOC_MOSI
PSOC_SCLK
Z2_MISO
Z2_CS_L
Z2_MOSI
Z2_SCLK

IN

P2_3
2 P2_1
3
P4_7
4
P4_5
5 P4_3
6
P4_1
7
P3_7
8
P3_5
9
P3_3
10
P3_1
11
P5_7
12
P5_5
13 P5_3
14
P5_1

18 P1_1

54 6

15 P1_7

WS_CONTROL_KEY
Z2_KEY_ACT_L

53

POWER

2.55 KOHM 0.0255 V


0.204 V

0.255E-6 W
16.32E-6 W

10UA
80UA

C5706

WS_KBD23
WS_KBD22
WS_KBD21
WS_KBD20
WS_KBD19
WS_KBD18
56

53

V_SNS

V+

53

55

53

R_SNS

TMP102

17 P1_3

54 6

CURRENT

53

16 P1_5

53

10%
2 16V
X7R-CERM
402

SMC_PME_S4_WAKE_L
PICKB_L
BUTTON_DISABLE
Z2_HOST_INTN
WS_LEFT_SHIFT_KEY
WS_LEFT_OPTION_KEY

OUT
54 6

C5705
0.1UF

5%
2 50V
CERM
402

220K

73

100PF

R57031

46 45

C5704

PIN NAME

C5703
0.1UF

10%
2 16V
X7R-CERM
402

Keys ANDed with PSOC power to isolate when PSOC is not powered.

C5701
4.7UF

63 53 48 47 46 45 43 26 7 6
73 64

20%
2 6.3V
X5R
603

72 54 53 46 7

BYPASS=U5701.22:19:5 mm
BYPASS=U5701.22:19:8 mm
BYPASS=U5701.22:19:11

PP3V42_G3H

PP3V3_S4

CRITICAL

mm

VDD

10%
2 16V
X7R-CERM
402

0.1UF

U5750

C5750

PP3V3_S4

IC

USB INTERFACES TO MLB


SPI HOST TO Z2
TRACKPAD PICK BUTTONS
KEYBOARD SCANNER

44

72 54 53 46 7

SLG4AP006
53 6

WS_LEFT_SHIFT_KBD

2 IN_A1

TDFN

(IPD)

3 IN_A2

OUT_A 4

WS_LEFT_SHIFT_KEY

53

OUT_B 8

WS_LEFT_OPTION_KEY

53

(IPD)

TPAD Buttons Disable

7 IN_A3_B2
(IPD)

53 6

BUTTON_DISABLE

(IPD)

D 3

PLACE THESE COMPONENTS CLOSE TO J5800


THIS ASSUMES THERES A PP3V42_G3H PULL UP ON MLB

THRM
PAD

GND

Q5701
SSM3K15FV

6 IN_B1

53

WS_LEFT_OPTION_KBD

SMC_TPAD_RST_L

SOD-VESM-HF

NO STUFF

OUT

46

Q5702

63 46 45

IN

SMC_LID

S 2

THE TPAD BUTTONS WILL BE DISABLE


WHEN THE LID IS CLOSED
LID OPEN => SMC_LID_LC ~ 3.42V
LID CLOSE => SMC_LID_LC < 0.50V

D 3

SOD-VESM-HF

CRITICAL

C5755

SSM3K15FV

VDD

10%
2 16V
X7R-CERM
402

0.1UF

U5755

S 2

SLG4AP015V
2 IN_A1

TDFN

R5720

(IPD)

OUT_A* 4

3 IN_A2

SMC_TPAD_RST

(IPD)

53 6

WS_CONTROL_KBD

5%
1/16W
MF-LF
402

7 IN_A3_B2
(IPD)

OUT_B 8

6 IN_B1

WS_CONTROL_KEY

53

SYNC_MASTER=LINDA_K90I

WELLSPRING 1

THRM
PAD

DRAWING NUMBER

GND

SYNC_DATE=07/12/2010

PAGE TITLE

(IPD)

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

57 OF 109
SHEET

53 OF 86

BOOSTER +18.5VDC FOR SENSORS

BOOSTER DESIGN CONSIDERATION:


- POWER CONSUMPTION
- DROOP LINE REGULATION
- RIPPLE TO MEET ERS
- 100-300 KHZ CLEAN SPECTRUM
- STARTUP TIME LESS THAN 2MS
- R5812,R5813,C5818 MODIFIED
CRITICAL
PP5V_S3_P18V5S5

CONFRIM IF THIS CAN BE CONNECTED TO S3!!

D5802
SOD-323

PP5V_S5

R5805
2

P18V5S5_SW

R5806
PP18V5_S5_R

PP5V_S3_P18V5S5_VIN

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=5V

5%
1/16W
MF-LF
402

C5818

R5812

FB

53 6

C5819

2.2UF

THRML

16V
2 X5R

PAD

603

402

10%

53 6

R5813

54 6

603-1

53 6

71.5K

SW

1%
1/16W
MF-LF
2 402

R5811

100K

GND

10%

16V
X7R-CERM 2

53 6

25V 2
X5R

6 54

CRITICAL

C5817

PGND

0.1UF

Z2_BOOST_EN

1%
1/16W
MF-LF
2 402

CTRL

C5816

DO

1UF
10%

QFN

J5800
PP3V3_S4

72 53 46 7

53 6

TPS61045
NC

CRITICAL

6 54

53 6

1%
1/16W
MF-LF
2 402

P18V5S5_FB

PP18V5_S5
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=18.5V

1M

5%
50V
CERM 2
402

U5805

5%
1/16W
MF-LF
402

1
1

39PF

VIN

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=18.5V

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
SWITCH_NODE=TRUE
B0520WSXG

VLF3010AT-SM-HF

72 66 7

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=5V

IPD Flex Connector

CRITICAL

L5801

3.3UH-870MA

53 6

55560-0228

PP18V5_S5

M-ST-SM

Z2_CS_L
Z2_DEBUG3
Z2_MOSI
Z2_MISO
Z2_SCLK
Z2_BOOST_EN
Z2_HOST_INTN
P3V3_S3_TPAD
Z2_CLKIN

10

12

11

14

13

16

15

18

17

20

19

22

21

6 54

Z2_KEY_ACT_L 6 53
Z2_RESET
6 53
PSOC_F_CS_L
6 53
PICKB_L
6 53
PSOC_MISO
6 53
PSOC_MOSI
6 53
PSOC_SCLK
6 53
SMBUS_SMC_A_S3_SDA 6
SMBUS_SMC_A_S3_SCL 6

32 45 48 55 84
32 45 48 55 84

NO STUFF

R5800
48 33 32 31 30 26 24 18 8 7 6
73 72 55 50

PP3V3_S3

1
5% 1/16W

2
MF-LF 402

MIN_LINE_WIDTH=0.40MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V

516S0689

Keyboard Backlight Driver & Detection


72 70 68 65 52 47 42 22 7 6
77 73

PP5V_S0

CRITICAL
KB_BL

PP3V3_S0

470K

BI

SMC_SYS_KBDLED
1

If LOW, keyboard backlight present


If HIGH, keyboard backlight not present

5%
1/16W
MF-LF
2 402

R5853 always stuffed, R5854 only


grounded when KB BL flex connected.

R5854
4.7K

LED 5

KB_BL

KB_BL

5%
1/16W
MF-LF
402 2

KBDLED_ANODE

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM

R5855

U5850

NO STUFF

10

518S0691

1%
1/16W
MF-LF
2 402

KBDLED_CAP

CAP 4

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.25 MM

THRML
GND

PAD

J5815 pin 1 is grounded


on keyboard backlight flex

DFN

10K

CRITICAL

LT3491

R58521

SMC_KDBLED_PRESENT_L

SW 3

6 CTRL

KB_BL

To detect Keyboard backlight, SMC will


tristate and read SMC_SYS_KBDLED:

F-RT-SM
6

10V 2
X5R
402-1

FF18-4A-R11AD-B-3H

VIN

10%

45

1UF

5%
1/16W
MF-LF
402 2

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.25 MM
SWITCH_NODE=TRUE

1098AS-SM

KB_BL

C5850

J5815

R58531

CRITICAL
KB_BL

10UH-0.58A-0.35OHM
1
2
KBDLED_SW

72 71 62 61 57 52 51 50 49 48
23 22 20 19 18 17 16 12 8 7 6
46 42 41 40 37 36 33 29 27 26
85 77 75 74 73

Keyboard Backlight Connector

L5850

BYPASS=U5850.1:2:2 MM

KB_BL
1

C5855
1UF

10%
35V
2 X5R
603

(SMC_KBDLED_PRESENT_L)

SYNC_MASTER=LINDA_K90I

SYNC_DATE=07/12/2010

PAGE TITLE

WELLSPRING 2
DRAWING NUMBER

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

K6 NOTES : C5850 HAS BYPASS PROPERTY, SHOULD BE ADDED INCASE THIS PAGE IS SYNCED FROM T27

BRANCH

PAGE

58 OF 109
SHEET

54 OF 86

48 33 32 31 30 26 24 18 8 7 6
73 72 54 50

PP3V3_S3
BYPASS=U5920.14:13:8 mm

20%
6.3V
X5R
603

C5922
0.1UF

VDD

10%
16V
X5R
402

R5924 1

BYPASS=U5920.14:13:8 mm

NC
NC

10K
5%
1/16W
MF-LF
402

46 45

OUT

10UF

14

CRITICAL

C5926

NC

LIS331DLH
15

LGA

CS

11
9

5%
1/16W
MF-LF
402

SDO
SDA/SDI/SDO
SCL/SPC

INT1
INT2

0
1

7
6
4

SMS_ADDR_SELECT
I2C_SMC_SMS_SDA_R
I2C_SMC_SMS_SCL_R

SMBUS_SMC_A_S3_SDA

BI

SMBUS_SMC_A_S3_SCL

IN

6 32 45 48 54 84

R5922
R5921 1

16

13

2
5%
1/16W
MF-LF
402

GND
12

R5923

SMS_I2C_SEL

RESERVED

10K

PLACE_SIDE=TOP

U5920

10

SMS_INT_L
TP_SMS_INT2

R5920 1

VDD_IO

0
1

10K

338S0687

5%
1/16W
MF-LF
402

PLACEMENT_NOTE=See schematic for orientation.

6 32 45 48 54 84

5%
1/16W
MF-LF
402

SMS_ADDR_SELECT=0 Addr: 0x30(Wr)/0x31(Rd)


SMS_ADDR_SELECT=1 Addr: 0x32(Wr)/0x33(Rd)

Desired orientation when placed on top-side:

NOTE: SDA and SCL have internal pull-ups to VDD_IO.


+Y
+X

Front of system

+Z (up)

Circle indicates pin 1 location when placed


in correct orientation

SYNC_MASTER=LINDA_K90I

SYNC_DATE=07/08/2010

PAGE TITLE

Digital Accelerometer
DRAWING NUMBER

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

59 OF 109
SHEET

55 OF 86

C
PP3V3_S5

R6101
3.3K

C6100

30 26 24 23 22 20 19 17 8 7 6
85 76 74 73 72 66 46

20%
10V
CERM
402

CRITICAL

VDD

0.1UF

5%
1/16W
MF-LF
2 402

U6100
64MBIT

47

IN

SPI_MLB_CLK

SCK

SOIC

SI

SPI_MLB_MOSI

IN

47

SO

SPI_MLB_MISO

OUT

47

SST25VF064C
47

47 19 6

IN

IN

SPI_MLB_CS_L
SPI_WP_L
SPIROM_USE_MLB

1
3
7

CE*
WP*
HOLD*

OMIT

VSS
4

NOTE: If HOLD* is asserted


ROM will ignore SPI cycles.

SYNC_MASTER=K91_MLB

SYNC_DATE=05/15/2010

PAGE TITLE

SPI ROM
DRAWING NUMBER

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

61 OF 109
SHEET

56 OF 86

AUDIO CODEC
APPLE P/N 353S2355

L6201

U6201 CONSUMES ?MA MAX. FROM 1.5V RAIL

FERR-220-OHM
71 57 42 26 22 20 16 7

PP1V5_S0

IN

PP5V_S3

C6210

C6211

4.7UF

0.1UF

20%
4V
X5R-1
402

10%
16V
X5R
402

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.5V

PP1V5_S0

C6218

C6221

25

46

24

10%
16V
X5R
402

C6220

59

OUT AUD_GPIO_1

12

14
15

VD VA_REF VA_HP VA
VBIAS_DAC
HPOUT_L
VHP_FILT+
HPOUT_R
VHP_FILTCS4206B
HPREF
QFN
GPIO0/DMIC_SDA1 LINEOUT_L1+
GPIO1/DMIC_SDA2 LINEOUT_L1/SPDIF_OUT2
GPIO2
LINEOUT_R1+
GPIO3
LINEOUT_R1-

13

SENSE_A

45
43
42

FLYP
FLYC
FLYN

R6210
2.67K

57

10UF

20%
6.3V
X5R
603-1

20%
6.3V
X5R
603-1

VBIAS_DAC
CS4206_FP
CS4206_FN

CRITICAL

1%
1/16W
MF-LF
402

10UF

61

OUT AUD_GPIO_2
OUT AUD_GPIO_3

62

IN

AUD_SENSE_A

61 57 54 52 51 50 49 48 46
23 22 20 19 18 17 16 12 8 7 6
42 41 40 37 36 33 29 27 26
85 77 75 74 73 72 71 62

IN

PP3V3_S0

29
44
41

TP_AUD_DMIC_SDATA

60

CS4206_FLYP
CS4206_FLYC

C6222
1

C6226

C6223

2.2UF

20%
6.3V
CERM
402-LF

0.1UF
10%
16V
X5R
402

2.2UF
2

20%
6.3V
CERM
402-LF

CS4206_FLYN

U6201

VL_HD

VL_IF

BITCLK

C
HDA_SYNC
10

R6211
81 16

HDA_SDIN0

OUT

81 16

IN

81 16

IN

81

AUD_SDI_R

8
5

5%
1/16W
MF-LF
402

HDA_SDOUT
HDA_RST_L
TP_AUD_SPDIF_IN

NC

22

11

47
48

AUD_SPDIF_OUT_CHIP
61

AUD_SPDIF_OUT

OUT

10%
10V
X5R
402-1

C6217
10UF

C6214

0.1UF
10%
16V
X5R
402

10%
16V
X5R
402

20%
16V
TANT-POLY
2012-LLP

10UF

CRITICAL

38
40

MIN_LINE_WIDTH=0.30MM

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.30MM

MIN_NECK_WIDTH=0.20MM

AUD_HP_PORT_L
AUD_HP_PORT_R

39

MIN_LINE_WIDTH=0.30MM

MIN_NECK_WIDTH=0.20MM

AUD_HP_PORT_REF

57 58 61 62

59

OUT

TP_AUD_LO1_P_L
TP_AUD_LO1_N_L
AUD_LO1_P_R
AUD_LO1_N_R

35
34
36
37

OUT

59

IN

61

NC
NC

AUD_LO2_P_L
AUD_LO2_N_L
AUD_LO2_P_R
AUD_LO2_N_R

MICBIAS

16

AUD_CODEC_MICBIAS

OUT

60 85

OUT

60 85

OUT

60 85

OUT

60 85

OUT

60 85

OUT

60 85

OUT

62

FR SPKR AMP. SIG. SOURCE

LFT. SPKR AMP. SIG. SOURCE


RT. SPKR AMP. SIG. SOURCE

28 CS4206_VCOM

LINEIN_L+
LINEIN_CLINEIN_R+

21
23

AUD_LI_P_L
AUD_LI_REF
AUD_LI_P_R

MICIN_L+
MICIN_LMICIN_R+
MICIN_R-

18
17
19
20

AUD_MIC_INP_L
AUD_MIC_INN_L
AUD_MIC_INP_R
AUD_MIC_INN_R

VREF+_ADC

27

22

IN

58

IN

58

IN

58

IN

62

IN

62

IN

62

IN

62

SYNC
SDI
SDO
RESET*

SPDIF_IN
SPDIF_OUT

CS4206_VREF_ADC

22

DMIC_SCL

AUD_DMIC_SCL

BI MIC CODEC INPUT

TP_AUD_DMIC_CLK 57

5%
1/16W
MF-LF
402

DGND THRM_PAD AGND


7

EXT MIC CODEC INPUT

NC

R6214

1UF
20%
16V
TANT
0603-SM

C6225

NOSTUFF

10UF
1

20%
16V
TANT-POLY
2012-LLP

R6213
100K

5%
1/16W
MF-LF
402

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V

GND_AUDIO_CODEC

57 59 61

GND_AUDIO_CODEC

C6224

62 61 58 57

20%
6.3V
X5R
603-1

31
30
32
33

VCOM

6 57

C6213

GND_AUDIO_HP_AMP

39
5%
1/16W
MF-LF
402

0.1UF
2

R6212
1

D
IN

26

HDA_BIT_CLK

IN

49

IN

81 16

C6215

LINEOUT_L2+
LINEOUT_L2LINEOUT_R2+
LINEOUT_R2-

CRITICAL

81 16

0.1UF

CRITICAL

PP4V5_AUDIO_ANALOG

IN

GPIO1 = HP AMP CONTROL


GPIO2 = ANALOG SW CONTROL
GPIO3 = SPKR AMP SHDN CONTROL

20%
16V
TANT-POLY
2012-LLP

GND_AUDIO_HP_AMP

1UF

10UF

57 6

7 16 20 22 26 42 57 71

PP4V5_AUDIO_ANALOG

C6216
C6219

61 59 57

6 7 30 32 42 43 44 46 57 59 60
61 66 67 72

PP1V8R1V5_S0_AUDIO_DIG

0402

Digial Mic
57

TP_AUD_DMIC_CLK

57

TP_AUD_DMIC_SDATA TP_AUD_DMIC_SDATA

TP_AUD_DMIC_CLK

57

MAKE_BASE=TRUE

4.5V POWER SUPPLY FOR CODEC

57

MAKE_BASE=TRUE

APPLE P/N 353S2456


NOTES ON CODEC I/O
L6200

MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.10MM
VOLTAGE=5V

FERR-220-OHM
59 57 46 44 43 42 32 30 7 6
72 67 66 61 60

IN

PP5V_S3

IN

PP3V3_S0

TPS71745

4V5_REG_IN

IN

4V5_REG_EN

EN

0402

2.21K
1

SON

OUT

PP4V5_AUDIO_ANALOG

OUT

DIFF FSINPUT= 2.45VRMS


SE FSINPUT= 1.22VRMS
DAC1 FSOUTPUT= 1.34VRMS
DAC2/3 FSOUTPUTDIFF= 2.67VRMS
DAC2/3 FSOUTPUTSE= 1.34VRMS

6 57

CRITICAL

R6200
61 57 54 52 51 50 49 48 46
23 22 20 19 18 17 16 12 8 7 6
42 41 40 37 36 33 29 27 26
85 77 75 74 73 72 71 62

MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.10MM
VOLTAGE=4.5V

U6200

NR/FB

NC

4V5_NR

2
1%
1/16W
MF-LF
402

GND
1

C6200
1UF

10%
10V
X5R
402

C6202

C6201
1UF

XW6200
SM
1

10%
16V
X7R-CERM
402

10%
10V
X5R
402

C6203
1UF

0.1UF
2
2

10%
10V
X5R
402

GND_AUDIO_CODEC

57 58 61 62

NOSTUFF

R6201
1

SYNC_MASTER=LENG_K90I

AUDIO: CODEC/REGULATOR
DRAWING NUMBER

Apple Inc.

XW6201
SM
1

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V

SIZE

D
REVISION

GND_AUDIO_HP_AMP

57 59 61

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=08/10/2010

PAGE TITLE

5%
1/16W
MF-LF
402

BRANCH

PAGE

62 OF 109
SHEET

57 OF 86

D
LINE INPUT VOLTAGE DIVIDER
CODEC RIN = 20K OHMS
NET RIN = 10.36K OHMS (INCLUDING PULL-DOWNS AT ANALOG SWITCH COM PINS)
FC_HP = 3.6 HZ
FC_LP = 43KHZ
VIN = 2VRMS, CODEC VIN = 1.14 VRMS

CRITICAL

C6301

R6301
61

IN

AUD_LI_L
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM

2.2UF

7.87K2

AUD_LI_L_DIV

MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM

1%
1/16W
MF-LF
402

20%
10V
X5R-CERM
402

C
NOSTUFF
1

C6303
820PF

10%
2 50V
CERM
402

AUD_LI_P_L

57

OUT

MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM

R6302
21.5K

1%
1/16W
MF-LF
2 402

CRITICAL

C6302
2.2UF
1

20%
10V
X5R-CERM
402

61

IN

MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM

AUD_LI_GND

AUD_LI_REF
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM

OUT

57

R6300
10

CRITICAL

1%
1/16W
MF-LF
2 402

C6312
2.2UF
1

62 61 57

IN

GND_AUDIO_CODEC

NOSTUFF
1

C6313
820PF

10%
50V
2 CERM
402

20%
10V
X5R-CERM
402
1

R6312

21.5K
1%
1/16W
MF-LF
2 402

CRITICAL

C6311

R6311
61

IN

AUD_LI_R
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM

7.87K2

1%
1/16W
MF-LF
402

2.2UF

AUD_LI_R_DIV
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM

20%
10V
X5R-CERM
402

AUD_LI_P_R
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM

OUT

57

A
PAGE TITLE

AUDIO: LINE INPUT FILTER


DRAWING NUMBER

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

63 OF 109
SHEET

58 OF 86

FOR PROTO2, STUFF R6521 AND NO STUFF R6520 AND R6522 UNTIL
RE-TASKABLE IO SW SUPPORT AVAILABLE (FORCES IO INTO OUTPUT MODE).

D
L6520
FERR-120-OHM-1.5A

PP5V_S3

60 57 46 44 43 42 32 30 7 6
72 67 66 61

HP/LO AMP
APN: 353S1637

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
AUD_PP5V_F

2
0402-LF
1

C6520

NO STUFF

C6521

0.1UF

10UF

R6521

10%
16V
X7R-CERM
402

20%
6.3V
X5R
603

5%
1/16W
MF-LF
402

MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.2MM
12

VDD
AUD_LO_AMP_INL_M

ZOBEL NETWORK & 1ST ORDER DAC FILTER PLACEHOLDER

59

CRITICAL

AUD_LO_AMP_INR_M

INL
INR

AUD_GPIO_1_R

SHDN*

59

U6500
MAX9724A

0.1UF
10%
16V
X7R-CERM
402

NC

R6500

61 59 57

IN

PVSS

1UF

CRITICAL

R6523

10%
10V
X5R
402

2.21K
1%
1/16W
MF-LF
2 402

C6522
10%
10V
X5R
402

GND_AUDIO_HP_AMP
61 59 57

R6524
2.21K

1%
1/16W
MF-LF
2 402

C6523

1UF

1UF

59 61

C6524

CRITICAL

39
5%
1/16W
MF-LF
402

OUT

CRITICAL
1

MAX9724_SVSS

5%
1/16W
MF-LF
402

59 61

MAX9724_C1P
1

MAX9724_C1N

100K
2

AUD_HP_ZOBEL_L

R6522

SVSS

C6500

PGND

CRITICAL

THRM
PAD

5%
1/16W
MF-LF
402

AUD_HP_PORT_L

OUT

10

C1P
C1N
SGND

0
1

IN

AUD_GPIO_1

13

59 57

IN

AUD_LO_AMP_OUTR

11

OUTL
OUTR

TQFN

R6520
57

AUD_LO_AMP_OUTL

MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.2MM

10%
10V
X5R
402

GND_AUDIO_HP_AMP

R6510

39
5%
1/16W
MF-LF
402

NC

MAX9724 GAIN/FILTER COMPONENTS

AUD_HP_ZOBEL_R

AV_PB = -1V/V, FC_LPF = 35.2KHZ


CRITICAL

C6510

CRITICAL
1

C6530

0.1UF
10%
16V
X7R-CERM
402

59 57

IN

330PF
1

5%
50V
COG
402

AUD_HP_PORT_R

R6531
1

13.7K

1%
1/16W
MF-LF
402

R6530
AUD_HP_PORT_L
59 57

AUD_LO_AMP_INL_M

AUD_LO_AMP_OUTL

13.7K
1

IN

59

OUT

59 61

OUT

59 61

1%
1/16W
MF-LF
402

R6532
AUD_HP_PORT_R
59 57

IN

13.7K
1

AUD_LO_AMP_INR_M

AUD_LO_AMP_OUTR

59

1%
1/16W
MF-LF
402

R6533
1

13.7K

1%
1/16W
MF-LF
402

CRITICAL

C6531
330PF
1

5%
50V
COG
402

SYNC_MASTER=LENG_K90I

SYNC_DATE=08/10/2010

PAGE TITLE

AUDIO: HEADPHONE FILTER


DRAWING NUMBER

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

65 OF 109
SHEET

59 OF 86

SATELLITE

& SUB TWEETER AMPLIFIER

APN:353S2888
SATELLITE

169 HZ < FC < 282 HZ

SUB

80 HZ < FC < 132 HZ

GAIN

3DB

ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM

PP5V_S3

85 57

AUD_LO2_P_R

IN

C6607

CRITICAL

L6611

C6611

FERR-1000-OHM
85

0.1UF
10%

0.0047UF

SPKRAMP_INR_P

A1

59 57 46 44 43 42 32 30 7 6
72 67 66 61 60

16V

X5R
402

10%

FERR-1000-OHM
85 57

AUD_LO2_N_R

IN

85

MAX98300
WLP

CRITICAL

25V

C6610

CERM
402

0.0047UF
1

SPKRAMP_INR_N

85

85

A3 IN+
B3 IN-

SSM2315_R_P
SSM2315_R_N

CRITICAL

C6601
47UF

U6610

0402

L6610

PVDD

CRITICALOUT-

B1
C1

GAIN

C3

OUT+

20%
6.3V
TANT1
2012-LLP

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_R_P_OUT

6 61 85

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_R_N_OUT

6 61 85

0402
10%
25V

CERM
402

C2

SHDN*

B2

NC

SPKAMP1_GAIN

R6612

R6610
57

AUD_GPIO_3

IN

2
2

5%
1/16W
MF-LF
402
60

100K

R6611
100K

PGND

5%
1/16W
MF-LF
402

A2

5%
1/16W
MF-LF

2402

SPKRAMP_SHDN

ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM

PP5V_S3
CRITICAL

L6621
85 57

IN

AUD_LO1_P_R

85

C6608

C6621

FERR-1000-OHM

0.1UF

0.022UF
SPKRAMP_INSUB_P

A1

59 57 46 44 43 42 32 30 7 6
72 67 66 61 60

10%

16V

X5R
402

0402

FERR-1000-OHM
85 57

IN

AUD_LO1_N_R

25V

85

X7R
0402

C6620
0.022UF
SPKRAMP_INSUB_N

A3
B3

SSM2315_SUB_P
SSM2315_SUB_N

85

85

MAX98300
WLP
IN+
IN-

CRITICAL

C6603

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_SUB_P_OUT

100UF
2

U6620

10%
CRITICAL

L6620

PVDD

OUT+
CRITICALOUT-

20%
6.3V
TANT
CASE-AL1

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_SUB_N_OUT

B1
C1

6 61 85

6 61 85

0402
10%
25V

X7R
0402

C2

SHDN*

B2

NC

GAIN

C3SPKAMP2_GAIN
1

R6622
100K
5%
1/16W
MF-LF

PGND
SPKRAMP_SHDN

2402

A2

60

B
ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM

PP5V_S3

C6609
CRITICAL

L6631
85 57

IN

AUD_LO2_P_L

85

10%
16V

0.0047UF
SPKRAMP_INL_P

0.1UF

C6631

FERR-1000-OHM

X5R
402

2
10%
25V

CERM
402

PVDD

FERR-1000-OHM
85 57

IN

AUD_LO2_N_L

85

SPKRAMP_INL_N

U6630

CRITICAL

C6630
0.0047UF
1

85

85

SSM2315_L_P
SSM2315_L_N

A3
B3

MAX98300
WLP
IN+
IN-

CRITICAL

C6605

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_L_P_OUT

47UF

0402

L6630

A1

59 57 46 44 43 42 32 30 7 6
72 67 66 61 60

OUT+
CRITICALOUT-

20%
6.3V
TANT1
2012-LLP

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_L_N_OUT

B1
C1

6 61 85

6 61 85

0402
10%
25V

CERM
402

C2

SHDN*

B2

NC

GAIN

C3SPKAMP3_GAIN
1

R6632
100K

PGND
SPKRAMP_SHDN

A2

60

5%
1/16W
MF-LF

2402

SYNC_MASTER=LENG_K90I

SYNC_DATE=08/10/2010

PAGE TITLE

AUDI0: SPEAKER AMP


DRAWING NUMBER

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

66 OF 109
SHEET

60 OF 86

AUDIO JACK: LI/LO/HP CONNECTOR, SPDIF TX


AUD_SPDIF_OUT

IN

57

HS_MIC_HI

OUT

62

HS_MIC_LO

OUT

62

L6701
FERR-1000-OHM
85 77 75
51 50 49 48 46 42 41 40
20 19 18 17 16 12 8 7 6
37 36 33 29 27 26 23 22
74 73 72 71 62 57 54 52

PP3V3_S0
0402

L6702
FERR-1000-OHM
1

0402

XW6702
SM

CRITICAL

AUD_CONNJ1_MIC

SPDIF-TXRX-K24

L6703

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM

F-RT-TH
CRITICAL

MIC
DETECT
SWITCH
LEFT
RIGHT
GND

2 AUD_HP_PORT_REF

APN:514-0671
J6700

FERR-120-OHM-1.5A
1

AUD_CONNJ1_SLEEVE
6

SM

MIN_NECK_WIDTH=0.2MM

AUD_CONNJ1_SLEEVEDET
AUD_CONNJ1_TIPDET
AUD_CONNJ1_TIP
AUD_CONNJ1_RING

2
1
3

57 59

XW6701

0402-LF

GND_AUDIO_HP_AMP
2

AUD_CONN_GND

57

OUT

XW6700

MIN_LINE_WIDTH=0.4MM

SM
1

AUD_LI_GND
2

58

CRITICAL

L6704
FERR-220-OHM
1

(AUD_CONN_GND)

AUD_CONN_L

BI

61

BI

61

61

0402

AUDIO
A - VIN
B - VCC
C - GND

CRITICAL
7

L6705

FERR-220-OHM

POF

R6700
1
10

SHELL

C6700
CRITICAL

1UF
10%

11
2

12

SHIELD
PINS

AUD_CONN_R

2
0402

OPERATING VOLTAGE 3.3

DZ6705

6.3V

CERM
402

DZ6703

6.8V-100PF
2

CRITICAL

402
CRITICAL

DZ6704

ANALOG MIC CONNECTOR

62

CRITICAL

APN:518S0520

J6701
78171-0003

402
1

1
1

C6701
100PF

OUT

62

5%
1/16W
MF-LF
402

62 6
62 6

5%
2

M-RT-SM

AUD_J1_TIPDET_R

4.7

6.8V-100PF

402

402
1

OUT

R6701

DZ6700

6.8V-100PF

6.8V-100PF

AUD_J1_SLEEVEDET_R
2

CRITICAL

DZ6701

10K
5%
1/16W
MF-LF
402

6.8V-100PF

402

13

CRITICAL

50V

62 6

CERM
402

BI_MIC_LO
BI_MIC_SHIELD
BI_MIC_HI

1
2
3

GND_CHASSIS_AUDIO_JACK
VOLTAGE=0V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.1MM

CHASSIS GND STITCHES

XW6710
SM
1

XW6711
SM
1

CRITICAL

SPEAKER CONNECTOR

J6702
78171-0002

R6760

M-RT-SM

0
1

APN:518S0519

2
5%
1/16W
MF-LF
402

85 60 6

IN

85 60 6

IN

SPKRAMP_L_P_OUT
SPKRAMP_L_N_OUT

1
2

59 57 46 44 43 42 32 30 7 6
72 67 66 60

85 60 6

PP5V_S3

IN

SPKRAMP_SUB_P_OUT

NO STUFF
1
C6760
33PF

R6716
59

OUT

AUD_LO_AMP_OUTL_SWITCH

1UF

5%
1/16W
MF-LF
402

10%
10V
X5R
402

OUT

U6700
C4 NC1
C1 NC2

5%
1/16W
MF-LF
402

58

IN

WLP

COM1 B4
2

A4 NO1
A1 NO2

R6718
AUD_LI_L

AUD_LI_L_SWITCH

R6712

85 60 6

IN

24K

85 60 6

IN

5%
1/16W
MF-LF
402

SPKRAMP_SUB_N_OUT
SPKRAMP_R_P_OUT

61

33PF
GND

C6711

85 60 6

0.0033UF

5%
1/16W
MF-LF
402

10%
50V
CERM
402

C3

AUD_LI_R_SWITCH

B3

0
1

5%
50V
CERM
402

NO STUFF
1
C6763

AUD_CONN_R

A2 NEG

R6719
AUD_LI_R

33PF

IN

2
3

MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.15MM

NO STUFF
C6762

CRITICAL

EN* B2

5%
50V
CERM
402

BI

SWITCH_CP

33PF
61

COM2 B1

C2 CB

5%
1/16W
MF-LF
402

58

M-RT-SM

NO STUFF
C6761
BI

MAX14560EWC+

AUD_LO_AMP_OUTR_SWITCH

J6703

AUD_CONN_L

MIN_NECK_WIDTH=0.15MM

VCC
0

CRITICAL

78171-0004

MIN_LINE_WIDTH=0.2MM

R6717
AUD_LO_AMP_OUTR
59

5%
50V
CERM
402

APN: 353S2803

C6710
A3

AUD_LO_AMP_OUTL

R6713

IN

APN:518S0521

5%
50V
CERM
402

SPKRAMP_R_N_OUT

C6760 - C6763 ARE FOR FILTERING POTENTIAL FSB NOISE COUPLED ON SPKR LINES

24K
2
2

5%
1/16W
MF-LF
402

AUD_GPIO_2
57

IN

R6721
100K

R6715
AUD_CONN_GND
61

0
5%
1/16W
MF-LF
402

GND STUFFING OPTIONS FOR CMOS SWITCH


62 58 57

GND_AUDIO_CODEC

ANALOG AUDIO IO SWITCH

SYNC_MASTER=LENG_K90I

SYNC_DATE=08/10/2010

PAGE TITLE

AUDIO: JACK
DRAWING NUMBER

AUD_SWITCH_GND

GPIO0 = 0 AND GPIO1 = 1 --> HP PATH SELECTED


GPIO0 = 1 AND GPIO1 = 0 --> LI PATH SELECTED

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM

Apple Inc.

VOLTAGE=0V

SIZE

D
REVISION

NOSTUFF

R6714
1

NOTICE OF PROPRIETARY PROPERTY:

R6727

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

5%
1/16W
MF-LF
402

BRANCH

PAGE

67 OF 109
SHEET

61 OF 86

CODEC OUTPUT SIGNAL PATHS


PORT B LEFT(HEADSET MIC)
HP=80HZ, LP=8.82KHZ

FUNCTION

VOLUME

CONVERTER

PIN COMPLEX

MUTE CONTROL

DET ASSIGNMENT

HP/LINE OUT

0X02 (2)

0X02 (2)

0X09 (9,A)

GPIO_2 AND GPIO_1

0X09 (A)

LINE IN

0X05 (5)

0X05 (5)

0X0C (12)

GPIO_2 AND GPIO_1

0X09 (A)AND UI ELEMENT

SATELLITES

0X04 (4)

0X04 (4)

0X0B (11)

GPIO_3

N/A

SUB

0X03 (3)

0X03 (03)

0X0A (10)

GPIO_3

N/A

SPDIF OUT

N/A

0X08 (8)

0X10 (16)

N/A

0X0D (B)

MIKEY

L6880

MIN_LINE_WIDTH=0.10MM
MIN_NECK_WIDTH=0.10MM
VOLTAGE=3.3V

FERR-1000-OHM
71 62 61 57 54 52 51 50 49 48
23 22 20 19 18 17 16 12 8 7 6 PP3V3_S0
46 42 41 40 37 36 33 29 27 26
85 77 75 74 73 72

PP3V3_S0_HS_RX

WCSP MIKEY 1A
APN:353S2640

0402

CODEC INPUT SIGNAL PATHS


CONVERTER

PIN COMPLEX

VREF

DET ASSIGNMENT

BUILT-IN MIC

0X06 (6)

0X0D (13,B,RIGHT)

MIC_BIAS (80%)

N/A

HEADSET MIC

0X06 (6)

0X0D (13,V22,B,LEFT)

MIKEY

MIKEY

C6880

1UF
10%

U6880
CD3282A1

X5R
402

SOUTHBRIDGE RESOURCES
PULLUPS ON MCP PAGE

SYSTEM GPIO
COUGAR_POINT GPIO16

N/A

AUD_I2C_INT_L

N/A

COUGAR_POINT GPIO5/PIRQH

N/A

B3

OUT

AUD_I2C_INT_L

D3

INT*

IN

AUD_IPHS_SWITCH_EN

A3

ENABLE

A1

HDET

B2

CS

23 19

NOSTUFF
R6885

APN:376S0613

R6801
300K

AUD_OUTJACK_INSERT_L
2

5%
1/16W
MF-LF
402

Q6800

1%
1/16W
MF-LF

402

402

Q6801

Q6801

C6801

2
4

57

57
1

OUT AUD_MIC_INN_L

0.1UF
20%
CERM

R6881

1K

OUT AUD_MIC_INP_L
MIKEY
CRITICAL

MIKEY

57 58 61 62

MIKEY

R6882
2.2K
5%
1/16W

MF-LF
402

MIKEY

MF-LF
2

402

R6884
2.2K

SOT563

GND_AUDIO_CODEC

HS_MIC_HI_RC

HS_MIC_HI

MIKEY

IN

61

IN

61

5%
1/16W

R6883

MIKEY

5%
1/16W
MF-LF
402

MF-LF

MIKEY

402

C6884

100K

10%
25V
X5R
402

10V
402

10%
25V
X5R
402

0.1UF
5

MF-LF

10%
CERM

C6883

1/16W

C6886
5

MIKEY
CRITICAL

AUD_J1_DET_RC

2
5%
1/16W
MF-LF
402

MIKEY

20%
6.3V
TANT
402-1

C6881
16V
402

1%

SSM6N37FEAPE

SOT563

C6882

0.01UF

5%

NC

CRITICAL
2.2UF

1/16W

47K
AUD_J1_TIPDET_R

HS_RX_BP

GND_AUDIO_CODEC

SOT563

SSM6N37FEAPE

MIKEY
1

0.1UF

SSM6N37FEAPE

IN

100K

402

62 61 58 57

AUD_PORTB_DET_L

NC

R6880

R6802
62 61

MIKEY_HDET

5%
1/16W
MF-LF
402

R6805

1%
1/16W
MF-LF

AUD_PORTA_DET_L

20.0K

39.2K
1

BYPASS

D1

SMBUS_PCH_DATA

PORT B DETECT(SPDIF DELEGATE)

R6806

B1 HS_SW_DET

BI

62 61 AUD_J1_TIPDET_R

62 PP3V3_S0_AUDIO_F

DETECT

81 77 48 42 31 29 27 23 16

OUT AUD_SENSE_A

57

MICBIAS

SDA

IN

18

PORT A DETECT (HEADPHONES)

SCL

81 77 48 42 31 29 27 23 16

COUGAR_POINT GPIO3/PIRQH

C1 HS_MIC_BIAS

C3

SMBUS_PCH_CLK

DGND

AUD_IPHS_SWITCH_EN

AUD_IP_PERIPHERAL_DET

WCSP

SYSTEM INTERRUPT

C2

FUNCTION

CRITICAL
MIKEY

AVDD

10V

AGND

FUNCTION

D2

A2

CRITICAL
MIKEY

C6885

0.0082UF
10%
X7R

27PF

25V
402
2

CRITICAL

5%
CERM

50V
402

CRITICAL

XW6880
SM

62 61 58 57 GND_AUDIO_CODEC
62 61 58 57 GND_AUDIO_CODEC

HS_MIC_LO

R6803
220K
62 PP3V3_S0_AUDIO_F

220K

IN

Q6800

5%
1/16W

62 61

AUD_J1_SLEEVEDET_INV

5%
1/16W
MF-LF
402

R6804

62 61 AUD_J1_SLEEVEDET_R

SSM6N37FEAPE

MF-LF
402

PORT B RIGHT(BUILT-IN MIC)

SOT563

AUD_J1_SLEEVEDET_R

R6850
1

C6802

62 61 58 57 GND_AUDIO_CODEC

R6851

100
1

57

0.01UF

IN

2.4K

AUD_CODEC_MICBIAS

10%
16V
CERM
402

1%
1/16W
MF-LF

MIC_BIAS_FILT

402

2
1%
1/16W
MF
402-1

CRITICAL

C6852
2.2UF

20%
6.3V
TANT
402-1

62 61 58 57 GND_AUDIO_CODEC

CRITICAL

L6850

C6850

FERR-1000-OHM

0.1UF
57

OUT AUD_MIC_INP_R

10%
25V
X5R
402

C6851
0.1UF
1

OUT AUD_MIC_INN_R

VOLTAGE=3.3V

SM

EXTRACTION NOTIFICATION CKT

L6862

IN

6 61

5%
1/16W
MF-LF
402

C6853

IN

6 61

IN

6 61

C6854

0.001UF
50V
402

10%
CERM

27PF
5%
CERM

50V
402

L6851

FERR-1000-OHM

R6853
BI_MIC_LO_F

2.4K

BI_MIC_LO

BI_MIC_SHIELD

FERR-1000-OHM
PP3V3_S0

BI_MIC_HI

CRITICAL

1%
1/16W
MF
402-1

XW6851

62 PP3V3_S0_AUDIO_F

IN

0402

MIN_LINE_WIDTH=0.10MM
MIN_NECK_WIDTH=0.10MM

61 57 54 52 51 50 49 48 46
23 22 20 19 18 17 16 12 8 7 6
42 41 40 37 36 33 29 27 26
85 77 75 74 73 72 71 62

R6852

CRITICAL

100K

62 61 58 57 GND_AUDIO_CODEC

BI_MIC_HI_F

10%
25V
X5R
402

0402

CRITICAL

57

HP=80HZ
2

0402

PLACE L6800/C6800 CLOSE TO JACK TRANS. AREA

R6864

220K

C6861
0.1UF
10V
402

20%
CERM

5%
1/16W
MF-LF
402

R6865
100K

Q6802

5%
1/16W
MF-LF
402

R6861

SSM6N37FEAPE

AUD_PERPH_DET_R

SOT563

Q6802
1

15K
5%
1/16W
MF-LF
402

OUT

18

SSM6N37FEAPE
SOT563

R6860
1

62 61 AUD_J1_TIPDET_R

AUD_IP_PERIPHERAL_DET

5%
1/16W
MF-LF
402

TIPDET_FILT
2
5
1

0.1UF
2

C6860
AUD_J1_TIPDET_INV

20%
10V
CERM
402

SYNC_MASTER=LENG_K90I

SYNC_DATE=08/10/2010

PAGE TITLE

AUDIO: JACK TRANSLATORS

62 61 58 57 GND_AUDIO_CODEC

DRAWING NUMBER

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

68 OF 109
SHEET

62 OF 86

MagSafe DC Power Jack


CRITICAL

J6900

CRITICAL

78048-0573

F6905

M-RT-SM

6AMP-24V

6 PP18V5_DCIN_FUSE

PPDCIN_G3H

7 49 63 64

1206-1
1

PP3V42_G3H

C6905

MIN_LINE_WIDTH=1mm
MIN_NECK_WIDTH=0.20mm
VOLTAGE=18.5V

6 7 26 43 45 46 47 48 53 63 64
73

0.01UF

R6900
5%
1/16W
MF-LF
402

R6929
2.0K

SOT665
TC7SZ08AFEAPE
5

402
MF-LF
1/16W
5%

NOSTUFF

100K

C6908
0.1UF

SMC_BC_ACOK_VCC
1

518S0656

20%
50V
CERM
603

6 ADAPTER_SENSE

VCC

Y
1

SYS_ONEWIRE

BI

PLACE_NEAR=U6901.5:1mm

U6901
B

MAX9940
SC70-5

45

U6900
2

20%
10V
CERM
402

SMC_BC_ACOK

45 46 49 64

EXT 5

INT

NC
3

GND

NC

1-Wire OverVoltage Protection

BIL CONNECTOR
516S0523
CRITICAL

J6955
CPB6312-0101F

F-ST-SM
14

13

84 64 63 48 45 6

BI

SMBUS_SMC_BSA_SDA

PP3V42_G3H

84 64 63 48 45 6
46
45 6

BI

SMBUS_SMC_BSA_SCL

6 SMC_LID_R

TO SMC

SMC_BIL_BUTTON_L

100

10

C6952

NC

12

11

C6953

0.001UF

47PF

10%
50V
CERM
402

5%
50V
CERM
402

5%
50V
CERM
402

NC
C6951

47PF

C6954

SMC_LID

45 46 53

402
5%
MF-LF

3.425V "G3Hot" Supply


Supply needs to guarantee 3.31V delivered to SMC VRef generator

R6961
1
1/16W

16

15

10%
25V
X5R
402

C6955
0.001UF

0.1UF

10%
50V
CERM
402

D6990

BAT30CWFILM
SOT-323
1

P3V42G3H_REF3

PPDCIN_G3H

47

1%
1/3W
MF
805

PPDCIN_S5_P3V42G3H 2
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.3 mm
VOLTAGE=18.5V

C6996
0.1UF

R6995
1.00M

1%
1/8W
MF-LF
2 805

C6990 1
4.7UF

10%
35V
X5R-CERM 2
0805

P3V42G3H_TON

3 TON
4 EN

P3V42G3H_FB

C6991 1

NC

1 REF

353S2776

10%
2 16V
X5R
402-1

BYP 9

PM6640

DFN

CRITICAL

CRITICAL

33UH-20%-0.44A-0.455OHM

THRM
GND PAD
5

1UF

10%
25V
X5R 2
603-1

U6990

8 VCC
2 FB

REF3 10

R6990
64 63 49 7

PPVIN_G3H_P3V42G3H
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.3 mm
VOLTAGE=18.5V

L6995

SW 6

P3V42G3H_SW
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE

11

PPBUS_G3H

VIN 7

50 49 40 36 8 7 6
77 64

PP3V42_G3H

6 7 26 43 45 46 47 48 53 63 64
73

Vout = 3.425

D52LC-SM

DIDT=TRUE

300mA max output

C6994 1

f = 470 kHz

0.1UF

10%
16V 2
X5R
402-1

C6999
22UF

20%
6.3V
2 X5R-CERM-1
603

518-0375

BATTERY CONNECTOR

CRITICAL

J6950
BAT-K90-K91-K92
M-RT-TH

1
2
3

5
6
7

SMBUS_SMC_BSA_SCL

SMBUS_SMC_BSA_SDA

D6950
1

8
9
10
11

6
45 48 63 64 84

CRITICAL

64 6 PPVBAT_G3H_CONN

C6950

10%
25V
X5R
402

C6960

RCLAMP2402B

10%
25V
X5R
603-1

R6950

SYNC_MASTER=JACK_K90I

5%
1/16W
MF-LF
402

DC-In & Battery Connectors


DRAWING NUMBER

Apple Inc.

12
13

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=08/20/2010

PAGE TITLE

10K

SC-75

1UF

0.1UF

SHLD_PIN
SHLD_PIN
SHLD_PIN
SHLD_PIN

6 45 48 63 64 84

6 SYS_DETECT_L

P1
P2
P3
P4
P5
P6
P7
P8
P9

BRANCH

PAGE

69 OF 109
SHEET

63 OF 86

Inrush Limiter

Q7080

AON6405L

AON6405L

DFN5X6

PPDCIN_G3H

R7085

CHGR_AGATE_DIV

R7080

CHGR_SGATE_DIV

20

SMC_RESET_L

IN

5% 48
1/16W84
MF-LF48
402 84

1%
1/16W
MF-LF
2 402

45 6
63
45 6
63

BI

73

IN

IN

Float CELL for 1S

CHGR_ACIN

R7011
9.31K

1%
1/16W
MF-LF
2 402

R7015

84

100K

84

1%
1/16W
MF-LF
2 402

BATT_2S

R70131

1K

1%
1/16W
MF-LF
402 2

CHGR_ICOMP
CHGR_VCOMP
CHGR_VNEG
CHGR_CSO_P
CHGR_CSO_N

5
7
8
18
17

C7050

C7015

10%
2 16V
X5R
402

330PF

85

CHGR_CSI_R_N

Q7080

CRITICAL

SI7149DP

Q7085

CRITICAL

10

R7020
0.02

4 2

0.5%
1W
MF
0612-1

PPDCIN_G3H_CHGR
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=18.5V

C7021
0.1UF

10%
2 25V
X5R
402

CHGR_BOOT_R

U7000

26
1
28 84
27 84

CHGR_SGATE
CHGR_AGATE
CHGR_CSI_P
CHGR_CSI_N

25
24
23

CHGR_BOOT
CHGR_UGATE
CHGR_PHASE

21

CHGR_LGATE

R7025
0

5%
1/16W
MF-LF
402 2

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE

CHGR_BGATE
CHGR_AMON
CHGR_BMON
SMC_BC_ACOK

16
9
15
14

C7025

Q7030

0.22UF

10%
10V
2 CERM
402

Max Current = 8A
(L7030 limit)
f = 400 kHz

OMIT
CRITICAL

D
G

RJK03E1DNS
HWSON-8

C7036
1UF

10%
2 25V
X5R
603-1

C7037

0.001UF

10%
2 50V
X7R
402

10%
2 25V
X5R
603-1

GATE_NODE=TRUE
DIDT=TRUE

REFERENCE DES

RJK03E1DNS

Q7030

CRITICAL

376S0966

RJK03E1DNS

Q7035

CRITICAL

DIDT=TRUE

GATE_NODE=TRUE
DIDT=TRUE

CRITICAL

L7030

50

OUT

50

OUT

45 46 49 63

TO SYSTEM

F7040
8AMP-24V

PPBUS_G3H

6 7 8 36 40 49 50 63 77

IHLP4040DZ-SM
1206

180
5%
1/10W
MF-LF
603 2

OMIT
CRITICAL

Q7035

CHGR_PHASE_RC

RJK03E1DNS

DIDT=TRUE

PPVBAT_G3H_CHGR_REG
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=12.6V

NO STUFF
1

C7039

10%
2 50V
CERM
402

CRITICAL
1

CRITICAL
BATT_3S

Q7055

1
3

470PF

(CHGR_CSO_N)

85 50

5%
2

OMIT

PPVBAT_G3H_CHGR_R
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=12.6V

C7056
0.1UF

10%
16V 2
X5R
402-1

C7057

3 S
2
1

0.01uF

10%
16V
CERM 2
402

PPVBAT_G3H_CONN
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=12.6V

6 63

G
4

CHGR_CSO_R_P

1/16W MF-LF 402

85 50

5%

(PPVBAT_G3H_CHGR_R)

TO/FROM BATTERY

SYM-VER-2

2
4

AON6403L
DFN5X6

0.5%
1W
MF
0612-3

10%
25V
X5R 2
603-1
1

CRITICAL

0.01

1UF

2.2

0.001UF

R7050

C7055

R7051
R7052

C7045

10%
50V
2 X7R
402

20%
2 25V
POLY-TANT
CASE-D2-SM

PLACE_NEAR=U7000.29:1mm
PLACE_NEAR=U7000.22:1mm

(CHGR_CSO_P)

C7040
22UF

(GND)

10%
50V
2 CERM
402

BOM OPTION

NO STUFF

XW7000
SM

C7016

CRITICAL

R70391

OUT

QTY

4.7UH-9.5A
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm

353S2929

DESCRIPTION

376S0966

CHGR_VNEG_R
1

C7035
1UF

20%
2 25V
POLY-TANT
CASE-D2-SM

CRITICAL

S
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm 1 2 3

1 2 3

1%
1/16W
MF-LF
402 2

22UF

PLACE_NEAR=U7000.25:2mm

470PF

3.01K

C7031

PART NUMBER

R7016

CRITICAL
1

C7030

20%
2 25V
POLY-TANT
CASE-D2-SM

HWSON-8

CRITICAL
1

22UF

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

CHGR_DCIN

5%
2 50V
COG
402

10%
25V 2
X5R
402

VDDP

VHST CRITICAL DCIN


SMB_RST_N
SGATE
SCL
AGATE
TQFN
SDA
CSIP
VFRQ
CSIN
CELL
BOOT
ACIN
UGATE
PHASE
ICOMP
VCOMP
LGATE
VNEG
BGATE
CSOP
20V/V AMON
CSON
36V/V BMON
(OD) ACOK

1UF

CHGR_VCOMP_R

SI7149DP

20

VDD
12
13
11
10
4
6

CHGR_RST_L
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
CHGR_VFRQ
CHGR_CELL

ISL6259

30.1K

22 PGND

R7010

5%
1/16W
MF-LF
2 402

0.1UF

10%
10V 2
X5R
402

100K

64

C7022

1UF

R7000
1

C7001

R7002

GND_CHGR_AGND

47
45
46

R7022

3 1

5%
1/16W
MF-LF
402

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5.1V

5%
1/16W
MF-LF
402

(AGND)
29 THRM_PAD

CHGR_CSI_R_P

PP5V1_CHGR_VDDP

19

1K

4.7

10%
10V 2
X5R
402

1%
1/16W
MF-LF
402 2

NO STUFF

1UF

R70121

CRITICAL
85

0.047UF

R7001

5%
1/16W
MF-LF
402

C7020

10%
2 10V
CERM
402

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5.1V

10

30mA max load

C7002 1

BATT_3S

376S0845
376S0845

BOM OPTION

R7021

(CHGR_DCIN)

5%
1/16W
MF-LF
402

PP5V1_CHGR_VDD

CRITICAL

(CHGR_SGATE)

R7005
CHGR_DCIN_D_R

Divider sets ACIN threshold at 13.55V

63 53 48 47 46 45 43 26 7 6
73

Q7055

(CHGR_AGATE)

PP3V42_G3H

SI7137DP

5%
1/16W
MF-LF
2 402

SOT-323
1

Input impedance of ~40K meets


sparkitecture requirements

DESCRIPTION

62K

1%
1/16W
MF-LF
402 2

BAT30CWFILM

ACIN pin threshold is 3.2V, +/- 50mV

CRITICAL

R7081

332K

QTY

R7086
D7005

5%
1/16W
MF-LF
2 402

REFERENCE DES

376S0761

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.3 mm

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.3 mm
1

CRITICAL

PART NUMBER

G
4

PPDCIN_G3H_INRUSH
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=18.5V

100K

1%
1/16W
MF-LF
402

10%

D
5

470K

0.1UF

2 25V
X5R

402

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.3 MM
VOLTAGE=18.5V

C7085

OMIT
PPDCIN_G3H_INRUSH_FET

DFN5X6

OMIT

CRITICAL

Q7085
3 2 1

63 49 7

Reverse-Current Protection

CRITICAL

FROM ADAPTER

3 2 1

CHGR_CSO_R_N

1/16W MF-LF 402

(PPVBAT_G3H_CHGR_R)
(CHGR_BGATE)

C7042

C7011 1

0.068UF

0.01UF

10%
2 10V
CERM
402

10%
16V
CERM 2
402

C7000

C7005 1

1UF

0.22UF

10%
2 10V
X5R
402-1

C7026 1
0.001UF

20%
25V
X5R 2
603
64

10%
50V
CERM 2
402

TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

CRITICAL

BOM OPTION

R7050

CRITICAL

BATT_2S

GND_CHGR_AGND

TABLE_5_ITEM

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

107S0129

RES,5MOHM,1%,1W,0612,4-TERM

SYNC_MASTER=JACK_K90I

SYNC_DATE=10/11/2010

PAGE TITLE

PBus Supply & Battery Charger


DRAWING NUMBER

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

K6 NOTES : L7030 CHANGED BACK TO K24 IND DUE TO LAYOUT

BRANCH

PAGE

70 OF 109
SHEET

64 OF 86

System Agent Power Supply


D

70 69 68 67 50 7
72 70 68 54 52 47 42 22 7 6
77 73

PPBUS_S5_HS_COMPUTING_ISNS
PP5V_S0
VCCSAS0_BOOT_RC

R71011 C7101
10UF

2.2

20%
2 10V
X5R
603

5%
1/16W
MF-LF
2 402

VCC

PVCC

ISL95870AH
PVCCSA_EN

IN

R7146
113K

1%
1/16W
MF-LF
2 402

73

UGATE 17

VCCSAS0_SREF

PHASE 16

VCCSAS0_LL

VCCSAS0_VO

12 VO

VCCSAS0_OCSET

11 OCSET
14

VCCSAS0_FSEL

R7147
1

C7103

C7105
1000PF

5%
2 25V
NP0-C0G
402

R7148
47.5K

1%
1/16W
MF-LF
2 402

R7103

10%
2 16V
CERM-X5R
402

C7102

0.022UF

5%
1/16W
MF-LF
2 402

2.2UF

10%
16V 2
X5R
603

13

LGATE 1

CRITICAL

CRITICAL

Q7100
SIZ700DT
1

R7140

CRITICAL

POWERPAIR-6X3.7

0.001

L7100

1.0UH-7.7A
8

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE

2
FDV0630H-SM

PPVCCSA_S0_REG_R

1
MIN_LINE_WIDTH=0.6 mm 3
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V

1%
1W
MF-1
0612

PPVCCSA_S0_CPU
2
4

6 7 12 15

6A Max Output
f = 300 kHz

PGOOD

VCCSAS0_DRVL

RTN

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE

FSEL

8 SET0
9 SET1
6 VID0
5 VID1

PGND

R7141

85

VCCSAS0_CS_P

85

VCCSAS0_CS_N

1K

1%
1/16W
MF-LF
402 2

CPU_VCCSA_VID<1>

C7140
1000PF
1

5%
25V
NP0-C0G
402
IN

1000PF

C
2

12

C7122

5%
2 25V
NP0-C0G
402

10%
25V 2
X5R
402

GND

VCCSAS0_SET0
VCCSAS0_SET1

10%
2 16V
X5R
402

VCCSAS0_DRVH

10 FB

1%
1/16W
MF-LF
2 402

BOOT 18

VCCSAS0_FB

140K

UTQFN
CRITICAL

SREF

1UF

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE

PVCCSA_PGOOD

OUT

15 EN

R7130

73

CPU_VCCSASENSE

0.1UF

20%
16V 2
POLY
B1A-SM

C7130

VCCSAS0_VBST

U7100
12

C7121

C7120 1

39UF-0.027OHM
2.2

20

19

PLACE_NEAR=Q7100.2:1.5mm

CRITICAL

1
1

5%
1/10W
MF-LF
603 2

PP5V_S0_VCCSAS0_VCC
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE

R7142
1K

1%
1/16W
MF-LF
2 402

(VCCSAS0_OCSET)
(VCCSAS0_VO)

SYNC_MASTER=JACK_K90I

SYNC_DATE=08/19/2010

PAGE TITLE

System Agent Supply


DRAWING NUMBER

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

71 OF 109
SHEET

65 OF 86

5V_S3/3.3V_S5 POWER SUPPLY


D

D
VOUT = (2 * RA / RB) + 2

VOUT = (2 * RC / RD) + 2

<RA>
R7267

<RB>
R7268

15.0K

XW7203
SM
2

5V_S3_VFB_XW7203

<RD>
R7269

10K

1%
1/16W
MF-LF
402
1

<RC>
R7270

10K

6.49K

1%
1/16W
MF-LF
402

1%
1/16W
MF-LF
402
1

1%
1/16W
MF-LF
402

XW7204
SM

3V3S5_VFB_R7270

PLACE_NEAR=L7260.1:1 MM

PLACE_NEAR=L7220.2:1 MM

XW7205
SM
73

P5V3V3_REG_EN

PLACE_NEAR=C7251.1:1 MM

C
66 50 7

PPBUS_S5_HS_OTHER_ISNS

R7273

XW7202

SM
2

C7272

100K
5%
1/16W
MF-LF
402

1UF

10%
2 25V
X5R
603-1

PLACE_NEAR=C7291.1:1 MM

P5VP3V3_REG3
66 50 7

PPBUS_S5_HS_OTHER_ISNS
P5VP3V3_VREF

CRITICAL

603-1

C7260

0.1UF
10%
16V
X5R
402

OMIT
D

CRITICAL

Q7260

RJK03E1DNS

R7260

P5VS3_VBST_R

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

P5VS3_DRVH

MIN_LINE_WIDTH=0.6 MM DIDT=TRUE
MIN_NECK_WIDTH=0.2 MM

3 2 1

OMIT
D

CRITICAL
10UF

0.001UF
2

C7290

20%
10V
2 X5R
603

20%
50V
CERM
402

U7200

DRVH1

P5VS3_LL

20

P5VS3_DRVL

19

DRVL1

P5VS3_VO1

24

VO1

P5VS3_VFB

P5VS3_ENTRIP

LL1

C7291

RJK03E0DNS

17 PP5V_S5

VBST2

DRVL2

VFB1
ENTRIP1

R7220

R7271

MIN_LINE_WIDTH=0.6 MM
MM

3 2 1

VFB2

P3V3S5_VFB

ENTRIP2

P3V3S5_ENTRIP

18
23

EN0
GND THRM_PAD

WPAK
S1/D2

CRITICAL

PWM FREQ. = 375 KHZ


MAX CURRENT = 7.45A

L7220

4.7UH-5.5A
6

DIDT=TRUE

G2

IHLP2525CZ

S2

PP3V3_S5

74 76 85
6 7 8 17 19 20 22 23
24 26 30 46 56 72 73

CRITICAL

NC

13 5V3V3_REG_EN

C7273

C7251

1%
1/16W
MF-LF
402

C7250
10UF

150UF

75K

10UF

20%
6.3V
2 X5R
603

R7272

2 X5R

603

C7253
0.001UF

20%
6.3V

20%
6.3V
POLY
B1A-SM

20%
50V
CERM
402

XW7201
SM

Q7221

PLACE_NEAR=U7200.25:1 MM

SSM6N37FEAPE

P5VS3_EN_L

Q7220

G1

P5V3V3_PGOOD

SOT563

IN

20%
50V
CERM
402

RJK0384DPA

DIDT=TRUE

P3V3S5_VO2

VOLTAGE=0V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

73

CRITICAL

D1

DIDT=TRUE

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

VO2

X5R

1 402

DIDT=TRUE

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

12 P3V3S5_DRVL

VCLK

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

11 P3V3S5_LL

PGOOD

0.1UF

2 P3V3S5_VBST_R 2

DIDT=TRUE

GND_5V3V3S5_SGND

MIN_NECK_WIDTH=0.2
10 P3V3S5_DRVH

1%
1/16W
MF-LF
2 402

C7220 10%
16V

402 5% 1/16W MF-LF


P3V3S5_VBST

20%
16V
POLY
B1A-SM

88.7K

CRITICAL

72 54 7
VREG5

LL2

C7242
0.001UF

39UF-0.027OHM

10%

DIDT=TRUE

HWSON-8

20%
6.3V
ELEC
D1A-SM

VREG3

C7240

1UF
603-1

DRVH2

QFN

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

Q7261

220UF
2

CRITICAL

15

C7293

VBST1

C7241

25V
2 X5R

VREF

TONSEL

DIDT=TRUE

21

PP5V_S3
1

22

PCMB104E4R7-SM

CRITICAL
72 67
43 42 32 30 7 6
61 60 59 57 46 44

P5VS3_VBST

MIN_LINE_WIDTH=0.6 MM DIDT=TRUE
MIN_NECK_WIDTH=0.2 MM

L7260

4.7UH-13A-15MOHM

VIN
14
SKIPSEL

10%
10V
2 CERM
402

MIN_LINE_WIDTH=0.6 MM DIDT=TRUE
MIN_NECK_WIDTH=0.2 MM

MAX CURRENT = 12.947A


PWM FREQ. = 300 KHZ

0.22UF

402 5% 1/16W MF-LF

HWSON-8

C7271

1 CRITICAL

2 X5R

10%
25V

20%
16V
POLY
B1A-SM

20%
10V
2 CERM
603

1UF

39UF-0.027OHM

20%
50V
CERM
402

PPBUS_S5_HS_OTHER_ISNS

C7270
1UF

C7281
3

0.001UF
2

C7280

25

16

C7282

TPS51125

73

Q7221

SSM6N37FEAPE
SOT563

PART NUMBER

REFERENCE DES

CRITICAL

376S0966

QTY
1

DESCRIPTION
RJK03E1DNS

Q7260

CRITICAL

376S0895

RJK03E0DNS

Q7261

CRITICAL

BOM OPTION

P3V3S5_EN_L
73

IN

SYNC_MASTER=JACK_K90I

SYNC_DATE=10/04/2010

PAGE TITLE

5V/3.3V SUPPLY
DRAWING NUMBER

Apple Inc.
SEPERATED MASTER PGOOD FOR BOTH 5V AND 3V3.

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

NOTICE OF PROPRIETARY PROPERTY:

SIZE

REVISION

BRANCH

PAGE

72 OF 109
SHEET

66 OF 86

PPBUS_S5_HS_COMPUTING_ISNS

70 69 68 65 50 7

TABLE_ALT_HEAD

CRITICAL
1

CRITICAL
1

C7330

39UF-0.027OHM

72 67 30 29 27 7 6

20%
2 16V
POLY
B1A-SM

PP1V5_S3

CRITICAL

C7331

39UF-0.027OHM

20%
2 16V
POLY
B1A-SM

C7332

1UF
2

C7333
0.001UF

10%
25V
X5R
603-1

10%
50V
X7R
402

PART NUMBER

ALTERNATE FOR
PART NUMBER

128S0299

128S0218

ALL

128S0093

128S0218

ALL

C7334

BOM OPTION

REF DES

COMMENTS:
TABLE_ALT_ITEM

33UF

20%
2 16V
POLY-TANT
CASED2E-SM

TABLE_ALT_ITEM

NO STUFF
59 57 46 44 43 42 32 30 7 6
72 66 61 60

PP5V_S3

C7301

10UF

C7300

20%
10V
X5R
603

20%
10V
X5R
603

PLACE_NEAR=U7300.2:1mm

10UF

CRITICAL

Q7330

(DDRREG_DRVH)

PLACE_NEAR=U7300.12:1mm

CSD58858Q3

MIN_LINE_WIDTH=0.6 mm

3.3X3.3-QFN-COMBO

MIN_NECK_WIDTH=0.17 mm

VLDOIN

R7325

402
5%

DDRREG_VBST
MIN_NECK_WIDTH=0.17 mm

12

MEMVTT_EN
DDRREG_EN

IN

VTT Enable
VDDQ/VTTREF Enable

DDRREG_1V8_VREF

C7315

31 DDRREG_FB

16

U7300

S3
S5

TPS51916

PLACE_NEAR=U7300.6:1mm

1%
1/16W
MF-LF
402

VREF

REFIN

DDRREG_MODE

19

DDRREG_TRIP

18

MODE
TRIP

1%
1/16W
MF-LF
402

PLACE_NEAR=U7300.8:5mm

0.01UF
2

10%
16V
CERM
402

R7317
200K

PLACE_NEAR=U7300.8:1mm

1%
1/16W
MF-LF
402

10

100K

C7316

DDRREG_VBST_RC

14

DDRREG_DRVH

13

DDRREG_LL

MIN_LINE_WIDTH=0.6 mm

GATE_NODE=TRUE

DIDT=TRUE

DIDT=TRUE

CRITICAL

0.88UH-20%-19A-2.3MOHM
1

20

TP_DDRREG_PGOOD

DDRREG_VDDQSNS
PP0V75_S0_DDRVTT

CRITICAL

OUT

PPVTTDDR_S3
10mA max load

D
4

CRITICAL

20%
6.3V
X5R
603

R7318
95.3K

C7360, C7361 close


1

10%
10V
CERM
402

C7341

OMIT

20%
2V
TANT
CASE-B4-SM

1 2 3

C7346
0.001UF

2
1

C7345

10%
50V
X7R
402

10UF

270UF

20%
6.3V
X5R
603

20%
6.3V
X5R
603

XW7301
SM
1

PLACE_NEAR=L7330.2:1mm

PLACE_NEAR=C3101.1:3mm

to memory
(DDRREG_VDDQSNS)
MIN_LINE_WIDTH=0.2 mm

0.22UF

3.3X3.3-QFN-COMBO

C7361

20%
2V
TANT
CASE-B4-SM

CRITICAL

10UF

PLACE_NEAR=C3101.1:1mm

C7350

CSD58858Q3

CRITICAL

10UF

MIN_NECK_WIDTH=0.17 mm

C7360

SM

CRITICAL

Q7335

MIN_LINE_WIDTH=0.6 mm

VTT THRM
GND PAD

6 7 27 29 30 67 72

Vout = 1.5V
14.1A max output
(Q7335 limit)
f = 400 kHz

C7340
270UF

(DDRREG_DRVL)

SM

XW7300

XW7360

PP1V5_S3

MIN_NECK_WIDTH=0.17 mm

DIDT=TRUE

MPCG1040LR88-SM

MIN_LINE_WIDTH=0.6 mm

GATE_NODE=TRUE

PLACE_NEAR=U7300.19:3mm PLACE_NEAR=U7300.18:3mm

MIN_NECK_WIDTH=0.17 mm

PART NUMBER

PLACE_NEAR=U7300.21:1mm

GND_DDRREG_SGND
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=0V

L7330

1 2 3

10%
25V
X5R
402
(DDRREG_LL)

DDRREG_DRVL

11

1%
1/16W
MF-LF
2 402

PLACE_NEAR=C7361.1:3mm

VTTREF

MIN_NECK_WIDTH=0.17 mm

DDRREG_VTTSNS

PGND GND

R7316

MIN_LINE_WIDTH=0.6 mm

SWITCH_NODE=TRUE

DRVL
CRITICAL
PGOOD
VDDQSNS
VTT
VTTSNS

PLACE_NEAR=U7300.8:5mm

15

OMIT

0.1UF

MF-LF
1/16W

QFN

20.0K

0.1UF
10%
16V
X5R
402

R7315

17

VBST
DRVH
SW

21

IN

30 8
73 43

V5IN

C7325

QTY

DESCRIPTION

REFERENCE DES

CRITICAL

376S0790

CSDS58858Q3

Q7330

CRITICAL

376S0928

FDMC2514SDC

Q7335

CRITICAL

BOM OPTION

SYNC_MASTER=JACK_K90I

SYNC_DATE=10/11/2010

PAGE TITLE

1.5V DDR3 Supply


DRAWING NUMBER

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

73 OF 109
SHEET

67 OF 86

PART NUMBER

QTY

353S3259

DESCRIPTION

REFERENCE DES

CRITICAL

U7400

CRITICAL

IC,MAX15092,3+1PH CPU REG,IMVP7,5X5QFN40

BOM OPTION

Need symbol to be re-drawn to clean up this page


PP5V_S0

6 7 22 42 47 52 54 65 70 72 73
77

D
R7401
10

P5V_S0_CPUIMVP_VDD

2
5%
1/16W
MF-LF
402

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V

PP1V05_S0

PPBUS_S5_HS_COMPUTING_ISNS

7 50 65 67 69 70

23 22 20 17 16 14 12 10 9 7 6
73 70 45 40 36

C7401

2.2UF

R7479 1

C7403

2.2UF

20%
10V
X5R-CERM
402

20%
10V
X5R-CERM
402

130

15

PLACE_NEAR=U7400.24:2mm
PLACE_NEAR=U7400.15:2mm

PLACE_NEAR=U7400.16:2mm

24

PLACE_NEAR=U7400.18:2mm

1%
1/16W
MF-LF
402

VDDB

40

VCC

1%
1/16W
MF-LF
402

C7402
2.2UF

VDDA

54.9

R7480

20%
10V
X5R-CERM
402

R7406
300
1

U7400

R7402

MAX17511

NC

31

39
78 46 10

C
78 12

IN

R7466

5.76K

R7464

CRITICAL

18
17

1%
1/16W
MF-LF
402

CPUIMVP_NTC
CPUIMVP_NTCG

33

CPUIMVP_SLEW

32

34

CPUIMVP_IMAXA
CPUIMVP_IMAXB
1

R7462
154K

1%
1/16W
MF-LF
2 402

29
30

R7467
100KOHM-1%-100MW

0603

0603
2

R7465
200K

1%
1/16W
MF-LF
2 402

R7463
107K

1%
1/16W
MF-LF
2 402

CSPAAVE
CSNA
FBA

VDIO
CLK
ALERT*

CSPA2
BSTA2
DHA2
LXA2
DLA2

THERMA
THERMB
SR

BSTB
DHB
LXB
DLB

IMAXA
IMAXB

R7460
215K

1%
1/16W
MF-LF
2 402

CSPB1
CSNB
FBB
GNDSA

CRITICAL

R7469

16

EN

100KOHM-1%-100MW

CPU_VIDSOUT
CPU_VIDSCLK
CPU_VIDALERT_L

200K

1%
1/16W
MF-LF
2 402
2

CPUIMVP_VR_ON

NO STUFF

10

R7461

CPUIMVP_TON

20

CPUIMVP_BOOT1
CPUIMVP_UGATE1
CPUIMVP_PHASE1
CPUIMVP_LGATE1
CPUIMVP_ISUM1_P

22
21
23
36

CPUIMVP_ISUM
CPUIMVP_ISUM_N
CPUIMVP_FBA

35
37
4

28
26
27
25

13
12
14

CPUIMVP_ISUMG_P
CPUIMVP_ISUMG_N
CPUIMVP_FBB

8
9
6

OUT

69

OUT

69

NO STUFF

OUT

69

C7408

300

CPUIMVP_ISNS2_P
IN

49 69 85

5%
1/16W
MF-LF
402

69

C7404
0.0022UF

10%
2 50V
CERM
402

68

CPUIMVP_ISUM_R

10%
10V
X5R-CERM
0402

C7409

69

OUT

69

OUT

69

OUT

69

OUT

69

OUT

69

OUT

69

OUT

69

C7405
0.0022UF

OUT

5%
1/16W
MF-LF
402

NO STUFF

R7409
1

69

5%
50V
NP0-C0G
402

10%
50V
2 CERM
402

OUT

R7410

470PF
1

OUT

40.2K

1%
1/16W
MF-LF
402

69

OUT

69 85

OUT

69 85

NO STUFF
68

C7407

0.0022UF

C7418

XW7400

1%
1/16W
MF-LF
2 402

49 69 85

10%
2 50V
CERM
402
NO STUFF

137K

CPUIMVP_ISNS1_P
IN

0.039UF

CPUIMVP_BOOT1G
CPUIMVP_UGATE1G
CPUIMVP_PHASE1G
CPUIMVP_LGATE1G

11

R7407

69

OUT

CPUIMVP_ISUM2_P
CPUIMVP_BOOT2
CPUIMVP_UGATE2
CPUIMVP_PHASE2
CPUIMVP_LGATE2

38

1%
1/16W
MF-LF
402

OUT

THRM
PAD

1%
1/16W
MF-LF
2 402

IN

CPUIMVP_PGOOD
CPUIMVP_AXG_PGOOD

90.9K2
1

41

5.76K

IN

78 12

OUT

R7468

78 12

OUT

73

19

IN

26

TON
DRVPWMA
OMIT
CRITICAL
BSTA1
CSPA3
DHA1
VRHOT*
LXA1
DLA1
POKA
CSPA1
POKB

GNDSB

73

OUT

CPU_PROCHOT_L

QFN

5%
1/16W
MF-LF
402

SM
2

NO STUFF
1

C7419

NO STUFF

NO STUFF
1

C7414

C7415

NO STUFF
1

C7416

100PF

100PF

100PF

100PF

100PF

5%
50V
CERM
402

5%
50V
CERM
402

5%
50V
CERM
402

5%
50V
CERM
402

5%
50V
CERM
402

GND_CPUIMVP_SGND
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

C7440
1000PF

5%
25V
NP0-C0G
402

R7440

CPU_AXG_SENSE_R
1

IN

12 78

R7412

5%
1/16W
MF-LF
402

C7441
1000PF

CPU_AXG_SENSE_N

VOLTAGE=0V

5%
25V
NP0-C0G
402

68

CPUIMVP_FBA

VOLTAGE=0V

OMIT
1

C7442

OMIT
1

C7443

NOSTUFF

NOSTUFF

NONE
NONE
NONE
402

NONE
NONE
NONE
402

10

8.45K2

5%
25V
NP0-C0G
402

R7413

CPUIMVP_FBA_R

10
1

1%
1/16W
MF-LF
402

R7441

CPU_VCCSENSE_R

C7412
1000PF

10
1

CPU_VCCSENSE_N

IN

12 78

C7422

5%
1/16W
MF-LF
402

CPU_VCCSENSE_P

IN

12 78

CPU_AXG_SENSE_P IN

12 78

5%
1/16W
MF-LF
402
1

1000PF
5%
25V
NP0-C0G
402

R7422
68

CPUIMVP_FBB

8.66K2
1

R7423

CPUIMVP_FBB_R

1%
1/16W
MF-LF
402

10
1

2
5%
1/16W
MF-LF
402

SYNC_MASTER=JACK_K90I

SYNC_DATE=10/14/2010

PAGE TITLE

CPU IMVP7 & AXG VCore Regulator


DRAWING NUMBER

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

74 OF 109
SHEET

68 OF 86

70 69 68 67 65 50 7

PPBUS_S5_HS_COMPUTING_ISNS
THESE TWO CAPS ARE FOR EMC

CRITICAL

C7513

CRITICAL
1

82UF
20%

2 16V

R7511
0

68

IN

68

4.7

10%
10V
CERM
402

POLY-TANT
CASED2E-SM

376S0906
CRITICAL

R7510

CPUIMVP_UGATE1_R

CRITICAL

CSD58864Q5D

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

SON5X6

TG

VIN

VSW

TGR

L7510
PPVCORE_S0_CPU_PH1_L

DIDT=TRUE

NOSTUFF

R7512
2.2

BG

5%
1/10W
MF-LF
603

DIDT=TRUE

GATE_NODE=TRUE

CPUIMVP_ISNS1_N
CPUIMVP_ISNS1_P

R7513

46.4

1%
1/16W
MF-LF
402 2

CPUIMVP_PH1_SNUB
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.25V

DIDT=TRUE

NOSTUFF
1

PPVCORE_S0_CPU

1
3
85 49

152S1271

PGND

2
4

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.25V

FCUL1040-SM

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.25V

SWITCH_NODE=TRUE
5

1%
1W
MF
0612

PPVCORE_S0_CPU_PH1

SWITCH_NODE=TRUE

DIDT=TRUE

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

0.00075

0.36UH-20%-35A-0.00081OHM

DIDT=TRUE

GATE_NODE=TRUE

CPUIMVP_LGATE1

IN

20%

2 16V

CRITICAL

CPUIMVP_PHASE1
MIN_LINE_WIDTH=1.5 MM
MIN_NECK_WIDTH=0.2 MM

68

33UF

10%
50V
X7R
402

C7540

C7511
0.22UF

DIDT=TRUE

5%
1/16W
MF-LF
402

GATE_NODE=TRUE

IN

10%
50V
X7R
402

C7519
0.001UF

Q7510

R7515

DIDT=TRUE

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

10%
16V
X5R
402

C7518
0.001UF

D
1

CPUIMVP_BOOT1

CPUIMVP_UGATE1

10%
16V
X5R-CERM
0805

C7517
1UF

5%
1/16W
MF-LF
402 2

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM

10%
16V
X5R-CERM
0805

C7516
10UF

DIDT=TRUE

D
IN

20%
16V
POLY
B1A-SM

CRITICAL

CRITICAL
1

C7515
39UF-0.027OHM 10UF

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM

PHASE 1

68

ELEC
B6S-SM

CPUIMVP_BOOT1_RC

CRITICAL
1

C7514

70 69 68 67 65 50 7

49 68 85

1%
1/16W
MF-LF
402

CPUIMVP_ISUM_N

10%
50V
CERM
402

IN

68 69

NO STUFF

C7571
0.0022UF

10%
50V
2 CERM
402

OUT

R7514
10

C7512
0.001UF

6 7 9 12 14 49 69

CPUIMVP_ISUM1_P

IN

68

PPBUS_S5_HS_COMPUTING_ISNS
THESE TWO CAPS ARE FOR EMC

CRITICAL

CPUIMVP_BOOT2_RC

68

IN

4.7

10%
10V
CERM
402

C7527
1UF
10%
16V
X5R
402

C7528
0.001UF
10%
50V
X7R
402

C7529
0.001UF

C7530
33UF

10%
50V
X7R
402

20%

2 16V

POLY-TANT
CASED2E-SM

376S0906

CRITICAL

CPUIMVP_UGATE2_R

CRITICAL

R7520

CRITICAL

SON5X6

TG

VIN

VSW

GATE_NODE=TRUE
4

0.00075

L7520

TGR

PPVCORE_S0_CPU_PH2_L

DIDT=TRUE

PPVCORE_S0_CPU_PH2

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.25V

SWITCH_NODE=TRUE

1
3

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.25V

FCUL1040-SM

SWITCH_NODE=TRUE
8

CPUIMVP_LGATE2

1%
1W
MF
0612

0.36UH-20%-35A-0.00081OHM

DIDT=TRUE

CPUIMVP_PHASE2

IN

10%
16V
X5R-CERM
0805

CSD58864Q5D

MIN_LINE_WIDTH=0.5 MM

MIN_LINE_WIDTH=1.5 MM
MIN_NECK_WIDTH=0.2 MM

68

C7526
10UF

C7521
0.22UF

DIDT=TRUE

5%
MIN_NECK_WIDTH=0.25 MM
1/16W
MF-LF
402
DIDT=TRUE

DIDT=TRUE

IN

10%
16V
X5R-CERM
0805

Q7520

R7525

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

68

CPUIMVP_BOOT2

CPUIMVP_UGATE2

20%
16V
POLY
B1A-SM

C7525

39UF-0.027OHM 10UF

20%
16V
ELEC
B6S-SM

5%
1/16W
MF-LF
402 2

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM

C7524

82UF

CRITICAL

CRITICAL

DIDT=TRUE

R7521
0

IN

CRITICAL

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.25 MM

PHASE 2

68

C7523

CRITICAL

PPVCORE_S0_CPU

2
4
85 49

152S1271

6 7 9 12 14 49 69

CPUIMVP_ISNS2_N
CPUIMVP_ISNS2_P
OUT

BG

49 68 85

DIDT=TRUE

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

GATE_NODE=TRUE

PGND

R7523

Removed snubber with EMCs comment

46.4
1%
1/16W
MF-LF
402 2

R7524
10

1%
1/16W
MF-LF
402

B
CPUIMVP_ISUM_N
NO STUFF

IN

68 69

IN

68

C7572
0.0022UF

10%
50V
2 CERM
402

70 69 68 67 65 50 7

CPUIMVP_ISUM2_P

PPBUS_S5_HS_COMPUTING_ISNS
THESE TWO CAPS ARE FOR EMC

CRITICAL

CPUIMVP_UGATE1G_R
2

DIDT=TRUE

MIN_NECK_WIDTH=0.25 MM
MIN_LINE_WIDTH=0.5 MM

376S0906

GATE_NODE=TRUE

IN

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
68

IN

68

DIDT=TRUE

GATE_NODE=TRUE

CPUIMVP_PHASE1G
MIN_LINE_WIDTH=1.5 MM
MIN_NECK_WIDTH=0.2 MM

68

IN

DIDT=TRUE

TG

SON5X6

4.7

10%
16V
X5R-CERM
0805

10%
16V
X5R
402

C7558
0.001UF
10%
50V
X7R
402

C7559
0.001UF
10%
50V
X7R
402

C7560
33UF
20%

2 16V

POLY-TANT
CASED2E-SM

R7550

CRITICAL

VIN

VSW

CPUIMVP_VSWG

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM

0.00075

L7550

TGR

SWITCH_NODE=TRUE
DIDT=TRUE

2
FCUL1040-SM

NOSTUFF
1

152S1271

R7552
2.2

1%
1W
MF
0612

PGND

NOSTUFF
1

SWITCH_NODE=TRUE
DIDT=TRUE

GATE_NODE=TRUE

C7552
0.001UF

1
3

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.05V
85 49

CPUIMVP_ISNS1G_P

2
4

1%
1/16W
MF-LF
402 2

PPVCORE_S0_AXG

6 7 9 12 15 49

CPUIMVP_ISNS1G_N

85 49

46.4

CPUIMVP_AXG_SNUB

5%
1/16W
MF-LF
402

PPVCORE_S0_AXG_R

R75531

5%
1/10W
MF-LF
2 603

BG

CPUIMVP_LGATE1G
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

10%
16V
X5R-CERM
0805

C7557
1UF

0.36UH-20%-35A-0.00081OHM

R7555

DIDT=TRUE

IN

CPUIMVP_UGATE1G
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.5 MM

CPUIMVP_BOOT1G

20%
16V
POLY
B1A-SM

68

0.22UF
10%
10V
CERM
402

20%
16V
ELEC
B6S-SM

C7556
10UF

Q7550

C7551

82UF

CRITICAL

CRITICAL
1

CSD58864Q5D

DIDT=TRUE

5%
1/16W
MF-LF
402

CRITICAL
1

C7555
39UF-0.027OHM10UF

C7554

CRITICAL

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.25 MM

R7551
0

CRITICAL

CPUIMVP_BOOT1G_RC

AXG PHASE

C7553

R7554
10
1%
1/16W
MF-LF
402
SYNC_MASTER=JACK_K90I

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.25V

CPUIMVP_ISUMG_N

10%
50V
CERM
402

CPU IMVP7 & AXG VCore Output


IN

0.001UF

CPUIMVP_ISUMG_P

SIZE

D
REVISION

C7574

NOTICE OF PROPRIETARY PROPERTY:

10%
50V
2 X7R
402

DRAWING NUMBER

68 85

Apple Inc.
1

SYNC_DATE=09/03/2010

PAGE TITLE

DIDT=TRUE

IN

68 85

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

75 OF 109
SHEET

69 OF 86

CPU VCCIO (1.05V S0) Regulator

69 68 67 65 50 7
72 68 65 54 52 47 42 22 7 6
77 73

PPBUS_S5_HS_COMPUTING_ISNS
PP5V_S0
CPUVCCIOS0_VBST_RC
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

R7601

10UF

2.2
5%
1/16W
MF-LF
402 2

VCC
1

R7644

73 71

73

R7605

2.74K
1%
1/16W
MF-LF
402

IN

CPUVCCIOS0_FB

FB

CPUVCCIOS0_SREF

SREF

EN

CRITICAL

C7602

CRITICAL

C7604

47PF
5%
50V
CERM
402

C7605

47PF
2

5%
50V
CERM
402

11

PHASE

10

CPUVCCIOS0_LL

15

MIN_LINE_WIDTH=1.5 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE

VO

CPUVCCIOS0_DRVL

PGOOD

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE

LGATE

RTN

FSEL

2
2

R7640

CRITICAL

0.001

L7630

POWER56

1%
1W
MF-1
0612

0.68UH-18A-3.3MOHM

PPCPUVCCIO_S0_REG_R
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V

PCMB103T

PP1V05_S0

2.2

C7623

1000PF
5%
25V
NP0-C0G
402

CPUVCCSAS0_SNUB

MIN_LINE_WIDTH=0.6 MM

DIDT=TRUE

5%
1/10W
MF-LF
603

6 7 9 10 12 14 16 17 20 22 23
36 40 45 68 73

Vout = 1.05V

R7631
3 4 5

R7603

CRITICAL

FDMS3602S

18A Max Output


f = 300 kHz

MIN_NECK_WIDTH=0.2 MM

NOSTUFF
PGND

NOSTUFF
1

C7631
0.001UF

2.2UF
10%
16V
X5R
603

UGATE

OCSET

CPUVCCIOS0_FSEL

PLACE_NEAR=Q7630.1:1.5mm

CPUVCCIOS0_DRVH

GND
1

1%
1/16W
MF-LF
402

12

CPUVCCIOS0_RTN

5%
25V
NP0-C0G
402

Q7630
BOOT

CPUVCCIOS0_OCSET

C7622
1000PF

1UF

CPUVCCIOS0_VO

R7645

<Rb>

20%
2 16V
POLY
B1A-SM

PVCC

UTQFN

CPUVCCIOS0_EN

CPUVCCIOS0_PGOOD

OUT

2.74K

C7630
10%
16V
X5R
402

ISL95870

1%
1/16W
MF-LF
402

<Ra>

C7621

39UF-0.027OHM

20%
2 16V
POLY
B1A-SM

U7600

3.01K

3.01K

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE

CRITICAL
1

C7620

39UF-0.027OHM

16

R7604 1

R7630

CPUVCCIOS0_VBST

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V

CPU_VCCIOSENSE_N

CRITICAL

1DIDT=TRUE
5%
1/16W
MF-LF
2 402

PP5V_S0_CPUVCCIOS0_VCC

CPU_VCCIOSENSE_P

1%
1/16W
MF-LF
402

20%
10V
X5R
603

14

78 12

13

78 12

C7601

10%
2 50V
CERM
402

5%
1/16W
MF-LF
402

C7603

0.047UF
2

10%
16V
X7R
402

XW7600
SM

CPUVCCIOS0_AGND
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

PLACE_NEAR=U7600.1:1mm
1

R7641

85 49

CPUVCCIOS0_CS_P

85 49

CPUVCCIOS0_CS_N

2.67K

1%
1/16W
MF-LF
402 2

C7640
1000PF
2

5%
25V
NP0-C0G
402

R7642
2.67K

1%
1/16W
MF-LF
2 402

(CPUVCCIOS0_OCSET)
(CPUVCCIOS0_VO)

OCP = R7641 x 8.5uA / R7640


OCP = 22.695A
Vout = 0.5V * (1 + Ra / Rb)

SYNC_MASTER=JACK_K90I

SYNC_DATE=08/19/2010

PAGE TITLE

CPUVCCIO (1.05V) Power Supply


DRAWING NUMBER

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

76 OF 109
SHEET

70 OF 86

CAESAR IV 1.2V INT.VR CMPTS

1.05V S5 LDO

CRITICAL

L7700

Cougar Point requires JTAG pull-ups to be powered at 1.05V in S5.


Pull-ups (3) must be 51 ohms to support XDP (not required in production).
70mA is required to support pull-ups. Alternative is strong voltage
dividers (200/100) to 3.3V S5, which burns 100mW in all S-states.

4.7UH-0.91A
73 37 26 7 6

PP3V3_ENET

ENET_SR_LX

2
PLE031B-SM

PLACE_NEAR=U3900.16:1mm
1

C7717
4.7UF

20%
6.3V
2 CERM
603

C7718
0.1UF

10%
16V
2 X5R
402

37

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.2V
SWITCH_NODE=TRUE
DIDT=TRUE

CRITICAL
XDP_PCH

XW7700

U7740

SM

ENET_SR_VFB

37

MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.2V

PLACE_NEAR=C7725.1:1mm

TPS720105
SON

PP3V3_SUS

73 72 46 22 20 19 18 17 16 7

PP1V2_S3_ENET_INTREG

6 37 71

3 EN

NC 2

XDP_PCH

C7740
PP1V2_S3_ENET_INTREG

10UF
20%
2 6.3V
X5R
603-2

C7726
0.1UF

MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.2V

GND
5

1UF

6 37 71

7 23

Vout = 1.05V
Max Current = 0.35A

OUT 1

6 IN

C7725

PP1V05_SUS

4 BIAS

PLACE_NEAR=U3900.14:1mm
PLACE_NEAR=U3900.14:3mm

NC

XDP_PCH

THRM
PAD
7

C7741
2.2UF

10%
6.3V
CERM 2
402

10%
6.3V
2 X5R
402

10%
16V
2 X5R
402

PLACE_NEAR=L7700.1:1mm
PLACE_NEAR=L7700.1:3mm

C
71 62 61 57 54 52 51 50 49 48
23 22 20 19 18 17 16 12 8 7 6
46 42 41 40 37 36 33 29 27 26
85 77 75 74 73 72

PP3V3_S0
1

C7760

22UF

C7761
0.1UF

10%
2 16V
X5R
402-1

20%
2 6.3V
CERM-X5R
805

U7760
MAX15053EWL

CRITICAL

WLP

73

IN

P1V8S0_EN

P1V8S0_SS

C7764

R7765

0.022UF

10%
P1V8_S0_COMP_RC
16V
2 CERM-X5R
402

3.24K2
1

P1V8S0_COMP

B2

SKIP

B3

EN

CRITICAL

LX A2

C2

SS/REFIN

C1

FB

B1

L7760

IN A3

1.0UH-20%-11A-0.013OHM
P1V8S0_SW

P1V8S0_PGOOD

COMP
GND

1%
1/16W
MF-LF
402

OUT

PP1V8_S0

6 7 14 17 20 22 26 71

PIC0503H-SM
1

R7767

R7760 1 C7766

10K

20.0K

1%
NOSTUFF
1/16W
MF-LF
2 402

73

100PF

1%
1/16W
MF-LF
2 402

5%
50V
2 CERM
402

C7765
1500PF

10%
25V
2 X7R
402

C7767

C7762
22UF

20%
6.3V
2 X5R-CERM-1
603

P1V8_S0_RC
P1V8SO_FB

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE

PGOOD C3

A1

Vout = 1.8V
MAX CURRENT = 2A
F = 1MHZ

1.8V S0 Switcher

C7772
22UF

C7763
0.1UF

20%
10%
6.3V
16V
2 X5R-CERM-1 2 X5R
603
402-1

R7761

100PF
5%
50V
CERM NOSTUFF

10K

1%
1/16W
MF-LF
2 402

402

1.05V S0 LDO

1.5V S0 Switcher

CRITICAL
PP1V5_S0
71 62 61 57 54 52 51 50 49 48
23 22 20 19 18 17 16 12 8 7 6
46 42 41 40 37 36 33 29 27 26
85 77 75 74 73 72

CRITICAL
CRITICAL
L7770
10UH-0.55A-330MOHM
VI
PCAA031B-SM

10uF

20%
6.3V 2
X5R
603

U7770

73

IN

P1V5S0_EN

FB
EN

GND
2

71 62 61 57 54 52 51 50 49 48
23 22 20 19 18 17 16 12 8 7 6
46 42 41 40 37 36 33 29 27 26
85 77 75 74 73 72

C7773

73 70

PP3V3_S0

TPS720105
SON
4 BIAS

PP1V8_S0

6 IN

OUT 1

CPUVCCIOS0_EN

3 EN

NC 2

10uF

SOT23-5

SW 5

U7780

71 26 22 20 17 14 7 6

TPS62201
4

Vout = 1.5V
MAX CURRENT = 0.3A
F = 1MHZ

PP3V3_S0

C7770 1

7 16 20 22 26 42 57

P1V5S0_SW

20%
6.3V
2 X5R
603

C7782 1 C7780

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE

1UF

1UF

10%
6.3V
CERM 2
402

10%
6.3V
CERM 2
402

GND
5

THRM
PAD
7

PP1V05_S0_PCH_VCCADPLL

Vout = 1.05V
Max Current = 0.35A
NC
1

C7781
2.2UF

10%
6.3V
2 X5R
402

SYNC_MASTER=JACK_K90I
PLACE_NEAR=U7780.4:1mm
PLACE_NEAR=U7780.6:1mm

SYNC_DATE=08/19/2010

PAGE TITLE

Misc Power Supplies


DRAWING NUMBER

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

77 OF 109
SHEET

71 OF 86

R7803
0

3.3V S0 FET

5%

CRITICAL

Q7830

1/10W

SIA427DJ

MF-LF
603

SC70-6L

SIA427DJ

48 49 50 51 52 54 57 61 62 71
6 7 8 12 16 17 18 19 20 22 23
26 27 29 33 36 37 40 41 42 46
73 74 75 77 85

PP3V3_S0

PP3V3_S5

30 26 24 23 22 20 19 17 8 7 6
85 76 74 73 72 66 56 46

Q7800

CRITICAL

3.3V S4 FET

3.3V S0 FET

SC70-6L

IN

D
G

R7800
5.1K
1

5%
1/16W
MF-LF
2 402

SOT563

NO STUFF

3.3V S4 FET

0.01UF

P3V3S4_GATE

5%
1/16W
MF-LF
402

SiA427

CHANNEL

P-TYPE 8V/5V

RDS(ON)

10%
16V
CERM
402

73 72 49

MOSFET

IN

5 G

PM_SLP_S3_R_L

91K

S 4

MOSFET

SiA427

CHANNEL

P-TYPE 8V/5V

C7830
RDS(ON)

0.01UF

P3V3S0_SS

26 mOhm @1.8V

LOADING

5%
1/16W
MF-LF
402

3.2 A (EDP)

10%
16V
CERM
402

3.3V_SUS FET Q7820

26 mOhm @1.8V

LOADING

R7830

P3V3S0_EN_L

NO STUFF

C7800

10%
16V
X5R
402

7
10%
16V
X5R
402

NO STUFF

P3V3S4_EN_L

S 1

P3V3_S4_EN

Q7812

7 46 53 54

0.033UF

10K

SSM6N37FEAPE

0.033UF

220K

5%
1/16W
MF-LF
2 402

2 G
73

C7809

R7802

SOT563

4
1

D 6

Q7802
SSM6N37FEAPE

PP3V3_S4

NO STUFF

NO STUFF

C7831

R7832

D 3

PP3V3_S5

30 26 24 23 22 20 19 17 8 7 6
85 76 74 73 72 66 56 46

CRITICAL

1.35 A (EDP)

SIA427DJ
SC70-6L

D 6

C7821

SOT563

CRITICAL

Q7810
2 G

SIA427DJ
73 72

P3V3S3_EN

SiA427
P-TYPE 8V/5V
26 mOhm @1.8V

LOADING

100? mA (EDP)

CRITICAL

Q7840
SIA413DJ

C7810
0.01UF
1

P3V3S3_SS

5%
1/16W
MF-LF
402

MOSFET

SiA427

CHANNEL

P-TYPE 8V/5V

RDS(ON)

10%
16V
CERM
402

SC70-6L
72 66 54 7

PP5V_S5

PP5V_SUS

3.3V S3 FET

MOSFET
CHANNEL
RDS(ON)

7 22

31 mOhm @1.8V

C7841

LOADING

1.608 A (EDP)

Q7822

R7842

D 3

73 72

IN

PM_SUS_EN

10%
16V
X5R 2
402

5%
1/16W
MF-LF
2 402

SOT563

5 G

0.033UF

220K

SSM6N37FEAPE

P5VSUS_EN_L

S 4

R7840
3.3K
1

5V SUS FET

47K

5V_SUS FET

R7810

P3V3S3_EN_L

S 1

6 7 8 18 24 26 30 31 32 33 48
50 54 55 73

10%
16V
CERM
402

SOT563

IN

10%
16V
X5R
402

5%
1/16W
MF-LF
402

4 7

SSM6N37FEAPE

2 G

C7811
0.033UF

5%
1/16W
MF-LF
2402

0.01UF

P3V3SUS_SS

D 6

PP3V3_S3

R7812
100K

Q7812

73

PP3V3_S5

PM_SUS_EN

7 16 17 18 19 20 22 46 71 73

3.3V SUS FET

C7820

R7820

P3V3SUS_EN_L 1 12K 2

S 1

30 26 24 23 22 20 19 17 8 7 6
85 76 74 73 72 66 56 46

IN

10%
16V 2
X5R
402

SC70-6L

0.033UF

5%
1/16W
MF-LF
2 402

PP3V3_SUS

Q7822
SSM6N37FEAPE

R7822
100K

3.3V S3 FET

PP3V3_S5

30 26 24 23 22 20 19 17 8 7 6
85 76 74 73 72 66 56 46

MOSFET

C7840
0.01UF

P5VSUS_SS

5%
1/16W
MF-LF
402

10%
16V
CERM
402

SiA427

CHANNEL
RDS(ON)

P-TYPE 8V/5V
16 mOhm @4.5V

LOADING

100? mA (EDP)

1.5V S3/S0 FET


PP5V_S0

R7862
220K

SLG5AP020
2
3

TDFN

ON

CRITICAL

D 5
G

10%
6.3V
X5R-CERM 2
603

PG

SHDN*

NO STUFF

C7802

PP5V_S3

4.7UF

P1V5S0FET_GATE

5%
1/16W
MF-LF
2402

Q7801
4

5%
P1V5S0FET_GATE_R
1/16W
MF-LF
402

SI7108DN

PWRPK-1212-8-HF

P5V0S0_EN_L

2 3

5.0V S0 FET

0.033UF
10%
16V
X5R

R7860
10K
1

MOSFET

TPCP8102

CHANNEL

P-TYPE

RDS(ON)

18 MOHM @4.5V

LOADING

1.678 A (EDP)

C7860

402

0.01UF

P5V0S0_SS

5%

PP1V5_S3RS0

6 7 10 12 15 30 73 85

THRM
PAD

1/16W

10%

MF-LF

16V

402

CERM
402

GND

CRITICAL

R7801

C7861

5 6 7 8

B
P1V5CPU_EN

60 59 57 46 44 43 42 32 30 7 6
67 66 61

APN 376S0928

VCC

U7801

6 7 22 42 47 52 54 65 68 70 73
77

20%
10V
CERM
402

23V1K-SM

0.1UF

IN

Q7860

TPCP8102
C7801

30

CRITICAL

PP5V_S5

1 2 3

72 66 54 7

5.0V S0 FET

PP1V5_S3

67 30 29 27 7 6

Q7802

D 3

SSM6N37FEAPE

1.5V S3/S0 FET


TP_P1V5S3RS0_RAMP_DONE
OUT

MOSFET

SI7108DN

CHANNEL

N-TYPE

RDS(ON)

6 mOhm @4.5V

LOADING

5 A (EDP)

SOT563

5 G

8
73 72 49

IN

PM_SLP_S3_R_L

S 4

SYNC_MASTER=JACK_K90I

SYNC_DATE=10/22/2010

PAGE TITLE

Power FETs
DRAWING NUMBER

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

78 OF 109
SHEET

72 OF 86

S5 Rail Enables & PGOOD


63 53 48 47 46 45 43 26 7 6
73 64

PP3V42_G3H

10V
CERM 2
402

VDD

343S0497

U7941

SMC_PM_G2_EN

PP3V3_S5
Threshold: ??
DLY > 10 ms
S5PGOOD_DLY
1

R7941

IN_A

OUT_A*

(IPD)

(OD,IPU)
73 66
OUT_A
(OD,IPU)

IN_B

4
3

2:1 +
1.3V -

220PF

OUT_B

DLY

C7942

P3V3S5_EN_L
OUT

0.033UF

Sleep (S3)
Deep Sleep (S4)

66 73

Deep Sleep (S5)

P3V3S5_EN_L_R
NO STUFF
MAKE_BASE=TRUE
P5V3V3_REG_EN
MAKE_BASE=TRUE
P5V3V3_REG_EN
OUT

Battery Off (G3Hot)

S5_PWRGD

MAKE_BASE=TRUE

(OD,IPU)

5
1

PM_SLP_S5_L

IN

P3V3_S4_EN

PLACE_NEAR=U1800.G18:5mm

S0 ENABLE

5%
1/16W
MF-LF
4022
73 45 30 17 6

IN

30 26 24 23 22 20 19 17 8 7 6
85 76 74 73 72 66 56 46

PLACE_NEAR=U1800.P12:5mm

R7951
15.0K

U7940

Q1
Q2

NC

PM_SUS_EN

PM_SUS_EN

6.04K

1/16W
MF-LF
402 2

1%
1/16W
MF-LF
402 2

P5V_DIV_VMON

OUT

49 72 73

5.1K

PM_SLP_S3_R_L

OUT

49 72 73

5%
1/16W
MF-LF
402

39K

5%
1/16W
MF-LF
1 402
PLACE_NEAR=U7770.3:6mm

P1V8S0_EN

P1V8S0_EN

OUT

71 73

P1V5S0_EN

P1V5S0_EN

OUT

71 73

PVCCSA_EN

70 71 73

PVCCSA_EN

65 73

70 71 73

OUT

PLACE_NEAR=U7760.B3:6mm

D 3

PLACE_NEAR=U7100.15:6mm PLACE_NEAR=U7600.3:6mm

CPUVCCIOS0_EN

CPUVCCIOS0_EN OUT
CPUVCCIOS0_EN OUT

MAKE_BASE=TRUE

S 2

C7987

C7981

PLACE_NEAR=U7770.3:6mm

0.47UF

0.47UF

0.47UF

10%
6.3V
CERM-X5R
402

10%
6.3V
CERM-X5R
402

10%
6.3V
CERM-X5R
402

C7988

C7986
0.47UF
10%
6.3V
CERM-X5R
402

72 73

ENET Enable Generation

"ENET" = "S0" || ("S3" && "AC" && "WOL_EN")

3.3V ENET FET

3.3V SUS Detect

30 26 24 23 22 20 19 17 8 7 6
85 76 74 73 72 66 56 46

PP3V3_S5

PP3V3_SUS

C7930

No stuff C7931, 12ms


Min delay time
U7930 Sense input
threhold is 3.07V

Worst-Case Thresholds:

R79571
100

IN

IN

5 SENSE

PP3V3_SUS

20%
10V
CERM 2
402

C7960 1

IN

NO STUFF
100

CPUIMVP_AXG_PGOOD

5%
1/16W
MF-LF
402

U7930 RESET*

100

0.1uF

2
7

73 70

IN

U7960
ISL88042IRTEZ

IN

PVCCSA_PGOOD

TDFN

(IPU)
MR*
V2MON CRITICAL

100

1%
1/16W
MF-LF
4022

353S2310

C7922
0.01UF

100K 2

P3V3ENET_SS

10%
16V
CERM
402

19

IN

WOL_EN

SOT-363
5

WLAN Enable Generation

"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))


NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.

Q7921
SSM3K15FV

D 3

PM_WLAN_EN_L

SOD-VESM-HF

OUT

32

Q7925

1 G
73 45 30 17 6

IN

2N7002DW-X-G

S 2
G

SOT-363
2

AP_PWR_EN

IN

18 32

PM_SLP_S3_L
1

5%
1/16W
MF-LF
402

DP S4 Power Enable

(AC_EN_L)

AC_EN_L

Q7920

IN

SMC_S4_WAKESRC_EN
MAKE_BASE=TRUE

SMC_S4_WAKESRC_EN
OUT

NO STUFF

8 45 46 73 76

R79291

PSOC USB Power Enable

46 45 17

IN

SMC_ADAPTER_EN

1
OUT

SYNC_DATE=10/22/2010

PAGE TITLE

Power Control 1/ENABLE

SOT-363

ALL_SYS_PWRGD

SYNC_MASTER=JACK_K90I

2N7002DW-X-G
6
76 73 46 45 8

6 7 26 37
71

Q7925

2N7002DW-X-G

R7964
100

PP3V3_ENET

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402 2

Q7920

2N7002DW-X-G
SOT-363
5

(PM_SLP_S3_L)

DRAWING NUMBER

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

23 26 45 73

5%
1/16W
MF-LF
402

R7922

NC

R7962
330

PM_ENET_EN_L

PM_RSMRST_L goes to U1800.C21

NO STUFF

S0PGOOD_ISL

17

5%
1/16W
MF-LF
402

NC

OUT

R7966
100

0.033UF

5%
1/16W
MF-LF
402 2

R7963
65

C7931

C7921

10%
2 16V
X5R
402

10K

5%
1/16W
MF-LF
402

CPUVCCIOS0_PGOOD

VDD

SOT23-6
MR* 3
(90K IPU)

R79211

PM_RSMRST_L

20%
50V
2 CERM
402

5%
1/16W
MF-LF
402

P1V8S0_PGOOD

P5V3V3_PGOOD

100K

0.001UF

5%
1/16W
MF-LF
402 2

R7968

5%
1/16W
MF-LF
402

20%
10V
CERM 2
402

10K

R7965
66

PP3V3_S3

48 33 32 31 30 26 24 18 8 7 6
72 55 54 50

GND

R79671

PP3V3_S0

S0PGOOD_ISL

SOT-23-HF

VDD

P1V5S0_PGOOD from U7710


71

7 16 17 18 19 20 22 46
71 72 73

R7933

0.1uF

CRITICAL

5%
1/16W
MF-LF
402 2

Version in development)
68

NTR4101P

PLACE_NEAR=U7930.6:2.3mm

353S2809
S0PGD_BJT_GND_R

15.0K

49 72 73

PM_SLP_S3_R_L

Q7922

VMON_Q4_BASE

R7973

R7988

OUT

R7986

CRITICAL

R7971
10K

5%
1/16W
MF-LF
1
402
PLACE_NEAR=U7600.3:6mm

PM_SLP_S3_R_L
2

VFRQ Low: Fix Frequency


VFRQ High: Variable Frequency

5%
1/16W
MF-LF
402

R7961

1%
1/16W
MF-LF
4022

PLACE_NEAR=Q7812.2:6mm

Q4

5 V3MON
P1V5_DIV_VMON
S0PGOOD_ISL
1
S0PGOOD_ISL 8 ALL_SYS_PWRGD_R
P1V05_DIV_VMON 6 V4MON
RST*
1
15.0K S0PGOOD_ISL
1%
S0PGOOD_ISL
1
GND THRM_PAD
1/16W
MF-LF
4022

R7917

CRITICAL

S0 Rail PGOOD Circuitry

4022

43 67 73

NO STUFF

MF-LF
402 2

DFN2015H4-8

62 61 57 54 52 51 50 49 48
23 22 20 19 18 17 16 12 8 7 6 PP3V3_S0
46 42 41 40 37 36 33 29 27 26
85 77 75 74 73 72 71

10%
6.3V
CERM-X5R
402

CHGR VFRQ Generation

S4_PGOOD_CT 4 CT

R7960 S0PGOOD_ISL
6.04K R79701
1%
10K S0PGOOD_ISL
1/16W
R79721
MF-LF
1%

0.47UF

10%
6.3V
CERM-X5R
402

64

TPS3808G33DBVRG4

PP1V5_S3RS0
PP1V05_S0
S0PGOOD_ISL
1

OUT

100K
5% pull-down added to PCH page
Delete R when
1/16W

72 71 46 22 20 19 18 17 16 7
73

52 47 42 22 7 6 PP5V_S0
77 72 70 68 65 54
85 73 72 30 15 12 10 7 6

0.47UF

MAKE_BASE=TRUE

GND

R7918

ASMCC0179

Q2: 0.XXXV
Q3: 0.640V
3.3V w/Divider: 2.345V
Q4: 0.660V

71 62 61 57 54 52 51 50 49 48
23 22 20 19 18 17 16 12 8 7 6
46 42 41 40 37 36 33 29 27 26
85 77 75 74 73 72

OUT

Q3

NC

73 72

MAKE_BASE=TRUE

VMON_Q3_BASE

1
4

PM_SLP_SUS_L

IN

R7955

Thresholds:
(ISL
VDD:
2.734V-3.010V
V2MON: 2.815V-3.099V
V3MON: 0.572V-0.630V
V4MON: 0.572V-0.630V

73 71 70

SOD-VESM-HF

3 B

PLACE_NEAR=U1800.G16:5mm

Q7950

5%
1/16W
MF-LF
402

SSM3K15FV

74AUP1G3208
SOT891
1 A

SMC_BATLOW_L

IN

5%
1/16W
MF-LF
402
73 65

VMON_Q2_BASE

5%
1/16W
MF-LF
402

43 67 73

DDRREG_EN

MAKE_BASE=TRUE

CHGR_VFRQOUT

Q7931

VCC

23 26 45 73

17

R7954

1K

R7981
20K

R7987

73 71

20%
10V
CERM 2
402

ALL_SYS_PWRGD

72 73

OUT

C7910 1 C7912

R7931

5%
1/16W
MF-LF
402

PP1V05_S0

OUT

DDRREG_EN

MAKE_BASE=TRUE

0.1uF

R7953

23 22 20 17 16 14 12 10 9 7 6
73 70 68 45 40 36

P3V3S3_EN

PP3V42_G3H

C7943

46 45

DDRREG_EN

10K

S0PGD_C

1K

P3V3S3_EN

PM_SLP_S3_R_L

33K
5%
1/16W
MF-LF
402

PP3V3_S5

SMC_BATLOW_L:100K pull up on SMC page

1%
1/16W
MF-LF
402 2

MF-LF
402 2

3.3V/5.0V Sus ENABLE

45

150K

PP1V5_S3RS0

S SSM3K15FV
2

MAKE_BASE=TRUE

100K
5%
Delete R when
pull-down
added to PCH page
1/16W

63
7346
4843
7 6
4726
6445
53

PM_PECI_PWRGD
OUT

R7956

PP1V5_S3RS0

(PM_SLP_S3_R_L)

5%
1/16W
MF-LF
402

R7979 1

100

PM_SLP_S3_L

CPUVCCIOS0_PGOOD

12 10 7 6
85 73 72 30 15

Q7911

1 G

PLACE_NEAR=U7300.16:6mm

5%
1/16W
MF-LF
402

PP3V3_S5

1%
1/16W
MF-LF
2 402

9.1K

5%
1/16W
MF-LF
1 402
PLACE_NEAR=Q7812.2:6mm

R7978

68

30 26 24 23 22 20 19 17 8 7 6
85 76 74 73 72 66 56 46

7.15K

R7911
5.1K
5%
1/16W
MF-LF
402

73 71

5%
1/16W
MF-LF
402

R7952

D 3

R7912

PLACE_NEAR=U7760.B3:6mm

73 70

MF-LF
4022

MAKE_BASE=TRUE

PLACE_NEAR=U5701.3:6mm
2

72 73

OUT

R7975

1K

53 73

10%
10V
CERM
402

MAKE_BASE=TRUE

PLACE_NEAR=U7400.7:5mm

VMON_3V3_DIV 1

R7910

100K
5% added to PCH page
Delete R when pull-down
1/16W

53

PLACE_NEAR=U7100.15:6mm

1%
1/16W
MF-LF
2 402

0.068UF

MAKE_BASE=TRUE

PLACE_NEAR=U1800.G18:5mm

57
37
26
18
7 6 PP3V3_S0
12 8
20 19
29 27
41 40
51 50
62 61
77 75

PSOC_VBUS_EN
PSOC_VBUS_EN
OUT

STUFF
1 NO
C7913

5%
1/16W
MF-LF73
402

MAKE_BASE=TRUE

8 SMC_S4_WAKESRC_EN

S0 Rail PGOOD (BJT Version)


73
48
16
22
33
42
52
71
85

3.3K

73 72

PLACE_NEAR=U7940.1:2.3mm
1

74
49
17
23
36
46
54
72

MAKE_BASE=TRUE

NO STUFF

5%
1/16W
MF-LF
402

76 73 46 45

OUT

66 73

73 67 43

73

PLACE_NEAR=U7400.7:5mm

R7976
0

PM_SLP_S4_L

IN

PLACE_NEAR=U7300.16:6mm

2 72 P3V3_S4_EN

5%
1/16W
MF-LF
402

R79151

CPUVCORE ENABLE

PLACE_NEAR=U7400.7:5mm

45 30 17 6

NO STUFF
R7916

45

OUT

S5_PWRGD (old name RSMRST_PWRGD)-->SMC


SMC-->PM_DSW_PWRGD

CPUIMVP_VR_ON

OUT

SOD-VESM-HF

45 17

5%
1/16W
MF-LF
402

P5VS3_EN_L

R7914

PM_SLP_S3_L

NO STUFF
R7919

R7974

P5VS3_EN_L
MAKE_BASE=TRUE

66 73

100K

ALL_SYS_PWRGD

PM_SLP_S4_L

Delete R when pull-down added to PCH page

73 45 26 23

PM_SLP_S5_L

66 73

10%
2 16V
X5R
402

THRM
PAD

GND

5%
2 25V
CERM
402

P3V3S5_EN_L
MAKE_BASE=TRUE

SMC_PM_G2_ENABLE

Run (S0)

3.3V S4 ENABLE

DLY_1C

C7941

100 2

5%
1/16W
MF-LF
402

SLG4AP012
TDFN

MAKE_BASE=TRUE

85 76 74 73 72 66
22 20 19 17 8 7 6
56 46 30 26 24 23

CRITICAL

0.1uF
20%

5%
1/16W
MF-LF
402

State

IN

PP3V42_G3H

63 53 48 47 46 45 43 26 7 6
73 64

Internal pull-ups 100K +/- 20%

C7940 1

45 6

R7913
3.3V,5V S3 ENABLE
68K

BRANCH

PAGE

79 OF 109
SHEET

73 OF 86

LCD

CONNECTOR

LVDS CONNECTOR:518S0650
18 8

LCD_IG_PWR_EN

FOUR GROUNDING VIAS SHOULD BE DISTRIBUTED


ALONG THE GROUND SHAPE THAT BOUND THE CONNECTOR BODY

R9014

CRITICAL

100K

J9000

5%
1/16W
MF-LF
2 402

20474-030E-11
F-RT-SM
31

CRITICAL

C9015

U9000

0.001UF

FPF1009
1 ON
85 76
22 20 19 17 8 7 6
73 72 66 56 46 30 26 24 23

PP3V3_S5

MFET-2X2-8IN

3 VIN_2

GND
6

C9009
0.1UF

VOUT_1 4

PP3V3_LCDVDD_SW

VOUT_2 5

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.30 MM

THRM
PAD
7

32
2

C9011
0.1UF

L9008

CRITICAL

10UF

PP3V3_S0
1

R9008

5%
1/16W
MF-LF
2 402

18 8 6

LVDS_DDC_DATA

MIN_LINE_WIDTH=0.30 MM

4
5

BKL_VSYNC

PP3V3_S0_LCD_F

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.20 MM

7
80 18 6

LVDS_IG_A_DATA_N<0>

80 18 6

LVDS_IG_A_DATA_P<0>

8
9
10

2.2K

LVDS_DDC_CLK

VOLTAGE=3.3V

(LVDS DDC POWER)

18 8 6

PP3V3_LCDVDD_SW_F

77 6

2
0402-LF

71 62 61 57 54 52 51 50 49 48
23 22 20 19 18 17 16 12 8 7 6
46 42 41 40 37 36 33 29 27 26
85 77 75 73 72

MIN_NECK_WIDTH=0.20 MM

120-OHM-0.3A-EMI

C9012

20%
6.3V
2 X5R
603

2
0402-LF

MIN_NECK_WIDTH=0.20 MM

10%
16V
2 X5R
402

10%
16V
X5R
402

10%
50V
X7R
402

FERR-120-OHM-1.5A

2 VIN_1

0.001UF

10%
50V
X7R
402

L9004

C9010

R9009

80 18 6

LVDS_IG_A_DATA_N<1>

11

2.2K

80 18 6

LVDS_IG_A_DATA_P<1>

12

5%
1/16W
MF-LF
402

80 18 6

LVDS_IG_A_DATA_N<2>

14

80 18 6

LVDS_IG_A_DATA_P<2>

15

13

16

CRITICAL

L9080

85 6

LVDS_CONN_A_CLK_F_N

17

90-OHM-200MA
AMC2012-SM

85 6

LVDS_CONN_A_CLK_F_P

18

LVDS I/F

SYM_VER-1

19
80 18

LVDS_IG_A_CLK_N

80 18

LVDS_IG_A_CLK_P

77 6

PPVOUT_SW_LCDBKLT

20

NC

C9020

21

0.001UF
10%
50V
X7R
402

22
2

23

NC

24

LED BKLT I/F

25
26
27
28

77 6

LED_RETURN_1

77 6

LED_RETURN_2

77 6

LED_RETURN_3

77 6

LED_RETURN_4

77 6

LED_RETURN_5

33

77 6

LED_RETURN_6

34

29
30

NC

SYNC_MASTER=K24_MLB

SYNC_DATE=07/20/2009

PAGE TITLE

LVDS CONNECTOR
DRAWING NUMBER

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

90 OF 109
SHEET

74 OF 86

3
8

81 8

C9301

DP_EXTA_ML_C_N<0>

IN

C9302

DP_EXTA_ML_C_P<1>

IN

C9303

DP_EXTA_ML_C_N<1>

IN

C9304

DP_EXTA_ML_C_P<2>

IN

C9305

DP_EXTA_ML_C_N<2>

IN

IN

DP_EXTA_ML_C_P<3>

C9306

81 8

IN

DP_EXTA_ML_C_N<3>

C9307

C9308

BI

C9309

DP_EXTA_AUXCH_C_N

BI

OUT

L9372

75 81

75 81

83 34

IN

83 34

IN

DP_EXTA_ML_P<2>

T29_R2D_C_N<0>
T29_R2D_C_P<0>

DP_EXTA_ML_N<2>

75 81

10% 16V
X5R-CERM
0201
2

DP_EXTA_ML_P<3>

75 81

DP_EXTA_ML_N<3>

75 81

10% 16V
X5R-CERM
0201

83 34

10% 16V
X5R-CERM
0201

R9309

L9373

DP_EXTA_AUXCH_N

R9308

83 34

IN

83 34

IN

5%
MF

C9311

0.1UF

10%
16V
2 X5R-CERM
0201

1.0NH+/-0.1NH

L9383

1.0NH+/-0.1NH

81 75
81 75

81 75

Note: Other Parade


devices use 96/B6,
so only 94/B4 are
used for this part.

81 75

81 75
81 75

81 75

NO STUFF

81 75

R9310
17 8

IN

17 8

BI

R9355

R9351

C9312
0.1UF

10%
16V
2 X5R-CERM
0201

30

17 8

OUT_D1P
OUT_D1N

28
27

DP_EXTA_ML_P<2>
DP_EXTA_ML_N<2>

7 IN_D2P
8 IN_D2N

OUT_D2P
OUT_D2N

25
24

DP_EXTA_ML_P<3>
DP_EXTA_ML_N<3>

9 IN_D3P
10 IN_D3N

OUT_D3P
OUT_D3N

23
22

DP_EXTA_DDC_CLK
DP_EXTA_DDC_DATA

14 IN_SCL
13 IN_SDA

AC_AUXP
AC_AUXN

20
19

OUT

DPSDRVA_I2C_CTL_EN

48

IN

48

BI

B
23 16

IN

CRITICAL

2
0201-1

30

30

5%
MF

1/20W
201

5%
MF

1/20W
201

5%
MF

1/20W
201

5%
MF

1/20W
201

83

83

83
83

83
83

83
83

83
83

83
83

2
83
83

30

1%
1/16W
MF-LF
2 402

C9363

DP_SDRVA_ML_C_P<1>
DP_SDRVA_ML_C_N<1>

0.1UF

C9362

DP_SDRVA_ML_C_P<2>
DP_SDRVA_ML_C_N<2>

0.1UF

C9367

DP_SDRVA_ML_C_P<3>
DP_SDRVA_ML_C_N<3>

0.1UF

C9366

DP_SDRVA_AUXCH_C_P
DP_SDRVA_AUXCH_C_N

0.1UF

CA_DET

32

DP_A_CA_DET

CEXT

11

DPSDRVA_CEXT

0.1UF
IN

C9368

75

0.1UF

C9319

75

Desktops use PCIe WAKE#


Mobiles use S4 WAKE#

OUT

=T29_WAKE_L
OMIT

34

OUT

OUT

T29_MCU_INT_L

BI

76

IN

76

OUT

18

R9383
83
83

DP_SDRVA_ML_P<0>
DP_SDRVA_ML_N<0>

83

DP_SDRVA_ML_P<2>
DP_SDRVA_ML_N<2>

R9365
R9364

22

HVQFN25
1 RESET#/PIO0_0
R/PIO1_0/AD1
2 PIO0_1/CLKOUT
R/PIO1_1/AD2
7 PIO0_2/SSEL/CT16B0_CAP0
R/PIO1_2/AD3
(IPU) SWDIO/PIO1_3/AD4
8 PIO0_4/SCL (OD)
PIO1_4/AD5/WAKEUP
9 PIO0_5/SDA (OD)

83
83

R9393
51

5%
1/20W
MF
2 201

10
11
12
13
14
15

SWCLK

5%
1/20W
MF
201

10K

20%
2 10V
CERM
402

5%
1/16W
MF-LF
402 2
IN

76

IN

76

75
76 8

46 75

T29_A_HV_EN

OUT

1K

5%
1/16W
MF-LF
2 402

R9336
10K

R9339

5%
1/20W
MF
2 201

51

5%
1/20W
MF
201

C9358
0.1uF

DIN1_1+
DIN1_1-

DP_SDRVA_AUXCH_P
DP_SDRVA_AUXCH_N

19
18

AUX1+
AUX1-

DP_SDRVA_HPD

17

HPD_1

T29_D2R1_BIASP
T29_D2R1_BIASN

15
14

AUX2+
AUX2-

13

HPD_2

10
32
11

GPU_SEL
AUX_SEL
NC

DP_A_PWRDWN
T29_A_BIAS

U9390
CBTL04DP081
HVQFN
DOUT_0+ 1
DOUT_0- 2

0.1UF
20%
402

T29DPA_ML_N<3>
T29DPA_ML_P<3>
T29: Unused

OUT

76 83
76 83

BI

T29DPA_ML_N<1>
BI 76 83
T29DPA_ML_P<1>
OUT 76 83
T29: LSX_A_R2P/P2R (P/N)

DIN2_0+
DIN2_0DIN2_1+
DIN2_1-

C9391

2 10V
CERM

5%
1/20W
MF
2 201

DOUT_1+ 4
DOUT_1- 5

23
22

20%
2 10V
CERM
402

100K

VDD

AUX+ 6
AUX- 7

DP_A_EXT_AUXCH_P BI
DP_A_EXT_AUXCH_N BI
T29: RX_1 Bias Sink

HPD_IN 8

DP_A_EXT_HPD

IN

76 83
76 83

46 75

R9398
100K

5%
1/20W
MF
2 201

LO=Port A
HI=Port B

THMPAD GND

SIGNAL_MODEL=T29DP_MUX

Note: U9390 ML/HPD defaults to T29 mode so that DP/T29


Display can detect host T29 support using I2C
pull-ups on ML<3>. U9390 AUX defaults to DP mode
because 100-ohm pull-downs would defeat DP Sinks
detection of DP Source.
SYNC_MASTER=T29

SYNC_DATE=10/16/2010

PAGE TITLE

DRAWING NUMBER

5%
1/16W
MF-LF
2 402

Apple Inc.

SIZE

D
REVISION

5%
1/16W
MF-LF
2 402

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2
10%
16V
X5R
402

0.1UF

CRITICAL

(T29_A_LSX_P2R)
(T29_A_LSX_R2P)

C9390

1M

T29_A_UC_ADDR
R9330 provides pads for programming/debug of MCU, please make accessible.
If project has space for 10-pin programming header it should be used.

51

R9363

DisplayPort/T29 A MUXing

SWDIO

27
26

P2R = Plug to Receptacle


R2P = Receptacle to Plug
34

75

DP_SDRVA_ML_N<1>
DP_SDRVA_ML_P<1>

8 36 76

R9335

R9362

R9399

DIN1_0+
DIN1_0-

5%
1/16W
MF-LF
402

75

I2C Addr:
0x26/0x27 (Wr/Rd)
1

1/20W
201
1/20W
201

VOLTAGE=3.3V

DP_SDRVA_ML_N<3>
DP_SDRVA_ML_P<3>

R9334
10K

76 83

CBTL04DP081 (353S3151) and


PI3vEDP212 (353S3055) are
footprint-compatible parts with
similar pinouts. NXP uses pin
10 for ML and HPD, Pericom uses
pin 10 for ML and pin 11 for HPD.

R9338

0.1UF

IN

5%
MF
5%
MF

DP_A_BIAS2

PLACE_NEAR=C9361.1:2mm2

NC

1K

C9331

T29_A_LSX_P2R
T29_A_LSX_R2P
T29_LSEO<1>

PIO0_6/SCK
PIO1_6/RXD 23
PIO0_7/CTS#
PIO1_7/TXD 24
PIO1_8/CT16B1_CAP0 6
PIO0_8/MISO/CT16B0_MAT0
PIO0_9/MOSI/CT16B0_MAT1
SWCLK/PIO0_10/SCK/CT16B0_MAT2 (OD)
R/PIO0_11/AD0 (OD)
THRM
XTALIN 4
VSS
PAD

1/20W
201

Both Rs:

31
30

R9397

76 83

OUT

PP3V3_SW_DPAPWR
76 75 8
Must be 3.3V DP A port power

2
10% 16V
X5R-CERM
0201
2
10% 16V
X5R-CERM
0201

T29DPA_CONFIG1_RC
T29DPA_CONFIG2_RC
T29_A_HV_EN_R
T29_A_UC_ADDR
DP_A_EXT_HPD

16
17
18
19
20

5%
MF

DP/T29 A Low-Speed MUX

83

Must be 3.3V DP A port power

20%
2 10V
CERM
402

OUT

VOLTAGE=3.3V

76 83

DP_A_BIAS0

DP_A_BIAS

83

1K

OMIT_TABLE

1.5K

U9359
74LVC1G04DBDCK

5%
1/20W
MF
201

0.1UF

1.5K

CRITICAL
5

R9396

VDD

DP Path Biasing
R9361 1.5K 1
2
5% 1/20W
201
R9360 1.5K 1
2 MF

6.3V
201

76 83

IN

Both Rs must connect


to C in star topology.

(D9360/D9361)
83

IN

R9384
R9385

(D9382/D9383)

OMIT_TABLE

5%
1/20W
MF
201 2

C9330

SIGNAL_MODEL=T29PIN

CKPLUS_WAIVE=NdifPr_badTerm
25
80 8 T29_A_RSVD_N
24
80 8 T29_A_RSVD_P

1/20W
201
1/20W
201

GND_VOID=TRUE (D9382/D9383)
GND_VOID=TRUE (D9361.2)
GND_VOID=TRUE
1.5K 1
2
GND_VOID=TRUE
5% 1/20W
201
1.5K 1
2 MF
5% 1/20W
MF
201

SIGNAL_MODEL=EMPTY

TSLP-2-7

TSLP-2-7
BAR90-02LRH
CRITICAL
(All 4 Ds)

6.3V
201
6.3V
201

76 83

(D9360.2)

51

PP3V3_SW_DPAPWR

5%
MF
5%
MF

T29: TX_1
T29DPA_ML_C_P<2>
T29DPA_ML_C_N<2>

TSLP-2-7

D9361

5% 1/20W
MF 201

GND_VOID=TRUE

BAR90-02LRH

83

25

34

I2C_T29_SCL
I2C_T29_SDA
T29DPA_HPD
T29_A_BIAS_R
T29_LSOE<0>
T29_LSOE<1>

83 48 34

=T29_WAKE_L:

T29_LSEO<0>

IC supports input
high while Vcc = 0V.

THMPAD

5
IN

2
20%
X5R
2
20%
X5R

6.3V
201

D9383

76 83

OUT

GND_VOID=TRUE

TSLP-2-7

OUT

D
1

R93921
GND

D9382

76 83

GND_VOID=TRUE

R9374 1.5K
R9375 1.5K

BAR90-02LRH

76 83

IN

(D9372/D9373)
(D9365.2)

SC70

34 PD (IPD)

21

IN

2
20%
X5R
2
20%
X5R

DP_A_PWRDWN

Port A MCU

34

1.5K

BAR90-02LRH

GND_VOID=TRUE

20%
6.3V
CERM 2
402-LF

39 AUXDDC_OFF (IPD)

83 48 34

83

2.2UF

DP_AUXCH_ISOL

DP_A_PWRDWN

5%
1/16W
MF-LF
402 2

0.22UF

C9361

R9382
1
2

D9360

5% 1/20W
MF 201

T29_R2D_P<1>
T29_R2D_N<1>

83

PLACE_NEAR=U9310.11:2 mm

12 REXT

DP_A_CA_DET

1.5K

20% 4V
CERM-X5R-1
201
2

83

U9330

R93301

D9372/D9373: SIGNAL_MODEL=T29PIN
D9364/D9365: SIGNAL_MODEL=EMPTY

C9359

LPC1112A

OUT

GND_VOID=TRUE
GND_VOID=TRUE

TSLP-2-7
BAR90-02LRH
CRITICAL
(All 4 Ds)

PP3V3_S0

2
10% 16V
X5R-CERM
0201
2
10% 16V
X5R-CERM
0201

C9369

DPSDRVA_REXT

75

17

C9360

2
10% 16V
X5R-CERM
0201
2
10% 16V
X5R-CERM
0201

(DP_SDRVA_HPD)

CRITICAL

C9365

TSLP-2-7

T29_D2R_C_P<1>
T29_D2R_C_N<1>

10%
16V
X5R 2
402

31

76 75 8

75

T29 Path
Biasing

GND_VOID=TRUE

20% 4V
CERM-X5R-1
201

4.22K

DP_SDRVA_ML_C_P<0>
DP_SDRVA_ML_C_N<0>

41

BAR90-02LRH

20% 4V
CERM-X5R-1
201
2

20% 4V
CERM-X5R-1
GND_VOID=TRUE 201

0.22UF

0.47UF

C9364

TSLP-2-7

IN

(D9364.2)

T29: TX_0
T29DPA_ML_C_P<0>
T29DPA_ML_C_N<0>

D9365

GND_VOID=TRUE
TSLP-2-7

D9373

0.1UF

(IPD) OUT_HPD

6
33

R9319

MF
2 201

3 IN_HPD

PS8301 has internal


~150K pull-down on PD
pin. Okay to drive this
pin even when VCC=0V per
Parade (pin is 5V-tolerant).

C9383

61
42
23
6
16
29
49
72

270

(DP_SDRVA_AUXCH_P)
(DP_SDRVA_AUXCH_N)

I2C_DPSDRVA_SCL
I2C_DPSDRVA_SDA

71 62
48 46
27 26
12 8 7
22 20 19 18 17
41 40 37 36 33
5%
57 54 52 51 50
1/20W 85 77 75 74 73

R9353

18
17

38 SCL_CTL
37 SDA_CTL

0.47UF

DP_SDRVA_ML_R_P<2>
DP_SDRVA_ML_R_N<2>
1

OUT_AUXP_SCL
OUT_AUXN_SDA

36 I2C_ADDR0 (IPD)
35 I2C_ADDR1 (IPD)

0.22UF

16 IN_AUXP
15 IN_AUXN

26 I2C_CTL_EN (IPU)

D9372

5% 1/20W
MF 201

R9373

BAR90-02LRH

GND_VOID=TRUE
1.5K 1
2

GND_VOID=TRUE

C9382

DP_SDRVA_ML_R_P<0>
DP_SDRVA_ML_R_N<0>

2
1

5%
1/20W
MF
201

83

BAR90-02LRH

T29_R2D_P<0>
T29_R2D_N<0>

83

T29_A_BIAS_R2DP1
T29_A_BIAS_R2DN1

0.22UF

AUXCH Snoop Port,


used by PS8301
during training.

DPSDRVA_I2C_ADDR0
DPSDRVA_I2C_ADDR1

DP_A_PWRDWN_R
SDRV_PD

83

5%
1/20W
MF
201 2

4 IN_D1P
5 IN_D1N

DP_EXTA_HPD

5%
1/16W
MF-LF
2 402

R9318

IN

T29_R2D_C_F_N<1>
T29_R2D_C_F_P<1>

270

30
29

DP_EXTA_ML_P<1>
DP_EXTA_ML_N<1>

83

R93521

OUT_D0P
OUT_D0N

1 IN_D0P
2 IN_D0N

81 75

1K

(C9383.2)

2
0201-1

VDD

DP_EXTA_ML_P<0>
DP_EXTA_ML_N<0>

DP_EXTA_AUXCH_P
DP_EXTA_AUXCH_N

81 75

R9312

IN

D9364

5% 1/20W
MF 201

20% 4V
CERM-X5R-1
201
2

20% 4V
CERM-X5R-1
GND_VOID=TRUE 201

(C9383.2)

QFN

5%
1/16W
MF-LF
2 402

0.47UF

R9308/R9309 maintain bias on C9308/C9309


to prevent spikes when U9310 AUXDDC_OFF
transitions from high to low.

1/20W
201

PS8301TQFN40GTR-A2

1K

1.5K R9372
1
2

0.47UF

C9381

(Both Ls)

L9382

T29_R2D_C_N<1>
T29_R2D_C_P<1>

U9310

Addr (W/R)
0x96/0x97
0xB6/0xB7
0x94/0x95
0xB4/0xB5

1K

T29_D2R_C_P<0>
T29_D2R_C_N<0>
GND_VOID=TRUE

20% 4V
CERM-X5R-1
201

GND_VOID=TRUE

21
40

20%
6.3V
CERM 2
402-LF

PS8301 I2C Addresses:

5%
1/16W
MF-LF
402 2

C9373

0.47UF

R9350

R9311

2
0201-1

0.47UF

OVERSIZE_PAD=0.875 mm^2

DP A Super-Driver

83

T29 A High-Speed Signals

GND_VOID=TRUE

C9372

T29_R2D_C_F_N<0>
T29_R2D_C_F_P<0>

T29_D2R_N<1>
T29_D2R_P<1>

75 81

1M

OUT

1/20W
201
81

10% 16V
X5R-CERM
0201

PP3V3_S0

A0
0
1
0
1

83

C9380

83 34
OUT
85
48 49 50 51 52
6 7 8 12 16 17 18 19 20 22 23
26 27 29 33 36 37 40 41 42 46
54 57 61 62 71 72 73 74 75 77

PP3V3_S0

5%
1M
MF
DP_EXTA_AUXCH_P 75

2.2UF

A1
0
0
1
1

0.47UF
(C9372.2)

2
0201-1

20% 4V
CERM-X5R-1
201
2

(C9380/C9381)

C9310

1.0NH+/-0.1NH

R9354
77
57
42
26
6
19
36
50
72

C9371

T29 signals are


P/N-swapped after AC
caps to improve layout.

75 81

10% 16V
X5R-CERM
0201

0.47UF

1.0NH+/-0.1NH

10% 16V
0.1UF
X5R-CERM
0201
If GPU uses common pins for AUX_CH
and DDC, alias nets together at GPU.

85
71 62 61
49 48 46
33 29 27
18 17 16 12 8 7
23 22 20
41 40 37
54 52 51
75 74 73

C9370

(C9370/C9371)

T29_D2R_N<0>
T29_D2R_P<0>

(C9373.2)
1

0.1UF
81 80 17 8

83 34

10% 16V
X5R-CERM
0201

0.1UF
DP_EXTA_AUXCH_C_P

DP_EXTA_ML_N<1>

0.1UF

81 80 17 8

DP_EXTA_ML_P<1>

0.1UF
81 8

OUT

OVERSIZE_PAD=0.875 mm^2

10% 16V
X5R-CERM
0201

0.1UF
81 8

75 81

83 34

(Both Ls)

0.1UF
81 8

DP_EXTA_ML_N<0>

0.1UF
81 8

GND_VOID=TRUE
75 81

10% 16V
X5R-CERM
0201

0.1UF
81 8

DP_EXTA_ML_P<0>

10% 16V
X5R-CERM
0201

0.1UF

C9300

DP_EXTA_ML_C_P<0>

IN

81 8

T29_A_BIAS_R2DP0
T29_A_BIAS_R2DN0
8
IN

IN

28
21

29
20
16
12
9
3

33

BRANCH

PAGE

93 OF 109
SHEET

75 OF 86

R94161

C9410

470K

0.1UF

5%
1/16W
MF-LF
402 2

VIN

VOUT

TPS2590
QFN

DPAPWRSW_HVEN_L_R

9 CT
GND
5
13
14

R9410

=
=
=
=

200k / RFLT = 885mA


201k / RLIM = 935mA
CCT * 38900
CCT * 100000

GND
2

FB 4
PGND
1

IN

IN

OUT

R94941
1K

5%
1/20W
MF
201 2

T29_A_BIAS
VOLTAGE=3.3V

5%
1/20W
MF
201 2
OUT

SIGNAL_MODEL=EMPTY

8 75 76

83 75

IN

IN

83 75

T29_A_BIAS_D2RN1
T29_A_BIAS_D2RP1

2.2K
5%
1/20W
MF
201 2

C9400 1

GND_VOID=TRUE
83 75
83 75

OUT
OUT

5%
1/20W
MF
2 201

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18V

10%
50V 2
X7R
402

DPAPWRSW_HV_DET

5%
1/16W
MF-LF
402

DP Dir

12

GND_DPACONN_8

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=0V

5%
1/20W
MF
201

SIGNAL_MODEL=EMPTY

6
8
10
12
14

R9404 GND_VOID=TRUE
1

12

GND_DPACONN_14

18

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=0V

5%
1/20W
MF
201

GND_VOID=TRUE

16

20

83
83

83 75

BI

T29DPA_D2R1_AUXCH_P
T29DPA_D2R1_AUXCH_N
CRITICAL

DP Dir

83

BOT ROW

TOP ROW

TH PINS

SM PINS

12

12

(Both Cs)

HOT_PLUG_DETECT
GND
CONFIG1
ML_LANE0P
CONFIG2
ML_LANE0N
GND
GND
ML_LANE3P
ML_LANE1P
ML_LANE3N
ML_LANE1N
GND
GND
AUX_CHP
ML_LANE2P
AUX_CHN
ML_LANE2N
DP_PWR
RETURN

C9471

30PF

5%
50V
CERM 2
402

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18V

C9499
30PF

5%
50V
2 CERM
402

3
5

GND_DPACONN_7

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=0V

C9402
0.01UF

10%
50V 2
X7R
402

12

C9401

12

75 83

T29DPA_ML_P<1>
T29DPA_ML_N<1>

IN

75 83

T29DPA_ML_C_P<2>
T29DPA_ML_C_N<2>

IN

75 83

IN

75 83

R9471
470K

5%
1/20W
MF
2 201

11

BI

75 83

13

T29: LSX_R2P/P2R (P/N)

15
17
19

GND_VOID=TRUE

GND_DPACONN_13

R9407
1

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=0V

12

GND_VOID=TRUE

(Both Cs)

5%
1/20W
MF
201

21

GND_DPACONN_19

C9472
C9473
1

2
0603

20% 4V
CERM-X5R-1
201

20% 4V
CERM-X5R-1
201

0.47UF
GND_VOID=TRUE

0.47UF

T29DPA_ML_P<2>
T29DPA_ML_N<2>

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=0V

75 83

IN

20% 4V
CERM-X5R-1
201

L9408

IN

GND_VOID=TRUE

5%
1/20W
MF
2 201

5%
1/20W
MF
201

T29DPA_ML_C_P<0>
T29DPA_ML_C_N<0>

470K

20% 4V
CERM-X5R-1
201

0.47UF

R9470

FERR-120-OHM-3A
DPACONN_20_RC

GND_VOID=TRUE

T29: TX_1

R9401

0.47UF

T29DPA_ML_P<0>
T29DPA_ML_N<0>

T29DPA_HPD_R

5%
1/20W
MF
201

1%
1/16W
MF-LF
402 2

R9402

GND_VOID=TRUE
SIGNAL_MODEL=EMPTY

DP_A_EXT_AUXCH_P
DP_A_EXT_AUXCH_N

GND_VOID=TRUE

C9470

GND_VOID=TRUE R9406

83

0603

C9498 1

1%
1/16W
MF-LF
402 2

DPAPWR_FB_DIV

5%
1/20W
MF
201

T29 Dir

83

650NH-5%-0.430MA-0.052OHM

(Both Ls)
BI

DSPLYPRT-M97-1

22

L9499

GND_VOID=TRUE
SIGNAL_MODEL=T29PIN

83 75

GND_DPACONN_1

J9400

SHIELD PINS

SIGNAL_MODEL=EMPTY

5%
1/16W
MF-LF
2 402

R9405

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=0V
83

0603

5%
1/16W
MF-LF
402 2

Circuit threshold range: 2.877-2.941V (2.903V nominal)

CRITICAL

R9403 GND_VOID=TRUE

5%
1/20W
MF
2 201

D9499

10K

T29: TX_0

L9498

BAR90-02LRH

100K

R9432

F-RT-THSM

1K

2
TSLP-2-7

R94351

R94361

For J9400 T29 SMT pads


(3, 5, 17 & 19):
GND_VOID=TRUE

T29DPA_ML_P<3>
T29DPA_ML_N<3>
BI
T29: Unused

5%
1/16W
MF-LF
402 2

220

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18V

0603

BI

D9498

75
8
36
76

PP3V3RHV_SW_DPAPWR

R9495

TSLP-2-7
BAR90-02LRH
CRITICAL

R9472
470K

5%
1/20W
MF
2 201

GND_VOID=TRUE
1

R9473
470K

5%
1/20W
MF
2 201

R9408

5%
1/20W
MF
201

12

5%
1/20W
MF
201

0.01UF

10%
2 50V
X7R
402

470k Rs for ESD protection


on AC-coupled signals.

T29DPA_HPD

75

OUT

75

OUT

T29DPA_CONFIG1_RC

75

OUT

T29DPA_CONFIG2_RC

R94521
1M

5%
1/16W
MF-LF
402 2

1K

GND_VOID=TRUE

650NH-5%-0.430MA-0.052OHM

GND_VOID=TRUE

T29_A_HV_EN

R9433

0.01UF

T29_D2R_C_P<1>
T29_D2R_C_N<1>

GND_VOID=TRUE

2.2K

G 2

1 S

82

R9499

S 4

DisplayPort/T29 A Connector

L9400

FERR-120-OHM-3A
PP3V3RHV_SW_DPAPWR_UF

CRITICAL

R94981

0.1UF

24.9K

Q9419
DMB53D0UV

GND_VOID=TRUE

51

SOT563

C9435

20%
10V
2 CERM
402

ZXRE060A

10%
10V 2
X5R
402

6
D

3
IN

SOT353
4 FB
PGND
GND
2
1

1UF

DPAPWRSW_NPN_E

T29_D2R_C_P<0>
T29_D2R_C_N<0>

R94911

5 OUT

R94371

ZXRE060A REF range:


0.595-0.605V (0.600V nominal)
Circuit threshold range: 3.363-3.439V (3.395V nominal)

T29 Dir
83 75

T29_A_BIAS

DPAPWRSW_ON_C

5%
1/16W
MF-LF
402 2

2
OUT

76 75 8

22

DPAPWR_BLDR_B

Note: Bleeder active when


DPAPWRSW_HV_DET is
HIGH and T29_A_HV_EN
is LOW.

83 75

20%
2 6.3V
POLY-TANT
CASE-B2-SM

SSM6N37FEAPE

R9424

0.1UF

2 G

10%
16V
X5R
402

20%
2 6.3V
X5R-CERM-1
603

Q9430

SOT363

R9418

T29_A_BIAS_R 0.1uF
1

6 D

SOT563

5 G

DMB53D0UV

MIN_LINE_WIDTH=0.20 MM
MIN_NECK_WIDTH=0.20 MM

D 3

SSM6N37FEAPE

Q9426

T29_A_HV_EN

C9490

75

C9429

20%
10V
2 CERM
402

SOT-563
76 75 36 8

Q9430

MMDT3946XG

DPAPWRSW_HV_DET_L
NO STUFF
1

SOT-563

2.5V / 249 ohm = 10mA


R9419 P = ~27mW
249 1
2
DPAPWR_BLDR_E
1%
1/16W
MF-LF
402

SOT353

<RLIM>

100UF

CRITICAL

Q9419
5

20%
10V
CERM 2
402

C9487

U9435

10%
10V
X5R 2
402 DPAPWRSW_ON_L_C

5%
1/16W
MF-LF
2 402

20%
10V
CERM 2
402

Bleeder Resistor

S 2

4.7K

U9426

0.1UF

DPAPWRSW_P3V3_ON

1
R9429 C9424
0.47UF

ZXRE060A

C9426

20%
2 10V
CERM
402

CRITICAL

C9480
22UF

<RFLT>

5%
1/16W
MF-LF
2 402

SOD-VESM-HF

1%
1/16W
MF-LF
2 402

20%
6.3V 2
X5R
603

0.1UF

4.7K

5%
1/16W
MF-LF
2 402

D 3

200K

1%
1/16W
MF-LF
402 2

C9481

0.1UF

R9430

1K

3 CRITICAL
IN
OUT 5

1%
1/16W
MF-LF
402 2

8 45 46 73

R9426

Q9415
SSM3K15FV

R9411

100K

C9485

C9436 1

21.5K

3.3V Always
1

10UF

DPAPWRSW_P3V3_ON_L
DPAPWRSW_HV_DET_R_L

R94281
1

<CT>

Blocking FET, off


when Source >3.4V
or HV_EN high.

DPAPWRSW_VREF

DPAPWRSW_IFLT

10%
2 6.3V
CERM-X5R
402

IFLT
ILIM
TFLT
TSD

5%
1/16W
MF-LF
402 2

4.7K

46 56 66 72 73
6 7 8 17 19 20
22 23 24 26 30
74 85

SMC_S4_WAKESRC_EN
IN

EN 4

CRITICAL

C9486 1

BGA

0.47UF

R94251

1%
1/16W
MF-LF
402 2

100K

DPAPWRSW_ILIM

IFLT 8
THRM
PAD

Q9425

C9412

R94271

TP_DPAPWRSW_FLT_L

16 EN*
FLT* 15
(IPU-Weak!)
6 RTRY*
ILIM 7

DPAPWRSW_CT

MIN_LINE_WIDTH=0.38 MM
2 50V
X7R MIN_NECK_WIDTH=0.20 MM
STPS2L30AF
603-1VOLTAGE=18V

3 OC*

PP3V3_S5
IN 5

GND
2

SI8409DB

3.3V/HV MUXed

D9410
SM

C9411

0.1UF PPHV_SW_DPAPWR
1
10%

U9410

10%
50V 2
X7R
603-1

(*) U9410 tolerance unknown


CRITICAL

10
11
12

T29_A_HV_EN

76 75 36 8

2 3

CRITICAL

DFLS1100

1
2
3
4

TPS2051B
SOT23

1 OUT

CRITICAL

PP15V_T29
20V Max

-30V
+/-12V
-1.4V
65mOhm @ 2.5V Vgs
3.7A @ 70C

DP_PWR must be S4 to support


wake from T29 devices.

U9480

POWERDI-123
2
1

SI8409DB:
Vds(max):
Vgs(max):
Vgs(th):
Rds(on):
Id(max):

Max
894mA (*)
944mA (*)
26.7ms
724ms

IFLT
ILIM
TFLT
TSD

CRITICAL

D9425

Min
876mA
925mA
13.4ms
235ms

Port A 3.3V Power Switch

B1100 chosen for high Vf


for 2.9V mode. CRITICAL

Nominal
885mA
935mA
18.3ms
470ms

17

36 8 7

3.3V/HV Power MUX

PP3V3_SW_DPAPWR
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V

Port A HV Power Switch


D

75 8

DP Source must pull


down HPD input with
greater than or equal
to 100K (DPv1.1a).

R9451 C9494 1
1M

5%
1/16W
MF-LF
2 402

330PF

10%
50V
CERM 2
402

C9495
330PF

10%
50V
2 CERM
402

SYNC_MASTER=T29
1

DisplayPort/T29 A Connector

100K
5%
1/16W
MF-LF
2 402

DRAWING NUMBER

Apple Inc.

Sink HPD range:


High: 2.0 - 5.0V
Low: 0 - 0.8V

SYNC_DATE=10/16/2010

PAGE TITLE

R9441

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

94 OF 109
SHEET

76 OF 86

PPBUS S0 LCDBkLT FET

CRITICAL
Q9706

MOSFET

FDC638APZ

CHANNEL

P-TYPE

RDS(ON)

43 mOhm @4.5V

LOADING

0.65 A (EDP)

FDC638APZ_SBMS001
SSOT6-HF

PPBUS_SW_LCDBKLT_PWR
5

PPBUS_S0_LCDBKLT_FUSED

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V

603-HF

BOTTOM

C9782

R9788

10%
16V
X5R
402

1%
1/16W
MF-LF
402

70 68 65 54 52 47 42 22 7 6
73 72

PLACE_NEAR=L9701.2:3mm

CRITICAL

CRITICAL

L9701

D9701
SOD-123

33UH-1.8A-110MOHM
8

PPBUS_SW_BKL
CRITICAL

C9712 1

R9789

10UF

147K

PP5V_S0

LCDBKLT_EN_DIV
1

*C9797 AND C9799 SHOULD BE PLACED IN T-BONE FOR ACOUSTICS


*PPBUS_SW_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.
*LCD_BKLT_PWM SHOULD BE AWAY FROM BOOST CIRCUIT

0.1UF

301K

8 77

THERE IS A SENSE RESISTOR BETWEEN


PPBUS_SW_LCDBKLT_PWR
AND PPBUS_SW_BKL
ON THE SENSOR PAGE

PPBUS_G3H

40 36 8 7 6
64 63 50 49

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V

F9700
3AMP-32V-467

1217AS-2SM

C9713
0.1UF

10%
25V 2
X5R
805
PLACE_NEAR=L9701.1:3mm

1%
1/16W
MF-LF
402

10%
2 25V
X5R
402
PLACE_NEAR=L9701.1:3mm

PPBUS_SW_LCDBKLT_PWR_SW
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.375 MM
VOLTAGE=50V
SWITCH_NODE=TRUE
DIDT=TRUE

RB160M-60G

PLACE_NEAR=U9701.A5:3mm

C9796
220PF

10%
2 50V
X7R-CERM
402

LCDBKLT_EN_L

Q9707

PLACE_NEAR=U9701.D1:5mm
1

5
18 8

IN

LCD_BKLT_EN

71 62 61 57 54 52 51 50 49 48
23 22 20 19 18 17 16 12 8 7 6
46 42 41 40 37 36 33 29 27 26
85 75 74 73 72

Q9707

10%
2 16V
CERM
402

10UF

MIN_LINE_WIDTH=0.5 MM
CRITICAL MIN_NECK_WIDTH=0.375 MM
VOLTAGE=50V

6 74

C9799
10UF

10%
2 50V
X5R
1210-1

10%
2 50V
X5R
1210-1
PLACE_NEAR=D9701.2:5mm
PLACE_NEAR=D9701.2:3mm

XW9720

SM
1
2
PPVOUT_SW_LCDBKLT_FB
VOLTAGE=50V
MIN_LINE_WIDTH=0.1 MM PLACE_NEAR=C9797.1:5mm
MIN_NECK_WIDTH=0.1 MM

PP3V3_S0
PLACE_NEAR=U9701.C4:4mm

LCDBKLT_DISABLE

0.01UF

10%
25V 2
X5R
603-1

C9797

C9714

1UF

SOT563

PLACE_NEAR=U9701.D1:3mm
1

C9710

SSM6N15FEAPE

PPVOUT_SW_LCDBKLT

CRITICAL
1

C9711 1

0.1UF

10%
16V
X5R 2
402

SSM6N15FEAPE
SOT563

C
2

BKLT_PLT_RST_L

NO STUFF
1

R9755

C9740
10UF
1

IN

SMBUS_PCH_CLK

R9757
1
SMBUS_PCH_DATA
Addr: 0x58(Wr)/0x59(Rd)

81 62 48 42 31 29 27 23 16

77 8

5%
1/16W
MF-LF
402

PPBUS_SW_LCDBKLT_PWR

R9731
1%
1/16W
MF-LF
402

R9704
IN

LCD_BKLT_PWM

33

5%
1/16W
MF-LF
402

R9715

VSYNC

C2

FILTER

C1
SW_0 B1
SW_1 B2

BKL_ISET

B3

ISET

BKL_FSET

B4

FSET

BKL_SCL
BKL_SDA

D3
D4

SCLK
SDA

OUT1 E5
OUT2 D5

BKL_PWM
BKL_EN

A4

PWM

A3

EN

C3

OUT3 C5
OUT4 E3
OUT5 E2

FAULT

TP_BKL_FAULT

D2

PLACE_SIDE=BOTTOM

FB

1%
1/16W
MF-LF
1 402

C9704

BKLT:PROD

R9717

0 2
PLACE_NEAR=U9701.E5:10mm
1
MIN_LINE_WIDTH=0.5 mm
5%
MIN_NECK_WIDTH=0.20 mm
1/16W
BOTTOM MF-LF

A5

LED_RETURN_1
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

OUT

6 74

OUT

6 74

OUT

6 74

OUT

6 74

OUT

6 74

OUT

6 74

402

CRITICAL

100K

B5

18 8

BKL_FLTR

301K

25-BUMP-MICRO

1%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

BI

10K

U9701

47.0K2
1

R9741

R9753
81 62 48 42 31 29 27 23 16

R9740

BKL_FLTR_R

20%
6.3V
X5R
603

VIN

VDDIO VLDO

NO STUFF

LP8550

BKL_VSYNC

10%
6.3V
X5R
402

NO STUFF

D1

1UF

OUT6 E1

BKL_ISEN1
BKL_ISEN2
BKL_ISEN3
BKL_ISEN4
BKL_ISEN5
BKL_ISEN6

BKLT:PROD

R9718

0 2
PLACE_NEAR=U9701.D5:10mm
1
MIN_LINE_WIDTH=0.5 mm
5%
MIN_NECK_WIDTH=0.20 mm
1/16W
BOTTOM MF-LF

LED_RETURN_2
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

402

BKLT:PROD

GND_SW
GND_SW

IN

C9741

5%
1/16W
MF-LF
2 402

R9719

0 2
PLACE_NEAR=U9701.C5:10mm
1
MIN_LINE_WIDTH=0.5 mm
5%
MIN_NECK_WIDTH=0.20 mm
1/16W
BOTTOM MF-LF

A2

74 6

NO STUFF

10K

5%
1/16W
MF-LF
2 402

GND_L

A1

R9754

E4

C4

IN

BKL_VSYNC_R

GND_S

26

LED_RETURN_3
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

402

33PF

5%
2 50V
CERM
402

I_LED=22.7mA

R97161

90.9K
1%
Fpwm=9.62kHz 1/16W
MF-LF
see spec for others
402 2

BKLT:PROD

R9714

R9720

16.2K

0 2
PLACE_NEAR=U9701.E3:10mm
1
LED_RETURN_4
1%
1/16W
MIN_LINE_WIDTH=0.5 mm
PLACEMENT_NOTE=Keep away from noise nodes(E4, A1, A2, B1, B2 pins) MIN_LINE_WIDTH=0.5 mm
5%
MF-LF
MIN_NECK_WIDTH=0.20 mm
MIN_NECK_WIDTH=0.20 mm
1/16W
2 402
SM
BOTTOM MF-LF
402
1
2
GND_BKL_SGND
MIN_LINE_WIDTH=0.4 MM
BKLT:PROD
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V
0 2
PLACE_NEAR=U9701.E2:10mm
1
LED_RETURN_5
I_LED=369/Riset
MIN_LINE_WIDTH=0.5 mm
MIN_LINE_WIDTH=0.5 mm
5%
(EEPROM should set EN_I_RES=1)
MIN_NECK_WIDTH=0.20 mm
MIN_NECK_WIDTH=0.20 mm
1/16W
BOTTOM MF-LF

XW9710

R9721

402

BKLT:PROD

R9722

0 2
PLACE_NEAR=U9701.E1:10mm
1
MIN_LINE_WIDTH=0.5 mm
5%
MIN_NECK_WIDTH=0.20 mm
1/16W
BOTTOM MF-LF

LED_RETURN_6
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

402

PART NUMBER

QTY

DESCRIPTION

REFERENCE DES

103S0198

RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM

R9717,R9718,R9719

CRITICAL

BOM OPTION
BKLT:ENG

103S0198

RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM

R9720,R9721,R9722

BKLT:ENG

SYNC_MASTER=VEMURI_K90I

10.2 ohm resistors for current


measurement on LED strings.

SYNC_DATE=06/25/2010

PAGE TITLE

LCD Backlight Driver


DRAWING NUMBER

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

97 OF 109
SHEET

77 OF 86

CPU Signal Constraints

CPU Net Properties


TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

CPU_50S

=50_OHM_SE

=50_OHM_SE

=50_OHM_SE

=50_OHM_SE

=STANDARD

=STANDARD

NET_TYPE
ELECTRICAL_CONSTRAINT_SET

PHYSICAL

SPACING

TABLE_PHYSICAL_RULE_ITEM

DMI_S2N

PCIE_85D

PCIE

DMI_S2N

PCIE_85D

PCIE

TABLE_PHYSICAL_RULE_ITEM

CPU_55S

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=STANDARD

=STANDARD
TABLE_PHYSICAL_RULE_ITEM

CPU_27P4S

=27P4_OHM_SE

=27P4_OHM_SE

=27P4_OHM_SE

=27P4_OHM_SE

7 MIL

TABLE_SPACING_RULE_HEAD

LAYER

LINE-TO-LINE SPACING

WEIGHT

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

=STANDARD

9 17

DMI_N2S

PCIE_85D

PCIE

PCIE_85D

PCIE

FDI_DATA

PCIE_85D

PCIE

FDI_DATA

PCIE_85D

PCIE

CPU_50S

CPU_AGTL

FDI_DATA_P<7:0>
FDI_DATA_N<7:0>
FDI_FSYNC<1..0>

CPU_50S

CPU_AGTL

FDI_LSYNC<1..0>

9 17

CPU_50S

CPU_AGTL

FDI_INT

9 17

CPU_PECI

CPU_50S

PCIE

CPU_PECI

10 19 45

PM_SYNC

CPU_50S

CPU_AGTL

PM_MEM_PWRGD

CPU_50S

CPU_AGTL

PM_SYNC
PM_MEM_PWRGD

CPU_50S

CPU_ITP

XDP_DBRESET_L

CPU_50S

CPU_ITP

CPU_50S

CPU_ITP

XDP_CPU_PRDY_L
XDP_CPU_PREQ_L

CPU_50S

CPU_AGTL

WEIGHT

TABLE_SPACING_RULE_ITEM

CPU_AGTL

9 17

DMI_N2S

7 MIL

NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.
SPACING_RULE_SET

DMI_S2N_P<3:0>
DMI_S2N_N<3:0>
DMI_N2S_P<3:0>
DMI_N2S_N<3:0>

9 17
9 17

9 17
9 17
9 17

TABLE_SPACING_RULE_ITEM

CPU_AGTL

TOP,BOTTOM

=2x_DIELECTRIC

TABLE_SPACING_RULE_ITEM

CPU_8MIL

8 MIL

?
TABLE_SPACING_RULE_ITEM

CPU_COMP

20 MIL

CPU_ITP

=2:1_SPACING

CPU_VCCSENSE

25 MIL

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

10 17
10 17 30

Most CPU signals with impedance requirements are 50-ohm single-ended.


Some signals require 27.4-ohm single-ended impedance.
10 23 26

SOURCE: Huron River SFF DG (DG-438297_v1.0), Section 4.18 and Huron River Platform Power Delivery DG v1.0 Section 2.7

PCI-Express

10 23
10 23

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

PCIE_85D

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

TABLE_PHYSICAL_RULE_ITEM

CPU_50S

CPU_AGTL

CPU_SM_RCOMP

CPU_27P4S

CPU_COMP

CPU_SM_RCOMP

CPU_27P4S

CPU_COMP

CPU_SM_RCOMP

CPU_27P4S

CPU_COMP

CPU_50S

CPU_ITP

CPU_50S

CPU_AGTL

CPU_50S

CPU_AGTL

CPU_PROCHOT_L

CPU_50S

CPU_AGTL

CPU_PWRGD

CPU_50S

CPU_AGTL

CPU_PROCHOT_L
CPU_PWRGD

PM_THRMTRIP_L

CPU_50S

CPU_8MIL

PM_THRMTRIP_L

DMI_CLK100M

CLK_PCIE_90D

CLK_PCIE

DMI_CLK100M

CLK_PCIE_90D

CLK_PCIE

ITPCPU_CLK100M

CLK_PCIE_90D

CLK_PCIE

DMI_CLK100M_CPU_P
DMI_CLK100M_CPU_N
ITPCPU_CLK100M_P
ITPCPU_CLK100M_N
ITPXDP_CLK100M_P
ITPXDP_CLK100M_N
XDP_CPU_CLK100M_P
XDP_CPU_CLK100M_N

TABLE_PHYSICAL_RULE_ITEM

CLK_PCIE_90D

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

=3X_DIELECTRIC

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

=4X_DIELECTRIC

CPU_CATERR_L
TABLE_SPACING_RULE_ITEM

PCIE

TABLE_SPACING_RULE_ITEM

PCIE

TOP,BOTTOM

PM_EXT_TS_L<0>
PM_EXT_TS_L<1>
CPU_SM_RCOMP<0>
CPU_SM_RCOMP<1>
CPU_SM_RCOMP<2>
CPU_CFG<11..0>
CPU_CATERR_L
CPU_VCCIO_SEL

10
10
10
9 23
10
12

TABLE_SPACING_RULE_ITEM

CLK_PCIE

20 MIL

SOURCE: Huron River SFF DG (DG-438297_v1.0), Section 4.18 and Huron River Platform Power Delivery DG v1.0 Section 2.7

ITPCPU_CLK100M

CLK_PCIE_90D

CLK_PCIE

I125

ITPCPU_CLK100M

CLK_PCIE_90D

CLK_PCIE

I126

ITPCPU_CLK100M

CLK_PCIE_90D

CLK_PCIE

I127

ITPCPU_CLK100M

CLK_PCIE_90D

CLK_PCIE

I128

ITPCPU_CLK100M

CLK_PCIE_90D

CLK_PCIE

CPU_27P4S

CPU_COMP

CPU_27P4S

CPU_COMP

I121

XDP_TDI

CPU_50S

CPU_ITP

XDP_TDO

CPU_50S

CPU_ITP

XDP_TMS

CPU_50S

CPU_ITP

XDP_TCK

CPU_50S

CPU_ITP

XDP_TRST_L

CPU_50S

CPU_ITP

XDP_BPM_L

CPU_50S

CPU_ITP

XDP_BPM_R_L

CPU_50S

CPU_ITP

(FSB_CPURST_L)

CPU_50S

CPU_ITP

CPU_VCCAXG_SENSE

CPU_27P4S

CPU_VCCSENSE

CPU_VCCAXG_SENSE

CPU_27P4S

CPU_VCCSENSE

CPU_VCCSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_VCCSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_VCCAXG_SENSE

CPU_27P4S

CPU_VCCSENSE

CPU_VCCAXG_SENSE

CPU_27P4S

CPU_VCCSENSE

I115

CPU_VALSENSE

CPU_27P4S

CPU_VCCSENSE

I116

CPU_VALSENSE

CPU_27P4S

CPU_VCCSENSE

I117

CPU_VALSENSE

CPU_27P4S

CPU_VCCSENSE

I118

CPU_VALSENSE

CPU_27P4S

CPU_VCCSENSE

I119

CPU_VALSENSE

CPU_27P4S

CPU_VCCSENSE

I120

CPU_VALSENSE

CPU_27P4S

CPU_VCCSENSE

I122

CPU_SVIDALERT_L

CPU_50S

CPU_COMP

I123

CPU_SVIDSCLK

CPU_50S

CPU_COMP

EDP_COMP
CPU_PEG_COMP

XDP_CPU_TDI
XDP_CPU_TDO
XDP_CPU_TMS
XDP_CPU_TCK
XDP_CPU_TRST_L
XDP_BPM_L<3..0>
CPU_CFG<15..12>
XDP_CPURST_L

CPU_VCCSENSE_P
CPU_VCCSENSE_N
CPU_VCCIOSENSE_P
CPU_VCCIOSENSE_N
CPU_AXG_SENSE_P
CPU_AXG_SENSE_N
CPU_VDDQ_SENSE_P
CPU_VDDQ_SENSE_N
CPU_AXG_VALSENSE_P
CPU_AXG_VALSENSE_N
CPU_VCC_VALSENSE_P
CPU_VCC_VALSENSE_N

10 46 68
10 19 23

10 19

10 16
10 16
10 16
10 16
16 23
16 23
23
23

9
9

10 23
10 23
10 23
10 23
10 23
10 23
9 23
23

12 68

CPU_VCCSA_VID<0>
CPU_VCCSA_VID<1>

12 68
12 70
12 70

12 68
12 68

12
12
9
9
9
9

CPU_VIDALERT_L

I124

CPU_SVIDSOUT

CPU_50S

CPU_COMP

12 68

CPU_VIDSCLK

12 68

CPU_VIDSOUT

12 68

SYNC_MASTER=ANNE_K90I

SYNC_DATE=06/08/2010

PAGE TITLE

PEG_R2D

PEG_D2R

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

PEG_R2D_P<15..0>
PEG_R2D_N<15..0>
PEG_R2D_C_P<15..0>
PEG_R2D_C_N<15..0>
PEG_D2R_P<15..0>
PEG_D2R_N<15..0>
PEG_D2R_C_P<15..0>
PEG_D2R_C_N<15..0>

CPU Constraints
DRAWING NUMBER

Apple Inc.

8
8
8

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

PAGE

100 OF 109
SHEET

78 OF 86

Memory Bus Constraints

Memory Net Properties


TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

MEM_37S

=37_OHM_SE

=37_OHM_SE

=37_OHM_SE

=37_OHM_SE

=STANDARD

=STANDARD

NET_TYPE
ELECTRICAL_CONSTRAINT_SET

PHYSICAL

SPACING

TABLE_PHYSICAL_RULE_ITEM

MEM_A_CLK

MEM_72D

MEM_CLK

MEM_A_CLK

MEM_72D

MEM_CLK

MEM_A_CNTL

MEM_37S

MEM_CTRL

MEM_A_CNTL

MEM_37S

MEM_CTRL

MEM_A_CNTL

MEM_37S

MEM_CTRL

MEM_A_CMD

MEM_40S

MEM_CMD

MEM_A_CMD

MEM_40S

MEM_CMD

MEM_A_CMD

MEM_40S

MEM_CMD

MEM_A_CMD

MEM_40S

MEM_CMD

MEM_A_CMD

MEM_40S

MEM_CMD

MEM_A_DQ_BYTE0

MEM_50S

MEM_DATA

MEM_A_DQ_BYTE1

MEM_50S

MEM_DATA

MEM_A_DQ_BYTE2

MEM_50S

MEM_DATA

MEM_A_DQ_BYTE3

MEM_50S

MEM_DATA

MEM_A_DQ_BYTE4

MEM_50S

MEM_DATA

TABLE_PHYSICAL_RULE_ITEM

MEM_40S

=40_OHM_SE

=40_OHM_SE

=40_OHM_SE

=40_OHM_SE

=STANDARD

=STANDARD

MEM_A_CLK_P<5..0>
MEM_A_CLK_N<5..0>

11 27
11 27

TABLE_PHYSICAL_RULE_ITEM

MEM_72D

=72_OHM_DIFF

=72_OHM_DIFF

=72_OHM_DIFF

=72_OHM_DIFF

=72_OHM_DIFF

=72_OHM_DIFF

MEM_50S

TOP,BOTTOM

=50_OHM_SE

=50_OHM_SE

=50_OHM_SE

=STANDARD

=STANDARD

TABLE_PHYSICAL_RULE_ITEM

MEM_A_CKE<3..0>
MEM_A_CS_L<3..0>
MEM_A_ODT<3..0>

11 27
11 27
11 27

TABLE_PHYSICAL_RULE_ITEM

MEM_85D

TOP,BOTTOM

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF
TABLE_PHYSICAL_RULE_ITEM

MEM_50S

ISL10

=50_OHM_SE

=50_OHM_SE

=50_OHM_SE

=STANDARD

=STANDARD
TABLE_PHYSICAL_RULE_ITEM

MEM_85D

ISL10

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

MEM_50S

ISL3,ISL4,ISL9

=50_OHM_SE

=50_OHM_SE

=50_OHM_SE

=STANDARD

=STANDARD

MEM_85D

ISL3,ISL4,ISL9

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

TABLE_PHYSICAL_RULE_ITEM

MEM_A_A<15..0>
MEM_A_BA<2..0>
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L

11 27
11 27

11 27
11 27
11 27

TABLE_PHYSICAL_RULE_ITEM

MEM_A_DQ_BYTE5

MEM_50S

MEM_DATA

MEM_A_DQ_BYTE6

MEM_50S

MEM_DATA

MEM_A_DQ_BYTE7

MEM_50S

MEM_DATA

MEM_A_DQS0

MEM_85D

MEM_DQS

MEM_A_DQS0

MEM_85D

MEM_DQS

MEM_A_DQS1

MEM_85D

MEM_DQS

MEM_A_DQS1

MEM_85D

MEM_DQS

MEM_A_DQS2

MEM_85D

MEM_DQS

MEM_A_DQS2

MEM_85D

MEM_DQS

MEM_A_DQS3

MEM_85D

MEM_DQS

MEM_A_DQS3

MEM_85D

MEM_DQS

MEM_A_DQS4

MEM_85D

MEM_DQS

MEM_A_DQS4

MEM_85D

MEM_DQS

MEM_A_DQS5

MEM_85D

MEM_DQS

MEM_A_DQS5

MEM_85D

MEM_DQS

MEM_A_DQS6

MEM_85D

MEM_DQS

MEM_A_DQS6

MEM_85D

MEM_DQS

MEM_A_DQS7

MEM_85D

MEM_DQS

MEM_A_DQS7

MEM_85D

MEM_DQS

MEM_B_CLK

MEM_72D

MEM_CLK

TABLE_SPACING_RULE_ITEM

MEM_B_CLK

MEM_72D

MEM_CLK

TABLE_SPACING_RULE_ITEM

MEM_B_CNTL

MEM_37S

MEM_CTRL

MEM_B_CNTL

MEM_37S

MEM_CTRL

MEM_B_CNTL

MEM_37S

MEM_CTRL

MEM_B_CMD

MEM_40S

MEM_CMD

MEM_B_CMD

MEM_40S

MEM_CMD

MEM_B_CMD

MEM_40S

MEM_CMD

MEM_B_CMD

MEM_40S

MEM_CMD

MEM_B_CMD

MEM_40S

MEM_CMD

MEM_B_DQ_BYTE0

MEM_50S

MEM_DATA

MEM_B_DQ_BYTE1

MEM_50S

MEM_DATA

MEM_B_DQ_BYTE2

MEM_50S

MEM_DATA

MEM_B_DQ_BYTE3

MEM_50S

MEM_DATA

MEM_B_DQ_BYTE4

MEM_50S

MEM_DATA

MEM_B_DQ_BYTE5

MEM_50S

MEM_DATA

MEM_B_DQ_BYTE6

MEM_50S

MEM_DATA

MEM_B_DQ_BYTE7

MEM_50S

MEM_DATA

MEM_B_DQS0

MEM_85D

MEM_DQS

MEM_B_DQS0

MEM_85D

MEM_DQS

MEM_B_DQS1

MEM_85D

MEM_DQS

MEM_B_DQS1

MEM_85D

MEM_DQS

MEM_B_DQS2

MEM_85D

MEM_DQS

MEM_B_DQS2

MEM_85D

MEM_DQS

MEM_B_DQS3

MEM_85D

MEM_DQS

MEM_B_DQS3

MEM_85D

MEM_DQS

MEM_B_DQS4

MEM_85D

MEM_DQS

MEM_B_DQS4

MEM_85D

MEM_DQS

MEM_B_DQS5

MEM_85D

MEM_DQS

MEM_B_DQS5

MEM_85D

MEM_DQS

MEM_B_DQS6

MEM_85D

MEM_DQS

MEM_B_DQS6

MEM_85D

MEM_DQS

MEM_B_DQS7

MEM_85D

MEM_DQS

MEM_B_DQS7

MEM_85D

MEM_DQS

C
TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT
TABLE_SPACING_RULE_ITEM

MEM_CLK2MEM

=4:1_SPACING

?
TABLE_SPACING_RULE_ITEM

MEM_CTRL2CTRL

=3:1_SPACING

?
TABLE_SPACING_RULE_ITEM

MEM_CTRL2MEM

=2.5:1_SPACING

MEM_A_DQ<7..0>
MEM_A_DQ<15..8>
MEM_A_DQ<23..16>
MEM_A_DQ<31..24>
MEM_A_DQ<39..32>
MEM_A_DQ<47..40>
MEM_A_DQ<55..48>
MEM_A_DQ<63..56>

MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>

11 28
11 28
11 28
11 28
11 27 28
11 28
11 28
11 28

11 27 28
11 27 28
11 28
11 28
11 28
11 28

11 28
11 28
11 28
11 28
11 28
11 28
11 28
11 28
11 28
11 28

TABLE_SPACING_RULE_ITEM

MEM_CMD2CMD

=1.5:1_SPACING

MEM_CMD2MEM

=3:1_SPACING

MEM_DATA2DATA

=1.5:1_SPACING

MEM_DATA2MEM

=3:1_SPACING

TABLE_SPACING_RULE_ITEM

MEM_B_CLK_P<5..0>
MEM_B_CLK_N<5..0>
MEM_B_CKE<3..0>
MEM_B_CS_L<3..0>
MEM_B_ODT<3..0>

11 29
11 29

11 29
11 29
11 29

TABLE_SPACING_RULE_ITEM

MEM_DQS2MEM

=3:1_SPACING

MEM_2OTHER

25 MILS

TABLE_SPACING_RULE_ITEM

Memory Bus Spacing Group Assignments


TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

MEM_CLK

MEM_CLK

MEM_CLK2MEM

MEM_CLK

MEM_CTRL

MEM_CLK2MEM

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

MEM_CMD

MEM_CLK

MEM_CMD2MEM

MEM_CMD

MEM_CTRL

MEM_CMD2MEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CLK

MEM_CMD

MEM_CLK2MEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CMD

MEM_CMD

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CLK

MEM_DATA

MEM_CLK2MEM

MEM_CLK

MEM_DQS

MEM_CLK2MEM

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

MEM_CMD

MEM_DATA

MEM_CMD2MEM

MEM_CMD

MEM_DQS

MEM_CMD2MEM

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

MEM_DATA

MEM_CLK

MEM_DATA2MEM

MEM_DATA

MEM_CTRL

MEM_DATA2MEM

MEM_DATA

MEM_CMD

MEM_DATA2MEM

MEM_DATA

MEM_DATA

MEM_DATA2DATA

MEM_DATA

MEM_DQS

MEM_DATA2MEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

MEM_CTRL2MEM

MEM_CTRL

MEM_CTRL2CTRL

MEM_CMD

MEM_CTRL2MEM

MEM_DATA

MEM_CTRL2MEM

MEM_CTRL

MEM_DQS

MEM_CTRL2MEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_DQS

MEM_CLK

MEM_DQS2MEM

MEM_CTRL

MEM_DQS2MEM

MEM_CLK

MEM_CMD

MEM_DQS2MEM

MEM_CTRL

MEM_DATA

MEM_DQS2MEM

MEM_CMD

MEM_DQS

MEM_DQS2MEM

MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM

MEM_DATA

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_DQS

MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_DQS

MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_DQS

SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_DQS

MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM

MEM_DQS

MEM_2OTHER

Need to support MEM_*-style wildcards!


DDR3: Sandybridge SFF 2C when routed on Type-3 (Through hole) should follow rPGA guidelines
per Huron River SFF DG rev1.0 (#438297).
DQS intra-pair matching should be within 0.127mm, no inter-pair matching requirement.
DQ to DQS matching per byte lane should be within 0.127mm.
DQS to clock matching should be within [CLK-63.5mm] and [CLK+38.1mm].
CLK intra-pair matching should be within 0.127mm, inter-pair matching should be within 0.0508mm.
CONTROL signals should be matched within [CLK-2.54mm] to [CLK+0.0mm] of CLK pairs.
A/BA/CMD signals should be matched within [CLK-12.7mm] to [CLK+12.7mm] of CLK pairs A/BA/CMD signals to each other should match within 5.08mm.
DQ/DQS/A/BA/cmd signal spacing is 4x dielectric, CLK is 5x dielectric.
Maximum length of any signal from die pad to SODIMM pad is 119.83mm, from procesor ball to SODIMM pad is 88.9mm.
SOURCE: Huron River Platform DG, Rev 1.01 (#436735), Section 2.5

11 29

11 28
11 28
11 28
11 28

11 28 29
11 28
11 28
11 28

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

NET_SPACING_TYPE1

MEM_B_DQ<7..0>
MEM_B_DQ<15..8>
MEM_B_DQ<23..16>
MEM_B_DQ<31..24>
MEM_B_DQ<39..32>
MEM_B_DQ<47..40>
MEM_B_DQ<55..48>
MEM_B_DQ<63..56>

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CTRL

11 29

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CTRL

11 29

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CTRL

11 29

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CLK

MEM_CMD2CMD
TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CTRL

11 29

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_B_A<15..0>
MEM_B_BA<2..0>
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L

MEM_B_DQS_P<0>
MEM_B_DQS_N<0>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<7>
MEM_B_DQS_N<7>

11 28 29
11 28 29
11 28
11 28
11 28
11 28
11 28
11 28
11 28
11 28
11 28
11 28
11 28
11 28

SYNC_MASTER=ANNE_K90I
11 28

SYNC_DATE=05/28/2010

PAGE TITLE

Memory Constraints

11 28

DRAWING NUMBER

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

101 OF 109
SHEET

79 OF 86

Digital Video Signal Constraints

PCH Net Properties


TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

NET_TYPE

TABLE_PHYSICAL_RULE_ITEM

DP_85D

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

LVDS_90D

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

ELECTRICAL_CONSTRAINT_SET

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

=3x_DIELECTRIC

LVDS

=3x_DIELECTRIC

DISPLAYPORT

DP_ML

DP_85D

DISPLAYPORT

DP_EXTA_AUXCH

DP_85D

DISPLAYPORT

DP_EXTA_AUXCH

DP_85D

DISPLAYPORT

LVDS_IG_A_CLK

LVDS_90D

LVDS

LVDS_IG_A_CLK

LVDS_90D

LVDS

LVDS_IG_A_DATA

LVDS_90D

LVDS

LVDS_IG_A_DATA

LVDS_90D

LVDS

LVDS_90D

LVDS

LVDS_90D

LVDS

I213

LVDS_90D

LVDS

I214

LVDS_90D

LVDS

I215

LVDS_90D

LVDS

I216

LVDS_90D

LVDS

SATA_HDD_R2D

SATA_90D

SATA

SATA_HDD_R2D

SATA_90D

SATA

SATA_HDD_R2D_CONN

SATA_90D

SATA

SATA_HDD_R2D_CONN

SATA_90D

SATA

SATA_HDD_D2R

SATA_90D

SATA

SATA_HDD_D2R

SATA_90D

SATA

SATA_HDD_D2R_CONN

SATA_90D

SATA

SATA_HDD_D2R_CONN

SATA_90D

SATA

SATA_ODD_R2D

SATA_90D

SATA

SATA_ODD_R2D

SATA_90D

SATA

SATA_ODD_R2D

SATA_90D

SATA

SATA_ODD_R2D

SATA_90D

SATA

SATA_ODD_D2R

SATA_90D

SATA

SATA_ODD_D2R

SATA_90D

SATA

SATA_HDD_R2D_CONN

SATA_90D

SATA

SATA_HDD_R2D_CONN

SATA_90D

SATA

SATA_HDD_D2R_CONN

SATA_90D

SATA

SATA_HDD_D2R_CONN

SATA_90D

SATA

DP_IG_ML_P<3..0>
DP_IG_ML_N<3..0>
DP_EXTA_AUXCH_C_P
DP_EXTA_AUXCH_C_N

8
8
8 17 75 81
8 17 75 81

TABLE_SPACING_RULE_ITEM

DISPLAYPORT

TOP,BOTTOM

=4x_DIELECTRIC

LVDS

TOP,BOTTOM

=4x_DIELECTRIC

TABLE_SPACING_RULE_ITEM

DP_85D

WEIGHT

TABLE_SPACING_RULE_ITEM

SPACING

DP_ML

TABLE_SPACING_RULE_HEAD

WEIGHT

DISPLAYPORT

PHYSICAL

TABLE_SPACING_RULE_ITEM

LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length.
DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.
DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.
Max length of LVDS/DisplayPort/TMDS traces: 12 inches.
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4.

SATA Interface Constraints

LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_N
LVDS_IG_A_DATA_P<2..0>
LVDS_IG_A_DATA_N<2..0>
NC_LVDS_IG_A_DATAP<3>
NC_LVDS_IG_A_DATAN<3>
LVDS_IG_B_DATA_P<3..0>
LVDS_IG_B_DATA_N<3..0>
TP_LVDS_IG_B_CLKP
TP_LVDS_IG_B_CLKN

18 74
18 74
6 18 74

6 18 74
8 18
8 18
8
8
6 8 18
6 8 18

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

SATA_90D

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

TABLE_SPACING_RULE_HEAD

WEIGHT

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

TABLE_SPACING_RULE_ITEM

SATA

=4x_DIELECTRIC

TABLE_SPACING_RULE_ITEM

SATA

TOP,BOTTOM

=3x_DIELECTRIC

TABLE_SPACING_RULE_ITEM

SATA_ICOMP

8 MIL

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1.

USB 2.0 Interface Constraints


TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP


TABLE_PHYSICAL_RULE_ITEM

PCH_USB_RBIAS

=STANDARD

8 MIL

8 MIL

=STANDARD

=STANDARD

=STANDARD

USB_85D

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

TABLE_SPACING_RULE_ITEM

USB

=2x_DIELECTRIC

TABLE_SPACING_RULE_ITEM

USB

TOP,BOTTOM

=4x_DIELECTRIC

SATA_HDD_R2D_C_P
SATA_HDD_R2D_C_N
SATA_HDD_R2D_P
SATA_HDD_R2D_N
SATA_HDD_D2R_P
SATA_HDD_D2R_N
SATA_HDD_D2R_C_P
SATA_HDD_D2R_C_N
SATA_ODD_R2D_C_P
SATA_ODD_R2D_C_N
SATA_ODD_R2D_P
SATA_ODD_R2D_N
SATA_ODD_D2R_P
SATA_ODD_D2R_N
SATA_HDD_R2D_RC_P
SATA_HDD_R2D_RC_N
SATA_HDD_D2R_RC_P
SATA_HDD_D2R_RC_N

16 42
16 42
6 42
6 42
16 42
16 42
6 42
6 42
16 42
16 42
6 42
6 42
16 42
16 42
42
42
42

42

SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.8

PCH_SATA_ICOMP

SATA_ICOMP

USB_HUB1_UP

USB_85D

USB

USB_85D

USB

USB_85D

USB

USB_85D

USB

USB_EXTA

USB_85D

USB

USB_EXTA

USB_85D

USB

USB_EXTB

USB_85D

USB

USB_85D

USB

USB_85D

USB

USB_85D

USB

USB_85D

USB

USB_85D

USB

USB_85D

USB

USB_85D

USB

USB_85D

USB

USB_85D

USB

USB_85D

USB

USB_85D

USB

USB_BT

USB_85D

USB

USB_BT

USB_85D

USB

USB_TPAD

USB_85D

USB

USB_85D

USB

USB_85D

USB

USB_85D

USB

USB_85D

USB

USB_85D

USB

USB_85D

USB

USB_85D

USB

USB_HUB2_UP

USB_EXTC

I217

USB_EXTD

I218

USB_CAMERA

USB_CAMERA

USB_IR

USB_SDCARD

USB_BRCRYPT

PCH_SATAICOMP
USB_HUB1_UP_P
USB_HUB1_UP_N
USB_HUB2_UP_P
USB_HUB2_UP_N
USB_EXTA_P
USB_EXTA_N
USB_EXTB_P
USB_EXTB_N
USB_EXTC_P
USB_EXTC_N
USB_T29A_P
USB_T29A_N
T29_A_RSVD_P
T29_A_RSVD_N
USB_CAMERA_P
USB_CAMERA_N
USB_CAMERA_CONN_P
USB_CAMERA_CONN_N
USB_BT_P
USB_BT_N
USB_TPAD_P
USB_TPAD_N
USB_IR_P
USB_IR_N
USB_SDCARD_P
USB_SDCARD_N
USB_BRCRYPT_P
USB_BRCRYPT_N
PCH_USB_RBIAS

PCH_USB_RBIAS

PCH_USB_RBIAS

PCH_DIFFCLK_UNUSED_

CLK_PCIE_90D

CLK_PCIE

PCH_DIFFCLK_UNUSED_

CLK_PCIE_90D

CLK_PCIE

CLK_PCIE_90D

CLK_PCIE

CLK_PCIE_90D

CLK_PCIE

PCH_DIFFCLK_UNUSED_

CLK_PCIE_90D

CLK_PCIE

PCH_DIFFCLK_UNUSED_

CLK_PCIE_90D

CLK_PCIE

PCH_DIFFCLK_UNUSED_

CLK_PCIE_90D

CLK_PCIE

PCH_DIFFCLK_UNUSED_

CLK_PCIE_90D

CLK_PCIE

CPU_50S

CLK_PCIE

LPC_CLK33M

CPU_50S

CLK_PCIE

GFX_CLK_DPLLSS

CLK_PCIE_90D

CLK_PCIE

GFX_CLK_DPLLSS

CLK_PCIE_90D

CLK_PCIE

PCIE_CLK100M_PCH_P
PCIE_CLK100M_PCH_N
NC_FSB_CLK133M_PCH_P
NC_FSB_CLK133M_PCH_N
PCH_CLK96M_DOT_P
PCH_CLK96M_DOT_N
PCH_CLK100M_SATA_P
PCH_CLK100M_SATA_N
PCH_CLK14P3M_REFCLK
PCH_CLK33M_PCIIN
GFX_CLK120M_DPLLSS_P
GFX_CLK120M_DPLLSS_N

16
18 24
18 24
18 24
18 24
24 43
24 43
24 43
24 43
8 24
8 24
8 24
8 24
8 75
8 75
18 32
18 32
6 32
6 32

6 24 32
6 24 32
24 53
24 53
24 44
24 44

18

16 25
16 25
8
8
16 25
16 25
16 25
16 25
16 25
16 26

SYNC_MASTER=K91_MLB

SYNC_DATE=05/15/2010

PAGE TITLE

PCH Constraints 1
DRAWING NUMBER

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

102 OF 109
SHEET

80 OF 86

LPC Bus Constraints

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

PCH Net Properties

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

Chipset Net Properties

NET_TYPE

DIFFPAIR NECK GAP


ELECTRICAL_CONSTRAINT_SET

PHYSICAL

SPACING

NET_TYPE

TABLE_PHYSICAL_RULE_ITEM

LPC_50S

=50_OHM_SE

=50_OHM_SE

=50_OHM_SE

=50_OHM_SE

=STANDARD

=STANDARD

ELECTRICAL_CONSTRAINT_SET
TABLE_PHYSICAL_RULE_ITEM

CLK_LPC_50S

=50_OHM_SE

=50_OHM_SE

=50_OHM_SE

=50_OHM_SE

=STANDARD

LPC_AD

LPC_50S

LPC

LPC_FRAME_L

LPC_50S

LPC

LPC_RESET_L

LPC_50S

LPC

LPC_CLK33M

CLK_LPC_50S

CLK_LPC

LPC_CLK33M

CLK_LPC_50S

CLK_LPC

LPC_CLK33M

CLK_LPC_50S

CLK_LPC

=STANDARD

LPC_AD<3..0>
LPC_FRAME_L
LPCPLUS_RESET_L

LAYER

LINE-TO-LINE SPACING

WEIGHT
TABLE_SPACING_RULE_ITEM

LPC

6 MIL

?
TABLE_SPACING_RULE_ITEM

CLK_LPC

8 MIL

DP_EXTA_ML

DP_85D

DISPLAYPORT

I251

DP_EXTA_ML

DP_85D

DISPLAYPORT

6 26 47

SMBus Interface Constraints


LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

SMB_50S

=50_OHM_SE

=50_OHM_SE

=50_OHM_SE

=50_OHM_SE

=STANDARD

=STANDARD

TABLE_PHYSICAL_RULE_ITEM

SMB_50S

SMB

SMBUS_PCH_DATA

SMB_50S

SMB

SMBUS_PCH_0_CLK

SMB_50S

SMB

SMBUS_PCH_0_DATA

SMB_50S

SMB

SMBUS_PCH_1_CLK

SMB_50S

SMB

SMBUS_PCH_1_DATA

SMB_50S

SMB

HDA_BIT_CLK

HDA_50S

HDA

HDA_50S

HDA

HDA_50S

HDA

HDA_50S

HDA

HDA_50S

HDA

HDA_50S

HDA

HDA_50S

HDA

HDA_50S

HDA

HDA_50S

HDA

HDA_50S

HDA

HDA_BIT_CLK
HDA_BIT_CLK_R
HDA_SYNC
HDA_SYNC_R
HDA_RST_R_L
HDA_RST_L
HDA_SDIN0
AUD_SDI_R
HDA_SDOUT
HDA_SDOUT_R

CLK_SLOW_55S

CLK_SLOW

PM_CLK32K_SUSCLK

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

WEIGHT
HDA_SYNC
TABLE_SPACING_RULE_ITEM

SMB

=2x_DIELECTRIC

?
HDA_RST_L

HDA_SDIN0

HD Audio Interface Constraints


TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

HDA_SDOUT

TABLE_PHYSICAL_RULE_ITEM

HDA_50S

=50_OHM_SE

=50_OHM_SE

=50_OHM_SE

=50_OHM_SE

=STANDARD

SMBUS_PCH_CLK
SMBUS_PCH_DATA
SML_PCH_0_CLK
SML_PCH_0_DATA
SML_PCH_1_CLK
SML_PCH_1_DATA

SMBUS_PCH_CLK

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

I253

DP_85D

DISPLAYPORT

18 26

I255

DP_85D

DISPLAYPORT

26 45

I254

DP_EXTA_AUXCH

DP_85D

DISPLAYPORT

6 26 47

I256

DP_EXTA_AUXCH

DP_85D

DISPLAYPORT

I257

DP_85D

DISPLAYPORT

I258

DP_85D

DISPLAYPORT

SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15

SPACING_RULE_SET

LPC_CLK33M_SMC_R
LPC_CLK33M_SMC
LPC_CLK33M_LPCPLUS

16 23 27 29 31 42 48 62 77

LAYER

LINE-TO-LINE SPACING

WEIGHT

=2x_DIELECTRIC

SPI_CLK

SPI_55S

SPI

SPI_55S

SPI

SPI_55S

SPI

SPI_55S

SPI

SPI_MISO

SPI_55S

SPI

SPI_CS0

SPI_55S

SPI

SPI_55S

SPI

TABLE_SPACING_RULE_ITEM

HDA

SPI_MOSI

SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15

SIO Signal Constraints


TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

SPACING_RULE_SET

LAYER

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=STANDARD

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

=STANDARD
PCIE_ENET_R2D

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

WEIGHT
TABLE_SPACING_RULE_ITEM

CLK_SLOW

PCIE_ENET_D2R

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

8 MIL

SPI Interface Constraints

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

PCIE_85D

PCIE

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP


TABLE_PHYSICAL_RULE_ITEM

SPI_55S

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=STANDARD

PCIE_AP_R2D

=STANDARD
PCIE_AP_D2R

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

PCIE_ENET_R2D_P
PCIE_ENET_R2D_N
PCIE_ENET_R2D_C_P
PCIE_ENET_R2D_C_N
PCIE_ENET_D2R_P
PCIE_ENET_D2R_N
PCIE_ENET_D2R_C_P
PCIE_ENET_D2R_C_N
PCIE_AP_R2D_P
PCIE_AP_R2D_N
PCIE_AP_R2D_C_P
PCIE_AP_R2D_C_N
PCIE_AP_D2R_P
PCIE_AP_D2R_N

8 75
75
75
8 17 75
80
8 17 75
80
75

75

16 48
16 48
16 48

16 57
16
16 57
16
16

I267

DP_INT_ML

DP_85D

DISPLAYPORT

16 57

I268

DP_INT_ML

DP_85D

DISPLAYPORT

16 57

I269

DP_INT_AUXCH

DP_85D

DISPLAYPORT

57

I270

DP_INT_AUXCH

DP_85D

DISPLAYPORT

I271

PCIE_T29_R2D

PCIE_85D

PCIE

I273

PCIE_T29_R2D

PCIE_85D

PCIE
PCIE

DP_INT_ML_C_P<3..0>
DP_INT_ML_C_N<3..0>
DP_INT_AUXCH_C_P
DP_INT_AUXCH_C_N

16 57
16

I272

PCIE_85D

16 47

I274

PCIE_85D

PCIE

47

I276

PCIE_T29_D2R

PCIE_85D

PCIE

16 47

I275

PCIE_T29_D2R

PCIE_85D

PCIE

47

I277

PCIE_85D

PCIE

16 47

I278

PCIE_85D

PCIE

PCIE_T29_R2D_C_P<3..0>
PCIE_T29_R2D_C_N<3..0>
PCIE_T29_R2D_P<3..0>
PCIE_T29_R2D_N<3..0>
PCIE_T29_D2R_P<3..0>
PCIE_T29_D2R_N<3..0>
PCIE_T29_D2R_C_P<3..0>
PCIE_T29_D2R_C_N<3..0>

16 47

I279

PCIE_CLK100M_T29

CLK_PCIE_90D

CLK_PCIE

I280

PCIE_CLK100M_T29

CLK_PCIE_90D

CLK_PCIE

47

DIFFPAIR NECK GAP


TABLE_PHYSICAL_RULE_ITEM

CLK_SLOW_55S

SPI_CLK_R
SPI_CLK
SPI_MOSI_R
SPI_MOSI
SPI_MISO
SPI_CS0_R_L
SPI_CS0_L

8 75

16 48

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

DP_EXTA_ML_C_P<3..0>
DP_EXTA_ML_C_N<3..0>
DP_EXTA_ML_P<3..0>
DP_EXTA_ML_N<3..0>
DP_EXTA_AUXCH_C_P
DP_EXTA_AUXCH_C_N
DP_EXTA_AUXCH_P
DP_EXTA_AUXCH_N

16 23 27 29 31 42 48 62 77

=STANDARD
PM_SUS_CLK

SPACING

I252
6 16 45 47

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

PHYSICAL

6 16 45 47

PCIE_CLK100M_T29_P
PCIE_CLK100M_T29_N

8 34
8 34
34
34
8 34
8 34
34
34

16 34
16 34

37

37
16 37

Clock Net Properties

16 37

NET_TYPE
16 37

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

SPACING

16 37
37

I281

SYSCLK_CLK32K_RTC

CLK_SLOW_55S

CLK_SLOW

SYSCLK_CLK32K_RTC

I282

SYSCLK_CLK25M_SB

CLK_25M_55S

CLK_25M

SYSCLK_CLK25M_SB
SYSCLK_CLK25M_SB_R
SYSCLK_CLK25M_ENET
SYSCLK_CLK25M_ENET_R
SYSCLK_CLK25M_T29
SYSCLK_CLK25M_T29_R

37

I283

CLK_25M_55S

CLK_25M

6 32

I284

CLK_25M_55S

CLK_25M

16 32

I285

CLK_25M_55S

CLK_25M

16 32

I286

CLK_25M_55S

CLK_25M

16 32

I287

CLK_25M_55S

CLK_25M

6 32

SYSCLK_CLK25M_T29

16 26

16 26
16
26 37

26 34
34

16 32

TABLE_SPACING_RULE_ITEM

SPI

8 MIL

PCIE_FW_R2D

PCIE_FW_D2R

DisplayPort Signal Constraints

PCIE_AP_D2R
TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

DP_85D

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

SPACING_RULE_SET

LAYER

PCIE_AP_R2D
TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

WEIGHT

=3x_DIELECTRIC

LAYER

LINE-TO-LINE SPACING

DISPLAYPORT

TOP,BOTTOM

=4x_DIELECTRIC

CLK_PCIE_90D

CLK_PCIE

CLK_PCIE_90D

CLK_PCIE

CLK_PCIE_90D

CLK_PCIE

CLK_PCIE_90D

CLK_PCIE

CLK_PCIE_90D

CLK_PCIE

CLK_PCIE_90D

CLK_PCIE

CLK_PCIE_90D

CLK_PCIE

CLK_PCIE_90D

CLK_PCIE

CLK_PCIE_90D

CLK_PCIE

CLK_PCIE_90D

CLK_PCIE

I235

CPU_27P4S

CPU_COMP

I236

CPU_27P4S

CPU_COMP

I237

CPU_27P4S

CPU_COMP

I238

CPU_27P4S

CPU_COMP

I239

CPU_27P4S

CPU_COMP

I240

CPU_27P4S

CPU_COMP

I241

CPU_27P4S

CPU_COMP

I242

CPU_27P4S

CPU_COMP

I243

CPU_27P4S

CPU_COMP

I244

CPU_27P4S

CPU_COMP

I245

CPU_27P4S

CPU_COMP

I246

CPU_27P4S

CPU_COMP

I247

CPU_27P4S

CPU_COMP

I248

CPU_27P4S

CPU_COMP

I249

CPU_27P4S

CPU_COMP

I250

CPU_27P4S

CPU_COMP

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

PCIE_85D

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

MCP_PE1_REFCLK

TABLE_PHYSICAL_RULE_ITEM

MCP_PE2_REFCLK

TABLE_PHYSICAL_RULE_ITEM

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

=3X_DIELECTRIC

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

TABLE_SPACING_RULE_ITEM

20 MIL

PCIE

TOP,BOTTOM

=4X_DIELECTRIC

System Clock Signal Constraints


TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP


TABLE_PHYSICAL_RULE_ITEM

CLK_SLOW_55S

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=STANDARD

=STANDARD
TABLE_PHYSICAL_RULE_ITEM

CLK_25M_55S

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=STANDARD

=STANDARD

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT
TABLE_SPACING_RULE_ITEM

CLK_SLOW

=2x_DIELECTRIC

CLK_25M

=5x_DIELECTRIC

16 39
16 39
39
39

6 32
6 32
32
32

NC_PEG_CLK100MP
NC_PEG_CLK100MN
PCIE_CLK100M_ENET_P
PCIE_CLK100M_ENET_N
PCIE_CLK100M_AP_P
PCIE_CLK100M_AP_N
PCIE_CLK100M_FW_P
PCIE_CLK100M_FW_N
NC_PCIE_CLK100M_EXCARDP
NC_PCIE_CLK100M_EXCARDN

8 16
8 16
16 37
16 37
16 32
16 32
16 39
16 39
8 16
8 16

WEIGHT

TABLE_SPACING_RULE_ITEM

CLK_PCIE

16 39

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

PCIE

16 39

TABLE_SPACING_RULE_ITEM

PCI-Express Signal Constraints

39

WEIGHT

PCIE_CLK100M_ENET

CLK_PCIE_90D

PCIE_AP_D2R_PI_P
PCIE_AP_D2R_PI_N
PCIE_AP_R2D_PI_P
PCIE_AP_R2D_PI_N

39

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

TABLE_SPACING_RULE_ITEM

DISPLAYPORT

PCIE_FW_R2D_P
PCIE_FW_R2D_N
PCIE_FW_R2D_C_P
PCIE_FW_R2D_C_N
PCIE_FW_D2R_P
PCIE_FW_D2R_N
PCIE_FW_D2R_C_P
PCIE_FW_D2R_C_N

TABLE_SPACING_RULE_ITEM

NOTE: 25MHz system clocks very sensitive to noise.

PCH_VSS_NCTF<1>
PCH_VSS_NCTF<2>
PCH_VSS_NCTF<5>
TP_PCH_VSS_NCTF<7>
PCH_VSS_NCTF<9>
PCH_VSS_NCTF<9>
PCH_VSS_NCTF<11>
PCH_VSS_NCTF<12>
PCH_VSS_NCTF<15>
PCH_VSS_NCTF<17>
PCH_VSS_NCTF<19>
PCH_VSS_NCTF<21>
PCH_VSS_NCTF<22>
PCH_VSS_NCTF<25>
PCH_VSS_NCTF<27>
PCH_VSS_NCTF<29>

6
6
6

6 81
6 81
6
6
6
6
6
6

SYNC_MASTER=K91_MLB

SYNC_DATE=05/15/2010

PAGE TITLE

PCH Constraints 2

DRAWING NUMBER

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

103 OF 109
SHEET

81 OF 86

CAESAR IV (Ethernet) Constraints

Ethernet Net Properties


TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

ENET_50S

=50_OHM_SE

=50_OHM_SE

=50_OHM_SE

=50_OHM_SE

=STANDARD

=STANDARD

NET_TYPE
ELECTRICAL_CONSTRAINT_SET

PHYSICAL

SPACING

TABLE_PHYSICAL_RULE_ITEM

ENET_50S

ENET_3X

ENET_50S

ENET_3X

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

=3:1_SPACING

ENET_50S

ENET_3X

ENET_100D

ENET_MDI

ENET_100D

ENET_MDI

BCM5764_CLK25M_XTALI
BCM5764_CLK25M_XTALO
ENET_RESET_L

33 37

TABLE_SPACING_RULE_ITEM

ENET_3X

ENET_MDI

ENET_MDI_P<3..0>
ENET_MDI_N<3..0>

37 38
37 38

SOURCE: Broadcom 5764-DS04-RDS Page 38


TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

I166

CR_DATA

ENET_50S

ENET_CR_DATA

I167

CR_DATA

ENET_50S

ENET_CR_DATA

I168

CR_CLK

ENET_50S

ENET_CR_DATA

I169

CR_DATA

ENET_50S

ENET_CR_DATA

I170

CR_DATA

ENET_50S

ENET_CR_DATA

I171

CR_CLK

ENET_50S

ENET_CR_DATA

I172

CR_CLK

ENET_50S

ENET_CR_DATA

TABLE_SPACING_RULE_ITEM

ENET_CR_DATA

8MIL

CAESAR IV (Ethernet PHY) Constraints


TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

ENET_CR_DATA<7..0>
ENET_CR_CMD
ENET_CR_CLK
SDCONN_DATA<7..0>
SDCONN_CMD
SDCONN_CLK
SDCONN_CLK_L

33 37
33 37

33 37
33
33
33
33

DIFFPAIR NECK GAP


TABLE_PHYSICAL_RULE_ITEM

ENET_100D

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

0.6 MM

TABLE_SPACING_RULE_ITEM

ENET_MDI

SOURCE: Broadcom 5764-DS04-RDS Page 38

FireWire Interface Constraints

FireWire Net Properties


TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

FW_110D

=110_OHM_DIFF

=110_OHM_DIFF

=110_OHM_DIFF

=110_OHM_DIFF

=110_OHM_DIFF

=110_OHM_DIFF

NET_TYPE
PHYSICAL

ELECTRICAL_CONSTRAINT_SET

SPACING

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

I158

FW_P0_TPA

FW_110D

FW_TP

I159

FW_P0_TPA

FW_110D

FW_TP

I160

FW_P0_TPB

FW_110D

FW_TP

I161

FW_P0_TPB

FW_110D

FW_TP

I162

FW_P1_TPA

FW_110D

FW_TP

I163

FW_P1_TPA

FW_110D

FW_TP

I164

FW_P1_TPB

FW_110D

FW_TP

I165

FW_P1_TPB

FW_110D

FW_TP

TABLE_SPACING_RULE_ITEM

FW_TP

=3:1_SPACING

NC_FW0_TPAP
NC_FW0_TPAN
NC_FW0_TPBP
NC_FW0_TPBN
FW_PORT1_TPA_P
FW_PORT1_TPA_N
FW_PORT1_TPB_P
FW_PORT1_TPB_N

6 39 41
39 41
6 39 41
6 39 41
39 41
39 41
39 41
39 41

Port 2 Not Used

SYNC_MASTER=K91_MLB

SYNC_DATE=05/15/2010

PAGE TITLE

Ethernet/FW Constraints
DRAWING NUMBER

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

104 OF 109
SHEET

82 OF 86

DisplayPort Signal Constraints

4
ELECTRICAL_CONSTRAINT_SET

T29 I2C Signal Constraints

I1

TABLE_PHYSICAL_RULE_HEAD

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

I2

TABLE_PHYSICAL_RULE_ITEM

T29_I2C_55S

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=STANDARD

=55_OHM_SE

I3

=STANDARD

I4

LAYER

LINE-TO-LINE SPACING

WEIGHT

I7

TABLE_SPACING_RULE_ITEM

T29_I2C

I6

=2x_DIELECTRIC

T29_R2D0
T29_R2D0
T29_R2D1
T29_R2D1

I5

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

I8

D T29 SPI Signal Constraints

I9
I10

T29_D2R0
T29_D2R0
T29_D2R1
T29_D2R1

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

T29_SPI_55S

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=55_OHM_SE

=STANDARD

=STANDARD

I11
I12

TABLE_PHYSICAL_RULE_ITEM

I13
I15

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

I14

TABLE_SPACING_RULE_ITEM

T29_SPI

I17

=2x_DIELECTRIC

I16
I18

T29/DP Connector Signal Constraints

I19
TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

T29DP_80D

=80_OHM_DIFF

=80_OHM_DIFF

=80_OHM_DIFF

=80_OHM_DIFF

=80_OHM_DIFF

=80_OHM_DIFF

I20
I21

TABLE_PHYSICAL_RULE_ITEM

I22

DP_SDRVA_ML_EVEN
DP_SDRVA_ML_EVEN
DP_SDRVA_ML_ODD
DP_SDRVA_ML_ODD
DP_SDRVA_AUXCH
DP_SDRVA_AUXCH

TABLE_PHYSICAL_RULE_ITEM

T29DP_100D

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

I23

=100_OHM_DIFF

I24
TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

TABLE_SPACING_RULE_HEAD

WEIGHT

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

=5x_DIELECTRIC

I25

WEIGHT

TABLE_SPACING_RULE_ITEM

T29DP

I26

TABLE_SPACING_RULE_ITEM

T29DP

TOP,BOTTOM

=7x_DIELECTRIC

I27
I28
I30
I29

SOURCE: Bill Corneliuss T29 Routing Notes


I31
I32

I34
I33

T29_R2D2
T29_R2D2
T29_R2D3
T29_R2D3

I35
I36
I37
I39
I38
I40

T29_D2R2
T29_D2R2
T29_D2R3
T29_D2R3

I41
I42
I43
I44
I46
I45
I47
I48
I49
I50
I51
I52

DP_SDRVB_ML_EVEN
DP_SDRVB_ML_EVEN
DP_SDRVB_ML_ODD
DP_SDRVB_ML_ODD
DP_SDRVB_AUXCH
DP_SDRVB_AUXCH

I53
I54
I55
I56
I57

B T29 IC Net Properties


ELECTRICAL_CONSTRAINT_SET
I62
I61
I63
I64

DP_T29SNK0_ML
DP_T29SNK0_ML

I65
I66
I67
I68

DP_T29SNK0_AUXCH
DP_T29SNK0_AUXCH

I69
I70
I71
I72

DP_T29SNK1_ML
DP_T29SNK1_ML

I74
I73
I75
I76

DP_T29SNK1_AUXCH
DP_T29SNK1_AUXCH

I77
I78
I79
I80

I81
I82

I83
I84
I85
I86

T29_SPI_CLK
T29_SPI_MOSI
T29_SPI_MISO
T29_SPI_CS_L

I87
I88
I89
I90

I58
I59

NET_TYPE
SPACING
PHYSICAL

I60

DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D

DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT

DP_T29SNK0_ML_C_P<3..0>
DP_T29SNK0_ML_C_N<3..0>
DP_T29SNK0_ML_P<3..0>
DP_T29SNK0_ML_N<3..0>
DP_T29SNK0_AUXCH_C_P
DP_T29SNK0_AUXCH_C_N
DP_T29SNK0_AUXCH_P
DP_T29SNK0_AUXCH_N

DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D

DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT

DP_T29SNK1_ML_C_P<3..0>
DP_T29SNK1_ML_C_N<3..0>
DP_T29SNK1_ML_P<3..0>
DP_T29SNK1_ML_N<3..0>
DP_T29SNK1_AUXCH_C_P
DP_T29SNK1_AUXCH_C_N
DP_T29SNK1_AUXCH_P
DP_T29SNK1_AUXCH_N

DP_85D
DP_85D
DP_85D
DP_85D

DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT

DP_T29SRC_ML_C_P<3..0>
DP_T29SRC_ML_C_N<3..0>
DP_T29SRC_AUXCH_C_P
DP_T29SRC_AUXCH_C_N

T29_I2C_55S
T29_I2C_55S

T29_I2C
T29_I2C

I2C_T29_SCL
I2C_T29_SDA

T29_SPI_55S
T29_SPI_55S
T29_SPI_55S
T29_SPI_55S

T29_SPI
T29_SPI
T29_SPI
T29_SPI

T29_SPI_CLK
T29_SPI_MOSI
T29_SPI_MISO
T29_SPI_CS_L

T29DP_80D
T29DP_80D
T29DP_100D
T29DP_100D

T29DP
T29DP
T29DP
T29DP

T29_R2D_C_P<3..0>
T29_R2D_C_N<3..0>
T29_D2R_P<3..0>
T29_D2R_N<3..0>

T29/DP Net Properties

NOTE: DisplayPort Physical/Spacing Constraints provided by Chipset or GPU page.

PHYSICAL_RULE_SET

3
NET_TYPE
SPACING
PHYSICAL
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_100D
T29DP_100D
T29DP_100D
T29DP_100D
T29DP_100D
T29DP_100D

T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP

T29_R2D_P<0>
T29_R2D_N<0>
T29_R2D_P<1>
T29_R2D_N<1>
T29_R2D_C_F_P<1..0>
T29_R2D_C_F_N<1..0>
T29_D2R_C_P<0>
T29_D2R_C_N<0>
T29_D2R_C_P<1>
T29_D2R_C_N<1>
T29DPA_D2R1_AUXCH_P
T29DPA_D2R1_AUXCH_N

T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D

T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP

DP_SDRVA_ML_C_P<3..0>
DP_SDRVA_ML_C_N<3..0>
DP_SDRVA_ML_R_P<3..0>
DP_SDRVA_ML_R_N<3..0>
DP_SDRVA_ML_P<2..0:2>
DP_SDRVA_ML_N<2..0:2>
DP_SDRVA_ML_P<3..1:2>
DP_SDRVA_ML_N<3..1:2>
DP_SDRVA_AUXCH_P
DP_SDRVA_AUXCH_N
DP_SDRVA_AUXCH_C_P
DP_SDRVA_AUXCH_C_N

T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D

T29DP
T29DP
T29DP
T29DP
T29DP
T29DP

T29DPA_ML_P<3..0>
T29DPA_ML_N<3..0>
T29DPA_ML_C_P<3..0>
T29DPA_ML_C_N<3..0>
DP_A_EXT_AUXCH_P
DP_A_EXT_AUXCH_N

T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_100D
T29DP_100D
T29DP_100D
T29DP_100D
T29DP_100D
T29DP_100D

T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP

T29_R2D_P<2>
T29_R2D_N<2>
T29_R2D_P<3>
T29_R2D_N<3>
T29_R2D_C_F_P<3..2>
T29_R2D_C_F_N<3..2>
T29_D2R_C_P<2>
T29_D2R_C_N<2>
T29_D2R_C_P<3>
T29_D2R_C_N<3>
T29DPB_D2R3_AUXCH_P
T29DPB_D2R3_AUXCH_N

T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D

T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP
T29DP

DP_SDRVB_ML_C_P<3..0>
DP_SDRVB_ML_C_N<3..0>
DP_SDRVB_ML_R_P<3..0>
DP_SDRVB_ML_R_N<3..0>
DP_SDRVB_ML_P<2..0:2>
DP_SDRVB_ML_N<2..0:2>
DP_SDRVB_ML_P<3..1:2>
DP_SDRVB_ML_N<3..1:2>
DP_SDRVB_AUXCH_P
DP_SDRVB_AUXCH_N
DP_SDRVB_AUXCH_C_P
DP_SDRVB_AUXCH_C_N

T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D
T29DP_80D

T29DP
T29DP
T29DP
T29DP
T29DP
T29DP

T29DPB_ML_P<3..0>
T29DPB_ML_N<3..0>
T29DPB_ML_C_P<3..0>
T29DPB_ML_C_N<3..0>
DP_B_EXT_AUXCH_P
DP_B_EXT_AUXCH_N

75
75
75
75
75
75
75 76
75 76

75 76
75 76
76
76

75
75
75
75
75 83
75 83
75
75
75
75
75
75

75 76
75 76
75 76
75 76
75 76
75 76

Only used on dual-port hosts.


83
83

8 34
8 34
34
34
8 17 34
8 17 34
34
34

8 34
8 34
34
34
8 17 34
8 17 34
34
34

Only used on hosts supporting T29 video-in

34 48 75

SYNC_MASTER=Master
34 48 75

SYNC_DATE=06/21/2010

PAGE TITLE

T29 Constraints
34

DRAWING NUMBER

Apple Inc.

34
34

SIZE

34

REVISION

NOTICE OF PROPRIETARY PROPERTY:

BRANCH

8 34 75

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8 34 75
8 34 75
8 34 75

PAGE

105 OF 109
SHEET

83 OF 86

SMC SMBus Net Properties


TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

1TO1_DIFFPAIR

=STANDARD

=STANDARD

=STANDARD

=STANDARD

0.1 MM

0.1 MM

NET_TYPE
ELECTRICAL_CONSTRAINT_SET

PHYSICAL

SPACING

TABLE_PHYSICAL_RULE_ITEM

SMBUS_SMC_A_S3_SCL

SMB_50S

SMB

SMBUS_SMC_A_S3_SDA

SMB_50S

SMB

SMBUS_SMC_B_S0_SCL

SMB_50S

SMB

SMBUS_SMC_B_S0_SDA

SMB_50S

SMB

SMBUS_SMC_0_S0_SCL

SMB_50S

SMB

SMBUS_SMC_0_S0_SDA

SMB_50S

SMB

SMBUS_SMC_BSA_SCL

SMB_50S

SMB

SMBUS_SMC_BSA_SDA

SMB_50S

SMB

SMBUS_SMC_MGMT_SCL

SMB_50S

SMB

SMBUS_SMC_MGMT_SDA

SMB_50S

SMB

SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SDA
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
SMBUS_SMC_MGMT_SCL
SMBUS_SMC_MGMT_SDA

6 32 45 48 54 55
6 32 45 48 54 55
45 48 51
45 48 51
6 32 45 48 51
6 32 45 48 51
6 45 48 63 64
6 45 48 63 64

45 48
45 48

SMBus Charger Net Properties


NET_TYPE
PHYSICAL

ELECTRICAL_CONSTRAINT_SET
CHGR_CSI

1TO1_DIFFPAIR
1TO1_DIFFPAIR

CHGR_CSO

1TO1_DIFFPAIR
1TO1_DIFFPAIR

SPACING

CHGR_CSI_P
CHGR_CSI_N

64
64

CHGR_CSO_P
CHGR_CSO_N

64
64

SYNC_MASTER=K91_MLB

SYNC_DATE=05/15/2010

PAGE TITLE

SMC Constraints
DRAWING NUMBER

Apple Inc.

SIZE

D
REVISION

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BRANCH

PAGE

106 OF 109
SHEET

84 OF 86

5
TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

K90i Specific Net Properties

K90i Specific Net Properties

NET_TYPE

NET_TYPE

TABLE_PHYSICAL_RULE_ITEM

SENSE_1TO1_55S

=55_OHM_SE

=1:1_DIFFPAIR

=55_OHM_SE

=55_OHM_SE

=1:1_DIFFPAIR

=1:1_DIFFPAIR

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

SPACING

THERM_1TO1_55S

=55_OHM_SE

=1:1_DIFFPAIR

=55_OHM_SE

=55_OHM_SE

=1:1_DIFFPAIR

ELECTRICAL_CONSTRAINT_SET

ENET_100D

ENETCONN

ENETCONN_P<3..0>

38

ENET_100D

ENETCONN

ENETCONN_N<3..0>

38

SATA_90D

SATA

SATA_ODD_D2R_UF_P

6 42

SATA_90D

SATA

SATA_ODD_D2R_UF_N

6 42

SATA_90D

SATA

SATA_HDD_D2R_RDRVR_OUT_P

42

SATA_90D

SATA

SATA_HDD_D2R_RDRVR_OUT_N

42

SATA

SATA_HDD_R2D_RDRVR_IN_P

42

TABLE_PHYSICAL_RULE_ITEM

PHYSICAL

SPACING

=1:1_DIFFPAIR
TABLE_PHYSICAL_RULE_ITEM

DIFFPAIR

=1:1_DIFFPAIR

=1:1_DIFFPAIR

=1:1_DIFFPAIR

=1:1_DIFFPAIR

PCIE_CLK100M_AP
TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

WEIGHT

SATA_90D
TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

SENSE

=2:1_SPACING

THERM

=2:1_SPACING

CPU_COMP

GND

SATA_90D

GND_P2MM

SATA

SATA_HDD_R2D_RDRVR_IN_N

PCIE_CLK100M_AP_CONN_P
PCIE_CLK100M_AP_CONN_N
CHGR_CSI_R_P
CHGR_CSI_R_N
CHGR_CSO_R_P
CHGR_CSO_R_N

42

I295

SATA_90D

SATA

SATA_HDD_D2R_RDRVR_IN_P

I298

SATA_90D

SATA

SATA_HDD_D2R_RDRVR_IN_N

42

I297

SATA_90D

SATA

SATA_HDD_R2D_RDRVR_OUT_P

42

I296

SATA_90D

SATA

TABLE_SPACING_ASSIGNMENT_ITEM

CPU_VCCSENSE

GND

42

1TO1_DIFFPAIR

GND_P2MM

=2:1_SPACING

CLK_PCIE

1TO1_DIFFPAIR

TABLE_SPACING_RULE_ITEM

CLK_PCIE

CLK_PCIE_90D

1TO1_DIFFPAIR
TABLE_SPACING_RULE_ITEM

AUDIO

CLK_PCIE_90D

SATA_HDD_R2D_RDRVR_OUT_N

1TO1_DIFFPAIR

6 32

64
50 64
50 64

(USB_EXTA)

USB_85D

USB

USB2_EXTA_MUXED_P

43

(USB_EXTA)

USB_85D

USB

USB2_EXTA_MUXED_N

43

42

THERM_1TO1_55S

THERM

CPUTHMSNS_D2_P

51

(USB_EXTA)

USB_85D

USB

THERM_1TO1_55S

THERM

CPUTHMSNS_D2_N

51

(USB_EXTA)

USB_85D

USB

USB2_LT1_P
USB2_LT1_N

SENSE_DIFFPAIR

THERM_1TO1_55S

THERM

CPU_THERMD_P

9 51

THERM_1TO1_55S

THERM

CPU_THERMD_N

9 51

SENSE_DIFFPAIR

THERM_1TO1_55S

THERM

T29_THERMD_P

34 51

THERM_1TO1_55S

THERM

T29_THERMD_N

51

THERM_1TO1_55S

THERM

T29THMSNS_D2_P

51

USB_85D

USB

CONN_USB2_BT_P

THERM_1TO1_55S

THERM

T29THMSNS_D2_N

51

USB_85D

USB

CONN_USB2_BT_N

USB_85D

USB

USB_85D

USB

SENSE_DIFFPAIR

6 32

64

43
43

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

I287

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

ENETCONN

25 MILS

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

ENET_MDI

GND

GND_P2MM

I288

?
TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

SENSE_DIFFPAIR

TABLE_SPACING_RULE_ITEM

GND

=STANDARD

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

CLK_PCIE

GND

GND_P2MM

USB_LT2_P
USB_LT2_N

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

PCIE

GND

GND_P2MM

SATA

GND

GND_P2MM

SENSE_DIFFPAIR

SENSE_1TO1_55S

SENSE

LAYER

LINE-TO-LINE SPACING

WEIGHT

0.20 MM

1000

SENSE_1TO1_55S

SENSE

SENSE_1TO1_55S

SENSE

SENSE_1TO1_55S

SENSE

USB

GND

SENSE_1TO1_55S

SENSE

GND_P2MM

0.20 MM

SENSE_DIFFPAIR
TABLE_SPACING_ASSIGNMENT_ITEM

1000
CLK_PCIE

SB_POWER

PWR_P2MM

SENSE_1TO1_55S

SENSE

ISNS_HS_OTHER_N
ISNS_HS_OTHER_P
CPUVCCIOS0_CS_N
CPUVCCIOS0_CS_P

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE2

AREA_TYPE

SATA

SB_POWER

DISPLAYPORT

50

SPK_OUT

DIFFPAIR

AUDIO

49 70

SPK_OUT

DIFFPAIR

AUDIO

49 70

SPK_OUT

DIFFPAIR

AUDIO

SPK_OUT

DIFFPAIR

AUDIO

SPK_OUT

DIFFPAIR

AUDIO

49 68 69

SPK_OUT

DIFFPAIR

AUDIO

49 69

I299

AUD_DIFF

1TO1_DIFFPAIR

AUDIO

49 68 69

I300

AUD_DIFF

1TO1_DIFFPAIR

AUDIO

SPKRAMP_L_P_OUT
SPKRAMP_L_N_OUT
SPKRAMP_SUB_P_OUT
SPKRAMP_SUB_N_OUT
SPKRAMP_R_P_OUT
SPKRAMP_R_N_OUT
SSM2315_SUB_N
SSM2315_SUB_P
SSM2315_L_N
SSM2315_L_P
SSM2315_R_N
SSM2315_R_P
AUD_LO2_N_R
AUD_LO2_P_R
AUD_LO1_N_R
AUD_LO1_P_R
AUD_LO2_N_L
AUD_LO2_P_L
SPKRAMP_INL_P
SPKRAMP_INL_N
SPKRAMP_INR_P
SPKRAMP_INR_N
SPKRAMP_INSUB_P
SPKRAMP_INSUB_N

PWR_P2MM

SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CLK

GND

USB

SB_POWER

PWR_P2MM

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_55S

SENSE

SENSE_DIFFPAIR

SENSE_1TO1_55S

SENSE

CPUIMVP_ISNS1_N
CPUIMVP_ISNS2_P

SENSE_1TO1_55S

SENSE

CPUIMVP_ISNS2_N

49 69

I302

AUD_DIFF

1TO1_DIFFPAIR

AUDIO

SENSE_DIFFPAIR

SENSE_1TO1_55S

SENSE

I301

AUD_DIFF

1TO1_DIFFPAIR

AUDIO

SENSE

CPUIMVP_ISNS1G_P
CPUIMVP_ISNS1G_N

49 69

SENSE_1TO1_55S

49 69

I304

AUD_DIFF

1TO1_DIFFPAIR

AUDIO

SENSE_DIFFPAIR

SENSE_1TO1_55S

SENSE

CPUIMVP_ISUM_R_P

49

I303

AUD_DIFF

1TO1_DIFFPAIR

AUDIO

SENSE_1TO1_55S

SENSE

I305

AUD_DIFF

1TO1_DIFFPAIR

AUDIO

SENSE_1TO1_55S

SENSE

CPUIMVP_ISUM_R_N
CPUIMVP_ISUMG_R_P

49

SENSE_DIFFPAIR

49

I307

AUD_DIFF

1TO1_DIFFPAIR

AUDIO

SENSE_1TO1_55S

SENSE

CPUIMVP_ISUMG_R_N

49

I306

AUD_DIFF

1TO1_DIFFPAIR

AUDIO

SENSE_1TO1_55S

SENSE

CPUIMVP_ISNS_P

49

I310

AUD_DIFF

1TO1_DIFFPAIR

AUDIO

SENSE_1TO1_55S

SENSE

CPUIMVP_ISNS_N

49

I308

AUD_DIFF

1TO1_DIFFPAIR

AUDIO

SENSE_1TO1_55S

SENSE

VCCSAS0_CS_P

65

I309

AUD_DIFF

1TO1_DIFFPAIR

AUDIO

SENSE_1TO1_55S

SENSE

VCCSAS0_CS_N

65

I311

AUD_DIFF

1TO1_DIFFPAIR

AUDIO

SENSE_1TO1_55S

SENSE

CPUIMVP_ISUMG_P

68 69

I312

AUD_DIFF

1TO1_DIFFPAIR

AUDIO

SENSE_1TO1_55S

SENSE

CPUIMVP_ISUMG_N

68 69

I313

AUD_DIFF

1TO1_DIFFPAIR

AUDIO

SENSE_1TO1_55S

SENSE

ISNS_CPU_N

I314

AUD_DIFF

1TO1_DIFFPAIR

AUDIO

SENSE_1TO1_55S

SENSE

ISNS_CPU_P

I315

AUD_DIFF

1TO1_DIFFPAIR

AUDIO

SENSE_1TO1_55S

SENSE

ISNS_HDD_N

I316

AUD_DIFF

1TO1_DIFFPAIR

AUDIO

SENSE_1TO1_55S

SENSE

ISNS_HDD_P

SENSE_1TO1_55S

SENSE

ISNS_HDD_R_N

USB_85D

USB

SENSE_1TO1_55S

SENSE

ISNS_HDD_R_P

USB_85D

USB

USB_TPAD_R_P
USB_TPAD_R_N

SENSE_1TO1_55S

SENSE

ISNS_LCDBKLT_N

SENSE_1TO1_55S

SENSE

ISNS_LCDBKLT_P

SB_POWER

PP3V3_S5

SENSE_1TO1_55S

SENSE

ISNS_ODD_N

SB_POWER

PP3V3_S0

SB_POWER

PP1V5_S3RS0

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CMD

GND

GND_P2MM

MEM_CTRL

GND

GND_P2MM

MEM_DATA

GND

GND_P2MM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_DQS

GND

CPUIMVP_ISNS1_P

SENSE_1TO1_55S

GND_P2MM

TABLE_SPACING_ASSIGNMENT_ITEM

GND_P2MM
LVDS

GND

GND_P2MM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

SENSE_DIFFPAIR

TABLE_PHYSICAL_RULE_ITEM

MEM_40S

OVERRIDE

OVERRIDE

0.09 MM

OVERRIDE

OVERRIDE

OVERRIDE

400 MIL

OVERRIDE

OVERRIDE

OVERRIDE

I249

SENSE_DIFFPAIR

TABLE_PHYSICAL_RULE_ITEM

MEM_72D

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

0.09 MM

400 MIL

OVERRIDE

OVERRIDE

I250

OVERRIDE

OVERRIDE

I252

SENSE_DIFFPAIR

TABLE_PHYSICAL_RULE_ITEM

MEM_37S

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

0.09 MM

400 MIL

OVERRIDE

OVERRIDE

I251

OVERRIDE

OVERRIDE

I253

SENSE_DIFFPAIR

TABLE_PHYSICAL_RULE_ITEM

MEM_85D

OVERRIDE

OVERRIDE

0.09 MM

OVERRIDE

OVERRIDE

OVERRIDE

I254

400 MIL

OVERRIDE

OVERRIDE

OVERRIDE

I256

SENSE_DIFFPAIR

TABLE_PHYSICAL_RULE_ITEM

PCIE_85D

OVERRIDE

OVERRIDE

0.076 MM

10 mm

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

0.1 MM

500 MIL

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

I255

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

I281

SENSE_DIFFPAIR

TABLE_PHYSICAL_RULE_ITEM

USB_85D

TOP

OVERRIDE

OVERRIDE

I282
I283

SENSE_DIFFPAIR

TABLE_PHYSICAL_RULE_ITEM

CPU_27P4S

TOP

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

0.09 MM

400 MIL

OVERRIDE

OVERRIDE

I284

OVERRIDE

OVERRIDE

I285

SENSE_DIFFPAIR

TABLE_PHYSICAL_RULE_ITEM

CLK_PCIE_90D

TOP

OVERRIDE

OVERRIDE

OVERRIDE

OVERRIDE

0.09 MM

400 MIL

OVERRIDE

OVERRIDE

I286

OVERRIDE

SENSE_DIFFPAIR

OVERRIDE

SENSE_DIFFPAIR

SENSE_1TO1_55S

SENSE

ISNS_ODD_P

SENSE_1TO1_55S

SENSE

ISNS_ODD_R_N

SENSE_1TO1_55S

SENSE

ISNS_ODD_R_P

6 60 61
6 60 61
6 60 61
6 60 61
6 60 61
6 60 61
60
60
60

60
60
60
57 60
57 60
57 60
57 60
57 60
57 60
60
60
60
60
60
60

53
53

6 7 8 17 19 20 22 23 24
46 56 66 72 73 74 76
48
6 7 8 12 16 17 18 19 20
26 27 29 33 36 37 40 41
51
6 7 10 12 15 30 72 7357
62
72
73
74
77

26 30
49 50
22 23
42 46
52 54
61
71
75

ISNS_P1V8GPU_N

SENSE_1TO1_55S

SENSE
SENSE

SENSE_1TO1_55S

SENSE

I291

SENSE_1TO1_55S

SENSE

ISNS_P1V8GPU_R_N
ISNS_P1V8GPU_R_P

I293

LVDS_90D

LVDS

LVDS_CONN_A_CLK_F_N

6 74

I294

LVDS_90D

LVDS

LVDS_CONN_A_CLK_F_P

6 74

SENSE_DIFFPAIR

GND

GND

SENSE_1TO1_55S
I292

43

50

TABLE_SPACING_ASSIGNMENT_ITEM

NET_SPACING_TYPE1

43

DP_IG_AUX_CH_C_P
DP_IG_AUX_CH_C_N

DISPLAYPORT

50
DP_85D

SENSE_DIFFPAIR
TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

PWR_P2MM

ISNS_HS_COMPUTING_P

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

GND_P2MM

50
DP_85D

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

ISNS_HS_COMPUTING_N

ISNS_P1V8GPU_P

Memory Constraint Relaxations

SYNC_MASTER=ANNE_K90I

SYNC_DATE=06/08/2010

PAGE TITLE

Allow 0.127 mm necks for >0.127 mm lines for ARD fanout.

Project Specific Constraints

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

MEM_72D

BOTTOM

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

0.127 MM

6.35 MM

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

DRAWING NUMBER

TABLE_PHYSICAL_RULE_ITEM

Apple Inc.

TABLE_PHYSICAL_RULE_ITEM

MEM_85D

TOP

0.1 MM

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6.35 MM

NOTICE OF PROPRIETARY PROPERTY:

SIZE

REVISION

BRANCH

PAGE

108 OF 109
SHEET

85 OF 86

K90i Board-Specific Spacing & Physical Constraints


TABLE_BOARD_INFO

BOARD LAYERS

BOARD AREAS

BOARD UNITS
(MIL or MM)

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

NO_TYPE,BGA

MM

ALLEGRO
VERSION
15.5.1

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

DEFAULT

=50_OHM_SE

=50_OHM_SE

10 MM

0 MM

0 MM

STANDARD

=DEFAULT

=DEFAULT

10 MM

=DEFAULT

=DEFAULT

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

LAYER

LINE-TO-LINE SPACING

WEIGHT

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1

NET_SPACING_TYPE2

AREA_TYPE

SPACING_RULE_SET

BGA

BGA_P1MM

MEM_CLK

BGA

BGA_P2MM

CLK_PCIE

BGA

BGA_P2MM

CLK_SLOW

BGA

BGA_P2MM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

DEFAULT

0.1 MM

TABLE_SPACING_ASSIGNMENT_ITEM

?
TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

0.110 MM

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

TOP,BOTTOM

=DEFAULT

TABLE_SPACING_ASSIGNMENT_ITEM

?
TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

50_OHM_SE

STANDARD

DIFFPAIR NECK GAP


BGA_P1MM

=DEFAULT

TABLE_SPACING_ASSIGNMENT_ITEM

?
TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

50_OHM_SE

0.080 MM

0.080 MM

=STANDARD

=STANDARD

=STANDARD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

BGA_P2MM

=DEFAULT

LINE-TO-LINE SPACING

WEIGHT

TABLE_PHYSICAL_RULE_HEAD

TOP,BOTTOM

0.165 MM

0.165 MM

LAYER

ISL10

0.126 MM

0.126 MM

1.5:1_SPACING

=STANDARD

=STANDARD

=STANDARD

0.15 MM

ISL3,ISL4,ISL9

0.126 MM

0.126 MM

=STANDARD

=STANDARD

0.2 MM

=STANDARD

=STANDARD

=STANDARD

=STANDARD

2X_DIELECTRIC

0.140 MM

3X_DIELECTRIC

0.210 MM

4X_DIELECTRIC

0.280 MM

TABLE_SPACING_RULE_ITEM

2.5:1_SPACING

=STANDARD

WEIGHT

TABLE_SPACING_RULE_ITEM

0.25 MM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

40_OHM_SE

LINE-TO-LINE SPACING

TABLE_SPACING_RULE_ITEM

2:1_SPACING

=STANDARD

LAYER

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

40_OHM_SE

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

40_OHM_SE

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

TABLE_PHYSICAL_RULE_ITEM

40_OHM_SE

TABLE_SPACING_RULE_ITEM

3:1_SPACING

0.3 MM

TABLE_SPACING_RULE_ITEM

5X_DIELECTRIC

0.350 MM

7X_DIELECTRIC

0.490 MM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

0.090 MM

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

4:1_SPACING

0.4 MM

TABLE_SPACING_RULE_ITEM

DIFFPAIR NECK GAP


TABLE_PHYSICAL_RULE_ITEM

37_OHM_SE

TOP,BOTTOM

0.190 MM

0.1 MM

37_OHM_SE

ISL10

0.145 MM

0.1 MM

=STANDARD

=STANDARD

=STANDARD

37_OHM_SE

ISL3,ISL4,ISL9

0.145 MM

0.1 MM

=STANDARD

=STANDARD

=STANDARD

37_OHM_SE

=STANDARD

=STANDARD

=STANDARD

=STANDARD

=STANDARD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

27P4_OHM_SE

TOP,BOTTOM

0.310 MM

0.2 MM

27P4_OHM_SE

0.235 MM

0.2 MM

=STANDARD

=STANDARD

=STANDARD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

55_OHM_SE

TOP,BOTTOM

0.090 MM

0.090 MM

55_OHM_SE

0.070 MM

0.070 MM

=STANDARD

=STANDARD

=STANDARD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP


TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

1:1_DIFFPAIR

=STANDARD

=STANDARD

=STANDARD

0.1 MM

0.1 MM

TABLE_PHYSICAL_RULE_ITEM

72_OHM_DIFF

=STANDARD

=STANDARD

=STANDARD

=STANDARD

72_OHM_DIFF

ISL3,ISL4,ISL9

0.140 MM

0.140 MM

=STANDARD

0.190 MM

0.190 MM

72_OHM_DIFF

ISL10

0.140MM

0.140 MM

0.190 MM

0.190 MM

72_OHM_DIFF

TOP,BOTTOM

0.175 MM

0.175 MM

0.200 MM

0.200 MM

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

MAXIMUM NECK LENGTH

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

85_DIFF_BGA

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF

85_DIFF_BGA

ISL3,ISL4

0.075 MM

0.075 MM

0.125 MM

0.125 MM

85_DIFF_BGA

ISL9,ISL10

0.075 MM

0.075 MM

0.125 MM

0.125 MM

TABLE_PHYSICAL_RULE_ITEM

85_OHM_DIFF

=STANDARD

=STANDARD

=STANDARD

=STANDARD

=STANDARD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

85_OHM_DIFF

ISL3,ISL4

0.101 MM

0.1 MM

0.170 MM

0.170 MM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

85_OHM_DIFF

ISL9,ISL10

0.101 MM

0.1 MM

0.170 MM

0.170 MM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

85_OHM_DIFF

TOP,BOTTOM

0.125 MM

0.1 MM

0.190 MM

NOTE: 85_DIFF_BGA is 85-ohms differential impedance on outer layers and 80-ohms on inner layers.

0.190 MM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

90_DIFF_BGA

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

=90_OHM_DIFF

90_DIFF_BGA

ISL3,ISL4

0.075 MM

0.075 MM

0.125 MM

0.125 MM

90_DIFF_BGA

ISL9,ISL10

0.075 MM

0.075 MM

0.125 MM

0.125 MM

TABLE_PHYSICAL_RULE_ITEM

90_OHM_DIFF

=STANDARD

=STANDARD

=STANDARD

=STANDARD

=STANDARD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

90_OHM_DIFF

ISL3,ISL4

0.091 MM

0.091 MM

0.180 MM

0.180 MM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

90_OHM_DIFF

ISL9,ISL10

0.091 MM

0.091 MM

0.180 MM

0.180 MM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

90_OHM_DIFF

TOP,BOTTOM

0.111 MM

0.111 MM

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

NOTE: 90_DIFF_BGA is 90-ohms differential impedance on outer layers and 85-ohms on inner layers.

0.200 MM

0.200 MM

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

TABLE_PHYSICAL_RULE_HEAD

MAXIMUM NECK LENGTH

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

100_DIFF_BGA

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

100_DIFF_BGA

ISL3,ISL4

0.075 MM

0.075 MM

0.125 MM

0.125 MM

100_DIFF_BGA

ISL9,ISL10

0.075 MM

0.075 MM

0.125 MM

0.125 MM

TABLE_PHYSICAL_RULE_ITEM

100_OHM_DIFF

=STANDARD

=STANDARD

=STANDARD

=STANDARD

=STANDARD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

100_OHM_DIFF

ISL3,ISL4

0.076 MM

0.076 MM

0.250 MM

0.250 MM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

100_OHM_DIFF

ISL9,ISL10

0.076 MM

0.076 MM

0.250 MM

0.250 MM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

100_OHM_DIFF

TOP,BOTTOM

0.085 MM

0.085 MM

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

110_OHM_DIFF

=STANDARD

=STANDARD

110_OHM_DIFF

ISL3,ISL4

0.070 MM

110_OHM_DIFF

ISL9,ISL10

110_OHM_DIFF

TOP,BOTTOM

NOTE: 100_DIFF_BGA is 100-ohms differential impedance on outer layers and 95-ohms on inner layers.

0.200 MM

0.200 MM

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

=STANDARD

=STANDARD

=STANDARD

0.070 MM

0.330 MM

0.330 MM

0.070 MM

0.070 MM

0.330 MM

0.330 MM

0.085 MM

0.085 MM

0.250 MM

0.250 MM

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

NOTE: 110_DIFF is 110-ohms differential impedance on outer layers and 105-ohms on inner layers.
TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

NOTE: These are Intel recommended impedances for PEG, unused on K90i.
TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

48_OHM_SE

TOP,BOTTOM

0.165 MM

0.165 MM

48_OHM_SE

0.090 MM

0.090 MM

=STANDARD

=STANDARD

=STANDARD

PHYSICAL_RULE_SET

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAP

MAXIMUM NECK LENGTH

TABLE_PHYSICAL_RULE_ITEM

SYNC_MASTER=ANNE_K90I

SYNC_DATE=06/08/2010

PAGE TITLE

TABLE_PHYSICAL_RULE_ITEM

PCB Rule Definitions


DRAWING NUMBER
TABLE_PHYSICAL_RULE_HEAD

Apple Inc.

TABLE_PHYSICAL_RULE_ITEM

80_OHM_DIFF

=STANDARD

=STANDARD

80_OHM_DIFF

ISL3,ISL4

0.115 MM

80_OHM_DIFF

ISL9,ISL10

0.115 MM

80_OHM_DIFF

TOP,BOTTOM

0.140 MM

=STANDARD

=STANDARD

=STANDARD

0.115 MM

0.180 MM

0.180 MM

0.115 MM

0.180 MM

0.180 MM

0.140 MM

0.190 MM

0.190 MM

SIZE

D
REVISION

R
TABLE_PHYSICAL_RULE_ITEM

NOTICE OF PROPRIETARY PROPERTY:


THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

BRANCH

PAGE

109 OF 109
SHEET

86 OF 86