Sie sind auf Seite 1von 75

8

CK
APPD

SEEDY

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.


2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

REV

ZONE

ECN

ENG
APPD

DESCRIPTION OF CHANGE
DATE

04

354713

ENGINEERING RELEASED

DATE

12/07/04 ?

12/07/04
D

CSA PDF
1
2
3
4
5
6
7
8
9
10
11
12
13*
14
16
17
18
21
22
23
24
25*
26
27
28
29
30
31
32
33
34
35
36
37
38
40
44
45
46
48
49
50

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42

CIRCUIT

BLOCK

TABLE OF CONTENTS
SYSTEM BLOCK DIAGRAM
POWER BLOCK DIAGRAM
REVISION HISTORY
TABLE ITEMS
FUNC TEST
POWER CONNECTOR / POWER ALIAS
SIGNAL ALIAS
2.5V VREG
1.2V VREG
3.3V/5V PWRON SWITCHING
VESTA POWER
SMU
CPU LOGIC ANALYZER CONNECTOR
FAN 0, 1 AND SYSTEM TEMP SENSOR
FAN 2 AND HARD DRIVE TEMP SENSOR
I2C CONNECTIONS
INDICATOR LED / AMBIENT LIGHT SENSOR
1.5V VREG / U3LITE CORE
SHASTA CORE
U3LITE MISC
SHASTA SERIAL
PULSAR POWER
PULSAR CLOCKS
U3LITE APPLE PI
NEO APPLE PI
CPU STRAPS
NEO POWER & BYPASS
CPU BYPASS
CPU VREG
CPU VREG
CPU VREG OUTPUT CAPS
CPU DIODE CONDITIONER
U3LITE MEMORY
SERIES TERMINATION
DIMMS
PARALLEL TERMINATION
PARALLEL TERMINATION
VTT VREG
U3LITE AGP
GPU AGP
GRAPHICS VREGS

TOP

51
52
53
54
55
56
58
59
60
62*
64
73
74*
75*
76
77*
80*
83
84*
86*
87
88*
89*
90
91*
92
94
95*
96*
98*
100*
101*
102*

43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75

PROCESSOR

CIRCUIT

BLOCK

y
r

GPU CORE POWER


GPU FRAME BUFFER
FRAME BUFFER TERMINATION
GRAPHICS DDR SDRAM A
GRAPHICS DDR SDRAM B
GPU STRAPS
GPU DVI & DACS
EXT VGA & TMDS
U3LITE HYPERTRANSPORT
SHASTA HYPERTRANSPORT
HYPERTRANSPORT LA CONNECTORS
PCI SERIES TERMINATION
SHASTA PCI
BOOT ROM
AIRPORT EXTREME & BLUETOOTH
USB2 PCI
SHASTA DISK
DISK CONNECTORS
SHASTA ETHERNET
VESTA ETHERNET PHY
ETHERNET CONNECTOR
SHASTA FIREWIRE
VESTA FIREWIRE PHY
FIREWIRE CONNECTORS
USB HOST INTERFACE
USB DEVICE INTERFACE
MODEM CONNECTOR
PCM3052A AUDIO CODEC
LINE IN AMP
LINE OUT AMP
SPEAKER AMP
AUDIO CONNECTORS
AUDIO POWER SUPPLIES

GRAPHICS

a
n
i

m
il

e
r

CSA PDF

HT
C

PCI
DISK
ETHERNET
FIREWIRE
USB

MODEM

AUDIO

MEMORY
DIMENSIONS ARE IN MILLIMETERS

Apple Computer Inc.

METRIC

XX

X.XX
DRAFTER

GRAPHICS

NOTICE OF PROPRIETARY PROPERTY

DESIGN CK

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

X.XXX
ENG APPD

MFG APPD

QA APPD

DESIGNER

RELEASE

SCALE

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

ANGLES

TITLE

DO NOT SCALE DRAWING

SCH,MLB,SEEDY
NONE
SIZE

* PAGES WHERE MASTER PAGE IS IN A DIFFERENT SCHEMATIC


THIRD ANGLE PROJECTION

MATERIAL/FINISH
NOTED AS
APPLICABLE

DRAWING NUMBER

051-6772
SHT

REV.

04

OF

102

FREQUENCIES LISTED ARE MAXIMUM DATA TRANSFER RATES SUPPORTED BY U3LITE

U2900

CPU
NEO 10S

U1300

U1301

PAGE 29
J5900, J5901
J5902, J5903

SMU

RTC

17",20" INVERTER

TMDS
EXT VGA

32-BIT
APPLE PI
ELASTIC INTERFACE
1.2V/900MHZ

PAGE 59

y
r

FRAME
BUFFER A

PAGE 28
U3

GPU

64-BIT
FRAME BUFFER
2.6V/400MHZ

AGP

32-BIT
8X AGP
0.8V/533MHZ

RV351LE

PAGE 54

U3LITE

PAGE
48

CORE

4X = 1.5V
I/O = 1.5V

64-BIT
FRAME BUFFER
2.6V/400MHZ

PULSAR

CLOCKS

FRAME
BUFFER B

PAGE 26

PAGE 27

PAGE 55

DIMMS

SERIES

HYPERTRANSPORT

PAGE 24

PAGE 60

TERM
PAGES 44&45

PAGE 38

a
n
i

CONTROL = 2.5V

J6400
J6401
J6402

PAGE 18

J9240

HT
DEBUG

AIRPORT
EXTREME
CONNECTOR

SATA/150

OPTICAL

UATA
CONNECTOR

UATA/133

3.3V/133MHZ

UATA

PAGE 80

J8301

PAGE 91

ETHERNET FIREWIRE

PAGE 83

PAGE 84

PAGE 88

PAGE 74

32-bit PCI (5V-3.3V/33MHz)

PAGE 86

4 Diff pairs
J8700

PAGE 94

SCCB
I2S2

U9500

S/PDIF

AUDIO CODEC
PCM3052A

LINE OUT
AMP
PAGE 97

SPEAKER
AMP

LINE IN
AMP
2 Diff pairs

PAGE 97

SYSTEM BLOCK DIAGRAM

SPEAKER
CONNECTOR

J9800

J9802

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT

LINE IN

MIC

CONNECTOR

CONNECTOR

PAGE 98

PAGE 98

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART


SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-6772

D
SCALE

NOTICE OF PROPRIETARY PROPERTY

PAGE 98

PAGE 97

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

J9000, J9001

PAGE 90

PAGE 98
LINE OUT

J9801

PAGE 89
0
1

PAGE 87

OPTICAL OUT
J9803

COMBO OUT
CONNECTOR

FIREWIRE A

FIREWIRE A
CONNECTORS

CTL-LESS /
SOFT MODEM
CONNECTOR

PAGE 95

ETHERNET
CONNECTOR

PCI

PAGE 77

J9401

VESTA

GIG ETHERNET

PAGE 92

uPD720101

PAGE 76

I2S

PAGE 25
SCCA
I2S0
I2S1

1394 OHCI (3.3V/98MHz)


8-bit TX/RX

GMII (3.3V/125MHz)
8-bit TX & 8-bit RX

NCs

CORE

PAGE 23

U8600

PCI

SHASTA

e
r

1.2V/1.5GHZ
PAGE 83

BLUETOOTH
CONNECTOR

PAGE 25

SATA DEV
CONNECTOR

U2300

SATA2

FOR DEVELOPMENT ONLY

SATA

PAGE 80

J8302

GPIO/PCI64

PAGE 62

PAGE 83

USB 2.0

m
il

HYPERTRANSPORT

SATA1

1.2V/1.5GHZ

U7700

J7600

PAGE 75

JXXXX

SATA/150

PAGE 92

PAGE 91

U7500

BOOTROM

SATA
CONNECTOR

USB

PAGE 64

HARD DRIVE

J9210/J9220/J9230

USB
CONNECTORS

8-BIT
HYPERTRANSPORT
1.2V/800MHZ

I2C

PARALLEL

TERM

PAGE 40

MISC

U5500, U5501

POWER

64/128-BIT
MAIN MEMORY
2.6V/400MHZ

PAGE 22

PAGE 49

U2600

MAIN MEMORY

APPLE PI
U4900

PAGE 37

J4000
J4001

U5400, U5401

PAGE 13

PAGE 13

OF

04
102

1
SMU

SYS_POWERUP_L

POWER SEQUENCE PIN


PULSAR_POWER_DOWN
MAKE_BASE=TRUE
=PULSAR_POWER_DOWN
27

SYS_POWERUP_L

J700
PAGE 7

POWER CONNECTOR

TP_SMU_PWRSEQ_P1_0

PP24V_RUN

PP12V_RUN

FW CONN
20" LCD INVERTER

PP5V_RUN

20" PANEL POWER


20" LCD INVERTER

PP5V_ALL

TURN_ON_PP1V2_PWRON_L

PP3V3_RUN

5V

a
n
i
PP1V2_ALL

PP3V3_ALL
LINEAR

SWITCHER

PAGE 10

PAGE 11

PP5V_RUN_AUDIO
LINEAR
PAGE 99

5V

CPU CORE
SWITCHER
PAGE 33

HP/LINEOUT AMP

6 7 8 31

PP2V5_RUN_CPU_AVDD
ALIAS

CPU_AVDD_EN

SC2643VX*1
SC1211*4

0.8~1.2V

31

LINEAR

PAGE 31

PP5V_PWRON
FET SWITCH

PP3V3_PWRON
FET SWITCH

PAGE 11
CPU AVDD

2.8V

GPUL

PAGE 11
USB CONN

5V

ENET PHY
USB2 HOST
MODEM & BT

3.3V

GPU CORE
SWITCHER

U3LITE CORE
SWITCHER

PAGE 99

4.5V

AUDIO CODEC

PAGE 22

1.53V

LINEAR

PAGE 50

IRU3037ACS

1.20V

RV351

m
il

PP2V5_PWRON
SWITCHER

IRU3037CS

PAGE 9

U3LITE CORE

IRU3037CS

SHASTA HT
DDR DIMM

2.59V

PP1V25_RAM_VTT
LINEAR
IN

PP2V5_PWRON

PAGE 46

RAM TERM
GRAPHIC FB

1.3V

PP1V8_GPU
LINEAR
PAGE 50

P
GPU

PP1V5_PWRON
LINEAR

e
r

PAGE 9

RAM VTT

46

13

(PWR_GOOD_SB_CORE)

SMU_PWRSEQ_P9_6

13

(PWR_GOOD_PP2V5)

SMU_PWRSEQ_P1_2

13

(TURN_ON_VTT)

PP3V3_ALL

IN

R331
10K

5%
1/16W
MF-LF
2 402

PWR_GOOD_SB_CORE

GPU

GPU

3
11

R330
5%
1/16W
MF-LF
402

GPU

PP1V2_PWRON
FET SWITCH IN
PAGE 10

PP1V2_RUN
FET SWITCH

PAGE 50

AGP BUS

14

GND
12

C330

0.01UF

20%
16V
2 CERM
402

IN

HT BUS

=PPVCORE_PWRON_SB
PP5V_ALL
PP3V3_ALL
1

R342

PULSAR CORE

PP1V5_RUN
POWER SW

PAGE 10

IN

SHASTA CORE
PWRON_SD
PWRON_DISK_SB
23 7 6

SOI

U1100

100K 2 COMPARE_SB_CORE
1

LINEAR

PAGE 50

LM339A

RAIL_CTL_NEG

V+

PP1V5_VDDC_CT

PAGE 50

1.5V

PAGE 50

LINEAR

PAGE 50

IN

PP2V5_RUN
FET SWITCH

13

SMU_PWRSEQ_P9_5

VESTA CORE

PP2V5_GPU_A2VDD

PP1V8_TPVDD

PP4V5_RUN_AUDIO
LINEAR

13

SMU_PWRSEQ_P1_1

IRU3037ACS

1.2V

FW PHY
SMU

3.3V

SMU_PWRSEQ_P1_0

y
r

PCI BUS
AUDIO CODEC

HDD & OPTICAL

=PP5V_RUN_CPU

13

MAKE_BASE=TRUE
10

SMU_PWRSEQ_P1_4

150K

R341
10K

LM339A

SOI

V+

R340

U1100

100K 2
5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
2 402

PS_2V_REF

5%
1/16W
MF-LF
2 402

COMPARE_PP2V5

PWR_GOOD_PP2V5

GND
12

C340

0.01UF

20%
16V
2 CERM
402

R343
100K

5%
1/16W
MF-LF
2 402

TURN_ON_VTT

POWER BLOCK DIAGRAM

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6772

OF

04
102

8
DATE

CLONED DESIGN FROM GILA (Q45 A/B) REV G


CHECKIN 00002

10/21/04

ADDED VESTA
ADDED 1.2V REGULATOR FOR VESTA CORE
ADDED 2.5V LDO FOR VESTA
ADDED FW LATE VG PROTECTION
REMOVED BCM5231 ETHERNET PHY
REMOVED FW802A FW PHY
REMOVED FW PORT POWER CIRCUITRY
REMOVED MICRODASH CONNECTOR
CHECKIN 00003

10/22/04

REMOVED NV18/34 GPU


REMOVED AGP VREG (VR5001)
REMOVED GPU VTT VREG
ADDED 2.5V VREG FOR A2VDD
REMOVED EXTERNAL TMDS TRANSMITTER
ADDED RV351LE GPU
CHECKIN 00004

10/26/04

GPU CORE POWER UPDATES


ADDED VESTA ETHERNET LOWPWR CIRCUIT
ADDED DEVELOPMENT LEDS FOR VESTA ENET
CHECKIN 00005

10/28/04

CONNECTED FRAME BUFFER


ADDED 1.8V GPU VREG
CONNECTED GPU TMDS AND VGA
CONNECTED GPU POWER AND POWER FILTERS
CHECKIN 00006

11/01/04

C
11/03/04

ADDED VOLTAGE, LINE WIDTH, AND NECK WIDTH PROPERTIES FOR GRAPHICS (IN MM)
TIED PPVCORE_NB DIRECTLY TO PP1V5_PWRON (REMOVED R707)
REPLACED EMC FERRITES WITH 0 OHM RESISTORS FOR GRAPHICS AND FANS
REMOVED VESTA CORE REGULATOR
REPURPOSED 1.2V REGULATOR FOR VESTA AND SHASTA
CHANGED FW LATE VG CIRCUITRY TO MATCH Q78 & Q86
CHECKIN 00007
<RADAR 3848831> MOVED SMU RESET BUTTON TO DEVELOPMENT BOM
<RADAR 3849762> MOVED SMU DOWNLOAD CONNECTOR TO DEVELOPMENT BOM
<RADAR 3849798> REDUCED CAPACITANCE OF C1100 & C1102
MASTER PAGE SYNC:
FRAME BUFFER SWAPS FOR CLEANER ROUTING
REMOVED VESTA ROM
AUDIO COST REDUCTIONS <RADAR 3849747 & 3849751>
AUDIO 3052A CODEC
ADDED 1.55V VREG FOR GPU VDDC_CT
MOVED VTT VREG TO 2.5V PWRON TO REDUCE CURRENT THROUGH Q903
CHANGED FETS IN GPU CORE FOR COST REDUCTION
ADDED SPACING & PHYSICAL CONSTRAINTS TO FRAME BUFFER
CHECKIN 00008

11/04/04

REMOVED 1.6GHZ PROCESSORS


CHANGED VOLTAGE SETTING OF 2.5V VREG TO 2.588V FROM 2.62V
1.2V VREG COST REDUCTIONS - Q1002 TO NTD60N02R; C1002/3 TO 10UF CERM
U2850 - REMOVED MAXIM AS AN ALTERNATE
MOVED GPU ZENER DIODES TO VREG PAGE SINCE THEY SHOULD BE PLACED NEAR THE VREGS
ADDED 8MX32 GRAPHICS MEMORY
ADDED GIGABIT ETHERNET CONNECTOR
CHECKIN 00009

11/06/04

ADDED GPU STRAPS


CONNECTED GPU GPIOS
REMOVED ON BOARD POWER SUPPLY TEMP SENSOR
ADDED AMBIENT LIGHT SENSOR CONNECTOR
CONNECTED GPU TEMP SENSOR
REMOVED CPU VREG 4TH PHASE
ADDED DEVELOPMENT LEDS TO REGULATORS
CHECKIN 00010

11/07/04

ADDED MORE GPU CONSTRAINTS


<RADAR 3616348, 3621390> CHANGED FL5900-2 TO 220 OHM
<RADAR 3848846> 2.5V RUN FET COST REDUCTION
<RADAR 3848859> 1.2V, 1.5V RUN FET COST REDUCTIONS
<RADAR 3848887> 5V & 3.3V PWRON FET COST REDUCTIONS
<RADAR 3849622> STUFFED AROUND TMDS FILTERS
<RADAR 3849656> STUFFED AROUND RGB FILTERS
<RADAR 3849806> CHEAPER SMU CRYSTAL
<RADAR 3849857> CHEAPER USB2 CRYSTAL
BOM RELEASE REV 01

FRAME BUFFER PIN SWAPS


<RADAR 3848846> UPDATE OF 2.5V RUN FET COST REDUCTION
<RADAR 3849743> ADDED RESISTORS TO STUFF AROUND USB FILTERS
CHECKIN 01001

11/09/04

<RADAR 3848850>
<RADAR 3849767>
<RADAR 3849772>
<RADAR 3849820>
<RADAR 3849854>
<RADAR 3865344>
CHECKIN 01002

11/10/04

REGULATOR COST REDUCTIONS


2.5V VREG COST REDUCTIONS
REMOVED OUTPUT CAP ON 1.2V_ALL VREG
SHASTA FILTER COST REDUCTION
GPU CORE VREG COST REDUCTION
SET GPU VDDC_CT VREG TO 1.55V

11/15/04

ADDED REGULATOR FOR GPU TPVDD


ADDED POWER SEQUENCING FOR GRAPHICS REGULATORS
ADDED TEST POINTS TO GRAPHICS FOR EXOR TESTING
REMOVED EXTERNAL S/PDIF TRANSMITTER
CHECKIN 01005

11/16/04

REMOVED P50 AIRPORT AND Q23 BLUETOOTH CONNECTORS, HOLES, & STANDOFFS
ADDED Q85 AIRPORT & BLUETOOTH CONNECTOR
CHECKIN 01006
(PP 16,17) REPLACED FAN CONTROL WITH NEW CIRCUIT
(P 76) FINISHED CONNECTING Q85 CONNECTOR
(P 7) ADDED PLATED HOLE ZH710 FOR TMDS GROUNDING
(P 7) TIED BOTH EI RAILS TO 1.5V
(P 5) NEW BOOTROM P/N
(P 9) ADDED EXTRA 10UF INPUT CAP
(P 12) VESTA_ENET_LOWPWR UPDATE
(P 18) <RADAR 3878118> MOVED SMU I2C E BUS
(P 22) CHANGED Q2250 TO 376S0143
(P 46) SLEEP SIGNAL TURNS OFF VTT VREG
(P 58) REPLACED THERMAL SENSOR WITH LM63
(P 59) TIED UNUSED BUFFER ENABLE PINS HIGH
(P 90) FIXED FW PORT NAMING
(P 90) CHANGED R9090 TO 665 OHM
(P 91) CHANGED USB2 CHIP GROUNDING
(P 8) ALIASED VESTA JTAG TO TEST POINT NETS
(P 9) <RADAR 3848846> ADDED PAD FOR 1NF CAP TO GATE OF Q903
CHECKIN 01007 / BOM RELEASE REV 02

11/18/04

ADDED PHYSICAL CONSTRAINTS


AUDIO STUFFING CHANGES
CHECKIN 02001

11/20/04

(P 36) CONNECTED NEW CPU DIODE REFERENCE


(P 77) USB2 IDESEL - NOW FROM USB2 SIDE
(P 56) ADDED BOMOPTIONS FOR MEMORY STRAPS
(PP 56, 58) CONNECTED PWM FROM RV351LEP & PUT IN PROTO WORKAROUND
(P 25) <RADAR 3849835> NEW SHASTA XTAL
(P 62) <RADAR 3849855> SHASTA HT_PLL FILTER COST REDUCTION
(P 91) <RADAR 3849858> USB CAP COST REDUCTION
(P 76) ADDED STANDOFFS FOR Q85 CARD
(PP 16,17) NEW FAN CIRCUIT CAPS (C1603, C1653, C1703)
(P 50) <RADAR 3865344> VDDC_CT SET TO 1.50V
(P 50) <RADAR 3877855> TP_VDD SET TO 1.80V
(P 12) VESTA_ENET_LOWPWR UPDATE
(PP 10, 22, 34, 50) USED COMPARATOR FOR LOW VOLTAGE RAIL LEDS
CHECKIN 02002

11/22/04

y
r

a
n
i

m
il

(P 49) CONNECTED AGPTEST RESISTOR TO VDDP


(P 56) ADDED PADS FOR STRAPPING RESISTORS TO GPU_GPIO<14>
(P 58) ADDED CONSTRAINT SETS
(P 59) STUFFED AROUND Q5900 PANEL PWR SEQUENCING
(P 59) LED 3 NOW DRIVEN FROM FPD_PWR_ON
(P 3) CONNECTED SHASTA CORE POWER FOR POWER SEQUENCING
(P 76) FIXED PCI_CBE_L<1> CONNECTION
MORE PHYSICAL & SPACING UPDATES
(P 83) <RADAR 3890225> OPTICAL DRIVE CONNECTOR CHANGED TO 516S0235
CHECKIN 02003
(P 56) ADDED OPTION OF USING PWM FROM SHASTA
<RADAR 3849718, 3849767, 3849854> MADE ON & VISHAY FETS TRUE ALTERNATES
(P5) ADDED U3L W/ NEW LAMINATE AS ALTERNATE
(P 16) C1653 - REPLACED WITH LOWER HEIGHT CAP
CHECKIN 02004

e
r

11/08/04

DESCRIPTION

10/20/04

11/23/04

(P 76) TABLED IN NEW STANDOFFS FOR Q85 CARD


PROTO RELEASE (REV 3)

12/02/04

(P 90) FIXED ALIAS PROBLEM WITH FW_TPB2_PD


(P 90) FIXED FW_CPS SHORT
(P 35) REMOVED DS3500 & DS3501
(P 83) REMOVED SECOND SATA CONNECTOR
CHECKIN 03001
CONVERTED DISCRETES TO LEAD FREE
CHECKIN 03002

12/07/04

CHANGED U7700 BACK TO LEADED PART


(P 5) REMOVED ORIGINAL U3LITE (NEW LAMINATE ONLY FOR C/D)
(P 49) CHANGED GPU TO RV351LEP (338S0231)
(P 76) NOW HAVE CORRECT SYMBOL FOR STANDOFFS
(P 76) J7650 - NEW TO ALLOW 5MM CONNECTED HEIGHT
BOM RELEASE REV 04

REVISION HISTORY

CHANGED SOURCE OF Q1003 TO PP1V2_ALL


RGB TERMINATION NOW CONNECTED TO DIGITAL GROUND
WHITE LED - CHANGED INDUCTORS TO 0 OHM RESISTORS
UPDATED POWER BLOCK DIAGRAM
CHECKIN 01003
<RADAR 3848850> 2.5V VREG COST REDUCTION
CHECKIN 01004

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-6772

D
SCALE

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

OF

04
102

ASICS

PROCESSORS

TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION
TABLE_5_ITEM

343S0320

IC,U3LITE,NEW LAM,300MM,PBGA

U3

QUALIFIED

TABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR
PART NUMBER

343S0321

343S0320

TABLE_11_HEAD

PART #

QTY

DEVICE

PACKAGE

DESCRIPTION

VALUE

VOLT.

WATT.

1.8GHZ

1.20V

42W

TOL.

REFERENCE DESIGNATOR(S)

337S2969

PROCESSOR CBGA-576-1MM IC,GPUL,10S,DD3,1.8G,85C,BPA

U2900

ALTERNATE FOR
PART NUMBER

BOM OPTION

REF DES

337S2970

337S2969

CPU_DD30_1_8GHZ U2900

IC,GPUL,DD3,1.8G,BRA

WAVE5

337S2981

337S2969

CPU_DD30_1_8GHZ U2900

IC,GPUL,DD3,1.8G,BPL

U3L,NEW LAM,200MM

y
r

TABLE_ALT_ITEM

WAVE3

U3

VOLTAGE

COMMENTS:

COMMENTS:

CPU_DD30_1_8GHZ

TABLE_ALT_HEAD

PART NUMBER

REF DES

TABLE_ALT_ITEM

TABLE_11_HEAD

WAVE3

BOM OPTION

BOM OPTION

1.25V

TABLE_ALT_ITEM

1.20V

TABLE_5_HEAD

PART#

TABLE_ALT_ITEM

WAVE5

337S2982

337S2969

CPU_DD30_1_8GHZ U2900

IC,GPUL,DD3,1.8G,BRL

1.25V

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION

TABLE_5_ITEM

343S0283

IC,ASIC,SHASTA,V1.1,PBGA

U2300

TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

a
n
i
343S0324

IC,ASIC,VESTA,V1.3

BOM OPTION

TABLE_5_ITEM

U8600

MISC PARTS

PART#

m
il

QTY

DESCRIPTION

TABLE_5_HEAD

REFERENCE DESIGNATOR(S)

062-2082

SPEC,VENDOR PACKAGING PROCEDURE

820-1747

PCB,FAB,MLB

825-6447

BARCODE LABEL, MLB, Q45

051-6772

PCB,SCHEM,MLB

341T1667

IC,FLASH,1MX8,3.3V,90NS

BOM OPTION

TABLE_5_ITEM

VPP1

TABLE_5_ITEM

MLB1

TABLE_5_ITEM

LBL1

TABLE_5_ITEM

SCH1

TABLE_5_ITEM

U7500
TABLE_5_ITEM

341T1395

PURCH ASSY, SMU BIG

CRITICAL 603-6015

HEAT SINK ASSEMBLY 17 IN

MECH17

U1300
17_INCH_LCD

CRITICAL 603-6016

HEAT SINK ASSEMBLY 20 IN

MECH20

20_INCH_LCD

TABLE_5_ITEM

TABLE_5_ITEM

ALTERNATES

PART NUMBER

ALTERNATE FOR
PART NUMBER

378S0119

378S0114

376S0204

376S0130

376S0207

376S0146

BOM OPTION

TABLE_ALT_HEAD

REF DES

COMMENTS:

LED700,LED702,LED5900
KINGBRIGHT LED
Q3310,Q3320,Q3410
MOSFET,N-CH,VISHAY
Q3311,Q3321,Q3411
MOSFET,N-CH,VISHAY

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

e
r

TABLE ITEMS
A

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6772

OF

04
102

1
PP12V_RUN

I434
I433
I436
I435
I437
I439
I438
I440
I441
I442
I444

I443

I781
I809
I810

I307

I337
I338

I344
I345
I346
I347
I348
I350
I349

I354
I355
I356
I357
I358
I360
I359
I362
I363
I361
I364
I365
I372
I373
I371
I374
I375

I376
I377
I378
I380
I379
I382
I383
I381
I384
I385
I386
I388
I387
I390
I389
I391
I393
I392
I395
I394
I396
I398
I397
I399
I401
I400

I403
I402
I404
I405
I406
I408
I407

I429
I428
I431
I430
I432

NO_TEST=YES

NO_TEST=YES
NO_TEST=YES

TP_FBBCS1_L

TP_AGP_MB_AGP8X_DET_L
TP_ATTENTION

NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES

TP_AFN
TP_PSRO1
TP_PSRO2
TP_PSYNCOUT
TP_USB2_PWREN<2>
TP_USB2_PWREN<3>
TP_USB2_PWREN<4>

NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES

TP_NEC_AMC
TP_NEC_NANDTEST
TP_NEC_NTEST1
TP_NEC_SMC
TP_NEC_SMI_L
TP_NEC_SRCLK
TP_NEC_SRDATA
TP_NEC_SRMOD
TP_NEC_TEB
TP_NEC_TEST
TP_PLS_CLK_66M_0
TP_PLS_CLK_66M_1
TP_PLS_REF_CML
TP_PLS_TEST1
TP_PLS_TEST2
TP_PLS_TEST3
TP_SB_FSTEST
TP_SB_PLLTEST
TP_VREF_CG
TP_SB_NC_P7
TP_SB_NC_P8
TP_SB_NC_R3
TP_SB_NC_R4
TP_SB_NC_R5
TP_SB_NC_R6
TP_SB_NC_R7
TP_SB_NC_R8
TP_SB_NC_T1
TP_SB_NC_T2
TP_SB_NC_T3
TP_SB_NC_T4
TP_SB_NC_T5
TP_SB_NC_T6
TP_SB_NC_T7
TP_SB_NC_T8
TP_SB_NC_U1
TP_SB_NC_U2
TP_SB_NC_U3
TP_SB_NC_U4
TP_SB_NC_U5
TP_SB_NC_U6
TP_SB_NC_V1
TP_SB_NC_V2
TP_SB_NC_V3
TP_SB_NC_V4
TP_SB_NC_W1
TP_SB_NC_W3
TP_SB_NC_Y1
TP_SB_NC_Y3
TP_SATA_CLK25M

NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES

TP_USB2_PWREN<0>
TP_USB2_PWREN<1>
TP_DUMMY_A
TP_DUMMY_B
TP_RAM_CKE_R<2>

NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES
NO_TEST=YES

NO_TEST=YES
NO_TEST=YES
NO_TEST=YES

TP_RAM_CKE_R<3>
TP_RAM_CKE_R<6>
TP_RAM_CKE_R<7>
TP_RAM_CS_L_R<10>
TP_RAM_CS_L_R<11>
TP_RAM_CS_L_R<2>
TP_RAM_CS_L_R<3>
TP_RAM_MUXEN0
TP_RAM_MUXEN4
TP_NB_PM_SLEEP0
TP_J4000_SJRESET_L
TP_J4001_SJRESET_L

U2100_UNUSED
PLS_CLK_66M_0_R
PLS_CLK_66M_1_R

101
8

48
29

29
29
29
29
92
92
92

77
77
77
77
77

91
91
91
91

91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91

IN

36 33 31

IN

24

IN
IN

40
77 76 75 74 73

IN

77 76 74 73

IN

21

IN

27

76 74

IN

27

76 74

IN

76 25

IN

74 56 8

IN

77 76 74 73

IN

77 76 74 73

IN

77 76 74 73

IN

77 76 74 73

IN

77 76 74 73

IN

77 76 74 73

IN

76

IN

76 75 74

IN

76 75 74

IN

14 28 29
14 28 29
14 28 29
76 75 74

IN

76 75

IN

76

IN

76

IN

76

IN

14 28 29
14 28 29
14 28 29
14 28 29
14 28 29
14 28 29
14 28 29
92

IN

92

IN

92

IN

8 14 29
14 29 30
14 25 29 30
92

IN

92

IN

92

IN

92

IN

14
14 27
14 27
14 28 29
92

IN

92

IN

94 25

IN

94 25

IN

94 25

IN

94 25

IN

94 25

IN

94 25

IN

94 25

IN

14 28 29 30
14 28 29 30
13 14 18

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES

AUD_MIC_IN_N_CONN
AUD_MIC_IN_P_CONN
FW_VP
GND_AUDIO_MIC_CONN
I2C_HD_TEMP_SCL
I2C_HD_TEMP_SDA
I2C_SB_SCL
I2C_SB_SDA
KPGND2
KPVDD2
TMDS_DCC_CLK
TMDS_DCC_DAT
PCI_AD<31..0>
PCI_CBE_L<3..0>
PCI_CLK33M_AIRPORT
PCI_SLOTA_REQ_L
PCI_SLOTA_GNT_L
PCI_SLOTA_INT_L
PCI_RESET_L
PCI_FRAME_L
PCI_TRDY_L
PCI_IRDY_L
PCI_STOP_L
PCI_DEVSEL_L
PCI_PAR
PCI_SLOTA_IDSEL
ROM_CS_L
ROM_OE_L
ROM_WE_L
ROM_ONBOARD_CS_L
AIRPORT_CLKRUN_L_PD

14 29
14 29 30
14 29 30
14 29
14 27

92 91

IN

92 91

IN

25

IN

25

IN

59

IN

59

IN

59

IN

18 11 10 7

IN

50 34 22 18 11 10 7

IN
IN

I2S1_DEV_TO_SB_DTI
I2S1_SYNC
I2S1_BITCLK
I2S1_MCLK
I2S1_SB_TO_DEV_DTO
I2S1_RESET_L
MODEM_RING2SYS_L

2
2
2
2
2
2
2

USB2_P<3>
USB2_N<3>
UDASH_SDOWN
UDASH_RESET_L

PP12V_RUN
PP5V_ALL
PP5V_RUN
PP3V3_RUN
PP24V_RUN

10 TEST POINTS

5 TEST POINTS

12 TEST POINTS

83 7

IN

83 7

IN

=PP5V_DISK
=PP12V_DISK

IN

GND

IN
IN
18 11

IN

58 27 18 11

IN
IN
IN

TEST
TEST
TEST
TEST
TEST
TEST
TEST

POINTS
POINTS
POINTS
POINTS
POINTS
POINTS
POINTS

FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES

FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES

PPVCC_TMDS
PP3V3_DDC
TD0M
TD0P
TD1M
TD1P
TD2M
TD2P
TCKM
TCKP
I2C_TMDS_SDA
I2C_TMDS_SCL
GND_CHASSIS_TMDS

FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES

IN
IN

59

IN

59

IN

59

IN

59

IN

59

IN

59

IN

59

IN

59 7

IN

59

IN

59

IN

59

IN

FILT_ANALOG_RED
FILT_ANALOG_GRN
FILT_ANALOG_BLU

59 58

IN

MON_DETECT

FUNC_TEST=YES

59

IN

59

IN

59

IN

59

IN

59

IN

59

IN

59

IN

59

IN

PP24V_INV
GND_20_INV
INV_20_LCD_PWM_
INV_20_CUR_HI_F
PP12V_INV
GND_17_INV
PP5V_AGP_RL
INV_17_LCD_PWM_F

FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES

INV_17_CUR_HI_F

FUNC_TEST=YES

CPU_VID_R<5..0>
KPVDD2_FMAX
KPGND2_FMAX
TDIODE_POS_FMAX
TDIODE_NEG_FMAX
CORE_ISNS_M
CORE_ISNS_P

FUNC_TEST=TRUE
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES

13 8 7

IN

31 8 7 3

IN

22

IN

35 34 33 7

IN

34 33

IN

33

IN

33

IN

8 7

IN

13 7

IN

IN

IN

13 8

IN

33 13 11 10 7

IN

46 22 11 10 9 8

IN

13 8

IN

IN

22

IN

59 58

IN

59 58

IN

59 58

IN

101 25

IN

75

IN

83 80

IN

83 80

IN

83 80

IN

83 80

IN

83 80

IN

83

IN

83 80

IN

83 806 6
83 80
83

IN

83 80

IN

83

IN

83

IN

83

IN

83

IN

36 31

IN

IN

FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES

5 TEST POINTS
5 TEST POINTS
5 TEST POINTS
5 TEST POINTS

PP5V_ALL

PP24V_RUN

PP3V3_RUN

FUNC_TEST=YES
FUNC_TEST=YES

5 TEST POINTS

FUNC_TEST=YES

y
r

PP2V5_RUN
PP1V5_RUN
PP5V_PWRON
PP3V3_PWRON
PP1V2_PWRON
=PPVCORE_PWRON_SB
=PP3V3_ALL_SMU
=PP5V_RUN_CPU
PPVCORE_NB
PPVCORE_CPU
PP12V_CPU
VCORE_SENSE_GND
VCORE_SENSE_VOUT
SMU_MANUAL_RESET_L
SYS_POWER_BUTTON_L
POWER_BUTTON_L
RESET_BUTTON_L
SMU_RESET_L
SYS_POWERUP_L
SYS_SLEEP
SYS_POWERFAIL_L

a
n
i

59

IN

IN

FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES

USB2_PORT1_N_F
USB2_PORT1_P_F
USB2_PORT2_N_F
USB2_PORT2_P_F
USB2_PORT3_N_F
USB2_PORT3_P_F
PP5V_USB2_PORT1_F
PP5V_USB2_PORT2_F
PP5V_USB2_PORT3_F

59

59

91

IN
11 7

FUNC_TEST=YES
FUNC_TEST=YES

USB_BT_N
USB_BT_P

m
il

13 14 18

e
r

91

IN

36 33 31
8

27

91

IN

25 18

40

27

91

25 18

27

48

IN

77

25

IN

18 17
8

77

25

IN

18 17
8

77

27

IN

101
8

77

27

IN

90
8

77

27

101
8

52

GENZ SHOULD USE J1400 FOR THE FOLLOWING NETS:


EI_CPU_TO_NB_AD<0..43>
NO_TEST=TRUE
I782
EI_CPU_TO_NB_CLK_N
NO_TEST=YES
I784
EI_CPU_TO_NB_CLK_P
NO_TEST=YES
I785
EI_CPU_TO_NB_SR_N<0..1>
NO_TEST=TRUE
I786
EI_CPU_TO_NB_SR_P<0..1>
NO_TEST=TRUE
I787
EI_NB_TO_CPU_AD<0..43>
NO_TEST=TRUE
I789
EI_NB_TO_CPU_CLK_N
NO_TEST=YES
I788
EI_NB_TO_CPU_CLK_P
NO_TEST=YES
I790
EI_NB_TO_CPU_SR_N<0..1>
NO_TEST=TRUE
I792
EI_NB_TO_CPU_SR_P<0..1>
NO_TEST=TRUE
I791
CHKSTOP_L
NO_TEST=YES
I793
CPU_HRESET_L
NO_TEST=YES
I794
CPU_INT_L
NO_TEST=YES
I795
CPU1_HTBEN
NO_TEST=YES
I796
EI_CPU1_CLK_N
NO_TEST=YES
I797
EI_CPU1_CLK_P
NO_TEST=YES
I798
EI_QACK_L
NO_TEST=YES
I799
EI_QREQ_L
NO_TEST=YES
I800
EI_SE
NO_TEST=YES
I801
I2C_SMU_A_SCL_OUT_L
NO_TEST=YES
I802
I2C_SMU_A_SDA_OUT_L
NO_TEST=YES
I803
MCP_L
NO_TEST=YES
I804
RI_L
NO_TEST=YES
I805
SYNCENABLE
NO_TEST=YES
I806
TP_PROC_TRIGGER_OUT
NO_TEST=YES
I807
EI_CPU1_SYNC
NO_TEST=YES
I808

IN

PP5V_RUN

2 TEST POINTS
2 TEST POINTS

PP2V5_RUN PP5V_PWRON
PP1V5_RUN

PP1V2_PWRON

PP3V3_PWRON

FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=TRUE
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES

U900_FEEDBACK
U2200_FEEDBACK
ANALOG_RED
ANALOG_GRN
ANALOG_BLU

FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES

AUDIO_LO_DET_L
ROM_WP_L

FUNC_TEST=YES
FUNC_TEST=YES

UATA_DD<15..0>
UATA_DA<2..0>
UATA_CS0_L
UATA_CS1_L
UATA_RESET_L
UATA_DSTROBE_R
UATA_HSTROBE
UATA_STOP
UATA_DMARQ_R
UATA_DMACK_L
UATA_INTRQ_R
UATA_IOCS16_PU
UATA_CSEL_PD
UATA_DASP_L
TDIODE_NEG

FUNC_TEST=TRUE
FUNC_TEST=TRUE
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=TRUE
FUNC_TEST=YES

FUNC TEST
A

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

91
27

33 8

IN

36

IN

92

36

IN

92

36

IN

24

36

IN

24

36 33

IN

36 33

IN

II NOT TO REPRODUCE OR COPY IT


III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT

NONE

REV.

051-6772
04
6
102
OF

7
PP12V_RUN

PP5V_RUN

PP5V_ALL

PP3V3_RUN

PP12V_RUN

PP5V_RUN

ONLY ON IN RUN

J700
F-RT-TH

POWER_GOOD

59

13

14

15

16

17

18

19

20

10

21

11

22

PWRON RAILS

ALL RAILS

ON IN RUN AND SLEEP

ALWAYS ON WHEN UNIT HAS AC POWER (TRICKLE)


PP5V_ALL

PP5V_PWRON

12

=PP24V_GRAPHICS

VOLTAGE=24V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
MAKE_BASE=TRUE

HM96110-P2

11 6

PP12V_RUN

VOLTAGE=12V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
MAKE_BASE=TRUE

=PP12V_AGP
=PP12V_RUN_CPU
=PP12V_DISK

50 59

59 11 7

PP12V_AUDIO_CODEC

102

VOLTAGE=3.3V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
MAKE_BASE=TRUE

ALIAS

PP12V_AUDIO_SPKRAMP 100

PIN 13,19,11,22 ARE DIFFERENCE FROM ATX .

XW705
SM
PP3V3_ALL

U700

14
2

SYS_POWERUP_L

33 13 11 10 6

C700

74LCX125

18 11 10 6

20%
2 10V
CERM
402

PP5V_RUN

VOLTAGE=5V
MAKE_BASE=TRUE
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

SYS_POWERUP_L_BUF

=PP5V_PATA
=PP5V_DISK

23
23
94

10

91
76
36
28
12

6 83

=PP5V_AGP

50 59

=PP5V_RUN_CPU
PP5V_AUDIO

ALIAS

a
n
i
=PP2V5_PWRON_SB

83

VOLTAGE=2.5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
MAKE_BASE=TRUE

101

=PP2V5_PWRON_RAM
=PP2V5_HT

50 34 22 18 11 10 6

PP5V_ALL

PP3V3_PWRON

R710
330

R700
330

2 ITS_PLUGGED_IN

5%
1/10W
MF-LF
603

PP3V3_RUN

DEVELOPMENT

5%
1/10W
MF-LF
603

LED702

R701
330

ITS_ALIVE

GREEN
2.0X1.25A

GREEN
2.0X1.25A
2

5%
1/10W
MF-LF
603

LED700

LED701

CRITICAL

SW703

SM

PWR-BUTT
ST-SM3

C703

PP1V5_RUN

SILKSCREEN:POWER

0.1UF

20%
10V
2 CERM
402

L701

PP2V5_GPU

ALIAS

e
r

GND_SYS_PWR_BTN_FILT

SM

35 34 33 6

PP1V2_RUN

13 7 6

SYS_POWER_BUTTON_L
DEVELOPMENT

R712
13

SYS_RESET_BUTTON_L 1

1K

5%
1/16W
MF-LF
402

POWER_BUTTON_L

5%
1/16W
MF-LF
402

SW702

SPST

SPST

SM
1

SM
2

2
1

C705
0.1UF

20%
10V
2 CERM
402
3

RESET

8 6

RESET_BUTTON_L
DEVELOPMENT

SW701

POWER

SMU_MANUAL_RESET_L
DEVELOPMENT

SW700
SPST
SM
1

25 74 75 76 77
77
83

C704
0.1UF

20%
10V
2 CERM
402

31

44 45

=PP1V5_AGP
=PPVCORE_PULSAR

60 64
62

87

=PPVCORE_NB

28 37 48 60
26
22

48 49 50

PPVCORE_CPU

=PPVCORE_CPU

MAKE_BASE=TRUE
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=1.2V

=PP1V2_PWRON_HT
=PP1V2_PWRON_DISK_SB
=PP1V2_PWRON_SB
=PPVCORE_PWRON_SB

102 100

36
12
86 87
89 90
89

PP1V2_VESTA
=PP1V2_ENETFW

12
86 89

GND RAILS
XW702
SM
1

GND_AUDIO

XW706
SM
1

XW703
SM

GND_AUDIO_SPKRAMP

XW707
SM
1

CHASSIS GND
ZH700

315R138
102 101

59

62

92

80

GND_CHASSIS_AUDIO_EXTERNAL
MIN_NECK_WIDTH=15MIL
MAKE_BASE=TRUE
VOLTAGE=0
MIN_LINE_WIDTH=25MIL

90

GND_CHASSIS_VGA
GND_CHASSIS_USB
GND_CHASSIS_FIREWIRE

ALIAS

25

ZH701

3 6 23

315R138
59 6

GND_CHASSIS_TMDS
MIN_NECK_WIDTH=15MIL
MIN_LINE_WIDTH=25MIL
VOLTAGE=0

ZH710

315R138
1

7R4.15

14 18 29 30 31 35

SH700

14 18 28

101

21

GND_CHASSIS_AUDIO_INTERNAL
MAKE_BASE=TRUE
GND_CHASSIS_LED

ALIAS

=PP1V2_HT

24 60

=PP1V2_PULSAR

26

SHLD-IO-CONN
Q45-TH1
3

PPVCORE_GPU

805-5664

ZH703

59

GND_CHASSIS_17_INCH_INVERTER
MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL
VOLTAGE=0

NOSTUFF

SDF700
HSK-NUT-6.5MM
TH

R720

6.00MM-PTH

NOSTUFF

29 31 32 36

MAKE_BASE=TRUE

ZH702

GND_CHASSIS_RJ45
MIN_NECK_WIDTH=15MIL
MIN_LINE_WIDTH=25MIL
VOLTAGE=0

87

26

=PP1V2_EI_CPU
=PP1V2_EI_NB

VOLTAGE=1.2V
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

R713
1K

74

50 52 54 55

=PP2V5_RUN_CPU
=PP2V5_RUN_RAM

VOLTAGE=1.5V
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

516S0248
FOXCONN
4

FERR-EMI-100-OHM
2

83

m
il

VOLTAGE=2.5V
MAKE_BASE=TRUE
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

2 SYS_PWR_BTN_FILT

33

=PP1V5_PWRON_NB_AVDD
=PPVCORE_PWRON_PULSAR

PP1V2_ALL
MAKE_BASE=TRUE
VOLTAGE=1.2V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=15MIL

6 8 13

PP1V2_PWRON

FERR-EMI-100-OHM

95 100 101 102

PP2V5_RUN

SILKSCREEN:RUN

L700

PP3V3_AUDIO
=PP3V3_RUN_CPU
=PP3V3_PATA
=PP3V3_SB_PCI
=PP3V3_PCI
=PPVIO_PCI_USB2
=PP3V3_DISK

ALIAS

MAKE_BASE=TRUE
VOLTAGE=1.5V
MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL

48 49 50 56 58 59

GREEN
2.0X1.25A

SILKSCREEN:2

SYS_POWER_BUTTON_L

=PP3V3_AGP

13 7 6

VOLTAGE=3.3V
MIN_LINE_WIDTH=12MIL
MIN_NECK_WIDTH=8MIL
MAKE_BASE=TRUE

ITS_RUNNING
DEVELOPMENT

SILKSCREEN:1

PP3V3_RUN

102

36

=PP3V3_ALL_SMU
=PP3V3_ALL_CPU
PP3V3_VESTA
=PP3V3_ENET
=PP3V3_FW
=PP3V3_ENETFW

PP3V3_ALL
MAKE_BASE=TRUE
VOLTAGE=3.3V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

26 37 40 46

PP1V5_PWRON
PP3V3_RUN

=PP5V_ALL_CPU

VOLTAGE=5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
MAKE_BASE=TRUE

23 25 74 88

=PP2V5_PWRON_HT
=PP2V5_ENET

3 6 8 31

PP5V_ALL

y
r

23 25 74

PP2V5_PWRON

125
1 TSSOP

=PP3V3_PWRON_SB
=PPPCI64_PWRON_SB
=PPPCI32_PWRON_SB
_PP3V3_PWRON_MODEM
=PP3V3_PWRON_USB
_PP3V3_PWRON_BT
=PP3V3_PWRON_CPU
=PP3V3_PWRON_EI
=PP3V3_PWRON_VESTA

PP5V_RUN

0.1UF

CRITICAL

46

PP3V3_PWRON

36

6 83

XW701
SM

P/N 518-0159

92

33

XW704
SM

VOLTAGE=0V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

_PP5V_PWRON_USB
=PP5V_PWRON_CPU
=PP5V_PWRON_RAM

VOLTAGE=5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
MAKE_BASE=TRUE

XW700
SM

59 11 7

RUN RAILS

PP24V_RUN

CRITICAL

PP24V_RUN

59

22 50 51

5%
1/8W
MF-LF
805

GND_CHASSIS_20_INCH_INVERTER
1
MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL
VOLTAGE=0
SDF700 IS USED FOR CPU HEATSINK MOUNTING

RTC BATTERY
ALWAYS ON (TRICKLE)
CRITICAL

DS700
SOD-123

13

=PP3V3_ALL_RTC

J702

R702

BB10209-A5

1K 2 PP3V3_ALL_BATT
2
1PP3V3_ALL_BATT_SAFETY 1
1
2
PP3V3_ALL_RTC
VOLTAGE=3.3V
VOLTAGE=3.3V
VOLTAGE=3.3V
5%
MIN_LINE_WIDTH=25MIL
MIN_LINE_WIDTH=25MIL
MIN_LINE_WIDTH=25MIL
1/16W
MIN_NECK_WIDTH=10MIL B0530WXF MIN_NECK_WIDTH=10MIL
MIN_NECK_WIDTH=10MIL TH
MF-LF
MAKE_BASE=TRUE
402

POWER CONN / ALIAS


A

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
3

4
SIZE

APPLE COMPUTER INC.

SMU RESET

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6772

OF

04
102

PCI CLOCKS

37

ALIAS

RAM_CKE_R<3>

37

ALIAS

RAM_CKE_R<6>

37

ALIAS

RAM_CKE_R<7>

37

ALIAS

RAM_MUXEN0

37

ALIAS

RAM_MUXEN4

37

ALIAS

RAM_CS_L_R<2>

37

ALIAS

RAM_CS_L_R<3>

37

ALIAS

RAM_CS_L_R<10>

37

ALIAS

RAM_CS_L_R<11>

37

TP_PCI_CLK_GP1
MAKE_BASE=TRUE
PCI_CLK33M_AIRPORT
MAKE_BASE=TRUE

I247

PCI_CLK_P3
_PCI_CLK33M_AIRPORT
PCI_CLK_P4

ALIAS

TP_ALS0_OUT
MAKE_BASE=TRUE
TP_ALS1_OUT
MAKE_BASE=TRUE
TP_ALS_GAIN_BOOST
MAKE_BASE=TRUE
TP_SMU_ONEWIRE
MAKE_BASE=TRUE

R850
180

5%
1/16W
MF-LF
2 402

LED850P1

LED850

13 8

RED

2
74 56 6

LED850P2

27

ALS0_OUT

13

ALIAS

ALS1_OUT

13

ALIAS

PP2V5_PWRON

ALS_GAIN_BOOST

13

ALIAS

PCI_RESET_L
MAKE_BASE=TRUE

4.7K

SMU_ONEWIRE

DEVELOPMENT

5%
1/16W
MF-LF
2 402

13

14

74LCX125

SMU_WARM_RESET_L

J800

U700
8
7

13

SMU_PWRSEQ_P1_3

13

SYS_DOOR_AJAR_L

13

FAN_PWM8

13

SYS_DRIVE_BAY_INT_L

13

NB_WARM_RESET_L

24

14
13

74LCX125

SMU_SLEEP

SYS_SLEEP

518S0104

14

74LCX125

125
13 TSSOP

12

NB_SUSPEND_ACK_L

11

NB_SUSPENDACK_L

76

SMU ANALOG VREF

75
77

DOWNLOAD
CONNECTOR
PP3V3_ALL

10K

5%
1/16W
MF-LF
2 402

R819

13

13

CPU_VID<4>

13

CPU_VID<5>

R809

10K

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

R804

10K

5%
1/16W
MF-LF
2 402

J802

13

6 33

6 33

CPU_VID_R<4>

6 33

CPU_VID_R<5>

6 33

NOSTUFF

NOSTUFF

R832

R831
1K

5%
1/16W
MF-LF
2 402

13

12

11

10

1K

5%
1/16W
MF-LF
2 402

NOSTUFF
1

R830
1K

5%
1/16W
MF-LF
2 402

e
r

NOSTUFF
1

R829
1K

5%
1/16W
MF-LF
2 402

NOTE:PULL UP CPU_VID<5>TO
2.2V FOR CPU VRM10.

BACKUP SMU RESET CIRCUIT

NOSTUFF

NOSTUFF

0.1uF
20%

P
DEVELOPMENT

R890

10V
CERM 2
402

R8011

1K

4.7K

5%
1/16W
MF-LF
2 402

VCC

U890

5%
1/16W
MF-LF
402 2

SM
8 7 6

SMU_MANUAL_RESET_L

DELAY

NOSTUFF RESET

SMU_RESET_L 6

NOSTUFF

NOSTUFF

C890 1

VOLTAGE DETECTOR
MC33465N_30ATR

0.01UF
10%

16V
CERM 2
402

C891
1uF

10%
6.3V
2 CERM
402

GND
3

NOSTUFF

R827

R811

1K

5%
1/16W
MF-LF
2 402

20K

5%
1/16W
MF-LF
2 402

J802_6

10

NOSTUFF
1

R805
0

5%
1/16W
MF-LF
402 2

1/16W
MF-LF
2 402

31 8 7 6 3

100

5%
1/16W
MF-LF
402

SMU_BOOT_BUSY
SMU_BOOT_RXD

C801

13

(SMU_BOOT_EPM)
SMU_MANUAL_RESET_L
SMU_BOOT_TXD

6 7 8
13

NOSTUFF

R803
10K
5%

1/16W
MF-LF
2 402

R800

2N3906

Q802_B

R838

5%
1/16W
MF-LF
2 402

29

ERROR_LED

C802

0.47UF

20%
10V
2 CERM
603

GND_SMU_AVSS

R833

2 GND_SMU_AVSS_DAGND

5%
1/16W
MF-LF
2 402

LED801_1
DEVELOPMENT
1

CPU HEATSINK SMT NUTS

SOT23

LED801

C880

0.01UF

C881

NOSTUFF

SDF803

OMIT

HSK-NUT-6.5MM

ZH804

TH
DEVELOPMENT

Q800

Q800_G

SOT23-LF

6P15R5P4

HS_SDF803 1

HS_SDF804

C883

0.01UF

DEVELOPMENT
2

DEVELOPMENT
3

R836
CHKSTOP_L 1

180

5%
1/16W
MF-LF
402

SDF700 IS ALSO
USED FOR HEATSINK
MOUNTING

C884

0.01UF

20%
16V
2 CERM
402

20%
16V
2 CERM
402

DEVELOPMENT

Q801

2N3904LF

Q801_B

SOT23
2

SIGNAL ALIAS

DEVELOPMENT

D810
RED

NOTICE OF PROPRIETARY PROPERTY

CLOCK_ERROR_L

SHASTA JTAG PULL DOWN

VESTA JTAG

TP_JTAG_VESTA_TCK
MAKE_BASE=TRUE
TP_JTAG_VESTA_TDI
MAKE_BASE=TRUE
TP_JTAG_VESTA_TDO
MAKE_BASE=TRUE
TP_JTAG_VESTA_TMS
MAKE_BASE=TRUE

ALIAS
ALIAS
ALIAS
ALIAS

ALIAS

=JTAG_VESTA_TRST_L

12
25

=JTAG_VESTA_TCK
=JTAG_VESTA_TDI
=JTAG_VESTA_TDO
=JTAG_VESTA_TMS

12
12
12
12

R840

10K

5%
1/16W
MF-LF
2 402

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

JTAG_SB_TRST_L

THESE PINS HAVE INTERNAL PULLUPS


JTAG_SB_TCK
TP_JTAG_SB_TCK
MAKE_BASE=TRUE ALIAS
JTAG_SB_TDI
TP_JTAG_SB_TDI
ALIAS
MAKE_BASE=TRUE
JTAG_SB_TDO
TP_JTAG_SB_TDO
ALIAS
MAKE_BASE=TRUE
JTAG_SB_TMS
TP_JTAG_SB_TMS
ALIAS
MAKE_BASE=TRUE

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT

25
25
25
25

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

R825

10K

SIZE

5%
1/16W
MF-LF
2 402

APPLE COMPUTER INC.

DRAWING NUMBER

REV.

051-6772

SHT
NONE

SM

JTAG_VESTA_TRST_L
MAKE_BASE=TRUE

C882

20%
16V
2 CERM
402

SCALE

0.01UF

20%
16V
2 CERM
402

2N7002

29 14 6

TH

HS_SDF802

0.01UF

20%
16V
2 CERM
402

27

TH

HS_SDF801

3
D

GREEN
2.0X1.25A
2

SDF802

TH

Q800_D

5%
1/16W
MF-LF
2 402

LED802

2N3904LF

NOSTUFF

SDF801

HS_SDF800 1

180

R835

Q803

NOSTUFF

SDF800

SM

R834

DEVELOPMENT

NOSTUFF

RED

DEVELOPMENT
1

LED802_1
DEVELOPMENT

36

180

13 33 36

DEVELOPMENT
1

5%
1/16W
MF-LF
2 402

Q803_C

5%
1/16W
MF-LF
402

2K PULLUP INSIDE P/S

NOSTUFF

=PP5V_RUN_CPU

180

5%
1/16W
MF-LF
2 402

2 Q803_B

5%
1/16W
MF-LF
402

POWER_GOOD IS A 5V DRIVEN
SIGNAL FROM POWER SUPPLY

HSK-NUT-6.5MM HSK-NUT-6.5MM HSK-NUT-6.5MM

13

5%
1/16W
MF-LF
402

PLLLOCK 1

31 8 7 6 3

1K

5%
1/16W
MF-LF
2 402

36

5%
1/16W
MF-LF
402

CHKSTOP LED

Q802_E

4.7K

2 PPVREF_SMU_ADC_REF

R828

180

6 13

R860

R802
1

SM
1

DEVELOPMENT

SYS_POWERFAIL_L
13

=PP5V_RUN_CPU

R837DEVELOPMENT
180
5%
Q802
1/16W

R839

330

=PPVREF_SMU

NOSTUFF

MF-LF
2 402

PPVREF_SMU
MAKE_BASE=TRUE

2.2UF

20%
10V
CERM 2
805

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

NOSTUFF

13

DEVELOPMENT

DEVELOPMENT

DEVELOPMENT

R810
1

J802_2 2

10K

430

1%
1/16W
MF-LF
2 402

PLL LOCK LED

PULSAR ERROR_L LED

=PP3V3_ALL_SMU

C800

10K
5%

PP3V3_RUN

13 7 6

518-0158

R807

5%
1/16W
MF-LF
402 2

NOSTUFF

R813 1R812

R818

J802 & R826 CAN MOVE TO DEVELOPMENT BOM POST RAMP

F-ST-SM
14

BM12B-SRSS-TB

NOSTUFF

1NOSTUFF

10K

6 33

CPU_VID_R<3>

5%
1/16W
MF-LF
402

J803

SMU_BOOT_CNVSS

R8061

CPU_VID_R<2>

R824
1

SMU_BOOT_SCLK
SMU_BOOT_CE

m
il
13

6 33

POWER_GOOD

NOSTUFF

R826

M-ST-TH

5%
1/16W
MF-LF
2 402

PP3V3_ALL
7

DEVELOPMENT

HC17051

10K

CPU_VID_R<1>

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

R808

10K

R822

R823
0

5%
1/16W
MF-LF
2 402

R817

13

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

CPU_VID<3>

10K

R820

5%
1/16W
MF-LF
402

R816

CPU_VID_R<0>

R821
CPU_VID<2>

POWER_FAIL_L
CONNECTION

200

DEVELOPMENT

R814

PP3V3_ALL_SMU_AVCC

13

PP3V3_RUN

13

a
n
i

13

49

SOT23

VID CONTROLLED BY SMU

CPU_VID<1>

6 9 10 11 22 46

125
4 TSSOP

U700
24

CPU VID<0:5>

13

6
7

NB_PMR_OBSV

U700

2N3904LF

5%
1/16W
MF-LF
402

CPU_VID<0>

F-ST-SM
3

8 25 74 77

24

SYS_SLOT_PWR

13

U.FL-R_SMT

SYS_WARM_RESET_L

125
10 TSSOP

13

PCI_AIRPORT_RESET_L
GPU_RESET_L
=PCI_ROM_RESET_L
=PCI_USB2_RESET_L

Q850

y
r

R870

13 8

2 DIAG_LED_R

8 25 74 77

76

SM

1K

13 24

27

ALIAS

TP_SYS_SLOT_PWR
ALIAS
MAKE_BASE=TRUE
TP_SMU_PWRSEQ_P1_3
ALIAS
MAKE_BASE=TRUE
TP_SYS_DOOR_AJAR_L
ALIAS
MAKE_BASE=TRUE
TP_FAN_PWM8
ALIAS
MAKE_BASE=TRUE
TP_SYS_DRIVE_BAY_INT_L ALIAS
MAKE_BASE=TRUE
SMU_WARM_RESET_L
ALIAS
MAKE_BASE=TRUE

1
DIAG_LED
MAKE_BASE=TRUE

SYS_COLD_RESET_L
SYS_WARM_RESET_L

DIAG LED

R851

DIFFERENTIAL_PAIR

10 MIL SPACING
10 MIL SPACING

27

PCI_CLK_P1

ALIAS

NET_SPACING_TYPE

SMU_RESET
SMU_RESET

I246
27

SMU

PP5V_ALL

ELECTRICAL_CONSTRAINT_SET

77

PCI_CLK_GP1

ALIAS

TP_PCI_CLK_P4
MAKE_BASE=TRUE
PCI_CLK33M_SB_EXT
MAKE_BASE=TRUE

74 27

27

PCI_CLK_GP0
=PCI_CLK33M_USB2

24

2.5V

RAM_CKE_R<2>

ALIAS

PCI_CLK33M_USB2
MAKE_BASE=TRUE

24

SSOT-23

ALIAS

2
3

NB_THMI
NB_THMO

ALIAS

VR801

TP_NB_THMI
MAKE_BASE=TRUE
TP_THMO
MAKE_BASE=TRUE
TP_RAM_CKE_R<2>
MAKE_BASE=TRUE
TP_RAM_CKE_R<3>
MAKE_BASE=TRUE
TP_RAM_CKE_R<6>
MAKE_BASE=TRUE
TP_RAM_CKE_R<7>
MAKE_BASE=TRUE
TP_RAM_MUXEN0
MAKE_BASE=TRUE
TP_RAM_MUXEN4
MAKE_BASE=TRUE
TP_RAM_CS_L_R<2>
MAKE_BASE=TRUE
TP_RAM_CS_L_R<3>
MAKE_BASE=TRUE
TP_RAM_CS_L_R<10>
MAKE_BASE=TRUE
TP_RAM_CS_L_R<11>
MAKE_BASE=TRUE

OF

04
102

2.5V VOLTAGE REGULATOR

y
r

PP5V_PWRON

PP5V_PWRON

D900
2

1
1

MBR0520LXXG
SOD-123

R900

SOD-123

5%
1/8W
MF-LF
2 805

20%
25V
2 CERM
805

VC

U900

IRU3037CS
SOI

HD
8

U900_SS

U900_COMP

U900_GATE_H

SS
LD

FB

U900_GATE_L

R902
1

Q901
Q901_GATE

5%
1/8W
MF-LF
805

NTD60N02R

1
G

C915
0.47UF

20%
10V
2 CERM
603

1%
1/16W
MF-LF
2 402

R901_P2
1

C914

3900PF

56PF

5%
50V
2 CERM
402

5%
2 50V
CERM
603

1800UF

C903

1800UF

20%
2 6.3V
ELEC
TH-KZJ

NOSTUFF

L901
2

R904

U900_FEEDBACK

220PF

5%
25V
2 CERM
402

NTD60N02R

1
G

C906
1

C905

5%
1/4W
MF-LF
2 1206

Q902
1

NOSTUFF

1.1K

D 4

VOLTAGE=2.5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

TH

1
6

C907

3300PF

10%
2 50V
CERM
603

R903
10.7K

1%
1/16W
MF-LF
2 402

C912

m
il

2200PF

5%
50V
2 CERM
603

1UF

R905

20%
25V
2 CERM
1206

10K

1%
1/16W
MF-LF
2 402

U900_FEEDBACK

e
r

PEAK CURRENT OF TOTAL RAILS


12.68A WITH DIMM TERMINATION
9.24A WITHOUT DIMM TERMINATION

C908

1800UF

NOSTUFF
1

NOTE:
SET OUTPUT=2.588V FOR FRAMEBUFFER.
IRU3037CS VREF=1.25VDC
VOUT=VREF*(R903+R905)/R905=2.588VDC

PP12V_RUN

R904_P2

CASE369

S3

1800UF

a
n
i

CRITICAL

Q902_DRAIN

C910

20%
2 6.3V
ELEC
TH-KZJ

PP2V5_PWRON

1.6UH

MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL

C913

C902

20%
2 6.3V
ELEC
TH-KZJ

C917

20%
10V
2 CERM
603

S3

GND
1

20%
2 6.3V
CERM
1206

1UF

CASE369

27.4K

C911
10UF

20%
2 6.3V
CERM
1206

D 4

COMP

R901

10UF

U900_VC_D

C916
1UF

VCC

C901

MBR0520LXXG
SOD-123
1

1UF

20%
2 25V
CERM
805

D901
U900_VC_R

U900_VC

C904

D902
MBR0520LXXG

4.7

20%
2 6.3V
ELEC
TH-KZJ

R940

C909

470K

1800UF

5%
1/16W
MF-LF
2 402

20%
2 6.3V
ELEC
TH-KZJ

5 6

Q903
IRF7413

HIGH TO ENABLE
Q903_GATE

SO-8

NOSTUFF

C940

0.001UF

2 3

PP2V5_RUN

20%
2 50V
CERM
402

DEVELOPMENT
1

R950
240

5%
1/16W
MF-LF
2 402
3

LED_PP2V5_RUN

Q940

2N7002

46 22 11 10 8 6

SYS_SLEEP

SOT23-LF

DEVELOPMENT

LED900

GREEN
2.0X1.25A

2
2

2.5V VREG
A

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6772

OF

04
102

PP1V2_ALL VOLTAGE REGULATOR


PP5V_ALL

PP5V_ALL

NOTE:
SET OUTPUT=1.2V
IRU3037ACS VREF=0.8VDC
VOUT=VREF*(R1003+R1005)/R1005=1.206VDC

D1000
2

1
1

MBR0520LXXG
SOD-123

R1002

MBR0520LXXG C1001
10UF
SOD-123

4.7
5%
1/8W
MF-LF
2 805

1UF

20%
2 25V
CERM
805

VCC

2 CERM
805

VC

U1000

HD

U1000_COMP

U1000_GATE_H

Q1001
NTD60N02R

1
G

CASE369

S3

MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL

LD

U1000_GATE_L

FB

U1000_FEEDBACK

0.1UF

C1014
3900PF

Q1002

C1013

C1006

5%
25V
2 CERM
402

NTD60N02R

1
G

NOSTUFF

220PF

5%
50V
2 CERM
603

CASE369

C1005

S3

0.022UF

1
TH

NOSTUFF

C1012

10K

1%
1/16W
MF-LF
2 402

e
r
RDSON=0.06 OHM
@ VGS=2.5 V

TSOP

R1009
2

R10141
5%
1/16W
MF-LF
402 2
3

R1013
SYS_POWERUP_L

5%
1/16W
MF
402-1

Q1006_G

P
R1012

TURN_ON_PP1V2_PWRON_L
NOSTUFF

33 13 11 7 6

100K 1
5%
1/16W
MF-LF
402

100K

5%
1/16W
MF-LF
402

PP5V_ALL

Q1005_G

PP1V2_RUN FET SWITCH

Q1005

Q1003

TSOP

50 34 22 18 11 10 7 6

5%
1/16W
MF-LF
402

20%
10V
2 CERM
402

DEVELOPMENT

5
3

5%
1/16W
MF-LF
2 402

0.1UF

Q1003_G

330

C1050

PP3V3_RUN

R10511

LED_PP1V2_RUN_P

100K

5%
1/16W
MF-LF
402 2

DEVELOPMENT

R1053
1

RDSON=?? OHM
@ VGS=?? V

GREEN
2.0X1.25A

LM339A

U1001
5

1V1_REF

SOI

V+

50 34 22

DEVELOPMENT

LED1000

DEVELOPMENT

PP1V2_RUN_FOR_LED

5%
1/16W
MF-LF
402

LED_PP1V2_RUN_N

GND
PLACE LED1000 NEAR VREG
12

DEVELOPMENT
1

R1052
47K

SOT23-LF

6 7 10 11 18 22 34 50

R1050

DEVELOPMENT

SI3446DV

2N7002

PP3V3_RUN

DEVELOPMENT

R1008
100K 1

6 7 11 18

PP5V_ALL

PP5V_RUN

PP1V2_RUN

PP1V2_ALL

PP1V2_PWRON

PP3V3_ALL

7 10

PEAK CURRENT ??A

PP1V2_ALL

SI3446DV

1800UF

R1005

10 7

Q1006

C1009

20%
2 6.3V
ELEC
TH-KZJ

m
il

PEAK CURRENT ??A

1%
1/16W
MF-LF
2 402

10%
2 50V
CERM
603

R1004_P2
1

1
C1007 R1003
5.11K

3300PF

20%
25V
2 CERM
1206

PP1V2_PWRON FET SWITCH

y
r

PEAK CURRENT OF TOTAL RAILS


~3A
<-- NEED TO VERIFY

NOSTUFF

5%
1/4W
MF-LF
2 1206

a
n
i

U1000_FEEDBACK

10 7

10UF

20%
6.3V
2 CERM
1206

PP1V2_ALL
VOLTAGE=1.2V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=15MIL

1UF

10%
50V
2 CERM
603

5%
2 50V
CERM
603

L1001

1.1K

D 4

68PF

R1001_P2

20%
16V
2 CERM
603

C1003

1UF

20%
10V
2 CERM
603

R1004

4
1

10UF

C1017

NOSTUFF

GND

1%
1/16W
MF-LF
2 402

C1015

20%
6.3V
2 CERM
1206

Q1002_DRAIN

COMP

27.4K

20%
6.3V
2 CERM
1206

1.6UH

SS

R1001

D 4

Q1001_GATE

5%
1/8W
MF-LF
805

SOI
8

U1000_VC_D

C1000
1UF
20%
R1000
25V

IRU3037ACS
U1000_SS

C1002

MBR0520LXXG
SOD-123

U1000_VC

C1004

D1001
U1000_VC_R

D1002

Q1004

2N7002DW

5%
1/16W
MF-LF
402 2

Q1004

2N7002DW

SOT-363

SOT-363
5

S
4

SYS_SLEEP

6 8 9 11 22 46

1.2V VREG
A

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6772

10

OF

04
102

11 7 6

PP5V_ALL

D
CRITICAL

y
r

Q1100

SI4467DY
18 10 7 6

PP5V_PWRON

SM-1

PP5V_RUN

6 18

VOLTAGE=5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

PP5V_PWRON

3
7

2
1

59 11 7

R1100
R1104

33 13 10 7 6

46 22 10 9 8 6

SYS_POWERUP_L

SYS_SLEEP

5%
1/16W
MF-LF
402

100K 2

LM339A
V+

5%
1/16W
MF-LF
402
RAIL_CTL_POS

PP3V3_RUN

Q1102

1%
1/16W
MF-LF
2 402

SI4467DY
3
7

13

GND

a
n
i
2
1

RUN -> LOW


SLEEP -> FLOAT
SHUTDOWN -> FLOAT

FET ON IN RUN

Q1103

SI3443DV

LM339A

U1100

RAIL_CTL_NEG
5

SOI

TSOP

GND

RAIL_SLEEP_FET
MIN_LINE_WIDTH=20MIL

47.0K

Q1101

SI3443DV

RUN -> FLOAT


SLEEP -> LOW
SHUTDOWN -> FLOAT

1%
1/10W
MF-LF
603 2

TSOP

1
2

PP3V3_ALL

FET ON IN SLEEP

m
il

CRITICAL

PROCESS SWING
3.30V - 3.45V

SENSE

VR1100

Vpwr >= Vout+0.35V

5
4

Vctrl >= Vout+1.25V

CS5253
SM
VPWR VOUT
VCTRL VOUT
TAB
ADJ

47UF

R1105
124

R1

e
r

C1101
0.1UF

N20P80%
16V
2 CERM
603

20%
2 10V
ELEC
SM

Vref=1.250V typ
Iadj=50uA typ

MIN_NECK_WIDTH=10MIL

C1102

7 11 59

VOLTAGE=3.3V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

Vout=Vref(1+R2/R1)+Iadj(R2)

2
3_3V_ALL_ADJ
MIN_LINE_WIDTH=20MIL

FET ON IN SLEEP

PP5V_ALL

1
2

MIN_NECK_WIDTH=10MIL
CRITICAL

12

R11021

11 7 6

V+

6 18 27 58

VOLTAGE=3.3V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

CRITICAL

RAIL_RUN_FET
MIN_LINE_WIDTH=20MIL

MIN_NECK_WIDTH=10MIL

12

PP3V3_PWRON

SM-1
8

SOI

U1100
11

50 34 22 18 10 7 6

1K

1%
1/16W
MF-LF
2 402

CRITICAL

10

100K 2

1K

R1103

5%
1/16W
MF-LF
402

R1107 1R1101

FET ON IN RUN

100K 2
1

PP3V3_ALL

1%
1/10W
MF-LF
2 603

C1100
100UF

20%
2 10V
ELEC
SM

R1106
210

R2

1%
1/10W
MF-LF
2 603

5V & 3.3V VREGS


A

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6772

11

OF

04
102

Page Notes
Power aliases required by this page:

Signal aliases required by this page:


(NONE)

BOM options provided by this page:


- VESTA1V2_BURST / VESTA1V2_PULSE
Controls operating mode of Vesta 1.2V
regulator. If both options are off the
regulator will be in continuous mode.

Ethernet LowPwr

y
r

2.5V LDO

ETHERNET PORTION IN LOW POWER MODE


WHEN NOT IN RUN MODE.

PP2V5_VESTA
12
VOLTAGE=2.5V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
MAKE_BASE=TRUE

CRITICAL
PP3V3_VESTA 7

U1280

12

MM1572FN
SOT-25A

R1262

12 7

a
n
i

100K

5%
1/16W
MF-LF
2 402

=PP3V3_PWRON_VESTA

VESTA_ENET_LOWPWR

R1260

C1280

86

5%
1/16W
MF-LF
2 402

1
3

1K

SOT23

C1261

20%
2 10V
CERM
402

5%
1/16W
MF-LF
402 2

Reset RC values per


Broadcom recommendation

Q1250

2N7002

ENETFW_RESET

0.1uF

SOT23-LF

C1250
1uF

20%
10V
2 CERM
603

DVDD

20%
10V
2 CERM
402

R12521

5%
1/16W
MF-LF
402 2

4.7K

=JTAG_VESTA_TDI
=JTAG_VESTA_TDO
=JTAG_VESTA_TCK
=JTAG_VESTA_TMS
=JTAG_VESTA_TRST_L

TP_VESTA_DNC_B9
R1252 to enable wirespeed feature
TP_VESTA_DNC_C9
TP_VESTA_DNC_E9

C1282
10UF

10%
6.3V
2 X5R
805

0.1uF

C1222

0.1uF

20%
10V
CERM 2
402

C1223

0.1uF

20%
10V
CERM 2
402

C1224

0.1uF

20%
10V
CERM 2
402

12

C1225 1

0.1uF

20%
10V
CERM 2
402

AVDD

H4

20%
10V
CERM 2
402

20%
10V
CERM 2
402

D7
E10
E7
E8
D8

B9
C9
E9

TDI
TDO
TCK
TMS
TRST*

C1231 1
0.1uF

20%
10V
CERM 2
402

PP3V3_VESTA

7 12

PVDD

VESTA MISC

RESET*

0.1uF

A15
N4

R3
R12

C1230

A1

NC C3
NC M13

To keep Vesta from being held


in reset when system is off
NOTE: Reset GPIO is active HIGH

AVDDL

P11

C1213

Schmitt trigger

PP3V3_VESTA

C1221

N9/N10

OVDD

0.1uF

20%
10V
2 CERM
402

20%
16V
CERM 2
402

0.1uF

P5
P10

C1212

0.01uF

C1240
0.1uF

C1241
0.1uF

20%
10V
CERM 2
402

20%
10V
CERM 2
402

A7
F15

C1242
0.1uF

20%
10V
CERM 2
402

C1243 1
0.1uF

20%
10V
CERM 2
402

K1

OMIT

U8600

2.5V_EN M3

TP_VESTA_2_5V_EN

REGSUP1 E1
REGSEN1 F1
REGCTL1 G5

TP_VESTA_REGSUP1
TP_VESTA_REGSEN1
TP_VESTA_REGCTL1

REGSUP2 E2
REGSEN2 F2
REGCTL2 G4

TP_VESTA_REGSUP2
TP_VESTA_REGSEN2
TP_VESTA_REGCTL2

BCM5462
FBGA-200
1 OF 3

DNC
DNC
DNC

Vesta Core / Misc

NC
NC

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

B2
B7

A2

P9

P8

P6
P7

GND
N8

M8
N7

M7

L7
L8

J11
J12

H12

H11

AGND

SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-6772

SCALE

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

K2

12 7

82K

25

0.1uF

20%
10V
2 CERM
402

N5/N6

VESTA_RESET_L

R12511

C1211

L9/M9

20%
10V
CERM 2
402

C1203

F14
J2

12 7

C1281 1

86 89

Vout = 2.5V @ 150 mA

20%
10V
2 CERM
402

C14

0.1uF

20%
10V
2 CERM
402

0.1uF

P4

P
C1210

C1202

20%
10V
2 CERM
402

N10

0.1uF

L6/M6

C1201

20%
10V
2 CERM
402

N6
N9

0.1uF

N5

C1200

20%
10V
2 CERM
402

M6
M9

10UF

L9

C1208

10%
6.3V
2 X5R
805

0.1uF

L6

PP3V3_VESTA

VESTA2V5_NOISE
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

GND

=PP2V5_ENETFW

ALIAS

PP2V5_VESTA

C1220 1

C15
J1

SM

B15

m
il

e
r

PP1V2_VESTA_AVDDL
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

FERR-EMI-600-OHM
1

10%
6.3V
2 CERM
402

B1

PP1V2_VESTA

C1260

0.1UF

L1200

2N3904LF

NOSTUFF

CONT NOISE

10%
6.3V
CERM 2
402

1uF

Q1260

VESTA_ENET_HIGHPWR

5%
1/16W
MF-LF
2 402

VOUT 5

VIN

1uF

2.0K

R1261

PP3V3_VESTA

04

12 102
OF

ELECTRICAL_CONSTRAINT_SET

NET_SPACING_TYPE

SMU_CLK10M_XTAL

15 MIL SPACING
15 MIL SPACING
15 MIL SPACING

SMU_CLK10M_XIN
SMU_CLK10M_XOUT
SMU_CLK10M_XOUT_R

15 MIL SPACING
15 MIL SPACING

RTC_CLK32K_X1
RTC_CLK32K_X2

Real Time Clock

13
13
7

13

13 8 7 6

System Management Unit

13

C1308 1

13 8 7 6

Power aliases required by this page:


- _PP3V3_ALL_SMU
- _PP3V3_ALL_RTC
- _PP3V3_PWRON_SMU
- _PPVREF_SMU (SMU AVCC or 2.5V reference)

C1300 1
10uF

20%
6.3V
CERM 2
805

C1301 1

C1302 1

0.1uF

0.1uF

20%
10V
CERM 2
402

4.7

5%
1/16W
MF-LF
402

NOTE: CPU current/voltage monitoring


(CPU_SENSE_I/CPU_SENSE_V) requires
100K/10uF RC filter at SMU pins.
Caps should connect to GND_SMU_AVSS.
SMU_VREF should be same signal or
reference used by monitoring
circuit, but be aware that this will
affect other analog inputs such as
AC adapter ID.

33
33
36
30
13
13
13
8

NOTE: All analog inputs to SMU should have


a 100pF capacitor to the SMU AVSS
signal (GND_SMU_AVSS). None of
those capacitors are provided on
this page.

3
3
3
8

NOTE: Some primary and alternate functions


reuire pull-ups that are not.
provided on this page. Please.
review the latest SMU specification
to ensure missing pull-ups are
provided on another page.

3
13 8 6
13 8
13 8

18
18

NOTE: Pinout matches SMU pinout v1.51.

16
16
17
13
13
13

18
18 14 6

NO_SMU_I2C_D

18

R1399
25

13 8 7 6

SMU_TO_SB_INT_L

18 14 6

18

5%
1/16W
MF-LF
402

=PP3V3_ALL_SMU

18
13
27 25 16

SOT23

8 6

13

C1310

13

0.22uF

20%
6.3V 2
CERM
402

R13171

5%
1/16W
MF-LF
402 2

13

SMU_CLK10M_XOUT

C1304

18pF

10M

CPU_VID<0>
CPU_VID<1>
CPU_VID<2>
CPU_VID<3>
CPU_VID<4>
CPU_VID<5>
SMU_BOOT_RXD
SMU_BOOT_TXD

SDA
SCL
TA1out
TA1in
TA2out
TA2in
TA3out
TA3in

P7[0] 27
P7[1] 26
P7[2] 25
P7[3] 24
P7[4] 23
P7[5] 22
P7[6] 21
P7[7] 20

Y
Y
Y
Y
Y
Y
N
Y

Y
Y
Y
Y
Y
Y
S
Y

Y
Y
Y
Y
Y
Y
S
Y

Y
Y
N
Y
N
Y
Y
Y

Y
Y
N
Y
N
Y
Y
Y

I2C_SMU_B_SDA
I2C_SMU_B_SCL
I2C_SMU_CPU_SDA_IN
FAN_RPM0
I2C_SMU_CPU_SCL_IN
FAN_RPM1
FAN_PWM8
FAN_RPM2

SDAmm
SCLmm
IOC2
IOC3
IOC4
IOC5
IOC6
IOC7

TA4out
TA4in
INT0*
INT1*
INT2*
NMI*
CE*

P8[0] 19
P8[1] 18
P8[2] 17
P8[3] 16
P8[4] 15
P8[5] 14
P8[6] 8
P8[7] 7

Y
Y
Y
S
Y
Y
Y
Y

Y
Y
Y
S
Y
Y
Y
Y

Y
Y
Y
S
Y
Y
Y
Y

Y
Y
Y
S
Y
S
Y
Y

Y
Y
Y
S
Y
S
Y
Y

SYS_LED
SYS_COLD_RESET_L
SYS_PME_L
SMU_QREQ
SYS_SLEWING_L
I2C_SMU_CPU_SDA_OUT_L
SYS_POWERUP_L
MAKE_BASE=TRUE
SMU_SLEEP

P3[0] CLK3
P3[1] Sin3
P3[2] Sout3
P3[3]
P3[4]
P3[5]
P3[6]
P3[7]

TB0in
TB1in
TB2in
AN24
AN25
AN26
AN27

P9[0] 5
P9[1] 4
P9[2] 3
P9[3] 2
P9[5] 1
P9[6] 80
P9[7] 79

Y
Y
Y
Y
Y
Y
S

Y
Y
Y
Y
Y
Y
S

Y
Y
Y
Y
Y
Y
Y

Y
S
Y
Y
Y
Y
Y

Y
S
Y
Y
Y
Y
S

CLOCK_RESET_L
CPU_HRESET
SB_TO_SMU_INT_L
SB_STOPXTALS_L
SMU_PWRSEQ_P9_5
SMU_PWRSEQ_P9_6
SYS_SLOT_PWR

AN0 P10[0] 76
AN1 P10[1] 74
AN2 P10[2] 73
AN3 P10[3] 72
KI0* P10[4] 71
KI1* P10[5] 70
KI2* P10[6] 69
KI3* P10[7] 68

S
Y
Y
Y
Y
Y
Y
Y

S
Y
Y
Y
Y
Y
Y
Y

S
Y
Y
Y
Y
Y
Y
Y

S
Y
Y
Y
Y
Y
Y
S

S
Y
Y
Y
Y
Y
Y
S

TP_SMU_SPARE_P10_0
SMU_WARM_RESET_L
NB_SUSPENDACK_L
SB_SUSPENDACK_L
SMU_SUSPENDREQ_L
SYS_POWER_BUTTON_L
SYS_RESET_BUTTON_L
I2C_SMU_CPU_SCL_OUT_L

SMU_PWRSEQ_P1_0
SMU_PWRSEQ_P1_1
SMU_PWRSEQ_P1_2
SMU_PWRSEQ_P1_3
SMU_PWRSEQ_P1_4
SYS_POWERFAIL_L
SYS_DRIVE_BAY_INT_L
SYS_DOOR_AJAR_L

Y
Y
Y
Y
Y
N
N
N

Y
Y
Y
Y
Y
Y
S
S

Y
Y
Y
Y
Y
Y
S
Y

Y
Y
Y
Y
Y
Y
S
Y

Y
Y
Y
Y
Y
Y
Y
Y

59
58
57
56
55
54
53
52

P1[0]
P1[1]
P1[2]
P1[3]
P1[4]
P1[5]
P1[6]
P1[7]

AN20
AN21
AN22
AN23

I2C_SMU_E_SDA
I2C_SMU_E_SCL
FAN_TACH0
FAN_TACH1
FAN_TACH2
FAN_TACH3
FAN_TACH4
FAN_TACH5

Y
Y
Y
Y
Y
S
S
S

Y
Y
Y
Y
Y
N
N
N

Y
Y
Y
Y
Y
Y
Y
Y

Y
Y
Y
Y
Y
Y
Y
Y

Y
Y
Y
Y
Y
Y
Y
Y

51
50
49
48
47
46
45
44

P2[0]
P2[1]
P2[2]
P2[3]
P2[4]
P2[5]
P2[6]
P2[7]

Y
Y
Y
Y
Y
Y
Y
Y

Y
Y
Y
Y
Y
Y
S
S

Y
Y
Y
Y
Y
Y
S
S

Y
Y
Y
Y
Y
Y
S
S

Y
Y
Y
Y
Y
Y
S
S

39
38
37
36
35
34
33
32

R13251

R1316
1

N
N
N
S
S
S
Y
Y

AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07

NO STUFF

10K

5%
1/16W
MF-LF
402 2

5%
1/16W
MF-LF
402

QFP-80
OMIT

INT3*
INT4*
INT5*

PCNVSS
RESET*
XOUT
XIN
VREF

C1325
1uF

VSS

75

XW1300
SM
1

8 13
8 13
8
8

8
8
8

18
18

13 18
16

13 18
16

Keep crystal subcircuit close to SMU.

13
13
13 8 6
13 8
13 8
13 8

FAN_RPM3
FAN_RPM4
FAN_RPM5
SYS_POWERFAIL_L
SYS_DRIVE_BAY_INT_L
SYS_DOOR_AJAR_L
FAN_PWM8

Port
0.4
0.5
0.6
1.5
1.6
1.7
7.6

ALS0_OUT
ALS1_OUT
ALS_GAIN_BOOST
SMU_ACIN
SMU_BATT_DET_L
SYS_LID_OPEN
SYS_KBDLED

13

13

13
13

FAN_TACH3
FAN_TACH4
FAN_TACH5
SMU_CHARGE_BATT

Port
2.5
2.6
2.7
3.6

RTC_CLK32K_X2
1

0.1uF

20%
2 10V
CERM
402

6 7 8 13

R1300
1

21

13 25 77

28

10K

5%
1/16W
MF-LF
402

13 25 27 33
18

10K

5%
1/16W
MF-LF
402

R1302

8 13 24

SYS_POWERUP_L

6 7 10 11 13 33

SYS_POWER_BUTTON_L

6 7 13

SYS_RESET_BUTTON_L

7 13

R1303
1

6 7 10 11 13 33

10K

5%
1/16W
MF-LF
402

8 13

27
30
25

PP3V3_PWRON

R1304

25
3

10K

SYS_PME_L

13 25 77

SYS_SLEWING_L

13 25 27 33

SMU_SUSPENDREQ_L

13 24 25 28

SYS_COLD_RESET_L

8 13 24

SMU_SLEEP

8 13

5%
1/16W
MF-LF
402

R1312
1

2.0K 2
5%
1/16W
MF-LF
402

8
25
13 24 25 28

NO STUFF

PP2V5_PWRON

7 13

18

100K 2
1

R1327
10K

2.0K 2
5%
1/16W
MF-LF
402

R1313

R1311

6 7 13

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
2 402

R1310

GND_SMU_AVSS 8 13 33 36
VOLTAGE=0V
MIN_LINE_WIDTH=15 mil
MIN_NECK_WIDTH=10 mil

100K 2
5%
1/16W
MF-LF
402

C1305
18pF

5%
50V
CERM 2
402

MASTER: SEEDY

System Management Unit

SYS_LED_RED
SYS_LED_GREEN
SYS_LED_BLUE
DIAG_LED

21

13 8

21

13 8

21

13 8

18 13
18 13

CPU_VID<0>
CPU_VID<1>
CPU_VID<2>
I2C_SMU_CPU_SDA_IN
I2C_SMU_CPU_SCL_IN

Port
6.0
6.1
6.2
7.2
7.4

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

FAN_TACH6
FAN_TACH7
FAN_TACH8
FAN_PWM6
FAN_PWM7

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

REV.

051-6772
SHT
NONE

NOTICE OF PROPRIETARY PROPERTY

Tower & Server

SCALE

13

C1309

Consumer

SM-1

=PP3V3_ALL_SMU

17

Alternate Functions
Portable

Y1301

32.768K
4

11.4X4.7X4.2-SM

5%
50V
CERM 2
402

1
2

8 13

10.000M
1
2

X1
X2
SCL
SQW/ VBAT
OUT GND

13

CRITICAL

SMU Pull-ups / pull-down

CRITICAL

Y1300

SDA

MSOP

PP3V3_RUN

AVSS

11

10%
6.3V
2 CERM
402

8 13

a
n
i

m
il
1

N
N
N
S
S
S
Y
Y

P0[0]
P0[1]
P0[2]
P0[3]
P0[4]
P0[5]
P0[6]
P0[7]

6
9
10
12
77

Y
Y
Y
Y
Y
Y
Y
Y

67
66
65
64
63
62
61
60

SMU_BOOT_CNVSS
SMU_RESET_L
SMU_CLK10M_XOUT_R
SMU_CLK10M_XIN

Y
Y
Y
Y
Y
Y
Y
Y

S
S
S
S
Y
Y
Y
Y

I2C_SMU_A_SDA_IN
I2C_SMU_A_SDA_OUT_L
I2C_SMU_A_SCL_IN
I2C_SMU_A_SCL_OUT_L
I2C_SMU_D_SDA
I2C_SMU_D_SCL
SMU_CHARGE_BATT
SYS_OVERTEMP_L

SMU_BOOT_BUSY
SMU_BOOT_SCLK
SMU_BOOT_CE

Y
Y
Y
Y
Y
Y
Y
Y

S
S
S
S
Y
Y
Y
Y

=PPVREF_SMU

8 13 33 36

RTS0*/
CTS0* P6[0] 43
CLK0 P6[1] 42
RXD0 P6[2] 41
TXD0 P6[3] 40
RTS1*
(BUSY) P6[4] 31
CLK1 P6[5] 30
RXD1 P6[6] 29
TXD1 P6[7] 28

Y
Y
Y
Y
Y
Y
Y
Y

e
r

5%
1/16W
MF-LF
2 402

AVCC

U1300

M30280F8

Y
Y
Y
Y
S
S
S
Y

150K

D1310

VCC

Y
Y
Y
Y
N
N
N
Y

R1322

MMBD914XXG

78

CPU_SENSE_I
CPU_SENSE_V
CPU_TEMP
CPU_BYPASS
FAN_RPM3
FAN_RPM4
FAN_RPM5
SMU_ONEWIRE

1
3

13

I2C_RTC_SCL

NC

Portable
Consumer
Entry Desktop
Desktop
Server

Y = Primary function
N = Alternate function
(see aliases below)
S = Spare

I2C_RTC_SDA

18

y
r

10%
6.3V
2 CERM
402

RTC_CLK32K_X1

U1301
DS1338U-33

18

C1303
1uF

20%
10V
CERM 2
402

VCC

20%
10V
CERM 2
402

PP3V3_ALL_SMU_AVCC 8
VOLTAGE=3.3V
MIN_LINE_WIDTH=15 mil
MIN_NECK_WIDTH=10 mil

GND_SMU_AVSS

BOM options provided by this page:


(NONE)

13

0.1uF

R1315

=PP3V3_ALL_SMU

Signal aliases required by this page:


(NONE)

=PP3V3_ALL_RTC
=PP3V3_ALL_SMU

13

Page Notes
D

DIFFERENTIAL_PAIR

Portable
Consumer
Entry Desktop
Desktop
Server

RTC_CLK32K_XTAL

OF

13
1

04

102

DEVELOPMENT

R1400
27

EI_CPU1_CLK_P_R

5%
MF-LF

EI_CPU1_CLK_P

6 14 27

EI_CPU1_CLK_N

6 14 27

1/16W
402

DEVELOPMENT

R1401

27

EI_CPU1_CLK_N_R

1
5%
MF-LF

D
27

CPU1_HTBEN_R

2
1/16W
402

DEVELOPMENT
0 R1402
1

CPU1_HTBEN

6 14

EI_CPU1_SYNC

6 14 27

y
r

5% 402

27

EI_CPU1_SYNC_R

DEVELOPMENT
0 R1403
1

5% 402

=PP1V2_EI_CPU 7

18 29 30 31 35

28 18 14 7

NOSTUFF

=PP1V2_EI_NB 7

J1400
YFS-30-03-H-08-SB
F-ST-BGA
27 14 6
29 8 6

H1

EI_CPU1_SYNC
CHKSTOP_L

H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12

H13
H14
H15
H16
29 28 6
29 28 6
29 28 6
29 28 6
29 28 6
29 28 6
29 28 6
29 28 6
29 28 6
29 28 6
29 28 6
29 28 6
30 29 6
30 29 28 6

H17

EI_NB_TO_CPU_AD<13>
EI_NB_TO_CPU_AD<15>
EI_NB_TO_CPU_AD<17>
EI_NB_TO_CPU_AD<21>
EI_NB_TO_CPU_AD<20>
EI_NB_TO_CPU_AD<25>
EI_NB_TO_CPU_AD<29>
EI_NB_TO_CPU_AD<28>
EI_NB_TO_CPU_AD<40>
EI_NB_TO_CPU_AD<10>
EI_NB_TO_CPU_AD<39>
EI_NB_TO_CPU_AD<36>
RI_L
EI_QREQ_L

H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H29
H30

H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H29
H30

G1 G1
G2 G2
G3 G3 NC
G4 G4
G5 G5
G6 G6
G7 G7
G8 G8
G9 G9
G10 G10
G11 G11
G12 G12 NC
G13 G13
G14 G14
G15 G15
G16 G16
G17 G17
G18 G18
G19 G19
G20 G20
G21 G21
G22 G22
G23 G23
G24 G24
G25 G25
G26 G26
G27 G27
G28 G28
G29 G29
G30 G30

EI_CPU1_CLK_P

6 14 27

14 6
27

EI_CPU1_CLK_N

F1
F2
F3
F4

EI_CPU_TO_NB_AD<3> 6 28 29
EI_CPU_TO_NB_AD<4> 6 28 29
EI_CPU_TO_NB_AD<7> 6 28 29
EI_CPU_TO_NB_AD<11> 6 28 29
EI_CPU_TO_NB_CLK_N 6 28 29
EI_CPU_TO_NB_CLK_P 6 28 29
EI_CPU_TO_NB_SR_N<1> 6 28 29
EI_CPU_TO_NB_SR_P<1> 6 28 29

F5
F6
F7
F8
F9
F10
F11
F12

EI_CPU_TO_NB_AD<17>
EI_CPU_TO_NB_AD<14>
EI_CPU_TO_NB_AD<24>
EI_CPU_TO_NB_AD<28>
EI_NB_TO_CPU_AD<14>
EI_NB_TO_CPU_AD<12>
EI_NB_TO_CPU_AD<18>
EI_NB_TO_CPU_AD<19>
EI_NB_TO_CPU_AD<27>
EI_NB_TO_CPU_AD<26>
EI_NB_TO_CPU_AD<30>
EI_NB_TO_CPU_AD<42>
EI_NB_TO_CPU_AD<41>

6 28 29

F13

6 28 29

F14
F15

6 28 29

F16

6 28 29
6 28 29 28 6
29
6 28 29

EI_NB_TO_CPU_AD<5>

F17
F18

6 28 29

F19

6 28 29

F20

6 28 29

F21

6 28 29

F22

6 28 29

F23

6 28 29

F24

6 28 29

F25
F26
F27

EI_NB_TO_CPU_SR_N<0> 6 28 29
29
EI_NB_TO_CPU_SR_P<0> 6 28 29
29
I2C_SMU_A_SCL_OUT_L 6 13 18

28 6
28 6
28 6
29

EI_NB_TO_CPU_AD<37>
EI_NB_TO_CPU_SR_N<1>
EI_NB_TO_CPU_SR_P<1>

F28
F29
F30

F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
F28
F29
F30

E1 E1
E2 E2
E3 E3
E4 E4
E5 E5
E6 E6
E7 E7
E8 E8 NC
E9 E9
E10 E10
E11 E11
E12 E12
E13 E13
E14 E14
E15 E15
E16 E16
E17 E17
E18 E18
E19 E19
E20 E20
E21 E21
E22 E22
E23 E23
E24 E24
E25 E25
E26 E26
E27 E27
E28 E28
E29 E29
E30 E30

30 29 25 6

a
n
i
D1

CPU_INT_L

D2
D3

D4
D5
D6

EI_CPU_TO_NB_AD<8> 6 28 29
EI_CPU_TO_NB_AD<13> 6 28 29

D7
D8

EI_CPU_TO_NB_AD<12> 6 28 29
EI_CPU_TO_NB_AD<5> 6 28 29
EI_CPU_TO_NB_AD<36> 6 28 29
EI_CPU_TO_NB_AD<35> 6 28 29
EI_CPU_TO_NB_AD<18> 6 28 29
EI_CPU_TO_NB_AD<43> 6 28 29
EI_CPU_TO_NB_AD<42> 6 28 29
EI_CPU_TO_NB_AD<38> 6 28 29
EI_CPU_TO_NB_AD<40> 6 28 29
EI_NB_TO_CPU_AD<9> 6 28 29
EI_NB_TO_CPU_AD<11> 6 28 29
EI_NB_TO_CPU_AD<0> 6 28 29
EI_NB_TO_CPU_AD<1> 6 28 29

D9

D10
D11
D12
D13
D14
D15
D16

28 6
29

EI_CPU_TO_NB_AD<15>

D17
D18
D19
D20

m
il
EI_NB_TO_CPU_AD<22> 6 28 29
EI_NB_TO_CPU_AD<33> 6 28 29
EI_NB_TO_CPU_AD<43> 6 28 29
EI_NB_TO_CPU_AD<2> 6 28 29
29
EI_NB_TO_CPU_AD<38> 6 28 29
29
SYNCENABLE 6 29 30
TP_PROC_TRIGGER_OUT 6 29 29

EI_NB_TO_CPU_AD<8>
EI_NB_TO_CPU_AD<24>
6 EI_NB_TO_CPU_AD<7>
29
6 EI_NB_TO_CPU_AD<6>
6 EI_QACK_L

28 6
28 6
28
28

29 28

=PP1V2_EI_NB

14 18 28

D21
D22
D23
D24
D25
D26
D27
D28
D29
D30

D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30

C1 C1
C2 C2
C3 C3
C4 C4
C5 C5
C6 C6
C7 C7
C8 C8
C9 C9
C10 C10
C11 C11
C12 C12
C13 C13
C14 C14
C15 C15
C16 C16
C17 C17
C18 C18
C19 C19
C20 C20
C21 C21
C22 C22
C23 C23
C24 C24
C25 C25
C26 C26
C27 C27
C28 C28
C29 C29
C30 C30

EI_CPU_TO_NB_AD<6> 6 28 29
EI_CPU_TO_NB_AD<21> 6 28 29
EI_CPU_TO_NB_AD<20> 6 28 29
EI_CPU_TO_NB_AD<25> 6 28 29
EI_CPU_TO_NB_AD<26> 6 28 29
EI_CPU_TO_NB_SR_P<0> 6 28 29
EI_CPU_TO_NB_SR_N<0> 6 28 29
EI_CPU_TO_NB_AD<27> 6 28 29
EI_CPU_TO_NB_AD<23> 6 28 29
EI_CPU_TO_NB_AD<39> 6 28 29
EI_CPU_TO_NB_AD<16> 6 28 29
EI_CPU_TO_NB_AD<19> 6 28 29 28

29 28 6

EI_NB_TO_CPU_AD<4>
EI_NB_TO_CPU_AD<3>
EI_NB_TO_CPU_AD<16>

29 28 6

EI_NB_TO_CPU_AD<35>

6
29

29 28 6

29 28 6

29 28 6

29 28 6
29 28 6
29 28 6
29 28 6

EI_SE

6 28 29
30

29 6

18 13 6

EI_NB_TO_CPU_AD<34>
EI_NB_TO_CPU_AD<31>
EI_NB_TO_CPU_AD<32>
EI_NB_TO_CPU_AD<23>
EI_NB_TO_CPU_CLK_N
EI_NB_TO_CPU_CLK_P
MCP_L
I2C_SMU_A_SDA_OUT_L

B1
B2
B3

B4
B5
B6
B7
B8
B9

B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30

B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30

A1 A1
A2 A2
A3 A3
A4 A4
A5 A5
A6 A6
A7 A7
A8 A8
A9 A9
A10 A10
A11 A11
A12 A12
A13 A13
A14 A14
A15 A15
A16 A16
A17 A17
A18 A18
A19 A19
A20 A20
A21 A21
A22 A22
A23 A23
A24 A24
A25 A25
A26 A26
A27 A27
A28 A28
A29 A29
A30 A30

CPU_HRESET_L
CPU1_HTBEN
EI_CPU_TO_NB_AD<0>
EI_CPU_TO_NB_AD<2>
EI_CPU_TO_NB_AD<1>
EI_CPU_TO_NB_AD<9>
EI_CPU_TO_NB_AD<10>
EI_CPU_TO_NB_AD<22>
EI_CPU_TO_NB_AD<31>
EI_CPU_TO_NB_AD<37>
EI_CPU_TO_NB_AD<30>
EI_CPU_TO_NB_AD<34>
EI_CPU_TO_NB_AD<33>
EI_CPU_TO_NB_AD<32>
EI_CPU_TO_NB_AD<41>
EI_CPU_TO_NB_AD<29>

6 29 30
6 14
6 28 29
6 28 29

6 28 29
6 28 29
6 28 29
6 28 29
6 28 29
6 28 29

6 28 29
6 28 29
6 28 29
6 28 29
6 28 29
6 28 29

e
r

CPU LOGIC ANALYZER


NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6772

14

OF

04
102

FAN 0

OPTICAL TEMP SENSOR

PP12V_RUN
PP3V3_PWRON

DZ1601
SOT23

R1602
1.0K

F0_T2DRAIN 1

5%
1/8W
MF-LF
2 805

MMBZ5231B

NOSTUFF

R1605

D1601

1.5K
5%
1/4W
MF-LF
2 1206

R1604
0

20%
2 25V
CERM
603

F0_GATESLOWDN

1206A-03

FAN_0_DRV 1
3

13

FAN_RPM0

Q1601

R1601

5%
1/8W
MF-LF
805

FAN_0_CNTL

5%
1/8W
MF-LF
805

6
7
8

1
2
3

FAN_0_PWR

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

MOTOR CONTROL
TACH
GND
12V DC

20%
25V
2 CERM
603

20%
2 16V
ELEC
6.3X11-TH

SOT23

17" SYSTEM FAN 603-5518

PP3V3_RUN

20" SYSTEM FAN 603-5521

R1610
10K

C
13

FAN_TACH0

1%
1/16W
MF-LF

2 402

FAN_0_TACH

5%
1/16W
MF-LF
402

m
il

FAN 1
PP12V_RUN

1.0K

F1_T2DRAIN 1

5%
1/8W
MF-LF
2 805

MMBZ5231B

R1655
1.5K

5%
1/4W
MF-LF
2 1206

5%
1/8W
MF-LF
805

B
3

Q1652

R1653
3

Q1651

R1651
13

FAN_RPM1

2N7002

FAN_1_CNTL

SOT23-LF

5%
1/8W
MF-LF
805

PP3V3_RUN

R1659
10K

R1650
13

FAN_TACH1

1%
1/16W
MF-LF
2 402

FAN_1_TACH

5%
1/16W
MF-LF
402

5%
1/8W
MF-LF
805

2N7002

F1_DRV

SOT23-LF

NOSTUFF
1

C1651

P
0.1UF

20%
2 25V
CERM
603

1.5K

C1652

R1621
0

TEMP_SENSOR_OS 1

2 SYS_OVERTEMP_L

13 25 27

5%
1/16W
MF-LF
402

SCL
GND

R1661
0

1
2
PP12V_RUN_FAN_1_LC
VOLTAGE=12V
5%
MIN_LINE_WIDTH=0.5MM
1/10W
MIN_NECK_WIDTH=0.25MM

5%
1/10W
MF-LF
603

MF-LF
603

C1660
0.01UF

20%
16V
2 CERM
402

0.1UF

5%
1/8W
MF-LF
805 2

SOT23

e
r
0

MMBD914XXG
1

NOSTUFF

R16571

20%
25V
2 CERM
603

NOSTUFF

R1654

FAN_1_DRV

NOSTUFF

D1651

R1660

R1656

F1_VOLTAGE8R5

1.8K 2
5%
1/8W
MF-LF
805

F1_GATESLOWDN

1206A-03

NTHS5443T1

Q1653

C1654

10%
16V
2 X7R
805

F1_RCFEEDBK

R1658
1

5%
1/8W
MF-LF
805

FAN_1_PWR

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

C1653

D1652
MMBD914XXG100UF

SOT23

20%
2 16V
ELEC
6.3X5.8

CRITICAL

0.47UF

J1601

10-89-7062

6
7
8

R1652

1
2
3

DZ1651
SOT23

y
r
OS

a
n
i

1
C1603
D1602
MMBD914XXG120UF

R1609
0

NOSTUFF

M-ST-TH

5%
1/8W
MF-LF
805

C1601

J1600

R1608

F0_RCFEEDBK

SOT23-LF

18

I2C_OPTICAL_SCL

HF28040-B

0.1UF

SOT23-LF

NOSTUFF

2N7002

2N7002

F0_DRV

CRITICAL

10%
2 16V
X7R
805

Q1602

D
1

I2C_OPTICAL_SDA

C1604
0.47UF

R1603

SDA

18

NTHS5443T1

Q1603

CRITICAL

1.8K 2
5%
1/8W
MF-LF
805

5%
1/8W
MF-LF
805

LM75

A0
A1
A2

R1606
F0_VOLTAGE8R5

U1602
SOP

I2C ADDR:90(1001000)

0.1UF

5%
1/8W
MF-LF
805 2

NOSTUFF

VS+

C1602

1.5K

SOT23

8 NOSTUFF

NOSTUFF

R16071

MMBD914XXG

M-ST-TH

R1662
1

5%
1/10W
MF-LF
603

MOTOR CONTROL
FAN_1_PWR_FILT

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

TACH

5%
1/10W
MF-LF
603

PP12V_RUN_FAN_1_LCL
VOLTAGE=12V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
GND

R1663
1

FAN_1_TACH_FILT

R1664
1

5%
1/10W
MF-LF
603

FAN_1_GND_FILT
VOLTAGE=0V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

17" CPU FAN 603-5519


20" HD FAN 603-5487

FAN 0, 1 & SYSTEM TEMP

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT

NONE

REV.

051-6772 04
16 102
OF

FAN 2
PP12V_RUN

D
DZ1701
SOT23

R1702
1.0K

F2_T2DRAIN

5%
1/8W
MF-LF
2 805

R1705
1.5K

5%
1/4W
MF-LF
2 1206

MMBZ5231B

F2_VOLTAGE8R5

1.8K 2
1

13

FAN_RPM2

Q1701

R1701

2N7002

FAN_2_CNTL

SOT23-LF

5%
1/8W
MF-LF
805

5%
1/8W
MF-LF
805

Q1702

C1704

C1701

a
n
i
1
2
3

5%
1/8W
MF-LF
805

0.1UF

20%
2 25V
CERM
603

PP3V3_RUN

J1700

10-89-7062
M-ST-TH

MOTOR CONTROL

FAN_2_PWR

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

y
r
CRITICAL

NOSTUFF
1

NTHS5443T1

R1708

F2_RCFEEDBK

SOT23-LF

1206A-03

Q1703
10%
16V
2 X7R
805

2N7002

F2_DRV

20%
2 25V
CERM
603

F2_GATESLOWDN

0.47UF

FAN_2_DRV 1

C1702
0.1UF

5%
1/8W
MF-LF
805 2

SOT23

5%
1/8W
MF-LF
805

3
D

1.5K

R1706

5%
1/8W
MF-LF
805

R1703

NOSTUFF

R17071

NOSTUFF

R1704
0

D1701
MMBD914XXG

6
7
8

NOSTUFF

TACH

1
C1703
D1702
MMBD914XXG120UF
SOT23

20%
2 16V
ELEC
6.3X11-TH

+12V DC

4
6

GND

17" HD FAN 603-5520


20" CPU FAN 603-5459

R1709
10K

13

FAN_TACH2

R1700
0
1

1%
1/16W
MF-LF
2 402

FAN_2_TACH

m
il

5%
1/16W
MF-LF
402

REMOTE HARD DRIVE TEMP SENSOR

e
r

18 6

18 6

I2C_HD_TEMP_SDA
I2C_HD_TEMP_SCL

CRITICAL

J1701

53261-0498

PP3V3_PWRON

M-RT-SM
5

1
2
3
4

I2C ADDR:92(1001001)
6

518S0193

FAN 2 & HD TEMP


A

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6772

17

OF

04
102

7
11 6

PP3V3_PWRON

PP5V_U1800

603

R1833

PP5V_RUN

1
50 34 22 11 10 7 6

=PP1V2_EI_NB

C1800

PP3V3_PWRON

58 27 18 11 6

NOSTUFF

R18091

0.1UF
NOSTUFF

NOSTUFF

R1830

D
13

14 13 6

13

14 13 6

R1831

2.0K

SMU
MASTER
U1300
I2C_SMU_A_SDA_IN
MAKE_BASE=TRUE
I2C_SMU_A_SDA_OUT_L
MAKE_BASE=TRUE
I2C_SMU_A_SCL_IN
MAKE_BASE=TRUE
I2C_SMU_A_SCL_OUT_L
MAKE_BASE=TRUE
PINS 36-39

R1800

2.0K

5%
1/16W
MF-LF
402 2

7 14 28

603

PP3V3_RUN

I2C B BUS

MIN_LINE_WIDTH=12MIL
MIN_NECK_WIDTH=8MIL

NOSTUFF

11 10 7 6

2.0K

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
402 2

R1801

20%
10V
CERM 2
402

R1828

4.7K

1
C1802 R1808
200

0.1UF

4.7K

5%
1/16W
MF-LF
402 2

2.0K

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
402 2

20%
10V
2 CERM
402

5%
1/16W
MF-LF
2 402

R18031

R1810
SMU

5%
1/16W
MF-LF
2 402

MASTER
U1300

SOI
14

NET_SPACING_TYPE=I2C

13

V+

U3LITE

U1800
GND

NET_SPACING_TYPE=I2C

2N7002DW

I2C_NB_A_SDA
I2C_NB_A_SCL

SOT-363

PINS A20, B20


6

V+

U1800
GND

3
7

2N7002DW

5
58 27 18 11 6

2.0K

5%
1/16W
MF-LF
402 2

SMU

13

13

SOT-363

S
4

5%
1/16W
MF-LF
2 402

LM339A

R1816

10

SOI

200

V+

5%
1/16W
MF-LF
402 2

U1800
GND

11

I2C

6
5

I2C

SMU_CPU_JTAG_OR_I2C
I2C_CPU_A_SCL
I2C_CPU_A_SDA_TO_SMU
I2C_CPU_A_SDA_TO_CPU

NET_SPACING_TYPE=I2C

LM339A

SOI

U1800
GND

NET_SPACING_TYPE=I2C

m
il

12

SOT-363

Q1801

2N7002DW

NET_SPACING_TYPE=I2C

I2C_CPU_SCL_LS

CPU JTAG
8

PP2V5_PWRON

JTAG_CPU_TDO
JTAG_CPU_TDI
JTAG_CPU_TMS
JTAG_CPU_TCK

5%
1/16W
MF-LF
402 2

29 30
29 30

e
r
PP2V5_PWRON

MASTER
U3
I2C_NB_C_SDA
MAKE_BASE=TRUE

NET_SPACING_TYPE=I2C
NET_SPACING_TYPE=I2C

I2C_NB_C_SCL
MAKE_BASE=TRUE
PINS C21, E21

R18121
2.0K

24

U3LITE B
U3

24

I2C_NB_B_SDA
I2C_NB_B_SCL

24

24

DIMMS

ALIAS
ALIAS

I2C_DIMM_SDA
I2C_DIMM_SCL
PINS 91, 92
OF EACH DIMM

40
40

5%
1/16W
MF-LF
402 2

CPU

R1813

R18071

2.0K

5%
1/16W
MF-LF
2 402

NOSTUFF

R18221
0

5%
1/16W
MF-LF
402 2

13

I2C_SMU_E_SDA

2.0K

5%
1/16W
MF-LF
402 2

I2C_SMU_E_SCL

PINS 50, 51

5%
1/16W
MF-LF
2 402

RTC

U1301

I2C_RTC_SDA
I2C_RTC_SCL

27

I2C_CLOCK_SDA
I2C_CLOCK_SCL

ALIAS
ALIAS

PINS C1, B1

U1602
16
16

I2C_OPTICAL_SDA
I2C_OPTICAL_SCL

ALIAS
ALIAS

PINS 1, 2

I2C ADDR:90

29

AMBIENT LIGHT SENSOR


J2100
21
21

I2C_ALS_SDA
I2C_ALS_SCL

ALIAS
ALIAS

PINS 2, 3

I2C ADDR:94??
J2100 CAN BE USED AS A SECOND TEMP SENSOR

HD TEMP SENSOR
U1702
17 6
17 6

I2C_HD_TEMP_SDA
I2C_HD_TEMP_SCL

ALIAS
ALIAS

GPU TEMP SENSOR

PP3V3_RUN

U5890
58

R18151

SHASTA

1K

MASTER
U2300

5%
1/16W
MF-LF
402 2

R1814
1K

58

I2C_GPU_DIODE_SDA
I2C_GPU_DIODE_SCL

ALIAS
ALIAS

PINS 7, 8

5%
1/16W
MF-LF
2 402

I2C ADDR:98

NET_SPACING_TYPE=I2C

I2C_SB_SDA
MAKE_BASE=TRUE
I2C_SB_SCL
MAKE_BASE=TRUE
PINS Y9, AB7

25 6

NET_SPACING_TYPE=I2C

25 6

13
13

AUDIO

PINS 5, 6

U9500 / AU300

NOSTUFF

95
95

I2C_AUDIO_SDA
I2C_AUDIO_SCL

ALIAS
ALIAS

PINS 18, 19

NOSTUFF

R1826

5%
1/16W
MF-LF
402

SMU NEW E

5%
1/16W
MF-LF
402

I2C CONNECTIONS

MASTER
U1300

NOSTUFF

I2C

27

OPTICAL TEMP SENSOR

29

I2C SB BUS

2.0K

I2C
I2C

R1824

I2C

U2600

I2C ADDR:92

R1806

R1823

MASTER
U1300

13

NET_SPACING_TYPE=I2C

PINS 2, 3

5%
1/16W
MF-LF
2 402

NET_SPACING_TYPE=I2C

I2C_SMU_B_SDA
MAKE_BASE=TRUE
I2C_SMU_B_SCL
MAKE_BASE=TRUE
PINS 26, 27

PP3V3_ALL

I2C
I2C

SMU OLD E

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

PULSAR

USE 576 OHM FOR R1811 IF 5V RAIL IS USED FOR REFERENCE

PINS C20, B21

J4000 = A0
J4001 = A2

200

I2C D & E BUS

U3LITE

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
402 2

29 30

1/16W
SM-LF

2.0K

4.7K

20%
10V
CERM 2
402

29 30

I2C C BUS
2.0K

SOT-363

C1801 1 R18111
0.1UF

5%
1

I2C_0V6_REF

NOSTUFF

RP1801

R1817

13

2.0K

PINS AA20, Y21

V+

Q1801

I2C_CPU_A_SCL
I2C_CPU_A_SDA

NET_SPACING_TYPE=I2C

1/16W
SM-LF

7 14 29 30 31 35

U2900

12

5%
1

I2C

2N7002DW

R1804

5%
1/16W
MF-LF
2 402

=PP1V2_EI_CPU

RP1800

a
n
i

2.0K

R18051

R1821

R1818

0
5%
1/16W
MF-LF
402 2

NOSTUFF
1

13

I2C

PP3V3_PWRON

R18191

NOSTUFF

Q1800 R18201

12

13

24

SOI

13

24

NET_SPACING_TYPE=I2C

LM339A

y
r

Q1800

NET_SPACING_TYPE=I2C

U3

12

R1802

5%
1/16W
MF-LF
402 2

LM339A

2.0K

200

MASTER
U1300
I2C_SMU_CPU_SCL_IN
MAKE_BASE=TRUE
I2C_SMU_CPU_SCL_OUT_L
MAKE_BASE=TRUE
I2C_SMU_CPU_SDA_IN
MAKE_BASE=TRUE
I2C_SMU_CPU_SDA_OUT_L
MAKE_BASE=TRUE
PINS 14,25,23,68

R1832

PP5V_PWRON

I2C A BUS

R1825
2

R1827

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

I2C
I2C

I2C_SMU_D_SDA
I2C_SMU_D_SCL

NOTICE OF PROPRIETARY PROPERTY


13

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

13

PINS 34, 35

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6772

18

OF

04
102

TOTAL CURRENT EXCLUDING LEDS CURRENT < 170 MICRO AMPS

RGB_LED

C2105
1

R2101
1

G_PWM_IN_H

5%
1/16W
MF-LF
402

RGB_LED

RGB_LED

R21041
953K

1%
1/16W
MF-LF
402 2

12

+
-

13

2N3904LF

RGB_LED

C2106 1

R21051

0.47UF

200K

20%
10V
CERM 2
603

1%
1/16W
MF-LF
402 2

G_DRV_FB
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
RGB_LED

RGB_LED

R2112
1K

G_IN_OFFSET

R2100
25.5

a
n
i

220PF
2

1%
1/16W
MF-LF
2 402

5%
25V
CERM
402

CHANGE R2100 VALUE


TO SET LED CURRENT
MAX LED CURRENT = 0.5 / R

100% DUTY CYCLE OF 3V-PP PWM = 0.5V

y
r

RGB_LED

<-- 17 INCH

PP3V3_PWRON

PP5V_PWRON

RGB_LED

RGB_LED

C2103

20%
10V
CERM 2
402

R_DRV_K
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
RGB_LED

L2101
400-OHM-EMI

RGB_LED

R21101
953K
1%
1/16W
MF-LF
402 2

5
6

R_BASE_DRV

RGB_LED

11TSSOP

Q2108

RGB_LED

2N3904LF

C2101

SOT23

0.022UF
2

RGB_LED
1

0.47UF

20%
10V
CERM 2
603

R2111

20%
16V
CERM
402

200K
1%
1/16W
MF-LF
402 2

R_DRV_FB
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

RGB_LED

R2114
2

R_IN_OFFSET

1K

e
r
RGB_LED

R2113

1%
1/16W
MF-LF
402

25.5

PLACE THESE PARTS CLOSE TO SMU IC


PP5V_PWRON

RGB_LED

R21181
953K

1%
1/16W
MF-LF
402 2

RGB_LED

R2130
2

5%
1/16W
MF-LF
402

U2100

B_PWM_IN_H

RGB_LED

R21161
953K
1%
1/16W
MF-LF
402 2

B_PWM_DC

SYS_LED_BLUE
13
MAKE_BASE=TRUE
PWM INPUT FROM SMU

RGB_LED

+
-

LP324
1

RGB_LED

C2102
0.022UF
1

RGB_LED

C2118
0.47UF

RGB_LED

20%
10V
CERM 2
603

R21171

20%
16V
CERM
402

200K
1%
1/16W
MF-LF
402 2

B_BASE_DRV

11TSSOP

RGB_LED

R2127
B_IN_OFFSET

1K

<-- 17 INCH

1%
1/16W
MF-LF
2 402

1%
1/16W
MF-LF
402

+
-

B_DRV_K
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

518S0193

C
SYS_DRV_A
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

LP324
8

LED2101
1

U2100_UNUSED

R2120
1

220PF

C2110

PWM INPUT FROM SMU

SYS_LED_H

1K

5%
1/10W
MF-LF
2 603

SYS_GATE

RGB_LED

L2102

1K

117_INCH_LCD

4.7K

R2103

5%
1/16W
MF-LF
402 2

400-OHM-EMI

56.2
1%
1/16W
MF-LF
2 402

SYS_LED_DRV_C
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

SYS_LED_IN
3

WHITE_LED

R2107
2

WHITE_LED

Q2101

FDV301N

SM-1

SM

5%
1/16W
MF-LF
402

SYS_LED_DRV_K
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

5%
1/16W
MF-LF
402

WHITE_LED

R2129

5%
1/16W
MF-LF
402

7 21

R2106

R2132

SYS_LED

GND_CHASSIS_LED

R2121

WHITE_LED

NOSTUFF

13

WHITE_LED

1%
1/16W
MF-LF
402

C2111

5%
25V
2 CERM
402

WHITE_LED

SOT-23

953K 1

5%
25V
CERM
402

NOSTUFF

NOSTUFF

5%
1/10W
MF-LF
WHITE_LED 603

Q2100

R2119

WHITE_LED

SM6

220PF

FDV302P

PP3V3_PWRON

PP5V_PWRON

WHITE

PLACE THESE PARTS CLOSE TO SMU IC

RGB_LED 1

C2112

m
il

R_DRV
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

LP324

+
-

5%
1/16W
MF-LF
402

U2100

R_PWM_IN_H

RGB_LED

R_PWM_DC

R2115
SYS_LED_RED
MAKE_BASE=TRUE
PWM INPUT FROM SMU

SM-1

1%
1/16W
MF-LF
402 2

953K
RGB_LED

10

RGB_LED

11TSSOP

R21021

PP5V_PWRON

13

U2100

0.1UF

PLACE THESE PARTS CLOSE TO SMU IC

J2100 CAN BE USED AS A SECOND TEMP SENSOR

7 21

C2109

1%
1/16W
MF-LF
402

5MV INPUT OFFSET

GND_CHASSIS_LED

5%
25V
CERM
402

20%
16V
CERM
402

C2107
220PF

220PF

Q2102

RGB_LED
1

C2108

RGB_LED

SOT23

RGB_LED

RGB_LED

I2C_ALS_SDA
I2C_ALS_SCL

18

5%
25V
2 CERM
402

G_DRV
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

C2104

SM-1

18

0.022UF

M-RT-SM
5

PP3V3_PWRON

BLUE

RGB_LED

RGB_LED_A
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

SM-1

11TSSOP

53261-0498

GRN

400-OHM-EMI

G_BASE_DRV

LP324
14

J2100

L2104

AMB

L2100

U2100
4

G_PWM_DC

SYS_LED_GREEN
MAKE_BASE=TRUE
PWM INPUT FROM SMU

13

RGB_LED

1%
1/16W
MF-LF
402 2

CRITICAL

RGB_LED

400-OHM-EMI

953K

PP5V_PWRON

LATBG66B
AMB-GRN-BLUE
PLCC

G_DRV_K
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

R21091
RGB_LED

LED2100
7 21

5%
25V
CERM
402

PP5V_PWRON

RGB_LED

GND_CHASSIS_LED

SYS_DRV_K
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

PLACE THESE PARTS CLOSE TO SMU IC

AMBIENT LIGHT SENSOR

RGB_LED

220PF

(STUFF WHEN SYS_LED_L = ACTIVE HIGH)


(AND NO STUFF R2132, R2119 & Q2100)

B_DRV
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
3

RGB_LED

Q2114

2N3904LF

TABLE_5_HEAD

SOT23

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION

2
TABLE_5_ITEM

B_DRV_FB
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
RGB_LED

114S3921

RES, 39.2 OHM, 1%, 402

R2103

114S1821

RES, 18.2 OHM, 1%, 402

R2100,R2113,R2126

20_INCH_LCD

INDICATOR LED

TABLE_5_ITEM

20 INCH -->

NOSTUFF

R2126
25.5

NOTICE OF PROPRIETARY PROPERTY

<-- 17 INCH

1%
1/16W
MF-LF
2 402

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-6772

04
OF

21

102

8
22 7

=PPVCORE_NB
1

C2222

0.1UF

C2223

C2225

0.1UF

0.1UF

20%
2 10V
CERM
402

20%
2 10V
CERM
402

C2227

0.1UF

20%
2 10V
CERM
402

C2228

0.1UF

C2229

C2230

0.1UF

0.1UF

20%
2 10V
CERM
402

20%
2 10V
CERM
402

20%
2 10V
CERM
402

20%
2 10V
CERM
402

C2231

0.1UF

20%
2 10V
CERM
402

C2232

0.1UF

C2233

0.1UF

20%
2 10V
CERM
402

C2234

0.1UF

C2235

C2236

0.1UF

20%
2 10V
CERM
402

20%
2 10V
CERM
402

0.1UF

C2237

0.1UF

20%
2 10V
CERM
402

20%
2 10V
CERM
402

20%
2 10V
CERM
402

C2238

0.1UF

20%
2 10V
CERM
402

C2239

0.1UF

C2240

0.1UF

C2242
0.1UF

20%
2 10V
CERM
402

20%
2 10V
CERM
402

20%
2 10V
CERM
402

C2243

0.1UF

C2244
0.1UF

20%
2 10V
CERM
402

20%
2 10V
CERM
402

C2245
0.1UF

20%
2 10V
CERM
402

C2246

0.1UF

20%
2 10V
CERM
402

C2247
0.1UF

20%
2 10V
CERM
402

SOD-123

D2201
U2200_VC_R

U2200_VC

C2204

1UF

MBR0520LXXG
SOD-123

VCC

VC

U2200

C
8

U2200_COMP

FB

Q2201

U2200_GATE_H

C2214
0.1UF

20%
16V
2 CERM
603

1%
1/16W
MF-LF
2 402
R2201_P2

C2215
3900PF

20%
25V
2 CERM
805

Q2202_DRAIN

Q2202
1

C2206

NTD60N02R
CASE369

5%
25V
2 CERM
402

C2205

IS D2250 NEEDED?

51 50 7

PPVCORE_GPU

R2205
10K

0.5%
1/16W
MF-LF
2 603

C2208
1800UF

20%
2 6.3V
ELEC
TH-KZJ

C2209
1800UF

20%
2 6.3V
ELEC
TH-KZJ

K15

L17
K12

N14
N17

AC13

N23

AC16
AC22

N27
M12

AB2

M15

AB6
AB23

M20
L10

AB27

L13

AA10
AA19

L18
K2

Y12
Y15

K6
K11

Y20

GND K16
K21
K25

W4 GND
W8
W13

J9

W18
W21

J14
H10

W25

H19

V11
V16

G4
G23

V19
U9

G27
F13

U14

F16

U17
T2

F22
D2

PP3V3_RUN

6 7 10 11 18 34 50

DEVELOPMENT
1

R2260

D7
D10
D19

T12
T15
T20

D25

T23
T27

B4
B13

R10
R13

B16
B22

330
5%
1/16W
MF-LF
2 402

PP1V5_RUN_FOR_LED

GREEN
2.0X1.25A

LM339A

V+

5%
1/16W
MF-LF
402

1V1_REF

SOI

U1001
50 34 10

DEVELOPMENT

LED2200

DEVELOPMENT
3

LED_PP1V5_RUN_N

GND

PLACE LED2200 NEAR VREG


12

RDSON=0.012 OHM
@ VGS=3.5 V

U3LITE CORE POWER

20%
10V
CERM
402

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

2N7002
S

N8
N9

AE25
AC7

Q2251

N4

PBGA

(SYM 6 OF 7)

T6

R2261

2 3
1

AE4

AE10
AE19

P16
P19

U3LITE
V1.0-300MM

0.1UF

SOT23-LF

P11

U3

NOSTUFF

8
7

R18

OMIT

AG16
AG22

C2250

Q5006G

5%
1/16W
MF-LF
402

0.5%
1/16W
MF-LF
2 603

DEVELOPMENT

SMB

Q2250

5 6

2.21K

VDD

AG7

AG13

LED_PP1V5_RUN_P

10BQ040PBF

R2250
100K

R2203

NOSTUFF

D2250

IRF7413
SO-8

PP5V_PWRON

PP1V5_RUN

C2212

20%
25V
2 CERM
1206

1.5V RUN FET

=PPVCORE_NB

20%
10V
2 CERM
603

1UF

e
r

C2207
1UF

1%
1/16W
MF-LF
2 402

0.022UF

CHECK FETS

20%
2 6.3V
ELEC
TH-KZJ

NOSTUFF

U2200_FEEDBACK

1800UF

R2204_P2

10%
50V
2 CERM
603

5%
2 50V
CERM
603

22 7

C2203

m
il

S3

NOSTUFF

220PF

5%
50V
2 CERM
603

NOSTUFF
1

1.1K

D 4
1
G

68PF

20%
2 6.3V
ELEC
TH-KZJ

TH

R2204

C2213

1800UF

U2200_FEEDBACK

GND
1

C2202

L2201

NOSTUFF
6

1.6UH

27.4K

20%
2 6.3V
CERM
1206

C2217

COMP

R2201

10UF

1UF

CASE369

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

U2200_GATE_L

NTD60N02R

Q2201_GATE

5%
1/8W
MF-LF
805

SS
LD

C2210

R2202

SOI

HD

C2216

20%
25V
2 CERM
805

20%
2 6.3V
CERM
1206

U2200_VC_D

IRU3037CS
U2200_SS

10UF

1UF

20%
25V
2 CERM
805

C2201

N18

MBR0520LXXG

5%
1/8W
MF-LF
2 805

P15
N13

D2202

4.7

a
n
i
=PPVCORE_NB

R17
P12

R2200

R14

T11
T16

MBR0520LXXG
SOD-123

U18

D2200

U10
U13

VOLTAGE=1.5V
MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL
MAKE_BASE=TRUE

V15

PPVCORE_NB

PP5V_PWRON

W17
V12

PP5V_PWRON
PP5V_PWRON

W14

y
r

7.73A OF PEAK CURRENT DRAW ON PCORE_NB

L14

NOTE:
SET OUTPUT=1.5VDC FOR U3LITE CORE
IRU3037CS VREF=1.25VDC
VOUT=VREF*(R2203+R2205)/R2205=1.53VDC

M11
M16

SYS_SLEEP

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

6 8 9 10 11 46

II NOT TO REPRODUCE OR COPY IT


2
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6772

22

OF

04
102

Page Notes

Power aliases required by this page:


- _PPPCI64_PWRON_SB (to 5V or 3.3V)
- _PPPCI32_PWRON_SB (to 5V or 3.3V)
- _PP3V3_PWRON_SB
- _PP2V5_PWRON_SB
- _PPVCORE_PWRON_SB (1.2V)
NOTE: PCI pads use the VIO supply to meet
different drive timing
characteristics required by the PCI
spec for 5V vs. 3.3V operation.
Connect _PPPCI32_PWRON_SB to
appropriate PCI bus voltage and
_PPPCI64_PWRON_SB to same if 64-bit
PCI, otherwise 3.3V.

y
r

Signal aliases required by this page:


(NONE)
BOM options provided by this page:
(NONE)

Power Sequencing:
Must power Shasta VCore rail before any
other Shasta supplies.

=PP2V5_PWRON_SB
7 6 3

a
n
i

=PPVCORE_PWRON_SB

C2350

20%
2 10V
CERM
402

20%
2 10V
CERM
402

20%
2 10V
CERM
402

0.1uF

20%
2 10V
CERM
402

VDDC
AA1
AA2

0.1uF

20%
2 10V
CERM
402

C2306

0.1uF

20%
2 10V
CERM
402

C2307

0.1uF

20%
2 10V
CERM
402

C2308

0.1uF

20%
2 10V
CERM
402

C2309
0.1uF

20%
2 10V
CERM
402

B2
B5

C2310
0.1uF

20%
2 10V
CERM
402

C2311
0.1uF

20%
2 10V
CERM
402

C2312
0.1uF

20%
2 10V
CERM
402

C2313
0.1uF

20%
2 10V
CERM
402

C2314
0.1uF

20%
2 10V
CERM
402

F4
F8

POWER

L21

OMIT

VIO2

H1
L7
M1

0.1uF

20%
2 10V
CERM
402

C2335

20%
2 10V
CERM
402

C2336

P
0.1uF

20%
2 10V
CERM
402

0.1uF

20%
2 10V
CERM
402

0.1uF

20%
10V
2 CERM
402

C2332
0.1uF

20%
2 10V
CERM
402

C2337
0.1uF

20%
2 10V
CERM
402

0.1uF

20%
10V
2 CERM
402

C2333
0.1uF

20%
2 10V
CERM
402

C2338

C2329

0.1uF

20%
2 10V
CERM
402

0.1uF

C2334
0.1uF

20%
2 10V
CERM
402

(1175
( 760
( 250
( 60
( 770

Total:

A5
AA10

20%
10V
2 CERM
402

mA
mA
mA
mA
mA

mW)
mW)
mW)
mW)
mW)

A22

e
r

C2331
0.1uF

C2328

20%
10V
2 CERM
402

A1
A2

950
600
100
20
220

0.1uF

20%
2 10V
CERM
402

0.1uF

20%
2 10V
CERM
402

0.1uF

=PPPCI32_PWRON_SB

C2360
0.1uF

20%
10V
2 CERM
402

C2361
0.1uF

20%
10V
2 CERM
402

C2362
0.1uF

For PCI_AD<31..0>

W5
W19

=PP2V5_PWRON_SB

T12
R19

AB22

20%
10V
2 CERM
402

AA6
AB1

C2357

20%
2 10V
CERM
402

U13
U10

7 23 25 74 88

C2365
0.1uF

20%
10V
2 CERM
402

P9
P4
GND P14
P13

C19
D2 GND
E22
F3
F7

P12
P10

H2

N9

H9
J10

N22
N13

J11
J13

N12
N11

J14

C2339

C2356

U22

3015 mW

N10

J16

M2

GND

M11
M12

C2330

0.1uF

20%
10V
2 CERM
402

0.1uF

M10

C2327

20%
10V
2 CERM
402

C2324

1.2V
1.2V
2.5V
2.5V
3.3V

L16
L9

0.1uF

L14

0.1uF

20%
10V
2 CERM
402

C2326

20%
10V
2 CERM
402

C2323

DIGITAL
ANALOG12
VDDPs
I/O 2.5
I/O 3.3

L12
L13

0.1uF

V7
W4

L11

C2325

20%
10V
2 CERM
402

C2322

Shasta max (est 06/30/03) current:

K9
L10

0.1uF

For PCI_AD<63..32>

U9

K13
K7

20%
10V
2 CERM
402

C2321

20%
2 10V
CERM
402

VDDP_KL V8

K12

0.1uF

C2355

W22
Y19

K10
K11

C2320

0.1uF

J22

H17
K21

m
il

=PP3V3_PWRON_SB

0.1uF

H18

VIO1

R2
U12

74 25 7

C2351

20%
10V
2 CERM
402

=PPPCI64_PWRON_SB

V1.0
BGA
(1 OF 8)

B1

D1
1

SHASTA

AB2
AB6

VDDO33

C2305

D19
VDDO25 G15

U2300

AA3
AB10
1

T10
T15

0.1uF

C2304

R9

R10
R12

0.1uF

C2303

P15

M15
N8

0.1uF

C2302

20%
10V
2 CERM
402

M13
M14

20%
2 10V
CERM
402

L8

0.1uF

C2301

K8
L15

J12
J15

C2300

H8

H15

0.1uF

7 23 25 74 88

Master: Link

Shasta Core Power

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6772
OF

23
1

04

102

y
r

=PP1V2_HT

60 7

PP3V3_PWRON

PP2V5_PWRON

R2400
100

U3LITE REQUIRES ALL JTAG SIGNALS


HIGH FOR NORMAL OPERATION

1%
1/16W
MF-LF
2 402

NOSTUFF
1

C2401

5%
25V
2 CERM
603

R2424 R2426 R2429 R2431 R2433 R2436


10K

10K

10K

10K

10K

10K

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

R2403
100

1%
1/16W
MF-LF
2 402

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

C2400 R2402 R2401


0.1UF
1

20%
2 10V
CERM
402

121

121

1%
1/16W
MF-LF
2 402

1%
1/16W
MF-LF
2 402

a
n
i
28 25 13

U3LITE
V1.0-300MM
PBGA
(SYM 7 OF 7)

27

JTAG_NB_TCK
JTAG_NB_TDI
JTAG_NB_TDO
JTAG_NB_TMS
JTAG_NB_TRST_L

P4 VSP_CLKP
R4 VSP_CLKN

VSP_NB_CLK_P
VSP_NB_CLK_N

AC2 CE1_RI
AH3 CEO_TEST
AD5 CE0_MC
AD3 CE0_RE

NB_TEST_PD
NB_MC_PD
NB_RE_PD
1

R2444 R2443 R2442


10K

10K

10K

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

13 8

SYS_COLD_RESET_L

5%
1/16W
MF-LF
2 402

6 NOSTUFF

3 NOSTUFF

NB_COLD_RESET_L

Q2412
2N7002DW
SOT-363

SOT-363

P
G

R2406
1

5%
1/16W
MF-LF
402

Q2412
2N7002DW

E20
D20
D21

API0_ISCL A20
API_ISCA B20
SYS_ISCL0 C20
SYS_ISCA0 B21
SYS_ISCL1 C21
SYS_ISCA1 E21
DUMMY_A AC28
DUMMY_B AB28

NB_WARM_RESET_L
NB_COLD_RESET_L
NB_SUSPEND_ACK_L
NB_SUSPEND_REQ_L
I2C_NB_A_SCL
I2C_NB_A_SDA
I2C_NB_B_SCL
I2C_NB_B_SDA
I2C_NB_C_SCL
I2C_NB_C_SDA
TP_DUMMY_A
TP_DUMMY_B
NB_INT_L

m
il
NB_PMR_OBSV
NB_THMI
NB_THMO

SMU_SUSPENDREQ_L

24
8

24

18
18
18

330

5%
1/16W
MF-LF
2 402
PMU_SUSPEND_REQ

5%
1/16W
MF-LF
2 402

Q2404
2N7002DW

24

Q2404
2N7002DW

SOT-363

NB_SUSPEND_REQ_L

SOT-363

NOSTUFF

R2408
1

5%
1/16W
MF-LF
402

18
18
18

6
6

25

8
8

e
r

4.7K

5%
1/16W
MF-LF
2 402
NB_PU_RESET

R2435

10K

4.7K

PURESET*
SUSPENDACK*
SUSPENDREQ*

THMI J17
THMO J18

R2405 R2438

D15 PM_SLEEP0

A21

PMR_OBSV Y9

PP2V5_PWRON

NOSTUFF
1

TP_NB_PM_SLEEP0

HRESET*

IRQ0 E9

PP3V3_PWRON

NOSTUFF

OMIT

R25 CE1_LT_TCK
V25 CE1_A_TDI
AA25 CE1_B_TDO
M26 CE1_DI1_TMS
F20 CE1_DI2_TRST

JTAG_NB_TCK
JTAG_NB_TDI
JTAG_NB_TDO
JTAG_NB_TMS
JTAG_NB_TRST_L
NB_RI_PU

R2419

330

U3

27

R2420

NB_VSP_CLK_VREF
VOLTAGE=0.6V

1000PF

PP2V5_PWRON

24

MASTER: GILA
LAST MODIFIED: JUNE 10, 04

U3LITE MISC
A

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6772

24

OF

04
102

10 MIL SPACING

I2S2_DEV_TO_SB_DTI
I2S2_SB_TO_DEV_DTO
I2S2_MCLK
I2S2_BITCLK
I2S2_SYNC

10 MIL SPACING

SB_CLK18M_XTALI
SB_CLK18M_XTALO
SB_CLK18M_XTALO_R
SB_CLK25M_ATA

SPACING
SPACING
SPACING
SPACING

6 25 94
30 29 25

6 25 94

25 102
25 102

25 102

25

25
88 74 23 7

25 27

3.3

2
1

SOT23

MPIC_SB

10K

10K

5%
1/16W
MF-LF
402

R2557

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

10K

94 25 6

102
102
102

25

PCI_SLOTA_INT_L

PCI_SLOTD_INT_L

25

25 56

6 25 76

25

10K

5%
1/16W
MF-LF
402

PCI_SLOTE_INT_L

25

PCI_SLOTG_INT_L

25 77

4
3

RP2530

2
1

PCI_64BIT

R25011
1K

5%
1/16W
MF-LF
402 2

33
5%
1/16W
SM-LF

7
8

(I2S2_RESET_L)

on right

25

94 25 6

18 6
18 6

77 74 8
13

28 24 13
13

77 13

8
8
8
8
8

R2580

4.7K

5%
1/16W
MF-LF
402 2

25
25

27 25

AA5 I2S2DTI_H
Y8 I2S2DTO_H
Y7 I2S2MCLK_H

AB4 I2S2BITCLK_H
W9 I2S2SYNC_H
Y2 GPIO_H_1

SB_INT_L
MODEM_RING2SYS_L
SB_PCI_SEL32BIT

AB3 GPIO_H_2
W8 GPIO_H_3
W6 PCI_SEL32BIT_H

I2C_SB_SCL
I2C_SB_SDA

Y9 I2CCLK_H
AB7 I2CDATA_H

SYS_WARM_RESET_L
SB_STOPXTALS_L
SMU_SUSPENDREQ_L
SB_SUSPENDACK_L
SYS_PME_L
TP_SB_WATCHDOG
JTAG_SB_TDI
JTAG_SB_TDO
JTAG_SB_TCK
JTAG_SB_TMS
JTAG_SB_TRST_L

SB_TEST_MODE_PD
TP_SB_PLLTEST
TP_SB_FSTEST
SB_CLK18M_XTALI
SB_CLK18M_XTALO_R
SB_CLK25M_ATA

R2590

E9
W10

RESET_L

U11

STOPXTALS_L
SUSPENDREQ_L

V11
W18

SUSPENDACK_L

V12

PCI1PME_L
INTRWD_H

AA11 TDI
W11 TDO
AB11 TCK

Y11 TMS
W12 TRST_L
A3 TEST_MODE_H
U14 PLLTEST
V14 FSTEST
W13 XTAL_18_I
V13 XTAL_18_O
U15 XTALI
NC V15 XTALO

200
1%
1/16W
MF-LF
2 402

Y2590

SB_CLK18M_XTALO

18.432M
1

22pF

5%
50V
CERM 2
402

W17

Y12

AA13

I2S0

V5 GPIO_H_0

(I2S2_DEV_TO_SB_DTI)
I2S2_SB_TO_DEV_DTO_R
I2S2_MCLK_R
I2S2_BITCLK_R
I2S2_SYNC_R

I2S1

V10 I2S1DTI_H
AB5 I2S1DTO_H
V9 I2S1MCLK_H
AA8 I2S1BITCLK_H
AA7 I2S1SYNC_H

(SCCA)

(I2S1_RESET_L)

=PP3V3_PWRON_SB

C2590 1

5%
1/16W
MF-LF
402

(I2S1_DEV_TO_SB_DTI)
I2S1_SB_TO_DEV_DTO_R
I2S1_MCLK_R
I2S1_BITCLK_R
I2S1_SYNC_R

33
5%
1/16W
SM-LF

I2S2_DEV_TO_SB_DTI
25 I2S2_SB_TO_DEV_DTO
25 I2S2_MCLK
25 I2S2_BITCLK
25 I2S2_SYNC
102 I2S2_RESET_L
AUDIO GPIO - see note

U8 I2S0MCLK_H
AA4 I2S0BITCLK_H
Y6 I2S0SYNC_H

m
il
7

RP2520

102 25
102

I2S2

94 25 6

BGA
(2 OF 8)

W7 I2S0DTI_H
Y5 I2S0DTO_H

(SCCB)

94 25 6

5%
1/16W
MF-LF
402 2

25

R2558

R2559
1

10K

PCI_SLOTF_REQ_L

PCI_SLOTF_GNT_L

R2556

10K

PCI_SLOTE_REQ_L

PCI_SLOTE_GNT_L

5%
1/16W
MF-LF
402

94 25 6

1 = 32-bit PCI & GPIOs


0 = 64-bit PCI & XGC

R2552

R2553
1

10K

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

94 25 6

I2S1_DEV_TO_SB_DTI
I2S1_SB_TO_DEV_DTO
I2S1_MCLK
I2S1_BITCLK
I2S1_SYNC
I2S1_RESET_L

PCI 32-bit select

R2551
1

94 25 6

(I2S0_DEV_TO_SB_DTI)
I2S0_SB_TO_DEV_DTO_R
I2S0_MCLK_R
I2S0_BITCLK_R
I2S0_SYNC_R

5
33
5%
1/16W
SM-LF

10K

7 74 75 76 77

UDASH_RESET_L

33 27 25 13

SYS_SLEWING_L

R2555
1

20%
6.3V 2
CERM
1206

7 23 25 74

C2540
0.1uF

20%
10V
2 CERM
402

25

25 12

86 25

25

11.4X4.7X4.2-SM
1

C2591
22pF

5%
2 50V
CERM
402

XTAL_18
GND

PLL_45
GND

6
7

PCI1REQ_3_L

8
9

PCI1REQ_4_L

PCI1GNT_3_L

PCI1GNT_4_L

"Slot E" - AD21


PCI_SLOTE_REQ_L
AA19 PCI_SLOTE_GNT_L
"Slot F" - AD22
AB21 PCI_SLOTF_REQ_L
AA20 PCI_SLOTF_GNT_L
U17

U16

10
11

PCI1REQ_5_L
PCI1GNT_5_L

12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43

PCI1AD_32_H D18
PCI1AD_33_H A20
PCI1AD_34_H F18

Y20

PCI1AD_35_H F17
PCI1AD_36_H G16
PCI1AD_37_H F16
PCI1AD_38_H A21
PCI1AD_39_H B21
PCI1AD_40_H C20
PCI1AD_41_H G17
PCI1AD_42_H G18
PCI1AD_43_H E19
PCI1AD_44_H F19
PCI1AD_45_H D20
PCI1AD_46_H E20
PCI1AD_47_H C21
PCI1AD_48_H F20
PCI1AD_49_H G19
PCI1AD_50_H C22
PCI1AD_51_H D21
PCI1AD_52_H G20
PCI1AD_53_H D22
PCI1AD_54_H K18
PCI1AD_55_H H19
PCI1AD_56_H J17
PCI1AD_57_H F21
PCI1AD_58_H G21
PCI1AD_59_H H20
PCI1AD_60_H J19
PCI1AD_61_H F22
PCI1AD_62_H G22
PCI1AD_63_H H21

J20
H22

44
45
46
47

PCI1C_BE_4_L

PCI1C_BE_7_L

K20

48
49
50

PCI1REQ64_L
PCI1ACK64_L

K17
L17

PCI1PAR64_H

E18

51
52
53
54

PCI1C_BE_5_L
PCI1C_BE_6_L

K22

XGI_CLK_H Y4
XGI_DTO0_H U7
XGI_DTO1_H T9
XGI_DTI_H W2

SB_TO_SMU_INT_L
CPU_SRESET_L

SB_GPIO12
SYS_OVERTEMP_L
UDASH_SDOWN
UDASH_RESET_L
AGP_INT_L
PCI_SLOTA_INT_L
PCI_SLOTB_INT_L
PCI_SLOTC_INT_L
PCI_SLOTD_INT_L
PCI_SLOTE_INT_L
PCI_SLOTF_INT_L
SB_GPIO23
SB_GPIO24
SB_GPIO25
SB_SATABR_RESET_L
PCI_SLOTG_INT_L
FW_LOWPWR
ENETFW_RESET
SB_GPIO30
ENET_ENERGYDET
AUDIO_LO_DET_L
AUDIO_LO_OPTICAL_PLUG_L
AUDIO_LI_DET_L
AUDIO_LI_OPTICAL_PLUG_L
AUDIO_HP_DET_L
AUDIO_SPKR_DET_L
AUDIO_LO_MUTE_L
AUDIO_HP_MUTE_L
AUDIO_SPKR_MUTE_L
AUDIO_EXT_MCLK_SEL
AUDIO_GPIO_11
AUDIO_GPIO_12

FW_LOWPWR

ENET_ENERGYDET

R2568

5%
1/16W
MF-LF
402

10K

I2S0_RESET_L
SB_GPIO45
SB_GPIO46
SB_GPIO47

74 25 23 7

25

SB_GPIO12

25

25

PCI_SLOTC_INT_L

25

25

25
25

=PP3V3_PWRON_SB

10K

RP2550
2

25

25

25

10K

RP2550

5%
1/16W
SM-LF

SB_GPIO30

10K

25

25

SB_GPIO45

25 89
25

SB_GPIO46

25

SB_GPIO47

25

SB_GPIO49

10K

12 25

25 86

10K

25

25

25 13

SB_GPIO50

10K

5%
1/16W
SM-LF

RP2553

RP2553

5%
1/16W
SM-LF

SMU_TO_SB_INT_L

10K

5%
1/16W
SM-LF

5%
1/16W
SM-LF

SB_GPIO51

SB_GPIO52

10K

RP2552

RP2553
25

5%
1/16W
SM-LF

5%
1/16W
SM-LF

10K

10K

RP2552

RP2552

25

5%
1/16W
SM-LF

5%
1/16W
SM-LF

25 77

10K

RP2551

RP2552

25

RP2551

5%
1/16W
SM-LF

25

10K

5%
1/16W
SM-LF

25
25

5%
1/16W
SM-LF

5%
1/16W
SM-LF

SB_GPIO25

10K

10K

RP2551

SB_GPIO24

25

25

RP2551

SB_GPIO23

25

95

10K

5%
1/16W
SM-LF

PCI_SLOTF_INT_L

10K

RP2553
1

10K

5%
1/16W
SM-LF

25

MASTER: SEEDY

25

SYS_SLEWING_L
SB_GPIO49
SB_GPIO50

13 25 27 33

Shasta Serial / Misc

25
25

SB_GPIO51
SB_GPIO52
NB_TO_SB_INT
SMU_TO_SB_INT_L

25

NOTICE OF PROPRIETARY PROPERTY

25

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

25
13 25

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

PLL_49
GND

II NOT TO REPRODUCE OR COPY IT


III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

REV.

051-6772
SHT
NONE

6 25 76

101

RP2550

49

102

5%
1/16W
SM-LF

PCI_SLOTB_INT_L

6 25

102

RP2550

100

R2567

SCALE

10K

10K

5%
1/16W
MF-LF
402

13 16 25 27

102

5%
1/16W
MF-LF
402

25

98

10K

5%
1/16W
MF-LF
402

R2566

ENETFW_RESET

25 29 30

102

13 25

102

R2565

25 56

102

5%
1/16W
MF-LF
402

SB_SATABR_RESET_L

25

101

10K

R2564

25

101

5%
1/16W
MF-LF
402

10K

R2561

5%
1/16W
MF-LF
402

25

6 101

R2563

I2S1_RESET_L

1K

5%
1/16W
MF-LF
402

MODEM_RING2SYS_L

REDUNDANT - NEED TO ADDRESS THIS


89 25

1K

10K

5%
1/16W
MF-LF
402

R2562

APPLE COMPUTER INC.

NO STUFF

NO STUFF

SIZE

5%
1/16W
MF-LF
402

OMIT

V1.0 GPIO

RP2510

3.3

5%
1/8W
MF-LF
805

10uF

VIO
PME

XTAL_18 PLL_45 PLL_49


VDD
VDD
VDD

SHASTA

4
3

XTAL
VDD

U2300

5%
1/16W
MF-LF
402

I2S0_DEV_TO_SB_DTI
I2S0_SB_TO_DEV_DTO
I2S0_MCLK
I2S0_BITCLK
I2S0_SYNC

R25001

From SouthBridge <SB_INT_L


25

R2550
10K

95 25

1uF

10%
6.3V
2 CERM
402

25 6

94 25 6

AA12

2N3904LF
2

5%
1/16W
MF-LF
402

=PP3V3_PCI

102 25

C2511

e
r

Q2576

R2578
47

10uF

20%
6.3V
2 CERM
1206

PCI

MPIC_SB

95 25
102 25

C2510

=PP3V3_PWRON_SB

NOSTUFF
1

GPIO

95 25

74 25 23 7

C2530

1uF

XGI

30 29 14 6

<- To CPU
CPU_INT_L

R2530

NOSTUFF

C2531

SYS_OVERTEMP_L

REDUNDANT - NEED TO ADDRESS THIS

a
n
i

1uF

10%
6.3V
2 CERM
402

I2C

To SouthBridge ->
NB_TO_SB_INT 25

MPIC_SB

5%
1/16W
MF-LF
402 2

C2501

PWR_MGT

I2S1: Soft Modem


I2S0: Audio DAC
I2S2: S/P-DIF

10K

R2576

PP2V5_PWRON_SB_XTALVDD
VOLTAGE=2.5V
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=15 mil

R2511

5%
1/16W
MF-LF
402

C2500
10uF

Re-pin within each RPAK as necessary


DO NOT swap between RPAKs

PP3V3_RUN

MPIC_NB

3.3

NorthBridge / SouthBridge MPIC Routing

R25791

y
r

20%
6.3V 2
CERM
1206

10%
6.3V 2
CERM
402

5%
1/8W
MF-LF
805

PP1V2_PWRON_SB_PLL49VDD
VOLTAGE=1.2V
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=15 mil

NOSTUFF

5%
1/8W
MF-LF
805

NB_INT_L_R

CPU_SRESET_L

94 25 6

PP2V5_PWRON_SB_XTAL18VDD
VOLTAGE=2.5V
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=15 mil

R2505

=PP2V5_PWRON_SB

BOM options provided by this page:


- PCI_64BIT
Configures Shasta for 64-bit PCI
NOTE: XGC required for Shasta GPIOs
- MPIC_NB/MPIC_SB
Selects whether NorthBridge or
SouthBridge MPIC will be used for
interrupt controller.

3.3

=PP1V2_PWRON_SB

25

R2510

10K

10uF

10%
6.3V 2
CERM
402

Signal aliases required by this page:


(NONE)

C2520

1uF

25 102

20%
6.3V
2 CERM
1206

R2575

R2520

NOSTUFF

C2521

25 102

Power aliases required by this page:


- _PP3V3_PCI
- _PP3V3_PWRON_SB
- _PP2V5_PWRON_SB
- _PP1V2_PWRON_SB

-> From NorthBridge


NB_INT_L

27 25 16 13

PP1V2_PWRON_SB_PLL45VDD
VOLTAGE=1.2V
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=15 mil

6 25 94

Page Notes

24

1K

5%
1/16W
MF-LF
402

R2560

5%
1/8W
MF-LF
805

5%
1/16W
MF-LF
2 402

6 25 94

SB_TO_SMU_INT_L

6 25 94

TEST

SB_CLK25M_ATA

MIL
MIL
MIL
MIL

25 13

25 95

XTALS

15
15
15
15

25 102

AB13

SB_CLK18M_XTAL

=PP3V3_PWRON_SB

R2554

25 102

Y13

I2S2_TO_SB
I2S2_TO_DEV
I2S2_TO_DEV
I2S2_BIDIR
I2S2_BIDIR

74 25 23 7

25 95

AUDIO GPIOS

I2S1_DEV_TO_SB_DTI
I2S1_SB_TO_DEV_DTO
I2S1_MCLK
I2S1_BITCLK
I2S1_SYNC

25 95

NOTE: It is the responsibility of


the audio circuit to provide the
necessary pull-ups & pull-downs.

I2S0_DEV_TO_SB_DTI
I2S0_SB_TO_DEV_DTO
I2S0_MCLK
I2S0_BITCLK
I2S0_SYNC

AUDIO

I2S1_TO_SB
I2S1_TO_DEV
I2S1_TO_DEV
I2S1_BIDIR
I2S1_BIDIR

DIFFERENTIAL_PAIR

W14

NET_SPACING_TYPE

I2S0_TO_SB
I2S0_TO_DEV
I2S0_TO_DEV
I2S0_BIDIR
I2S0_BIDIR

AB12

ELECTRICAL_CONSTRAINT_SET

OF

25
1

04

102

7
L2601

26 7

=PPVCORE_PWRON_PULSAR

26 7

180-OHM-1.5A
1

SYM 2 OF 2

=PPVCORE_PWRON_PULSAR

2
0603

C2645
2.2UF

20%
2 6.3V
CERM1
603

C2611
0.1UF
20%

C2609
0.1UF

20%
2 10V
CERM
402

46 40 37 26 7

2
0603

5%
1/16W
MF-LF
402
1

C2669

C2617

20%
6.3V
2 CERM1
603

C2613
0.1UF

26 7

2 10V
CERM
402

PLACE NEAR PIN D2 D1

L2605
180-OHM-1.5A
1

2
0603

R2603
4.7
1

PP1V5_PSL_PLL3

5%
1/16W
MF-LF
402

C2603
2.2UF

20%
6.3V
2 CERM1
603

C2615
0.1UF

20%
2 10V
CERM
402

L2607 PLACE

VOLTAGE=1.5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

C2601
0.1UF

20%
2 10V
CERM
402

NEAR PIN L8 K8

PP3V3_PWRON

0603

R2605
4.7
1

m
il
1

PP1V5_PSL_PLL4

5%
1/16W
MF-LF
402

C2607

20%
6.3V
2 CERM1
603

C2619
0.1UF

VOLTAGE=1.5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

C2605
0.1UF
20%

2.2UF

2 10V
CERM
402

2 10V
CERM
402

46 40 37 26 7

0.1UF
20%
402

2
0603

5%
1/16W
MF-LF
402

C2621
2.2UF

20%
2 6.3V
CERM1
603

0.1UF
20%

e
r

PP3V3_PSL_XTAL
1

C2620

C2622
0.1UF
20%

VOLTAGE=3.3V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

2 10V
CERM
402

2 10V
CERM
402

402 CAPS NOT NEEDED


IF 603 CAN BE PLACED CLOSE TO PULSAR

PART#
359S0076

QTY
1

C2639

2 10V
CERM

R2607
4.7
1

=PP2V5_PWRON_RAM

PLACE NEAR PIN M3 M2

L2609
180-OHM-1.5A
1

DESCRIPTION
PULSAR, PBGA

=PP1V2_PULSAR

26 7

=PPVCORE_PULSAR

A11 VDD_HCLK0
A9 VDD_HCLK0
A8 VDD_HCLK1
C5 VDD_HCLK2
B4 VDD_HCLK2

VSS_HCLK0 C10
VSS_HCLK0 B11

K10 VDD_HSYNC
H12 VDD_HSYNC

VSS_HSYNC H10
VSS_HSYNC K12

VSS_HCLK1 B7
VSS_HCLK2 A4
VSS_HCLK2 A7

J11 VDD15_HSYNC
M11 VDD15_PCLK
A1 VDD_VCLK
A12 VDD_XTAL

VSS_VCLK A3
VSS_XTAL C12

REFERENCE DESIGNATOR(S)

26 7

0.1UF
20%

0.1UF

20%
2 10V
CERM
402

2 10V
CERM
402

C2651 1 C2671
0.1UF

20%
2 10V
CERM
402

C2640
0.1UF
20%

2 10V
CERM

402

=PPVCORE_PULSAR

C2631 1 C2632 1 C2633 1 C2634 1 C2635 1 C2636 1 C2637 1 C2638


0.1UF

20%
2 10V
CERM
402

26 7

PP3V3_RUN

C2665 1 C2667
0.1UF
20%

20%
2 10V
CERM
402

PP3V3_PWRON

26 7

VSS33 E2
VSS33_BC L7
VSS33_BC1 M5

PINS G12, M12, H3, K1, L5, M9, A11, A9


A8, C5, B4, K10, H12 J11, M11, A1
CAN BE TURNED OFF IN SLEEP

180-OHM-1.5A
1

=PPVCORE_PULSAR

a
n
i

20%
2 10V
CERM
402

VSS25 L2
VSS25 H2

E1 VDD33
L5 VDD33_BC
M9 VDD33_BC1

0.1UF
20%

2.2UF

VSS_NBSYNC F11
VSS_PCLK L12

H3 VDD25
K1 VDD25

R2609
PP1V5_PSL_PLL2
VOLTAGE=1.5V
MIN_LINE_WIDTH=25MIL
1
MIN_NECK_WIDTH=10MIL

VSS_CML A6
VSS_I2C C2

y
r

=PP2V5_PWRON_RAM

PP3V3_PWRON
PP3V3_RUN

4.7 2

VSS_PLL4 M2

B2 VDD_I2C
G12 VDD_NBSYNC
M12 VDD_PCLK

=PP1V2_PULSAR

PLACE NEAR PIN D10 D12

180-OHM-1.5A

C4_VSS C9
VSS_PLL1 D12
VSS_PLL2 D1
VSS_PLL3 K8

M3 VDD_PLL4

26 7

FSBGA

PP3V3_PWRON

2 10V
CERM
402

L2603

PULSAR

D10 VDD_PLL1
D2 VDD_PLL2
L8 VDD_PLL3

PP1V5_PSL_PLL1
VOLTAGE=1.5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

C1_VSS G1
C2_VSS M4
C3_VSS E10

U2600

B9 C4_VDD

5%
1/16W
MF-LF
402
1

OMIT

F1 C1_VDD
L3 C2_VDD
E12 C3_VDD

R2601
4.7

0.1UF

20%
2 10V
CERM
402

0.1UF

20%
2 10V
CERM
402

0.1UF

20%
2 10V
CERM
402

0.1UF

20%
2 10V
CERM
402

0.1UF

20%
2 10V
CERM
402

0.1UF

20%
2 10V
CERM
402

0.1UF

20%
2 10V
CERM
402

=PPVCORE_PWRON_PULSAR

C2627 1 C2628 1 C2629 1 C2630


0.1UF

20%
2 10V
CERM
402

26 7

0.1UF

20%
2 10V
CERM
402

0.1UF

20%
2 10V
CERM
402

0.1UF

20%
2 10V
CERM
402

=PP1V2_PULSAR

C2623 1 C2624 1 C2625 1 C2626


0.1UF

20%
2 10V
CERM
402

0.1UF

20%
2 10V
CERM
402

0.1UF

20%
2 10V
CERM
402

0.1UF

20%
2 10V
CERM
402

MASTER: GILA
LAST MODIFIED: APR 09, 04

TABLE_5_HEAD

BOM OPTION

PULSAR POWER

TABLE_5_ITEM

U2600

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6772 04
26 102
SHT

OF

NONE

7
ELECTRICAL_CONSTRAINT_SET

29 27
29 27
14 6
14 6
28 27
28 27
29 27
28 27

14 6

27 24
27 24

48 27
49 27

EI_CPU_CLK_P
EI_CPU_CLK_N
EI_CPU1_CLK_P
EI_CPU1_CLK_N
EI_NB_CLK_P
EI_NB_CLK_N
EI_CPU_SYNC
EI_NB_SYNC
EI_CPU1_SYNC

EI_CPU_CLK
EI_CPU_CLK
EI_CPU1_CLK
EI_CPU1_CLK
EI_NB_CLK
EI_NB_CLK
EI_SYNC

NET_PHYSICAL_TYPE

NET_SPACING_TYPE

DIFFERENTIAL_PAIR

CLOCKS
CLOCKS
CLOCKS
CLOCKS
CLOCKS
CLOCKS
CLOCKS
CLOCKS
CLOCKS

EI_CPU_CLK
EI_CPU_CLK
EI_CPU1_CLK
EI_CPU1_CLK
EI_NB_CLK
EI_NB_CLK

EI_CPU1_SYNC

CLOCKS
CLOCKS
CLOCKS
CLOCKS
CLOCKS
CLOCKS
CLOCKS
CLOCKS
CLOCKS

VSP_NB_CLK_P
VSP_NB_CLK_N

VSP_NB_CLK
VSP_NB_CLK

CLOCKS
CLOCKS

CLOCKS
CLOCKS

VSP_NB_CLK
VSP_NB_CLK

AGP_CLK66M_NB
AGP_CLK66M_GPU

AGP_NB_CLK
AGP_GPU_CLK

CLOCKS
CLOCKS

CLOCKS
CLOCKS

HT_CLK66M_NB
HT_CLK66M_SB

HT_NB_CLK
HT_SB_CLK

CLOCKS
CLOCKS

CLOCKS
CLOCKS

PCI_CLK66M_SB_INT
PCI_CLK33M_SB_EXT

CLOCKS_PCI
CLOCKS_PCI

CLOCKS
CLOCKS

CLOCKS
CLOCKS

R2701
5%

I86
I87

62 27

I117

74 8

3.3V

33MHZ

3.3V

33MHZ

R2761
0

I96

I97

5% 402

PCI_CLK_GP0

PCI_CLK_GP1

I98
I99

C2708

I118

0.001UF
50V 1

2 CERM

I94

y
r
10%

I95

402

VSP_NB_CLK_P
VSP_NB_CLK_N

C2710

0.001UF

I100

50V

I101

I102

30 29 27

PLS_EXTCLK

PLS_XTAL

I103

402

0.001UF

I90

10%

I91

CPU_HTBEN

CLOCKS

CLOCKS

I119

CLOCKS

CLOCKS

I120

a
n
i

DIFFERENTIAL SIGNALS SHOULD HAVE 5 MIL SPACING TO EACH OTHER


ALL SPACING GROUPS SHOULD HAVE 15 MIL SPACING TO SIGNALS NOT IN THEIR GROUP

NET
SPACING
TYPE

SYM 1 OF 2

EI_NB_SYNC IS PART OF EI_CPU_SYNC TOPOLOGY

GPCLK33_0 L4
GPCLK33_1 K4

OMIT

U2600

PULSAR
FSBGA

13

R2704
0

CLOCK_RESET_L

18

I2C_CLOCK_SCL

C1 SCLK

18

I2C_CLOCK_SDA

B1 SDATA

PLS_RESET_L

D3

PLS_X_IN

C11 XIN

PLS_X_OUT

B12 XOUT

RESET*

5% 402

NOSTUFF
R2738
1K

0=IIC ADDR D2/D3

PLS_X_ADDRSEL

6
6
6

TP_PLS_TEST1
TP_PLS_TEST2
TP_PLS_TEST3

VCLKN A2
VCLKP B3

58 18 11 6

PP3V3_PWRON

R2722

NOSTUFF

R2748

SYS_OVERTEMP_L

25 16 13

K3 TEST1
E11 TEST2
D11 TEST3

R2742

806 1

R2750 47

R2752
J2700
F-ST-SM
3

24

NOSTUFF
1

R2724 1K

5%
1/16W
MF-LF
402

R2762

PLS_EXTCLK
NOSTUFF
1

27

5%
1/16W
MF-LF
2 402
PLS_INTERM

R2754
0
1

R2758
1

330K2
5%
1/16W
MF-LF
402

R2764

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
402

NO STUFF

24

R2756
0
1

5%
1/16W
MF-LF
402

CRITICAL

Y2701

25.0000M
1

C2707

PLS_X_OUT_B

PLS_X_IN_B

402 1%

A5 REF_CML

PLS_PRES_CML

B6 PRES_CML

F2

FORCESPO*

8X4.5MM-SM

33PF
5%

2 CERM
402

EI_CPU_CLK_P
EI_CPU_CLK_N

402 5%
402 5%

PULSAR_POWER_DOWN_R

PLS_CLK_66M_0_R
PLS_CLK_66M_1_R

HT_CLK66M_NB_R
RAM_CLK66M_NB_R

PCLK33_0 K5
PCLK33_1 L6
PCLK33_2 M7
PCLK33_3 L9

PCI_CLK66M_SB_INT_R
PCI_CLK_P1_R
AGP_CLK66M_GPU_R
PCI_CLK_P3_R
PCI_CLK_P4_R

CLOCKS

EI_CPU_SYNC_R
EI_CPU1_SYNC_R

CLOCKS
CLOCKS

SB_CLK25M_ATA_R
SATA_CLK25M_R

CLOCKS
CLOCKS

PCLK12 L11
PCLK15 L10

402

EI_NB_CLK_P
EI_NB_CLK_N

C2702

0.001UF
50V 1

2
1

2 50V
CERM
402

66MHZ
66MHZ

TP_PLS_CLK_66M_0
TP_PLS_CLK_66M_1

2.5V
2.5V

66MHZ
66MHZ

HT_CLK66M_NB
RAM_CLK66M_NB

3.3V
3.3V
3.3V
3.3V

66MHZ
33MHZ
66MHZ
33MHZ

PCI_CLK66M_SB_INT
PCI_CLK_P1
AGP_CLK66M_GPU
PCI_CLK_P3
PCI_CLK_P4

1.2V

33MHZ

CPU_HTBEN

27 29 30

1.2V

EI_NB_SYNC

27 28

1.2V

EI_CPU_SYNC

27 29

0 R2705
2

5% 402

0 R2707

5% 402

5% 402

2.5V
2.5V
20 R2703
1

0 R2711
1

5% 402

0 R2702
1

5% 402

0 R2779
1

5% 402

6
6

27 60
37

27 74
8
27 49
8
8

5% 402

14

0 R2768
1
1

5% 402

5% 402

14

20 R2770
NOSTUFF
22 R2700
1

0 R2720
CLOCKS

27 28

402

NOSTUFF
0 R2776
5% 402

27 28

2 CERM

0 R2772

SYS_SLEWING_L

5% 402

2.5V
2.5V

25MHZ
25MHZ

SB_CLK25M_ATA
TP_SATA_CLK25M

1.2V
1.5V

66MHZ
66MHZ

HT_CLK66M_SB
AGP_CLK66M_NB

25
6

5% 402
13 25 33

5% 402

HT_CLK66M_SB_R
AGP_CLK66M_NB_R

2 CERM

0 R2715

EI_NB_SYNC_R

SLEWING_L_R
CLOCK_ERROR_L

10%

5% 402

CLOCKS
CLOCKS

C2700

20 R2709

27 29

2 CERM

0.001UF

50V 1

5% 402

27 29

402

NOSTUFF 10%
0 R2775

CLOCKS
CLOCKS
CLOCKS
CLOCKS
CLOCKS

NBSYNC F12

K9
M8

10%

14

CLOCKS
CLOCKS

CPU_HTBEN_R
CPU1_HTBEN_R

REFCLK_0 G2
REFCLK_1 H1

50V 1

14

CLOCKS
CLOCKS

HTBEN_0 K11
HTBEN_1 J12

HSYNC_0 J10
HSYNC_1 H11

0.001UF

0 R2717

CLOCKS
CLOCKS

5% 402

0 R2719
1

27 62
27 48

5% 402

MASTER: SEEDY
LAST MODIFIED: NOV 22, 04

PULSAR CLOCKS

C2705
33PF
5%

50V
CERM 2
402

NOSTUFF

CLOCKS
CLOCKS
CLOCKS
CLOCKS
CLOCKS
CLOCKS

PCLK25_0 K2
PCLK25_1 L1

SLEWING*
ERROR*

C3 PD

NO STUFF

U.FL-R_SMT

G11 REF15
J2 REF25
M6 REF33

TP_PLS_REF_CML

PLS_FORCE_P0_L_R

=PULSAR_POWER_DOWN

NOSTUFF

M1 SCAN_MODE

e
r
6

5%
1/16W
MF-LF
402

PLS_REF15
PLS_REF25
PLS_REF33

1K

5%
1/16W
MF-LF
2 402

PLS_SCAN_MODE

1%

402 1%
402 1%
402
1%
2

R2744 681 1
R2740 1K 1
R2746 1K 1

402

CLOCKS
CLOCKS

EI_CPU_CLK_N_C
EI_CPU1_CLK_N_R
EI_NB_CLK_N_C
EI_CPU_CLK_P_C
EI_CPU1_CLK_P_R
EI_NB_CLK_P_C

HCLKP_0 A10
HCLKP_1 B8
HCLKP_2 B5
GPCLK25_0 J3
GPCLK25_1 J1

CLOCKS
CLOCKS

VSP_NB_CLK_N_C
VSP_NB_CLK_P_C

HCLKN_0 B10
HCLKN_1 C8
HCLKN_2 C4

PCLK33_4 M10

R2706 249

PCI_CLK_GP0_R
PCI_CLK_GP1_R

m
il

E3 ADDRSEL

5% 402

1=IIC ADDR D4/D5

24 27

2 CERM

C2715

27

24 27

C2713

50V

74 27

I116

10%

60 27

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6772

27

OF

04
102

=PP1V2_EI_NB

ELECTRICAL_CONSTRAINT_SET
29 28 14 6

C2800
0.1UF

20%
10V
2 CERM
402

C2801
0.1UF

20%
10V
2 CERM
402

C2802
0.1UF

C2803
0.1UF

20%
10V
2 CERM
402

C2804

0.1UF

C2805
0.1UF

20%
10V
2 CERM
402

20%
10V
2 CERM
402

C2806

0.1UF

C2808

0.1UF

20%
10V
2 CERM
402

20%
10V
2 CERM
402

C2807

0.1UF

C2809
0.1UF

20%
10V
2 CERM
402

20%
10V
2 CERM
402

20%
10V
2 CERM
402

C2810
0.1UF

20%
10V
2 CERM
402

C2811

0.1UF

C2812
0.1UF

20%
10V
2 CERM
402

20%
10V
2 CERM
402

C2813
0.1UF

20%
10V
2 CERM
402

C2814
0.1UF

20%
10V
2 CERM
402

C2815
0.1UF

20%
10V
2 CERM
402

C2816

0.1UF

20%
10V
2 CERM
402

C2817

29 28 14 6

0.1UF

29 28 14 6

20%
10V
2 CERM
402

29 28 14 6

29 28 14 6
29 28 14 6

29 28 14 6
29 28 14 6

=PP1V5_PWRON_NB_AVDD

R2800
PP1V5_PWRON_EI_NB_AVDD

VOLTAGE=1.5V

5%
1/10W
MF-LF
603

29 28 14 6

C2818

C2819

=PP1V2_EI_NB

29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6

29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6

29 28 14 6
29 28 14 6
29 28 14 6
29 28 14 6

29 28 14 6
29 28 14 6
29 28 14 6

PLACE R2805 AND R2806


NEAR U3LITE

29 28 14 6

29 14 6

F15 API0_BCLKIP
E15 API0_BCLKIN

EI_NB_TO_CPU_CLK_P
EI_NB_TO_CPU_CLK_N

APPLE PI
INTERFACE

B10
B19

D13

D16
B7

API0_BCLKOP D6
API0_BCLKON E6
API0_ADO0 J2
API0_ADO1 H1
API0_ADO2 J1
API0_ADO3 K1
API0_ADO4 E1
API0_ADO5 F2
API0_ADO6 J4
API0_ADO7 H4
API0_ADO8 G1
API0_ADO9 H2
API0_ADO10 F1

E11 API0_ADI11
A10 API0_ADI12
A9 API0_ADI13
A8 API0_ADI14
B9 API0_ADI15

API0_ADO11 H5
API0_ADO12 H3

C11 API0_ADI16
B11 API0_ADI17
A11 API0_ADI18

API0_ADO16 E3
API0_ADO17 F4
API0_ADO18 E2

A12 API0_ADI19
B12 API0_ADI20
C12 API0_ADI21

API0_ADO19 F5
API0_ADO20 H6
API0_ADO21 J7

D12 API0_ADI22
E12 API0_ADI23
A13 API0_ADI24
A14 API0_ADI25
B14 API0_ADI26

API0_ADO22 F3
API0_ADO23 J8

C14 API0_ADI27
A16 API0_ADI28
A15 API0_ADI29

API0_ADO27 E4
API0_ADO28 D8
API0_ADO29 A5

B15 API0_ADI30
C15 API0_ADI31
H15 API0_ADI32

API0_ADO30 C2
API0_ADO31 C3
API0_ADO32 C5

G15 API0_ADI33
F17 API0_ADI34
G17 API0_ADI35
G18 API0_ADI36
H18 API0_ADI37

API0_ADO33 C6
API0_ADO34 B2

F18 API0_ADI38
E18 API0_ADI39
A17 API0_ADI40

API0_ADO38 A6
API0_ADO39 C8
API0_ADO40 A2

A18 API0_ADI41
B17 API0_ADI42
C17 API0_ADI43

API0_ADO41 B3
API0_ADO42 A7
API0_ADO43 B8

EI_NB_TO_CPU_SR_P<0>
EI_NB_TO_CPU_SR_N<0>
EI_NB_TO_CPU_SR_P<1>
EI_NB_TO_CPU_SR_N<1>

D17 API0_SRIP0
A19 API0_SRIN0
E17 API0_SRIP1

API0_SROP0 A3
API0_SRON0 A4
API0_SROP1 B5

B18 API0_SRIN1

API0_SRON1 B6

EI_QACK_L

D14 API_QACK0

NB_APSYNC

API0_ADO35 D1
API0_ADO36 B1
API0_ADO37 C1

0.1UF

20%
10V
CERM 2
402

25 24 13

POST-RAMP QUAL

EI_QREQ_L
SMU_SUSPENDREQ_L
TABLE_ALT_HEAD

PART NUMBER

ALTERNATE FOR
PART NUMBER

353S0920

353S0867

BOM OPTION

REF DES

COMMENTS:

U2850

PERICOM ANALOG SWITCH CRITICAL

EI_CPU_TO_NB_AD<0..43>
EI_NB_TO_CPU_AD<0..43>

EI_CPU_TO_NB_CAD
EI_NB_TO_CPU_CAD

EI_CAD
EI_CAD

EI_CPU_TO_NB_AD
EI_NB_TO_CPU_AD

EI_CPU_TO_NB_SR_P<0>
EI_CPU_TO_NB_SR_N<0>
EI_CPU_TO_NB_SR_P<1>
EI_CPU_TO_NB_SR_N<1>

EI_CPU_TO_NB_CAD
EI_CPU_TO_NB_CAD
EI_CPU_TO_NB_CAD
EI_CPU_TO_NB_CAD

EI_CAD
EI_CAD
EI_CAD
EI_CAD

EI_CPU_TO_NB_CLK
EI_CPU_TO_NB_CLK
EI_CPU_TO_NB_CLK
EI_CPU_TO_NB_CLK

EI_CPU_TO_NB_SR0
EI_CPU_TO_NB_SR0
EI_CPU_TO_NB_SR1
EI_CPU_TO_NB_SR1

EI_NB_TO_CPU_SR_P<0>
EI_NB_TO_CPU_SR_N<0>
EI_NB_TO_CPU_SR_P<1>
EI_NB_TO_CPU_SR_N<1>

EI_NB_TO_CPU_CAD
EI_NB_TO_CPU_CAD
EI_NB_TO_CPU_CAD
EI_NB_TO_CPU_CAD

EI_CAD
EI_CAD
EI_CAD
EI_CAD

EI_NB_TO_CPU_CLK
EI_NB_TO_CPU_CLK
EI_NB_TO_CPU_CLK
EI_NB_TO_CPU_CLK

EI_NB_TO_CPU_SR0
EI_NB_TO_CPU_SR0
EI_NB_TO_CPU_SR1
EI_NB_TO_CPU_SR1

y
r

API_CSTP F14

OMIT

OMIT

OMIT

ZT2858

ZT2849
1

ZT2850
1

OMIT

6 14 28 29

ZT2851

6 14 28 29
6 14 28 29

OMIT

6 14 28 29

ZT2852

6 14 28 29

OMIT

ZT2853

6 14 28 29

m
il
6 14 28 29

OMIT

6 14 28 29

ZT2854

6 14 28 29

HOLE-VIA-20R10

6 14 28 29

6 14 28 29

OMIT

6 14 28 29

ZT2855

6 14 28 29

HOLE-VIA-20R10

6 14 28 29

6 14 28 29
6 14 28 29

OMIT

ZT2800

ZT2810

ZT2820

HOLE-VIA-20R10

HOLE-VIA-20R10

OMIT

OMIT

OMIT

OMIT

OMIT

ZT2801

ZT2811

ZT2821

OMIT

ZT2831

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

OMIT

OMIT

OMIT

OMIT

OMIT

OMIT

ZT2802

ZT2812

ZT2822

ZT2832

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

OMIT

OMIT

OMIT

OMIT

OMIT

ZT2803

ZT2813

ZT2823

HOLE-VIA-20R10

HOLE-VIA-20R10

OMIT

OMIT

OMIT

OMIT

OMIT

ZT2864

ZT2804

ZT2814

ZT2824

OMIT

HOLE-VIA-20R10

HOLE-VIA-20R10

HOLE-VIA-20R10

OMIT

OMIT

OMIT

OMIT

OMIT

ZT2865

HOLE-VIA-20R10
1

ZT2805

HOLE-VIA-20R10
1

ZT2815

ZT2825

OMIT

HOLE-VIA-20R10

OMIT

OMIT

OMIT

ZT2806

HOLE-VIA-20R10
1

ZT2816

HOLE-VIA-20R10
1

6 14 28 29

=PP1V2_EI_NB

6 14 28 29

OMIT

ZT2826

ZT2846

PLACE QREQ CIRCUITS BETWEEN CPU AND U3LITE

ZT2866

HOLE-VIA-20R10

100

6 14 28 29

NOSTUFF

6 14 28 29

6 14 28 29

C2821

1%
1/16W
MF-LF
2 402

0.001UF

6 14 28 29

10%
50V
2 CERM
402

6 14 28 29

NOSTUFF

R2801
100

6 14 28 29

6 14 28 29

EI_APCLK_VREF
VOLTAGE=0.6V
NOSTUFF
NOSTUFF
1

C2820
0.1UF

1%
1/16W
MF-LF
2 402

6 14 28 29

20%
10V
2 CERM
402

EI_NB_CLK_P

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
NOSTUFF
1

R2803 R2804
121

121

1%
1/16W
MF-LF
2 402

1%
1/16W
MF-LF
2 402

EI_NB_CLK_P
EI_NB_CLK_N

EI_NB_CLK_N

CPU_CHKSTOP_L

OMIT

ZT2856

HOLE-VIA-20R10

27
27

29

QREQ TO SMU

MASTER: SEEDY

=PP3V3_PWRON_EI
NOSTUFF

U3LITE APPLE PI

R2898
10K

5%
1/16W
MF-LF
2 402

EI_NB_QREQ_L

10K

SMU_QREQ

180

13

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOSTUFF
EI_NB_QREQ_L_R

II NOT TO REPRODUCE OR COPY IT

Q2899

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

2N3904LF

5%
1/16W
MF-LF
402

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

SOT23
2

SIZE

5%
1/16W
MF-LF
402 2

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

REV.

051-6772

SHT
NONE

HOLE-VIA-20R10

R2802

R28511

5%
1/16W
MF-LF
402

ZT2836

HOLE-VIA-20R10

6 14 28 29

EI_CPU_TO_NB_SR_P<0>
EI_CPU_TO_NB_SR_N<0>
EI_CPU_TO_NB_SR_P<1>
EI_CPU_TO_NB_SR_N<1>

OMIT

HOLE-VIA-20R10

7 14 18 28

NOSTUFF

6 14 28 29

28 7

GND

ZT2845

HOLE-VIA-20R10

OMIT

6 14 28 29

NOSTUFF

ZT2835

HOLE-VIA-20R10
1

ZT2844

HOLE-VIA-20R10

HOLE-VIA-20R10
1

ZT2834

HOLE-VIA-20R10
1

ZT2843

HOLE-VIA-20R10

HOLE-VIA-20R10
1

OMIT

HOLE-VIA-20R10
1

ZT2842

ZT2833

HOLE-VIA-20R10
1

HOLE-VIA-20R10

HOLE-VIA-20R10
1

6 14 28 29

R2899
NOSTUFF

ZT2841

HOLE-VIA-20R10

LAST MODIFIED: NOV 4, 04

R2850

HOLE-VIA-20R10

6 14 28 29

TI

ZT2840

HOLE-VIA-20R10

HOLE-VIA-20R10

6 14 28 29

SOT23-5

VCC

OMIT

HOLE-VIA-20R10
1

ZT2839

ZT2830

HOLE-VIA-20R10
1

I225

HOLE-VIA-20R10

HOLE-VIA-20R10

ZT2863

HOLE-VIA-20R10

6 14 28 29

OMIT

6 14 28 29
6 14 28 29

OMIT

ZT2862

HOLE-VIA-20R10

6 14 28 29

OMIT

I224

OMIT

ZT2829

OMIT

I223

HOLE-VIA-20R10

6 14 28 29

ZT2819

I222

ZT2838

OMIT

HOLE-VIA-20R10

ZT2861

HOLE-VIA-20R10

ZT2809

I221

OMIT

HOLE-VIA-20R10

6 14 28 29

ZT2869

I220

HOLE-VIA-20R10

OMIT

I219

ZT2828

OMIT

I218

ZT2837

HOLE-VIA-20R10

HOLE-VIA-20R10

ZT2860

HOLE-VIA-20R10

ZT2818

HOLE-VIA-20R10

I215

HOLE-VIA-20R10

HOLE-VIA-20R10
1

OMIT

HOLE-VIA-20R10

OMIT

ZT2859

6 14 28 29

6 14 28 29

OMIT

HOLE-VIA-20R10

6 14 28 29

HOLE-VIA-20R10

OMIT

6 14 28 29

ZT2808

a
n
i
HOLE-VIA-20R10

6 14 28 29

ZT2868

I214

OMIT

OMIT

I213

I217

OMIT

OMIT

I212

I216

ZT2827

OMIT

6 14 28 29

6 14 28 29

OMIT

ZT2817

HOLE-VIA-20R10

ZT2848

6 14 28 29

ZT2807

HOLE-VIA-20R10

HOLE-VIA-20R10

6 14 28 29

OMIT

ZT2867

HOLE-VIA-20R10

6 14 28 29

74LVC1G66DBVG4

EI_CPU_TO_NB_CLK
EI_CPU_TO_NB_CLK
EI_NB_TO_CPU_CLK
EI_NB_TO_CPU_CLK

HOLE-VIA-20R10

U2850

TABLE_ALT_ITEM

EI_CPU_TO_NB_CLK
EI_CPU_TO_NB_CLK
EI_NB_TO_CPU_CLK
EI_NB_TO_CPU_CLK

HOLE-VIA-20R10

6 14 28 29

CRITICAL

30 29 14 6

DIFFERENTIAL_PAIR

EI_CLK
EI_CLK
EI_CLK
EI_CLK

OMIT

ZT2857

NET_PHYSICAL_TYPE

=PP3V3_PWRON_EI

C2850 1

NET_SPACING_TYPE

EI_CPU_TO_NB_CLK
EI_CPU_TO_NB_CLK
EI_NB_TO_CPU_CLK
EI_NB_TO_CPU_CLK

HOLE-VIA-20R10
6 14 28 29

EI_CPU_TO_NB_AD<0>
EI_CPU_TO_NB_AD<1>
EI_CPU_TO_NB_AD<2>
EI_CPU_TO_NB_AD<3>
EI_CPU_TO_NB_AD<4>
EI_CPU_TO_NB_AD<5>
EI_CPU_TO_NB_AD<6>
EI_CPU_TO_NB_AD<7>
EI_CPU_TO_NB_AD<8>
EI_CPU_TO_NB_AD<9>
EI_CPU_TO_NB_AD<10>
EI_CPU_TO_NB_AD<11>
EI_CPU_TO_NB_AD<12>
EI_CPU_TO_NB_AD<13>
EI_CPU_TO_NB_AD<14>
EI_CPU_TO_NB_AD<15>
EI_CPU_TO_NB_AD<16>
EI_CPU_TO_NB_AD<17>
EI_CPU_TO_NB_AD<18>
EI_CPU_TO_NB_AD<19>
EI_CPU_TO_NB_AD<20>
EI_CPU_TO_NB_AD<21>
EI_CPU_TO_NB_AD<22>
EI_CPU_TO_NB_AD<23>
EI_CPU_TO_NB_AD<24>
EI_CPU_TO_NB_AD<25>
EI_CPU_TO_NB_AD<26>
EI_CPU_TO_NB_AD<27>
EI_CPU_TO_NB_AD<28>
EI_CPU_TO_NB_AD<29>
EI_CPU_TO_NB_AD<30>
EI_CPU_TO_NB_AD<31>
EI_CPU_TO_NB_AD<32>
EI_CPU_TO_NB_AD<33>
EI_CPU_TO_NB_AD<34>
EI_CPU_TO_NB_AD<35>
EI_CPU_TO_NB_AD<36>
EI_CPU_TO_NB_AD<37>
EI_CPU_TO_NB_AD<38>
EI_CPU_TO_NB_AD<39>
EI_CPU_TO_NB_AD<40>
EI_CPU_TO_NB_AD<41>
EI_CPU_TO_NB_AD<42>
EI_CPU_TO_NB_AD<43>

e
r

QREQ_L HACK
28 7

EI_CPU_TO_NB_CLK_P
EI_CPU_TO_NB_CLK_N

API_QREQ0 E14

API_APCLKP D18
API_APCLKN C18

API_APCLK_AVSS

402

EI_SE

API0_ADO24 F6
API0_ADO25 E5
API0_ADO26 D5

G20

API0_ADO13 J3
API0_ADO14 J5
API0_ADO15 J6

E8 API0_APSYNC
H17 API0_SE

OMIT

ZT2847

D9 API0_ADI8
C9 API0_ADI9
D11 API0_ADI10

NOSTUFF

30 29 14 6

F10
D4

H12 API0_ADI5
H14 API0_ADI6
G14 API0_ADI7

R2806
EI_SYNC_FROM_NB

PBGA
(SYM 1 OF 7)

OMIT

402

29

OMIT

U3LITE
V1.0-300MM

EI_CPU_TO_NB_CLK_P
EI_CPU_TO_NB_CLK_N
EI_NB_TO_CPU_CLK_P
EI_NB_TO_CPU_CLK_N

VDD_API

F11 API0_ADI0
F12 API0_ADI1
G11 API0_ADI2
H11 API0_ADI3
G12 API0_ADI4

EI_NB_SYNC

29 28 14 6

U3

EI_NB_TO_CPU_AD<0>
EI_NB_TO_CPU_AD<1>
EI_NB_TO_CPU_AD<2>
EI_NB_TO_CPU_AD<3>
EI_NB_TO_CPU_AD<4>
EI_NB_TO_CPU_AD<5>
EI_NB_TO_CPU_AD<6>
EI_NB_TO_CPU_AD<7>
EI_NB_TO_CPU_AD<8>
EI_NB_TO_CPU_AD<9>
EI_NB_TO_CPU_AD<10>
EI_NB_TO_CPU_AD<11>
EI_NB_TO_CPU_AD<12>
EI_NB_TO_CPU_AD<13>
EI_NB_TO_CPU_AD<14>
EI_NB_TO_CPU_AD<15>
EI_NB_TO_CPU_AD<16>
EI_NB_TO_CPU_AD<17>
EI_NB_TO_CPU_AD<18>
EI_NB_TO_CPU_AD<19>
EI_NB_TO_CPU_AD<20>
EI_NB_TO_CPU_AD<21>
EI_NB_TO_CPU_AD<22>
EI_NB_TO_CPU_AD<23>
EI_NB_TO_CPU_AD<24>
EI_NB_TO_CPU_AD<25>
EI_NB_TO_CPU_AD<26>
EI_NB_TO_CPU_AD<27>
EI_NB_TO_CPU_AD<28>
EI_NB_TO_CPU_AD<29>
EI_NB_TO_CPU_AD<30>
EI_NB_TO_CPU_AD<31>
EI_NB_TO_CPU_AD<32>
EI_NB_TO_CPU_AD<33>
EI_NB_TO_CPU_AD<34>
EI_NB_TO_CPU_AD<35>
EI_NB_TO_CPU_AD<36>
EI_NB_TO_CPU_AD<37>
EI_NB_TO_CPU_AD<38>
EI_NB_TO_CPU_AD<39>
EI_NB_TO_CPU_AD<40>
EI_NB_TO_CPU_AD<41>
EI_NB_TO_CPU_AD<42>
EI_NB_TO_CPU_AD<43>

R2805
27

29 28 14 6
29 28 14 6

F7

20%
10V
2 CERM
402

API
APCLK_AVDD

29 28 14 6

7 14 18 28

0.1UF
H16
G2

1UF

H13

10%
6.3V
2 CERM
402

29 28 14 6

29 28 14 6

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

K8
J13

F21

2.2

29 28 14 6

K4

60 48 37 7

7 14 18 28

28

OF

04
102

PLACE NEAR PROCESSOR.


PLACE AT PROCESSOR PINS.

35 31 30 29 18 14 7

=PP1V2_EI_CPU
NOSTUFF

NOSTUFF

R2909

R2903

27

EI_CPU_CLK_P

100

46.4 2

1%
1/16W
MF-LF
2 402

1%
1/16W
MF-LF
402

NOSTUFF

R2901
27

EI_CPU_CLK_N

46.4 2
1%
1/16W
MF-LF
402

MORE PROCESSOR DECOUPLING ON PAGES 31 & 32

=PPVCORE_CPU

SYSCLK_TERM
VOLTAGE=0.6V

NOSTUFF
1

36 32 31 7

NOSTUFF

10%
6.3V
2 CERM
402

R2907

C2901

100

0.22UF

1%
1/16W
MF-LF
2 402

20%
6.3V
2 X5R
402

C2953
1UF

C2954

1UF

T22
R22

SYSCLK*

28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28

14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14

28 14
28 14
28 14
28 14

6 EI_NB_TO_CPU_AD<0>
6 EI_NB_TO_CPU_AD<1>
6 EI_NB_TO_CPU_AD<2>
6 EI_NB_TO_CPU_AD<3>
6 EI_NB_TO_CPU_AD<4>
6 EI_NB_TO_CPU_AD<5>
6 EI_NB_TO_CPU_AD<6>
6 EI_NB_TO_CPU_AD<7>
6 EI_NB_TO_CPU_AD<8>
6 EI_NB_TO_CPU_AD<9>
6 EI_NB_TO_CPU_AD<10>
6 EI_NB_TO_CPU_AD<11>
6 EI_NB_TO_CPU_AD<12>
6 EI_NB_TO_CPU_AD<13>
6 EI_NB_TO_CPU_AD<14>
6 EI_NB_TO_CPU_AD<15>
6 EI_NB_TO_CPU_AD<16>
6 EI_NB_TO_CPU_AD<17>
6 EI_NB_TO_CPU_AD<18>
6 EI_NB_TO_CPU_AD<19>
6 EI_NB_TO_CPU_AD<20>
6 EI_NB_TO_CPU_AD<21>
6 EI_NB_TO_CPU_AD<22>
6 EI_NB_TO_CPU_AD<23>
6 EI_NB_TO_CPU_AD<24>
6 EI_NB_TO_CPU_AD<25>
6 EI_NB_TO_CPU_AD<26>
6 EI_NB_TO_CPU_AD<27>
6 EI_NB_TO_CPU_AD<28>
6 EI_NB_TO_CPU_AD<29>
6 EI_NB_TO_CPU_AD<30>
6 EI_NB_TO_CPU_AD<31>
6 EI_NB_TO_CPU_AD<32>
6 EI_NB_TO_CPU_AD<33>
6 EI_NB_TO_CPU_AD<34>
6 EI_NB_TO_CPU_AD<35>
6 EI_NB_TO_CPU_AD<36>
6 EI_NB_TO_CPU_AD<37>
6 EI_NB_TO_CPU_AD<38>
6 EI_NB_TO_CPU_AD<39>
6 EI_NB_TO_CPU_AD<40>
6 EI_NB_TO_CPU_AD<41>
6 EI_NB_TO_CPU_AD<42>
6 EI_NB_TO_CPU_AD<43>
6 EI_NB_TO_CPU_SR_P<0>
6 EI_NB_TO_CPU_SR_N<0>
6 EI_NB_TO_CPU_SR_P<1>
6 EI_NB_TO_CPU_SR_N<1>

H21
J21
H22
J22
C13
A13
K22
H23
J24
G20
F23
G21
D22
G24
G19
B15
A14
C15
D15
A16
C22
E20
E21
B23
B24
F21
B17
B19
C14
C17
D18
B21
D20
A22
C19
C18
A21
A23
A20
A18
A15
A17
C16
A19

L24
K24
L21
L22

EI_ADI0
EI_ADI1
EI_ADI2
EI_ADI3
EI_ADI4
EI_ADI5
EI_ADI6
EI_ADI7
EI_ADI8
EI_ADI9
EI_ADI10
EI_ADI11
EI_ADI12
EI_ADI13
EI_ADI14
EI_ADI15
EI_ADI16
EI_ADI17
EI_ADI18
EI_ADI19
EI_ADI20
EI_ADI21
EI_ADI22
EI_ADI23
EI_ADI24
EI_ADI25
EI_ADI26
EI_ADI27
EI_ADI28
EI_ADI29
EI_ADI30
EI_ADI31
EI_ADI32
EI_ADI33
EI_ADI34
EI_ADI35
EI_ADI36
EI_ADI37
EI_ADI38
EI_ADI39
EI_ADI40
EI_ADI41
EI_ADI42
EI_ADI43

28 14 6

EI_QACK_L

V21

QACK*

CHKSTOP_L

R20

CHKSTOP*

30 29 27

CPU_HTBEN
6

30 14 6

TP_PSYNCOUT

CPU_HRESET_L

AD17

TBEN

AD14

APSYNCOUT

V20

U2900
CBGA
(1 OF 3)

CPU_SRESET_L

AB4

SRESET*

PROC_THERM_INT_L

V22

THERM_INT*

30
30
30

PROCID0
PROCID1
PROCID2

EI_CLKO
EI_CLKO*

D3

EI_ADO0
EI_ADO1
EI_ADO2
EI_ADO3
EI_ADO4
EI_ADO5
EI_ADO6
EI_ADO7
EI_ADO8
EI_ADO9
EI_ADO10
EI_ADO11
EI_ADO12
EI_ADO13
EI_ADO14
EI_ADO15
EI_ADO16
EI_ADO17
EI_ADO18
EI_ADO19
EI_ADO20
EI_ADO21
EI_ADO22
EI_ADO23
EI_ADO24
EI_ADO25
EI_ADO26
EI_ADO27
EI_ADO28
EI_ADO29
EI_ADO30
EI_ADO31
EI_ADO32
EI_ADO33
EI_ADO34
EI_ADO35
EI_ADO36
EI_ADO37
EI_ADO38
EI_ADO39
EI_ADO40
EI_ADO41
EI_ADO42
EI_ADO43

N3

EI_SRO0
EI_SRO0*
EI_SRO1
EI_SRO1*

L3

30 28 14 6
14 6

30
30
30
30
30

30
30
30
30
30
29 14 6

30
30
30
30
30 14 6
30 14 6

EI_SE
TP_PROC_TRIGGER_OUT
6 TP_AFN
AVPRESET_L
BIMODE_L
C1UNDGLOBAL
C2UNDGLOBAL
DI2_L

LSSDMODE
LSSDSCANENABLE
LSSDSTOPC2ENABLE
LSSDSTOPC2STARENABLE
LSSDSTOPENABLE
MCP_L
6 TP_PSRO1
6 TP_PSRO2
PULSESEL0
PULSESEL1
PULSESEL2
RAMSTOPENABLE
RI_L
SYNCENABLE

N21
N19

AA12
W23
AC24
AC16
AC15
U24

AB5
U19
AD8
AD7
AD11
AD18

V23
V5
AC9
AB11
AC10
AB6
AA5
AB24

K3
L1
M3
K4
K2
H3
H1
G4
F2
F4
E2
G3
B8
D11
E12
A11
B10
C11
C1
C5
B2
D6
A5
A2
D2
D8
C12
A12
B6
B4
C4
C7
A7
C8
C6
A4
A9
C9
A10
C10
A8
A6

L2
G1
F1

PROCID0
PROCID1
PROCID2
TRIGGER_IN
TRIGGER_OUT
AFN
AVPRESET*
BIMODE*
C1UNDGLOBAL
C2UNDGLOBAL
DI2*
LSSDMODE
LSSDSCANENABLE
LSSDSTOPC2ENABLE
LSSDSTOPC2STARENABLE
LSSDSTOPENABLE
MCP*

10%
6.3V
2 CERM
402

C2948

1UF

10%
6.3V
2 CERM
402

C2946

y
r

1UF

10%
6.3V
2 CERM
402

1UF

10%
6.3V
2 CERM
402

C2939

C2940

6 14 28
6 14 28
6 14 28
6 14 28

6 14 28 30

CPU_INT_L

6 14 25 30

APSYNCIN

AA10

IIC_SCL
IIC_SDA

AA20

PSRO1
PSRO2
PULSESEL0
PULSESEL1
PULSESEL2
RAMSTOPENABLE
RI*
SYNCENABLE*

1UF

10%
6.3V
2 CERM
402

10%
6.3V
2 CERM
402

18
18

N22

I2CGO

30

AA14

CKTERMDIS_L

30

P20

EI_DISABLE

30

AA19

ATTENTION
GPUL_DBG
JTAGMODE

AD12

TCK
TDI
TDO
TMS
TRST*

AD21

49.9 2
1

10%
6.3V
2 CERM
402

10%
6.3V
2 CERM
402

AC19
AB16

AA22
W4

AB21
AD13
AD22
W20

1UF

10%
6.3V
2 CERM
402

AB7
AA9
W22
T19

PLACE BY PROCESSOR PIN.

28

TP_ATTENTION
GPUL_DBG
JTAGMODE_SPARE2

6
30
30

JTAG_CPU_TCK
JTAG_CPU_TDI
JTAG_CPU_TDO
JTAG_CPU_TMS
JTAG_CPU_TRST_L

18
18
18
18
30

CPU_SPARE

AA13

P
0

1UF

10%
6.3V
2 CERM
402

C2952

1UF

10%
6.3V
2 CERM
402

C2950

C2960

C2959
1UF

10%
6.3V
2 CERM
402

10%
6.3V
2 CERM
402

C2910
1UF

10%
6.3V
2 CERM
402

C2909
1UF

10%
6.3V
2 CERM
402

C2943
1UF

10%
6.3V
2 CERM
402

1UF

10%
6.3V
2 CERM
402

1UF

C2949
1UF

10%
6.3V
2 CERM
402

1UF

10%
6.3V
2 CERM
402

C2944

10%
6.3V
2 CERM
402

C2958
1UF

10%
6.3V
2 CERM
402

C2908
1UF

10%
6.3V
2 CERM
402

C2941
1UF

10%
6.3V
2 CERM
402

C2942

C2957
1UF

10%
6.3V
2 CERM
402

C2907
1UF

10%
6.3V
2 CERM
402

C2929

1UF

10%
6.3V
2 CERM
402

C2930

C2931

10%
6.3V
2 CERM
402

1UF

C2927

1UF

10%
6.3V
2 CERM
402

10%
6.3V
2 CERM
402

C2918

C2934

C2919

10%
6.3V
2 CERM
402

C2916

C2917
1UF

10%
6.3V
2 CERM
402

C2933

C2932
1UF

10%
6.3V
2 CERM
402

1UF

1UF

1UF

C2904

1UF

1UF

C2913

10%
6.3V
2 CERM
402

10%
6.3V
2 CERM
402

10%
6.3V
2 CERM
402

C2905
1UF

C2923

10%
6.3V
2 CERM
402

10%
6.3V
2 CERM
402

1UF

C2915
1UF

C2912
1UF

1UF

1UF

10%
6.3V
2 CERM
402

C2906

C2922

10%
6.3V
2 CERM
402

C2935

10%
6.3V
2 CERM
402

10%
6.3V
2 CERM
402

10%
6.3V
2 CERM
402

1UF

C2921
1UF

C2914

10%
6.3V
2 CERM
402

1UF

1UF

10%
6.3V
2 CERM
402

C2926

10%
6.3V
2 CERM
402

C2936

1UF

10%
6.3V
2 CERM
402

10%
6.3V
2 CERM
402

1UF

C2925
1UF

C2920

10%
6.3V
2 CERM
402

1UF

10%
6.3V
2 CERM
402

1UF

10%
6.3V
2 CERM
402

1UF

C2924

10%
6.3V
2 CERM
402

EI_CPU_SYNC

27

5%
1/16W
MF-LF
402

NOSTUFF

EI_SYNC_FROM_NB

28

5%
1/16W
MF-LF
402

30
30
30
30

10%
6.3V
2 CERM
402

C2903 1C2902
1UF

1UF

10%
6.3V
2 CERM
402

10%
6.3V
2 CERM
402

30
8
30
30
30
30
30

PROCESSOR IIC ADDRESS:


80,84

30

=PP1V2_EI_CPU

R2906

R2908

1K

1K

5%
1/16W

5%
1/16W
MF-LF
402

MF-LF

2 402

MASTER: GILA
LAST MODIFIED: APR 09, 04

CHKSTOP_L 6

NEO APPLE PI

8 14 29

5%
1/16W
MF-LF
402

CPU_CHKSTOP_L

1UF

10%
6.3V
2 CERM
402

1UF

10%
6.3V
2 CERM
402

C2928
1UF

1UF

1UF

10%
6.3V
2 CERM
402

C2938

m
il

R2910
1

30
30
30

CPU_BYPASS_L
PLLLOCK
PLLMULT
PLLRANGE0
PLLRANGE1
PLLTEST
PLLTESTOUT

V24
T20
AA8

C2911

C2951

C2937

e
r
BUSCFG0
BUSCFG1
BUSCFG2

R2902

1%
1/16W
MF-LF
402

C2900
1UF

Y21

C2956

1UF

CPU_APSYNC
I2C_CPU_A_SCL
I2C_CPU_A_SDA

BUSCFG0
BUSCFG1
BUSCFG2

SPARE

MATCH TO SYSCLK

C2955

1UF

a
n
i
1

28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28
28

EI_QREQ_L

BYPASS*
PLLLOCK
PLLMULT
PLLRANGE0
PLLRANGE1
PLLTEST
PLLTESTOUT

NOSTUFF

EI_CPU_TO_NB_SR_P<0>
EI_CPU_TO_NB_SR_N<0>
EI_CPU_TO_NB_SR_P<1>
EI_CPU_TO_NB_SR_N<1>

14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14

AB19

EI_DISABLE

R2905
CPU_HTBEN

6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6

AB12

35 31 30 29 18 14 7

30 29 27

6 14 28
6 14 28

INT*

I2CGO

M18

H2

EI_CPU_TO_NB_CLK_P
EI_CPU_TO_NB_CLK_N
EI_CPU_TO_NB_AD<0>
EI_CPU_TO_NB_AD<1>
EI_CPU_TO_NB_AD<2>
EI_CPU_TO_NB_AD<3>
EI_CPU_TO_NB_AD<4>
EI_CPU_TO_NB_AD<5>
EI_CPU_TO_NB_AD<6>
EI_CPU_TO_NB_AD<7>
EI_CPU_TO_NB_AD<8>
EI_CPU_TO_NB_AD<9>
EI_CPU_TO_NB_AD<10>
EI_CPU_TO_NB_AD<11>
EI_CPU_TO_NB_AD<12>
EI_CPU_TO_NB_AD<13>
EI_CPU_TO_NB_AD<14>
EI_CPU_TO_NB_AD<15>
EI_CPU_TO_NB_AD<16>
EI_CPU_TO_NB_AD<17>
EI_CPU_TO_NB_AD<18>
EI_CPU_TO_NB_AD<19>
EI_CPU_TO_NB_AD<20>
EI_CPU_TO_NB_AD<21>
EI_CPU_TO_NB_AD<22>
EI_CPU_TO_NB_AD<23>
EI_CPU_TO_NB_AD<24>
EI_CPU_TO_NB_AD<25>
EI_CPU_TO_NB_AD<26>
EI_CPU_TO_NB_AD<27>
EI_CPU_TO_NB_AD<28>
EI_CPU_TO_NB_AD<29>
EI_CPU_TO_NB_AD<30>
EI_CPU_TO_NB_AD<31>
EI_CPU_TO_NB_AD<32>
EI_CPU_TO_NB_AD<33>
EI_CPU_TO_NB_AD<34>
EI_CPU_TO_NB_AD<35>
EI_CPU_TO_NB_AD<36>
EI_CPU_TO_NB_AD<37>
EI_CPU_TO_NB_AD<38>
EI_CPU_TO_NB_AD<39>
EI_CPU_TO_NB_AD<40>
EI_CPU_TO_NB_AD<41>
EI_CPU_TO_NB_AD<42>
EI_CPU_TO_NB_AD<43>

QREQ*

CKTERMDIS
L19
M19

E3

R2911

HRESET*

30

30 25

OMIT

CRITICAL

EI_SRI0
EI_SRI0*
EI_SRI1
EI_SRI1*

29 14 8 6

C2945

SYSCLK

E24 EI_CLKI
D24
EI_CLKI*

NEO-10S-REV2
1.8GHZ-76C

28 14 6 EI_NB_TO_CPU_CLK_P
28 14 6 EI_NB_TO_CPU_CLK_N

1UF

10%
6.3V
2 CERM
402

1UF

10%
6.3V
2 CERM
402

C2947

NOTICE OF PROPRIETARY PROPERTY

NOSTUFF

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

R2904
1

MCP_L

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

6 14 29

5%
1/16W
MF-LF
402

II NOT TO REPRODUCE OR COPY IT


III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

PROCESSOR LOGIC I/O

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-6772

04

OF

29

102

SELECT PROCESSOR CLOCK MULTIPLIER. PROCESSOR CLOCK(MHZ)= SYSTCLOCK * PLLMULT.


TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION
TABLE_5_ITEM

114S1103

RES,1K OHM,1/16W,5%,0402

R3034

EI_3TO1

114S1103

RES,1K OHM,1/16W,5%,0402

R3018

EI_2TO1

SYSCLK * 12
TABLE_5_ITEM

=PP1V2_EI_CPU

7 14 18 29 30 31 35

SELECT EI BUS DIVIDER. BUS DATA RATE(BPS)= (PROCESSOR CLOCK) / BUSCFG.

R3039
29

JTAGMODE_SPARE2

SYSCLK * 8

TABLE_5_HEAD

35 31 30 29 18 14 7

=PP1V2_EI_CPU

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION
TABLE_5_ITEM

29

C1UNDGLOBAL

R3077

R3043

1K

1K

5%
1/16W
MF-LF
402

29 18

R3079

R3069

1K

5%
1/16W
MF-LF
402

1K

BIMODE_L

29

R3073

DI2_L

29 14 6

RI_L

5%
1/16W
MF-LF
402

R3042

1K

1K

1K

29 25 14 6

CPU_INT_L

1K

LSSDSTOPC2ENABLE

PROC_THERM_INT_L

1K

29

LSSDSTOPC2STARENABLE

1K

2
29

LSSDSTOPENABLE

1K

2
29 28 14 6

EI_QREQ_L

1K

10K

SYNCENABLE

1K

RAMSTOPENABLE

1K

CPU_SPARE

1K

29

29 28 14 6

EI_SE

R3083
1K

5%
1/16W
MF-LF
1 402

Q3000
2N7002DW
SOT-363

=PP1V2_EI_CPU

7 14 18 29 30 31 35

R3059
1K

5%
1/16W
MF-LF
2 402

CPU_BYPASS_L

Q3000
2N7002DW

13

CPU_BYPASS

SOT-363

1K

29

NOSTUFF
1

R3057

1K

RES,1K OHM,1/16W,5%,0402

R3024,R3010,R3012

NOSTUFF

RES,1K OHM,1/16W,5%,0402

R3008,R3026,R3028

NOSTUFF

RES,1K OHM,1/16W,5%,0402

R3008,R3026,R3012

NOSTUFF

RES,1K OHM,1/16W,5%,0402

R3008,R3010,R3028

NOSTUFF

RES,1K OHM,1/16W,5%,0402

R3008,R3010,R3012

NOSTUFF

y
r

114S1103

1K

PROC / 6
TABLE_5_ITEM

PROC / 8
TABLE_5_ITEM

PROC / 12
TABLE_5_ITEM

PROC / 16
TABLE_5_ITEM

PART#

QTY

114S1103
114S1103

DESCRIPTION

TABLE_5_HEAD

REFERENCE DESIGNATOR(S)

BOM OPTION
TABLE_5_ITEM

RES,1K OHM,1/16W,5%,0402

R3036

RES,1K OHM,1/16W,5%,0402

R3020

TABLE_5_ITEM

BYPASS MODE

NOSTUFF

SELECT PLL FREQUENCY RANGE.


PART#

>= 1.8 GHZ *


<= 1.6 GHZ *

114S1103
114S1103

114S1103

QTY

DESCRIPTION

TABLE_5_HEAD

REFERENCE DESIGNATOR(S)

BOM OPTION
TABLE_5_ITEM

RES,1K OHM,1/16W,5%,0402

R3030,R3032

CPU_PLL_LOW

RES,1K OHM,1/16W,5%,0402

R3030,R3016

CPU_PLL_HIGH

RES,1K OHM,1/16W,5%,0402

R3014,R3032

CPU_PLL_MEDIUM

RES,1K OHM,1/16W,5%,0402

R3014,R3016

NOSTUFF

QTY

DESCRIPTION

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

RESERVED

TABLE_5_HEAD

REFERENCE DESIGNATOR(S)

BOM OPTION
TABLE_5_ITEM

RES,1K OHM,1/16W,5%,0402

AVPRESET OFF

R3022
TABLE_5_ITEM

RES,1K OHM,1/16W,5%,0402

R3038

AVPRESET ON

NOSTUFF

m
il

=PP1V2_EI_CPU

7 14 18 29 30 31 35

R3068
10K

5%
1/16W
MF-LF
2 402

SYSTEM CONFIGURATION

35 31 30 29 18 14 7

29
29
29
29
29
29
29
29

=PP1V2_EI_CPU

1 OMIT

1 OMIT

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

R3008
1K

R3010
1K

OMIT

R3012
1K

1 OMIT

1 OMIT

1 OMIT

1 OMIT

1 OMIT

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

2 402

R3014
1K

R3016
1K

R3018
1K

R3020
1K

R3022
1K
5%
1/16W
MF-LF

BUSCFG0
BUSCFG1
BUSCFG2
PLLRANGE0
PLLRANGE1
PLLMULT
EI_DISABLE
AVPRESET_L

B
1 OMIT

1 OMIT

1 OMIT

1 OMIT

1 OMIT

1 OMIT

1 OMIT

1 OMIT

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

2 402

R3024
1K

R3026
1K

R3028
1K

R3030
1K

R3032
1K

R3034
1K

R3036
1K

R3038
1K
5%
1/16W
MF-LF

5%
1/16W
MF-LF
402

R3002

29 PROCID0

1K

5%
1/16W
MF-LF
402

R3004

29 PROCID1

1K

MASTER: GILA

LAST MODIFIED: APR 27, 04

5%
1/16W
MF-LF
402

CPU STRAPS

R3006
29 PROCID2

1K

NOTICE OF PROPRIETARY PROPERTY

2
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

5%
1/16W
MF-LF
402

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

1K

5%
1/16W
MF-LF
2 402

II NOT TO REPRODUCE OR COPY IT


III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-6772

SCALE

PROC / 4

SELECT ELASTIC MODE OR BYPASS.

114S1103

R3007

29 PULSESEL2

114S1103

PROC / 3

* STUFF THESE ON Q45.

5%
1/16W
MF-LF
402

6 14 29

CPU_HRESET

PULSESEL1

NOSTUFF

a
n
i

10K

R3005

29

CPU_HRESET_L

13

R3024,R3010,R3028

114S1103

5%
1/16W
MF-LF
402

7 14 18 29 30 31 35

PULSESEL0

RES,1K OHM,1/16W,5%,0402

114S1103

e
r
29

PART#

R3003

=PP1V2_EI_CPU

PLLTESTOUT

5%
1/16W
MF-LF
402

1K

114S1103

PROC / 2
TABLE_5_ITEM

114S1103

5%
1/16W
MF-LF
402

R3081

EI_3TO1

114S1103

R3071

5%
1/16W
MF-LF
402

1K

EI_2TO1

R3024,R3026,R3012

NOSTUFF

R3067
29

R3024,R3026,R3028

RES,1K OHM,1/16W,5%,0402

114S1103

5%
1/16W
MF-LF
402
NOSTUFF

RES,1K OHM,1/16W,5%,0402

TABLE_5_ITEM

5%
1/16W
MF-LF
402

R3055
29

5%
1/16W
MF-LF
402

29 18 JTAG_CPU_TMS

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

R3099

R3037

R3089
CPU_HTBEN

10K

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

29 27

1K

114S1103

5%
1/16W
MF-LF
402

R3053

R3087
I2CGO

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

29

10K

R3051

29 14 6

1K

114S1103

R3097
29 18 JTAG_CPU_TDI

5%
1/16W
MF-LF
402

R3085
CPU_SRESET_L

1K

5%
1/16W
MF-LF
402

R3049

5%
1/16W
MF-LF
402

29 25

29 18 JTAG_CPU_TCK

5%
1/16W
MF-LF
402

R3065
29

1K

R3095

R3047
29

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

R3091

NOSTUFF

5%
1/16W
MF-LF
402

LSSDSCANENABLE

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

R3040
1K

29

R3035

GPUL_DBG

5%
1/16W
MF-LF
402

R3075
5%
1/16W
MF-LF
402

1K

1K

TABLE_5_ITEM

R3041

R3033

5%
1/16W
MF-LF
402

1K

1K

R3001

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

CKTERMDIS_L

1K

LSSDMODE

R3031
29

R3061

NOSTUFF

29

R3063
5%
1/16W
MF-LF
402
29

JTAG_CPU_TDO

PLLTEST

1K

29

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

NOSTUFF

R3045

R3093

C2UNDGLOBAL

1K

1K

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

NOSTUFF

29

JTAG_CPU_TRST_L

NOSTUFF

R3000
JTAG_SEL

29

NOSTUFF

29

5%
1/16W
MF-LF
402

R3009

04

OF

30

102

=PP1V2_EI_CPU

=PPVCORE_CPU

36 32 31 29 7

7 14 18 29 30 35

VOLTAGE=1.2V
MIN_LINE_WIDTH=10MIL
MIN_NECK_WIDTH=8MIL
=PP2V5_RUN_CPU

8 7 6 3

L3101

VR3100
SOT-25A
1

CPU_AVDD_EN

CONT NOISE

VOLTAGE=2.5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

SM
0805

CPU_AVDD_NOISE

2.2

5%
1/10W
MF-LF
603

C3148
0.01UF

1UF

20%
16V
CERM 2
402

20%

2 10V
CERM
603

C3150

AVDD

C3199

1
1

C3102
10UF

10%
2 6.3V
CERM
402

C3100
0.22UF

20%
6.3V
2 X5R
402

10UF

20%
2 6.3V
CERM
805

TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION
TABLE_5_ITEM

CRITICAL 353S0806

VREG MM1572 2.6V

VR3100

CPU_AVDD_2V6
TABLE_5_ITEM

CRITICAL 353S0886

VREG MM1572 2.7V

VR3100

CPU_AVDD_2V7
TABLE_5_ITEM

CRITICAL 353S0807

VREG MM1572 2.8V

VR3100

CPU_AVDD_2V8

10UF

10UF

10UF

20%
6.3V
2 CERM
805

20%
6.3V
2 CERM
805

20%
6.3V
2 CERM
805

C3114

10UF

10%
6.3V
2 CERM
402

CRITICAL

U2900
CBGA
(2 OF 3)

A3
B1
B12
B14
B18
B22
B5
B9
C21
C23
C3
D1
D10
D12
D14
D16
D4
E11
E13
E15
E17
E19
E23
E5
E7
E9
F10
F12
F14
F16
F18
F20
F22
F24
F6
F8
G11
G13
G15
G17
G2
G23
G5
G7
G9
H10
H12
H14
H16
H18
H20
H4
H6
H8
J11
J13
J15
J17
J19
J23
J3
J5
J7
J9
K1
K10
K12
K14
K16
K18
K20
K6
K8
L11
L13
L15
L17
L23
L5
L7
L9
M10
M12
M14
M16
M2
M20
M22
M24
M4
M6
M8
N1
N11
N13
N15
N17
N23
N5
N7
N9
P10
P12
P14
P16

OMIT

CRITICAL

GND

X105

CBGA

(3 OF 3)

X105

KPGND1

GND_SPARE_GND

31

VCORE
X100

XW3100
SM

C3106
1UF

10%
6.3V
2 CERM
402

GND
X99

P18
P2
P22
P4
P6
P8
R1
R11
R13
R15
R17
R19
R21
R23
R3
R5
R7
R9
T10
T12
T14
T16
T18
T24
T4
T6
T8
U1
U11
U13
U15
U17
U21
U23
U3
U5
U7
U9
V10
V12
V14
V16
V18
V2
V4
V6
V8
W1
W11
W13
W15
W17
W19
W21
W3
W5
W7
W9
Y10
Y12
Y14
Y16
Y18
Y2
Y20
Y24
Y4
Y6
Y8
AA11
AA15
AA17
AA21
AA23
AA3
AA7
AB10
AB14
AB18
AB2
AB20
AB22
AB8
AC1
AC11
AC13
AC17
AC21
AC23
AC3
AC5
AC7
AD10
AD16
AD2
AD20
AD24
AD4
AD6

GND_Z_OUT

31

GND_Z_SENSE

31

10%
2 6.3V
CERM
402

C3113

10%
6.3V
2 CERM
402

C3126

C3127
1UF

10%
6.3V
2 CERM
402

31 GND_Z_OUT

C3103
1UF

31 GND_Z_SENSE

C3104

1UF

10%
2 6.3V
CERM
402

C3108
1UF

C3118
1UF

10%
2 6.3V
CERM
402

C3121

C3119
1UF

10%
6.3V
2 CERM
402

C3124

1UF

10%
2 6.3V
CERM
402

C3122
1UF

10%
6.3V
2 CERM
402

C
C3129

10%
6.3V
2 CERM
402

1UF

1UF

C3137
1UF

10%
6.3V
2 CERM
402

10%
2 6.3V
CERM
402

C3134

1UF

10%
6.3V
2 CERM
402

C3135

10%
2 6.3V
CERM
402

C3141
1UF

C3132
1UF

C3133
1UF

10%
2 6.3V
CERM
402

10%
6.3V
2 CERM
402

C3146

1UF

1UF

C3130

10%
6.3V
2 CERM
402

10%
2 6.3V
CERM
402

C3145

10%
6.3V
2 CERM
402

1UF

C3123
1UF

1UF

1UF

C3131

10%
6.3V
2 CERM
402

C3138

10%
6.3V
2 CERM
402

10%
2 6.3V
CERM
402

10%
2 6.3V
CERM
402

C3125

10%
6.3V
2 CERM
402

C3136

R3129

10%
6.3V
2 CERM
402

R3131
31 GND_SPARE_GND1

C3120

1UF

1UF

10%
2 6.3V
CERM
402

1UF

1UF

C3107

10%
6.3V
2 CERM
402

10%
6.3V
2 CERM
402

C3128

C3139
1UF

10%
6.3V
2 CERM
402

C3142

1UF

10%
2 6.3V
CERM
402

C3140
1UF

10%
2 6.3V
CERM
402

5%
1/16W
MF-LF
402

NET_SPACING_TYPE=PROC_DIFF

C3110

10%
2 6.3V
CERM
402

1UF

R3127

C3147
1UF

5%
1/16W
MF-LF
402

C3144
1UF

10%
6.3V
2 CERM
402

C3143
1UF

10%
6.3V
2 CERM
402

5%
1/16W
MF-LF
402

MASTER: GILA
LAST MODIFIED: JULY 9, 04

36 32 31 29 7

CPU POWER AND BYPASS

NOSTUFF

R3103

=PPVCORE_CPU

2
NOSTUFF

5%
1/16W
MF-LF
402
NOSTUFF

5%
1/16W
MF-LF
402

C3101
0.22UF

KPVDD2
MIN_LINE_WIDTH=10MIL

NOTICE OF PROPRIETARY PROPERTY

6 33 36

MIN_NECK_WIDTH=8MIL
DIFFERENTIAL_PAIR=P_KP2
NET_SPACING_TYPE=PROC_DIFF

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

20%
6.3V
2 X5R
402

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


KPGND2
MIN_LINE_WIDTH=10MIL

II NOT TO REPRODUCE OR COPY IT


6 33 36

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

MIN_NECK_WIDTH=8MIL
DIFFERENTIAL_PAIR=P_KP2
NET_SPACING_TYPE=PROC_DIFF

SIZE

PLACE ALL THESE PARTS VERY CLOSE TO U2900

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-6772

SCALE

10%
6.3V
2 CERM
402

10%
2 6.3V
CERM
402

10%
6.3V
2 CERM
402

10%
2 6.3V
CERM
402

C3109

1UF

1UF

TDIODE_NEG 6 36
DIFFERENTIAL_PAIR=P_TDD
MIN_LINE_WIDTH=10MIL
MIN_NECK_WIDTH=8MIL

C3105
1UF

1UF

1UF

R3105

10%
6.3V
2 CERM
402

10%
2 6.3V
CERM
402

1UF

T2

AA1

C3112
1UF

KPGND2

GND_CPU_AVDD

2 OMIT

y
r

U2900

P1
P11
P13
P15
P17
P19
P21
P23
P3
P5
P7
P9
R10
R12
R14
R16
R18
R4
R6
R8
T1
T11
T13
T15
T17
T21
T23
T3
T5
T7
T9
U10
U12
U14
U16
U18
U2
U20
U22
U4
U6
U8
V1
V11
V13
V15
V17
V19
V3
V7
V9
W10
W12
W14
W16
W18
W2
W24
W6
W8
Y11
Y13
Y15
Y17
Y19
Y22
Y23
Y3
Y5
Y7
Y9
AA16
AA18
AA2
AA24
AA4
AA6
AB1
AB13
AB15
AB17
AB23
AB3
AB9
AC12
AC14
AC18
AC2
AC20
AC22
AC4
AC6
AC8
AD1
AD15
AD19
AD23
AD3
AD5
AD9

a
n
i

VCORE

R24

KPVDD2

OMIT

AGND

C3111
1UF

20%
6.3V
2 CERM
805

R2

Y1

KPVDD1

m
il

e
r

C3117 1 C3116 1 C3115

1
A1
A24
B11
B13
B16
B20
B3
B7
C2
C20
C24
D13
D17
D19
D21
D23
D5
D7
D9
E1
E10
E14
E16
E18
E22
E4
E6
E8
F11
F13
F15
F17
F19
F3
F5
F7
F9
G10
G12
G14
G16
G18
G22
G6
G8
H11
H13
H15
H17
H19
H24
H5
H7
H9
J1
J10
J12
J14
J16
J18
J2
J20
J4
J6
J8
K11
K13
K15
K17
K19
K21
K23
K5
K7
K9
L10
L12
L14
L16
L18
L20
L4
L6
L8
M1
M11
M13
M15
M17
M21
M23
M5
M7
M9
N10
N12
N14
N16
N18
N2
N20
N24
N4
N6
N8

1UF

20%
2 6.3V
CERM
805

GND

C3149

DIFFERENTIAL_PAIR=P_TDD
MIN_LINE_WIDTH=10MIL
TDIODE_POS 36
MIN_NECK_WIDTH=8MIL

PP2V5_RUN_CPU_AVDD_R_L

P24

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=2.5V

2
CPU_AVDD_2V6&CPU_AVDD_2V7&CPU_AVDD_2V8 1
CPU_AVDD_2V6&CPU_AVDD_2V7&CPU_AVDD_2V8
1
1

PP2V5_RUN_CPU_AVDD_R

VOLTAGE=2.5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

PP2V5_RUN_CPU_AVDD

VOUT

VIN

35

R3101

MM1572JN

NET_SPACING_TYPE=PROC_DIFF

60-OHM-EMI

5%
1/10W
MF-LF
603

OMIT

=PP5V_RUN_CPU

2.2

NEO-10S-REV2
1.8GHZ-76C

NOSTUFF

R3132

NEO-10S-REV2
1.8GHZ-76C

04

OF

31

102

D
36 31 29 7

y
r

=PPVCORE_CPU

C3222
1UF

10%
6.3V
2 CERM
402

C3293

1UF

10%
2 6.3V
CERM
402

C3294

1UF

10%
2 6.3V
CERM
402

C3296

10%
6.3V
2 CERM
402

C3297

1UF

10%
2 6.3V
CERM
402

C3298

C3299

1UF

C3202

1UF

C3283

10%
6.3V
2 CERM
402

C3203

10%
2 6.3V
CERM
402

C3292
1UF

10%
2 6.3V
CERM
402

C3261

10%
2 6.3V
CERM
402

C3264

1UF

10%
2 6.3V
CERM
402

C3266

10%
6.3V
2 CERM
402

C3276

1UF

10%
2 6.3V
CERM
402

C3277

C3279

1UF

C3280

1UF

C3275

C3290
1UF

10%
2 6.3V
CERM
402

C3235

1UF

10%
6.3V
2 CERM
402

1UF

10%
2 6.3V
CERM
402

C3236
1UF

10%
6.3V
2 CERM
402

C3239

C3240
1UF

10%
6.3V
2 CERM
402

C3252

10%
2 6.3V
CERM
402

C3253
1UF

10%
6.3V
2 CERM
402

C3257

10%
6.3V
2 CERM
402

C3237

10%
2 6.3V
CERM
402

C3238
1UF

10%
6.3V
2 CERM
402

C3250

C3251
1UF

10%
6.3V
2 CERM
402

C3254

C3226

10%
2 6.3V
CERM
402

C3258
1UF

10%
6.3V
2 CERM
402

C3288
1UF

10%
2 6.3V
CERM
402

C3255
1UF

10%
6.3V
2 CERM
402

C3287
1UF

10%
2 6.3V
CERM
402

C3227

1UF

10%
2 6.3V
CERM
402

C3231

10%
6.3V
2 CERM
402

10%
2 6.3V
CERM
402

C3244

C3245

10%
2 6.3V
CERM
402

C3256
1UF

10%
6.3V
2 CERM
402

C3289

1UF

C3201
1UF

10%
6.3V
2 CERM
402

C3223

a
n
i

1UF

10%
2 6.3V
CERM
402

C3234
1UF

10%
6.3V
2 CERM
402

1UF

10%
2 6.3V
CERM
402

C3200

10%
6.3V
2 CERM
402

1UF

C3242

10%
6.3V
2 CERM
402

C3248

1UF

10%
2 6.3V
CERM
402

C3246

C3267
1UF

10%
2 6.3V
CERM
402

C3278
1UF

10%
6.3V
2 CERM
402

1UF

C3247
1UF

10%
6.3V
2 CERM
402

10%
6.3V
2 CERM
402

C3286
1UF

10%
2 6.3V
CERM
402

C3285
1UF

10%
2 6.3V
CERM
402

C3206

1UF

10%
2 6.3V
CERM
402

C3207
1UF

10%
6.3V
2 CERM
402

1UF

10%
2 6.3V
CERM
402

C3249

1UF

1UF

10%
6.3V
2 CERM
402

C3241

10%
2 6.3V
CERM
402

1UF

10%
6.3V
2 CERM
402

m
il

C3243
1UF

C3229

C3212
1UF

1UF

1UF

10%
6.3V
2 CERM
402

C3228

10%
2 6.3V
CERM
402

1UF

C3225

10%
6.3V
2 CERM
402

C3230

1UF

1UF

10%
6.3V
2 CERM
402

C3224

10%
2 6.3V
CERM
402

1UF

C3215

10%
6.3V
2 CERM
402

1UF

1UF

10%
2 6.3V
CERM
402

1UF

10%
6.3V
2 CERM
402

1UF

10%
2 6.3V
CERM
402

C3216
1UF

1UF

1UF

10%
2 6.3V
CERM
402

C3233
1UF

1UF

10%
2 6.3V
CERM
402

C3232

1UF

1UF

10%
2 6.3V
CERM
402

C3217

e
r

10%
6.3V
2 CERM
402

C3291

1UF

1UF

10%
6.3V
2 CERM
402

10%
2 6.3V
CERM
402

C3274

10%
2 6.3V
CERM
402

1UF

C3273

10%
6.3V
2 CERM
402

10%
2 6.3V
CERM
402

10%
6.3V
2 CERM
402

1UF

1UF

10%
6.3V
2 CERM
402

C3272

10%
2 6.3V
CERM
402

1UF

C3263

C3218
1UF

1UF

1UF

10%
6.3V
2 CERM
402

C3262

10%
2 6.3V
CERM
402

1UF

C3260

10%
6.3V
2 CERM
402

C3265

1UF

1UF

10%
6.3V
2 CERM
402

C3259

10%
2 6.3V
CERM
402

1UF

C3219

10%
6.3V
2 CERM
402

1UF

1UF

1UF

10%
6.3V
2 CERM
402

C3284

10%
2 6.3V
CERM
402

1UF

C3281

10%
6.3V
2 CERM
402

10%
2 6.3V
CERM
402

1UF

10%
6.3V
2 CERM
402

1UF

1UF

10%
6.3V
2 CERM
402

C3282

10%
2 6.3V
CERM
402

1UF

C3270

C3220
1UF

1UF

1UF

10%
6.3V
2 CERM
402

C3271

10%
2 6.3V
CERM
402

1UF

C3269

10%
6.3V
2 CERM
402

C3295

1UF

1UF

10%
6.3V
2 CERM
402

C3268

10%
2 6.3V
CERM
402

1UF

C3221
1UF

10%
6.3V
2 CERM
402

C3210

1UF

10%
2 6.3V
CERM
402

C3211
1UF

10%
6.3V
2 CERM
402

C3214
1UF

10%
2 6.3V
CERM
402

C3205
1UF

10%
6.3V
2 CERM
402

1UF

10%
2 6.3V
CERM
402

C3204

C3208
1UF

10%
2 6.3V
CERM
402

C3209
1UF

10%
6.3V
2 CERM
402

C3213
1UF

10%
2 6.3V
CERM
402

MASTER: GILA
LAST MODIFIED: APR 09, 04

PROC DECOUPLING
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6772

32

OF

04
102

7
33 7

=PP12V_RUN_CPU

C3310

R3329

U3310_BST_R

33

C3319

R33901

1UF

8 6
8 6
8 6
8 6
8 6
8 6

5%
1/16W
MF-LF
402 2

U3300
14 VID0
13 VID1
12 VID2

CPU_VID_R<0>
CPU_VID_R<1>
CPU_VID_R<2>
CPU_VID_R<3>
CPU_VID_R<4>
CPU_VID_R<5>

11 VID3
10 VID4
15 VID5
3 OS1
2 OS2

SC2643_OS1
SC2643_OS2
SC2643_OS3
SC2643_OS4

1 OS3
24 OS4

0
5%
1/16W
MF-LF
2 402

SC2643_OSCREF

R3391

AUX2

33

AUX3

33

R3300

R3313
20.5K

GSENSE 6

C3300
0.1UF

20%
2 10V
CERM
402

NOSTUFF

AGND

C3304

R3314
0.0082UF
10%
25V
X7R
402

20.5K

1%
1/16W
MF-LF
2 402

C3305 R3315
20.5K
0.0082UF 1%

10%
25V
2 X7R
402

SYS_POWERUP_L

332K

1%
1/16W
MF-LF
2 402

SC2643_ERROUT

R3301
30K

5%
1/16W
MF-LF
2 402

33

34

SC2643_VCC

33

33

330PF

10%
50V
2 CERM
402

R3302
0

5%
1/16W
MF-LF
2 402

SC2643_AGND

SC2643_OS_HUB

1%
1/16W
MF-LF
402

R3304

DIFFERENTIAL PAIR

FOR REMOTE SENSE

261

0.068UF

U3320_BST_R

VCORE_SENSE_VOUT

33

6 33

PP12V_CPU

OUT2

OMIT

XW3300
SM
1

301

NOSTUFF

R3324
330

NOSTUFF

5%
1/16W
MF-LF
2 402

R3325

1K

e
r

R3325_2

5%
1/16W
MF-LF
402

PLACE R3325 CLOSE TO INDUCTOR OUTPUT LEAD.


NOSTUFF

C3309
0.015UF
SC2643_OUTSEN

P
10% 16V
X7R 402

R3327
1

1.5K 2

SC2643_OUTSEN_R

1%
1/16W
MF-LF
402

35 34 33 7 6

PPVCORE_CPU

MIN_LINE_WIDTH=10MIL

MIN_NECK_WIDTH=8MIL
UNDER PROCESSOR

R3336
1

5%
1/16W
MF-LF
402

R3337

R3339

FAR SIDE

KPGND2

R3342
1

NOSTUFF

36 31 6

PPVCORE_CPU

6 33

DIFFERENTIAL_PAIR=P_SENSE_CORE

MIN_NECK_WIDTH=8MIL
NET_SPACING_TYPE=PROC_DIFF

VCORE_SENSE_GND

6 33

DIFFERENTIAL_PAIR=P_SENSE_CORE
MIN_LINE_WIDTH=10MIL

2.2

U3320_BST

3 BST

PLACE NEXT TO SMU

35 34 33 7 6

PPVCORE_CPU

R3360
10K

R3308
1

100K 2

CPU_SENSE_V 13

5%
1/16W
MF-LF
402

C3321

VPN 5

GND_SMU_AVSS

2 CERM
1210

VPN2

CASE369

C3328

1800UF

20%
2 6.3V
ELEC
TH-KZJ

C3325

0.0022UF

0.001UF

1800UF

20%
2 6.3V
ELEC
TH-KZJ

R3321
1

5%
1/8W
MF-LF
2 805

C3326_1
1

C3326

0.0047UF

10%
25V
2 CERM
402

33

PN2

CRITICAL

L3300

33 7

PP12V_CPU

R3343

=PP12V_RUN_CPU 1UH-20A-4.5MOHM

TH-VERT

1%
1W
MF
2512

6 33 34

VOLTAGE=12V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

0.0252

2 PP12V_CPU_R

CURRENT SENSE

KEEP SHORTS NEXT TO U3301


PLACE R3344 AND C3331 BY SMU
OMIT

VIN+ VINSOT23-5

OUT

CORE_ISNS_P

R3344
CPU_SENSE_I_R

R3345

100K 2

SCALE

COUNT

2.73224 A/V

.00675 A/COUNT

CPU_SENSE_I 13

CPU VREG
NOTICE OF PROPRIETARY PROPERTY

ADC IS 10BIT 0 TO 1023


0 TO 2.5V

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

C3331

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

20%
2 6.3V
CERM
805

1%
1/16W
MF-LF
2 402

OMIT

GND_SMU_AVSS

XW3301
SM
2

CORE_ISNS_M

II NOT TO REPRODUCE OR COPY IT


III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
8 13 33 36

APPLE COMPUTER INC.

6 36

DRAWING NUMBER

SHT
NONE

REV.

051-6772

D
SCALE

SOT23

10UF

73.2K

5%
1/16W
MF-LF
402

D3300
BAS16

OMIT
1

3 NOSTUFF

6 36

XW3303
SM

INA138
V+

INA138_OUT

U3301
5

=PP3V3_RUN_CPU

XW3304
SM

GND

CASE369

20%
50V
2 CERM
402

5%
1/16W
MF-LF
402

6 7 33 34 35

C3333

CRITICAL

NTD70N03R

10%
50V
2 CERM
402

C3324

PPVCORE_CPU

2
TH1

NOSTUFF

AUX2

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

5%
1/16W
MF-LF
2 402

PN2

Q3321
U3320_BG

100

6 7 33 34 35

L3320

0.6UH-24A
33

R3322

33

NTD60N02R
S 3

5%
1/16W
MF-LF
2 402

.01464 V/COUNT

ADC IS 10BIT 0 TO 1023


0 TO 2.5V

Q3320
1
G

5%
1/16W
MF-LF
402

U3320_VREG

C3323

CRITICAL

10K

COUNT

6 V/V
D 4

8 13 33 36

10%
16V

20%
16V
ELEC
TH-KZJ

R3351

R3320

20%
6.3V
2 CERM
805

1%
1/16W
MF-LF
2 402

C3322

C3303
10UF

2.0K

SCALE

R3361

10UF

1000UF
2

1%
1/16W
MF-LF
2 402

NOSTUFF

PP12V_CPU

THMPAD

SOT23

5%
1/16W
MF-LF
402

VOLTAGE SENSE
PP12V_CPU

34 33 6

U3320_TG

TG 2

1UF

R3341

KPVDD2
CPU SENSE SIDE

0.0047UF

VREG 7

1 DRN

20%
2 16V
CERM
1206

NOSTUFF

5%
1/16W
MF-LF
402
36 31 6

5%
1/16W
MF-LF
402

R3340
1

NOSTUFF

4 CO

D3320
BAS16

C3316

BG 8

MIN_NECK_WIDTH=8MIL
NET_SPACING_TYPE=PROC_DIFF

NOSTUFF

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

R3338
1

NOSTUFF
NEAR SIDE

VCORE_SENSE_VOUT
MIN_LINE_WIDTH=10MIL

5%
1/16W
MF-LF
402
NOSTUFF

XW3302
SM

SOIC

20%
2 6.3V
ELEC
TH-KZJ

10%
2 25V
CERM
402

SC1211

6 VIN

CONNECT BETWEEN THE INDUCTOR & BULK CAPS.

PLACE REGULATOR SENSE POINTS AT DESIGNATED LOCATIONS.

R3335

OMIT

20%
16V
2 CERM
1206

U3320

5%
1/10W
MF-LF
603

1UF

1%
1/16W
MF-LF
402

C3330

C3332
1800UF

20%
2 6.3V
ELEC
TH-KZJ

C3316_1

U3320_DRN

R3306

R3326

20%
16V
CERM
1206

m
il

6 33

10%
10V
CERM
402

34 33 6

1UF

33

34 33 6

1%
1/16W
MF-LF
402

C3308
1

SC2643_AGND

PN1

C3317
1800UF

20%
2 6.3V
ELEC
TH-KZJ

5%
1/8W
MF-LF
2 805

10%
50V
2 CERM
402

C3320

1800UF

0.0022UF

0.001UF

C3318

R3311

CASE369

C3315

20%
50V
2 CERM
402

6 7 33 34 35

CRITICAL
1

NTD70N03R

NOSTUFF

C3314

PPVCORE_CPU

TH1

CRITICAL

Q3311

AUX1

NOSTUFF

C3302

U3310_BG

33

a
n
i

1UF

5%
1/10W
MF-LF
603

R3305

33

5%
1/16W
MF-LF
402

PN1

33

MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL

2 402

5%
1/16W
MF-LF
2 402

C3313

20%
16V
2 CERM
1206

1%
1/16W
MF-LF
2 402

4.99K2

100

2.7M 2

0.6UH-24A

5%
1/16W
MF-LF

R3310

R3312

0.0082UF

10K

33

CRITICAL

L3310

R3350

VPN1

10%
2 6.3V
CERM
402

CASE369

S3

6 7 10 11 13

R3303

C3306 R3318
20.5K

10%
25V
2 X7R
402

1/16W
MF-LF
2 402

SC2643_VCC

NTD60N02R

1
G

y
r

VPN 5
THMPAD

1UF

VCORE_SENSE_GND

33

NOSTUFF

3 BST

SOT23

NOSTUFF

C3301

SC2643_AGND

18

1%
1/16W
MF-LF
2 402

NOSTUFF

R3328

20.5K

1%
1/16W
MF-LF
2 402

2N7002

S
1

R3317

20.5K

1%
1/16W
MF-LF
2 402

U3310_BST

Q3310

D3310
BAS16

D SOT23-LF

SC2643_DACSTEP

1210

D 4 CRITICAL

U3310_TG

TG 2

U3310_VREG

R3316

1 DRN

Q3312

10%
16V

2 CERM

BG 8

VREG 7

5%
1/10W
MF-LF
603

VRM_EN

5%
1/16W
MF-LF
402

C3302_1

20%
2 16V
CERM
1206

34

FB 7

SC2643_AGND
AUX1

C3329 R3307
2.2
1UF

33

1.5K 2

SOIC

4 CO
1

SC2643_PGOOD

DACSTEP 8

OUT1

33

C3312
10UF

20%
16V
ELEC
TH-KZJ

U3310

PP12V_CPU

6 VIN

ERROUT 5

17 OSCREF

SC1211

U3300_BGOUT

CRITICAL
1

C3311
1000UF

25 27
34 33 6

OUT4

BGOUT 4

23 OUTSEN
1

OUT1
OUT2
OUT3

OUT4 22

PGOOD 16

SYS_SLEWING_L 13

33

OUT1 19
OUT2 20
OUT3 21

TSSOP

SC2643VX

U3310_DRN

5%
1/16W
MF-LF
402

9
VCC

20%
16V
2 CERM
1206

SC2643_AGND

PP12V_CPU

20%
16V
CERM
1206

R3330

CRITICAL

5%
1/16W
MF-LF
2 402

33

34 33 6

1UF
SC2643_VCC

10

33

OF

04
102

PP12V_CPU

C3410

1UF
U3410_BST_R

C3411

1000UF

2
2

20%
16V
CERM
1206

20%
16V
ELEC
TH-KZJ

C3412
1000UF

C3422

20%
16V
ELEC
TH-KZJ

6 33 34

PPVCORE_CPU

35 34 33 7 6

C3468
10%
16V

EXTRA_C

2 CERM
1

1210

20%
6.3V
2 CERM
1206

U3410

33

SC1211

PP12V_CPU

6 VIN

OUT3

SOIC

4 CO

R3423
1
1

C3470

U3410_BST

TG 2

3 BST

VPN 5

R3410
1

U3410_VREG
VPN3

100
1

5%
1/16W
MF-LF
2 402

C3413
1UF

20%
16V
2 CERM
1206

33

AUX3

34

PN3

TH1

CASE369

NOSTUFF

C3415

20%
2 6.3V
CERM
1206

EXTRA_C
1

C3429
10UF

20%
6.3V
2 CERM
1206

10%
2 50V
CERM
402

C3418
1800UF

20%
2 6.3V
ELEC
TH-KZJ

C3472
1800UF

20%
2 6.3V
ELEC
TH-KZJ

C3473
1800UF

C3427

1800UF

20%
2 6.3V
ELEC
TH-KZJ

20%
2 6.3V
ELEC
TH-KZJ

C3474

C3475

1800UF

20%
2 6.3V
ELEC
TH-KZJ

1800UF

R3411
1

5%
1/8W
MF-LF
2 805

PP3V3_RUN

330

5%
1/16W
MF-LF
2 402

0.0047UF

LED_CPU_CORE_P

DEVELOPMENT

PN3

R3491
1

GREEN
2.0X1.25A

LM339A

V+

5%
1/16W
MF-LF
402

U1001

50 22 10

1V1_REF

DEVELOPMENT

LED3400

DEVELOPMENT

CPU_CORE_FOR_LED

SOI

14

C3444

20%
6.3V
2 CERM
1206

10UF

20%
6.3V
2 CERM
1206

C3437
10UF

20%
2 6.3V
CERM
1206

LED_CPU_CORE_N

GND

PLACE LED3400 NEAR VREG

C3445
10UF

10UF

20%
2 6.3V
CERM
1206

20%
6.3V
2 CERM
1206

20%
6.3V
2 CERM
1206

10UF

20%
2 6.3V
CERM
1206

C3446
10UF

20%
6.3V
2 CERM
1206

10UF

20%
6.3V
2 CERM
1206

EXTRA_C

C3455
10UF

20%
2 6.3V
CERM
1206

C3442

20%
6.3V
2 CERM
1206

C3435
10UF

20%
2 6.3V
CERM
1206

C3449
10UF

20%
2 6.3V
CERM
1206

C3460
10UF

20%
6.3V
2 CERM
1206

C3436
10UF

20%
6.3V
2 CERM
1206

C3465
10UF

20%
2 6.3V
CERM
1206

EXTRA_C
1

C3466
10UF

20%
6.3V
2 CERM
1206

C3439
10UF

20%
2 6.3V
CERM
1206

10UF

EXTRA_C
1

C3401
10UF

C3440
10UF

20%
6.3V
2 CERM
1206

20%
2 6.3V
CERM
1206

EXTRA_C

C3402
10UF

20%
6.3V
2 CERM
1206

C3447
10UF

20%
2 6.3V
CERM
1206

C3400
10UF

20%
6.3V
2 CERM
1206

EXTRA_C
1

C3467
10UF

20%
2 6.3V
CERM
1206

EXTRA_C
1

C3464

20%
6.3V
2 CERM
1206

EXTRA_C
1

C3463
10UF

20%
2 6.3V
CERM
1206

EXTRA_C

EXTRA_C

C3462

EXTRA_C
1

EXTRA_C

C3441

C3459

20%
6.3V
2 CERM
1206

10UF

EXTRA_C

10UF

20%
2 6.3V
CERM
1206

EXTRA_C

C3438
10UF

C3430
10UF

EXTRA_C

EXTRA_C

6 7 10 11 18 22 50

DEVELOPMENT

C3416

20%
2 6.3V
CERM
1206

10UF

R3490

10UF

C3416_1

C3432

EXTRA_C

20%
2 6.3V
ELEC
TH-KZJ

a
n
i

10%
2 25V
CERM
402

C3414

C3443

EXTRA_C

C3461

EXTRA_C
1

y
r

6 7 33 34 35

CRITICAL

20%
50V
2 CERM
402
34

C3417

20%
2 6.3V
ELEC
TH-KZJ

NTD70N03R

G
S

0.001UF

1800UF

Q3411

PPVCORE_CPU

U3410_BG

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

5%
1/16W
MF-LF
402

0.0022UF

C3431
10UF

EXTRA_C

L3410

0.6UH-24A

5%
1/16W
MF-LF
2 402

R3412

CASE369
S3

R3450
10K

SOT23

NTD60N02R

1
G
1

THMPAD

D3410
BAS16

20%
6.3V
2 CERM
1206

Q3410
U3410_TG

C3434
10UF

D 4 CRITICAL

VREG 7

EXTRA_C
1

EXTRA_C
BG 8

1 DRN

5%
1/10W
MF-LF
603

1UF

20%
2 16V
CERM
1206

2.2

C3433
10UF

U3410_DRN

34 33 6

10UF

1000UF

20%
16V
ELEC
TH-KZJ

EXTRA_C

C3405
10UF

C3403
10UF

20%
2 6.3V
CERM
1206

20%
2 6.3V
CERM
1206

12

m
il

EXTRA_C
1

C3456
10UF

20%
6.3V
2 CERM
1206

EXTRA_C
1

C3450
10UF

20%
6.3V
2 CERM
1206

EXTRA_C
1

10UF

20%
6.3V
2 CERM
1206

EXTRA_C
1

C3457
10UF

20%
2 6.3V
CERM
1206

C3448

10UF

20%
6.3V
2 CERM
1206

EXTRA_C
1

C3453
10UF

20%
2 6.3V
CERM
1206

C3451
10UF

20%
2 6.3V
CERM
1206

C3406

10UF

EXTRA_C
1

C3404

20%
6.3V
2 CERM
1206

EXTRA_C

C3409
10UF

C3407
10UF

20%
2 6.3V
CERM
1206

20%
2 6.3V
CERM
1206

EXTRA_C
1

C3458
10UF

20%
6.3V
2 CERM
1206

C3454
10UF

20%
6.3V
2 CERM
1206

C3452
10UF

20%
6.3V
2 CERM
1206

C3419
10UF

20%
6.3V
2 CERM
1206

C3408
10UF

20%
6.3V
2 CERM
1206

e
r

CPU VREG
A

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6772

34

OF

04
102

D
35 34 33 7 6

PPVCORE_CPU
CRITICAL
EXTRA_C
1

C3500
10UF

20%
6.3V
2 CERM
1206

EXTRA_C
1

C3512
10UF

20%
6.3V
2 CERM
1206

EXTRA_C
1

C3523
10UF

20%
6.3V
2 CERM
1206

EXTRA_C
1

10UF

20%
6.3V
2 CERM
1206

EXTRA_C
1

C3513
10UF

PPVCORE_CPU

DS3502
SMB

6 7 33 34 35

20%
2 6.3V
CERM
1206

PP2V5_RUN_CPU_AVDD_R

C3524
10UF

10BQ040PBF

20%
6.3V
2 CERM
1206

10UF

20%
2 6.3V
CERM
1206

C3510
10UF

20%
2 6.3V
CERM
1206

C3535
10UF

20%
2 6.3V
CERM
1206

20%
2 6.3V
CERM
1206

C3522
10UF

C3546
10UF

20%
6.3V
2 CERM
1206

20%
6.3V
2 CERM
1206

20%
6.3V
2 CERM
1206

EXTRA_C

C3533
10UF

20%
2 6.3V
CERM
1206

C3521
10UF

C3557
10UF

20%
2 6.3V
CERM
1206

m
il
1

C3568
10UF

20%
6.3V
2 CERM
1206

C3579
10UF

20%
2 6.3V
CERM
1206

C3532
10UF

20%
2 6.3V
CERM
1206

C3544
10UF

20%
6.3V
2 CERM
1206

e
r

C3555
10UF

20%
2 6.3V
CERM
1206

20%
6.3V
2 CERM
1206

C3590
10UF

20%
6.3V
2 CERM
1206

C3566
10UF

20%
6.3V
2 CERM
1206

C3577
10UF

20%
2 6.3V
CERM
1206

C3502
10UF

20%
2 6.3V
CERM
1206

C3520
10UF

20%
6.3V
2 CERM
1206

20%
2 6.3V
CERM
1206

C3501
10UF

20%
6.3V
2 CERM
1206

C3507
10UF

20%
2 6.3V
CERM
1206

EXTRA_C

C3554
10UF

20%
2 6.3V
CERM
1206

10UF

20%
6.3V
2 CERM
1206

C3531
10UF

20%
2 6.3V
CERM
1206

C3565
10UF

20%
6.3V
2 CERM
1206

20%
2 6.3V
CERM
1206

C3576
10UF

20%
2 6.3V
CERM
1206

C3542
10UF

20%
6.3V
2 CERM
1206

C3541
10UF

20%
6.3V
2 CERM
1206

20%
6.3V
2 CERM
1206

C3588
10UF

20%
6.3V
2 CERM
1206

10UF

20%
6.3V
2 CERM
1206

EXTRA_C
1

C3599
10UF

20%
2 6.3V
CERM
1206

C3587

10UF

20%
2 6.3V
CERM
1206

C3598
10UF

20%
2 6.3V
CERM
1206

C3540
10UF

20%
6.3V
2 CERM
1206

20%
6.3V
2 CERM
1206

C3553
10UF

20%
2 6.3V
CERM
1206

C3552
10UF

20%
2 6.3V
CERM
1206

10UF

20%
2 6.3V
CERM
1206

EXTRA_C

C3564
10UF

20%
6.3V
2 CERM
1206

C3575
10UF

20%
2 6.3V
CERM
1206

C3563
10UF

20%
6.3V
2 CERM
1206

C3574
10UF

20%
2 6.3V
CERM
1206

10UF

20%
2 6.3V
CERM
1206

C3586
10UF

20%
6.3V
2 CERM
1206

C3585
10UF

20%
6.3V
2 CERM
1206

10UF

20%
6.3V
2 CERM
1206

20%
6.3V
2 CERM
1206

EXTRA_C

C3505
10UF

20%
2 6.3V
CERM
1206

C3517
10UF

20%
6.3V
2 CERM
1206

10UF

20%
6.3V
2 CERM
1206

EXTRA_C

C3528
10UF

20%
2 6.3V
CERM
1206

C3516

C3539
10UF

20%
6.3V
2 CERM
1206

C3527
10UF

20%
2 6.3V
CERM
1206

C3550
10UF

20%
2 6.3V
CERM
1206

C3538
10UF

20%
6.3V
2 CERM
1206

C3504
10UF

10UF

EXTRA_C
1

C3549
10UF

20%
2 6.3V
CERM
1206

20%
2 6.3V
CERM
1206

EXTRA_C

C3515
10UF

20%
6.3V
2 CERM
1206

10UF

EXTRA_C

C3526
10UF

20%
2 6.3V
CERM
1206

EXTRA_C

C3537
10UF

20%
6.3V
2 CERM
1206

EXTRA_C
1

C3597
10UF

20%
2 6.3V
CERM
1206

C3596
10UF

20%
2 6.3V
CERM
1206

C3536
10UF

20%
6.3V
2 CERM
1206

EXTRA_C
1

C3525
10UF

20%
2 6.3V
CERM
1206

C3514

20%
6.3V
2 CERM
1206

C3548
10UF

EXTRA_C
1

C3547
10UF

20%
2 6.3V
CERM
1206

20%
2 6.3V
CERM
1206

C3562
10UF

20%
6.3V
2 CERM
1206

10UF

20%
6.3V
2 CERM
1206

EXTRA_C

C3573
10UF

20%
2 6.3V
CERM
1206

C3584
10UF

20%
6.3V
2 CERM
1206

C3561

C3560
10UF

20%
6.3V
2 CERM
1206

10UF

20%
6.3V
2 CERM
1206

EXTRA_C
1

C3572
10UF

20%
2 6.3V
CERM
1206

C3583
10UF

20%
6.3V
2 CERM
1206

C3571
10UF

20%
2 6.3V
CERM
1206

C3582
10UF

20%
6.3V
2 CERM
1206

C3570
10UF

10UF

EXTRA_C
1

C3595
10UF

20%
2 6.3V
CERM
1206

C3569
10UF

20%
2 6.3V
CERM
1206

EXTRA_C
1

C3558

20%
6.3V
2 CERM
1206

EXTRA_C
1

EXTRA_C
1

C3559

20%
2 6.3V
CERM
1206

EXTRA_C
1

C3581
10UF

20%
6.3V
2 CERM
1206

C3580
10UF

20%
6.3V
2 CERM
1206

EXTRA_C
1

C3503
10UF

20%
2 6.3V
CERM
1206

EXTRA_C
1

C3556

20%
6.3V
2 CERM
1206

EXTRA_C

EXTRA_C
1

EXTRA_C

EXTRA_C

EXTRA_C

C3567
10UF

EXTRA_C

EXTRA_C
1

C3506

C3578

EXTRA_C

EXTRA_C

C3551

EXTRA_C

EXTRA_C

EXTRA_C
1

C3529

C3589
10UF

EXTRA_C

EXTRA_C
1

C3518
10UF

EXTRA_C

EXTRA_C

C3530
10UF

EXTRA_C

C3519

EXTRA_C

EXTRA_C
1

EXTRA_C

EXTRA_C

EXTRA_C

10UF

EXTRA_C

EXTRA_C

C3543
10UF

EXTRA_C

C3508

y
r

EXTRA_C
1

EXTRA_C
1

EXTRA_C

EXTRA_C

20%
6.3V
2 CERM
1206

EXTRA_C

EXTRA_C

C3509
10UF

EXTRA_C

EXTRA_C
1

C3511

C3545
10UF

EXTRA_C
1

EXTRA_C
1

EXTRA_C
1

a
n
i

31

C3534

EXTRA_C
1

C3594
10UF

20%
2 6.3V
CERM
1206

C3593
10UF

20%
2 6.3V
CERM
1206

C3592
10UF

C3591
10UF

20%
2 6.3V
CERM
1206

20%
2 6.3V
CERM
1206

CPU VREG OUTPUT CAPS

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6772

35

OF

04
102

NOSTUFF
7

=PP5V_PWRON_CPU

DS3602
SOD-123
1

B0530WXF

=PP5V_ALL_CPU

R3602

D
MIN_LINE_WIDTH=15MIL

C3603 1 C3604

2.2UF

2.2UF

20%
10V
2 CERM
805

XW3601
SM
1

DAVDD

36

DAGND

36

MIN_NECK_WIDTH=10MIL

C3605

2.2UF

y
r

C3600
2.2UF

20%
10V
2 CERM
805

20%
10V
2 CERM
805

20%
10V
2 CERM
805

MIN_LINE_WIDTH=15MIL

OMIT

MIN_NECK_WIDTH=10MIL

XW3600, R3602, AND DS3602 MUST BE PLACED CLOSE TO SMU

100UA CURRENT SOURCE

R3606
36

10.0K2

DAGND 1

0.1%
1/16W
MF-LF
603

THESE SIGNALS HAVE A MIN_LINE_WIDTH=10MIL


AND MIN_NECK_WIDTH=8MIL

a
n
i

R3603
10.0K

2 TD_CURRENT
TD11
10MIL 0.1%
8MIL 1/16W
MF-LF
603
36

DAVDD

U3601

5 LMV2011
SOT23-5

36

20.0K2

TD23

ADC_REF 1

0.1%
1/16W
MF-LF
603

BUFFER

R3604

R3608

DAGND

12.7K

36

36

DAVDD

U3602

5 LMV2011
SOT23-5

1%
1/10W
MF-LF
2 603

1
3

R3607
36

20.0K2

DAGND 1

0.1%
1/16W
MF-LF
603

R3605

DAGND
TD_BUFFERED

10.0K2

1
10MIL

8MIL

36

MIN_LINE_WIDTH=10MIL
0.1%
1/16W
MF-LF
603

C3607

MIN_NECK_WIDTH=8MIL

10UF
1

R3609
10.0K2
1

R3611
100K 2
1

TD3

m
il

20%
6.3V
CERM
805

10MIL
0.1%
1/16W
MF-LF
603

36

TDIODE_POS
1

C3610

0.0022UF

36 31 6

R3610

1K

0.0022UF

1%
1/16W
MF-LF
2 402

DAVDD

U3603
5 LMV2011
1

R3615
0

e
r
2

DAGND

R3613
36

40.2K2

ADC_REF 1

0.1%
1/16W
MF-LF
603

10MIL

8MIL

100K 2
0.1%
1/16W
MF-LF
603

ADC_REF

C3608
10UF
2

20%
6.3V
CERM
805

J3600

BM12B-SRSS-TB
F-ST-SM
14

P
6

1
2
3
4
5
6

7
8
9
10
11
12

13

36

R3614

TD4

NOSTUFF

CPU_TEMP_R

0.1%
1/16W
MF-LF
603

5%
1/16W
MF-LF
2 402

R3628

SOT23-5

10.0K2
1

TDIODE_NEG

36

0.1%
1/16W
MF-LF
603

R3616

10%
2 50V
CERM
402

10%
2 50V
CERM
402

40.2K2

DAGND 1

1NOSTUFF

C3606

NEED TO CONNECT TO P65 OF 80PIN SMU OR PIN 49 OF 64PIN SMU

R3612

32 31 29 7 =PPVCORE_CPU
36 31

0.1%
1/16W
MF-LF
603

8MIL

CPU_TEMP

B0530WXF
2

PP3V3_CPU_DIODE
MIN_LINE_WIDTH=25MIL

MIN_NECK_WIDTH=10MIL

R3601
200

MIN_NECK_WIDTH=8MIL

36

10UF

2.2UF

20%
10V
2 CERM
805

ADC_REF
MIN_LINE_WIDTH=10MIL

R3690

PPVREF_SMU_ADC_REF 1

8 13 33

5%
1/16W
MF-LF
402

6
VREF

U3650

ADJ 5

NC

NCV1009D
SO-8

NC1
NC2
NC3
NC4
NC5

1
2
3
7
8

NOSTUFF

D3600
2.5V
SSOT-23

NOSTUFF

R3691
8

GND_SMU_AVSS_DAGND 1

GND
4

C3602
0.47UF

20%
10V
2 CERM
603

DAGND

5%
1/16W
MF-LF
402

KPVDD2

NOSTUFF

R3620

6 31 33

OMIT

XW3612
SM
1

KPGND2

36 13

CPU_TEMP

6 31 33

OMIT

XW3613
SM
1

TDIODE_POS_FMAX
DIFFERENTIAL_PAIR=TDIODE
MIN_LINE_WIDTH=10MIL
MIN_NECK_WIDTH=8MIL
NET_SPACING_TYPE=PROC_DIFF

FMAXT_P
DIFFERENTIAL_PAIR=P_FMAXT

NOSTUFF

NET_SPACING_TYPE=PROC_DIFF

TDIODE_POS 31

36

36

DAGND

51

5%
1/16W
MF-LF
402

TDIODE_NEG 6

R3619
0

5%
1/8W
MF-LF
2 805

R3621

OMIT

NOSTUFF

XW3614
SM

TDIODE_NEG_FMAX
DIFFERENTIAL_PAIR=TDIODE
MIN_LINE_WIDTH=10MIL
MIN_NECK_WIDTH=8MIL
NET_SPACING_TYPE=PROC_DIFF

51

5%
1/16W
MF-LF
402

FMAXT_M
DIFFERENTIAL_PAIR=P_FMAXT

NET_SPACING_TYPE=PROC_DIFF

CPU DIODE CONDITIONER

PLACE AT BOARD EDGE

31 36

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

6 33

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
6 33

SIZE

DRAWING NUMBER

SHT
NONE

REV.

051-6772

SCALE

36

NEEDED FOR FMAX

APPLE COMPUTER INC.

C3601

MIN_NECK_WIDTH=8MIL

20%
2 6.3V
CERM
805

GND_SMU_AVSS

DS3650
SOD-123

5%
1/10W
MF-LF
2 603

13 36

C3613

1 NOSTUFF

MIN_LINE_WIDTH=10MIL

=PP3V3_PWRON_CPU

R3650

XW3611
SM

KPGND2_FMAX
DIFFERENTIAL_PAIR=KP2_FMAX
MIN_LINE_WIDTH=10MIL
MIN_NECK_WIDTH=8MIL
NET_SPACING_TYPE=PROC_DIFF

CORE_ISNS_P
DIFFERENTIAL_PAIR=CORE_ISNS
MIN_LINE_WIDTH=10MIL
MIN_NECK_WIDTH=8MIL
NET_SPACING_TYPE=PROC_DIFF

5%
1/16W
MF-LF
402

=PP3V3_ALL_CPU
1

1%
1/10W
MF-LF
2 603

PLACE CLOSE
TO U2900
OMIT

KPVDD2_FMAX
DIFFERENTIAL_PAIR=KP2_FMAX
MIN_LINE_WIDTH=10MIL
MIN_NECK_WIDTH=8MIL
NET_SPACING_TYPE=PROC_DIFF

CORE_ISNS_M
DIFFERENTIAL_PAIR=CORE_ISNS
MIN_LINE_WIDTH=10MIL
MIN_NECK_WIDTH=8MIL
NET_SPACING_TYPE=PROC_DIFF

36

100K 2
1

POWER MONITOR

5%
1/10W
MF-LF
603

04

OF

36

102

1
U3TWINS DO NOT HAVE MASKS

=PP2V5_PWRON_RAM

R3702
PP1V5_PWRON_RAM_NB_AVDD

38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38

38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38

38
38
38
38
38
38
38
38
38
38
38

=PP2V5_PWRON_RAM

C3700
0.1UF

20%
10V
2 CERM
402

DDR_DQ64 AG27
DDR_DQ65 AF24
DDR_DQ66 AE24
DDR_DQ67 AG26

OMIT

AB20 DDR_DQ4
AC21 DDR_DQ5
AD23 DDR_DQ6

DDR_DQ68 AF26
DDR_DQ69 AD24
DDR_DQ70 AD25

MEMORY
DATA
INTERFACE

AD21 DDR_DQ7
AH26 DDR_DQ8
AH25 DDR_DQ9

DDR_DQ71 AG28
DDR_DQ72 AF28
DDR_DQ73 AE28

AH24 DDR_DQ10
AH23 DDR_DQ11
AH27 DDR_DQ12

DDR_DQ74 AD26
DDR_DQ75 AF27
DDR_DQ76 AC26

AG24 DDR_DQ13
AF23 DDR_DQ14
AH28 DDR_DQ15
U25 DDR_DQ16
AA23 DDR_DQ17

DDR_DQ77 AC25
DDR_DQ78 AC27

Y22 DDR_DQ18
AA22 DDR_DQ19
U24 DDR_DQ20

DDR_DQ82 AA24
DDR_DQ83 AA28
DDR_DQ84 Y26

DDR_DQ79 AD27
DDR_DQ80 AA27
DDR_DQ81 AA26

V23 DDR_DQ21
V22 DDR_DQ22
U22 DDR_DQ23

DDR_DQ85 Y25
DDR_DQ86 Y28
DDR_DQ87 Y24

P25 DDR_DQ24
R22 DDR_DQ25
R21 DDR_DQ26
U23 DDR_DQ27
P26 DDR_DQ28

DDR_DQ88 V26
DDR_DQ89 V27

R24 DDR_DQ29
P24 DDR_DQ30
P23 DDR_DQ31

DDR_DQ93 V28
DDR_DQ94 T28
DDR_DQ95 U26

M25 DDR_DQ32
M23 DDR_DQ33
P21 DDR_DQ34

DDR_DQ96 R27
DDR_DQ97 R26
DDR_DQ98 R28

P22 DDR_DQ35
M24 DDR_DQ36
L22 DDR_DQ37
L23 DDR_DQ38
J23 DDR_DQ39

DDR_DQ99 P27
DDR_DQ100 M28
DDR_DQ101 N28
DDR_DQ102 L28
DDR_DQ103 P28

D23 DDR_DQ40
D24 DDR_DQ41
C26 DDR_DQ42

DDR_DQ104 L25
DDR_DQ105 L26
DDR_DQ106 L27

C27 DDR_DQ43
A22 DDR_DQ44
A25 DDR_DQ45

DDR_DQ107 K28
DDR_DQ108 H27
DDR_DQ109 H28

C24 DDR_DQ46
C23 DDR_DQ47
B24 DDR_DQ48
B23 DDR_DQ49
A23 DDR_DQ50

DDR_DQ110 J27
DDR_DQ111 L24

A24 DDR_DQ51
A27 DDR_DQ52
A28 DDR_DQ53

DDR_DQ115 G28
DDR_DQ116 H25
DDR_DQ117 H24

B28 DDR_DQ54
A26 DDR_DQ55
F24 DDR_DQ56

DDR_DQ118 F27
DDR_DQ119 H26
DDR_DQ120 E28

J22 DDR_DQ57
E23 DDR_DQ58
H23 DDR_DQ59
J21 DDR_DQ60
H21 DDR_DQ61

DDR_DQ121 E27
DDR_DQ122 F26

DDR_DQ90 V24
DDR_DQ91 W28
DDR_DQ92 U27

DDR_DQ112 J25
DDR_DQ113 J24
DDR_DQ114 J26

0.1UF

G21 DDR_DQ62
H22 DDR_DQ63

20%
10V
2 CERM
402

C3702
0.1UF

20%
10V
2 CERM
402

C3703
0.1UF

20%
10V
2 CERM
402

P
DDR_DQ126 E25
DDR_DQ127 E24

C3704
0.1UF

20%
10V
2 CERM
402

C3705
0.1UF

20%
10V
2 CERM
402

38

DDR
CLK_AVDD

38

C3706
0.1UF

20%
10V
2 CERM
402

C3707
0.1UF

20%
10V
2 CERM
402

B25

D22
D27

F19

K27
G25

K19
K23

20%
2 10V
CERM
402

VDD_DDR

U3

38
38

27

38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38

AC20 DDR_CLKP

RAM_CLK_A_P_R
RAM_CLK_A_N_R
RAM_CLK_B_P_R
RAM_CLK_B_N_R
RAM_CLK_C_P_R
RAM_CLK_C_N_R
RAM_CLK_D_P_R
RAM_CLK_D_N_R
RAM_CLK_E_P_R
RAM_CLK_E_N_R
RAM_CLK_F_P_R
RAM_CLK_F_N_R

AA12 DDR_CK_A
AB12 DDR_CK_AN
AB14 DDR_CK_B
AA14 DDR_CK_BN

RAM_CKE_R<0>
RAM_CKE_R<1>
RAM_CKE_R<2>
RAM_CKE_R<3>
RAM_CKE_R<4>
RAM_CKE_R<5>
RAM_CKE_R<6>
RAM_CKE_R<7>

AC17 DDR_CKE0
AD17 DDR_CKE1
AE17 DDR_CKE2

38
38
38
38
8
38
8
38
38
38
38
38
8
38
8
38
38

=PP2V5_PWRON_RAM

7 26 37 40 46

38
38

R37001

38

1K

1%
1/16W
MF-LF
402 2

38
38
38

1K

38

38
38
38
38
38
38
38
38
38

0.1UF

1%
1/16W
MF-LF
402 2

38

C3730

C3746

0.1UF

38
38
38
38
38
38
38
38
38
38
38
38
38
38

38

RAM_BA_R<0>
RAM_BA_R<1>
RAM_MUXEN0
RAM_MUXEN4

DDR_MAD0 AG12
DDR_MAD1 AH13
DDR_MAD2 AH14
DDR_MAD3 AH15

MEMORY
CONTROL
INTERFACE

RAM_A_R<0>
RAM_A_R<1>
RAM_A_R<2>
RAM_A_R<3>
RAM_A_R<4>
RAM_A_R<5>
RAM_A_R<6>
RAM_A_R<7>
RAM_A_R<8>
RAM_A_R<9>
RAM_A_R<10>
RAM_A_R<11>
RAM_A_R<12>
RAM_A_R<13>

DDR_MAD4 AF12
DDR_MAD5 AE12
DDR_MAD6 AD12
DDR_MAD7 AC12
DDR_MAD8 AG15
DDR_MAD9 AF15

DDR_MAD10 AF14
DDR_MAD11 AG14

AA18 DDR_CKE7

C3747

20%
2 10V
CERM
402

38

RAM_WE_L_R

DDR_MUXEN0 AH16
DDR_MUXEN4 AH18

AF17 DDR_CKE3
AB17 DDR_CKE4
AA17 DDR_CKE5
AB18 DDR_CKE6

0.1UF

20%
2 10V
CERM
402

20%
2 10V
CERM
402

38

RAM_CAS_L_R

DDR_BA0 AF21
DDR_BA1 AE20

AD14 DDR_CK_DN
AD15 DDR_CK_E
AC15 DDR_CK_EN
AA15 DDR_CK_F
AB15 DDR_CK_FN

m
il
VOLTAGE=1.25V

R37011

38

RAM_RAS_L_R

DDR_CAS AD20
DDR_WE AC23

AE15 DDR_CK_C
AE14 DDR_CK_CN
AC14 DDR_CK_D

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
PP1V25_PWRON_RAM_VREF_NB

38

DDR_RAS AE21

OMIT

DDR_MAD12 AH17
DDR_MAD13 AG17

Y21 DDR_VREF0
U21 DDR_VREF1
L21 DDR_VREF2
H20 DDR_VREF3

38
38

y
r

PBGA
(SYM 3 OF 7)

a
n
i

38
38

U3LITE
V1.0-300MM

RAM_CLK66M_NB

DDR_CS0 AF18
DDR_CS1 AE18
DDR_CS2 AG20

AA21 DDR_VREF4
M21 DDR_VREF5
V21 DDR_VREF6

RAM_CS_L_R<0>
RAM_CS_L_R<1>
RAM_CS_L_R<2>
RAM_CS_L_R<3>
RAM_CS_L_R<8>
RAM_CS_L_R<9>
RAM_CS_L_R<10>
RAM_CS_L_R<11>

DDR_CS3 AH20
DDR_CS8 AC18
DDR_CS9 AD18

J20 DDR_VREF7

DDR_CS10 AG18
DDR_CS11 AH19

C3748
0.1UF

DDR_DQSP0 AC24
DDR_DQSP1 AG23

20%
2 10V
CERM
402

RAM_DQS_R<0>
RAM_DQS_R<1>
RAM_DQS_R<2>
RAM_DQS_R<3>
RAM_DQS_R<4>
RAM_DQS_R<5>
RAM_DQS_R<6>
RAM_DQS_R<7>
RAM_DQS_R<8>
RAM_DQS_R<9>
RAM_DQS_R<10>
RAM_DQS_R<11>
RAM_DQS_R<12>
RAM_DQS_R<13>
RAM_DQS_R<14>
RAM_DQS_R<15>

DDR_DQSP2 Y23
DDR_DQSP3 R23
DDR_DQSP4 M22
DDR_DQSP5 B26
DDR_DQSP6 B27
DDR_DQSP7 F23
DDR_DQSP8 AE23
DDR_DQSP9 AD28

DDR_DQSP10 Y27
DDR_DQSP11 U28
DDR_DQSP12 M27

e
r

DDR_DQ123 E26
DDR_DQ124 D28
DDR_DQ125 C28

7 26 37 40 46

C3701

RAM_DQ_R<64>
RAM_DQ_R<65>
RAM_DQ_R<66>
RAM_DQ_R<67>
RAM_DQ_R<68>
RAM_DQ_R<69>
RAM_DQ_R<70>
RAM_DQ_R<71>
RAM_DQ_R<72>
RAM_DQ_R<73>
RAM_DQ_R<74>
RAM_DQ_R<75>
RAM_DQ_R<76>
RAM_DQ_R<77>
RAM_DQ_R<78>
RAM_DQ_R<79>
RAM_DQ_R<80>
RAM_DQ_R<81>
RAM_DQ_R<82>
RAM_DQ_R<83>
RAM_DQ_R<84>
RAM_DQ_R<85>
RAM_DQ_R<86>
RAM_DQ_R<87>
RAM_DQ_R<88>
RAM_DQ_R<89>
RAM_DQ_R<90>
RAM_DQ_R<91>
RAM_DQ_R<92>
RAM_DQ_R<93>
RAM_DQ_R<94>
RAM_DQ_R<95>
RAM_DQ_R<96>
RAM_DQ_R<97>
RAM_DQ_R<98>
RAM_DQ_R<99>
RAM_DQ_R<100>
RAM_DQ_R<101>
RAM_DQ_R<102>
RAM_DQ_R<103>
RAM_DQ_R<104>
RAM_DQ_R<105>
RAM_DQ_R<106>
RAM_DQ_R<107>
RAM_DQ_R<108>
RAM_DQ_R<109>
RAM_DQ_R<110>
RAM_DQ_R<111>
RAM_DQ_R<112>
RAM_DQ_R<113>
RAM_DQ_R<114>
RAM_DQ_R<115>
RAM_DQ_R<116>
RAM_DQ_R<117>
RAM_DQ_R<118>
RAM_DQ_R<119>
RAM_DQ_R<120>
RAM_DQ_R<121>
RAM_DQ_R<122>
RAM_DQ_R<123>
RAM_DQ_R<124>
RAM_DQ_R<125>
RAM_DQ_R<126>
RAM_DQ_R<127>

7 26 37 40 46

DDR_DQSP13 J28
DDR_DQSP14 F28
DDR_DQSP15 F25

38

38

8
8

38
38
38
38
38

38
38

38
38
38
38
38

38
38

38
38
8
8
38
38
8
8

38
38
38
38
38
38
38
38
38
38
38
38
38
38
38

38

DDR_CLK_AVSS
AA20

38

(SYM 2 OF 7)

=PP2V5_PWRON_RAM

C3744
0.1UF

10%
2 6.3V
CERM
402

PBGA

AF20 DDR_DQ0
AH22 DDR_DQ1
AH21 DDR_DQ2
AG21 DDR_DQ3

RAM_DQ_R<0>
RAM_DQ_R<1>
RAM_DQ_R<2>
RAM_DQ_R<3>
RAM_DQ_R<4>
RAM_DQ_R<5>
RAM_DQ_R<6>
RAM_DQ_R<7>
RAM_DQ_R<8>
RAM_DQ_R<9>
RAM_DQ_R<10>
RAM_DQ_R<11>
RAM_DQ_R<12>
RAM_DQ_R<13>
RAM_DQ_R<14>
RAM_DQ_R<15>
RAM_DQ_R<16>
RAM_DQ_R<17>
RAM_DQ_R<18>
RAM_DQ_R<19>
RAM_DQ_R<20>
RAM_DQ_R<21>
RAM_DQ_R<22>
RAM_DQ_R<23>
RAM_DQ_R<24>
RAM_DQ_R<25>
RAM_DQ_R<26>
RAM_DQ_R<27>
RAM_DQ_R<28>
RAM_DQ_R<29>
RAM_DQ_R<30>
RAM_DQ_R<31>
RAM_DQ_R<32>
RAM_DQ_R<33>
RAM_DQ_R<34>
RAM_DQ_R<35>
RAM_DQ_R<36>
RAM_DQ_R<37>
RAM_DQ_R<38>
RAM_DQ_R<39>
RAM_DQ_R<40>
RAM_DQ_R<41>
RAM_DQ_R<42>
RAM_DQ_R<43>
RAM_DQ_R<44>
RAM_DQ_R<45>
RAM_DQ_R<46>
RAM_DQ_R<47>
RAM_DQ_R<48>
RAM_DQ_R<49>
RAM_DQ_R<50>
RAM_DQ_R<51>
RAM_DQ_R<52>
RAM_DQ_R<53>
RAM_DQ_R<54>
RAM_DQ_R<55>
RAM_DQ_R<56>
RAM_DQ_R<57>
RAM_DQ_R<58>
RAM_DQ_R<59>
RAM_DQ_R<60>
RAM_DQ_R<61>
RAM_DQ_R<62>
RAM_DQ_R<63>

38

M19

U3
38

C3745
1UF

U3LITE
V1.0-300MM

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

VOLTAGE=1.5V

N21
N25

VDD_DDR

P20

5%
1/10W
MF-LF
603

T21
T25

2.2

T19

=PP1V5_PWRON_NB_AVDD

W27
V20

W23

Y16
Y19

AA16

AB25
AA13

AC19

AE22
AE27

AE13
AE16

AG25

AG19

60 48 28 7

AB21

46 40 37 26 7

38
38

C3708
0.1UF

20%
10V
2 CERM
402

C3709
0.1UF

20%
10V
2 CERM
402

C3710
0.1UF

20%
10V
2 CERM
402

MASTER: GILA
1

C3711
0.1UF

20%
10V
2 CERM
402

C3712
0.1UF

20%
10V
2 CERM
402

C3713
0.1UF

20%
10V
2 CERM
402

C3714
0.1UF

20%
10V
2 CERM
402

C3731
0.1UF

20%
10V
2 CERM
402

C3732
0.1UF

20%
10V
2 CERM
402

C3733
0.1UF

20%
10V
2 CERM
402

C3734
0.1UF

20%
10V
2 CERM
402

C3735
0.1UF

20%
10V
2 CERM
402

C3736
0.1UF

20%
10V
2 CERM
402

C3737

LAST MODIFIED: APR 12, 04

0.1UF

20%
10V
2 CERM
402

U3LITE MEMORY
A

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

C3715
0.1UF

20%
2 10V
CERM
402

C3716
0.1UF

20%
2 10V
CERM
402

C3717
0.1UF

20%
2 10V
CERM
402

C3718
0.1UF

20%
2 10V
CERM
402

C3719
0.1UF

20%
2 10V
CERM
402

C3720
0.1UF

20%
2 10V
CERM
402

C3721
0.1UF

20%
2 10V
CERM
402

C3722

0.1UF

C3724
0.1UF

20%
2 10V
CERM
402

20%
2 10V
CERM
402

C3725
0.1UF

20%
2 10V
CERM
402

C3726
0.1UF

C3727
0.1UF

20%
2 10V
CERM
402

20%
2 10V
CERM
402

C3728
0.1UF

20%
2 10V
CERM
402

C3729
0.1UF

20%
2 10V
CERM
402

C3743
0.1UF

20%
2 10V
CERM
402

C3742
0.1UF

20%
2 10V
CERM
402

C3740
0.1UF

20%
2 10V
CERM
402

C3739
0.1UF

20%
2 10V
CERM
402

C3738

II NOT TO REPRODUCE OR COPY IT

0.1UF

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

20%
2 10V
CERM
402

SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6772

37

OF

04
102

38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37

38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37

38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37
38 37

38 37
38 37

38 37
38 37
38 37
38 37

RAM_DQ_R<7>
RAM_DQ_R<2>
RAM_DQ_R<0>
RAM_DQ_R<3>
RAM_DQ_R<1>
RAM_DQ_R<4>
RAM_DQ_R<6>
RAM_DQ_R<5>
RAM_DQ_R<9>
RAM_DQ_R<10>
RAM_DQ_R<11>
RAM_DQ_R<14>
RAM_DQ_R<12>
RAM_DQ_R<13>
RAM_DQ_R<15>
RAM_DQ_R<8>
RAM_DQ_R<17>
RAM_DQ_R<22>
RAM_DQ_R<19>
RAM_DQ_R<18>
RAM_DQ_R<20>
RAM_DQ_R<16>
RAM_DQ_R<21>
RAM_DQ_R<23>
RAM_DQ_R<30>
RAM_DQ_R<26>
RAM_DQ_R<24>
RAM_DQ_R<27>
RAM_DQ_R<28>
RAM_DQ_R<31>
RAM_DQ_R<29>
RAM_DQ_R<25>
RAM_DQ_R<32>
RAM_DQ_R<35>
RAM_DQ_R<38>
RAM_DQ_R<37>
RAM_DQ_R<39>
RAM_DQ_R<33>
RAM_DQ_R<34>
RAM_DQ_R<36>
RAM_DQ_R<47>
RAM_DQ_R<46>
RAM_DQ_R<43>
RAM_DQ_R<41>
RAM_DQ_R<45>
RAM_DQ_R<42>
RAM_DQ_R<40>
RAM_DQ_R<44>
RAM_DQ_R<51>
RAM_DQ_R<50>
RAM_DQ_R<49>
RAM_DQ_R<48>
RAM_DQ_R<52>
RAM_DQ_R<53>
RAM_DQ_R<54>
RAM_DQ_R<55>
RAM_DQ_R<56>
RAM_DQ_R<63>
RAM_DQ_R<59>
RAM_DQ_R<61>
RAM_DQ_R<57>
RAM_DQ_R<60>
RAM_DQ_R<58>
RAM_DQ_R<62>

ELECTRICAL_CONSTRAINT_SET

RP3836
RP3836
RP3836
RP3836
RP3816
RP3816
RP3816
RP3816
RP3835
RP3801
RP3801
RP3801
RP3835
RP3801
RP3835
RP3835
RP3822
RP3822
RP3822
RP3822
RP3823
RP3823
RP3823
RP3823
RP3808
RP3824
RP3808
RP3824
RP3808
RP3808
RP3824
RP3824
RP3826
RP3807
RP3826
RP3807
RP3826
RP3807
RP3807
RP3826
RP3811
RP3811
RP3814
RP3814
RP3811
RP3814
RP3814
RP3811
RP3830
RP3830
RP3830
RP3830
RP3812
RP3812
RP3812
RP3812
RP3813
RP3831
RP3813
RP3831
RP3831
RP3831
RP3813
RP3813

22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22

RAM_DQ<7>
RAM_DQ<2>
RAM_DQ<0>
RAM_DQ<3>
RAM_DQ<1>
RAM_DQ<4>
RAM_DQ<6>
RAM_DQ<5>
RAM_DQ<9>
RAM_DQ<10>
RAM_DQ<11>
RAM_DQ<14>
RAM_DQ<12>
RAM_DQ<13>
RAM_DQ<15>
RAM_DQ<8>
RAM_DQ<17>
RAM_DQ<22>
RAM_DQ<19>
RAM_DQ<18>
RAM_DQ<20>
RAM_DQ<16>
RAM_DQ<21>
RAM_DQ<23>
RAM_DQ<30>
RAM_DQ<26>
RAM_DQ<24>
RAM_DQ<27>
RAM_DQ<28>
RAM_DQ<31>
RAM_DQ<29>
RAM_DQ<25>
RAM_DQ<32>
RAM_DQ<35>
RAM_DQ<38>
RAM_DQ<37>
RAM_DQ<39>
RAM_DQ<33>
RAM_DQ<34>
RAM_DQ<36>
RAM_DQ<47>
RAM_DQ<46>
RAM_DQ<43>
RAM_DQ<41>
RAM_DQ<45>
RAM_DQ<42>
RAM_DQ<40>
RAM_DQ<44>
RAM_DQ<51>
RAM_DQ<50>
RAM_DQ<49>
RAM_DQ<48>
RAM_DQ<52>
RAM_DQ<53>
RAM_DQ<54>
RAM_DQ<55>
RAM_DQ<56>
RAM_DQ<63>
RAM_DQ<59>
RAM_DQ<61>
RAM_DQ<57>
RAM_DQ<60>
RAM_DQ<58>
RAM_DQ<62>

THE FOLLOWING IS A SWAPPABLE GROUP


RP3841 3
6
15
RAM_CKE_R<4>
RAM_CKE<4>
RP3841 4
5
15
RAM_CKE_R<5>
RAM_CKE<5>
RP3841
2
7
15
RAM_CKE_R<0>
RAM_CKE<0>
RP3841 1
8
15
RAM_CKE_R<1>
RAM_CKE<1>

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 37
38 37
38 37

38 37
38 37
38 37
38 37
38 37
38 37
38 37

38 37
38 37
38 37
38 37

38 37
38 37

38 37
38 37

RAM_CS_L_R<8>
RAM_CS_L_R<9>
RAM_CS_L_R<1>
RAM_CS_L_R<0>

RP3842
RP3842
RP3842
RP3842

15
15
15
15

RAM_CS_L<8>
RAM_CS_L<9>
RAM_CS_L<1>
RAM_CS_L<0>

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 45

38 40 44

38 37

38 40 44

THE FOLLOWING IS A SWAPPABLE GROUP


RP3832 3
6
15
RAM_A_R<11>
RAM_A<11>
RP3832 4
5
15
RAM_A_R<1>
RAM_A<1>
RP3832
2
7
15
RAM_A_R<10>
RAM_A<10>
RP3800 4
5
15
RAM_WE_L_R
RAM_WE_L
RP3833 3
6
15
RAM_A_R<4>
RAM_A<4>
RP3833
2
7
15
RAM_A<6>
RAM_A_R<6>
RP3833
1
8
15
RAM_A_R<7>
RAM_A<7>
1

RAM_A_R<12>
RAM_A_R<2>
RAM_A_R<0>
RAM_A_R<5>
RAM_A_R<13>
RAM_A_R<3>

RP3834
RP3800
RP3834
RP3833
RP3832
RP3800
RP3800

RAM_CAS_L_R
RAM_BA_R<0>

RP3804
RP3804

RAM_BA_R<1>
RAM_RAS_L_R
RAM_A_R<9>
RAM_A_R<8>

RP3804
RP3804
RP3834
RP3834

15
15
15
15
15
15
15

RAM_A<12>
RAM_A<2>
RAM_A<0>
RAM_A<5>
RAM_A<13>
RAM_A<3>

15
15

RAM_CAS_L
RAM_BA<0>

15
15
15
15

RAM_BA<1>
RAM_RAS_L
RAM_A<9>
RAM_A<8>

38 40 45

38 37

38 40 44
38 40 44

38 40 44
38 40 44
38 40 45
38 40 45
38 40 44
38 40 44
38 40 44

38 37
38 37
38 37

38 37
38 37
38 37
38 37
38 37
38 37

38 37
38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37

38 40 44

38 37
38 37

38 40 45

38 37

38 40 45

38 37
38 37

38 37
38 37
38 37
38 37

RP3818
RP3805
RP3818
RP3805
RP3818
RP3805
RP3805
RP3818
RP3817
RP3802
RP3817
RP3817
RP3802
RP3817
RP3802
RP3802
RP3806
RP3821
RP3821
RP3821
RP3806
RP3806
RP3821
RP3806
RP3819
RP3819
RP3803
RP3819
RP3803
RP3819
RP3803
RP3803
RP3820
RP3820
RP3820
RP3820
RP3825
RP3825
RP3825
RP3825
RP3809
RP3809
RP3809
RP3829
RP3829
RP3829
RP3809
RP3829
RP3828
RP3815
RP3815
RP3828
RP3815
RP3828
RP3828
RP3815
RP3827
RP3827
RP3827
RP3810
RP3827
RP3810
RP3810
RP3810

4
1
4
2
1
1
3
3
2
4
3
2

2
1
4
1
3

RAM_DQ<68>
RAM_DQ<65>
RAM_DQ<70>
RAM_DQ<66>
RAM_DQ<71>
RAM_DQ<64>
RAM_DQ<67>
RAM_DQ<69>
RAM_DQ<74>
RAM_DQ<73>
RAM_DQ<72>
RAM_DQ<75>
RAM_DQ<78>
RAM_DQ<79>
RAM_DQ<77>
RAM_DQ<76>
RAM_DQ<87>
RAM_DQ<86>
RAM_DQ<81>
RAM_DQ<80>
RAM_DQ<84>
RAM_DQ<85>
RAM_DQ<83>
RAM_DQ<82>
RAM_DQ<91>
RAM_DQ<93>
RAM_DQ<94>
RAM_DQ<90>
RAM_DQ<88>
RAM_DQ<89>
RAM_DQ<92>
RAM_DQ<95>
RAM_DQ<98>
RAM_DQ<96>
RAM_DQ<103>
RAM_DQ<97>
RAM_DQ<100>
RAM_DQ<99>
RAM_DQ<102>
RAM_DQ<101>
RAM_DQ<111>
RAM_DQ<106>
RAM_DQ<105>
RAM_DQ<108>
RAM_DQ<107>
RAM_DQ<110>
RAM_DQ<104>
RAM_DQ<109>
RAM_DQ<119>
RAM_DQ<112>
RAM_DQ<117>
RAM_DQ<118>
RAM_DQ<113>
RAM_DQ<115>
RAM_DQ<116>
RAM_DQ<114>
RAM_DQ<121>
RAM_DQ<124>
RAM_DQ<120>
RAM_DQ<123>
RAM_DQ<125>
RAM_DQ<122>
RAM_DQ<126>
RAM_DQ<127>

38 37
38 40 45
38 37
38 40 45
38 37
38 40 45
38 37
38 40 45
38 37
38 40 45
38 37
38 40 45
38 37
38 40 45
38 37
38 40 45
38 37
38 40 45
38 37
38 40 45
38 37
38 40 45
38 37
38 40 45
40 38
38 40 45
40 38
38 40 45
40 38
38 40 45
40 38
38 40 45
40 38
38 40 45
40 38
38 40 45
40 38
38 40 45
40 38
38 40 45
40 38
38 40 45
40 38
38 40 45
40 38
38 40 45
40 38

6
5
8
5
7
8
8
6
6
7
5
6
7
5
7
8
5
8
6

38 40 45

38 37

38 40 45

38 37

38 40 44

38 37

38 40 44

38 37

RAM_CLK_A_P_R
RAM_CLK_A_N_R
RAM_CLK_B_P_R
RAM_CLK_B_N_R
RAM_CLK_C_P_R
RAM_CLK_C_N_R
RAM_CLK_D_P_R
RAM_CLK_D_N_R
RAM_CLK_E_P_R
RAM_CLK_E_N_R
RAM_CLK_F_P_R
RAM_CLK_F_N_R

RAM_DQS_R<0>
RAM_DQS_R<1>
RAM_DQS_R<2>
RAM_DQS_R<3>
RAM_DQS_R<4>
RAM_DQS_R<5>
RAM_DQS_R<6>
RAM_DQS_R<7>
RAM_DQS_R<8>
RAM_DQS_R<9>
RAM_DQS_R<10>
RAM_DQS_R<11>
RAM_DQS_R<12>
RAM_DQS_R<13>
RAM_DQS_R<14>
RAM_DQS_R<15>

R3816
R3817
R3818
R3819
R3820
R3821
R3822
R3823
R3824
R3825
R3826
R3827

R3800
R3801
R3802
R3803
R3804
R3805
R3806
R3807
R3808
R3809
R3810
R3811
R3812
R3813
R3814
R3815

1
1
1
1

2
2
2
2

15
15
15
15
15
15
15
15
15
15
15
15

RAM_CLK_A_P
RAM_CLK_A_N
RAM_CLK_B_P
RAM_CLK_B_N
RAM_CLK_C_P
RAM_CLK_C_N
RAM_CLK_D_P
RAM_CLK_D_N
RAM_CLK_E_P
RAM_CLK_E_N
RAM_CLK_F_P
RAM_CLK_F_N

38 40 45

38 37

38 40 45

38 37

38 40 45

44 40 38

38 40 45

44 40 38

38 40 45

45 40 38

38 40 45

45 40 38

38 40 45

38 37

38 40 45

38 37

38 40 45

44 40 38

38 40 45

44 40 38

38 40 45

45 40 38

38 40 45

45 40 38

38 40 45
38 40 45

38 37

38 37

38 40 45
38 40 45

45 44 40 38

38 40 45

44 40 38

38 40 45

44 40 38

44 40 38

38 40 45

44 40 38

38 40 45
38 40 45
38 40 45
38 40 45
38 40 45
38 40 45
38 40 45
38 40 45
38 40 45
38 40 45
38 40 45
38 40 45

44 40 38
44 40 38

44 40 38
44 40 38
44 40 38
44 40 38

44 40 38
44 40 38
44 40 38
44 40 38
44 40 38

38 40 45

44 40 38

38 40 45

45 40 38

38 40 45

45 40 38

38 40 45

45 40 38

38 40 45

45 40 38

38 40 45

45 40 38

38 40 45

45 40 38

38 40 45

45 40 38

38 40 45

45 40 38
45 40 38
45 40 38
45 40 38
45 40 38

38 40

45 40 38

38 40

45 40 38

38 40

45 40 38

38 40

45 40 38

38 40

38 37

38 40

38 37

38 40

38 37

38 40

38 37

38 40

38 37

38 40

45 44 40 38

38 40

45 40 38

45 40 38

15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15

RAM_DQS<0>
RAM_DQS<1>
RAM_DQS<2>
RAM_DQS<3>
RAM_DQS<4>
RAM_DQS<5>
RAM_DQS<6>
RAM_DQS<7>
RAM_DQS<8>
RAM_DQS<9>
RAM_DQS<10>
RAM_DQS<11>
RAM_DQS<12>
RAM_DQS<13>
RAM_DQS<14>
RAM_DQS<15>

RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK

RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK
RAM_CLK

RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD

RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD

RAM_DQS0
RAM_DQS0
RAM_DQS1
RAM_DQS1
RAM_DQS2
RAM_DQS2
RAM_DQS3
RAM_DQS3
RAM_DQS4
RAM_DQS4
RAM_DQS5
RAM_DQS5
RAM_DQS6
RAM_DQS6
RAM_DQS7
RAM_DQS7
RAM_DQS8
RAM_DQS8
RAM_DQS9
RAM_DQS9
RAM_DQS10
RAM_DQS10
RAM_DQS11
RAM_DQS11
RAM_DQS12
RAM_DQS12
RAM_DQS13
RAM_DQS13
RAM_DQS14
RAM_DQS14
RAM_DQS15
RAM_DQS15

RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD

RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD

RAM_A_CTL
RAM_A_CTL
RAM_A_CTL
RAM_A_CTL
RAM_A_CTL

RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD

RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD
RAM_CAD

RAM_CLK0
RAM_CLK0
RAM_CLK0
RAM_CLK0
RAM_CLK0
RAM_CLK0
RAM_CLK1
RAM_CLK1
RAM_CLK1
RAM_CLK1
RAM_CLK1
RAM_CLK1

RAM_CKE_R<1..0>
RAM_CKE_R<5..4>
RAM_CKE<0>
RAM_CKE<1>
RAM_CKE<4>
RAM_CKE<5>
RAM_CS_L_R<1..0>
RAM_CS_L_R<9..8>
RAM_CS_L<0>
RAM_CS_L<1>
RAM_CS_L<8>
RAM_CS_L<9>

RAM_DQS_R<15..0>
RAM_DQ_R<127..0>
RAM_DQ<127..0>
RAM_DQS<0>
RAM_DQ<7..0>
RAM_DQS<1>
RAM_DQ<15..8>
RAM_DQS<2>
RAM_DQ<23..16>
RAM_DQS<3>
RAM_DQ<31..24>
RAM_DQS<4>
RAM_DQ<39..32>
RAM_DQS<5>
RAM_DQ<47..40>
RAM_DQS<6>
RAM_DQ<55..48>
RAM_DQS<7>
RAM_DQ<63..56>
RAM_DQS<8>
RAM_DQ<71..64>
RAM_DQS<9>
RAM_DQ<79..72>
RAM_DQS<10>
RAM_DQ<87..80>
RAM_DQS<11>
RAM_DQ<95..88>
RAM_DQS<12>
RAM_DQ<103..96>
RAM_DQS<13>
RAM_DQ<111..104>
RAM_DQS<14>
RAM_DQ<119..112>
RAM_DQS<15>
RAM_DQ<127..120>

RAM_CKECS0
RAM_CKECS0
RAM_CKECS1
RAM_CKECS1

RAM_CKECS0
RAM_CKECS0
RAM_CKECS1
RAM_CKECS1

NET_SPACING_TYPE

y
r

DIFFERENTIAL_PAIR
RAM_CLK_A_R
RAM_CLK_A_R
RAM_CLK_B_R
RAM_CLK_B_R
RAM_CLK_C_R
RAM_CLK_C_R
RAM_CLK_D_R
RAM_CLK_D_R
RAM_CLK_E_R
RAM_CLK_E_R
RAM_CLK_F_R
RAM_CLK_F_R
RAM_CLK_A
RAM_CLK_A
RAM_CLK_B
RAM_CLK_B
RAM_CLK_C
RAM_CLK_C
RAM_CLK_D
RAM_CLK_D
RAM_CLK_E
RAM_CLK_E
RAM_CLK_F
RAM_CLK_F

I209
I210
I211
I212
I213
I214
I215

I216
I217
I218
I219
I220
I221
I222
I223
I224
I225
I226
I227
I228
I229

I234
I236
I235
I237
I238
I241
I243
I242
I245
I244

I305
I294
I293
I246
I248
I251
I252
I253
I254
I255
I256
I257
I258
I259
I260
I261
I262
I263
I264
I265
I267
I266
I268
I270
I269

I272
I271
I273
I275
I274
I277
I276
I278
I280

38 40 44

45 40 38

RAM_A_R<13..0>
RAM_BA_R<1..0>
RAM_RAS_L_R
RAM_CAS_L_R
RAM_WE_L_R
RAM_A<13..0>
RAM_BA<1..0>
RAM_RAS_L
RAM_CAS_L
RAM_WE_L

I279

I295
I296
I297
I298
I299
I300
I304
I303
I302
I301

38 40 44
38 40 44
38 40 44

SERIES TERM

RAM_CLK PRIMARY SPACING SET BASED ON DIFF IMPEDANCE


RAM_CLK LINE-LINE SPACING SET TO 15MIL
TOTAL LENGTH TOLERENCE = 20PS = 2.82MM

38 40 44
38 40 44
38 40 44
38 40 44

NOTICE OF PROPRIETARY PROPERTY

RAM_CAD SPACING IS 10MIL

38 40 45

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

38 40 45
38 40 45

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

38 40 45

II NOT TO REPRODUCE OR COPY IT

38 40 45

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

38 40 45
38 40 45

SIZE
38 40 45

DRAWING NUMBER

REV.

051-6772

SHT
NONE

I208

I232

SCALE

I207

I230

APPLE COMPUTER INC.

I206

38 40

45 40 38

RAM_CLK_A_P_R
RAM_CLK_A_N_R
RAM_CLK_B_P_R
RAM_CLK_B_N_R
RAM_CLK_C_P_R
RAM_CLK_C_N_R
RAM_CLK_D_P_R
RAM_CLK_D_N_R
RAM_CLK_E_P_R
RAM_CLK_E_N_R
RAM_CLK_F_P_R
RAM_CLK_F_N_R
RAM_CLK_A_P
RAM_CLK_A_N
RAM_CLK_B_P
RAM_CLK_B_N
RAM_CLK_C_P
RAM_CLK_C_N
RAM_CLK_D_P
RAM_CLK_D_N
RAM_CLK_E_P
RAM_CLK_E_N
RAM_CLK_F_P
RAM_CLK_F_N

NET_PHYSICAL_TYPE

a
n
i

38 40 45

m
il

22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22

THE FOLLOWING ARE 0402 5% RESISTORS

38 40 45

38 40 45

RAM_DQ_R<68>
RAM_DQ_R<65>
RAM_DQ_R<70>
RAM_DQ_R<66>
RAM_DQ_R<71>
RAM_DQ_R<64>
RAM_DQ_R<67>
RAM_DQ_R<69>
RAM_DQ_R<74>
RAM_DQ_R<73>
RAM_DQ_R<72>
RAM_DQ_R<75>
RAM_DQ_R<78>
RAM_DQ_R<79>
RAM_DQ_R<77>
RAM_DQ_R<76>
RAM_DQ_R<87>
RAM_DQ_R<86>
RAM_DQ_R<81>
RAM_DQ_R<80>
RAM_DQ_R<84>
RAM_DQ_R<85>
RAM_DQ_R<83>
RAM_DQ_R<82>
RAM_DQ_R<91>
RAM_DQ_R<93>
RAM_DQ_R<94>
RAM_DQ_R<90>
RAM_DQ_R<88>
RAM_DQ_R<89>
RAM_DQ_R<92>
RAM_DQ_R<95>
RAM_DQ_R<98>
RAM_DQ_R<96>
RAM_DQ_R<103>
RAM_DQ_R<97>
RAM_DQ_R<100>
RAM_DQ_R<99>
RAM_DQ_R<102>
RAM_DQ_R<101>
RAM_DQ_R<111>
RAM_DQ_R<106>
RAM_DQ_R<105>
RAM_DQ_R<108>
RAM_DQ_R<107>
RAM_DQ_R<110>
RAM_DQ_R<104>
RAM_DQ_R<109>
RAM_DQ_R<119>
RAM_DQ_R<112>
RAM_DQ_R<117>
RAM_DQ_R<118>
RAM_DQ_R<113>
RAM_DQ_R<115>
RAM_DQ_R<116>
RAM_DQ_R<114>
RAM_DQ_R<121>
RAM_DQ_R<124>
RAM_DQ_R<120>
RAM_DQ_R<123>
RAM_DQ_R<125>
RAM_DQ_R<122>
RAM_DQ_R<126>
RAM_DQ_R<127>

e
r

38 40 44

38 37

38 37

ALL R PACKS ARE 1/16W 5%

38

OF

04
102

8
46 40 37 26 7

=PP2V5_PWRON_RAM

=PP2V5_PWRON_RAM

J4000
DDR-DIMM-STD
F-28DEG-TH

40
44 38

44 38

RAM_DQ<10>
RAM_DQS<1>
RAM_DQ<9>

44 38

RAM_DQ<15>

44 38
44 38

PP1V25_RAM_VREF_DIMM
RAM_DQ<14>

2
3
4
5
6
7
8

NC
6

44 38
44 38
44 38

38
38

44 38
44 38
44 38

44 38
44 38
44 38

44 40 38
44 38
44 40 38

TP_J4000_SJRESET_L
RAM_DQ<2>
RAM_DQ<0>
RAM_DQS<0>
RAM_CLK_A_P
RAM_CLK_A_N
RAM_DQ<6>
RAM_DQ<5>
RAM_CKE<0>
RAM_DQ<19>
RAM_DQ<18>
RAM_DQS<2>
RAM_A<9>
RAM_DQ<23>
RAM_A<7>

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

44 38
44 40 38
44 38

44 38
44 38
44 40 38

RAM_DQ<16>
RAM_A<5>
RAM_DQ<27>
RAM_DQ<29>
RAM_DQS<3>
RAM_A<4>

31
32
33
34
35
36
37
38

44 38
44 38
44 40 38

44 40 38

RAM_DQ<31>
RAM_DQ<28>
RAM_A<2>
RAM_A<1>

39
40
41
42
43

NC 44
NC 45
46

NC 47
44 40 38

45 40 38

44 38

44 38
44 38
44 38

RAM_A<0>

RAM_BA<1>
RAM_DQ<34>
RAM_DQ<37>
RAM_DQS<4>
RAM_DQ<38>

44 38

44 38

45 40 38
44 38
45 40 38

RAM_BA<0>
RAM_DQ<32>
RAM_DQ<61>
RAM_WE_L
RAM_DQ<57>
RAM_CAS_L

44 38
44 38

44 38
44 38

38
38

RAM_DQS<7>
RAM_DQ<59>
RAM_DQ<56>

RAM_DQ<43>
RAM_DQ<41>
RAM_CLK_B_N
RAM_CLK_B_P

44 38
44 38

RAM_DQS<5>
RAM_DQ<47>
RAM_DQ<44>

44 38
44 38
44 38

40 18
40 18

VSS
NC

DQ3
NC

NC

NC
VSS
DQ8

A13
VDDQ

DQ9

DQ12

DQS1
VDDQ

DQ13
DM1/DQS10

CK1

VDD

CK1*
VSS

DQ14
DQ15

DQ10
DQ11

CKE1
VDDQ

CKE0

BA2

VDDQ
DQ16

DQ20
A12

DQ17

VSS

DQS2
VSS

DQ21
A11

A9

DM2/DQS11

DQ18
A7

VDD
DQ22

VDDQ
DQ19

A8
DQ23

A5

VSS

DQ24
VSS

A6
DQ28

DQ25

DQ29

DQS3
A4

VDDQ
DM3/DQS12

VDD

A3

DQ26
DQ27

DQ30
VSS

A2
VSS

DQ31
NC

A1

NC

NC
NC

VDDQ
CK0

VDD

CKO*

A10

50
NC 51
52
53
54
55
56
57
59
60
61
62
63
64
65
67
68
69
70
NC 71
72
73
74
75
76
78
79
80

RAM_DQ<50>
RAM_DQ<51>

83

RAM_DQS<6>
RAM_DQ<53>
RAM_DQ<52>

86
87

I2C_DIMM_SDA
I2C_DIMM_SCL

DQ6
DQ7

DQ2
VDD

VSS
NC

81

44 38

DM0/DQS9

NC

NC 82
44 38

DQ5
VDDQ

NC
A0

77
44 38

VSS
DQ4

VSS
DQ1
DQS0

84
85

88
89
NC 90
91
92

VSS
NC

NC
VDDQ

BA1

NC

DQ32
VDDQ

VSS
DQ36

DQ33

DQ37

DQS4
DQ34

VDD
DM4/DQS13

VSS

DQ38

BA0
DQ35

DQ39
VSS

DQ40
VDDQ

DQ44
RAS*

WE*

DQ45

DQ41
CAS*

VDDQ
S0*

VSS

S1*

DQS5
DQ42

DM5/DQS14
VSS

DQ43

DQ46

VDD
NC,S2*

DQ47
NC,S3*

DQ48
DQ49

VDDQ
DQ52

VSS

DQ53

CK2*
CK2

NC,FETEN
VDD

VDDQ

DM6/DQS15

DQS6
DQ50

DQ54
DQ55

DQ51

VDDQ

VSS
VDDID

NC
DQ60

DQ56
DQ57

DQ61
VSS

VDD

DM7/DQS16

DQS7
DQ58

DQ62
DQ63

DQ59

VDDQ

VSS
WP

SA0
SA1

SDA

SA2

SCL

516-0086

TOP SIDE

OMIT

DQ0

48

66
44 38

VREF

NC 49

58
45 40 38

BOT SIDE

VVDDSPD

7 26 37 40 46

46 40 37 26 7

=PP2V5_PWRON_RAM

95
96

45 38

38 44

97

45 38

98
99

45 38

45 38

RAM_DQ<77>

45 38

105

45 38

RAM_DQ<3>
RAM_DQ<7>

106
107

45 38
38 44
45 38

RAM_DQ<1>
RAM_DQ<4>
RAM_CKE<1>

111
112
113 NC
114
115

38

45 38
38 44

38 44

38 40 44

116

RAM_DQ<22>
RAM_A<11>

38 44

RAM_DQ<21>
RAM_A<8>
RAM_DQ<20>

38 44
38 40 44

C4039

RAM_A<3>
RAM_DQ<24>

133

RAM_DQ<30>

45 38

0.1UF

C4040
0.1UF

20%
2 10V
CERM
402

38 44
38 44

C4044
0.1UF

38 40 44

20%
2 10V
CERM
402

38 44

C4045
0.1UF
20%

138
139
140 NC
141

402

38

C4038
0.1UF

20%
2 10V
CERM
402
1

C4041
0.1UF

20%
2 10V
CERM
402
1

C4043
0.1UF

C4048
0.1UF

20%
2 10V
CERM
402

38 40 45

142 NC
143

44 40 38

45 38

C4024

45 38

C4046
0.1UF

20%
2 10V
CERM
402

C4031

0.1UF
RAM_DQ<35>
RAM_DQ<33>

147

20%
10V
402

2 CERM

38 44
38 44

45 38
45 38

0.1UF

C4047

151
152
153

RAM_DQ<60>
RAM_RAS_L
RAM_DQ<63>

154
155
156
157

RAM_CS_L<0>
RAM_CS_L<1>

158

38 44
38 44

38 44

38 44

38 44
38 44

C4050
0.1UF

20%
2 10V
CERM
402
1

38 40 45

159
160

RAM_DQ<62>
RAM_DQ<58>

C4028
0.1UF

20%
2 10V
CERM
402

P
RAM_DQ<40>
RAM_DQ<42>
RAM_A<13>

RAM_DQ<46>
RAM_DQ<45>

RAM_DQ<49>
RAM_DQ<48>

RAM_DQ<54>
RAM_DQ<55>

RAM_DQ<87>
RAM_A<5>
RAM_DQ<90>

32
33

RAM_DQ<89>
RAM_DQS<11>
RAM_A<4>

44 40 38

RAM_DQ<88>
RAM_DQ<94>
RAM_A<2>

44 40 38

RAM_A<1>

45 38
45 38

C4026

C4029

44 40 38

20%
10V
402

C4030
0.1UF

45 38

20%
10V
402

45 38

38 44
38 44

38 44
38 44

C4049
0.1UF

20%
10V
2 CERM
402
1

45 38

C4032

41
42

38 44

RAM_A<0>

RAM_BA<1>

RAM_DQ<98>

20%
10V
2 CERM
402

45 40 38
45 38
45 38

C4022
0.1UF

45 40 38

20%
2 10V
CERM
402

45 38

45 40 38

45 38
45 38
45 38

46
47

NC

48

NC 49
50

NC 51
52

53
54
55
56
57
58
59

RAM_BA<0>
RAM_DQ<102>
RAM_DQ<106>

60
61
62
63

RAM_WE_L
RAM_DQ<111>
RAM_CAS_L

64
65
66
67

RAM_DQS<13>
RAM_DQ<107>
RAM_DQ<110>

68
69
70
71

NC
45 38
45 38

72
73

RAM_DQ<114>
RAM_DQ<113>

74
38
38

45 38
45 38
45 38

75
76

RAM_CLK_E_N
RAM_CLK_E_P

77
78

RAM_DQS<14>
RAM_DQ<115>
RAM_DQ<118>

79
80
81

NC 82

38 44

45 38

38 44

45 38

83
84

RAM_DQ<124>
RAM_DQ<125>

85
45 38

38 44

45 38

38 44

45 38

86
87

RAM_DQS<15>
RAM_DQ<127>
RAM_DQ<126>

88
89

NC 90
40 18

R4014

40 18

10K 2
1

5%
1/16W
MF-LF
ADDR=0(A0/A1) 402

NC
NC 45

RAM_DQ<103>
RAM_DQS<12>
RAM_DQ<101>

SD_A_SA0

SA1
SA2

43
44

0.1UF

38 40 44

38 44

37

40

20%
2 10V
CERM
402

2 CERM

35
36
38
39

0.1UF

0.1UF
2 CERM

e
r
1

RAM_DQ<36>
RAM_DQ<39>

30
31

0.1UF

24
25

29

20%
10V
2 CERM
402
1

23

27
28

RAM_A<9>
RAM_DQ<82>
RAM_A<7>

C4025

20%
2 10V
CERM
402
1

BOT SIDE

VREF
DQ0
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC

TOP SIDE

OMIT

VSS
DQ4
DQ5

91
92

I2C_DIMM_SDA
I2C_DIMM_SCL

VDDQ
DM0/DQS9
DQ6
DQ7
VSS
NC

NC
VSS

NC
A13

DQ8

VDDQ

DQ9
DQS1

DQ12
DQ13

VDDQ

DM1/DQS10

CK1
CK1*

VDD
DQ14

VSS
DQ10

DQ15
CKE1

DQ11

VDDQ

CKE0
VDDQ

BA2
DQ20

DQ16

A12

DQ17
DQS2

VSS
DQ21

94
95

RAM_DQ<74>
RAM_DQ<72>

VSS

A9
DQ18

A11

DM2/DQS11
VDD

A7
VDDQ

DQ22
A8

DQ19

DQ23

A5
DQ24

VSS
A6

VSS

DQ25
DQS3
A4

DQ28

DQ29
VDDQ

DM3/DQS12

VDD
DQ26

A3
DQ30

DQ27
A2

VSS
DQ31

VSS

NC

A1
NC

NC
VDDQ

NC

CK0

VDD
NC
A0

NC
VSS
NC
BA1

CKO*
VSS
NC

A10
NC

VDDQ
NC

DQ32

VSS

VDDQ

DQ36

DQ33
DQS4

DQ37
VDD

DQ34

DM4/DQS13

VSS
BA0

DQ38
DQ39

DQ35

VSS

DQ40
VDDQ

DQ44
RAS*

WE*
DQ41

DQ45
VDDQ

CAS*

S0*

VSS
DQS5

S1*
DM5/DQS14

DQ42

VSS

DQ43
VDD

DQ46
DQ47

NC,S2*

NC,S3*

DQ48
DQ49

VDDQ
DQ52

VSS
CK2*

DQ53
NC,FETEN

CK2

VDD

VDDQ
DQS6

DM6/DQS15
DQ54

DQ50

DQ55

DQ51
VSS

VDDQ
NC

VDDID

DQ60

DQ56
DQ57

DQ61
VSS

VDD
DQS7

DM7/DQS16
DQ62

DQ58

DQ63

DQ59
VSS
WP
SDA
SCL

VDDQ
SA0
SA1
SA2
VVDDSPD

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION
TABLE_5_ITEM

CONN,DDR DIMM 30 DEG

J4000,J4001

CRITICAL

17_INCH_LCD

V
V
R
R
V

TABLE_5_ITEM

516-0087

CONN,DDR DIMM REVERSE 30 DEG

J4000,J4001

20_INCH_LCD

150
1%
1/16W
MF-LF
2 402

38 45
38 45

96
97
98

RAM_DQ<76>
RAM_DQ<78>

99
100
101 NC
102 NC
103 NC FETEN
104
105
106

RAM_DQ<69>
RAM_DQ<68>
RAM_CKE<5>

111
112

CRITICAL

C4035 R4010
1UF

38 45

150
1%
1/16W
MF-LF
2 402

38 45
38 45

38 45
38 45
38 45

=PP2V5_PWRON_RAM

113 NC
114

RAM_DQ<81>
RAM_A<12>

115
116
117

RAM_DQ<86>
RAM_A<11>

118
119
120
121

RAM_DQ<85>
RAM_A<8>
RAM_DQ<84>

122
123
124
125

RAM_A<6>
RAM_DQ<91>
RAM_DQ<93>

126
127
128

7 26 37 40 46

38 45

38 40 44

10UF

38 40 44

C4011
0.1UF

20%
10V
2 CERM
402

38 40 44
38 45

38 40 44
38 45

C4014
0.1UF

20%
10V
2 CERM
402

38 45

10UF

20%
6.3V
2 CERM
1206

38 45

38 45

C4008 1 C4007

20%
6.3V
2 CERM
1206

C4010

0.1UF

20%
10V
2 CERM
402
1

C4012

20%
10V
2 CERM
402

C4009
0.1UF
20%
10V
402

2 CERM

0.1UF

C4033
0.1UF
20%
10V
402

2 CERM

129
130
131

RAM_A<3>
RAM_DQ<92>

38 40 44

RAM_DQ<95>

137

RAM_CLK_D_P
RAM_CLK_D_N

138
139

140 NC
141
142 NC

RAM_A<10>

0.1UF

38 45

20%

2 10V
CERM

132

133
134 NC
135 NC
136

C4000
402

38 45

C4020
20%
402

38

C4017
0.1UF

38 40 45

20%
2 10V
CERM
402

143

0.1UF
20%

2 10V
CERM

402

0.1UF
2 10V
CERM

38

C4013

C4015
20%
402

C4016

0.1UF
20%
402

C4001
0.1UF
20%

10V
2 CERM
402

0.1UF

20%
2 10V
CERM
402

C4042

2 10V
CERM

0.1UF
10V
2 CERM

C4027
0.1UF
20%

2 10V
CERM

402

144 NC
145
146

RAM_DQ<96>
RAM_DQ<97>

147
148

0.1UF
38 45
38 45

RAM_DQ<99>
RAM_DQ<100>

152
153
154

RAM_DQ<104>
RAM_RAS_L
RAM_DQ<105>

155
156
157

RAM_CS_L<8>
RAM_CS_L<9>

158
159

C4021

20%
10V
2 CERM
402

38 45

0.1UF
2 CERM

0.1UF

38 45

C4051

20%
10V
402

2 CERM

149
150
151

C4019

C4004
0.1UF

20%
10V
402

2 CERM

C4018

20%
10V
402

0.1UF

20%
10V
2 CERM
402

C4005
0.1UF
20%
10V
402

2 CERM

38 45
38 40 45

C4052
0.1UF

38 45

20%
10V
2 CERM
402

38 45

C4002
0.1UF

20%
10V
2 CERM
402

C4003
0.1UF

20%
10V
2 CERM
402

38 45

160
161
162

RAM_DQ<108>
RAM_DQ<109>

163 NC
164
165

RAM_DQ<112>
RAM_DQ<117>
RAM_A<13>

166
167
168
169
170

RAM_DQ<119>
RAM_DQ<116>

171
172
173 NC
174

RAM_DQ<120>
RAM_DQ<121>

175
176

38 45
38 45

38 45
38 45
38 40 44

38 45
38 45

38 45
38 45

DIMMS

177
178
179
180
181
182
183
184

RAM_DQ<122>
RAM_DQ<123>
SA0
SA1
SA2

38 45

RS ADJACENT TO VS OR GS
VS ADJACENT TO GS FORBIDDEN

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

SD_B_SA2

R4006

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

10K 2

II NOT TO REPRODUCE OR COPY IT


III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

REV.

051-6772

D
SCALE

38 45

SHT
NONE

40

y
r

RAM_DQ<65>
RAM_DQ<64>

110

10%
6.3V
2 CERM
603

107
108
109

PP1V25_RAM_VREF_DIMM
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
38 45

5%
1/16W
MF-LF
402
ADDR=1(A2/A3)

TABLE_5_HEAD

PART#

7 26 37 40 46

R4008

93

516-0086

=PP2V5_PWRON_RAM
1

a
n
i

RAM_DQ<83>
RAM_DQ<80>
RAM_DQS<10>

34

20%
2 10V
CERM
402

45 38

148
149
150

21
22

0.1UF

45 40 38

144 NC
145
146

19
20

RAM_DQ<71>
RAM_DQ<70>
RAM_CKE<4>

m
il

20%
10V
2 CERM
402

38

1
RAM_A<10>

16
17

RAM_CLK_F_P
RAM_CLK_F_N

38 44

10V
2 CERM

RAM_CLK_C_P
RAM_CLK_C_N

13
14

26

C4023

1
38 40 44

136
137

184

0.1UF

20%
2 10V
CERM
402

183

C4037

20%
2 10V
CERM
402

134 NC
135 NC

181
182

45 38

44 40 38

131
132

180

20%
2 10V
CERM
402

130

178
179

20%
6.3V
2 CERM
1206

38 44

128
129

176
177

10UF

44 40 38

RAM_A<6>
RAM_DQ<26>
RAM_DQ<25>

127

175

45 38

0.1UF

125
126

173 NC
174

45 38

10UF

44 40 38

123
124

172

7 26 37 40 46

38 40 44

122

170
171

45 38

C4036 1 C4006

20%
6.3V
2 CERM
1206

119
120
121

12

18

45 38

117
118

RAM_DQ<66>
RAM_DQ<67>
RAM_DQS<8>

38 44
38 44

=PP2V5_PWRON_RAM
RAM_DQ<17>
RAM_A<12>

TP_J4001_SJRESET_L

10
11

15
38

109
110

169

8
9

38 44

108

167
168

5
6

NC

103 NC FETEN
104

165
166

38 44

101 NC
102 NC

162
163 NC
164

2
3

38 44

100

161

PP1V25_RAM_VREF_DIMM
RAM_DQ<75>

38 44

RAM_DQ<79>
RAM_DQS<9>
RAM_DQ<73>

RAM_DQ<8>
RAM_DQ<12>

7 26 37 40 46

F-28DEG-TH
40

RAM_DQ<11>
RAM_DQ<13>

=PP2V5_PWRON_RAM

J4001

DDR-DIMM-STD

93
94

5
PIN 82:
NC: VDD & VDDQ ARE THE SAME
GND: VDD & VDDQ ARE DIFFERENT

40

OF

04
102

46 45 44

RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5 RAM_VTT

RP4400
82

RP4400
82

RP4401
82

RP4401
82

RP4401
82

RP4401
82

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

20%
10V
2 CERM
402

40 38
40 38
40 38
40 38
40 38
40 38
40 38

46 45 44

0.1UF

46 45 44

PP1V25_RAM_VTT
8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT

RAM_VTT

C4400

RP4400
82

1
40 38

RAM_VTT

RP4400
82

C4412
0.1UF

20%
10V
2 CERM
402

RAM_DQ<7>
RAM_DQ<0>
RAM_DQ<3>
RAM_DQ<2>
RAM_DQ<5>
RAM_DQ<4>
RAM_DQ<1>
RAM_DQ<6>

40 38
40 38
40 38
40 38
40 38
40 38
40 38

RAM_VTT

RP4416
82

RP4416
82

RP4416
82

RP4417
82

RP4417
82

RP4417
82

RP4417
82

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

20%
10V
2 CERM
402

0.1UF

RAM_VTT

RAM_VTT

RAM_VTT 5RAM_VTT

0.1UF

20%
10V
2 CERM
402

40 38
40 38
40 38
40 38
40 38
40 38
40 38

RP4404
82

RP4404
82

RP4405
82

RP4405
82

RP4405
82

RP4405
82

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

20%
2 10V
CERM
402

40 38
40 38
40 38

40 38
40 38
40 38
40 38

0.1UF

C4413
0.1UF

20%
2 10V
CERM
402

RAM_DQ<10>
RAM_DQ<13>
RAM_DQ<11>
RAM_DQ<14>
RAM_DQ<15>
RAM_DQ<12>
RAM_DQ<8>
RAM_DQ<9>

RP4420
82

RP4420
82

RP4420
82

RP4420
82

RP4421
82

RP4421
82

RP4421
82

RP4421
82

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

40 38
40 38
40 38
40 38
40 38
40 38
40 38
40 38

RAM_VTT

C4406
0.1UF

20%
2 10V
CERM
402

120

120

120

120

120

120

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

RAM_DQS<0>
RAM_DQS<1>
RAM_DQS<2>
RAM_DQS<3>
RAM_DQS<4>
RAM_DQS<5>
RAM_DQS<6>
RAM_DQS<7>

y
r

RP4437

C4415

150
5%
1/16W

0.1UF

20%
2 10V
CERM
402

SM-LF

40 38
40 38
40 38
40 38
40 38

40 38
40 38

RAM_VTT

40 38
40 38
40 38
40 38

40 38
40 38
40 38

46 45 44

RAM_VTT

6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5


RAM_VTT

RP4408
82

RP4408
82

RP4409
82

RP4409
82

RP4409
82

RP4409
82

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

20%
2 10V
CERM
402

40 38
40 38
40 38
40 38
40 38
40 38

C4416
0.1UF

20%
2 10V
CERM
402

40 38
40 38
40 38
40 38
40 38
40 38

RAM_VTT

5 RAM_VTT

RP4412
82

RP4412
82

RP4412
82

RP4412
82

RP4413
82

RP4413
82

RP4413
82

RP4413
82

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

20%
10V
2 CERM
402

RAM_DQ<30>
RAM_DQ<28>
RAM_DQ<31>
RAM_DQ<24>
RAM_DQ<29>
RAM_DQ<25>
RAM_DQ<26>
RAM_DQ<27>

7RAM_VTT 6

RAM_VTT

C4403
0.1UF

RP4424
82

RP4424
82

RP4424
82

RP4425
82

RP4425
82

RP4425
82

RP4425
82

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

RAM_DQ<51>
RAM_DQ<48>
RAM_DQ<50>
RAM_DQ<49>
RAM_DQ<52>
RAM_DQ<55>
RAM_DQ<53>
RAM_DQ<54>

e
r
40 38

5RAM_VTT 8
RAM_VTT

m
il

RP4424
82
1

40 38

40 38

0.1UF

RAM_DQ<22>
RAM_DQ<18>
RAM_DQ<19>
RAM_DQ<17>
RAM_DQ<20>
RAM_DQ<16>
RAM_DQ<21>
RAM_DQ<23>

8RAM_VTT 7RAM_VTT 6RAM_VTT

8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT

RAM_VTT

C4402

RP4408
82

5%
1/16W
SM-LF

PP1V25_RAM_VTT

40 38

RAM_VTT

RP4408
82
1
40 38

PP1V25_RAM_VTT

46 45 44

C4405
0.1UF

20%
2 10V
CERM
402

C4417
0.1UF

20%
10V
2 CERM
402

40 38
40 38
40 38
40 38
40 38
40 38
40 38
40 38

SM-LF

40 38
40 38
40 38
40 38

RAM_VTT

C4404

RP4429
82

RP4429
82

RP4429
82

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

20%
10V
2 CERM
402

RAM_DQ<58>
RAM_DQ<62>
RAM_DQ<56>
RAM_DQ<59>
RAM_DQ<57>
RAM_DQ<63>
RAM_DQ<60>
RAM_DQ<61>

0.1UF

0.1UF

20%
10V
2 CERM
402

40 38
40 38
40 38

C4409

RP4436
150

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

20%
2 10V
CERM
402

RP4438
150

RP4439
150

RP4439
150

RP4439
150

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

C4421
0.1UF

20%
2 10V
CERM
402

RP4438
150
3

0.1UF

RP4438
150

RP4439
150
5%
1/16W
SM-LF

RP4441
150

RP4441
150

5%
1/16W
SM-LF

5%
1/16W
SM-LF

RP4441 R4416
150
150
5%
5%
1/16W
SM-LF

RP4442
150

RP4442
150

RP4442
150

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

R4417
150

5%
1/16W
MF-LF
2 402

2 402

R4420
150

C4410
0.1UF

20%
10V
2 CERM
402

C4422
0.1UF

20%
10V
2 CERM
402

R4421
150
5%
1/16W
MF-LF

=PP2V5_RUN_RAM
1

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

R4408
120

C4418

40 38

RP4436
150

PP1V25_RAM_VTT

RAM_VTT
1

RP4436
150

SM-LF

RP4429
82

0.1UF

20%
2 10V
CERM
402

150
5%
1/16W

RP4428
82

RP4436
150

RP4442

RP4428
82

C4420

RP4441_NC
RAM_A<8>
RAM_A<9>
RAM_A<11>
RAM_A<12>
RAM_A<13>

RP4428
82

150
5%
1/16W

20%
2 10V
CERM
402

RP4428
82

RP4437
150

RP4441

0.1UF

40 38

8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT

20%
2 10V
CERM
402

RP4437
150

C4419

46 45 44

RAM_VTT
1

0.1UF

=PP2V5_RUN_RAM

RAM_VTT

PP1V25_RAM_VTT

RAM_VTT

SM-LF

45 44 7

RAM_VTT

C4408

RP4437
150

RAM_A<0>
RAM_A<1>
RAM_A<2>
RAM_A<3>
RAM_A<4>
RAM_A<6>
RAM_A<5>
RAM_A<7>

150
5%
1/16W

46 45 44

RAM_VTT
1

RP4438

PP1V25_RAM_VTT

RAM_VTT

5%
1/16W
MF-LF
2 402

46 45 44

RAM_VTT

120

=PP2V5_RUN_RAM

40 38

RAM_DQ<43>
RAM_DQ<42>
RAM_DQ<40>
RAM_DQ<41>
RAM_DQ<44>
RAM_DQ<45>
RAM_DQ<47>
RAM_DQ<46>

RAM_VTT

5%
1/16W
MF-LF
2 402

RAM_VTT

RAM_VTT

120

a
n
i
45 44 7

8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT

RAM_VTT

C4401

RP4404
82

1
40 38

RAM_VTT

RP4404
82

RAM_VTT

R4400 1R4401 1R4402 1R4403 1R4404 1R4405 1R4406 1R4407

8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6

RAM_VTT

C4414
40 38

46 45 44

PP1V25_RAM_VTT

RAM_VTT
1

RAM_DQ<33>
RAM_DQ<37>
RAM_DQ<35>
RAM_DQ<34>
RAM_DQ<32>
RAM_DQ<39>
RAM_DQ<36>
RAM_DQ<38>

PP1V25_RAM_VTT

PP1V25_RAM_VTT

C4407

RP4416
82
1

40 38

PP1V25_RAM_VTT

46 45 44

R4409
120

R4410
150

R4411
150

7 44 45

C4411
0.1UF

20%
10V
2 CERM
402

RAM_CKE<0>
RAM_CKE<1>
RAM_CS_L<0>
RAM_CS_L<1>

PARALLEL TERM
R4412
4.7K

5%
1/16W
MF-LF
402

R4413
4.7K

R4414
150

R4415
150

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6772

44

OF

04
102

8
46 45 44

PP1V25_RAM_VTT
46 45 44

8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT

RP4500
82

RP4500
82

RP4501
82

RP4501
82

RP4501
82

RP4501
82

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

20%
10V
2 CERM
402

40 38

40 38
40 38
40 38
40 38
40 38

0.1UF

46 45 44

PP1V25_RAM_VTT

RAM_VTT

C4500

RP4500
82

1
40 38

RAM_VTT

RP4500
82

8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT

C4510
0.1UF

20%
10V
2 CERM
402

40 38
40 38
40 38
40 38
40 38
40 38
40 38

C4507

RP4516
82

RP4516
82

RP4516
82

RP4517
82

RP4517
82

RP4517
82

RP4517
82

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

20%
10V
2 CERM
402

0.1UF

RAM_VTT

RAM_VTT
1

46 45 44

46 45 44

8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT

40 38
40 38
40 38
40 38

40 38
40 38
40 38
40 38

RAM_VTT

0.1UF

20%
10V
2 CERM
402

40 38

40 38
40 38
40 38
40 38
40 38
40 38

RP4504
82

RP4504
82

RP4504
82

RP4505
82

RP4505
82

RP4505
82

RP4505
82

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

20%
2 10V
CERM
402

0.1UF

RP4520
82

0.1UF

20%
2 10V
CERM
402

RAM_DQ<79>
RAM_DQ<72>
RAM_DQ<74>
RAM_DQ<75>
RAM_DQ<77>
RAM_DQ<78>
RAM_DQ<76>
RAM_DQ<73>

40 38
40 38
40 38
40 38
40 38
40 38
40 38

PP1V25_RAM_VTT
46 45 44

7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT

RP4508
82

RP4508
82

RP4508
82

RP4509
82

RP4509
82

RP4509
82

RP4509
82

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

20%
2 10V
CERM
402

40 38
40 38
40 38
40 38

40 38
40 38
40 38

0.1UF

20%
2 10V
CERM
402

40 38

40 38
40 38
40 38
40 38
40 38

1
40 38
40 38
40 38
40 38
40 38

40 38
40 38
40 38

RP4512
82

RP4512
82

RP4512
82

RP4512
82

RP4513
82

RP4513
82

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

RAM_DQ<95>
RAM_DQ<94>
RAM_DQ<92>
RAM_DQ<88>
RAM_DQ<93>
RAM_DQ<89>
RAM_DQ<91>
RAM_DQ<90>

P
RAM_VTT

C4503

RP4513
82

RP4513
82

5%
1/16W
SM-LF

5%
1/16W
SM-LF

20%
10V
2 CERM
402

0.1UF

46 45 44

RAM_DQ<117>
RAM_DQ<112>
RAM_DQ<113>
RAM_DQ<114>
RAM_DQ<118>
RAM_DQ<116>
RAM_DQ<115>
RAM_DQ<119>

RAM_VTT

RAM_VTT

RAM_VTT

RAM_VTT

120

120

120

120

120

120

120

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

RAM_DQS<8>
RAM_DQS<9>
RAM_DQS<10>
RAM_DQS<11>
RAM_DQS<12>
RAM_DQS<13>
RAM_DQS<14>
RAM_DQS<15>

RAM_VTT
1

C4508
0.1UF

20%
10V
2 CERM
402

RAM_VTT
1

C4518
0.1UF

20%
10V
2 CERM
402

5%
1/16W
SM-LF
1

RP4521
82

5%
1/16W
SM-LF
2

5%
1/16W
SM-LF
3

RAM_VTT

C4506

RP4521
82

5%
1/16W
SM-LF

20%
10V
2 CERM
402

m
il

0.1UF

y
r

C4505

RP4525
82

RP4525
82

RP4525
82

RP4525
82

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

20%
10V
2 CERM
402

0.1UF

20%
10V
2 CERM
402

RAM_VTT

RP4524
82

C4513

44 7

RP4524
82

RAM_VTT

0.1UF

C4509

0.1UF

C4519
0.1UF

20%
10V
2 CERM
402

20%
10V
2 CERM
402

PP1V25_RAM_VTT

46 45 44

=PP2V5_RUN_RAM

RAM_VTT

C4516

0.1UF

20%
10V
2 CERM
402

40 38
40 38
40 38
40 38
40 38
40 38
40 38
40 38
40 38

RAM_VTT

RAM_VTT

RP4530

RP4531

RP4531

RP4532

RP4532

RP4533

RP4533

150

150

150

150

150

150

150

150

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

2
40 38

RP4530

R4508

R4509

120

120

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

RAM_RAS_L
RAM_BA<0>
RAM_CAS_L
RAM_WE_L
RAM_CS_L<9>
RAM_CS_L<8>
RAM_BA<1>
RAM_A<10>
RAM_CKE<4>
RAM_CKE<5>

RP4530

RP4530

RP4531

RP4531

RP4532

RP4532

RP4533

RP4533

150
5%

150
5%

150
5%

150
5%

150
5%

150
5%

150
5%

150
5%

1/16W
SM-LF

1/16W
SM-LF

1/16W
SM-LF

1/16W
SM-LF

1/16W
SM-LF

1/16W
SM-LF

1/16W
SM-LF

1/16W
SM-LF

R4510 1R4511
4.7K

4.7K

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

PP1V25_RAM_VTT

RAM_VTT

5%
1/16W
SM-LF
4

RP4521
82

RP4524
82

e
r
40 38

8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT

5%
1/16W
SM-LF
3

RP4521
82

RP4524
82
1

PP1V25_RAM_VTT

RP4520
82

8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT

C4514

40 38

46 45 44

5%
1/16W
SM-LF
2

PP1V25_RAM_VTT

0.1UF

RAM_DQ<84>
RAM_DQ<87>
RAM_DQ<85>
RAM_DQ<82>
RAM_DQ<86>
RAM_DQ<80>
RAM_DQ<83>
RAM_DQ<81>

RP4520
82

RAM_DQ<111>
RAM_DQ<105>
RAM_DQ<106>
RAM_DQ<104>
RAM_DQ<109>
RAM_DQ<108>
RAM_DQ<110>
RAM_DQ<107>

RAM_VTT

C4502

RP4508
82
1
40 38

RAM_VTT

RP4520
82

5%
1/16W
SM-LF
1

RAM_VTT

120

a
n
i

8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT

C4501 1 C4511

RP4504
82
2

PP1V25_RAM_VTT

RAM_VTT

40 38

46 45 44

RAM_VTT

R4500 1R4501 1R4502 1R4503 1R4504 1R4505 1R4506 1R4507

40 38

PP1V25_RAM_VTT

RAM_VTT

C4512

RAM_DQ<97>
RAM_DQ<103>
RAM_DQ<96>
RAM_DQ<98>
RAM_DQ<102>
RAM_DQ<100>
RAM_DQ<99>
RAM_DQ<101>

PP1V25_RAM_VTT

40 38

40 38

RAM_VTT

RP4516
82
1

RAM_DQ<64>
RAM_DQ<67>
RAM_DQ<65>
RAM_DQ<66>
RAM_DQ<70>
RAM_DQ<71>
RAM_DQ<68>
RAM_DQ<69>

8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT 8RAM_VTT 7RAM_VTT 6RAM_VTT 5RAM_VTT

C4515
0.1UF

20%
10V
2 CERM
402

40 38
40 38
40 38
40 38
40 38
40 38
40 38
40 38

RAM_VTT

C4504

RP4528
82

RP4528
82

RP4528
82

RP4528
82

RP4529
82

RP4529
82

RP4529
82

RP4529
82

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

20%
2 10V
CERM
402

0.1UF

RAM_VTT
1

C4517
0.1UF

20%
2 10V
CERM
402

RAM_DQ<126>
RAM_DQ<123>
RAM_DQ<127>
RAM_DQ<122>
RAM_DQ<125>
RAM_DQ<124>
RAM_DQ<121>
RAM_DQ<120>

PARALLEL TERM
A

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6772

45

OF

04
102

ONLY STUFF ONE VTT VREG

46 40 37 26 7

=PP2V5_PWRON_RAM
NOSTUFF

D
U4700_REFOUT

VDD
REFOUT

R4603

C4610

10K

0.1UF
10%
16V
X7R
603

RAM_VTT

NOSTUFF
1

C4601

PHILIPS
353S0603

5%
1/16W
MF-LF
402

10UF
20%
6.3V
CERM
805

y
r

VTT 1

RAM_VTT
1

C4606

SHTDWN 4

VR4700_SHTDWN

0.1UF

VSS
3

VSS
U4600

10%
16V
X7R
603

NE57811
SPAK-5

RAM_VTT

NOTE: U4700 PIN 4 IS LOW ACTIVE.

a
n
i

NOSTUFF

PP1V25_RAM_VTT

R4610
3

TURN_ON_VTT

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=1.25V

5%
1/16W
MF-LF
402

3
D

22 11 10 9 8 6

C4609

Q4600

SOT23-LF

20%
2 2V
TANT
7343

220UF

2N7002

SYS_SLEEP

C4608

C4600

10UF

10UF

20%
6.3V
CERM
1206

20%
6.3V
CERM
1206

44 45

C4602
10UF

20%
6.3V
CERM
1206

PLACE 10UF CAPS NEAR DIMMS

=PP5V_PWRON_RAM

m
il

VTT_ALT
1

0.1UF

20%
10V
CERM 2
402

NTD70N03R
CASE369
3

=PP2V5_PWRON_RAM
4

46 40 37 26 7

VTT_ALT

Q4651

VTT_ALT

C4655

.5%
1/16W
603 FF

SEMTECH
353S0880

VTT_ALT
1
VCC

2
1

1K

R4671

VTT_ALT

22uF

20%
2 6.3V
CERM
1206

3 REF

DRVH 6

SC1116ISKTRT
5
4
FB

C4650

VTT_ALT

R4673

GND

R4672

.5%
1/16W
603 FF

1K

5%
402
MF-LF
1/16W

R4673_1
VTT_ALT

0.1UF 1K

20%
10V
2 CERM
402

DRVL
SOT23-6L

VTT_ALT
1

VTT_ALT

C4652

0.0047UF

MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL
U4650_6
MIN_NECK_WIDTH=10MIL
U4650_4
MIN_LINE_WIDTH=25MIL

e
r

U4650

U4650_3

10%
25V
2 CERM
402

NTD70N03R

R4674

1K

VTT_ALT

Q4652
CASE369

VTT_ALT

C4651

5%
402
MF-LF
1/16W

R4674_1

VTT_ALT

C4653

0.0047UF

10%
2 25V
CERM
402

MEM TERM VREGS


A

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6772

46

OF

04
102

ELECTRICAL_CONSTRAINT_SET

R4800
2.2
1

5%
1/10W
MF-LF
603

C4811 C4816
1UF
10%

6.3V
2 CERM
402

0.1UF
20%

2 10V
CERM
402

AGP_AD_0
AGP_AD_1

AGP_DATA
AGP_DATA

AGP_DATA
AGP_DATA

AGP_SB_STBF
AGP_SB_STBS
AGP_AD_STBF<0>
AGP_AD_STBS<0>
AGP_AD_STBF<1>
AGP_AD_STBS<1>

AGP_SB_STBS
AGP_SB_STBS
AGP_AD_STB_0
AGP_AD_STB_0
AGP_AD_STB_1
AGP_AD_STB_1

AGP_STROBE
AGP_STROBE
AGP_STROBE
AGP_STROBE
AGP_STROBE
AGP_STROBE

AGP_STROBE
AGP_STROBE
AGP_STROBE
AGP_STROBE
AGP_STROBE
AGP_STROBE

AGP_DBI_LO
AGP_DBI_HI

AGP_AD_1
AGP_AD_1

AGP_DATA
AGP_DATA

AGP_DATA
AGP_DATA

I55

AGP_AD<15..0>
AGP_AD<31..16>

AGP_AD_0
AGP_AD_1

AGP_DATA
AGP_DATA

AGP_DATA
AGP_DATA

I57

49 48

49 48

AGP_SBA_L<7..0>

AGP_SBA

AGP_DATA

AGP_DATA

I59

49 48

49 48
49 48
49 48

VDD_AGP

49 48

OMIT

49 48

U3

AG8 AGP_CBE0
AF8 AGP_CBE1

AGP_CBE<0>
AGP_CBE<1>

49 48
49 48

49 48

49 48
49 48

U3LITE
V1.0-300MM

AGP_AD0 AB11
AGP_AD1 AA11

PBGA

AGP_AD2 AG11

(SYM 4 OF 7)

AGP_DBI_LO

AA6 AGP_DBI_LO

AGP_AD_STBF<0>
AGP_AD_STBS<0>

AE8 AGP_AD_STBF0
AD8 AGP_AD_STBS0

AGP_AD5

AGP_AD8
AGP_AD9
AGP_AD10

AGP
INTERFACE

AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15

49 48

Y8 AGP_CBE2
AA5 AGP_CBE3

49 48

AGP_DBI_HI

AA4 AGP_DBI_HI

AGP_AD19

AGP_AD_STBF<1>
AGP_AD_STBS<1>

AA3 AGP_AD_STBF1
AA2 AGP_AD_STBS1

AGP_AD20
AGP_AD21

49 48
49 48

AGP_AD22

AGP_AD25

AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31

AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7

49
49
49

49
49
49
49
49
49

49

AGP_PAR

AH7 AGP_PAR

AGP_ST<0>
AGP_ST<1>
AGP_ST<2>

AC4 AGP_ST0
AC1 AGP_ST1
AB1 AGP_ST2

AGP_RBF
AGP_WBF
AGP_TRDY
AGP_IRDY
AGP_GNT
AGP_FRAME
AGP_DEVSEL

AC6
AD6
AH5
AG6
AC3
AH6
AF6

AGP_SBA_L<0>
AGP_SBA_L<1>
AGP_SBA_L<2>
AGP_SBA_L<3>
AGP_SBA_L<4>
AGP_SBA_L<5>
AGP_SBA_L<6>
AGP_SBA_L<7>

AGP_SBA1 AF3
AGP_SBA2 AH1
AGP_SBA3

49

Y5
AA1
Y2
Y1
Y7
V5
V6
V4
V3
V8
V7
W1
AA7

AGP_SBA0 AG2

AD1 AGP_SB_STBF
AE1 AGP_SB_STBS

AGP_SB_STBF
AGP_SB_STBS

49 48

AGP_AD<16>
AGP_AD<17>
AGP_AD<18>
AGP_AD<19>
AGP_AD<20>
AGP_AD<21>
AGP_AD<22>
AGP_AD<23>
AGP_AD<24>
AGP_AD<25>
AGP_AD<26>
AGP_AD<27>
AGP_AD<28>
AGP_AD<29>
AGP_AD<30>
AGP_AD<31>

AGP_AD17 Y3
AGP_AD18 Y6

AGP_AD23
AGP_AD24

49 48

AD11
AE11
AF11
AH8
AH9
AH10
AH11
AG9
AF9
AE9
AD9

AGP_AD16 Y4

AGP_CBE<2>
AGP_CBE<3>

49 48

AGP_AD<0>
AGP_AD<1>
AGP_AD<2>
AGP_AD<3>
AGP_AD<4>
AGP_AD<5>
AGP_AD<6>
AGP_AD<7>
AGP_AD<8>
AGP_AD<9>
AGP_AD<10>
AGP_AD<11>
AGP_AD<12>
AGP_AD<13>
AGP_AD<14>
AGP_AD<15>

AGP_AD3 AH12
AGP_AD4 AC11
AGP_AD6
AGP_AD7

DBIHI AND DBILO


GROUPS WITH STROBE1
FOR CONSTRAINTS

AGP_REFCLK AH2

AGP_BUSY*
AGP_STP_AGP*

AGP_RBF
AGP_WBF

AGP_IRDY
AGP_GNT

AGP_FRAME
AGP_DEVSEL

AGP_CLK66M_NB

AC8
AD4

e
r

AGP_TRDY

AB9 AGP_REQ
AH4 AGP_STOP

AGP_REQ
AGP_STOP

49

NB_AGP_BUSY_L
NB_STOP_AGP_L

=PP1V5_AGP

7 48 49 50

10V
2 CERM
402

0.1UF
20%

2 10V
CERM
402

0.1UF
20%

10V
2 CERM
402

0.1UF
20%

2 10V
CERM
402

0.1UF
20%

10V
2 CERM
402

48 49
49 48
48 49

I46
I48

48 49

AGP_SB_STB
AGP_SB_STB
AGP_AD_STB0
AGP_AD_STB0
AGP_AD_STB1
AGP_AD_STB1

I49
I50
I51
I52
I53
I54

y
r

48 49

48 49
48 49
48 49

I56

I58

DBI_HI IS NOT A STROBE BUT SHARES THE SAME TOPOLOGY AS A STROBE

48 49
48 49
48 49

a
n
i

48 49
48 49
48 49

48 49

LEVEL SHIFTER FOR U3LITE

48 49
48 49

AGP BUSY AND STOP ARE NOT USED IN ALL DESIGNS

48 49
48 49

59 58 56 50 49 48 7

48 49
48 49
48 49
48 49
48 49
48 49
48 49

=PP3V3_AGP

50 49 48 7

AGP_BUSYSTOP

10K

5%
1/16W
MF-LF
2 402

48 49
48 49
48 49

48 49
48 49
48 49
48 49
48 49

48 49
48 49

48 49

27

10K

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

NB_AGP_BUSY_L

AGP_BUSY_L_F
6

AGP_BUSYSTOP

Q4801

AGP_BUSYSTOP

Q4801

2N7002DW

SOT-363

SOT-363

59 58 56 50 49 48 7

59 58 56 50 49 48 7

48

2N7002DW

AGP_BUSY_L

48

R4807

10K

R4811

R4812

48 49

=PP1V5_AGP

=PP3V3_AGP

=PP3V3_AGP

48

50 49 48 7

=PP1V5_AGP

R4810

AGP_BUSYSTOP
1

5%
1/16W
MF-LF
2 402

10K

5%
1/16W
MF-LF
2 402

R4813

NB_STOP_AGP_L

1K

5%
1/16W
MF-LF
402

49

STOP_AGP_L

STOP_AGP_L_F

AGP_BUSYSTOP
48

5%
1/16W
MF-LF
2 402

10K

R4809

10K

R4808

TP_AGP_MB_AGP8X_DET_L

3 AGP_BUSYSTOP
3

Q4803

AGP_BUSYSTOP

Q4802

2 STOP_AGP_L_R 1

2N3904LF

2N7002

SOT23-LF

SOT23
2

AGP_REFCLK_AVSS

C4817
0.01UF

20%
2 16V
CERM
402

MASTER: SEEDY
LAST MODIFIED: NOV 18, 04

U3LITE AGP

C4800 1 C4801 1 C4802 1 C4803 1 C4804 1 C4805 1 C4806 1 C4807 1 C4808


0.1UF
20%

49 48
48 49

1%
1/16W
MF-LF
402

TP_VREF_CG
AGP_VREF_GC

AGP_MB_AGP8X_DET AA8

AE5

49

48 49

R4801
182

AGP_VREFCG AC5

AC9 AGP_TYPEDET
AB8 AGP_GC_AGP8X_DET

AGP_TYPEDET_L
NB_AGP_GCDET_L

49 48

PVTREF RESISTOR

AGP_VREFGC AA9

49

48 49

m
il

AG3
AD2
AF2
AG1
AF1

AGP_PVTREF1 AG5 AGP_PVTREF1


AGP_PVTREF2 AF5 AGP_PVTREF2

49

DIFFERENTIAL_PAIR

7 48 49 50

49 48

AGP
REFCLK_AVDD

NET_SPACING_TYPE

AGP_CBE<1..0>
AGP_CBE<3..2>

49 48

=PP1V5_AGP

PP1V5_PWRON_AGP_NB_AVDD
VOLTAGE=1.5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
1
1

AG4
AG10
AE2
AE7
AC10
AB4
Y11
W2
W6
W10
V9

=PP1V5_PWRON_NB_AVDD

AE6

60 37 28 7

NET_PHYSICAL_TYPE

0.1UF
20%

2 10V
CERM
402

0.1UF
20%

10V
2 CERM
402

0.1UF
20%

2 10V
CERM
402

0.1UF
20%

10V
2 CERM
402

C4810 1 C4812 1 C4813 1 C4814 1 C4815


0.1UF
20%

2 10V
CERM
402

0.1UF
20%

10V
2 CERM
402

0.1UF
20%

2 10V
CERM
402

0.1UF
20%

2 10V
CERM
402

NOTICE OF PROPRIETARY PROPERTY

0.1UF
20%

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

2 10V
CERM
402

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT

NONE

REV.

051-6772
04
48 102
OF

TABLE_5_HEAD

PART#

QTY

DESCRIPTION

REFERENCE DESIGNATOR(S)

BOM OPTION

50 49 48 7

=PP1V5_AGP

TABLE_5_ITEM

338S0231

IC,RV351LEP, GRAPHICS CTLR

U4900
1

C4900
1UF

10%
6.3V
2 CERM
402

U3LITE AGP I/O REFERENCE

C4901
1UF

C4902
0.01UF

20%
16V
2 CERM
402

10%
6.3V
2 CERM
402

C4903

0.01UF

C4904
0.01UF

20%
16V
2 CERM
402

20%
16V
2 CERM
402

C4905
0.01UF

20%
16V
2 CERM
402

R4914

1%
1/16W
MF-LF
2 402

48

27

48

R4940 1 C4940
1.02K

48

0.01UF

1%
1/16W
MF-LF
2 402

48

20%
2 16V
CERM
402

48
48
48
48
48
48
48
48
48
48
48
48

GPU AGP I/O REFERENCE

48

(PLACE CLOSE TO GPU AGP BALLS)

48
48
48

=PP1V5_AGP

48

AGP 3.0
0.233 * VDDP
0.35V

R4906
3.32K

48
48
48

1%
1/16W
MF-LF
2 402

48
48
48

GPU_AGP_VREF

48

49

VOLTAGE=0.35V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

48
48

R4907 1 C4957
1.02K

48

0.01UF
20%

48

2 16V
CERM
402

48

48
48
48
48
48

DO WE NEED THE SERIES R?

48

GPU_RESET_L

48

5%
1/16W
MF-LF
402

48
48
48

48
48
48
48
48

U3LITE SIGNALS

48

NB_AGP_GCDET_L

48

AGP_TYPEDET_L
1

R4913 1R4909
0

5%
1/16W
MF-LF
2 402

10K

5%
1/16W
MF-LF
2 402

AGP_CLK66M_GPU
AGP_AD<0>
AGP_AD<1>
AGP_AD<2>
AGP_AD<3>
AGP_AD<4>
AGP_AD<5>
AGP_AD<6>
AGP_AD<7>
AGP_AD<8>
AGP_AD<9>
AGP_AD<10>
AGP_AD<11>
AGP_AD<12>
AGP_AD<13>
AGP_AD<14>
AGP_AD<15>
AGP_AD<16>
AGP_AD<17>
AGP_AD<18>
AGP_AD<19>
AGP_AD<20>
AGP_AD<21>
AGP_AD<22>
AGP_AD<23>
AGP_AD<24>
AGP_AD<25>
AGP_AD<26>
AGP_AD<27>
AGP_AD<28>
AGP_AD<29>
AGP_AD<30>
AGP_AD<31>
AGP_SBA_L<0>
AGP_SBA_L<1>
AGP_SBA_L<2>
AGP_SBA_L<3>
AGP_SBA_L<4>
AGP_SBA_L<5>
AGP_SBA_L<6>
AGP_SBA_L<7>

AG30
H29
H28
J29
J28
K29
K28
L29
L28
N28
P29
P28
R29
R28
T29
T28
U29
N25
R26
P25
R27
R25
T25
T26
U25
V27
W26
W25
Y26
Y25
AA26
AA25
AA27
AD28
AD29
AC28
AC29
AA28
AA29

PCICLK
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15

y
r

C4910

P23
T23

N30

AF27
J30

AC27

AE30

AB30
AC23

W30
Y27

V24

M23
M24

20%
16V
2 CERM
402

48
48

48
48

Y28
Y29

AGP_ST<0>
AGP_ST<1>
AGP_ST<2>

AF29
AD27

ST0
ST1
ST2

AF28

V29
V28

W29

W28
AC26
AE29

M26

CBE0*
CBE1*

N29

PLACE C4910 CLOSE TO BALL M26

U28

AGP_CBE<0>
AGP_CBE<1>

AB26

AGP_DBI_LO

AD_STBF_0
AD_STBS_0*

M28

AGP_AD_STBF<0>
AGP_AD_STBS<0>

CBE2*
CBE3*

P26

M29

48
48

DBI_HI
AD_STBF_1
AD_STBS_1*

SB_STBF
SB_STBS*

PAR

INTA*

AGPTEST*

REQ*
GNT*
STOP*
DEVSEL*
TRDY*
IRDY*
FRAME*
WBF*
RBF*

AGP8X_DET*

48

a
n
i

AGP

48
48

U26

AGP_CBE<2>
AGP_CBE<3>

48

AB25

AGP_DBI_HI

48

V25
V26

AGP_AD_STBF<1>
AGP_AD_STBS<1>

m
il

RST*

AD26
N26

AGPREF

DBI_LO

SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7

AG28

AGP_REQ
AGP_GNT
AGP_STOP
AGP_DEVSEL
AGP_TRDY
AGP_IRDY
AGP_FRAME
AGP_WBF
AGP_RBF

RV351
(1 OF 5)

AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

ATI_PCIRST_L

AE28

U4900
BGA

e
r
48

R4912

49

0.01UF

VOLTAGE=0.35V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

1%
1/16W
MF-LF
2 402

OMIT
AGP_VREF_GC

50 49 48 7

D
GPU_AGP_VREF

VDDP

3.32K

U27
V23

=PP1V5_AGP

T24
T30

50 49 48 7

P27

AA23
AA24

(PLACE CLOSE TO GPU AGP BALL)

AB29
AB28

M25

48

48
48

AGP_SB_STBF
AGP_SB_STBS

48

48

=PP3V3_AGP

R4908
10K

5%
1/16W
MF-LF
2 402

48

AE26

GPU_AGPTEST_L

AC25

AGP VERSION SELECT

7 48 50 56 58 59

AGP_PAR

M27

AGP_INT_L

R4910
1

47

=PP1V5_AGP

25

7 48 49 50

1%
1/16W
MF-LF
402

(LOW = AGP V3.X)


(HIGH = AGP V2.X)

GPU AGP

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-6772

04

OF

49

102

GPU VCORE VREG

NOTE:
SET OUTPUT = 1.20V +/- 5% FOR RV351LE
IRU3037ACS VREF = 0.8 VDC
VOUT=VREF*(R5003+R5005)/R5005 = 1.199 VDC

59 7

=PP12V_AGP

59 7

=PP5V_AGP

59 58 56 50 49 48 7

R5000

D
C5004
1UF

20%
25V
CERM 2
805

20%
2 25V
CERM
805

5%
1/8W
MF-LF
2 805

C5016
1UF

4.7

10UF

VC

HD
8

U5000_SS

1800UF

C5003
1800UF

20%
2 6.3V
ELEC
TH-KZJ

=PP3V3_AGP

U5000_GATE_L

FB

U5000_FEEDBACK

1%
1/16W
MF-LF
2 402

Q5002
NTD60N02R

1
G

C5006
220PF

5%
2 50V
CERM
603

C5023

NOSTUFF

0.51
D 4

CASE369
S3

5%
2 25V
CERM
402

C5005

C5008

10UF

C5012

R5005

20%
2 6.3V
ELEC
TH-KZJ

10K

1%
1/16W
MF-LF
2 402

CRITICAL

SOP-8

C5080

NOSTUFF

10UF

IN
EN

R5080

U5080_ADJ

R5081

453

C5083
330UF

1%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

20%
2 6.3V
ELEC
SM-1

R5082
1K

R5085
58 51 50

PP2V5_GPU_A2VDD

1%
1/16W
MF-LF
2 402

U5080_EN

5%
1/16W
MF-LF
402

C5082
0.01UF
10%
16V
CERM
402

GPU 1.50V VDDC_CT

P
=PP3V3_AGP

THIS RAIL SHOULD BE THE LAST UP AND THE FIRST DOWN

R5092
0

59 58 56 50 49 48 7

=PP3V3_AGP

CRITICAL

4.7UF
20%
6.3V
CERM
805

U5090
2

SOT23-6

58 51 50

PP2V5_GPU_A2VDD

5%
1/16W
MF-LF
402

VOUT 6

VIN
PG
3 EN
4

U5090_EN
1

C5095
0.1UF

ADJ 5
GND

C5091

10%
50V
2 CERM
402

R5090

59 58 56 50 49 48 7

C5070 1R5070
1UF

VOUT 5

VIN

CONT NOISE

10K

U5070_NOISE

C5071 1

GND

5%
1/16W
MF-LF
2 402

0.01UF

20%
16V
CERM 2
402

1%
1/16W
MF-LF
2 402

R5091

C5072
10UF

20%
2 6.3V
CERM
805

PP1V8_GPU_TPVDD
58
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

CRITICAL

4.7UF
20%
6.3V
CERM
805

U5060
2

SOT23-6

58 51 50

PP2V5_GPU_A2VDD

VOUT 6

VIN
4 PG
3 EN

C5061

0.001UF

FAN2558
1

1
1

ADJ 5

10%
50V
2 CERM
402

R5060
100K

1%
1/16W
MF-LF
2 402
1

GND

C5062
1uF

U5060_ADJ
1

R5061

10%
6.3V
2 CERM
402

48.7K

1%
1/16W
MF-LF
2 402

C5092
1uF

FAN2558_ADJ

U5070_CONT

C5060 1

GRAPHICS VREGS

10%
6.3V
2 CERM
402

NOTICE OF PROPRIETARY PROPERTY


VOUT = 0.59V * [1 + R5060 / R5061]
VOUT = 1.80V

1%
1/16W
MF-LF
2 402

20%
10V
2 CERM
402

PP2V5_GPU_A2VDD 50 51 58
VOLTAGE=2.5V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

SOT-25A

=PP3V3_AGP

100K

PLACE LED5000 NEAR VREG

U5070

7 48 49 50 56 58 59

64.9K

LED_GPU_CORE_N

GPU 1.80V TPVDD

PP1V5_GPU_VDDC_CT 51
VOLTAGE=1.5V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

0.001UF

FAN2558
1

R5095
2.0K 2
1

5%
1/8W
MF-LF
805

C5090 1

GND

10BQ040PBF

NOSTUFF

=PP1V5_AGP

13

U1001

11

1V1_REF

MM1572FN

20%
10V
2 CERM
805

D5090
SMB

49 48 7

=PP3V3_AGP

e
r

NOSTUFF
1

51 52 58

59 58 56 50 49 48 7

GND

3.3K

20%
2 6.3V
CERM
1206

OUT
ADJ

m
il

PP1V8_GPU
=PP1V8_GPU
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM
MAKE_BASE=TRUE

U5080
MIC39102

SOI

GPU 2.5V A2VDD

GPU 1.8V VREG


2

V+

34 22 10

GREEN
2.0X1.25A

LM339A

10

12

U5000_FEEDBACK

PP2V5_GPU

GPU_CORE_FOR_LED

5%
1/16W
MF-LF
402

C5009
1800UF

20%
2 6.3V
CERM
805

DEVELOPMENT

LED5000

DEVELOPMENT

a
n
i
0

20%
50V
2 CERM
1206

R5020

1%
1/16W
MF-LF
2 402

R5004_P2

0.1UF

2200PF

10%
50V
2 CERM
402

10%
2 50V
CERM
603

DEVELOPMENT

1
C5007 R5003
4.99K

3300PF

5%
1/4W
FF
2 1206

5%
2 50V
CERM
603

0.0018UF

55 54 52 7

LED_GPU_CORE_P

R5004

20PF

R5001_2

C5013

5%
1/16W
MF-LF
2 402

7 22 51

TH

4
1

VOLTAGE=1.2V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM

1.6UH

GND

61.9K

330

PPVCORE_GPU

L5001

COMP

R5001

R5019

10BQ040PBF

S3

6 7 10 11 18 22 34

DEVELOPMENT

Q5002_DRAIN

LD

y
r
PP3V3_RUN

CASE369

U5000_GATE_H

7 48 49 50 56 58 59

D5000
SMB

NTD60N02R

1
G

Q5001_GATE

C5002

20%
2 6.3V
ELEC
TH-KZJ

SS

U5000_COMP

20%
2 16V
CERM
603

Q5001

5%
1/8W
MF-LF
805

IRU3037ACS
SOI

0.1UF

10UF

20%
6.3V
2 CERM
1206

D 4

R5002

U5000

C5014

C5001 1 C5010

20%
6.3V
2 CERM
1206

U5000_VC

VCC

PEAK CURRENT OF TOTAL RAILS


5A WITH RV351LE

=PP3V3_AGP

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT

VOUT = 0.59V * [1 + R5090 / R5091]


VOUT = 1.50V

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

POWER SEQUENCING FOR RV351: =PP3V3_AGP > PP2V5_GPU > PPVCORE_GPU > VDDC_CT
PP2V5_GPU_A2VDD > PP1V8_GPU
HOWEVER IDEALLY ALL POWER RAILS SHOULD RAMP TOGETHER

SIZE

APPLE COMPUTER INC.

SHT
NONE

REV.

051-6772

SCALE

POWER DOWN SEQUENCE SHOULD BE IN REVERSE ORDER

DRAWING NUMBER

04

OF

50

102

NOSTUFF

W12

V14

V17
V18

V12
V13

U14

U17
U18
U19

P19
U13

P14
P17

P18

P12
P13

N18
N19

N12

N14
N17

M19

M14
M17
M18

M13

M12
AD15

AD13

W19
AC17

W14
W17
W18

PPVCORE_GPU
AC13

51 50 22 7

5
V19
W13

AC15
N13
U12

C5100
10UF

20%
6.3V
2 CERM
805

VDDC
AJ1

OMIT

AG9
AG5

U4900

AG27

RV351

BGA

AG22
AG18

(2 OF 5)

AG15

C5101
1UF

10%
2 6.3V
CERM
402

AG11
AF20

1UF

10%
2 6.3V
CERM
402

AE16

AD30
AD25

C5105

0.01UF

20%
2 16V
CERM
402

AD16

a
n
i
1

0.01UF

20%
16V
2 CERM
402

AB4

AB27
AB24

L5130
58 52 50

AB23

1.8UH

=PP1V8_GPU
1

2
0805

PP1V8_GPU_PVDD
VOLTAGE=1.8V
NOSTUFF
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM 1

C5130
10UF

XW5130
SM

GND_GPU_PVSS
VOLTAGE=0V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

20%
6.3V
2 CERM
805

AB1
AA30

A29

C5131

A22
AD18

1UF

10%
6.3V
2 CERM
402

AK28

PVDD
PVSS

AJ28

25MA MAX

Y4
W8

PP1V5_GPU_VDDC_CT

C5140
1UF

10%
6.3V
2 CERM
402

C5141
1UF

10%
6.3V
2 CERM
402

C5142
1UF

10%
6.3V
2 CERM
402

C5143
1UF

10%
6.3V
2 CERM
402

PP1V8_GPU_TXVDDR

m
il

AE15

L5150

FERR-220-OHM
2
0805

PP2V5_GPU_VDDL1
VOLTAGE=2.5V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

VDDL0

AE17
AE20

PPVCORE_GPU

M15
R19

VSS

20%
16V
2 CERM
402

C5115
0.01UF

20%
16V
2 CERM
402

0.01UF

C5116
0.01UF

20%
16V
2 CERM
402

C5109

0.01UF

20%
2 16V
CERM
402

0.01UF

0.01UF

20%
2 16V
CERM
402

C5117

20%
16V
2 CERM
402

C5110

C5111

20%
2 16V
CERM
402

C5118
0.01UF

20%
16V
2 CERM
402

0.01UF

C5112
0.01UF

20%
2 16V
CERM
402

C5119
0.01UF

20%
16V
2 CERM
402

C5120
0.01UF

20%
16V
2 CERM
402

U15
T27
T19
T18
T17
T16
T14
T13
T1
R8
R7
R30
R24
R23

R18

W16

0.01UF

C5108

20%
2 16V
CERM
402

20%
2 16V
CERM
402

U23
U16

VDDCI

T12

C5114

0.01UF

U8
U4

VDDL1

e
r
51 50 22 7

C5107

V16

P8
Y23

AF21
AJ20

W15
V30

VDD15

L23

58

PP2V5_GPU_A2VDD

10%
2 6.3V
CERM
402

W23

H11
H20

Y8

58 50

C5104

W27
W24

AC20
1

1UF

10%
2 6.3V
CERM
402

W7

AC11
50

C5113

C5106

20%
2 16V
CERM
402

AC18

AB8
AB7

C5103
1UF

0.01UF

AD12
AC4
AC16
AC14

y
r

AF15
AE19

CORE POWER

C5102

R17
R15
R14
R13
R12
P4
P16
P15
N27
N24
N23
N15
M8
M7
M30
M16
L4
K8
K7
K30
K27
K23
K1
H9

GPU CORE POWER

H8
H4
H27

NOTICE OF PROPRIETARY PROPERTY

H23
H21

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

H18

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT

VSS
H16

G9
H12

G24

G18
G21

G16

F27
G12

E4

D4
D9

D25
D27

D24

D18
D21

D15

D10
D12

C30

C1
C28

AK25
AK29

AK2

AJ19
AJ30

AE27

V15

A2
AC12

R16
T15

K24
N16

H14

C3
D6

A16

A10

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART


SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-6772

04

OF

51

102

7
55 54 52 50 7

PP2V5_GPU

C5200 1 C5201
10UF

10UF

20%
6.3V
2 CERM
805

20%
6.3V
2 CERM
805

C5202 1 C5203
1UF

1UF

10%
6.3V
2 CERM
402

10%
6.3V
2 CERM
402

C5204 1 C5205
1UF

10%
6.3V
2 CERM
402

0.01UF

20%
16V
2 CERM
402

C5206 1 C5207
0.01UF

20%
16V
2 CERM
402

0.01UF

20%
16V
2 CERM
402

C5208 1 C5209
0.01UF

0.01UF

C5210 1 C5211
0.01UF

20%
16V
2 CERM
402

20%
16V
2 CERM
402

20%
16V
2 CERM
402

0.01UF

20%
16V
2 CERM
402

C5212
0.01UF

20%
16V
2 CERM
402

L5230

53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53

10MA MAX

53
53
53
53
53
53
53
53
53
53
53
53
53
53

A15
A21
D11
F4
H17
M4
T8
V4
V7
V8
A28
A3
A9
AA1
AA4
AA7
AA8
AD4
B1
B30
D13
D14
D17
D19
D20
D23
D26
D5

N6

PP1V8_GPU_MPVDD
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14

OMIT

U4900
RV351
BGA

(3 OF 5)

E22
B22
B23
B24
C23
C22
F22
F21
C21
A24
C24
A25
E21
B20
C19

DQMA0*
DQMA1*
DQMA2*
DQMA3*
DQMA4*
DQMA5*
DQMA6*
DQMA7*

J25
F29
E25
A27
F15
C15
C11
E11

QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7

J27
F30
F24
B27
E16
B16
B11
F10

FBA<0>
FBA<1>
FBA<2>
FBA<3>
FBA<4>
FBA<5>
FBA<6>
FBA<7>
FBA<8>
FBA<9>
FBA<10>
FBA<11>
FBA<12>
FBA<13>
TP_FBA<14>
FBDQM<5>
FBDQM<4>
FBDQM<7>
FBDQM<6>
FBDQM<0>
FBDQM<1>
FBDQM<3>
FBDQM<2>

GND_GPU_MPVSS
VOLTAGE=0V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

53 54

NOSTUFF
1

C5230
10UF

XW5230
SM

VDDR1

53

53 54

53

53 54

53

53 54

53

53 54

53

53 54

53

53 54

53

53 54

53

53 54

53

53 54

53

53 54

53

53 54

53

53 54

53

53 54

53
53
53

53 54
53
53 54
53
53 54
53
53 54
53
53 54
53
53 54
53
53 54
53
53 54
53

FBDQS<5>
FBDQS<4>
FBDQS<7>
FBDQS<6>
FBDQS<0>
FBDQS<1>
FBDQS<3>
FBDQS<2>

53
53
53
53
53
53
53
53
53
53

53

53

53

53

53

53

FBACAS_L

54

WEA* E19
CSA0* E20

FBAWE_L

54

FBACS0_L

54

CSA1* F20
CKEA B19

TP_FBACS1_L

MVREFD
MVREFS

VSSRH1
M6

54

53
53
53
53
53
53
53

e
r
CLKA0 B21
CLKA0* C20
CLKA1 C18
CLKA1* A18

VSSRH0

53

FBARAS_L

B7

FBACLK0
FBACLK0_L
FBACLK1
FBACLK1_L

53 54

53 54

53 54
53 54

GPU_MVREFD

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

B8

DIMA_0 D30
DIMA_1 B13

GPU_MVREFS

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

TP_GPU_DIMA_0
TP_GPU_DIMA_1

C5231
1UF

FBD<104>
FBD<107>
FBD<106>
FBD<111>
FBD<109>
FBD<110>
FBD<108>
FBD<105>
FBD<96>
FBD<97>
FBD<98>
FBD<99>
FBD<100>
FBD<101>
FBD<102>
FBD<103>
FBD<120>
FBD<121>
FBD<123>
FBD<122>
FBD<124>
FBD<126>
FBD<125>
FBD<127>
FBD<116>
FBD<113>
FBD<118>
FBD<112>
FBD<114>
FBD<119>
FBD<115>
FBD<117>
FBD<64>
FBD<65>
FBD<66>
FBD<67>
FBD<68>
FBD<70>
FBD<69>
FBD<71>
FBD<72>
FBD<73>
FBD<75>
FBD<74>
FBD<76>
FBD<77>
FBD<78>
FBD<79>
FBD<80>
FBD<81>
FBD<82>
FBD<83>
FBD<84>
FBD<85>
FBD<86>
FBD<87>
FBD<88>
FBD<89>
FBD<90>
FBD<91>
FBD<92>
FBD<93>
FBD<94>
FBD<95>

FBACKE

53

54

53

R5200
10K

53

5%
1/16W
MF-LF
2 402

53
53
53
53
53

PP2V5_GPU

7 50 52 54 55

53
53

R5220

53

100

53

1%
1/16W
MF-LF
2 402

53
53
53

C5221 1

R5221

0.1UF
20%
10V
CERM
402

53

100

53

1%
1/16W
MF-LF

53
53

2 402

53
53
53

PP2V5_GPU

A7 MPVDD
A6 MPVSS
D7 DQB0
F7 DQB1
E7 DQB2
G6 DQB3
G5 DQB4
F5 DQB5
E5 DQB6
C4 DQB7
B5 DQB8
C5 DQB9
A4 DQB10
B4 DQB11
C2 DQB12
D3 DQB13
D1 DQB14
D2 DQB15
G4 DQB16
H6 DQB17
H5 DQB18
J6 DQB19
K5 DQB20
K4 DQB21
L6 DQB22
L5 DQB23
G2 DQB24
F3 DQB25
H2 DQB26
E2 DQB27
F2 DQB28
J3 DQB29
F1 DQB30
H3 DQB31
U6 DQB32
U5 DQB33
U3 DQB34
V6 DQB35
W5 DQB36
W4 DQB37
Y6 DQB38
Y5 DQB39
U2 DQB40
V2 DQB41
V1 DQB42
V3 DQB43
W3 DQB44
Y2 DQB45
Y3 DQB46
AA2 DQB47
AA6 DQB48
AA5 DQB49
AB6 DQB50
AB5 DQB51
AD6 DQB52
AD5 DQB53
AE5 DQB54
AE4 DQB55
AB2 DQB56
AB3 DQB57
AC2 DQB58
AC3 DQB59
AD3 DQB60
AE1 DQB61
AE2 DQB62
AE3 DQB63

y
r

VDDR1

OMIT

U4900
RV351
BGA

(4 OF 5)

N5
M1
M3
L3
L2
M2
M5
P6
N3
K2
K3
J2
P5
P3
P2

FBBA<0>
FBBA<1>
FBBA<2>
FBBA<3>
FBBA<4>
FBBA<5>
FBBA<6>
FBBA<7>
FBBA<8>
FBBA<9>
FBBA<10>
FBBA<11>
FBBA<12>
FBBA<13>
TP_FBBA<14>

DQMB0*
DQMB1*
DQMB2*
DQMB3*
DQMB4*
DQMB5*
DQMB6*
DQMB7*

E6
B2
J5
G3
W6
W2
AC6
AD2

FBDQM<13>
FBDQM<12>
FBDQM<15>
FBDQM<14>
FBDQM<8>
FBDQM<9>
FBDQM<10>
FBDQM<11>

QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7

F6
B3
K6
G1
V5
W1
AC5
AD1

FBDQS<13>
FBDQS<12>
FBDQS<15>
FBDQS<14>
FBDQS<8>
FBDQS<9>
FBDQS<10>
FBDQS<11>

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14

a
n
i

m
il

53

RASA* A19
CASA* E18

10%
6.3V
2 CERM
402

20%
6.3V
2 CERM
805

53

F19

53

DQA0
DQA1
DQA2
DQA3
DQA4
DQA5
DQA6
DQA7
DQA8
DQA9
DQA10
DQA11
DQA12
DQA13
DQA14
DQA15
DQA16
DQA17
DQA18
DQA19
DQA20
DQA21
DQA22
DQA23
DQA24
DQA25
DQA26
DQA27
DQA28
DQA29
DQA30
DQA31
DQA32
DQA33
DQA34
DQA35
DQA36
DQA37
DQA38
DQA39
DQA40
DQA41
DQA42
DQA43
DQA44
DQA45
DQA46
DQA47
DQA48
DQA49
DQA50
DQA51
DQA52
DQA53
DQA54
DQA55
DQA56
DQA57
DQA58
DQA59
DQA60
DQA61
DQA62
DQA63

2
0805

MEMORY INTERFACE A

53

L25
L26
K25
K26
J26
H25
H26
G26
G30
D29
D28
E28
E29
G29
G28
F28
G25
F26
E26
F25
E24
F23
E23
D22
B29
C29
C25
C27
B28
B25
C26
B26
F17
E17
D16
F16
E15
F14
E14
F13
C17
B18
B17
B15
C13
B14
C14
C16
A13
A12
C12
B12
C10
C9
B9
B10
E13
E12
E10
F12
F11
E9
F9
F8

VDDRH1

F18
53

FBD<40>
FBD<41>
FBD<43>
FBD<42>
FBD<44>
FBD<46>
FBD<45>
FBD<47>
FBD<35>
FBD<38>
FBD<39>
FBD<37>
FBD<36>
FBD<32>
FBD<33>
FBD<34>
FBD<59>
FBD<56>
FBD<57>
FBD<58>
FBD<60>
FBD<62>
FBD<61>
FBD<63>
FBD<49>
FBD<48>
FBD<54>
FBD<50>
FBD<51>
FBD<55>
FBD<52>
FBD<53>
FBD<0>
FBD<1>
FBD<2>
FBD<3>
FBD<5>
FBD<6>
FBD<4>
FBD<7>
FBD<9>
FBD<8>
FBD<11>
FBD<12>
FBD<15>
FBD<14>
FBD<13>
FBD<10>
FBD<24>
FBD<26>
FBD<25>
FBD<27>
FBD<29>
FBD<31>
FBD<30>
FBD<28>
FBD<17>
FBD<16>
FBD<20>
FBD<18>
FBD<19>
FBD<21>
FBD<22>
FBD<23>

VDDRH0

53

1.8UH

MEMORY INTERFACE B

=PP1V8_GPU

D8
E27
G10
G13
G15
G19
G22
G27
G7
H10
H13
H15
H19
H22
J1
J23
J24
J4
J7
J8
L27
L8
N4
N7
N8
R1
R4
T4
T7

58 52 51 50

53 55
53 55
53 55
53 55
53 55
53 55
53 55
53 55
53 55
53 55
53 55
53 55
53 55
53 55

53 55
53 55
53 55
53 55
53 55
53 55
53 55

53 55

53
53
53
53
53
53
53
53

RASB* R2
CASB* T5

FBBRAS_L

55

FBBCAS_L

55

WEB* T6
CSB0* R5

FBBWE_L

55

FBBCS0_L

55

CSB1* R6
CKEB R3

TP_FBBCS1_L

FBBCKE

55

CLKB0 N1
CLKB0* N2
CLKB1 T2
CLKB1* T3
ROMCS* AF5

R5201

FBBCLK0
FBBCLK0_L
FBBCLK1
FBBCLK1_L

10K

53 55

5%
1/16W
MF-LF

53 55

2 402

53 55
53 55

TP_GPU_ROMCS_L
58 52 51 50

MEMVMODE
1.8V
2.5V
2.8V

01
10
11

MEMVMODE0 C6

NOSTUFF
1

R5224

GPU_MEMVMODE0

R5226

4.7K

MEMVMODE1 C7
MEMTEST C8

4.7K

5%
1/16W
MF-LF
402 2

GPU_MEMVMODE1

=PP1V8_GPU

01

5%
1/16W
MF-LF

2 402

GPU_MEMTEST
NOSTUFF

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

DIMB_0 E3
DIMB_1 AA3

R5228 R52251
47

TP_GPU_DIMB_0
TP_GPU_DIMB_1

R5227

4.7K

1%
1/16W
MF-LF
2 402

4.7K

5%
1/16W
MF-LF
402 2

5%
1/16W
MF-LF

2 402

7 50 52 54 55

R5222
47

1%
1/16W
MF-LF
2 402

C5223
0.1UF

GPU FRAME BUFFER

1
1

20%
10V
CERM 2
402

R5223
51.1

NOTICE OF PROPRIETARY PROPERTY

1%
1/16W
MF-LF
2 402

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

D
SCALE

DRAWING NUMBER

REV.

051-6772 04
52 102
SHT

OF

NONE

53 52
53 52
53 52
53 52
53 52

53 52
53 52
53 52
53 52
53 52
53 52
53 52
53 52
53 52
53 52
53 52
53 52
53 52
53 52
53 52
53 52
53 52
53 52
53 52
53 52
53 52
53 52
53 52
53 52
53 52
53 52

PLACE CLOCK TERMINATION AFTER MEMORY


GPU -> MEMORY -> TERMINATION
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22

FBD<31>
FBD<30>
FBD<29>
FBD<28>
FBD<27>
FBD<26>
FBD<25>
FBD<24>
FBD<0>
FBD<1>
FBD<2>
FBD<3>
FBD<17>
FBD<16>
FBD<18>
FBD<19>
FBD<15>
FBD<14>
FBD<13>
FBD<12>
FBD<10>
FBD<11>
FBD<9>
FBD<8>
FBD<5>
FBD<6>
FBD<4>
FBD<7>
FBD<20>
FBD<21>
FBD<22>
FBD<23>

1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4

8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5

RP5320
RP5320
RP5320
RP5320
RP5321
RP5321
RP5321
RP5321
RP5322
RP5322
RP5322
RP5322
RP5323
RP5323
RP5323
RP5323
RP5324
RP5324
RP5324
RP5324
RP5325
RP5325
RP5325
RP5325
RP5326
RP5326
RP5326
RP5326
RP5327
RP5327
RP5327
RP5327

RFBD<31>
RFBD<30>
RFBD<29>
RFBD<28>
RFBD<27>
RFBD<26>
RFBD<25>
RFBD<24>
RFBD<0>
RFBD<1>
RFBD<2>
RFBD<3>
RFBD<17>
RFBD<16>
RFBD<18>
RFBD<19>
RFBD<15>
RFBD<14>
RFBD<13>
RFBD<12>
RFBD<10>
RFBD<11>
RFBD<9>
RFBD<8>
RFBD<5>
RFBD<6>
RFBD<4>
RFBD<7>
RFBD<20>
RFBD<21>
RFBD<22>
RFBD<23>

53 54

53 52

53 54

53 52

53 54

53 52

53 54

53 52

53 54

53 52

53 54

53 52

53 54

53 52

53 54

53 52

53 54

53 52

53 54

53 52

53 54

53 52

53 54

53 52

53 54

53 52

53 54

53 52

53 54

53 52

53 54

53 52

53 54

53 52

53 54

53 52

53 54

53 52

53 54

53 52

53 54

53 52

53 54

53 52

53 54

53 52

53 54

53 52

53 54

53 52

53 54

53 52

53 54

53 52

53 54

53 52

53 54

53 52

53 54

53 52

53 54

53 52

53 54

53 52

22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22

FBD<32>
FBD<33>
FBD<34>
FBD<35>
FBD<36>
FBD<37>
FBD<38>
FBD<39>
FBD<40>
FBD<41>
FBD<42>
FBD<43>
FBD<44>
FBD<45>
FBD<46>
FBD<47>
FBD<48>
FBD<49>
FBD<50>
FBD<51>
FBD<52>
FBD<53>
FBD<54>
FBD<55>
FBD<56>
FBD<57>
FBD<58>
FBD<59>
FBD<60>
FBD<61>
FBD<62>
FBD<63>

3
4
1
2
4
3
2
1
2
1
3
4
1
2
4
3
4
3
1
2
4
3
2
1
1
2
4
3
1
3
2
4

6
5
8
7
5
6
7
8
7
8
6
5
8
7
5
6
5
6
8
7
5
6
7
8
8
7
5
6
8
6
7
5

RP5328
RP5328
RP5328
RP5328
RP5316
RP5316
RP5316
RP5316
RP5329
RP5329
RP5329
RP5329
RP5330
RP5330
RP5330
RP5330
RP5331
RP5331
RP5331
RP5331
RP5300
RP5300
RP5300
RP5300
RP5301
RP5301
RP5301
RP5301
RP5302
RP5302
RP5302
RP5302

RFBD<32>
RFBD<33>
RFBD<34>
RFBD<35>
RFBD<36>
RFBD<37>
RFBD<38>
RFBD<39>
RFBD<40>
RFBD<41>
RFBD<42>
RFBD<43>
RFBD<44>
RFBD<45>
RFBD<46>
RFBD<47>
RFBD<48>
RFBD<49>
RFBD<50>
RFBD<51>
RFBD<52>
RFBD<53>
RFBD<54>
RFBD<55>
RFBD<56>
RFBD<57>
RFBD<58>
RFBD<59>
RFBD<60>
RFBD<61>
RFBD<62>
RFBD<63>

53 54
53 54
53 54
54 53 52
53 54

53 52
53 52
53 52
53 52
53 52
53 52
53 52
53 52
53 52
53 52
53 52
53 52
53 52
53 52
53 52
53 52

53 52
53 52
53 52
53 52
53 52
53 52
53 52
53 52
53 52
53 52
53 52
53 52
53 52
53 52

FBD<64>
FBD<65>
FBD<66>
FBD<67>
FBD<84>
FBD<85>
FBD<86>
FBD<87>
FBD<72>
FBD<73>
FBD<75>
FBD<74>
FBD<68>
FBD<70>
FBD<69>
FBD<71>
FBD<80>
FBD<81>
FBD<82>
FBD<83>
FBD<76>
FBD<77>
FBD<78>
FBD<79>
FBD<91>
FBD<90>
FBD<89>
FBD<88>
FBD<95>
FBD<94>
FBD<93>
FBD<92>

GPU128BIT

GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT

ELECTRICAL_CONSTRAINT_SET
53 52
55 54 53

54 52
55 52
55 54 52
53 52

54 53 52
54 53 52
54 53 52
54 53 52
55 53 52
55 53 52
55 53 52
55 53 52

22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22

GPU128BIT

1
2
3
4
1
2
3
4
4
3
2
1
1
2
3
4
1
2
3
4
4
3
2
1
1
2
3
4
1
2
3
4

8
7
6
5
8
7
6
5
5
6
7
8
8
7
6
5
8
7
6
5
5
6
7
8
8
7
6
5
8
7
6
5

RP5310
RP5310
RP5310
RP5310
RP5309
RP5309
RP5309
RP5309
RP5319
RP5319
RP5319
RP5319
RP5308
RP5308
RP5308
RP5308
RP5307
RP5307
RP5307
RP5307
RP5317
RP5317
RP5317
RP5317
RP5318
RP5318
RP5318
RP5318
RP5303
RP5303
RP5303
RP5303

NET_PHYSICAL_TYPE

FBD<127..0>
RFBD<127..0>
FBA<13..0>
FBBA<13..0>
FBDQM<15..0>
FBDQS<15..0>

GPU_FB
GPU_FB
GPU_FB
GPU_FB
GPU_FB
GPU_FB

FBACLK0
FBACLK0_L
FBACLK1
FBACLK1_L
FBBCLK0
FBBCLK0_L
FBBCLK1
FBBCLK1_L

GPU_FBCLK
GPU_FBCLK
GPU_FBCLK
GPU_FBCLK
GPU_FBCLK
GPU_FBCLK
GPU_FBCLK
GPU_FBCLK

RFBD<64>
RFBD<65>
RFBD<66>
RFBD<67>
RFBD<84>
RFBD<85>
RFBD<86>
RFBD<87>
RFBD<72>
RFBD<73>
RFBD<75>
RFBD<74>
RFBD<68>
RFBD<70>
RFBD<69>
RFBD<71>
RFBD<80>
RFBD<81>
RFBD<82>
RFBD<83>
RFBD<76>
RFBD<77>
RFBD<78>
RFBD<79>
RFBD<91>
RFBD<90>
RFBD<89>
RFBD<88>
RFBD<95>
RFBD<94>
RFBD<93>
RFBD<92>

53 55

53 52

53 55

53 52

53 55

53 52

53 55

53 52

53 55

53 52

53 55

53 52

53 55

53 52

53 55

53 52

53 55

53 52

53 55

53 52

53 55

53 52

53 55

53 52

53 55

53 52

53 54

53 52

53 55

53 52
53 52

53 55

53 52

53 55
53 55

53 52

53 55

53 52

53 55

53 52

53 55

53 52

53 55

53 52

53 55

53 52
53 52

53 55
53 55

53 52

53 55

53 52

P
NET_SPACING_TYPE

53 55
53 55
53 55

53 55
53 55

GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT

53 52
53 52
53 52
53 52
53 52
53 52

GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT
GPU128BIT

22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22

4
3
2
1
4
3
2
1
1
2
3
4
1
2
3
4
4
3
2
1
4
3
2
1
1
2
4
3
1
3
2
4

5
6
7
8
5
6
7
8
8
7
6
5
8
7
6
5
5
6
7
8
5
6
7
8
8
7
5
6
8
6
7
5

RP5315
RP5315
RP5315
RP5315
RP5314
RP5314
RP5314
RP5314
RP5312
RP5312
RP5312
RP5312
RP5313
RP5313
RP5313
RP5313
RP5311
RP5311
RP5311
RP5311
RP5306
RP5306
RP5306
RP5306
RP5304
RP5304
RP5304
RP5304
RP5305
RP5305
RP5305
RP5305

RFBD<96>
RFBD<97>
RFBD<98>
RFBD<99>
RFBD<100>
RFBD<101>
RFBD<102>
RFBD<103>
RFBD<104>
RFBD<105>
RFBD<106>
RFBD<107>
RFBD<108>
RFBD<109>
RFBD<110>
RFBD<111>
RFBD<112>
RFBD<113>
RFBD<114>
RFBD<115>
RFBD<116>
RFBD<117>
RFBD<118>
RFBD<119>
RFBD<120>
RFBD<121>
RFBD<122>
RFBD<123>
RFBD<124>
RFBD<125>
RFBD<126>
RFBD<127>

54

53 52

FBDQS<1>
MAKE_BASE=TRUE

RFBDQS<1>

54

53 52

FBDQS<2>
MAKE_BASE=TRUE

RFBDQS<2>

53 52

FBDQS<3>
MAKE_BASE=TRUE

RFBDQS<3>

54

53 52

FBDQS<4>
MAKE_BASE=TRUE

RFBDQS<4>

54

FBDQS<5>
MAKE_BASE=TRUE

RFBDQS<5>

FBACLK0

R53201

y
r

53 54
53 54
53 54
53 54
53 54
53 54
53 54
53 54
53 54
53 54

53 52

53 54

a
n
i

53 54
53 54
53 54
53 54
53 54
53 54
53 54
53 54
53 54
53 54
53 54
53 54
53 54

53 55
53 55
53 55
53 55
53 55
53 55
53 55
53 55
53 55
53 55

1%
1/16W
MF-LF
402 2

FBACLK0_TERM

54

R53211

FBDQS<6>
MAKE_BASE=TRUE

RFBDQS<6>

54

53 52

FBDQS<7>
MAKE_BASE=TRUE

RFBDQS<7>

54

C5321 1

56.2

0.01UF

1%
1/16W
MF-LF
402 2

54 53 52

FBACLK0_L

54 53 52

FBACLK1

54 53 52

55 53 52

20%
16V
CERM 2
402

R53221
56.2

1%
1/16W
MF-LF
402 2

FBACLK1_TERM

R53231

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

C5323 1

56.2
1%
1/16W
MF-LF
402 2

0.01UF

20%
16V
CERM 2
402

FBACLK1_L

FBBCLK0

R53241
56.2

53 52

FBDQS<8>
MAKE_BASE=TRUE

RFBDQS<8>

55

53 52

FBDQS<9>
MAKE_BASE=TRUE

RFBDQS<9>

55

1%
1/16W
MF-LF
402 2

FBBCLK0_TERM
1

R5325

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

C5325 1

56.2

53 52

FBDQS<10>
MAKE_BASE=TRUE

RFBDQS<10>

55

53 52

FBDQS<11>
MAKE_BASE=TRUE

RFBDQS<11>

55

53 52

FBDQS<12>
MAKE_BASE=TRUE

RFBDQS<12>

55

53 52

FBDQS<13>
MAKE_BASE=TRUE

RFBDQS<13>

55

53 52

FBDQS<14>
MAKE_BASE=TRUE

RFBDQS<14>

55

53 52

FBDQS<15>
MAKE_BASE=TRUE

RFBDQS<15>

55

1%
1/16W
MF-LF
402 2

53 55

53 55

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

54

53 52

53 55

56.2

55 53 52

FBBCLK0_L

55 53 52

FBBCLK1

0.01UF

20%
16V
CERM 2
402

53 55
53 55
53 55
53 55
53 55

56.2

1%
1/16W
MF-LF
402 2

53 55
53 55
53 55

FBBCLK1_TERM

53 55
53 55

R53261

53 55

R53271

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

C5327 1

56.2

53 55

1%
1/16W
MF-LF
402 2

53 55
53 55

0.01UF

20%
16V
CERM 2
402

53 55
55 53 52

53 55

FBBCLK1_L

53 55
53 55
53 55

DIFFERENTIAL_PAIR

GPU_FB
GPU_FB
GPU_FB
GPU_FB
GPU_FB
GPU_FB

GPU_FBCLK
GPU_FBCLK
GPU_FBCLK
GPU_FBCLK
GPU_FBCLK
GPU_FBCLK
GPU_FBCLK
GPU_FBCLK

GPU128BIT

RFBDQS<0>

53 54

m
il

GPU128BIT

e
r

53 55

53 55

FBD<96>
FBD<97>
FBD<98>
FBD<99>
FBD<100>
FBD<101>
FBD<102>
FBD<103>
FBD<104>
FBD<105>
FBD<106>
FBD<107>
FBD<108>
FBD<109>
FBD<110>
FBD<111>
FBD<112>
FBD<113>
FBD<114>
FBD<115>
FBD<116>
FBD<117>
FBD<118>
FBD<119>
FBD<120>
FBD<121>
FBD<122>
FBD<123>
FBD<124>
FBD<125>
FBD<126>
FBD<127>

FBDQS<0>
MAKE_BASE=TRUE

53 54

FRAME BUFFER B TERMINATION


53 52

53 52
53 54

53 52

PLACE RS CLOSE TO MEMORY

FRAME BUFFER A TERMINATION


53 52

FBACLK0
FBACLK0
FBACLK1
FBACLK1
FBBCLK0
FBBCLK0
FBBCLK1
FBBCLK1

I421

FB TERMINATION

I425
I426

NOTICE OF PROPRIETARY PROPERTY

I428
I429

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I423

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

I430

II NOT TO REPRODUCE OR COPY IT

I431

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I432
I433

SIZE

I435
I434

APPLE COMPUTER INC.

I436

DRAWING NUMBER

SCALE

REV.

051-6772
SHT
NONE

I427

04

OF

53

102

55 54 52 50 7

PP2V5_GPU

55 54 52 50 7

PP2V5_GPU

PLACE NEAR VDD PINS

55 54 52 50 7

PP2V5_GPU

PLACE NEAR VDD PINS

C5415
1 C5424
0.1UF
2

1 C5425
0.1UF

20%
10V
CERM
402

1 C5426
0.1UF

20%
10V
CERM
402

1 C5422
0.001UF

20%
10V
CERM
402

1 C5427
0.1UF

10%
50V
CERM
402

1 C5428
0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

1 C5429
0.1UF
2

1 C5423
0.001UF

20%
10V
CERM
402

1 10UF
20%
6.3V
2 CERM
805

10%
50V
CERM
402

C5414

C5401

1 10UF
20%
6.3V
2 CERM
805

C5400
1 10UF
20%
6.3V
2 CERM
805

1 10UF
20%
6.3V
2 CERM
805

D
55 54 52 50 7

55 54 52 50 7

PP2V5_GPU

y
r

PP2V5_GPU
OMIT
OMIT

U5401
SDRAM_DDR_4MX32

U5400
SDRAM_DDR_4MX32

BGA

BGA
(2 OF 2)

D7
D8
E4
E11
L4
L7
L8
L11

C
54

SGRAVREF

VDD
VSS

C3
C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11

VDDQ

N13

VREF

E5
E7
E8
E10
K6
K7
K8
K9
L5
L10

U5400
SDRAM_DDR_4MX32
54 53 52
54 53 52
54 53 52
54 53 52
54 53 52
54 53 52
54 53 52

VSS_THERM

1 C5434

0.1UF
2

20%
10V
CERM
402

VSSQ

F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9

54 53 52
54 53 52
54 53 52
54 53 52
54 53 52

53
53
53
53

53 52
53 52
53 52
53 52

54 53 52

B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10

53 52
53 52
54 52
54 52
54 52
54 52
54 52

FBA<0>
FBA<1>
FBA<2>
FBA<3>
FBA<4>
FBA<5>
FBA<6>
FBA<7>
FBA<8>
FBA<9>
FBA<10>
FBA<11>
RFBDQS<0>
RFBDQS<3>
RFBDQS<1>
RFBDQS<2>

10%
50V
CERM
402

1 C5408
0.1UF

1 C5409
0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

10%
50V
CERM
402

1 C5410
0.1UF
2

20%
10V
CERM
402

1 C5411
0.1UF

FBA<12>
FBA<13>

N4
M5

BA0
BA1

FBACLK0
FBACLK0_L
FBACKE
FBACS0_L
FBARAS_L
FBACAS_L
FBAWE_L

QTY

M11
M12
N12
N2
M2
L2
L3

1 C5420
0.001UF
2

10%
50V
CERM
402

DESCRIPTION

BGA
(1 OF 2)

DQS0
DQS1
DQS2
DQS3
DM0
DM1
DM2
DM3

CK
CK
CKE
CS
RAS
CAS
WE

NC

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

B7
C6
B6
B5
C2
D3
D2
E2
K13
K12
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8

MCL

M13

RFU1
RFU2

L9
M10

RFBD<7>
RFBD<5>
RFBD<6>
RFBD<4>
RFBD<2>
RFBD<3>
RFBD<1>
RFBD<0>
RFBD<31>
RFBD<30>
RFBD<29>
RFBD<28>
RFBD<27>
RFBD<26>
RFBD<25>
RFBD<24>
RFBD<15>
RFBD<14>
RFBD<13>
RFBD<12>
RFBD<10>
RFBD<11>
RFBD<8>
RFBD<9>
RFBD<23>
RFBD<22>
RFBD<21>
RFBD<20>
RFBD<19>
RFBD<16>
RFBD<18>
RFBD<17>

e
r
1 C5412
0.1UF

1 C5413
0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

REFERENCE DES

CRITICAL

333S0251

SDRAM,4MX32,DDR,300MHZ

U5400,U5401

CRITICAL

SAMSUNG64

333S0252

SDRAM,4MX32,DDR,300MHZ

U5400,U5401

CRITICAL

HYNIX64

333S0299

SDRAM,8MX32,DDR,300MHZ

U5400,U5401

CRITICAL

HYNIX128

1 C5421
0.001UF
2

10%
50V
CERM
402

ALTERNATE FOR
PART NUMBER

BOM OPTION

REF DES

53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53

53

SGRAVREF

54

SAMSUNG64

U5400,U5401,U5500,U5501

HYN4M G-DIE

333S0292

333S0252

HYNIX64

U5400,U5401,U5500,U5501

SAM4M B-DIE

E5
E7
E8
E10
K6
K7
K8
K9
L5
L10

OMIT

U5401
SDRAM_DDR_4MX32

FBA<0>
FBA<1>
FBA<2>
FBA<3>
FBA<4>
FBA<5>
FBA<6>
FBA<7>
FBA<8>
FBA<9>
FBA<10>
FBA<11>

N5
N6
M6
N7
N8
M9
N9
N10
N11
M8
L6
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11

RFBDQS<6>
RFBDQS<4>
RFBDQS<7>
RFBDQS<5>

B2
H13
H2
B13

DQS0
DQS1
DQS2
DQS3

FBDQM<6>
FBDQM<4>
FBDQM<7>
FBDQM<5>

B3
H12
H3
B12

DM0
DM1
DM2
DM3

FBA<12>
FBA<13>

N4
M5

BA0
BA1

FBACLK1
FBACLK1_L
FBACKE
FBACS0_L
FBARAS_L
FBACAS_L
FBAWE_L

M11
M12
N12
N2
M2
L2
L3

CK
CK
CKE
CS
RAS
CAS
WE

54 53 52
54 53 52
54 53 52

a
n
i

VDDQ

N13

VREF

54 53 52
54 53 52
54 53 52

VSS_THERM

53

F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9

54 53 52
54 53 52

54 53 52
54 53 52
54 53 52
54 53 52

53
53
53
53

53 52
53 52
53 52
53 52

54 53 52

53

1 C5435

53

0.1UF

53

53

20%
10V
CERM
402

53

53

53
53
53

53

VSSQ

NO_TEST
NO_TEST

B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10

54 53 52

53 52
53 52

54 52
54 52
54 52
54 52
54 52

C4
C11
H4
H11
L12
L13
M3
M4
N3

BGA

(1 OF 2)

NC

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

B7
C6
B6
B5
C2
D3
D2
E2
K13
K12
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8

MCL

M13

RFU1
RFU2

L9
M10

RFBD<48>
RFBD<49>
RFBD<50>
RFBD<51>
RFBD<53>
RFBD<52>
RFBD<54>
RFBD<55>
RFBD<32>
RFBD<33>
RFBD<35>
RFBD<34>
RFBD<37>
RFBD<36>
RFBD<38>
RFBD<39>
RFBD<57>
RFBD<56>
RFBD<58>
RFBD<59>
RFBD<62>
RFBD<60>
RFBD<61>
RFBD<63>
RFBD<41>
RFBD<40>
RFBD<42>
RFBD<43>
RFBD<44>
RFBD<47>
RFBD<45>
RFBD<46>

53
53
53
53
53
53
53
53
53
53
53
53
53
53
53

53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53

TP_U5401_RFU1
TP_U5401_RFU2

NO_TEST
NO_TEST

PP2V5_GPU

10%
50V
CERM
402

1 C5402
0.1UF

1 C5403
0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

1 C5430
0.001UF
2

10%
50V
CERM
402

1 C5404
0.1UF

1 C5405
0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

1 C5431
0.001UF
2

10%
50V
CERM
402

1 C5406
0.1UF

1 C5407
0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

1 C5432
0.001UF
2

10%
50V
CERM
402

EVENLY PLACE 0.1UF CAP & 0.01UF CAPS

DDR SDRAM A VREF

BOM OPTION

55 54 52 50 7

PP2V5_GPU
1
R5400
1K
2

GPU DDR SDRAM A

1%
1/16W
MF-LF
402

NOTICE OF PROPRIETARY PROPERTY


SGRAVREF

1
R5401
1K

TABLE_ALT_ITEM

333S0251

VSS

C3
C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11

1 C5433
0.001UF

COMMENTS:

333S0290

VDD

53

55 54 52 50 7

TABLE_ALT_HEAD

PART NUMBER

53

(2 OF 2)

m
il

TP_U5400_RFU1
TP_U5400_RFU2

PP2V5_GPU

P
2

20%
10V
CERM
402

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11

B3
H12
H3
B12

SGRAM0 & SGRAM1 MEMORY SUPPORT

PART NUMBER

B2
H13
H2
B13

C4
C11
H4
H11
L12
L13
M3
M4
N3

1 C5419
0.001UF
2

N5
N6
M6
N7
N8
M9
N9
N10
N11
M8
L6
M7

FBDQM<0>
FBDQM<3>
FBDQM<1>
FBDQM<2>

55 54 52 50 7

1 C5418
0.001UF

D7
D8
E4
E11
L4
L7
L8
L11

OMIT

54 53 52

1%
1/16W
MF-LF
402

1 C5417
0.1UF
2

54

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

VOLTAGE=1.25V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

20%
10V
CERM
402

II NOT TO REPRODUCE OR COPY IT


III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

TABLE_ALT_ITEM

SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-6772

04

OF

54

102

55 54 52 50 7

55 54 52 50 7

PP2V5_GPU

5
PP2V5_GPU

55 54 52 50 7

PLACE NEAR VDD PINS

PP2V5_GPU

PLACE NEAR VDD PINS


GPU128BIT

GPU128BIT

GPU128BIT

1 C5518
0.1UF
2

55 54 52 50 7

GPU128BIT

1 C5519
0.1UF

20%
10V
CERM
402

GPU128BIT

1 C5520
0.1UF

20%
10V
CERM
402

GPU128BIT

1 C5521
0.001UF

20%
10V
CERM
402

GPU128BIT

1 C5522
0.1UF

10%
50V
CERM
402

1 C5523
0.1UF

20%
10V
CERM
402

GPU128BIT

20%
10V
CERM
402

C5515

GPU128BIT

1 C5524
0.1UF

1 C5525
0.001UF

20%
10V
CERM
402

1 10UF
20%
6.3V
2 CERM
805

10%
50V
CERM
402

D7
D8
E4
E11
L4
L7
L8
L11

U5501
SDRAM_DDR_4MX32
BGA

SGRBVREF

(2 OF 2)

OMIT

VDD
VSS

C3
C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11

VDDQ

N13

VREF

E5
E7
E8
E10
K6
K7
K8
K9
L5
L10

55 53 52
55 53 52
55 53 52
55 53 52
55 53 52
55 53 52

VSS_THERM

GPU128BIT

1 C5534

0.1UF
2

20%
10V
CERM
402

VSSQ

F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9

55 53 52
55 53 52
55 53 52
55 53 52
55 53 52

RFBDQS<8>
RFBDQS<11>
RFBDQS<9>
RFBDQS<10>

53
53
53
53

53 52
53 52
53 52
53 52

DM0
DM1
DM2
DM3

FBBA<12>
FBBA<13>

N4
M5

BA0
BA1

M11
M12
N12
N2
M2
L2
L3

53 52
55 52
55 52
55 52
55 52
55 52

C4
C11
H4
H11
L12
L13
M3
M4
N3

GPU128BIT

GPU128BIT

1 C5508
0.1UF
2

1 C5509
0.1UF

20%
10V
CERM
402

20%
10V
CERM
402

GPU128BIT

1 C5527
0.001UF
2

10%
50V
CERM
402

GPU128BIT

1 C5510
0.1UF
2

20%
10V
CERM
402

GPU128BIT

1 C5511
0.1UF
2

20%
10V
CERM
402

GPU128BIT

10%
50V
CERM
402

1 C5512
0.1UF
2

20%
10V
CERM
402

(1 OF 2)

CK
CK
CKE
CS
RAS
CAS
WE

NC

OMIT

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

B7
C6
B6
B5
C2
D3
D2
E2
K13
K12
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8

MCL

M13

RFU1
RFU2

L9
M10

RFBD<71>
RFBD<69>
RFBD<70>
RFBD<68>
RFBD<65>
RFBD<67>
RFBD<66>
RFBD<64>
RFBD<95>
RFBD<94>
RFBD<93>
RFBD<92>
RFBD<91>
RFBD<90>
RFBD<89>
RFBD<88>
RFBD<79>
RFBD<78>
RFBD<77>
RFBD<76>
RFBD<74>
RFBD<75>
RFBD<72>
RFBD<73>
RFBD<87>
RFBD<86>
RFBD<85>
RFBD<84>
RFBD<83>
RFBD<81>
RFBD<82>
RFBD<80>

PP2V5_GPU

GPU128BIT

1 C5513
0.1UF
2

20%
10V
CERM
402

GPU128BIT

1 C5529
0.001UF
2

QTY

DESCRIPTION

REFERENCE DES

53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53

VDD

VSS

55

53

SGRBVREF

E5
E7
E8
E10
K6
K7
K8
K9
L5
L10

C5500
1 10UF
20%
6.3V
2 CERM
805

U5501

55 53 52
55 53 52
55 53 52

a
n
i

C3
C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11

VDDQ

N13

VREF

55 53 52
55 53 52
55 53 52

VSS_THERM

53

53

F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9

55 53 52
55 53 52
55 53 52
55 53 52
55 53 52
55 53 52

53
53
53
53

53 52
53 52
53 52
53 52

55 53 52

GPU128BIT

53

1 C5535

53

0.1UF

53

53
53

20%
10V
CERM
402

53
53
53

53

53

VSSQ

NO_TEST
NO_TEST

55 53 52

53 52
53 52
55 52
55 52
55 52
55 52
55 52

N5
N6
M6
N7
N8
M9
N9
N10
N11
M8
L6
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11

RFBDQS<14>
RFBDQS<12>
RFBDQS<15>
RFBDQS<13>

B2
H13
H2
B13

DQS0
DQS1
DQS2
DQS3

FBDQM<14>
FBDQM<12>
FBDQM<15>
FBDQM<13>

B3
H12
H3
B12

DM0
DM1
DM2
DM3

FBBA<12>
FBBA<13>

N4
M5

BA0
BA1

FBBCLK1
FBBCLK1_L
FBBCKE
FBBCS0_L
FBBRAS_L
FBBCAS_L
FBBWE_L

M11
M12
N12
N2
M2
L2
L3

CK
CK
CKE
CS
RAS
CAS
WE

C4
C11
H4
H11
L12
L13
M3
M4
N3

(1 OF 2)

OMIT

NC

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

B7
C6
B6
B5
C2
D3
D2
E2
K13
K12
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8

MCL

M13

RFU1
RFU2

L9
M10

RFBD<113>
RFBD<114>
RFBD<112>
RFBD<115>
RFBD<117>
RFBD<116>
RFBD<118>
RFBD<119>
RFBD<97>
RFBD<96>
RFBD<99>
RFBD<98>
RFBD<100>
RFBD<101>
RFBD<102>
RFBD<103>
RFBD<121>
RFBD<120>
RFBD<122>
RFBD<123>
RFBD<126>
RFBD<124>
RFBD<125>
RFBD<127>
RFBD<104>
RFBD<105>
RFBD<106>
RFBD<107>
RFBD<108>
RFBD<110>
RFBD<109>
RFBD<111>

53
53
53
53
53
53
53
53
53
53
53
53
53
53
53

53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53
53

TP_U5501_RFU1
TP_U5501_RFU2

NO_TEST
NO_TEST

GPU128BIT

1 C5530
0.001UF
2

DDR SDRAM B VREF

55 54 52 50 7

B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10

SDRAM_DDR_4MX32
BGA

FBBA<0>
FBBA<1>
FBBA<2>
FBBA<3>
FBBA<4>
FBBA<5>
FBBA<6>
FBBA<7>
FBBA<8>
FBBA<9>
FBBA<10>
FBBA<11>

PP2V5_GPU

10%
50V
CERM
402

10%
50V
CERM
402

GPU128BIT

1 C5502
0.1UF
2

20%
10V
CERM
402

GPU128BIT

1 C5503
0.1UF
2

20%
10V
CERM
402

GPU128BIT

1 C5531
0.001UF
2

10%
50V
CERM
402

GPU128BIT

1 C5504
0.1UF
2

20%
10V
CERM
402

GPU128BIT

1 C5505
0.1UF
2

20%
10V
CERM
402

GPU128BIT

1 C5532
0.001UF
2

10%
50V
CERM
402

GPU128BIT

1 C5506
0.1UF
2

20%
10V
CERM
402

GPU128BIT

GPU128BIT

1 C5507
0.1UF
2

1 C5533
0.001UF

20%
10V
CERM
402

10%
50V
CERM
402

EVENLY PLACE 0.1UF CAP & 0.01 UF CAPS

PP2V5_GPU
1GPU128BIT
R5500
1K
1%
1/16W
MF-LF

GPU DDR SDRAM B

2 402
SGRBVREF
GPU128BIT

1
R5501
1K
1%
1/16W
MF-LF

2 402

CRITICAL

OMIT

55 54 52 50 7

SGRAM0 & SGRAM1 MEMORY SUPPORT

PART NUMBER

53

(2 OF 2)

m
il

TP_U5500_RFU1
TP_U5500_RFU2

e
r

GPU128BIT

P
1 C5528
0.001UF

SDRAM_DDR_4MX32
BGA

DQS0
DQS1
DQS2
DQS3

B3
H12
H3
B12

FBBCLK0
FBBCLK0_L
FBBCKE
FBBCS0_L
FBBRAS_L
FBBCAS_L
FBBWE_L

53 52

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11

FBDQM<8>
FBDQM<11>
FBDQM<9>
FBDQM<10>

55 53 52

B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10

B2
H13
H2
B13

55 54 52 50 7

GPU128BIT

D7
D8
E4
E11
L4
L7
L8
L11

U5500
N5
N6
M6
N7
N8
M9
N9
N10
N11
M8
L6
M7

FBBA<0>
FBBA<1>
FBBA<2>
FBBA<3>
FBBA<4>
FBBA<5>
FBBA<6>
FBBA<7>
FBBA<8>
FBBA<9>
FBBA<10>
FBBA<11>

55 53 52

55 53 52

10%
50V
CERM
402

GPU128BIT

C5501
1 10UF
20%
6.3V
2 CERM
805

y
r

PP2V5_GPU

SDRAM_DDR_4MX32
BGA

GPU128BIT

C5514

D
55 54 52 50 7

1 C5526
0.001UF

GPU128BIT

1 10UF
20%
6.3V
2 CERM
805

PP2V5_GPU

U5500

55

GPU128BIT

1 C5517
0.1UF
2

55

VOLTAGE=1.25V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

20%
10V
CERM
402

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT

BOM OPTION

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

333S0251

SDRAM,4MX32,DDR,300MHZ

U5500,U5501

CRITICAL

SAMSUNG64

333S0252

SDRAM,4MX32,DDR,300MHZ

U5500,U5501

CRITICAL

HYNIX64

333S0299

SDRAM,8MX32,DDR,300MHZ

U5500,U5501

CRITICAL

HYNIX128

SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-6772

04

OF

55

102

7
=PP3V3_AGP

APPLE GPIO

R5600 1R5602
10K

10K

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

58
58
58

GPU_GPIO<0>
GPU_GPIO<1>

58

58

NOSTUFF

GPU_GPIO<9>
GPU_GPIO<13>
GPU_GPIO<12>
GPU_GPIO<11>

ATI STRAP
AGPFBSKEW(1:0)

58

PIN

DESCRIPTION

DEFAULT

GPIO(1:0)

AGP 1X CLOCK FEEDBACK PHASE ADJUSTMENT WRT REFCLK (CPUCLK)


00 - REFCLK SLIGHTLY EARLIER THEN FEEDBACK
01 - REFCLK 1 TAP EARLIER THEN FEEDBACK
10 - REFCLK 1 TAP LATER THEN FEEDBACK
11 - REFCLK 2 TAPS EARLIER THEN FEEDBACK CLOCK (ATI RECOMMENDED)

00

CLOCK PHASE ADJUSTMENT BETWEEN X1 CLK AND X2CLK


00 - 0 TAP DELAY

00

GPU_GPIO<8>

NOSTUFF

NOSTUFF

R5601 1R5603

R5604 1R5605 1R5606 1R5607

R56231

10K

10K

10K

10K

10K

10K

10K

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

1%
1/16W
MF-LF
402 2

=PP3V3_AGP

59 58 56 50 49 48 7

NOSTUFF
1

59 56

=PP3V3_AGP
FPD_PWR_ON

GPIO(3:2)

y
r

ROMIDCFG(3:0)

GPIO(9,13:11)

IF NO ROM ATTACHED, CONTROLS CHIP IDS.


0X0X - NO ROM, CHG_ID=0

ID_DISABLE

GPIO(8)

STRAP

R56251

0.1UF

20%
10V
2 CERM
402

NOSTUFF

58

PCI_RESET_L

ATI_PWM

5%
1/16W
MF-LF
402 2

R5626
0

LCD_PWM_U5600

NOSTUFF

R5610

MC74VHC1G08
3 SOT23-5

47

BUSCFG(2:0)
LCD_PWM

59

5%
1/16W
MF-LF
402

NOSTUFF

R5624

a
n
i

5%
1/16W
MF-LF
2 402

R5611

U5600 4

10K

MULTIFUNC(1:0)

1%
1/16W
MF-LF
402 2

10K
1%
1/16W
MF-LF
2 402

NOSTUFF

R5609
1

5%
1/16W
MF-LF
402

MEMSTRAP(1:0)

NOSTUFF

R5629
PCI_SLOTF_GNT_L

25

5%
1/16W
MF-LF
402

=PP3V3_AGP
NOSTUFF

INV_CUR_HI

=PP3V3_AGP

7 48 49 50 56 58 59

NOSTUFF

R5612 1R5614

58
58

10K

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

GPU_GPIO<15>
GPU_GPIO<10>

e
r
SAMSUNG64

R5613 1R5615
10K

10K

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

GPU_GPIO<7>

INV_CUR_HI

5%
1/16W
MF-LF
402

59 58 56 50 49 48 7

=PP3V3_AGP
NOSTUFF
1

C5601
0.1UF

20%
2 10V
CERM
402

NOSTUFF
74 56 8 6

58

PCI_RESET_L

GPU_GPIO<16>

U5601 4

R5621
1

10K

5%
1/16W
MF-LF
2 402

FPD_PWR_ON

3 MC74VHC1G08
SOT23-5

R5617

10K

59

58

56 59

SAMSUNG64&HYNIX64

R5619

R5620
58

R5616

10K

58

47

R5618

10K

58

HYNIX128

10K

GPU_LCDDATA<16>
GPU_LCDDATA<17>

m
il

7 48 49 50 56 58 59

HYNIX128&HYNIX64

PULL-DOWN

INTERNAL
PULL-DOWN

IF ROM- IDENTIFIES TYPE

0 - NORMAL OPERATION
1 - SHUTS THE CHIP DOWN BY NOT RESPONDING TO ANY CONFIG CYCLES

NOSTUFF

C5600

INTERNAL

D
X1CLK_SKWE(1:0)

TO TEST THE RV351LEP PWM, NOSTUFF R5625 & STUFF R5609


59 58 56 50 49 48 7

74 56 8 6

7 48 49 50 56 58 59

58

5%
1/16W
MF-LF
2 402

=PP3V3_AGP

GPIO(6:4)

AGP8X_DETB
0

LCDDATA(17:16)

GPU_GPIO<15,10>

GPIO<7>

BUSCFG[2:0]
000

AGPMODE
AGP8X

SIGNALING
0.8V

INTERNAL PULL-DOWN

000

IDSEL
AD16

INTERNAL
PULL-DOWN

00

MULTI-FUNCTION DEVICE SELECT


00 - SINGLE FUNCTION DEVICE.
01 - TWO FUNCTION DEVICE. NO AGP IN EITHER FUNCTION
10 - TWO FUNCTION DEVICE. AGP ONLY IN FUNCTION 0
11 - TWO FUNCTION DEVICE. AGP IN BOTH FUNCTIONS
IF BUSCFG PIN BASED STRAPS ARE SET TO PCI, THEN AGP WILL NOT BE
ENABLED IN ANY FUNCTION.
00
01
10
11

SAMSUNG 4MX32
UNDEFINED
HYNIX 4MX32
HYNIX 8MX32

OUTPUT: GPU READS PANEL ID AND SETS THIS BIT ACCORDINGLY


FOR REFERENCE ONLY, ACTIONS COME FROM BOOTROM

SYSTEM

PANEL ID

INV_CUR_HI

Q45 A

0X9C27

0X9C38

0X9C3A

0X9C39

TBD

TBD

0X9C3A

Q45 B

Q45 C

Q45 D

Q45 A/B SUPPORT IS FOR DEVELOPMENT

FPD_PWR_ON

GPIO<16>

OUTPUT: PANEL POWER SEQUENCING

TMDS_EN

GPIO<14>

INPUT: PANEL POWER SEQUENCING

7 48 49 50 56 58 59

NOSTUFF

R5627
10K

5%
1/16W
MF-LF
2 402

GPU_GPIO<14>

R5622
1

NOSTUFF
1

R5628
10K

47

TMDS_EN

59

5%
1/16W
MF-LF
402

GPU STRAPS

5%
1/16W
MF-LF
2 402

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

5%
1/16W
MF-LF
402

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-6772

04

OF

56

102

59 58
59 58
59 58
59 58
59 58
59 58

59 58 6
59 58 6
59 58 6

GPU_TMDS
GPU_TMDS
GPU_TMDS
GPU_TMDS
GPU_TMDS
GPU_TMDS
GPU_TMDS
GPU_TMDS
GPU_VGA_37P5
GPU_VGA_37P5
GPU_VGA_37P5

TMDS
TMDS
TMDS
TMDS

GPU_TMDS
GPU_TMDS
GPU_TMDS
GPU_TMDS
GPU_TMDS
GPU_TMDS
GPU_TMDS
GPU_TMDS
GPU_VGA_37P5
GPU_VGA_37P5
GPU_VGA_37P5

I573
I575
56

I574
56

I576
I577
I578
I579

I590
56

I591
56
56
56
56
56
56
56
56
56

R5814

GPU_GPIO<0>
GPU_GPIO<1>
TP_GPU_GPIO<2>
TP_GPU_GPIO<3>
TP_GPU_GPIO<4>
TP_GPU_GPIO<5>
TP_GPU_GPIO<6>
GPU_GPIO<7>
GPU_GPIO<8>
GPU_GPIO<9>
GPU_GPIO<10>
GPU_GPIO<11>
GPU_GPIO<12>
GPU_GPIO<13>
GPU_GPIO<14>
GPU_GPIO<15>
GPU_GPIO<16>

VDDR3

AJ5
AH5

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

AJ4
AK4
AH4
AF4
AJ3
AK3
AH3
AJ2
AH2
AH1
AG3
AG1
AG2
AF3
AF2

22PF

27.000M

5%
50V
CERM 2
603

C5815
22PF

5%
50V
2 CERM
603

AH28

GPU_CLK27M_XIN
GPU_CLK27M_XOUT

AJ29

E8

NC AE25
AH27

=PP3V3_AGP

R58161

GPU_DIODE_PLUS
GPU_DIODE_MINUS

58

1K

58

1%
1/16W
MF-LF
402 2

PP1V8_GPU_TXVDDR

FERR-220-OHM
1

C5835
10UF

GND_GPU_TXVSSR

20%
6.3V
2 CERM
805

L5830

PP1V8_GPU_TPVDD

1.8UH

10%
6.3V
2 CERM
402

C5837
0.1UF

10UF

GND_GPU_TPVSS
VOLTAGE=0V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

L5840

FERR-220-OHM
1

PP1V8_GPU_VDDDI
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

0805

C5840

20%
2 6.3V
CERM
805

VOLTAGE=0V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

L5845

FERR-220-OHM
2

PP1V8_GPU_AVDD

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

0805

GND_GPU_AVSSN

C5845

20%
6.3V
2 CERM
805

VOLTAGE=0V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

PP2V5_GPU_A2VDD

1UF

0.1UF

1UF

10%
2 6.3V
CERM
402

58

C5846
1UF

10%
6.3V
2 CERM
402

C5855
10UF

XW5855
SM

VOLTAGE=0V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

20%
6.3V
2 CERM
805

C5856

NC

HPD1

AF12

NO CONNECTS

NC

AH17
AH19

AK16
AK19

AH20

AF16

GND_GPU_AVSSQ

AE22

AE23
AE21

TXVDDR
TXVSSR

TMDS

TPVDD 75MA

MAX

TPVSS

VDD1DI
VDD2DI
VSS1DI
VSS2DI

DAC1

TXCP
TXCM*
TX0P
TX0M*
TX1P
TX1M*
TX2P
TX2M*

AH24

AVDD

AD24

AVSSQ

AH23

AVSSN

AF23

1UF

A2VSSQ

10%
6.3V
2 CERM
402

AJ14
AK15
AJ15

AE13

1UF

=PP3V3_AGP

56

y
r

7 48 49 50 56 58 59

56

1
RP5810 RP5810 RP5810 RP5810 R5818
10K

4.7K

4.7K

4.7K

5%
1/16W
SM-LF

5%
1/16W
SM-LF

5%
1/16W
SM-LF

4.7K
5%
1/16W
SM-LF

5%
1/16W
MF-LF
2 402

MON_DETECT 6

27 18 11 6

PP3V3_PWRON
DEVELOPMENT
1

R
G
B
HSYNC
VSYNC

AK27

AE14

AJ27
AJ26
AG25

NC
NC
NC
NC

58 59

10UF

DEVELOPMENT

58 59

C5892

AF26

NC

Y_G
C_R
COMP_B
H2SYNC
V2SYNC

AJ22

R2SET

AK21

DDC3CLK
DDC3DATA

AG23
AG24

LM63CIMA
SOI

2200PF

58 59

5%
50V
CERM 2
603

58 59
58 59

XW5865
SM
1

GND_GPU_A2VSSQ

20%
2 6.3V
CERM
805

PWM 4

SMBCLK 8
SMBDA 7

U5890_PWM
I2C_GPU_DIODE_SCL
I2C_GPU_DIODE_SDA

18
18

GPU_DIODE_MINUS

58

59

GPU_DAC1_VSYNC

NO_TEST=TRUE

DEVELOPMENT

R58261

GPU_RSET
GPU_STEREOSYNC

75

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

R58251

1%
1/16W
MF-LF
402 2

R5820

10K

499

5%
1/16W
MF-LF
402 2

XW5847
SM
1

1%
1/16W
MF-LF
2 402

GND_GPU_AVSSQ

58

AG26

ANALOG_GRN
ANALOG_RED
ANALOG_BLU
ANALOG_HSYNC
ANALOG_VSYNC

AJ23
AK22
AJ24
AK24

6 58 59
ROUTE SIGNALS AT 37.5 OHMS
6 58 59
6 58 59
59
59

R5821 1R5822 1R5823


75

I2C_GPU_MON_SCL
I2C_GPU_MON_SDA

59
59

1%
1/16W
MF-LF
2 402

75
1%
1/16W
MF-LF
2 402

75
1%
1/16W
MF-LF
2 402

GPU DVI & DACS


PLACE R5821-3 & FL5900-2 NEAR MINI-VGA CONNECTOR
ROUTE GND IN BETWEEN RGB SIGNALS WITH A VIA EVERY INCH

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

1%
1/16W
MF-LF
2 402

C5866
1UF

10%
2 6.3V
CERM
402

II NOT TO REPRODUCE OR COPY IT


III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

REV.

051-6772
SHT
NONE

5%
1/16W
MF-LF
2 402

U5890_ALERT_L

SCALE

10K

5%
1/16W
MF-LF
2 402

59

VOLTAGE=0V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

R5892

10K

GND

58 59

AH26

AUXWIN
STEREOSYNC

U5890

2 D+
3 D-

715

R5891

R5824

C5865

DEVELOPMENT

100PF

5%
2 50V
CERM
402

VDD
DEVELOPMENT ALERT*/ 6
TACH

GPU_DIODE_PLUS

58
58 59

AH25

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

NOSTUFF
1

DEVELOPMENT

C5891

GPU_R2SET

PP1V8_GPU_A2VDDQ
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

DEVELOPMENT
1

20%
2 10V
CERM
402

1
2
0805

C5890
0.1UF

FERR-220-OHM
1

59

GPU THERMAL SENSOR

58 59

I2C_GPU_TMDS_SCL
I2C_GPU_TMDS_SDA

NC
NC

DAC2

A2VDDQ

AJ13
AH15

DDC1CLK
DDC1DATA

A2VDD
A2VSSN

TMDS_CKP
TMDS_CKM
TMDS_D0P
TMDS_D0M
TMDS_D1P
TMDS_D1M
TMDS_D2P
TMDS_D2M

AH13
AH14

AF24
AF25

AG21

AH22
AJ21

C5803

10%
6.3V
2 CERM
402

5%
1/16W
MF-LF
402

AK13

DDC2CLK
DDC2DATA

RSET

AH21

10%
2 6.3V
CERM
402

THE FREQUENCY OF THE 20" PIXEL CLOCK IS 119 MHZ

AH12

AE24

1UF

MON_DETECT_R

AJ17
AJ18
AJ25

GND_GPU_A2VSSN

L5865

AE10

AH16

AF22
1

DVOMODE

AH30
AJ16

NOSTUFF

AJ11
AH11

AH18

AJ12

C5802

GPU_LCDCNTL<0>
GPU_LCDCNTL<1>
GPU_LCDCNTL<2>
GPU_LCDCNTL<3>

AK10

AG16
AG17

AK12

a
n
i

AJ10

AG12

C5833

20%
10V
2 CERM
402

C5841

0
1
2
3

TP_GPU_LCDDATA<0>
TP_GPU_LCDDATA<1>
TP_GPU_LCDDATA<2>
AH7 TP_GPU_LCDDATA<3>
AK7 TP_GPU_LCDDATA<4>
AJ7 TP_GPU_LCDDATA<5>
AH8 TP_GPU_LCDDATA<6>
AJ8 TP_GPU_LCDDATA<7>
AH9 TP_GPU_LCDDATA<8>
AJ9 TP_GPU_LCDDATA<9>
AK9 TP_GPU_LCDDATA<10>
AH10 TP_GPU_LCDDATA<11>
AE6 TP_GPU_LCDDATA<12>
AG6 TP_GPU_LCDDATA<13>
AF6 TP_GPU_LCDDATA<14>
AE7 TP_GPU_LCDDATA<15>
AF7
GPU_LCDDATA<16>
AE8
GPU_LCDDATA<17>
AG8 TP_GPU_LCDDATA<18>
AF8 TP_GPU_LCDDATA<19>
AE9 TP_GPU_LCDDATA<20>
AF9 TP_GPU_LCDDATA<21>
AG10 TP_GPU_LCDDATA<22>
AF10 TP_GPU_LCDDATA<23>

AE12
AE18

NOSTUFF

10UF

XW5845
SM

C5832

10%
6.3V
2 CERM
402

NOSTUFF
1

P
GND_GPU_VSSDI

1UF

10UF

XW5840
SM

C5831

10%
6.3V
2 CERM
402

10%
2 6.3V
CERM
402

R5819

AF13

e
r

C5830

20%
6.3V
2 CERM
805

1UF

AK6

AF17
AF18

AG13
AG14

C5801

AH6
AJ6

AH29

20%
10V
2 CERM
402

50

XW5830
SM

51 50

1UF

NOSTUFF

0805

C5836

LCDCNTL

VREFG

AF14

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

VOLTAGE=0V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

NOSTUFF

RSTB_MSK

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23

m
il

51

ATI_PWM

56

NOSTUFF

XW5835
SM

20%
10V
2 CERM
402

VOLTAGE=1.8V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

0805

AG29

AG19
AG20

L5835

=PP1V8_GPU

C5817
0.1UF

1%
1/16W
MF-LF
402 2

TEST_MCLK
TEST_YCLK
PLLTEST
TESTEN
DPLUS
DMINUS

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

1K

52 51 50

XTALIN
XTALOUT

AF11
AE11

AG4

GPU_VREFG

R58171

AG7

BGA
(5 OF 5)

5%
1/16W
MF-LF
402

B6

59 58 56 50 49 48 7

AD10
AD9

RV351

CLK

R5815
GPU_CLK27M_XOUT_R

20%
2 6.3V
CERM
805

OMIT

U4900

TEST

C5814

5%
1/16W
MF-LF
2 402

C5800
10UF

VDDR4

1M

NOSTUFF
1

I572

I589

Y5800
SM-3

AC10
AC9

AD22
AD7

AD21

AD19

AC19

TMDS_CK
TMDS_CK
TMDS_D0
TMDS_D0
TMDS_D1
TMDS_D1
TMDS_D2
TMDS_D2

=PP3V3_AGP

DIFFERENTIAL_PAIR

LCDDATA

59 58

TMDS_CKP
TMDS_CKM
TMDS_D0P
TMDS_D0M
TMDS_D1P
TMDS_D1M
TMDS_D2P
TMDS_D2M
ANALOG_GRN
ANALOG_RED
ANALOG_BLU

NET_SPACING_TYPE

EXTERNAL TMDS

59 58

NET_PHYSICAL_TYPE

AC22
AC8

59 58 56 50 49 48 7

ELECTRICAL_CONSTRAINT_SET

5
AC21

7
DIFFERENTIAL IMPEDANCE SHOULD BE 100 OHM

GPIO

04

OF

58

102

PLACE R5901-R5904 AS CLOSE TO GPU AS POSSIBLE

EXTERNAL VGA CONNECTOR

=PP3V3_AGP

R5926

U5970
0.1UF

CRITICAL
14
58

74LCX125

ANALOG_VSYNC

12

20%
2 10V
CERM
402

U5970
3

R5971
10

VGA_VSYNC

VGA_VSYNC_R

PP5V_USB2

10

VGA_HSYNC

125
4 TSSOP

PP5V_VGA
VOLTAGE=5V

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM

R5972

74LCX125

ANALOG_HSYNC

58

R5980

5%
1/16W
MF-LF
402

VGA_HSYNC_R
NOSTUFF

C5907

22PF

58

5%
50V
2 CERM
402

TMDS_D1P

58

TMDS_D0M

DV01793
F-ST-TH
58

16

TMDS_D0P

58

VGA_HSYNC_R
FILT_ANALOG_RED
FILT_ANALOG_GRN
FILT_ANALOG_BLU
I2C_MON_SCL_R
MON_DETECT

3 4

R5941
0

59

402

NOSTUFF
FL5902

58 6

VGA_VSYNC_R

7
8
9
10
11

PP5V_VGA
I2C_MON_SDA_R

59

12(BLU_RTN)
13

1 C5905
0.01UF
2

18

10%
16V
CERM
402

1 C5904
0.01UF
2

10%
16V
CERM
402

1 C5903
0.01UF
2

58

10%
16V
CERM
402

TCKP
TCKM
TD0P
TD0M
TD1P
TD1M
TD2P
TD2M
FILT_ANALOG_GRN
FILT_ANALOG_RED
FILT_ANALOG_BLU

59 6

7 59

59 6

R5942
0

59 6
59 6

402

59 6

=PP3V3_AGP

59 58 56 50 49 48 7

59

59 6

PP5V_VGA

59 6
59 6

R59731

10K

5%
1/16W
MF-LF
402 2
58

R59771

R5974

10K

R5978

4.7K

5%
1/16W
MF-LF
2 402

2N7002DW

R5975

SOT-363
1 S

I2C_GPU_MON_SCL

D 6

100

2N7002DW

SOT-363
D 3 I2C_MON_SDA

5%
1/16W
MF-LF
2 402

I2C_MON_SCL_R

100

47PF
11 7

PP12V_RUN

NOSTUFF

NOSTUFF

R5950

PPVCC_FPD

R5922

5%
1/4W
MF-LF
2 1206

GND_CHASSIS_VGA

R5923

5%
1/4W
MF-LF
2 1206

5%
1/4W
MF-LF
2 1206

7 8

NOSTUFF

Q5900
SO-8

PP3V3_RUN

IRF7410

FPD_PWR_SW_G

376S0082
3

5%
1/4W
MF-LF
2 1206

FPD_PWR_SW_S
NOSTUFF

MIN_NECK_WIDTH=0.3MM
MIN_LINE_WIDTH=0.6MM

C5918

NOSTUFFC5919

0.022UF

120_INCH_LCD

R5935
0

5%
1/4W
MF-LF
2 1206

NOSTUFF

1 NOSTUFF

20%
16V
CERM
402

10K

NOSTUFF

R5925
1

100K

20%
16V
CERM
402

R5913

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

SOT23

FPD_PWR_ON_D
TMDS_EN_R

Q5901

FPD_PWR_ON
NOSTUFF1

R5915
100K
5%
1/16W
MF-LF
402

SOT23-LF

S
2

R5914
10K

2
56

1
C5917 R5960
10K

10UF
MMBD914XXG10%
16V

2N7002
59 56

D5914

NOSTUFF

TD0P

6 59

02

NET_SPACING_TYPE

TCKM

TCKP

6 59

6 59

0
2

TD0M
TD0P

59 6
59 6

TD2M
TD2P

59 6

59 6

I2C_TMDS_SDA

59 6

2 CERM
1210

59

7 59

PPVCC_TMDS

TCK
TCK
TD0
TD0
TD1
TD1
TD2
TD2

7 6

6 59

PP3V3_DDC

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

6 59
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

TCKM
TCKP

6 59
6 59

TD1M
TD1P
I2C_TMDS_SCL

6 59
6 59
6 59

C5916

C
C5900
0.01UF

10%
2 16V
CERM
1210

10%
16V
CERM
402

SDF5901
STDOFF-118OD-181H-TH

I886

I888
I889
I890
I892
I891
I893
I895
I894

Q5903_GATE

Q5903

SI3433DV
TSOP

59 50 7

=PP12V_AGP

59 50 7

R5919

R5921

SOT23

100K

59 56

LCD_PWM

Q5902

R5988

SOT23-LF
59 56

INV_CUR_HI

805
1

20%
10V
2 CERM
402

C5921

17_INCH_LCD

DEVELOPMENT

17_INCH_LCD

10UF

10UF

20%
16V
ELEC
SM

20%
16V
ELEC
SM

C5922

C5910

20%
50V
CERM
603

8
7

20%
50V
CERM
603

C5911

17_INCH_LCD
1

0.01UF
2

20%
50V
CERM
603

17_INCH_LCD

C5912

220PF
2

C5915
0.01UF

5%
25V
CERM
603

20%
50V
CERM
603

GND_CHASSIS_17_INCH_INVERTER

53048

20_INCH_LCD

R5989

=PP24V_GRAPHICS

805

RT-S-TH

VOLTAGE=24V
MIN_LINE_WIDTH=2MM
MIN_NECK_WIDTH=0.25MM

PP24V_INV

R5990

LED5900_PWR

125
10 TSSOP

R5912
59 56

LCD_PWM

SILKSCREEN: 3

INV_20_LCD_PWM_
INV_20_CUR_HI_F

805

59 56

INV_CUR_HI

1UF

20%
50V
CERM 2
1210

20_INCH_LCD

C5942

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

805

20_INCH_LCD

C5943

20_INCH_LCD

0.01UF
2

20%
50V
CERM
603

C5944

20_INCH_LCD

0.01UF
2

20%
50V
CERM
603

C5945

20_INCH_LCD

220PF
2

5%
25V
CERM
603

C5946

SIZE

0.01UF

20%
50V
CERM
603

APPLE COMPUTER INC.

REV.

051-6772
SHT
NONE

DRAWING NUMBER

SCALE

GND_CHASSIS_20_INCH_INVERTER

1UF

20%
50V
2 CERM
1210

NOTE:REMOVED 2 PINS:LAMP_STATUS &


ON/OFF FOR 20" LCD INVETER.

20_INCH_LCD

EXT VGA / TMDS


AND INVERTER

518-0141

R5992
C5947 1

6
6

20_INCH_LCD

NOSTUFF

GREEN
2.0X1.25A

GND_20_INV

R5991

330

SOT23

VOLTAGE=0V
MIN_LINE_WIDTH=2MM
MIN_NECK_WIDTH=0.25MM

805

5%
1/10W
MF-LF
2 603

1
2

20_INCH_LCD

DEVELOPMENT

0.01UF

CRITICAL

LED5900

DZ5900

C5913

J5901

14 74LCX125
9

17_INCH_LCD
1

0.01UF

20_INCH_LCD

U5970
FPD_PWR_ON

LEAVING CONNECTED
DURING DEVELOPMENT
SO WE CAN USE
Q45A INVERTERS

17_INCH_LCD

59 56

DEVELOPMENT

C5920

PIN 3 IS NC
ON Q45C
INVERTER

805

0.1UF

5%
1/16W
MF-LF
2 402

6 59

R5987

518-0135

805

DEVELOPMENT

R5916

LAMP_STS NOT USED ON Q45C


NC
6 INV_17_CUR_HI_F

17_INCH_LCD

2N7002

Q5902_GATE
DEVELOPMENT

MIN_LINE_WIDTH=2MM
MIN_NECK_WIDTH=0.25MM

Q5902_DRAIN

D5901
MMBD914XXG

5%
1/16W
MF-LF
2 402

PP5V_AGP_P_SEQ

10K

NOSTUFF

R5986

5%
1/16W
MF-LF
2 402

200K

PP12V_INV
GND_17_INV
PP5V_AGP_RL
INV_17_LCD_PWM_F

DEVELOPMENT

DEVELOPMENT

DEVELOPMENT

805

=PP12V_AGP

VOLTAGE=0V
MIN_LINE_WIDTH=2MM
VOLTAGE=5V
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=2MM
MIN_NECK_WIDTH=0.25MM

R5985
0

VOLTAGE=12V
MIN_LINE_WIDTH=2MM
MIN_NECK_WIDTH=0.25MM

17_INCH_LCD

42375
M-ST-TH

805

100K 2
5%
1/16W
MF-LF
402

CRITICAL

J5900

20" LCD INVERTER NEED +24V.


17" LCD INVERTER NEED +12V.

R5984

17_INCH_LCD

INVERTER INTERFACE

17_INCH_LCD

LED5900_P1

MMBZ5227B

GND_CHASSIS_TMDS

I887

R5920

5%
1/16W
MF-LF
402

PPVCC_TMDS
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

I885

DEVELOPMENT

5%
1/8W
MF-LF
805

5%
1/16W
MF-LF
2 402

20_INCH_LCD

DIFFERENTIAL_PAIR

GPU_TMDS
GPU_TMDS
GPU_TMDS
GPU_TMDS
GPU_TMDS
GPU_TMDS
GPU_TMDS
GPU_TMDS
GPU_VGA
GPU_VGA
GPU_VGA

R5981
1

=PP5V_AGP

50 7

TMDS_EN
3

10UF

VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM

0.01UF
2

PP12V_RUN

117_INCH_LCD

R5934

1 2
VOLTAGE=3.3V

5%
2 50V
CERM
402

NOSTUFF

C5978
47PF

5%
50V
CERM 2
402

PP3V3_ALL
1

59

e
r

I2C_MON_SDA_R

C5977

6 59

SYM_VER-1

90-OHM
SM

DEVELOPMENT

R5976
5%
1/16W
MF-LF
402

PP3V3_RUN

59 6

5%
1/16W
MF-LF
402

Q5975

4 S

I2C_GPU_MON_SDA

I2C_MON_SCL

59 6

4.7K

5%
1/16W
MF-LF
402 2

Q5975

G
58

GPU_TMDS
GPU_TMDS
GPU_TMDS
GPU_TMDS
GPU_TMDS
GPU_TMDS
GPU_TMDS
GPU_TMDS
GPU_VGA_75
GPU_VGA_75
GPU_VGA_75

m
il
59 6

PLACE R5821-3 & FL5900-2 CLOSE TO J5903 ON BOTTOM SIDE OF BOARD

TD0M

NET_PHYSICAL_TYPE

GND_CHASSIS_VGA

3 4

TMDS_CKP

6 59

CRITICAL

F-ST-SM

R5933

14

I2C_TMDS_SDA

53307-3072

SYM_VER-1

1%
1/16W
MF-LF
2 402

59

6 59

5%
1/16W
MF-LF
402

(516S0241)

R5901
332

17

ANALOG_BLU

02

R5931

6 (GRN_RTN)

I2C_TMDS_SCL

SDF5900

NOSTUFF
L5910

4 (RED_RTN)

LCFILTER
58 6

TMDS_CKM

59

SM-220MHZ

y
r

5%
1/16W
MF-LF
402

STDOFF-118OD-181H-TH

R5932

SM-220MHZ

59

6 59

SM

1%
1/16W
MF-LF
2 402

15

ANALOG_GRN

TD1P

a
n
i
R5902
332

J5903

NOSTUFF
FL5901

6 59

R5906
33

R5900
33

10%
16V
CERM
402

J5902

NOSTUFF
L5909
90-OHM 1

LCFILTER
58 6

(514-0201)

402

TD1M

CRITICAL

R5940

SM

1 C5901
0.01UF
2

6 59

INTERNAL TMDS CONNECTOR

2
3 4

90-OHM

R5930

SM-220MHZ

ANALOG_RED

SYM_VER-1

PP3V3_DDC

5%
1/16W
MF-LF
2 402

I2C_GPU_TMDS_SDA

58

1%
1/16W
MF-LF
402

2.0K

I2C_GPU_TMDS_SCL

58

7 59

LCFILTER
58 6

6 59

NOSTUFF
L5908

R5929
58

TD2P

R5907

5%
1/16W
MF-LF
402 2

02

R5903
332

7 59

5%
1/8W
MF-LF
805

2.0K

6 59

02

GND_CHASSIS_VGA

GND_CHASSIS_VGA

R5927

TMDS_D1M

C5902

TD2M

3
1

10%
16V
2 CERM
402

C5908

R5928

59

R59051

SYM_VER-1

TMDS_D2P

0.01UF

22PF

5%
50V
CERM 2
402

NOSTUFF
FL5900

5%
1/8W
MF-LF
805

59

NOSTUFF
1

R5982

=PP3V3_AGP

SM

1%
1/16W
MF-LF
2 402

59

92

14

R5904
332

58

59 58 56 50 49 48 7

125
13 TSSOP

=PP3V3_AGP

59 58 56 50 49 48 7

02

NOSTUFF
L5902
90-OHM 1

11

5%
1/16W
MF-LF
402

U5970

TMDS_D2M

125
1 TSSOP

58

14 74LCX125

C5970

59 58 56 50 49 48 7

04

OF

59

102

ELECTRICAL_CONSTRAINT_SET

R6000
C6013

C6012

=PP1V2_HT

64 62 60

20%
2 10V
CERM
402

64 62 60

HT_CLK
AVDD

64 62 60
64 62 60

64 62 60
64 62 60
64 62 60
64 62 60
64 62 60
64 62 60
64 62 60
64 62 60
64 62 60
64 62 60
64 62 60

64 60 7

64 62 60

=PP2V5_HT

64 62 60
64 62 60

R6005 R6004 R6003 R6002


1K

1K

5%
1/16W
MF-LF
2 402

1K

5%
1/16W
MF-LF
2 402

1K

5%
1/16W
MF-LF
2 402

5%
1/16W
MF-LF
2 402

64 62 60
64 62 60

7 24 60

0.1UF

10%
2 6.3V
CERM
402

27

64 62 60

VDD_HT
2_5

HT_CLK66M_NB

H9 HT_CLK

HT_SB_TO_NB_CLK_P
HT_SB_TO_NB_CLK_N

N1 HT_CLK_RXP0
P1 HT_CLK_RXN0

64 62 60

VDD_HT
1_2

64 62 60

U3

64 62 60

U3LITE
V1.0-300MM
PBGA
(SYM 5 OF 7)

HT
INTERFACE

L1 HT_CAD_RXP0
L2 HT_CAD_RXN0

HT_SB_TO_NB_CAD_P<0>
HT_SB_TO_NB_CAD_N<0>
HT_SB_TO_NB_CAD_P<1>
HT_SB_TO_NB_CAD_N<1>
HT_SB_TO_NB_CAD_P<2>
HT_SB_TO_NB_CAD_N<2>
HT_SB_TO_NB_CAD_P<3>
HT_SB_TO_NB_CAD_N<3>
HT_SB_TO_NB_CAD_P<4>
HT_SB_TO_NB_CAD_N<4>
HT_SB_TO_NB_CAD_P<5>
HT_SB_TO_NB_CAD_N<5>
HT_SB_TO_NB_CAD_P<6>
HT_SB_TO_NB_CAD_N<6>
HT_SB_TO_NB_CAD_P<7>
HT_SB_TO_NB_CAD_N<7>

64 62 60

L9

1UF

64 62 60

N10

64 62 60
7 60 64

N2
N6

5%
1/10W
MF-LF
603

=PP2V5_HT

PP1V5_PWRON_HT_NB_AVDD
VOLTAGE=1.5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

R9

2.2

T4
T8

J10
G6

=PP1V5_PWRON_NB_AVDD

F8

48 37 28 7

64 62 60

OMIT

64 62 60
64 62 60

HT_CLK_TXP0 R7
HT_CLK_TXN0 R8

HT_NB_TO_SB_CLK_P
HT_NB_TO_SB_CLK_N

60 62 64

64 62 60

60 62 64

64 62 60
64 62 60

HT_CAD_TXP0 U8
HT_CAD_TXN0 U7

L3 HT_CAD_RXP1
L4 HT_CAD_RXN1
M4 HT_CAD_RXP2
M3 HT_CAD_RXN2

HT_CAD_TXP1 U6
HT_CAD_TXN1 U5
HT_CAD_TXP2 U4
HT_CAD_TXN2 U3

M2 HT_CAD_RXP3
M1 HT_CAD_RXN3
P2 HT_CAD_RXP4

HT_CAD_TXP3 R5
HT_CAD_TXN3 R6
HT_CAD_TXP4 P8

P3 HT_CAD_RXN4
R3 HT_CAD_RXP5
R2 HT_CAD_RXN5

HT_CAD_TXN4 P7
HT_CAD_TXP5 P6
HT_CAD_TXN5 P5

R1 HT_CAD_RXP6
T1 HT_CAD_RXN6
U1 HT_CAD_RXP7

HT_CAD_TXP6 M5
HT_CAD_TXN6 M6
HT_CAD_TXP7 M7

U2 HT_CAD_RXN7

HT_CAD_TXN7 M8

HT_NB_TO_SB_CAD_P<0>
HT_NB_TO_SB_CAD_N<0>
HT_NB_TO_SB_CAD_P<1>
HT_NB_TO_SB_CAD_N<1>
HT_NB_TO_SB_CAD_P<2>
HT_NB_TO_SB_CAD_N<2>
HT_NB_TO_SB_CAD_P<3>
HT_NB_TO_SB_CAD_N<3>
HT_NB_TO_SB_CAD_P<4>
HT_NB_TO_SB_CAD_N<4>
HT_NB_TO_SB_CAD_P<5>
HT_NB_TO_SB_CAD_N<5>
HT_NB_TO_SB_CAD_P<6>
HT_NB_TO_SB_CAD_N<6>
HT_NB_TO_SB_CAD_P<7>
HT_NB_TO_SB_CAD_N<7>

60 62 64

64 62 60

60 62 64

64 62 60

60 62 64

64 62 60

60 62 64

64 62 60

60 62 64

64 62 60

64 62 60

60 62 64

64 62 60

60 62 64

64 62 60
64 62 60

60 62 64
60 62 64

64 62 60

60 62 64

64 62 60

60 62 64

64 62 60

60 62 64

64 62 60
64 62 60

60 62 64

64 62 60

60 62 64

64 62 60

HT_CTL_TXP0 L6
HT_CTL_TXN0 L5

V2 HT_CTL_RXP0
V1 HT_CTL_RXN0

HT_SB_TO_NB_CTL_P
HT_SB_TO_NB_CTL_N

HT_NB_TO_SB_CTL_P
HT_NB_TO_SB_CTL_N

60 62 64

64 62 60

60 62 64

64 62 60
64 62 60

64 62 60
64 62 60
64 62 60
64 62 60

F9 HT_PWROK
G9 HT_RESET*
H8 HT_LDTSTOP*

HT_PWROK
HT_RESET_L
HT_LDTSTOP_L
HT_LDTREQ_L

H7

64 62 60
64 62 60

HT_PVTREF0 L7
HT_PVTREF1 L8

HT_LDTREQ*

HT_NB_PVTREF0
HT_NB_PVTREF1

64 62 60
64 62 60

R6001

HT_CLK_AVSS
G8

200

64 60 7

=PP2V5_HT

60 24 7

C6010
0.1UF

20%
2 10V
CERM
402

C6011
0.1UF

20%
2 10V
CERM
402

=PP1V2_HT

C6000
0.1UF

20%
2 10V
CERM
402

0.1UF

20%
2 10V
CERM
402

C6002
0.1UF

20%
2 10V
CERM
402

C6004
0.1UF

20%
2 10V
CERM
402

64 62 60

1%
1/16W
MF-LF
2 402

m
il

e
r

C6001

C6005
0.1UF

20%
2 10V
CERM
402

C6006
0.1UF

20%
2 10V
CERM
402

C6007
0.1UF

20%
2 10V
CERM
402

64 62 60

64 62 60
64 62 60
64 62 60
64 62 60

NET_SPACING_TYPE
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB

HT_NB_TO_SB_CLK
HT_NB_TO_SB_CLK
HT_NB_TO_SB_CTL
HT_NB_TO_SB_CTL
HT_NB_TO_SB_CAD0
HT_NB_TO_SB_CAD0
HT_NB_TO_SB_CAD1
HT_NB_TO_SB_CAD1
HT_NB_TO_SB_CAD2
HT_NB_TO_SB_CAD2
HT_NB_TO_SB_CAD3
HT_NB_TO_SB_CAD3
HT_NB_TO_SB_CAD4
HT_NB_TO_SB_CAD4
HT_NB_TO_SB_CAD5
HT_NB_TO_SB_CAD5
HT_NB_TO_SB_CAD6
HT_NB_TO_SB_CAD6
HT_NB_TO_SB_CAD7
HT_NB_TO_SB_CAD7
HT_SB_TO_NB_CLK
HT_SB_TO_NB_CLK
HT_SB_TO_NB_CTL
HT_SB_TO_NB_CTL
HT_SB_TO_NB_CAD0
HT_SB_TO_NB_CAD0
HT_SB_TO_NB_CAD1
HT_SB_TO_NB_CAD1
HT_SB_TO_NB_CAD2
HT_SB_TO_NB_CAD2
HT_SB_TO_NB_CAD3
HT_SB_TO_NB_CAD3
HT_SB_TO_NB_CAD4
HT_SB_TO_NB_CAD4
HT_SB_TO_NB_CAD5
HT_SB_TO_NB_CAD5
HT_SB_TO_NB_CAD6
HT_SB_TO_NB_CAD6
HT_SB_TO_NB_CAD7
HT_SB_TO_NB_CAD7

HT_SB_TO_NB_CLK_P
HT_SB_TO_NB_CLK_N
HT_SB_TO_NB_CTL_P
HT_SB_TO_NB_CTL_N
HT_SB_TO_NB_CAD_P<0>
HT_SB_TO_NB_CAD_N<0>
HT_SB_TO_NB_CAD_P<1>
HT_SB_TO_NB_CAD_N<1>
HT_SB_TO_NB_CAD_P<2>
HT_SB_TO_NB_CAD_N<2>
HT_SB_TO_NB_CAD_P<3>
HT_SB_TO_NB_CAD_N<3>
HT_SB_TO_NB_CAD_P<4>
HT_SB_TO_NB_CAD_N<4>
HT_SB_TO_NB_CAD_P<5>
HT_SB_TO_NB_CAD_N<5>
HT_SB_TO_NB_CAD_P<6>
HT_SB_TO_NB_CAD_N<6>
HT_SB_TO_NB_CAD_P<7>
HT_SB_TO_NB_CAD_N<7>

HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB

HT_CAD
HT_CAD
HT_CAD
HT_CAD
HT_CAD
HT_CAD
HT_CAD
HT_CAD
HT_CAD
HT_CAD
HT_CAD
HT_CAD
HT_CAD
HT_CAD
HT_CAD
HT_CAD
HT_CAD
HT_CAD
HT_CAD
HT_CAD

HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB
HT_SB_TO_NB

HT_PWROK
HT_RESET_L
HT_LDTSTOP_L
HT_LDTREQ_L

HT_PWROK
HT_CTL
HT_CTL
HT_CTL

HT_2V5
HT_2V5
HT_2V5
HT_2V5

HT_2V5
HT_2V5
HT_2V5
HT_2V5

HT_NB_TO_SB

I46
I47
I83
I82
I51
I50
I52

I53
I54
I55
I56
I57
I58
I59
I60
I61
I62
I63
I64
I65

I48
I49
I84
I85
I66
I67
I68
I69
I70
I71
I72
I73
I74

I75
I76
I77
I78
I79
I80
I81

I86
I87
I88
I89

HT_SB_TO_NB

HT_2V5

5 MIL SPACING FOR DIFF PAIR


10 MIL SPACING TO ANYTHING ELSE

C6008

DIFFERENTIAL_PAIR

HT_CAD
HT_CAD
HT_CAD
HT_CAD
HT_CAD
HT_CAD
HT_CAD
HT_CAD
HT_CAD
HT_CAD
HT_CAD
HT_CAD
HT_CAD
HT_CAD
HT_CAD
HT_CAD
HT_CAD
HT_CAD
HT_CAD
HT_CAD

y
r

a
n
i

60 62 64

NET_PHYSICAL_TYPE

HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB
HT_NB_TO_SB

60 62 64

64 62 60

64 62 60

HT_NB_TO_SB_CLK_P
HT_NB_TO_SB_CLK_N
HT_NB_TO_SB_CTL_P
HT_NB_TO_SB_CTL_N
HT_NB_TO_SB_CAD_P<0>
HT_NB_TO_SB_CAD_N<0>
HT_NB_TO_SB_CAD_P<1>
HT_NB_TO_SB_CAD_N<1>
HT_NB_TO_SB_CAD_P<2>
HT_NB_TO_SB_CAD_N<2>
HT_NB_TO_SB_CAD_P<3>
HT_NB_TO_SB_CAD_N<3>
HT_NB_TO_SB_CAD_P<4>
HT_NB_TO_SB_CAD_N<4>
HT_NB_TO_SB_CAD_P<5>
HT_NB_TO_SB_CAD_N<5>
HT_NB_TO_SB_CAD_P<6>
HT_NB_TO_SB_CAD_N<6>
HT_NB_TO_SB_CAD_P<7>
HT_NB_TO_SB_CAD_N<7>

4 MIL SPACING IN GROUP


8 MIL SPACING TO ANYTHING ELSE

LENGTH TOLERENCE CAN BE LOOSE


MATCHED GROUP CONSTRAINT IS TIGHT ENOUGH

0.1UF

20%
2 10V
CERM
402

MASTER: GILA
LAST MODIFIED: APR 12, 04

U3LITE HT
A

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6772

60

OF

04
102

8
ELECTRICAL_CONSTRAINT_SET

7
NET_SPACING_TYPE

DIFFERENTIAL_PAIR
HT_CLK66M_SB_C

15 MIL SPACING

62

Page Notes
Power aliases required by this page:
- _PP2V5_PWRON_HT
- _PP1V2_PWRON_HT

Signal aliases required by this page:


(NONE)

BOM options provided by this page:


- SB_HT_200M
Stuffs resistor to select 200MHz HT I/F.

=PP2V5_PWRON_HT

62 7

3.3

5%
1/8W
MF-LF
805

C6200
10uF

C6201
1uF

=PP1V2_PWRON_HT

10%
6.3V
2 CERM
402

C6230

R6210
3.3

20%
2 10V
CERM
402

PP1V2_PWRON_HT_PLLAVDD
VOLTAGE=1.2V
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=15 mil

5%
1/8W
MF-LF
805

NOSTUFF

C6210

C6211
G11

B9

B12

B17
G13

B15

10%
6.3V
2 CERM
402

20%
10V
2 CERM
402

U2300

C6240
0.1uF

AVDD DVDD VDDP HT_RXVDD HT_TXVDD


HT_PLL
HT OMIT

SHASTA
V1.0

64 60
64 60
64 60
64 60
64 60
64 60
64 60
64 60
64 60
64 60

64 60

C6255
0.1uF

27

HT_CLK66M_SB

R62551
332

1%
1/16W
MF-LF
402 2

P
62 7

64 60

64 60

62

20%
10V
CERM
402

AC coupled
1.0V pk-pk

HT_CADOUT_4_P A11
HT_CADOUT_4_N B11
HT_CADOUT_5_P C12
HT_CADOUT_5_N D12
HT_CADOUT_6_P E12
HT_CADOUT_6_N F12

B14 HT_CADIN_7_P
A14 HT_CADIN_7_N

HT_CADOUT_7_P A13
HT_CADOUT_7_N B13

F13 HT_CTLIN_P
E13 HT_CTLIN_N

HT_NB_TO_SB_CTL_P
HT_NB_TO_SB_CTL_N
HT_PWROK
HT_RESET_L
HT_LDTSTOP_L

HT_CADOUT_2_N F11
HT_CADOUT_3_P D11
HT_CADOUT_3_N C11

C14 HT_CADIN_5_N
E14 HT_CADIN_6_P
F14 HT_CADIN_6_N

HT_CTLOUT_P C13
HT_CTLOUT_N D13

E16 HT_PWROK_H
C18 HT_RESET_L
E17 HT_LDTSTOP_L

HT_LDTREQ_L

C8 HT_REFCLK
D8 HT_S100M66M
V6 SEL_HT00_H

HT_CLK66M_SB_C
SB_HT_S100M66M
SB_SELHT100

HT_PLL
AGND DGND
C6

64 60

B16 HT_CADIN_4_P
A16 HT_CADIN_4_N
D14 HT_CADIN_5_P

HT_CADOUT_1_N A8
HT_CADOUT_2_P E11

20%
2 10V
CERM
402

HT_TXGND

C6241

47pF

5%
50V
CERM 2
402

20%
10V
2 CERM
402

7 62

60 64
60 64

60 64
60 64
60 64
60 64
60 64
60 64

60 64
60 64
60 64
60 64
60 64
60 64
60 64
60 64
60 64
60 64

60 64
60 64

60 64

R6250
1

C6250 1

C6242
0.1uF

20%
10V
2 CERM
402

HT_SB_TO_NB_CTL_P
HT_SB_TO_NB_CTL_N

SB_HT_R100_P
SB_HT_R100_N

0.1uF

A19 HT_LDTREQ_L

HT_R100P E10
HT_R100N F10

HT_RXGND

HT_SB_TO_NB_CAD_P<0>
HT_SB_TO_NB_CAD_N<0>
HT_SB_TO_NB_CAD_P<1>
HT_SB_TO_NB_CAD_N<1>
HT_SB_TO_NB_CAD_P<2>
HT_SB_TO_NB_CAD_N<2>
HT_SB_TO_NB_CAD_P<3>
HT_SB_TO_NB_CAD_N<3>
HT_SB_TO_NB_CAD_P<4>
HT_SB_TO_NB_CAD_N<4>
HT_SB_TO_NB_CAD_P<5>
HT_SB_TO_NB_CAD_N<5>
HT_SB_TO_NB_CAD_P<6>
HT_SB_TO_NB_CAD_N<6>
HT_SB_TO_NB_CAD_P<7>
HT_SB_TO_NB_CAD_N<7>

m
il

e
r
64 60

C6232
0.1uF

20%
2 10V
CERM
402

HT_SB_TO_NB_CLK_P
HT_SB_TO_NB_CLK_N

G10

64 60

A18 HT_CADIN_1_N
F15 HT_CADIN_2_P
E15 HT_CADIN_2_N
D16 HT_CADIN_3_P
C16 HT_CADIN_3_N

A9

64 60

HT_CADOUT_0_P D10
HT_CADOUT_0_N C10
HT_CADOUT_1_P B8

A12

64 60

D17 HT_CADIN_0_P
C17 HT_CADIN_0_N
B18 HT_CADIN_1_P

HYPERTRANSPORT

64 60

HT_NB_TO_SB_CAD_P<0>
HT_NB_TO_SB_CAD_N<0>
HT_NB_TO_SB_CAD_P<1>
HT_NB_TO_SB_CAD_N<1>
HT_NB_TO_SB_CAD_P<2>
HT_NB_TO_SB_CAD_N<2>
HT_NB_TO_SB_CAD_P<3>
HT_NB_TO_SB_CAD_N<3>
HT_NB_TO_SB_CAD_P<4>
HT_NB_TO_SB_CAD_N<4>
HT_NB_TO_SB_CAD_P<5>
HT_NB_TO_SB_CAD_N<5>
HT_NB_TO_SB_CAD_P<6>
HT_NB_TO_SB_CAD_N<6>
HT_NB_TO_SB_CAD_P<7>
HT_NB_TO_SB_CAD_N<7>

G12

64 60

D15 HT_CLKIN_P
C15 HT_CLKIN_N

A17

64 60

HT_NB_TO_SB_CLK_P
HT_NB_TO_SB_CLK_N

BGA
B10
(3 OF 8) HT_CLKOUT_P
HT_CLKOUT_N A10

A15

64 60

A6

64 60

0.1uF

=PP1V2_PWRON_HT

1uF
B19

20%
6.3V
2 CERM
1206

B6

10uF

C7

C6231

7 62

a
n
i

0.1uF

y
r

20%
10V
2 CERM
402

NOSTUFF
1

20%
6.3V
2 CERM
1206

C6220
0.1uF

PP1V2_PWRON_HT_PLLDVDD
VOLTAGE=1.2V
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=15 mil

R6200

=PP1V2_PWRON_HT

82.5 2
1%
1/16W
MF-LF
402

C6251
47pF

5%
50V
2 CERM
402

=PP1V2_PWRON_HT

NO STUFF

R62521

R62541

5%
1/16W
MF-LF
402 2

5%
1/16W
MF-LF
402 2

4.7K

10K

SB_HT_200M

R62531

R62511

5%
1/16W
MF-LF
402 2

5%
1/16W
MF-LF
402 2

4.7K

MASTER: SEEDY

1K

Shasta HyperTransport

NOTICE OF PROPRIETARY PROPERTY

HT RefClk

HT I/F Speed

1 = 100MHz
0 = 66MHz

1 = 100MHz
0 = 200MHz

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-6772

04

OF

62

102

SAME CONNECTORS & PINOUT AS

y
r

Q37 HYPERTRANSPORT BETWEEN GOLEM AND K2

NOSTUFF

NOSTUFF

J6400

a
n
i

J6401

P6860

P6860

ST-SM-DF

ST-SM-DF

SYM_VER1

SYM_VER1

A15

62 60

HT_NB_TO_SB_CLK_N

A14

CLK-

HT_NB_TO_SB_CLK_P

A13

GND

62 60

62 60

HT_NB_TO_SB_CAD_P<6>

A12

62 60

B12
D15

B11

GND

B10

CLK+

A11

GND

62 60

HT_NB_TO_SB_CAD_N<6>

A10

62 60

HT_NB_TO_SB_CAD_N<4>

A9

B9
D11

B8

GND

B7

D9

GND

62 60

HT_NB_TO_SB_CAD_P<4>

62 60

HT_NB_TO_SB_CAD_N<2>

A6

62 60

HT_NB_TO_SB_CAD_P<2>

D7

B5

GND

B4

D8

D5

A4

GND

B3
D3

B2

GND

B1

D4

62 60

HT_NB_TO_SB_CAD_N<0>

62 60

HT_NB_TO_SB_CAD_P<0>

60 62

HT_NB_TO_SB_CAD_P<5>

60 62

HT_SB_TO_NB_CAD_N<0>

A13

HT_SB_TO_NB_CAD_N<2>

A12

A3
D1

A1

GND

D15

B11

GND

B10

HT_SB_TO_NB_CAD_P<2>

HT_NB_TO_SB_CAD_P<3>

60 62

HT_NB_TO_SB_CAD_N<3>

60 62

HT_SB_TO_NB_CAD_P<4>

A11

D13

A10

GND

A9
A8

62 60

HT_SB_TO_NB_CAD_N<4>

D11

B8

GND

B7

62 60

HT_SB_TO_NB_CAD_P<6>

62 60

HT_SB_TO_NB_CAD_N<6>

HT_SB_TO_NB_CAD_N<1>

60 62

62 60

A7

D5

A4

GND

HT_SB_TO_NB_CAD_P<3>

60 62

HT_SB_TO_NB_CAD_N<3>

60 62

HT_SB_TO_NB_CAD_N<5>

60 62

D7

B5

GND

B4

HT_SB_TO_NB_CAD_P<5>

60 62

B3

HT_SB_TO_NB_CAD_N<7>

60 62

D3

HT_SB_TO_NB_CTL_P

62 60

HT_SB_TO_NB_CTL_N

A3

D1

A1

GND

TEK_HT_A12

TEK_HT_A10
TEK_HT_A9

HT_SB_TO_NB_CAD_P<7>

5%
1/10W
MF-LF
603

62 60

B2
B1

A14

CLK-

A13

GND

HT_LDTSTOP_L

60 62

D0

62 60

B12
B11

GND

B10

TEK_HT_B10

B9

HT_RESET_L

HT_PWROK

A11

D13

A10

GND

D11

B8

GND

B7

A9

A7

60 62

D10
D9

B6

GND
D7

B5

GND

B4

D8

A6

HT_LDTREQ_L

60 62

D6

A5

D5

A4

GND

B3
D3

B2

GND

B1

D4

A3

HT_NB_TO_SB_CTL_N

60 62

HT_NB_TO_SB_CTL_P

60 62

D2

A2

D1

A1

GND

D0

=PP2V5_HT
DEVELOPMENT

7 60

R6401

10K

5%
1/16W
MF-LF

2 402

HT_VREF_DEBUG
VOLTAGE=1.25V
MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL

DEVELOPMENT

R6402

10K

5%
1/16W
MF-LF

e
r

5%
1/10W
MF-LF
603

TEK_HT_B12

D14

A8

TEK_HT_A7

D15

A12

D12

R6404

NOSTUFF

R6400

A15

CLK+

5%
1/10W
603

D2

A2

HT_SB_TO_NB_CLK_P

R6403

m
il
GND

62 60

SYM_VER1

HT_SB_TO_NB_CLK_N

D6

A5

ST-SM-DF

NOSTUFF

B6

GND

A6

P6860

NOSTUFF

D10

D4

60 62

D0

60 62

D9

D8

60 62

HT_SB_TO_NB_CAD_P<1>

D14

D12

D2

A2

B12

B9
62 60

HT_NB_TO_SB_CAD_N<1>

GND

CLK+

HT_NB_TO_SB_CAD_N<5>

HT_NB_TO_SB_CAD_P<1>

CLK-

62 60

D6

A5

62 60

A14
62 60

62 60

B6

A15

60 62

D10

A8
A7

HT_NB_TO_SB_CAD_P<7>

60 62

D14
D13

D12

HT_NB_TO_SB_CAD_N<7>

HT_SB_TO_NB_CAD_P<0>

NOSTUFF

J6402

2 402

MASTER: GILA
LAST MODIFIED: APR 12, 04

HT DEBUG CONN
A

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6772

64

OF

04
102

ALL RESISTOR PACKS ARE 47 OHM 1/16W 5%

R PAKS ARE PIN SWAPPABLE ACROSS ALL SIGNALS (EXCEPT IDSELS)

74

PCI_SB_AD<0>
PCI_SB_AD<1>
PCI_SB_AD<2>
PCI_SB_AD<3>
PCI_SB_AD<4>
PCI_SB_AD<5>
PCI_SB_AD<6>
PCI_SB_AD<7>
PCI_SB_AD<8>
PCI_SB_AD<9>
PCI_SB_AD<10>
PCI_SB_AD<11>
PCI_SB_AD<12>
PCI_SB_AD<13>
PCI_SB_AD<14>
PCI_SB_AD<15>
PCI_SB_AD<16>

74

PCI_SB_AD<17>

74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74

RP7300
RP7303
RP7303
RP7303
RP7309
RP7300
RP7300
RP7309
RP7300
RP7301
RP7301
RP7301
RP7309
RP7309
RP7301
RP7307
RP7308

47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47

PCI_AD<0>
PCI_AD<1>
PCI_AD<2>
PCI_AD<3>
PCI_AD<4>
PCI_AD<5>
PCI_AD<6>
PCI_AD<7>
PCI_AD<8>
PCI_AD<9>
PCI_AD<10>
PCI_AD<11>
PCI_AD<12>
PCI_AD<13>
PCI_AD<14>
PCI_AD<15>
PCI_AD<16>

y
r

6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77

a
n
i

6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77

R7300
1

47

PCI_AD<17>

6 74 75 76 77

5%
1/16W
MF-LF
402

74
74
74
74
74
74
74
74
74

PCI_SB_AD<18>
PCI_SB_AD<19>
PCI_SB_AD<20>
PCI_SB_AD<21>
PCI_SB_AD<22>
PCI_SB_AD<23>
PCI_SB_AD<24>
PCI_SB_AD<25>
PCI_SB_AD<26>

RP7307
RP7306
RP7305
RP7305
RP7302
RP7302
RP7304
RP7306
RP7305

47
47
47
47
47
47
47
47
47

PCI_AD<18>
PCI_AD<19>
PCI_AD<20>
PCI_AD<21>
PCI_AD<22>
PCI_AD<23>
PCI_AD<24>
PCI_AD<25>
PCI_AD<26>

6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 76 77
6 74 76 77
6 74 76 77
6 74 75 76 77
6 74 75 76 77

m
il
3

6 74 75 76 77

R7301

74

PCI_SB_AD<27>

47

PCI_AD<27>

6 74 75 76 77

5%
1/16W
MF-LF
402

74
74
74
74

74
74

PCI_SB_AD<28>
PCI_SB_AD<29>
PCI_SB_AD<30>
PCI_SB_AD<31>

RP7302
RP7304
RP7302
RP7304

PCI_SB_CBE_L<0>
PCI_SB_CBE_L<1>
PCI_SB_CBE_L<2>
PCI_SB_CBE_L<3>

RP7303
RP7306
RP7305
RP7304

PCI_SB_DEVSEL_L
PCI_SB_FRAME_L
PCI_SB_IRDY_L
PCI_SB_TRDY_L
PCI_SB_STOP_L
PCI_SB_PAR

RP7306
RP7307
RP7307
RP7308
RP7308
RP7308

e
r
74
74

74
74

74
74
74
74

47
47
47
47

PCI_AD<28>
PCI_AD<29>
PCI_AD<30>
PCI_AD<31>

47
47
47
47

PCI_CBE_L<0>
PCI_CBE_L<1>
PCI_CBE_L<2>
PCI_CBE_L<3>

47
47
47
47
47
47

PCI_DEVSEL_L
PCI_FRAME_L
PCI_IRDY_L
PCI_TRDY_L
PCI_STOP_L
PCI_PAR

6 74 75 76 77
6 74 75 76 77
6 74 75 76 77
6 74 75 76 77

6 74 76 77
6 74 76 77
6 74 76 77
6 74 76 77

6 74 76 77
6 74 76 77

6 74 76 77
6 74 76 77
6 74 76 77
6 74 76 77

PLACE CLOSE TO SHASTA

AD<17> IS IDSEL FOR AIRPORT


AD<27> IS IDSEL FOR USB

PCI SERIES TERMINATION

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6772

73

OF

04
102

8
ELECTRICAL_CONSTRAINT_SET

7
NET_SPACING_TYPE

DIFFERENTIAL_PAIR

PCI_AD
PCI_AD27
PCI_AD
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD
PCI_AD17
PCI_AD

PCI_AD<31..28>
PCI_AD<27>
PCI_AD<26..24>
PCI_AD<23>
PCI_AD<22>
PCI_AD<21>
PCI_AD<20>
PCI_AD<19..18>
PCI_AD<17>
PCI_AD<16..0>

PCI
PCI
PCI_CTL
PCI_CTL
PCI_CTL
PCI_CTL
PCI_CTL

PCI_CBE_L<3..0>
PCI_PAR
PCI_DEVSEL_L
PCI_FRAME_L
PCI_IRDY_L
PCI_TRDY_L
PCI_STOP_L

6 73 75 76 77
6 73 75 76 77
6 73 75 76 77
6 73 76 77
6 73 76 77
6 73 76 77
6 73 75 76 77
6 73 75 76 77
6 73 75 76 77
6 73 75 76 77

6 73 76 77
6 73 76 77

y
r

6 73 74 76 77
6 73 74 76 77
6 73 74 76 77
6 73 74 76 77
6 73 74 76 77

Page Notes
Power aliases required by this page:
- _PP3V3_PCI
- _PP3V3_SB_PCI (can be _PP3V3_PCI)
- _PP3V3_PWRON_SB
- _PP2V5_PWRON_SB

Signal aliases required by this page:


(NONE)

NO STUFF
1

C7410

20%
2 6.3V
CERM
805

BOM options provided by this page:


(NONE)

20%
2 10V
CERM
402

C7401
0.1uF

20%
2 10V
CERM
402

C7402
0.1uF

C7403
0.1uF

20%
2 10V
CERM
402

C7404
0.1uF

20%
2 10V
CERM
402

20%
2 10V
CERM
402

NO STUFF

0.1uF

20%
10V
2 CERM
402

C7406
0.1uF

20%
10V
2 CERM
402

C7407
0.1uF

20%
10V
2 CERM
402

C7408
0.1uF

C7409

C7420 1 C7421

0.1uF

20%
10V
2 CERM
402

0.1uF

20%
10V
CERM 2
402

20%
10V
2 CERM
402

VDDOPC

N20
U20

C7405

J18

PCI1)
PCI0 or 2)
PCI0 or 2)
PCI0 or 2)
PCI0)

B20

20%
6.3V
2 CERM
805

U21
V19

10uF

N21
R20

C7411

M16

H16
J21

(0x106B/0x004F,
(0x1166/0x0240,
(0x106B/0x0050,
(0x106B/0x0052,
(0x106B/0x0051,

0.1uF

E21

KeyLargo
SATA 150
UATA 133
FireWire
Ethernet

C7400

AA22
B22

=PP2V5_PWRON_SB

PCI Devices implemented on this page:


AD11 - PCI0
(0x106B/0x0053)
AD11 - PCI1
(0x106B/0x0054)
AD11 - PCI2
(0x106B/0x0055)
AD23
AD28
AD29
AD30
AD31

a
n
i

=PP3V3_SB_PCI

10uF

PCIVDDP

U2300

OMIT

SHASTA

m
il
V1.0

27

PCI_CLK66M_SB_INT

AB9 PCIBR_CLK_H

27 8

PCI_CLK33M_SB_EXT

U19 PCI1CLK_H

BGA
(4 OF 8)

PCI

=PP3V3_PCI 7

76 74 6

25 74 75 76 77

76 74 6

RP7400
4.7K
2

PCI_SLOTA_REQ_L

5%
1/16W
SM-LF

PCI_SLOTA_GNT_L

4.7K

PCI_SLOTG_GNT_L

74 77

74

74 77

5%
1/16W
SM-LF

PCI_SLOTD_REQ_L

74

RP7401
4

4.7K

PCI_SLOTD_GNT_L

"Slot A" - AD17


PCI_SLOTA_REQ_L
PCI_SLOTA_GNT_L

e
r

6 74 76

74

PCI_SLOTG_REQ_L

RP7401
5%
1/16W
SM-LF

77 74

RP7400
3

4.7K

5%
1/16W
SM-LF

77 74

5%
1/16W
SM-LF

RP7400
4.7K
4

6 74 76

RP7400
4.7K
1

74

5%
1/16W
SM-LF

76 75 6
76 75 6
76 75 6

"Slot G" - AD27


PCI_SLOTG_REQ_L
PCI_SLOTG_GNT_L
"Slot D" - AD20
PCI_SLOTD_REQ_L
PCI_SLOTD_GNT_L

PCI1AD_0_H L18
PCI1AD_1_H K19
PCI1AD_2_H L22
PCI1AD_3_H M22
PCI1AD_4_H M18
PCI1AD_5_H L20
PCI1AD_6_H M21
PCI1AD_7_H N16
PCI1AD_8_H M20
PCI1AD_9_H P22

AB18

PCI1REQ_0_L

AA18

PCI1GNT_0_L

AB20
AB19

PCI1REQ_1_L
PCI1GNT_1_L

V17

PCI1REQ_2_L

V18

PCI1GNT_2_L

PCI1AD_10_H M17
PCI1AD_11_H N18
PCI1AD_12_H M19
PCI1AD_13_H N19
PCI1AD_14_H P21
PCI1AD_15_H R22
PCI1AD_16_H P20
PCI1AD_17_H V21
PCI1AD_18_H P18
PCI1AD_19_H T20
PCI1AD_20_H R16
PCI1AD_21_H R17
PCI1AD_22_H W21
PCI1AD_23_H Y22
PCI1AD_24_H R18
PCI1AD_25_H T19
PCI1AD_26_H T18
PCI1AD_27_H Y21
PCI1AD_28_H W20

PCI1AD_29_H T16
PCI1AD_30_H AA21
PCI1AD_31_H T17
PCI1C_BE_0_L

L19

PCI1C_BE_1_L

P16
V22

PCI1C_BE_2_L
PCI1C_BE_3_L

AB8
AA9

ROM_CS_L
ROM_OE_L
ROM_WE_L

Y10

ROMCS_L
ROMOE_L
ROMRW_L

V20

PCI1DEVSEL_L

T22

PCI1FRAME_L
PCI1IRDY_L

T21
R21

PCI1TRDY_L

P19

PCI1STOP_L
PCI1PAR_H

P17
N17

PCI1RST_L

U18

C7422

0.1uF

PCI_SB_AD<0>
PCI_SB_AD<1>
PCI_SB_AD<2>
PCI_SB_AD<3>
PCI_SB_AD<4>
PCI_SB_AD<5>
PCI_SB_AD<6>
PCI_SB_AD<7>
PCI_SB_AD<8>
PCI_SB_AD<9>
PCI_SB_AD<10>
PCI_SB_AD<11>
PCI_SB_AD<12>
PCI_SB_AD<13>
PCI_SB_AD<14>
PCI_SB_AD<15>
PCI_SB_AD<16>
PCI_SB_AD<17>
PCI_SB_AD<18>
PCI_SB_AD<19>
PCI_SB_AD<20>
PCI_SB_AD<21>
PCI_SB_AD<22>
PCI_SB_AD<23>
PCI_SB_AD<24>
PCI_SB_AD<25>
PCI_SB_AD<26>
PCI_SB_AD<27>
PCI_SB_AD<28>
PCI_SB_AD<29>
PCI_SB_AD<30>
PCI_SB_AD<31>

PCI_SB_CBE_L<0>
PCI_SB_CBE_L<1>
PCI_SB_CBE_L<2>
PCI_SB_CBE_L<3>
PCI_SB_DEVSEL_L
PCI_SB_FRAME_L
PCI_SB_IRDY_L
PCI_SB_TRDY_L
PCI_SB_STOP_L
PCI_SB_PAR

0.1uF

20%
10V
CERM 2
402

20%
10V
CERM 2
402

C7423

0.1uF

20%
10V
CERM 2
402

7 23 25 88

73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73

77 76 75 74 25 7

=PP3V3_PCI

73

RP7402

73
73
77 76 74 73 6

PCI_DEVSEL_L

4.7K

73

5%
1/16W
SM-LF

RP7402

73
73
77 76 74 73 6

PCI_FRAME_L

4.7K

73

5%
1/16W
SM-LF

73
73
77 76 74 73 6

RP7402
2

PCI_IRDY_L

4.7K

73

5%
1/16W
SM-LF

RP7402

73
73
77 76 74 73 6

PCI_TRDY_L

4.7K

73

5%
1/16W
SM-LF

73

77 76 74 73 6

73

RP7401
7

PCI_STOP_L

4.7K

73
73

5%
1/16W
SM-LF

73

=PP3V3_PWRON_SB

7 23 25

73

Master: Link

73
73
73
73
73

R7455
4.7K

C7450 1R7450
0.1uF

20%
10V
2 CERM
402

5%
1/16W
MF-LF
2 402

4.7K

Shasta PCI Interface

5%
1/16W
MF-LF
2 402

5
1

SB_PCI_RESET_L

77 25 8

NOTICE OF PROPRIETARY PROPERTY

U7450 4
2

SYS_WARM_RESET_L

Shasta drives PCI RESET, but its output


may not be valid during power-up, so
it is ANDed with a reset from the SMU.

PCI_RESET_L 6

8 56

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

3MC74VHC1G08
SOT23-5

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6772
OF

74
1

04

102

Page Notes
Power aliases required by this page:
- _PP3V3_PCI
Signal aliases required by this page:
(NONE)
BOM options provided by this page:
(NONE)

NOTE: This page does not specify a BootROM


part number. Must use a TABLE_x_ITEM
symbol to declare U7500 part number.

77 76 75 74 25 7

y
r

a
n
i

=PP3V3_PCI

C7500

C7501

2.2uF

0.1uF

20%
10V
CERM 2
402

20%
10V
CERM 2
805

C7502

0.1uF

20%
10V
CERM 2
402

11

30

VPP

31

VCC

U7500

77 76 74 73 6
77 76 74 73 6
77 76 74 73 6
77 76 74 73 6
77 76 74 73 6
77 76 74 73 6

77 76 74 73 6
77 76 74 73 6
77 76 74 73 6
77 76 74 73 6
77 76 74 73 6
77 76 74 73 6
77 76 74 73 6
77 76 74 73 6

=PP3V3_PCI

77 76 74 73 6
77 76 74 73 6

R75001

77 76 74 73 6

R7501

10K

10K

77 76 74 73 6

e
r
5%
1/16W
MF-LF
402 2

76 74 6

ROM_CS_L

R7502
1

1K

5%
Allows ROM override module
1/16W
to intercept ROM chip select MF-LF

402

5%
1/16W
MF-LF
2 402

21

ROM_ONBOARD_CS_L
ROM_OE_L
ROM_WE_L
ROM_WP_L
=PCI_ROM_RESET_L

22

20
19
18
17
16

25
26
27
28
32
33

m
il
77 76 74 73 6

77 76 75 74 25 7

PCI_AD<0>
PCI_AD<1>
PCI_AD<2>
PCI_AD<3>
PCI_AD<4>
PCI_AD<5>
PCI_AD<6>
PCI_AD<7>
PCI_AD<8>
PCI_AD<9>
PCI_AD<10>
PCI_AD<11>
PCI_AD<12>
PCI_AD<13>
PCI_AD<14>
PCI_AD<15>
PCI_AD<16>
PCI_AD<17>
PCI_AD<18>
PCI_AD<19>
PCI_AD<20>

FEPR-1MX8
90.0ns
TSOP
A0
DQ0
A1 OMIT DQ1
A2
DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20

77 76 74 73 6
77 76 74 73 6

76 6

76 74 6
76 74 6
6
8

15
14
8
7

36
6
5
4
3
2
1

40
13
37
38

24

12

10

34
35

PCI_AD<24> 6
PCI_AD<25> 6
PCI_AD<26> 6
PCI_AD<27> 6
PCI_AD<28> 6
PCI_AD<29> 6
PCI_AD<30> 6
PCI_AD<31> 6

73 74 76 77
73 74 76 77
73 74 76 77
73 74 76 77
73 74 76 77
73 74 76 77
73 74 76 77
73 74 76 77

CE
OE
WE
WP
PWD

GND
23

39

Master: Link

BootROM

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-6772

04

OF

75

102

8
ELECTRICAL_CONSTRAINT_SET
PCI_CLK_AIRPORT

7
NET_SPACING_TYPE

DIFFERENTIAL_PAIR
_PCI_CLK33M_AIRPORT

CLOCKS

8 76

Page Notes
Power aliases required by this page:
- _PP3V3_PCI
Signal aliases required by this page:
- _PCI_CLK33M_AIRPORT (33MHz PCI clock)

BOM options provided by this page:


(NONE)

y
r

PCI Devices implemented on this page:


AD17 (Slot "A") - AirPort (0x????/0x????)

Q85 WIRELESS CONNECTOR

NOTE: This AirPort implementation does


not support PME#.

=PP3V3_PCI

77 75 74 25 7

SDF7600

NOSTUFF

STDOFF-3MMOD5MMH-TH

C7650 1 C7651
10UF
20%

1UF

2 6.3V
CERM
1206

20-5602-080-041-829
F-ST-SM

77 75 74 73 6

77 75 74 73 6
74 6
77 75 74 73 6
77 75 74 73 6

77 74 73 6
77 75 74 73 6

R7651
77 76 75 74 73 6

PCI_AD<17>

22

77 74 73 6

5%
1/16W
MF-LF
402

77 75 74 73 6
77 74 73 6
77 74 73 6
77 75 74 73 6
77 74 73 6

76 8
77 74 73 6
77 75 74 73 6
77 74 73 6

77 75 74 73 6
77 75 74 73 6
77 74 73 6

77 75 74 73 6

77 75 74 73 6

77 75 74 73 6
77 75 74 73 6

77 75 74 73 6

91
91

ALIAS
ALIAS

6
6

USB_BT_P
USB_BT_N

R7660
15K

5%
1/16W
MF-LF
402 2

PCI_AD<27>
PCI_SLOTA_REQ_L
PCI_AD<25>
PCI_AD<29>
PCI_CBE_L<3>
PCI_AD<26>
PCI_AD<22>
PCI_SLOTA_IDSEL
PCI_AD<19>
PCI_AD<21>
PCI_IRDY_L
PCI_AD<18>
PCI_DEVSEL_L

MAKE_BASE=TRUE
MAKE_BASE=TRUE

R7661
15K

5%
1/16W
MF-LF
2 402

91

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

PCI_AD<31>
AIRPORT_CLKRUN_L_PD
TP_AP_PME_L
PCI_SLOTA_GNT_L

PCI_AD<24>
PCI_AIRPORT_RESET_L
PCI_AD<28>
PCI_AD<23>
PCI_AD<20>
PCI_FRAME_L
PCI_AD<17>

m
il

_PCI_CLK33M_AIRPORT
PCI_STOP_L
PCI_AD<12>
PCI_PAR
PCI_AD<8>
PCI_AD<9>
PCI_CBE_L<0>
PCI_AD<7>
PCI_AD<3>
PCI_AD<6>

e
r
77 75 74 73 6

USB2_P<4>
USB2_N<4>

PCI_AD<30>

PCI_AD<1>
PCI_AD<5>
PCI_AD<0>

_PP3V3_PWRON_BT
USB2_OC<4>
ALIAS

C7660 1

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

PCI_TRDY_L

PCI_CBE_L<2>
PCI_AD<16>

PCI_AD<14>
PCI_AD<13>

C7652
1UF

10%
2 6.3V
CERM
402

a
n
i

CRITICAL

J7650
1

10%
2 6.3V
CERM
402

PCI_AD<10>
PCI_AD<15>
AP_ALT_ANT
PCI_CBE_L<1>
PCI_AD<4>
PCI_AD<11>
ROM_WE_L
PCI_AD<2>

PCI_SLOTA_INT_L
ROM_OE_L
ROM_ONBOARD_CS_L
ROM_CS_L

6 73 74 75 77

6 74

6 73 74 75 77

R7650

10K
5%
1/16W
MF-LF
2 402

6 73 74 75 77

6 73 74 77

6 73 74 75 77
6 73 74 77

6 73 74 75 76 77

6 73 74 77

6 73 74 77

6 73 74 75 77

6 73 74 75 77
6 73 74 75 77

6 73 74 75 77
6 73 74 75 77

6 73 74 77
6 73 74 75 77

6 73 74 75 77
6 74 75

6 73 74 75 77

6 25
6 74 75
6 75
6 74 75

516S0285

1UF

10%
6.3V
CERM 2
402

SDF7601
STDOFF-3MMOD5MMH-TH
1

AIRPORT & BLUETOOTH

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-6772

04

OF

76

102

8
ELECTRICAL_CONSTRAINT_SET
PCI_CLK_USB2

7
NET_SPACING_TYPE

DIFFERENTIAL_PAIR
=PCI_CLK33M_USB2

CLOCKS

8 77

Page Notes
Power aliases required by this page:
- _PPVIO_PCI (to 3.3V or 5V)
Signal aliases required by this page:
- _PCI_CLK33M_USB2 (33MHz PCI clock)

BOM options provided by this page:


(NONE)
7

=PPVIO_PCI_USB2

y
r

PCI Devices implemented on this page:


AD27 (Slot "G") - USB2 (0x1033/0x0035)

C7703 1

NOTE: This USB2 implementation supports


D3cold.

0.1uF

76 75 74 73 6
76 75 74 73 6
76 75 74 73 6
76 75 74 73 6
76 75 74 73 6
76 75 74 73 6
76 75 74 73 6
76 75 74 73 6
76 75 74 73 6
76 75 74 73 6
76 75 74 73 6
76 75 74 73 6
76 75 74 73 6
76 75 74 73 6
76 75 74 73 6
76 75 74 73 6

76 75 74 73 6
76 75 74 73 6
76 75 74 73 6
76 75 74 73 6
76 75 74 73 6
76 74 73 6
76 74 73 6
76 74 73 6
76 75 74 73 6
76 75 74 73 6
76 75 74 73 6
76 75 74 73 6

PCI_AD<27>
76 75 74 73
76 75 74 73
76 75 74 73
76 75 74 73

22

5%
1/16W
MF-LF
402 2

76 74 73 6
76 74 73 6
76 74 73 6

76 74 73 6

=PP3V3_PCI

76 74 73 6
76 74 73 6

R77161 R77131
10K

25

PCI_SLOTG_INT_L

47

RP7703
2

RP7702
3

SYS_WARM_RESET_L

SYS_PME_L

47

5%
1/16W
SM-LF
8

=PCI_USB2_RESET_L

47

5%
1/16W
SM-LF

RP7702
25 13

47

5%
1/16W
SM-LF
74 25 8

47

5%
1/16W
SM-LF

RP7703
3

5%
1/16W
MF-LF
402 2

5%
1/16W
SM-LF

RP7702
2

47

5%
1/16W
SM-LF

RP7702 & RP7703 required to


facilitate NAND-tree testing

76 74 73 6

10K

5%
1/16W
MF-LF
402 2

RP7703

N5
P4
N4
M3
N3
M1
L2
L1
K2
L3
K1
K3
J2
J1
F2
E3
E1
D3
D1
D2
C2
C1

76 74 73 6
74
74

77 8

B4

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

M4

C8

a
n
i

CRITICAL

U7700
NEC_UPD720101_USB2
FBGA

m
il
A4
B5
C4
A5
C5
B6
A6

M2

PCI_CBE_L<0>
PCI_CBE_L<1>
PCI_CBE_L<2>
PCI_CBE_L<3>

e
r
76 74 73 6

76 75 74 25 7

P5

(PCI_AD<27>)
6 PCI_AD<28>
6 PCI_AD<29>
6 PCI_AD<30>
6 PCI_AD<31>

76 74 73 6

R77141

M5

PCI_AD<0>
PCI_AD<1>
PCI_AD<2>
PCI_AD<3>
PCI_AD<4>
PCI_AD<5>
PCI_AD<6>
PCI_AD<7>
PCI_AD<8>
PCI_AD<9>
PCI_AD<10>
PCI_AD<11>
PCI_AD<12>
PCI_AD<13>
PCI_AD<14>
PCI_AD<15>
PCI_AD<16>
PCI_AD<17>
PCI_AD<18>
PCI_AD<19>
PCI_AD<20>
PCI_AD<21>
PCI_AD<22>
PCI_AD<23>
PCI_AD<24>
PCI_AD<25>
PCI_AD<26>

VDD_PCI

H3

20%
10V
CERM 2
402

J3
F1
C3

PCI_PAR
PCI_FRAME_L
PCI_IRDY_L
PCI_TRDY_L
PCI_STOP_L
PCI_SLOTG_IDSEL
PCI_DEVSEL_L
PCI_SLOTG_REQ_L
PCI_SLOTG_GNT_L
NEC_PERR_L_PU
NEC_SERR_L_PU
NEC_INTA_L
NEC_INTB_L
NEC_INTC_L
=PCI_CLK33M_USB2
NEC_VBBRST_L
NEC_CRUN_L_PD
NEC_PME_L
NEC_VCCRST_L
TP_NEC_SMI_L

CBE0
CBE1
CBE2
CBE3

J4

PAR
FRAME
IRDY
G1
TRDY
G3
STOP
B3 IDSEL
G2
DEVSEL
C6
REQ
D6
GNT
H2
PERR
H1
SERR OD
C7
INTA OD
B7
INTB OD
A7
INTC OD
A8
PCLK
F3
F4

B8
N6
D9
C9
L6

L7

NEC_LEGC_PD

VBBRST (CHIP RESET)


CRUN
PME OD
VCCRST (PCI RESET)
SMI OD

LEGC

IPD NTEST1 M8

B
TP_NEC_NTEST1

IPD

SMC M7

TP_NEC_SMC

IPD
IPD

TEB N7
AMC P7

TP_NEC_TEB
TP_NEC_AMC

IPD

TEST L8

NANDTEST
SRCLK
SRDTA
IPD SRMOD

M10
M9
N9
P9

TP_NEC_TEST

TP_NEC_NANDTEST
TP_NEC_SRCLK
TP_NEC_SRDATA
TP_NEC_SRMOD

6
6

6
6
6
6

R77151

RP7703

4.7K

5%
1/16W
MF-LF
402 2

47
5%
1/16W
SM-LF

USB 2.0 PCI Interface

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-6772

04

OF

77

102

8
ELECTRICAL_CONSTRAINT_SET

7
NET_SPACING_TYPE

DIFFERENTIAL_PAIR

SATA_RXD1
SATA_RXD1

NET_PHYSICAL_TYPE
SATA
SATA

SATA
SATA

SATA_RXD1_C
SATA_RXD1_C

SATA_RXD_P1_C
SATA_RXD_N1_C

SATA_TXD1
SATA_TXD1

SATA
SATA

SATA
SATA

SATA_TXD1
SATA_TXD1

SATA_TXD_P1
SATA_TXD_N1

SATA_RXD2
SATA_RXD2

SATA
SATA

SATA
SATA

SATA_RXD2_C
SATA_RXD2_C

SATA_RXD_P2_C
SATA_RXD_N2_C

SATA_TXD2
SATA_TXD2

SATA
SATA

SATA
SATA

SATA_TXD2
SATA_TXD2

SATA_TXD_P2
SATA_TXD_N2

80 83

80 83

RP8000

80 83

80 83

80

UATA_DD_R<0>

80 83

80 83
80

UATA_DD_R<1>

6 80 83
6 80 83

80

UATA_DD<0>

6 80 83

UATA_DD<1>

6 80 83

UATA_DD<2>

6 80 83

6 80 83
6 80 83

80

6 80 83
6 80 83
6 80 83

80

6 80 83
6 80 83

80

80 83
80 83
80 83

a
n
i

80

80

UATA_DD_R<3>

SATA_VDD x 5
C8000
0.1uF

20%
2 10V
CERM
402

Net Spacing Type: SATA

C8001
0.1uF

20%
2 10V
CERM
402

C8002
0.1uF

20%
2 10V
CERM
402

C8003

0.1uF

C8004
0.1uF

20%
2 10V
CERM
402

20%
2 10V
CERM
402

AB14

Line To Line:
15 mils
Length Tolerance:
50 mils
Primary Max Sep:
10 mils outer
Primary Max Sep:
9 mils inner
Secondary Max Sep: 100 mils
Secondary Length: 500 mils

W15
Y18

AB17
T14

=PP1V2_PWRON_DISK_SB

SATA_VDD

U2300

OMIT

SHASTA
V1.0

NOTE: Target differential impedance for


SATA data pairs is 100 ohms.

BGA
(5 OF 8)

m
il
UD_IDEDD_0_H J6
UD_IDEDD_1_H H7
UD_IDEDD_2_H H6
UD_IDEDD_3_H E2
UD_IDEDD_4_H C1

UATA

UD_IDEDD_5_H C2
UD_IDEDD_6_H E3
UD_IDEDD_7_H G6

UD_IDEDD_8_H G5
UD_IDEDD_9_H D4
UD_IDEDD_10_H G7
UD_IDEDD_11_H F6
UD_IDEDD_12_H C3

e
r

UD_IDEDA0_H E6
UD_IDEDA1_H C4

STOP aka:
DIOW*

UD_IDEDA2_H D6

UATA_DSTROBE

F9 UD_IDECHRDY_H

UD_IDECS1FX_L
UD_IDECS3FX_L

B3
B4

83 80

UATA_DMARQ

D7 UD_IDEDMARQ_H

UD_IDEDMACK_L

E8

UATA_INTRQ

C5 UD_IDEINTRQ_H

UD_IDERD_L

83 80

E4
D3

UATA_DD<3>

6 80 83

UATA_DD<4>

6 80 83

UATA_DD<5>

6 80 83

UATA_DD<6>

6 80 83

UATA_DD<7>

6 80 83

83 80

83 80
83 80

SATA_RXD_P1_C
SATA_RXD_N1_C

Y17 RXDP1
Y16 RXDN1

SATA_RXD_P2_C
SATA_RXD_N2_C

AB15 RXDP2
AA15 RXDN2

AC coupling required for any SATA pair used.


Recommend 0.1uF cap placed close to Shasta.
(Caps provided by device page)

SATA 0
SATA 1

E7

UATA_DA_R<0>
UATA_DA_R<1>
UATA_DA_R<2>
UATA_CS0_L_R
UATA_CS1_L_R
UATA_DMACK_L_R
UATA_HSTROBE_R
UATA_STOP_R
UATA_RESET_L_R

TXDP1 AA16 SATA_TXD_P1


TXDN1 AB16 SATA_TXD_N1
TXDP2 Y15
TXDN2 Y14

SATA_TXD_P2
SATA_TXD_N2

80

UATA_DD<8>

6 80 83

80

UATA_DD_R<7>

UATA_DD<9>

6 80 83

UATA_DD<10>

6 80 83

UATA_DD<11>

6 80 83

UATA_DD<12>

6 80 83

UATA_DD<13>

6 80 83

UATA_DD<14>

6 80 83

UATA_DD_R<9>

UATA_DD<15>

6 80 83

UATA_DA<0>

6 80 83

33

80

UATA_DD_R<11>

UATA_DA<1>

6 80 83

UATA_DA<2>

6 80 83

UATA_RESET_L

6 80 83

UATA_CS0_L

6 80 83

UATA_CS1_L

6 80 83

UATA_HSTROBE

6 80 83

UATA_STOP

6 80 83

UATA_DMACK_L

6 80 83

RP8000

80

UATA_DD_R<12>

33

RP8004
1

UATA_DD_R<14>

UATA_DD_R<15>

33

80

RP8004
2

80

UATA_DA_R<1>

33

80
80

80

RP8004
4

UATA_DA_R<2>

80

80

UATA_RESET_L_R

33

33

5%
1/16W
SM-LF

RP8004

80

5%
1/16W
SM-LF

80

33

5%
1/16W
SM-LF

RP8001

80

5%
1/16W
SM-LF

UATA_DA_R<0>

80

33

5%
1/16W
SM-LF

80

5%
1/16W
SM-LF

RP8003
80

33

5%
1/16W
SM-LF
80

RP8001

RP8002
UATA_DD_R<13>

5%
1/16W
SM-LF

80

33

5%
1/16W
SM-LF

RP8002
33

5%
1/16W
SM-LF

33

5%
1/16W
SM-LF

80

80

RP8002

RP8003
2

5%
1/16W
SM-LF

UATA_DD_R<10>

80

80

33

33

5%
1/16W
SM-LF

RP8002

UATA_DD_R<8>

80

80

RP8003
3

5%
1/16W
SM-LF

80
80

33

33

5%
1/16W
SM-LF

RP8001

UATA_DD_R<6>

5%
1/16W
MF-LF
402 2

80

RP8001

UATA_DD_R<4>

UATA_DD_R<5>

5%
1/16W
SM-LF

80

80

5%
1/16W
SM-LF

80

80

80

R8000
1

UATA_CS0_L_R

80

80
80

UATA_CS1_L_R

80

80

80 83
80

R8003

5%
1/16W
MF-LF
402

UATA_STOP_R

80 83

80

22

5%
1/16W
MF-LF
402

80 83

SATA_GND

R8002

UATA_HSTROBE_R

80 83

5%
1/16W
MF-LF
402

80
80

33

33

5%
1/16W
MF-LF
402

R8001

W16

83 80

UD_IDEWR_L
UD_IDERST_L

AA17
T13

83 80

HSTROBE aka:
DIOR*

AA14

UD_IDEDD_13_H F5
UD_IDEDD_14_H E5
UD_IDEDD_15_H D5

DSTROBE aka:
IORDY/HDMARDY*

UATA_DD_R<0>
UATA_DD_R<1>
UATA_DD_R<2>
UATA_DD_R<3>
UATA_DD_R<4>
UATA_DD_R<5>
UATA_DD_R<6>
UATA_DD_R<7>
UATA_DD_R<8>
UATA_DD_R<9>
UATA_DD_R<10>
UATA_DD_R<11>
UATA_DD_R<12>
UATA_DD_R<13>
UATA_DD_R<14>
UATA_DD_R<15>

10K

33

33

5%
1/16W
SM-LF

RP8003
4

RP8000

UATA_DD_R<2>

y
r

6 80 83

BOM options provided by this page:


(NONE)

5%
1/16W
SM-LF

R80051

80 83

Page Notes
Signal aliases required by this page:
(NONE)

33

33

5%
1/16W
SM-LF

RP8000

Power aliases required by this page:


- _PP1V2_PWRON_DISK

UATA Termination

80 83

UATA_DD<15..8>
UATA_DD<7>
UATA_DD<6..0>
UATA_DA<2..0>
UATA_CS0_L
UATA_CS1_L
UATA_HSTROBE
UATA_STOP
UATA_DMACK_L
UATA_RESET_L
UATA_DSTROBE
UATA_DMARQ
UATA_INTRQ

UATA_DD
UATA_DD7
UATA_DD
UATA_HOST
UATA_HOST
UATA_HOST
UATA_HOST
UATA_HOST
UATA_HOST_R
UATA_HOST_R
UATA_DEV_R_C
UATA_DEV_R
UATA_DEV_R

UATA_DMACK_L_R

22

R8004
1

22

5%
1/16W
MF-LF
402

Shasta Disk

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-6772

SCALE

OF

80
1

04

102

ELECTRICAL_CONSTRAINT_SET
83 80 6
83 80 6
83 80 6
83 80 6
83 80 6
83 80 6
83 80 6
83 80 6
83 80 6
83 80 6

83 80
83 80
83 80

UATA_DD<15..8>
UATA_DD<7>
UATA_DD<6..0>
UATA_DA<2..0>
UATA_CS0_L
UATA_CS1_L
UATA_HSTROBE
UATA_STOP
UATA_DMACK_L
UATA_RESET_L
UATA_DSTROBE
UATA_DMARQ
UATA_INTRQ

C8304

J8300
LD18077-S04
M-ST-TH

0.1UF
1
2

SATA_TXD_P1

80

20%
10V
CERM
402

SATA_TXD_N1_C

SATA_TXD_N1

80

0.1UF
1
2

0.1UF
1
2

C8308

5
6

0.1UF
1
2

SATA_RXD_P1

20%
10V
CERM
402

a
n
i
R83111

R8313

SATA_RXD_N1_C

10K

10K

80

5%
1/16W

5%
1/16W
MF-LF
402 2

SATA_RXD_P1_C

CRITICAL
MF-LF

J8301

F-ST-SM
51

R8314

20%
10V
CERM
402

518-0157

4.7K

5%
1/16W
MF-LF
2 402

NC

Per ATA Spec

83 80 6
83 80 6
83 80 6
83 80 6

Sourced by drive
Terminate near connector
SATA_TXD_P2

83 80 6

83 80 6
83 80 6

TP_SATA_TXD_P2
80

80

m
il

MAKE_BASE=TRUE

83 80 6

83 80 6

SATA_TXD_N2

TP_SATA_TXD_N2
80

80

MAKE_BASE=TRUE

83 80 6

80

SATA_RXD_N2_C

80

R8315

TP_SATA_RXD_N2_C
MAKE_BASE=TRUE

83 80

80

SATA_RXD_P2_C

80

UATA_DSTROBE

82

TP_SATA_RXD_P2_C

UATA_INTRQ

NO STUFF

83 80 6

=PP5V_DISK
CRITICAL

J8303
S05B-XA

6 7

=PP12V_DISK

6 7

M-RT-TH
1

=PP3V3_DISK

2
3
4
5

518-0144

82

10pF

UATA_RESET_L
UATA_DD<7>
UATA_DD<6>
UATA_DD<5>
UATA_DD<4>
UATA_DD<3>
UATA_DD<2>
UATA_DD<1>
UATA_DD<0>

UATA_STOP
UATA_DSTROBE_R
UATA_INTRQ_R
UATA_DA<1>
UATA_DA<0>
UATA_CS0_L
UATA_DASP_L

5%
1/16W
MF-LF
402

C8301 1

e
r

HD POWER

83 80 6

R8316

83 80

83 80 6

5%
1/16W
MF-LF
402

MAKE_BASE=TRUE

402 2

804RVS-050505R

80

5%
50V
CERM 2
402

DIFFERENTIAL_PAIR

ATA-6 spec does not call out R8180 or R8182

NO STUFF

=PP3V3_PATA

NO STUFF

C8307

20%
10V
CERM
402

SATA_RXD_N1

=PP5V_PATA

1
2

83 7

NET_SPACING_TYPE

y
r

PATA CONNECTOR

C8305

NET_PHYSICAL_TYPE

UATA_DD
UATA_DD7
UATA_DD
UATA_HOST
UATA_HOST
UATA_HOST
UATA_HOST
UATA_HOST
UATA_HOST_R
UATA_HOST_R
UATA_DEV_R_C
UATA_DEV_R
UATA_DEV_R

SATA CONNECTORS

SATA_TXD_P1_C

UATA_CSEL_PD

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

NC 49

50

NC
NC

R8312
1K

5%
1/16W
MF-LF
2 402

Obsolete

UATA_DD<8>
UATA_DD<9>
UATA_DD<10>
UATA_DD<11>
UATA_DD<12>
UATA_DD<13>
UATA_DD<14>
UATA_DD<15>
UATA_HSTROBE
UATA_DMACK_L
UATA_IOCS16_PU

6 80 83
6 80 83
6 80 83
6 80 83
6 80 83
6 80 83
6 80 83
6 80 83

6 80 83

6 80 83
6

NC

UATA_DA<2>
UATA_CS1_L

6 80 83
6 80 83

NC

52

R8320

83 80

UATA_DMARQ

82

UATA_DMARQ_R

5%
1/16W
MF-LF
402

516S0235

ATA-6 spec does not call out C8177


83 7

R83191

=PP5V_PATA

R8318 1R8317

5.6K

DEVELOPMENT

R8321

5%
1/16W
MF-LF
402 2

5%
1/16W
MF-LF
2 402

499

1%
1/16W
MF-LF
402 2

6.2K

5%
1/16W
MF-LF
2 402
PER ATA7 SPEC

Per ATA Spec


Per ATA Spec

DEVELOPMENT

LED8301
UATA_DASP_L_DS

GREEN
2.0X1.25A

"UATA ACTIVE"

DISK CONNECTORS

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-6772

04

OF

83

102

8
ELECTRICAL_CONSTRAINT_SET

NET_PHYSICAL_TYPE

ENET_RX_CLK
ENET_RX_CLK
ENET_GBE_REF
ENET_TX_CLK

7
NET_SPACING_TYPE

ENET_RX
ENET_RX_CTL
ENET_RX_CTL

ENET_RXD<7..0>
ENET_RX_DV
ENET_RX_ER

ENET_TX
ENET_TX_CTL
ENET_TX_CTL

ENET_TXD<7..0>
ENET_TX_EN
ENET_TX_ER

ENET_RX_CTL
ENET_RX_CTL
ENET_MDC
ENET_MDIO

ENET_CRS
ENET_COL
ENET_MDC
ENET_MDIO

84 86
84 86
84 86
84 86
84

84 86
84 86
84 86

84 86

84 86
84 86

y
r

84 86
84 86
84 86
84 86

Page Notes
Power aliases required by this page:
(NONE)
Signal aliases required by this page:
(NONE)

a
n
i

BOM options provided by this page:


(NONE)

RP8400
2

U2300
SHASTA

m
il

J2 ETH_RXD_6_H
G1 ETH_RXD_7_H

ETH_TXD_6_H J4
ETH_TXD_7_H K6

ENET_TXD_R<0>
ENET_TXD_R<1>
ENET_TXD_R<2>
ENET_TXD_R<3>
ENET_TXD_R<4>
ENET_TXD_R<5>
ENET_TXD_R<6>
ENET_TXD_R<7>

86 84

ENET_RX_DV
ENET_RX_ER

K4 ETH_RX_DV_H
G2 ETH_RX_ER_H

ETH_TX_EN_H H3
ETH_TX_ER_H F1

ENET_TX_EN_R
ENET_TX_ER_R

86 84

ENET_CLK125M_GBE_REF

M5 ETH_REFCLK_H

86 84
86 84
86 84
86 84
86 84
86 84
86 84

86 84

J1 ETH_RXD_3_H
L4 ETH_RXD_4_H
K3 ETH_RXD_5_H

ETH_TXD_3_H J5
ETH_TXD_4_H G3
ETH_TXD_5_H F2

ETH_GTX_CLK_H K5

86 84

ENET_CRS

L6 ETH_CRS_H

ETH_MDC_H M4

86 84

ENET_COL

L5 ETH_COL_H

ETH_MDIO_H M6

e
r

ETH_TXD_0_H G4
ETH_TXD_1_H E1
ETH_TXD_2_H H4

K1 ETH_RXD_0_H
L3 ETH_RXD_1_H
K2 ETH_RXD_2_H

84

ENET_CLK125M_GTX_R
ENET_MDC

84 86

ENET_MDIO

84 86

5%
1/16W
SM-LF

ENET_TXD<3>

84 86

ENET_TXD<4>

84 86

ENET_TXD<5>

84 86

ENET_TXD<6>

84 86

ENET_TXD<7>

84 86

ENET_TX_EN

84 86

ENET_TX_ER

84 86

ENET_CLK125M_GTX

84 86

R8400
1

5%
1/16W
MF-LF
402

R8401
0

84 86

5%
1/16W
SM-LF

RP8401

5%
1/16W
MF-LF
402

ENET_TXD<2>

RP8401
1

5%
1/16W
SM-LF

84 86

5%
1/16W
SM-LF

RP8401

ENET_TXD<1>

RP8401
2

5%
1/16W
SM-LF

84 86

5%
1/16W
SM-LF

RP8400

ENET_RXD<0>
ENET_RXD<1>
ENET_RXD<2>
ENET_RXD<3>
ENET_RXD<4>
ENET_RXD<5>
ENET_RXD<6>
ENET_RXD<7>

86 84

ETHERNET

86 84

ENET_CLK25M_TX
ENET_CLK125M_RX

ENET_TXD<0>

RP8400
1

BGA
(6 OF 8)
H5 ETH_TX_CLK_H
J3 ETH_RX_CLK_H

5%
1/16W
SM-LF

V1.0
86 84

5%
1/16W
SM-LF

RP8400

OMIT

DIFFERENTIAL_PAIR
ENET_CLK25M_TX
ENET_CLK125M_RX
ENET_CLK125M_GBE_REF
ENET_CLK125M_GTX
ENET_CLK125M_GTX_R

P25MM
P25MM
P25MM
P25MM

R8402
1

5%
1/16W
MF-LF
402

Master: Link

Shasta Ethernet

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6772
OF

84
1

04

102

ENET_CLK125M_GBE_REF_R
ENET_CLK125M_RX_R
ENET_CLK25M_TX_R

L8600

86

89 12

86 87

FERR-EMI-600-OHM

=PP2V5_ENETFW

86 87

PP2V5_VESTA_BIASVDD1
VOLTAGE=2.5V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

SM

86 87

86 87

C8601
0.1uF

86 87

20%
10V
2 CERM
402

86 87
86 87

86 87

VESTA_CLK25M_XTALI
VESTA_CLK25M_XTALO
VESTA_CLK25M_XTALO_R

L8601

86

FERR-EMI-600-OHM

86

PP2V5_VESTA_XTALVDD1
VOLTAGE=2.5V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

Page Notes

C8602
10UF

10%
2 6.3V
X5R
805

C8603

C8604 1

0.001uF

N1
84

ENET_CLK125M_GTX

A4

OMIT

84
84
84
84
84
84

=PP3V3_ENET

R86501

84

5%
1/16W
MF-LF
402 2

84

1.5K

84

84

Vesta Config Straps:

SPD0
0
1
X
0
1
0
1

MANMS - Manual Master/Slave Configuration Select


Sets manual master/slave configuration enable bit
(Internal Pull-down)

HUB - Repeater Select


Sets Hub/DTE bit and master/slave configuration value bit
(Internal Pull-down)
ER - Edge Rate Select
1 - Rise time approx. 5 ns
0 - Rise time approx. 4 ns
(Internal Pull-down)
AN_EN - Auto-Negotiation Select
1 - Auto-negotiation enabled
0 - Auto-negotiation disabled
(Internal Pull-up)
TXC_RXC_DELAY
1 - If RGMII Mode enabled, RXC clock and
GTXCLK are delayed by 1.9 ns
0 - No clock delay
(Internal Pull-down)

Description
Force 10BASE-T
Force 100BASE-TX
Force 1000BASE-T (test use only)
Auto-negotiate advertise 10BASE-T
Auto-negotiate advertise 10/100BASE-TX
Auto-negotiate advertise 10/100/1000BASE-T
Auto-negotiate advertise 1000BASE-T

ENET_TX_EN
ENET_TX_ER

B4

C7
D6

TXC A6

86

ENET_CLK25M_TX_R

RXC C1

86

E6
C5
B5
A5

C4

RXD[0]
RXD[1]
RXD[2] E5
RXD[3] E4
RXD[4] E3
RXD[5] D5
RXD[6] D4
RXD[7] D3

TXD[0]
TXD[1]
TXD[2]
TXD[3]
TXD[4]
TXD[5]
TXD[6]
TXD[7]

RX_DV D2
RX_ER C2

TX_EN
TX_ER

G2

MDC
MDIO

VESTA_ENET_LOWPWR

H5

LOWPWR

TP_VESTA_PHYA<0>
TP_VESTA_PHYA<1>
TP_VESTA_PHYA<2>
TP_VESTA_PHYA<3>
TP_VESTA_PHYA<4>

L5

PHYA[0]
PHYA[1]
PHYA[2]
PHYA[3]
PHYA[4]

COL F3
CRS G3

m
il

e
r

ENET_TXD<0>
ENET_TXD<1>
ENET_TXD<2>
ENET_TXD<3>
ENET_TXD<4>
ENET_TXD<5>
ENET_TXD<6>
ENET_TXD<7>

G1

ENET_MDC
ENET_MDIO

12

F1000
0
0
1
0
0
1
1

ENET_CLK125M_GBE_REF_R

F4
F5

TP_VESTA_EN_10B
TP_VESTA_RGMIIEN
TP_VESTA_FDX
TP_VESTA_F1000
TP_VESTA_SPD0
TP_VESTA_MANMS
TP_VESTA_HUB
TP_VESTA_ER
TP_VESTA_TEST<0>
TP_VESTA_TEST<1>
TP_VESTA_TVCO

Put crystal circuit close to PHY


86 VESTA_CLK25M_XTALI
86 VESTA_CLK25M_XTALO_R
1

R8609
0

CRITICAL

Y8600

25.0000M
1

C8618 1 C8619
5%
50V
CERM 2
402

L2
L1

K3

B8
C8
K4

K5
D9
A9
H3

M4

M5
N3
N2
P2

EN_10B
RGMIIEN
FDX
F1000
SPD0
MANMS
HUB
ER
TEST[0]
TEST[1]
TVCO

RBC0 A3
RBC1 B3

ENET_RX_DV
ENET_RX_ER

84
84

84

84
84

R8601

R8602

5%
1/16W
MF-LF
402

ENET_CLK125M_GBE_REF

84

ENET_CLK25M_TX

84

ENET_CLK125M_RX

84

5%
1/16W
MF-LF
402

84
84
84

84
84

ENET_COL
ENET_CRS

84
84

TP_VESTA_RBC0
TP_VESTA_RBC1

ENET_MDI_P<0>
ENET_MDI_N<0>

TRD+[1] R7
TRD-[1] R6

ENET_MDI_P<1>
ENET_MDI_N<1>

TRD+[2] R8
TRD-[2] R9

ENET_MDI_P<2>
ENET_MDI_N<2>

TRD+[3] R11
TRD-[3] R10

ENET_MDI_P<3>
ENET_MDI_N<3>

D10

ENET_ENERGYDET

25

R8614

XTALI
XTALO

RDAC1 R1
PLLGND1

TP_VESTA_AN_EN
TP_VESTA_TXC_RXC_DELAY
TP_VESTA_LINK1_L
TP_VESTA_LINK2_L
TP_VESTA_FDXLED_L
TP_VESTA_XMTLED_L
TP_VESTA_ACTLED_L

87
87

1.24K

1%
1/16W
MF-LF
402 2

C8620
0.01UF

20%
16V
2 CERM
402

C8621
0.01UF

20%
16V
2 CERM
402

1%
1/16W
MF-LF
2 402

ENET_MDI2
1

C8622
0.01UF

20%
16V
2 CERM
402

ENET_MDI3
1

C8623
0.01UF

20%
16V
2 CERM
402

PLACE RESISTORS CLOSE TO PHY


VESTA_CLK25M_XTALO 86

33pF

5%
50V
CERM 2
402

CRYSTAL LOAD CAPACITANCE IS 20PF

Vesta Ethernet PHY

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

DRAWING NUMBER

SHT
NONE

REV.

051-6772

SCALE

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

APPLE COMPUTER INC.

86 87

49.9

1%
1/16W
MF-LF
2 402

ENET_MDI1
1

86 87

R8621

49.9

1%
1/16W
MF-LF
2 402

ENET_MDI0
1

86 87

R8619

49.9

1%
1/16W
MF-LF
2 402

86 87

R8617

49.9

86 87

1%
1/16W
MF-LF
402 2

R8615

86 87

49.9

1%
1/16W
MF-LF
402 2

86 87

R8620

49.9

1%
1/16W
MF-LF
402 2

86 87

R8618

49.9

1%
1/16W
MF-LF
402 2

VESTA_RDAC1_PD

R86131

R8616

49.9

SLAVE*/AN_EN C10
QUALITY*/TXC_RXC_DELAY A8
LINK1* A10
LINK2* B11
FDXLED* B10
XMTLED* B12
ACTLED* A11

5%
1/16W
MF-LF
2 402

ENET_RXD<0>
ENET_RXD<1>
ENET_RXD<2>
ENET_RXD<3>
ENET_RXD<4>
ENET_RXD<5>
ENET_RXD<6>
ENET_RXD<7>

TRD+[0] R4
TRD-[0] R5

INTR*/ENERGYDET

XTALGND BIASGND

7 89

5%
1/16W
MF-LF
402

ENET_CLK125M_RX_R

8X4.5MM-SM

33pF

L4
L3

P3

84

AN_EN
0
0
0
1
1
1
1

86

U8600
B6
C6

=PP1V2_ENETFW

R8600

FBGA-200
2 OF 3

84

ESR < 0.5 ohms

CLK125 D1

BCM5462

87 7

SPD0 - Speed Select


See table below
(Internal Pull-down)

20%
6.3V 2
CERM
1206-1

a
n
i

GTXCLK

VESTA ENET

NOTE: Target differential impedance for


ENET data pairs is 100 ohms.

F1000 - Speed Select


See table below
(Internal Pull-up)

10uF

20%
50V
CERM 2
402

Line To Line:
0.38 mms
Length Tolerance:
50 mils
Primary Max Sep:
5 mils
Secondary Max Sep: 100 mils
Secondary Length: 500 mils

FDX - Full-Duplex Select


Sets manual duplex mode bit
(Internal Pull-up)

C8605 1

0.001uF

20%
2 50V
CERM
402

Net Spacing Type: ENET

RGMIIEN - RGMII Enable


1 - RGMII/RTBI Mode
0 - GMII/TBI Mode
(Internal Pull-down)

XTALVDD1 BIASVDD1 PLLVDD1

BOM options provided by this page:


(NONE)

EN_10B - TBI Interface Select


1 - TBI/RTBI Mode
0 - GMII/RGMII Mode
(Internal Pull-down)

FERR-EMI-600-OHM
SM

Signal aliases required by this page:


(NONE)

PHYA<4..0> - PHY Address Select


(Internal Pull-downs)

L8602

PP1V2_VESTA_PLLVDD1
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

SM

Power aliases required by this page:


- _PP3V3_ENET
- _PP2V5_ENETFW
- _PP1V2_ENETFW

y
r

86

M1

P25MM
P25MM
P25MM

ENET_MDI_P<0>
ENET_MDI_N<0>
ENET_MDI_P<1>
ENET_MDI_N<1>
ENET_MDI_P<2>
ENET_MDI_N<2>
ENET_MDI_P<3>
ENET_MDI_N<3>

ENET_MDI0
ENET_MDI0
ENET_MDI1
ENET_MDI1
ENET_MDI2
ENET_MDI2
ENET_MDI3
ENET_MDI3

86

M2

VESTA_CLK25M_XTAL

ENET
ENET
ENET
ENET
ENET
ENET
ENET
ENET

86

P1

ENET
ENET
ENET
ENET
ENET
ENET
ENET
ENET

DIFFERENTIAL_PAIR

P25MM
P25MM
P25MM
ENET_MDI
ENET_MDI
ENET_MDI
ENET_MDI
ENET_MDI
ENET_MDI
ENET_MDI
ENET_MDI

R2

ELECTRICAL_CONSTRAINT_SET

7
NET_TYPE
SPACING PHYSICAL

04

86 102
OF

y
r

L8700

PUT DEVELOPMENT LEDS ON TOP SIDE OF BOARD

FERR-EMI-600-OHM
7

=PP2V5_ENET

2
SM

87 86 7

GBIT_2_5V

C8704

a
n
i

GND_CHASSIS_RJ45
1

0.001UF

C8700

20%
50V
CERM 2
603

0.1UF

20%
2 10V
CERM
402

(514-0222)
CRITICAL

J8700
86
86

MJRR0156

ENET_MDI_P<0>
ENET_MDI_N<0>

F-ST-TH
PRIMARY

1CT:1CT

13

C8701

11

75 OHM

0.1UF

20%
2 10V
CERM
402

ENET_CTAP

ENET_CTAP

MDI_0+
MDI_0-

2
86
86

MDI_1+
MDI_1-

MDI_2+

8
9

MDI_2MDI_3+

10

MDI_3-

ENET_MDI_P<1>
ENET_MDI_N<1>

1CT:1CT
75 OHM

m
il

C8702
0.1UF

12
14

ENET_MDI_P<2>
ENET_MDI_N<2>

e
r

C8703
0.1UF

20%
2 10V
CERM
402

B
86
86

ENET_MDI_P<3>
ENET_MDI_N<3>

C8705

0.001UF

20%
50V
2 CERM
603

75 OHM

75 OHM

RJ45
CHIP SIDE
86

1CT:1CT

1CT:1CT

20%
2 10V
CERM
402

86

SECONDARY
J1

SHIELD

86

TP_VESTA_XMTLED_L

=PP3V3_ENET

DEVELOPMENT
1

R8701
330

5%
1/10W
MF-LF
2 603

DEVELOPMENT

R8700

10K

5%
1/16W
MF-LF
2 402

LED8700_P

DEVELOPMENT

LED8700
GREEN
2.0X1.25A

VESTA_XMTLED

LED8700_N

6 DEVELOPMENT

Q8700
2N7002DW

VESTA_XMTLED_L
MAKE_BASE=TRUE

Q8700
2N7002DW

SOT-363

J2
J3

3 DEVELOPMENT

SOT-363

J4
J5
J6
J7
J8

RJ45
CABLE SIDE

87 86 7

=PP3V3_ENET
DEVELOPMENT
1

R8703
330

1000PF, 2000V

5%
1/10W
MF-LF
2 603

DEVELOPMENT

R8702

10K

LED8701_P

5%
1/16W
MF-LF
2 402

DEVELOPMENT

LED8701
GREEN
2.0X1.25A
2

VESTA_ACTLED

LED8701_N

6 DEVELOPMENT

Q8701
2N7002DW

86

TP_VESTA_ACTLED_L

VESTA_ACTLED_L
MAKE_BASE=TRUE

3 DEVELOPMENT

Q8701
2N7002DW

SOT-363

SOT-363

ETHERNET CONNECTOR

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-6772

04

OF

87

102

8
ELECTRICAL_CONSTRAINT_SET

NET_PHYSICAL_TYPE

FW
FW
FW_LPS
FW_LREQ
FW_PINT
FW_LCLK
FW_PCLK

7
NET_SPACING_TYPE

15 MIL SPACING
15 MIL SPACING
15 MIL SPACING

DIFFERENTIAL_PAIR
FW_DATA<7..0>
FW_CTL<1..0>
FW_LPS
FW_LREQ
FW_PINT
FW_CLK98M_LCLK
FW_CLK98M_PCLK
FW_CLK98M_LCLK_R

88 89
88 89
88 89
88 89
88 89
88 89
88 89
88

Page Notes

y
r

Power aliases required by this page:


- _PP2V5_PWRON_SB
Signal aliases required by this page:
(NONE)
BOM options provided by this page:
(NONE)

a
n
i

=PP2V5_PWRON_SB

C8800
0.1uF

20%
2 10V
CERM
402

C8801
0.1uF

20%
2 10V
CERM
402

C8802
0.1uF

20%
2 10V
CERM
402

N5
J7

A4

74 25 23 7

FWVDDP

U2300

OMIT

SHASTA
V1.0
BGA
(7 OF 8)
PHY_DATA_0_H N4
PHY_DATA_1_H P5

FW_DATA<0>
FW_DATA<1>
FW_DATA<2>
FW_DATA<3>
FW_DATA<4>
FW_DATA<5>
FW_DATA<6>
FW_DATA<7>

FIREWIRE

m
il
PHY_DATA_2_H N1
PHY_DATA_3_H M7
PHY_DATA_4_H N6
PHY_DATA_5_H L1
PHY_DATA_6_H M3
PHY_DATA_7_H L2
PHY_CTL_0_H N2
PHY_CTL_1_H N3

FW_CTL<0>
FW_CTL<1>

PHY_LPS_H P6
PHY_LREQ_H P1

89 88

FW_CLK98M_PCLK

e
r
89 88

FW_PINT

P2 PHY_SCLK_H

PHY_LCLK_H R1

P3 PHY_PINT_L

PHY_LINKON_L N7

FW_LPS
FW_LREQ

88

88 89
88 89
88 89
88 89
88 89
88 89
88 89
88 89

88 89
88 89

88 89
88 89

R8800
1

FW_CLK98M_LCLK_R
FW_LINKON

89

22

FW_CLK98M_LCLK

88 89

5%
1/16W
MF-LF
402

Master: Link

Shasta FireWire

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SCALE

SHT
NONE

REV.

051-6772
OF

88
1

04

102

8
ELECTRICAL_CONSTRAINT_SET

FW
FW
FW
FW

FW
FW
FW
FW

FW_TPA2
FW_TPA2
FW_TPB2
FW_TPB2

FW_TPA_P<2>
FW_TPA_N<2>
FW_TPB_P<2>
FW_TPB_N<2>

89 90

I416
I415
I417

P38MM
P38MM
P38MM

89 90

ESR < 0.5 ohms

89 90
89 90

C8901

C8906

L8901

89 90
89 90

20%
10V
2 CERM
402

C8904
10UF

22

90

8
90 89 7

Net Spacing Type: FW

5%
1/16W
SM-LF

RP8900
3

FW_DATA<1>

22

FW_DATA<3>

22

RP8901
1

FW_DATA<5>

FW_DATA<6>

22

5%
1/16W
SM-LF

88

FW_CTL<0>

FW_CTL<1>

22

22

5%
1/16W
SM-LF

R8900
88

e
r

RP8900

FW_DATA<7>

5%
1/16W
SM-LF
88

22

5%
1/16W
MF-LF
402

VESTA_PWR_CLASS_0

R8901
1

22

R89121
10K

5%
1/16W
MF-LF
402 2

5%
1/16W
MF-LF
402

VESTA_BILINGUAL_EN12_L
VESTA_PORT1_DISABLE_L
VESTA_PORT2_DISABLE_L

VESTA_PORT1_DISABLE
VESTA_BILINGUAL_EN12
VESTA_PORT2_DISABLE
1

Vesta Config Straps:

R13

CPS

VESTA_BILINGUAL_EN12_L
VESTA_PORT1_DISABLE_L
VESTA_PORT2_DISABLE_L

C11

ESDET0
ESDET1
ESDET2

C12
C13

FAVDDM

y
r

88

25

VESTA FW
U8600

PLI_PCLK E15

FBGA-200
3 OF 3

FW_CLK98M_LCLK

D15

FW_DATA_R<0>
FW_DATA_R<1>
FW_DATA_R<2>
FW_DATA_R<3>
FW_DATA_R<4>
FW_DATA_R<5>
FW_DATA_R<6>
FW_DATA_R<7>

E12
E11

G12
G11

PLI_DATA[0]
PLI_DATA[1]
PLI_DATA[2]
PLI_DATA[3]
PLI_DATA[4]
PLI_DATA[5]
PLI_DATA[6]
PLI_DATA[7]

FW_CTL_R<0>
FW_CTL_R<1>

E14
E13

PLI_CTL[0]
PLI_CTL[1]

FW_LPS
FW_LREQ

D11

PLI_LPS
PLI_LREQ

F11
F12
F13
G13

D12
J3

FW_LOWPWR
VESTA_DS_ONLY_EN0
VESTA_PWR_CLASS

A12

TP_VESTA_TEST_1394<0>
TP_VESTA_TEST_1394<1>
TP_VESTA_TVCO_24

J4
N13

A13

J5

Put crystal circuit close to PHY


89 VESTA_CLK24M_XTALI
89 VESTA_CLK24M_XTALO_R

P14
P13

PLI_LCLK

CRITICAL

Y8920

24.576M
1

R89031

5%
1/16W
MF-LF
2 402

1K

1%
1/16W
MF-LF
402 2

TPBIAS[0] L13
TPAP[0] L15
TPAN[0] L14
TPBP[0] M15
TPBN[0] M14
TPBIAS[1] J13
TPAP[1] J15
TPAN[1] J14
TPBP[1] K15
TPBN[1] K14
TPBIAS[2] H13
TPAP[2] G15
TPAN[2] G14
TPBP[2] H15
TPBN[2] H14

TEST_1394[0]
TEST_1394[1]
TVCO_24

SDC H1
SDA H2
RDAC2 R15

XTALI_24
XTALO_24

BIASGND

R8921

PLI_INT D13
PLI_LINK D14

LPWR_1394
DS_ONLY_EN0 Internal Pull-Down
PWR_CLASS
Internal Pull-Up

R8933

R8935

10K

10K

10K

5%
1/16W
MF-LF
402 2

5%
1/16W
MF-LF
402 2

L8909

R8904
10K

0.1uF

20%
2 10V
CERM
402

=PP2V5_ENETFW

12 86 89

=PP1V2_ENETFW

7 86 89

10UF

L8913

FERR-EMI-600-OHM

C8915

0.1uF

C8919
10UF

20%
2 10V
CERM
402

10%
2 6.3V
X5R
805

R8902

FW_CLK98M_PCLK_R

FW_PINT
88
FW_LINKON
88
FW_TPBIAS<0>
90
MIN_LINE_WIDTH=0.25
MIN_NECK_WIDTH=0.25
FW_TPA_P<0>
89 90
FW_TPA_N<0>
89 90
FW_TPB_P<0>
89 90
FW_TPB_N<0>
89 90
FW_TPBIAS<1>
90
MIN_LINE_WIDTH=0.25
MIN_NECK_WIDTH=0.25
FW_TPA_P<1>
89 90
FW_TPA_N<1>
89 90
FW_TPB_P<1>
89 90
FW_TPB_N<1>
89 90
FW_TPBIAS<2>
90
MIN_LINE_WIDTH=0.25
MIN_NECK_WIDTH=0.25
FW_TPA_P<2>
89 90
FW_TPA_N<2>
89 90
FW_TPB_P<2>
89 90
FW_TPB_N<2>
89 90

C8918

10%
6.3V
2 X5R
805

SM

TP_VESTA_TDBL<0>
TP_VESTA_TDBL<1>
TP_VESTA_TDBL<2>

89

20%
10V
2 CERM
402

C8914

FAVDDL

TDBL[0] A14
TDBL[1] B13
TDBL[2] B14

OMIT

22

FW_CLK98M_PCLK

88

5%
1/16W
MF-LF
402

mm
mm

mm
mm

mm
mm

I2C_VESTA_SCL
I2C_VESTA_SDA
VESTA_RDAC2_PD

R89091

PLLGND2

2.0K

1%
1/16W
MF-LF
402 2

1%
1/16W
MF-LF
2 402

8X4.5MM-SM

C8921 1

5%
50V
CERM 2
402

5%
50V
CERM 2
402

VESTA_CLK24M_XTALO

89

22pF

90 89 7

=PP3V3_FW

R89151

89

10K

89

5%
1/16W
MF-LF
402 2

CRYSTAL LOAD CAPACITANCE IS 12PF

R8931

5%
1/16W
MF-LF
402 2

PWR_CLASS - FireWire Power Class


1 - Sets Power Class to 0x4
0 - Sets Power Class to 0x0
(Internal Pull-up)

88

C8920 1
22pF

89

89

FW_CPS

m
il

5%
1/16W
SM-LF

RP8901
88

5%
1/16W
SM-LF

89

88

RP8901
22

89

FAVDDH

BCM5462

5%
1/16W
MF-LF
402 2

RP8901

88

R89111

10K

5%
1/16W
SM-LF

FW_DATA<4>

VESTA_DS_ONLY_EN0

5%
1/16W
SM-LF

RP8900

88

22

=PP3V3_FW
(Int PU)
(Int PU)
(Int PU)

20%
2 10V
CERM
402

N15

5%
1/16W
MF-LF
402 2

C8913
0.1uF

XTALVDD2

=PPFW_PHY

RP8900

20%
2 50V
CERM
402

390K

88

FERR-EMI-600-OHM

0.1uF

a
n
i

C8905

R89141

FW_DATA<2>

10UF

C8911

PP1V2_VESTA_FAVDDL
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

0.001uF

10%
2 6.3V
X5R
805

90

C8909

20%
10V
2 CERM
402

PP2V5_VESTA_XTALVDD2
VOLTAGE=2.5V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

88

C8917

10%
6.3V
2 X5R
805

20%
10V
2 CERM
402

0.1uF

SM

NOTE: Target differential impedance for


FW data pairs is 110 ohms.

0.1uF

PP2V5_VESTA_FAVDDM
VOLTAGE=2.5V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

C8903

L8902

88

SM

89

0.38 mms
100 mils
7.5 mils
100 mils
500 mils

C8908

0.1uF

SM

89

Signal aliases required by this page:


(NONE)

Line To Line:
Length Tolerance:
Primary Max Sep:
Secondary Max Sep:
Secondary Length:

C8907

20%
10V
2 CERM
402

PP2V5_VESTA_BIASVDD2
VOLTAGE=2.5V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

FERR-EMI-600-OHM

=PP2V5_ENETFW

89

FERR-EMI-600-OHM

FW_DATA<0>

0.1uF

20%
50V
2 CERM
402

89 90

Page Notes

0.001uF

20%
6.3V
2 CERM
1206-1

20%
10V
2 CERM
402

88

=PP3V3_ENETFW

2
SM

0.1uF

BOM options provided by this page:


- VESTA_DS_ONLY_EN0
If stuffed, adds external pull-up to
counter internal pull-down in Vesta.
See straps table for more information.
- VESTA_PWR_CLASS_0
If stuffed, adds external pull-down to
counter internal pull-up in Vesta.
See straps table for more information.

89 90

Power aliases required by this page:


- _PPFW_PHY
- _PP3V3_FW
- _PP3V3_ENETFW
- _PP2V5_ENETFW
- _PP1V2_ENETFW

C8900
10uF

89 90

VESTA_CLK24M_XTALI
VESTA_CLK24M_XTALO
VESTA_CLK24M_XTALO_R

CRYSTAL
CRYSTAL
CRYSTAL

L8906

FERR-EMI-600-OHM

SM

89 86 12

VESTA_CLK24M_XTAL

PP3V3_VESTA_FAVDDH
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

N11
N12

I413

FW_TPA3
FW_TPA3
FW_TPB3
FW_TPB3

M10

I414

FW_TPA_P<1>
FW_TPA_N<1>
FW_TPB_P<1>
FW_TPB_N<1>

L10

I411

FW_TPA1
FW_TPA1
FW_TPB1
FW_TPB1

PP1V2_VESTA_PLLVDD2
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

FERR-EMI-600-OHM

=PP1V2_ENETFW

M12

I412

FW
FW
FW
FW

89 86 7
89 90

N14

I409

FW
FW
FW
FW

89 90

L12
M11

I410

FW_TPA2
FW_TPA2
FW_TPB2
FW_TPB2

L8900

89 90

L11

I408

89

FW_TPA_P<0>
FW_TPA_N<0>
FW_TPB_P<0>
FW_TPB_N<0>

K13

I407

FW_CLK98M_PCLK_R
FW_TPA0
FW_TPA0
FW_TPB0
FW_TPB0

K11
K12

I406

FW
FW
FW
FW

P15

I404

FW
FW
FW
FW

DIFFERENTIAL_PAIR

CLOCKS

P12

I405

FW_TPA1
FW_TPA1
FW_TPB1
FW_TPB1

P38MM

R14

I403

(PROVIDED BY LINK PAGE)

BIASVDD2
PLLVDD2

I402

7
NET_TYPE
SPACING PHYSICAL

R8916
10K

5%
1/16W
MF-LF
2 402

Vesta FireWire PHY

(I2C_VESTA_SDA)
(I2C_VESTA_SCL)

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

DS_ONLY_EN0 - Port 0 Data/Strobe


1 - Port 0 Data/Strobe mode only
0 - Port 0 Bilingual mode
(Internal Pull-down)

II NOT TO REPRODUCE OR COPY IT


III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-6772

SCALE

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

04

89 102
OF

8
I401
I400
I402
I404
I403
I405
I407
I406

FW
FW
FW
FW

FW
FW
FW
FW

FW
FW
FW
FW

NET_TYPE
SPACING PHYSICAL

FW
FW
FW
FW

PP24V_RUN

DIFFERENTIAL_PAIR
FW_PORT0_TPA_P_FL
FW_PORT0_TPA_N_FL
FW_PORT0_TPB_P_FL
FW_PORT0_TPB_N_FL

FW_TPA0_FL
FW_TPA0_FL
FW_TPB0_FL
FW_TPB0_FL

FW_PORT1_TPA_P_FL
FW_PORT1_TPA_N_FL
FW_PORT1_TPB_P_FL
FW_PORT1_TPB_N_FL

FW_TPA1_FL
FW_TPA1_FL
FW_TPB1_FL
FW_TPB1_FL

CRITICAL

8 WATTS MAX
90
90

24 VOLTS

90

1.3

90

MIN_LINE_WIDTH=35MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=24V

MAKE_BASE=TRUE

90

=PPFW_PHY

89

C9009
0.1UF
20%
50V
CERM
805

89

90

PP24V_FW_D

MIN_LINE_WIDTH=35MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=24V

SMC

90

L9001

R9002

MURS320XXG

PP24V_FW

20%
1W
FF
2512

90

D9000

R9056

1.3

MIN_LINE_WIDTH=35MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=24V

20%
1W
FF
2512

F9002

FERR-160-OHM

PP24V_FW_R

F9000

0.5AMP
6

FW_VP

VOLTAGE=24V
MIN_LINE_WIDTH=35MIL
MIN_NECK_WIDTH=10MIL

1206

1.5AMP-33V

2
SM

PPFW_PORT0_VP
VOLTAGE=33V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

PPFW_PORT1_VP 90
VOLTAGE=33V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

SM

D
"Snapback" & "Late VG" Protection
90

DP9010

Termination
89
89

DP9010

BAV99DW-X-F

C9010

0.001uF

Place close to FireWire PHY

y
r

PP3V3_FW_ESD

SOT-363
2

20%
50V
CERM 2
402

FW_TPBIAS<1>
FW_TPBIAS<0>

BAV99DW-X-F

C9011

SOT-363
5

0.001uF

20%
50V
CERM 2
402

PORT 0
1394A

FL9010
165-OHM
SM

SYM_VER-1

C9050

1uF

90

FW_PORT0_TPA_P

90

FW_PORT0_TPA_N

a
n
i

C9060
1uF

10%
2 6.3V
CERM
402

10%
2 6.3V
CERM
402

FL9011
165-OHM
SM
SYM_VER-1

R90501
56.2

89
89
89
89

R9051 R90601
56.2

1%
1/16W
MF-LF
402 2

1%
1/16W
MF-LF
2 402

R9061

56.2
1%
1/16W
MF-LF
402 2

90

56.2
1%
1/16W
MF-LF
2 402

FW_TPA_P<0>
FW_TPA_N<0>
FW_TPB_P<0>
FW_TPB_N<0>

ALIAS
ALIAS
ALIAS
ALIAS

90

FW_PORT0_TPB_N

SOT-363
2

C9012

89
89
89

FW_TPA_P<1>
FW_TPA_N<1>
FW_TPB_P<1>
FW_TPB_N<1>

ALIAS
ALIAS
ALIAS
ALIAS

R9052
56.2

R9053 R9062
56.2

1%
1/16W
MF-LF
402 2

1%
1/16W
MF-LF
2 402

56.2

1%
1/16W
MF-LF
402 2

270pF

5%
25V
CERM 2
402

6
1

56.2

1%
1/16W
MF-LF
2 402

R9054
4.99K C9064 1
1%

1/16W
MF-LF
2 402

270pF

5%
25V
CERM 2
402

R9064
4.99K

90

1%
1/16W
MF-LF
2 402

FW_TPBIAS<2>

89

FW_TPA_P<2>

89

FW_TPA_N<2>

89

89

FW_TPB_P<2>
FW_TPB_N<2>

5%
1/8W
MF-LF
805

20%
50V
CERM 2
402

PP3V3_FW_ESD

0.001uF

e
r

3rd TPA/TPB pair unused


89

FWS22

F-ST-TH

90

FW_PORT0_TPA_P_FL

90

FW_PORT0_TPA_N_FL

90

FW_PORT0_TPB_P_FL

90

FW_PORT0_TPB_N_FL

TPO

(TPA+)

TPO#

(TPA-)

TPI

(TPB+)

TPI#

(TPB-)

(PPFW_PORT0_VP)

VP

GND_FW_PORT0_VG
VOLTAGE=0V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

C9015 C9016
0.01uF

20%
2 16V
CERM
402

VGND
8

10

0.01uF

20%
16V
CERM 2
402

514-0202
GND_CHASSIS_FIREWIRE

7 90

"Snapback" & "Late VG" Protection

C9020 1

R9010

C9013 1

0.001uF

m
il

R9063

FW_TPA_C<1>

FW_TPA_C<0>

C9054 1

BAV99DW-X-F
SOT-363
5

20%
50V
CERM 2
402

FW_PORT1_TPA_P 90
MAKE_BASE=TRUE
FW_PORT1_TPA_N 90
MAKE_BASE=TRUE
FW_PORT1_TPB_P 90
MAKE_BASE=TRUE
FW_PORT1_TPB_N 90
MAKE_BASE=TRUE

DP9011

BAV99DW-X-F

FW_PORT0_TPA_P 90
MAKE_BASE=TRUE
FW_PORT0_TPA_N 90
MAKE_BASE=TRUE
FW_PORT0_TPB_P 90
MAKE_BASE=TRUE
FW_PORT0_TPB_N 90
MAKE_BASE=TRUE

DP9011

0.001uF
89

FW_PORT0_TPB_P

CRITICAL

J9000

NC_FW_TPBIAS2
MAKE_BASE=TRUE
NO_TEST=YES
NC_FW_TPA_P2
MAKE_BASE=TRUE
NO_TEST=YES
NC_FW_TPA_N2
MAKE_BASE=TRUE
NO_TEST=YES

FW_TPB2_PD
MAKE_BASE=TRUE
NO_TEST=YES

P
R90701
1K

5%
1/16W
MF-LF
402 2

DP9020

DP9020

BAV99DW-X-F

BAV99DW-X-F

SOT-363
2

20%
50V
CERM 2
402

C9021

0.001uF
6

90

90

90

90

PORT 1
1394A

FL9020
165-OHM
SM

SYM_VER-1

FW_PORT1_TPA_P

FW_PORT1_TPA_N

F-ST-TH
165-OHM
SM
4

DP9021

BAV99DW-X-F

BAV99DW-X-F

SOT-363
2

FW_PORT1_TPA_P_FL

90

FW_PORT1_TPA_N_FL

90

FW_PORT1_TPB_P_FL

C9023
0.001uF

90

FW_PORT1_TPB_N_FL

(PPFW_PORT1_VP)

R9020

SOT-363
5
6

20%
50V
CERM 2
402

90

TPO

(TPA+)

TPO#

(TPA-)

TPI

(TPB+)

TPI#

(TPB-)

SYM_VER-1

DP9021

FWS22

FL9021

FW_PORT1_TPB_N

C9022 1

CRITICAL

J9001

FW_PORT1_TPB_P

0.001uF

90

SOT-363
5

20%
50V
CERM 2
402

PPFW_PORT1_VP

1
3

5%
1/8W
MF-LF
805

1
4

20%
50V
CERM 2
402

VP

GND_FW_PORT1_VG
VOLTAGE=0V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

C9025 C9026
0.01uF

20%
16V
2 CERM
402

VGND
7

10

0.01uF

20%
16V
CERM 2
402

514-0202
GND_CHASSIS_FIREWIRE

7 90

ESD Rail

89 7

=PP3V3_FW

L9090

R9090
1

665

1%
1/16W
MF-LF
402

1
PP3V3_FW_ESD_F
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm

FIREWIRE CONNECTORS

PP3V3_FW_ESD
90
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm

400-OHM-EMI
2

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

SM-1
3

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

D9090
SOT23

II NOT TO REPRODUCE OR COPY IT


III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

BZX84C2V7-X-F

SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-6772

04

OF

90

102

USB2_1
USB2_1

USB2_P<1>
USB2_N<1>

USB2_2
USB2_2

USB2
USB2

USB2
USB2

USB2_2
USB2_2

USB2_P<2>
USB2_N<2>

USB2_3
USB2_3

USB2
USB2

USB2
USB2

USB2_3
USB2_3

USB2_P<3>
USB2_N<3>

USB2_4
USB2_4

USB2
USB2

USB2
USB2

USB2_4
USB2_4

USB2_P<4>
USB2_N<4>

91 92
91 92

91 92
91 92

6 91 92
6 91 92

76 91
76 91

NEC_CLK30M_XT1
NEC_CLK30M_XT2
NEC_CLK30M_XT2_R

15 MIL SPACING
15 MIL SPACING
15 MIL SPACING

USB2_NEC_XTAL

91 92

L9135

91
91
91 7

=PP3V3_PWRON_USB

91

2
SM

Page Notes
Power aliases required by this page:
- _PP3V3_PWRON_USB

C9136

10uF

0.1uF

Net Spacing Type: USB2


mils
mils
mils
mils
mils

C9126

C9127 1

C9128 1

0.1uF

0.1uF

0.1uF

20%
10V
CERM 2
402

20%
10V
CERM 2
402

0.1uF

0.1uF

20%
10V
CERM 2
402

R9100

20%
10V
CERM 2
402

CRITICAL

U7700

NOTE: Target differential impedance for


USB2 data pairs is 90 ohms.

36

RSDM1 M14
DM1 M13
DP1 L14
RSDP1 K13

0.1uF

20%
10V
CERM 2
402

91

a
n
i

VDD

20%
10V
CERM 2
402

C9129 1 C9130

20%
10V
CERM 2
402

0.1uF

20%
10V
CERM 2
402

N8

C9124 1 C9125

E2

20%
10V
CERM 2
402

0.1uF

A3

C9123 1

20%
10V
CERM 2
402

0.1uF

A12

C9122 1

20%
10V
CERM 2
402

A13

0.1uF

0.1uF

GND_NEC_AVSS_R

P12

C9121

C9137

20%
10V
CERM 2
402

20%
6.3V
CERM
805

AVDD

20%
6.3V 2
CERM
805

P3

10uF

P2

NOSTUFF

C9120

BOM options provided by this page:


(NONE)

4.7

C9135

5%
1/10W
MF-LF
603

Signal aliases required by this page:


(NONE)

Line To Line:
19.5
Length Tolerance:
50
Primary Max Sep:
7.5
Secondary Max Sep: 100
Secondary Length: 500

NOSTUFF

R9135
1

y
r

PP3V3_PWRON_NEC_AVDD
VOLTAGE=3.3V
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=10 mil

FERR-EMI-100-OHM

N12

USB2
USB2

N10

USB2
USB2

D7

USB2_1
USB2_1

91 92

H4

USB2_P<0>
USB2_N<0>

G12

USB2_0
USB2_0

D13

DIFFERENTIAL_PAIR

USB2
USB2

F13

NET_SPACING_TYPE

USB2
USB2

H13

NET_PHYSICAL_TYPE

USB2_0
USB2_0

J13

ELECTRICAL_CONSTRAINT_SET

L13

USB_NEC_N<0>

(USB2_N<0>)
(USB2_P<0>)
USB_NEC_P<0>

R9101
36

1%
1/16W
MF-LF
402

NEC_UPD720101_USB2
FBGA

1%
1/16W
MF-LF
402

USB2_N<0>
USB2_P<0>

91 92
91 92

R9102
36

=PP3V3_PWRON_USB

RP9110

V1.0

76

6
6

92

92

92

B10 OCI3
A10 OCI4
B9 OCI5

92

91 7

R91401

6
6
6
6
6
6
6

1.5K

5%
1/16W
MF-LF
402 2

5%
1/16W
MF-LF
2 402

91

C9145
22pF

RSDM4
DM4
DP4
RSDP4

F12

USB_NEC_N<3>

F14

(USB2_N<3>)
(USB2_P<3>)
USB_NEC_P<3>

E12
E14

P6 NC1
M6 NC2

5%
50V
CERM 2
402

91 92
91 92

36

1%
1/16W
MF-LF
402

USB2_N<3>
USB2_P<3>

6 91 92
6 91 92

R9107
36

R9108
36

RSDM5 E13
DM5 D14

NEC_CLK30M_XT1
NEC_CLK30M_XT2_R

DP5 C13
RSDP5 C14

L9 XT1/SCLK
P8 XT2

USB_NEC_N<4>
(USB2_N<4>)
(USB2_P<4>)
USB_NEC_P<4>

1%
1/16W
MF-LF
402

USB2_N<4>
USB2_P<4>

76 91
76 91

R9109
36

MASTER: SEEDY

1%
1/16W
MF-LF
402

RREF P11

NEC_CLK30M_XT2

91

36

5%
1/16W
MF-LF
1 402

11.4X4.7X4.2-SM
1

USB2_N<2>
USB2_P<2>

R9105

100

Y9145

R9106

R9145

30.0000M

36

1%
1/16W
MF-LF
402

CRITICAL

91 92

1%
1/16W
MF-LF
402

NEC_NC1_PU
NEC_NC2_PU

91

91 92

1%
1/16W
MF-LF
402

USB_NEC_N<2>

(USB2_N<2>)
(USB2_P<2>)
USB_NEC_P<2>

R9141

1.5K

36

C9146

VSS

AVSS

22pF

5%
2 50V
CERM
402

XW9100
SM
1

AVSS(R)

DP3 G13
RSDP3 G14

USB Host Interfaces

NEC_RREF_PD

R91381
1%
1/16W
MF-LF
402 2

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

Tie to GND at ball N11


II NOT TO REPRODUCE OR COPY IT
91

GND_NEC_AVSS_R
VOLTAGE=0V
MIN_LINE_WIDTH=20 mil
MIN_NECK_WIDTH=10 mil

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART


SIZE

Y9145 LOAD CAPACITANCE IS ??PF

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-6772

SCALE

NOTICE OF PROPRIETARY PROPERTY

9.09K

N11

=PP3V3_PWRON_USB

RSDM3 H11
DM3 G11

M12

USB2_N<1>
USB2_P<1>

R9103

P13

D8

F11

G4

J11

J12

A9 PPON5

D12

(USB2_N<1>)
(USB2_P<1>)
USB_NEC_P<1>

J14

C10 PPON4

H12

K12

1%
1/16W
MF-LF
402

R9104

C11 PPON3

L12

USB_NEC_N<1>

1%
1/16W
MF-LF
402

A11 PPON2

e
r
92

K14

C12 PPON1

USB2_PWREN<0>
USB2_PWREN<1>
USB2_PWREN<2>
USB2_PWREN<3>
USB2_PWREN<4>

M11

NC27 W3
NC28 Y1
NC29 Y3

B11 OCI2

B13

NC24 V3
NC25 V4
NC26 W1

92

B12 OCI1

(USB2_OC<0>)
(USB2_OC<1>)
(USB2_OC<2>)
(USB2_OC<3>)
(USB2_OC<4>)

N2

NC21 U6
NC22 V1
NC23 V2

USB2_OC<0>
USB2_OC<1>
USB2_OC<2>
USB2_OC<3>
USB2_OC<4>

N13

NC19 U4
NC20 U5

92

B2

NC16 U1
NC17 U2
NC18 U3

92

A2

NC13 T6
NC14 T7
NC15 T8

92

B14

NC10 T3
NC11 T4
NC12 T5

H14

NC8 T1
NC9 T2

N14

NC5 R6
NC6 R7
NC7 R8

N1

NC2 R3
NC3 R4
NC4 R5

TP_SB_NC_P7
TP_SB_NC_P8
TP_SB_NC_R3
TP_SB_NC_R4
TP_SB_NC_R5
TP_SB_NC_R6
TP_SB_NC_R7
TP_SB_NC_R8
TP_SB_NC_T1
TP_SB_NC_T2
TP_SB_NC_T3
TP_SB_NC_T4
TP_SB_NC_T5
TP_SB_NC_T6
TP_SB_NC_T7
TP_SB_NC_T8
TP_SB_NC_U1
TP_SB_NC_U2
TP_SB_NC_U3
TP_SB_NC_U4
TP_SB_NC_U5
TP_SB_NC_U6
TP_SB_NC_V1
TP_SB_NC_V2
TP_SB_NC_V3
TP_SB_NC_V4
TP_SB_NC_W1
TP_SB_NC_W3
TP_SB_NC_Y1
TP_SB_NC_Y3

2 3

B1

NC0 P7
NC1 P8

5%
1/16W
SM-LF

RSDM2
DM2
DP2
RSDP2

m
il

10K

5%
1/16W
MF-LF
402 1

BGA
(8 OF 8)

10K

SHASTA
OMIT

7 6

R91102

U2300

P10

91 7

OF

91
1

04

102

ELECTRICAL_CONSTRAINT_SET

NET_SPACING_TYPE

PROVIDED
BY
USB
CONTROLLER

USB2
USB2

USB2_PORT1_F
USB2_PORT1_F

USB2_PORT1_P_F
USB2_PORT1_N_F

USB2
USB2

USB2_PORT2_F
USB2_PORT2_F

USB2_PORT2_P_F
USB2_PORT2_N_F

USB2
USB2

USB2_PORT3_F
USB2_PORT3_F

USB2_PORT3_P_F
USB2_PORT3_N_F

6 92

External USB Ports

6 92

6 92
6 92

6 92

L9210

6 92

FERR-250-OHM
59

PP5V_USB2

VOLTAGE=5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

Page Notes

91

ALIAS

91

USB2_PWREN<2>

ALIAS

91

USB2_PWREN<3>

ALIAS

91

USB2_PWREN<4>

ALIAS

10UF

C9213 1

0.01uF

y
r

J9210

20%
16V
CERM 2
402

USB-UAS25
F-ST-TH
5
6

SYM_VER-1

91

USB2_N<0>

USB2_PORT1_N
MAKE_BASE=TRUE

ALIAS

4
92 6

91

USB2_P<0>

USB2_PORT1_P
MAKE_BASE=TRUE

ALIAS

92 6

USB2_PORT1_N_F
USB2_PORT1_P_F

R9212
0

C9214

C9215

2
3
4

33pF

5%
50V
CERM 2
402

R9213
1

33pF

VDD
DD+
GND
NO STUFF

a
n
i

NO STUFF

402

5%
50V
2 CERM
402

514-0199

GND_CHASSIS_USB

R92101
5%
1/16W
MF-LF
402 2

402

R9211

15K

15K

MIN_NECK_WIDTH=15MIL
MIN_LINE_WIDTH=25MIL
VOLTAGE=0

5%
1/16W
MF-LF
2 402

7 92

L9220

FERR-250-OHM
1

SM

NOSTUFF
1

C9220

10UF

m
il

SM

GND_USB2_PORT2
VOLTAGE=0V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=20MIL
NOSTUFF

C9222 1 C9223
0.01uF

0.01uF

20%
16V
CERM 2
402

L9222
165-OHM
SYM_VER-1

USB2_N<1>

1
USB2_PORT2_N
MAKE_BASE=TRUE

ALIAS

92 6

91

USB2_P<1>

2
USB2_PORT2_P
MAKE_BASE=TRUE

ALIAS

92 6

USB2_PORT2_N_F
USB2_PORT2_P_F

R9222

e
r

R92201
15K

5%
1/16W
MF-LF
402 2

F9200
2AMP-6V
_PP5V_PWRON_USB

SM-1

R9200
160

5%
1/10W
MF-LF
2 603

91

USB2_OC<0>

91

USB2_OC<1>

ALIAS

91

USB2_OC<2>

ALIAS

91

USB2_OC<3>

ALIAS

USB_OC
MAKE_BASE=TRUE

R9201
300

5%
1/10W
MF-LF
2 603

ALIAS

91

USB2_P<2>

91

USB2_N<2>

5%
50V
CERM 2
402

R9223
0

5%
1/16W
MF-LF
402 2

R9251
15K

5%
1/16W
MF-LF
2 402

J9220

USB-UAS25
F-ST-TH
5
6

VDD
DD+
GND
NO STUFF

C9225

2
3
4

33pF

5%
50V
2 CERM
402

514-0199
GND_CHASSIS_USB

402

15K

5%
1/16W
MF-LF
2 402

7 92

L9230

FERR-250-OHM
1

SM

NOSTUFF

C9230
150uF

L9231

FERR-250-OHM
2

NOSTUFF

20%
2 6.3V
POLY
SMD

PP5V_USB2_PORT3_F
VOLTAGE=5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

C9231
10UF

10%
2 16V
CERM
1210

SM

GND_USB2_PORT3
VOLTAGE=0V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=20MIL
NOSTUFF

C9232

0.01uF

20%
16V
CERM 2
402

C9233 1

CRITICAL

0.01uF

J9230

20%
16V
CERM 2
402

USB-UAS25
F-ST-TH
5

L9232
165-OHM

SM
SYM_VER-1

92 6

USB2_PORT3_P_F

ALIAS

2
USB2_PORT3_N
MAKE_BASE=TRUE

92 6

USB2_PORT3_N_F

R9232
1

402

R9233
1

15K

15K

R9221

1
USB2_PORT3_P
MAKE_BASE=TRUE

5%
1/16W
MF-LF
402 2

R92501

ALIAS

R92301

33pF

402

USB2_N<3>
USB2_P<3>

CRITICAL

NO STUFF

C9224

91 6

20%
16V
CERM 2
402

SM

91

91 6

C9221MIN_NECK_WIDTH=10MIL

10%
16V
2 CERM
1210

20%
2 6.3V
POLY
SMD

UNUSED PORT

PP5V_USB2_PORT2_F
VOLTAGE=5V
MIN_LINE_WIDTH=25MIL

NOSTUFF
1

150uF

L9221

FERR-250-OHM

CRITICAL

0.01uF

20%
16V
CERM 2
402

PORT 1

C9212

SM

neoBorg Implementation

TP_USB2_PWREN<0>
MAKE_BASE=TRUE
TP_USB2_PWREN<1>
MAKE_BASE=TRUE
TP_USB2_PWREN<2>
MAKE_BASE=TRUE
TP_USB2_PWREN<3>
MAKE_BASE=TRUE
TP_USB2_PWREN<4>
MAKE_BASE=TRUE

C9211

10%
16V
2 CERM
1210

L9212
165-OHM

NOTE: This design does not provide power


control on USB ports 2-4. Rename
USB controller outputs to indicate
single-pin connections.
ALIAS

PP5V_USB2_PORT1_F
VOLTAGE=5V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL

SM

GND_USB2_PORT1
VOLTAGE=0V
MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=20MIL
NOSTUFF

NOTE: USB pairs are NOT constrained on


this page. It is assumed that the
USB Host Controller page will
provide the appropriate constraints
to apply to entire USB D+/D- XNets.

USB2_PWREN<1>

C9210
150uF

BOM options provided by this page:


(NONE)

USB2_PWREN<0>

NOSTUFF

20%
2 6.3V
POLY
SMD

FERR-250-OHM

Signal aliases required by this page:


(NONE)
NOTE: This page is expected to contain the
necessary aliases to map the
USB pairs to their appropriate
destinations and/or to properly
terminate unused signals.

91

NOSTUFF

L9211

Power aliases required by this page:


- _PP5V_PWRON_USB
- _PP5V_PWRON_UDASH
- _PP3V3_PWRON_UDASH
- _PP3V3_PWRON_BT

SM

PORT 2

I527

DIFFERENTIAL_PAIR

R9231

NO STUFF

C9234

33pF

5%
50V
CERM 2
402

VDD
DD+
GND
NO STUFF

C9235

33pF

5%
2 50V
CERM
402

2
3
4

PORT 3

I526

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
7 92

II NOT TO REPRODUCE OR COPY IT

402

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

15K

5%
1/16W
MF-LF
2 402

SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-6772

SCALE

NOTICE OF PROPRIETARY PROPERTY

514-0199
GND_CHASSIS_USB

USB Device Interfaces

04

OF

92

102

Page Notes
Power aliases required by this page:
- _PP3V3_PWRON_MODEM
Spec Load: 0.5 A active, 3 mA auxiliary
Signal aliases required by this page:
(NONE)
BOM options provided by this page:
(NONE)

y
r

Q52 Modem Connector


SDF9400
STDOFF-4MM-9MMH-TH
1

CRITICAL

a
n
i

J9401
C104A-H9.0
F-ST-SM
NC 35
32 NC
NC 31

94 7

_PP3V3_PWRON_MODEM

NC 5
NC 7
NC 9
NC 11
NC 13

NC

C9450
10UF

20%
6.3V
2 CERM
805

C9451
0.1UF

20%
10V
2 CERM
402

C
25 6

I2S1_SB_TO_DEV_DTO
I2S1_RESET_L

25 6

I2S1_MCLK

_PP3V3_PWRON_MODEM
MODEM_RING2SYS_L

R9451
10K

5%
1/16W
MF-LF
2 402

14

MODEM_FC_RGDT

17

16 NC
18 NC

19

20

NC 21

22

23

24

25

26

27

28

29

30

I2S1_SYNC
I2S1_DEV_TO_SB_DTI

I2S1_BITCLK

6 25
6 25

6 25

m
il
NC 33
NC 36

34 NC

516S0116

SDF9401

STDOFF-4MM-9MMH-TH

GND_CHASSIS_MODEM

e
r

7 94

6 25

10 NC
12 NC

15

25 6

NC
NC

RJ11 CONNECTOR
STUFFED AT FATP
SYMBOL USED FOR PLACEMENT

OMIT

J9402
RJ11-HGT27.5
ST-TH

1
2

514-0205

From Intel Mobile Audio/Modem


Daughter Card Specification
Rev 1.0, February 22, 1999
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

MONO_OUT/PC_BEEP
GND
AUXA_RIGHT
AUXA_LEFT
CD_GND
CD_RIGHT
CD_LEFT
GND
3.3Vaux
GND
3.3Vmain
AC97_SDATA_OUT
AC97_RESET#
GND
AC97_MSTRCLK

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

AUDIO_PWRON
MONO_PHONE
RESERVED
GND
5Vmain
RESERVED
RESERVED
PRIMARY_DN
5Vd
GND
AC97_SYNC
AC97_SDATA_INB
AC97_SDATA_INA
GND
AC97_BITCLK

Modem Interface

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-6772

04

OF

94

102

y
r

AUDIO CODEC
APPLE P/N 353S0933
MIN_LINE_WIDTH=12MIL
MIN_NECK_WIDTH=8MIL
VOLTAGE=3.3V

L9500

1000-OHM-200MA
102 101 100 7

PP3V3_AUDIO

a
n
i

PPV_3V3_AUDIO_CODEC

PP4V5_AUDIO_ANALOG

0603

PLACE AT U9500

C9500

1
1

18

I2C_AUDIO_SCL
I2C_AUDIO_SDA

19
18

25

I2S0_RESET_L

PDWN*

102

AUD_CODEC_MCLK

AUDI2S0OUT
AUDSPDIFOUT

C
I2S0_SB_TO_DEV_DTO

12

NET_SPACING_TYPE=AUDIO

21

NC 20
18

I2S0_DEV_TO_SB_DTI

NET_SPACING_TYPE=AUDIO

NOSTUFF

C9513
4.7PF

101

AUD_SPDIF_OUT

R9501
47K

+/-0.25PF
50V
C0G 2
402

5%
1/16W
MF-LF
2 402

R9502

NET_SPACING_TYPE=AUDIO

33

5%
1/16W
MF-LF
402

102 98 96 95

6
25
24
26
4
5

AUD_PCM_REF1
AUD_PCM_REF2

3
32
27
28

SCKI
ATEST

AGND

29

C9504
0.1UF

10%
2 16V
X7R
603

10%
2 10V
CERM
805

GND_AUDIO_CODEC

C9506
10UF

20%
2 16V
ELEC
SM

95 96 98 102

C9508

10UF

C9510
10UF

20%
2 16V
ELEC
SM

20%
2 16V
ELEC
SM

C9505 1

C9507 1

C9509 1

C9511 1

10%
16V
X7R 2
603

10%
16V
X7R 2
603

10%
16V
X7R 2
603

10%
16V
X7R 2
603

0.1UF

0.1UF

0.1UF

AUD_CODEC_IN_L
AUD_CODEC_IN_R

AUD_CODEC_OUT_L
AUD_CODEC_OUT_R
AUD_PCM_VCOM

AUD_CODEC_LI_SHDN_L
AUD_PSEUDO_VREF

96
96

98 100
98 100

100

96
96

AUD_PCM_MBIAS 102
AUD_MICIN_N 102
AUD_MICIN_P 102
1

C9512
10UF

20%
2 16V
ELEC
SM

0.1UF

e
r

GND_AUDIO_CODEC

DGND

5%
1/16W
MF-LF
402

1
1

NC

15

25

33

m
il
17

NET_SPACING_TYPE=AUDIO

R9500

MBIAS
MINM
MINP

25

13
14

22
30

25

11
10

NET_SPACING_TYPE=AUDIO

C9503
1UF

10%
2 10V
CERM
805

U9500

I2S0_BITCLK_DELAYED
I2S0_SYNC

1UF

VCC

VDD

PCM3052A
VQFN
VINL
BCK
VINR
LRCK
DOUT
VOUTL
DOUTS
VOUTR
DIN
VCOM
I2CEN
VREF1
ADR
VREF2
L/M#
SCL
REFO
SDA

102

C9502

31

23

1%
1/16W
MF-LF
2 402

16

1K

10%
2 10V
CERM
805

20%
6.3V
CERM 2
805

R9503

C9501
1UF

10UF

96 102

AUDIO: CODEC

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-6772

04

OF

95

102

LINE IN PSEUDO-DIFFERENTIAL AMP


AV= 0.49

D
NOSTUFF

y
r

C9603
47PF
102 96 95

PP4V5_AUDIO_ANALOG

5%
50V
CERM
402

C9600

R9604

10UF

101

AUD_LI_L

AUD_LI_L1

47K

5%
1/16W
MF-LF
402 2

R9603

0.47UF

100K

AUD_LI_GNDL1

20.5K2

R9600
165

1%
1/16W
MF-LF
2 402

AUD_LI_VREFL

10K

GND_AUDIO_CODEC
NOSTUFF

95

AUD_CODEC_LI_SHDN_L

m
il

AUD_CODEC_LI_SHDN_L1

5%
1/16W
MF-LF
402

102 96 95

PP4V5_AUDIO_ANALOG

C9604
2

AUD_LI_R

AUD_LI_R1

e
r
20%
16V
ELEC
SM

R9608

100K

1%
1/16W
MF-LF
2 402

10UF
2

AUD_LI_GND

P
96 95

102 98 96 95

AUD_PSEUDO_VREF

GND_AUDIO_CODEC

20%
16V
ELEC
SM

20.5K2

47PF
1

R9612
1

CRITICAL
10
8

SOT-363
5

5%
50V
CERM
402

D9600

NOSTUFF

AUD_LI_R2

BAV99DW-X-F

95

C9606

1%
1/16W
MF-LF
402

C9605

101 96

APPLE P/N 353S0642

R9609

10UF
101

AUD_CODEC_IN_L

V4

R9601

U9600

MAX4253EUB
UMAX
5

1%
1/16W
MF-LF
402
102 98 96 95

V+

R9606

AUD_PSEUDO_VREF

1%
1/16W
MF-LF
402

a
n
i

SOT-363
2

1%
1/16W
MF-LF
402

20%
16V
ELEC
SM

96 95

BAV99DW-X-F

R9605

10UF

AUD_LI_GND

10

C9601
101 96

D9600
1

20%
10V
CERM 2
603

1%
1/16W
MF-LF
2 402

10K

CRITICAL

C9602

R9602

AUD_LI_L2

1%
1/16W
MF-LF
402

20%
16V
ELEC
SM

R9607

20.5K2

V+

10K

1%
1/16W
MF-LF
402

U9600
MAX4253EUB
UMAX
9

AUD_CODEC_IN_R

B
95

V4

APPLE P/N 353S0642

R9610

AUD_LI_GNDR1

20.5K2

AUD_LI_VREFR

1%
1/16W
MF-LF
402

R9611
1

10K

1%
1/16W
MF-LF
402

AUDIO: LINE INPUT AMP

NOTICE OF PROPRIETARY PROPERTY


THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE

APPLE COMPUTER INC.

DRAWING NUMBER

D
SCALE

SHT
NONE

REV.

051-6772

04

OF

96

102

LINE OUT LOW-PASS FILTER


FC = 37 KHZ, HO = -1.4

R9801
14.0K2

1%
1/16W
MF-LF
402

C9800

R9800

10UF

100 95

AUD_CODEC_OUT_L

AUDCODECOUTL

10K

270PF

3.92K2

1%
1/16W
MF-LF
402

20%
16V
ELEC
SM-1

C9801

R9802
AUDCODECOUTL1

1%
1/16W
MF-LF
402

AUD_LOAMP_OUT_L

y
r

98

5%
50V
CERM
603

AUD_LOAMP_IN_L_M

98

AUD_LOAMP_IN_L_P

98

CRITICAL
1

C9802
1.5NF

5%
25V
2 CERM
0603
101

R9803
14.0K2

AUD_LO_GND_PRB

1%
1/16W
MF-LF
402

a
n
i

R9804
10K

1%
1/16W
MF-LF
2 402

LINE OUT
GROUND NOISE
CANCELLATION

R9805
10K

102 98 96 95

1%
1/16W
MF-LF
2 402

R9806

GND_AUDIO_CODEC

14.0K2

AUD_LOAMP_IN_R_P

1%
1/16W
MF-LF
402

CRITICAL

C9804
1.5NF

5%
25V
2 CERM
0603

C9803

R9807

10UF
100 95

AUD_CODEC_OUT_R

AUDCODECOUTR

10K

C9805

R9808

270PF

3.92K2

AUDCODECOUTR1

1%
1/16W
MF-LF
402

20%
16V
ELEC
SM-1

AUD_LOAMP_IN_R_M

1%
1/16W
MF-LF
402

AUD_LOAMP_OUT_R

5%
50V
CERM
603

14.0K2

1%
1/16W
MF-LF
402

LINE OUT AMP

APPLE P/N 353S0687


4.7

e
r
1

5%
1/10W
MF-LF
603

C9807

10UF

R98151
4.7K

C9812 1

5%
1/16W
MF-LF
402 2

102 98 96 95

100PF

13

VDDL

RINRIN+

ROUT 10

5%
50V
CERM 2
402

1K

5%
1/16W
MF-LF
402

16

AUDIO_LO_MUTE_L_F

C9813

C1P 2
C1N 4

SHDN*
VSS

8
7

11

AUDIO_LO_MUTE_L

LOUT 12

MAX9722AETE
QFN

R9816

TO SHASTA GPIO
25

VDDR

AUD_LOAMP_IN_R_M
AUD_LOAMP_IN_R_P

100PF

102

14

MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL

R9812
1

C9808
1UF

14

AUD_LO_R

C9809

101

AUD_LOAMP_OUT_R

98

1UF

AUD_MAX9722_C1N

R9817

MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL

R9818
1K

1%
1/16W
MF-LF
2 402

R9813
1

AUD_LO_GND 101

AUDIO: LINE OUT AMP

5%
1/8W
MF-LF
805

MIN_LINE_WIDTH=12MIL
MIN_NECK_WIDTH=8MIL
AUD_MAX9722_PVSS
1

MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL

10%
10V
2 CERM
805

10%
10V
2 CERM
805

1%
1/16W
MF-LF
2 402

C9810

101

MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL

1%
1/8W
MF-LF
805

AUD_MAX9722_C1P
1

98

AUD_LO_L

1%
1/8W
MF-LF
805

1K

10%
10V
CERM 2
805

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

20%
1 16V
ELEC
SM

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT

R9814
1

GND_AUD_LOAMP

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

2
SIZE

5%
1/8W
MF-LF
805

APPLE COMPUTER INC.

DRAWING NUMBER

SHT
NONE

REV.

051-6772

D
SCALE

NOTICE OF PROPRIETARY PROPERTY

C9811
10UF

1UF
GND_AUD_LOAMP_CHGPMP

NC 17

98 102

R9811

MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL

5%
50V
CERM 2
402

GND_AUDIO_CODEC

102 98

AUD_LOAMP_OUT_L

U9800

LINLIN+

PVSS

98

14
15

B
GND_AUD_LOAMP_CHGPMP

CRITICAL

SGND

98

AUD_LOAMP_IN_L_M
AUD_LOAMP_IN_L_P

PGND

98

10UF

98

102 98

GND_AUD_LOAMP_CHGPMP

C9806

20%
2 16V
ELEC
SM

PVDD

20%
6.3V
CERM 2
805

98

MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=5V
PP5V_AUDIO_LOAMP

R9810
PP5V_AUDIO_ANALOG

98

m
il
R9809

102

98

04

OF

98

102

MIN_LINE_WIDTH=40MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=12V

FA000
1.5AMP-33V
1

PP12V_AUDIO_SPKRAMP

MIN_LINE_WIDTH=40MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=12V
PP12V_AUDIO_SPKRAMP_F

XWA000
OMIT
SM

DIFFERENTIAL_PAIR=AUD_SPKRAMP_PWR
NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=40MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=12V

FERR-250-OHM

PP12V_AUDIO_SPKRAMP_F2

SPEAKER AMP

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=12V

LA000

APPLE P/N 353S0680

PP12V_AUD_SPKRAMP_PLANE

SM-1

CA017

SM

LA005

AUDSAMPINLN

CA005
2
10%
16V
X7R
805

AUD_PCM_VCOM

LA007

CA006

1000-OHM-200MA

0.47UF

AUDSAMPINRP

0603

C
LA008

1000-OHM-200MA
1

AUD_CODEC_OUT_R

0603

100

PP3V3_AUDIO_SPKR

10K

2 AUDIO_SPKR_MUTE_L_INV

1%
1/16W
MF-LF
402

TIE TO SHASTA GPIO


25

AUDIO_SPKR_MUTE_L

47K

AUDIO_SPKR_MUTE_L_F

5%
1/16W
MF-LF
402

RA0121
4.7K

5%
1/16W
MF-LF
402 2

CA020 1

CA021 1

100PF

100PF

5%
50V
CERM 2
402

GND_AUDIO_SPKRAMP

102 100

22

NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL

LA001

AUD_SPKR_OUTL_P

NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL

LA002

180-OHM-1.5A
1

CA008
0.1UF

10%
50V
2 X7R
603-1

LA003

AUD_SPKR_OUTL_N

SS 12

PGND

NOSTUFF

LA011
800-OHM
ACM4532
SYM_VER-1

C
NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL

AUD_SPKR_OUTR_P

RA016

PP3V3_AUDIO

5%
1/10W
MF-LF
603

MIN_LINE_WIDTH=4MIL
MIN_NECK_WIDTH=4MIL
PP3V3_AUDIO_SPKR_EMI

RA017

180-OHM-1.5A
1

AUDSAMPOUTRN

AUD_SPKR_OUTR_N

101

0603

NOSTUFF

LA012
800-OHM
ACM4532
SYM_VER-1

NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL

LA004

NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL

CA010
1000PF

5%
2 25V
CERM
603

CA011
1000PF

5%
2 25V
CERM
603

CA012

1000PF

CA013
1000PF

5%
2 25V
CERM
603

5%
2 25V
CERM
603

CA009
0.47UF

10%
16V
2 X7R
805

APPLE P/N 155S0194

MIN_LINE_WIDTH=4MIL
MIN_NECK_WIDTH=4MIL

PP3V3_AUDIO_SPKR

5%
1/10W
MF-LF
603

NOSTUFF

CA022 1

8 7

100

6 5

RPA000

100PF

47K

5%
50V
CERM 2
402

5%
1/16W
SM-LF
1 2

3 4

AUDIO: SPEAKER AMP


AUD_SAMP_G1
100 AUD_SAMP_G2
100 AUD_SAMP_FS1
100 AUD_SAMP_FS2

100

NOTICE OF PROPRIETARY PROPERTY

NOSTUFF

RA008
0

5%
1/16W
MF-LF
2 402

102 100

RA009
0

5%
1/16W
MF-LF
2 402

NOSTUFF
1

RA010
0

5%
1/16W
MF-LF
2 402

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

NOSTUFF

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

RA011

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

5%
1/16W
MF-LF
2 402

SIZE

APPLE COMPUTER INC.

GND_AUDIO_SPKRAMP_PLANE

DRAWING NUMBER

SHT
NONE

REV.

051-6772

SCALE

101

GAIN AND SWITCHING FREQUENCY STUFF OPTIONS

101

0603

180-OHM-1.5A
1

101

0603

GAIN SETTINGS: +19DB


MODULATION SETTING: LOW EMI

102 101 95 7

THM
AGND PAD

CA014

e
r

MIN_LINE_WIDTH=40MIL
MIN_NECK_WIDTH=10MIL

GND_AUDIO_SPKRAMP_PLANE

14 REG

10%
2 16V
X7R
805

XWA002
OMIT
SM
1

OUTR- 25
OUTR- 26

100 102

180-OHM-1.5A

NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL
AUDSAMPOURTP

0.47UF

SM

102 7

m
il

5%
50V
CERM 2
402

XWA001
OMIT

10%
16V
2 CERM
1210

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
AUDSAMPCSS

XCA000
50R28
DIFFERENTIAL_PAIR=AUD_SPKRAMP_PWR
NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=40MIL
MIN_NECK_WIDTH=10MIL

C1- 5

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
AUDSAMPCPN

OUTR+ 27
OUTR+ 28

SHDN*

y
r

CA023

a
n
i

C1+ 6

QFN

8 NC

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL

SOT-363

U9700

10UF

10%
16V
2 CERM
1210

NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL
AUDSAMPOUTLN

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
AUDSAMPCPP

MAX9714

CA003
10UF

20%
16V
2 CERM
603

0603

AUD_MAX9714_VREG

2N7002DW

SOT-363

19 FS1
20 FS2

NC

QA000

2N7002DW

100 AUD_SAMP_FS1
100 AUD_SAMP_FS2

CHOLD 7

OUTL- 29
OUTL- 30

0.1UF

NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL
AUDSAMPOUTLP

OUTL+ 31
OUTL+ 32

15 INR-

AUD_SAMP_SHDN_L 11

QA000

RA013

16 INR+

2
10%
16V
X7R
805

RA015

AUD_SAMP_INR_P

17 G1
18 G2

CA007

AUDSAMPINRN

10 INL+

AUD_SAMP_G1
100 AUD_SAMP_G2

0.47UF

AUD_SAMP_INL_P

100

100PF

5%
50V
2 CERM
402

9 INL-

AUD_SAMP_INR_N

2
10%
16V
X7R
805

CA016

AUD_SAMP_INL_N

CA019

GND_AUDIO_SPKRAMP_PLANE

24

21
VDD

0.47UF

AUDSAMPINLP

0603

1%
1/16W
MF-LF
2 402

10K

23

1000-OHM-200MA

RA014

CA015

5%
2 50V
CERM
402

LA006

2
10%
16V
X7R
805

100PF

100

20%
16V
2 CERM
1206

33

AUD_CODEC_OUT_L

CA002
1UF

20%
16V
CERM 2
603

0.47UF

98 95

0.1UF

PP3V3_AUDIO_SPKR

CA004

0603

95

CA018 1

10%
16V
CERM 2
1210

20%
16V 2
ELEC
SM-2

GND_AUDIO_SPKRAMP_PLANE

1000-OHM-200MA
98 95

10UF

220UF

20%
16V 2
ELEC
SM-2
102 100

CA001

CA000 1

220UF

AUD_MAX9714_CHOLD

XWA003
OMIT

MIN_LINE_WIDTH=12MIL
MIN_NECK_WIDTH=8MIL

SM

13

04

OF

100

102

LINE IN JACK

SPEAKER CABLE CONNECTOR

APPLE P/N 514-0203

APPLE P/N 518-0138

F-ST-TH
5

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
AUD_LI_L_EMI

FERR-EMI-100-OHM
1

SM

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
AUD_LI_L 96

FERR-EMI-100-OHM
SM

100

LA101

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
AUD_LI_DET_JACK

1
3

LA105

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
AUD_LI_DET_EMI

FERR-EMI-100-OHM

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL

AUD_LI_R_EMI

AUD_LI_GND_JACK

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL

CA100
100PF

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
AUD_LI_GND_EMI

5%
2 50V
CERM
402

CA101
100PF

5%
2 50V
CERM
402

CA102

100PF

CA103

5%
1/16W
MF-LF
2 402

SPEAKER TYPE DETECT


TO SHASTA GPIO

DZA100

5%
2 50V
CERM
402

14V-15A

GND_CHASSIS_AUDIO_EXTERNAL

LA108

102

GND_AUDIO_MIC

RA101
47K

RA100

5%
1/16W
MF-LF
2 402

100K

5%
1/16W
MF-LF
2 402

GND_AUDIO_MIC_EMI

SM

SM

LA109

LA112

FERR-EMI-100-OHM

TO SHASTA GPIO
102

AUDIO_LI_DET_L

AUD_MIC_IN_P

RA102
2

AUDLINDETH

5%
1/16W
MF-LF
402

SOT23-LF

102

AUD_MIC_IN_N

CA108

m
il

LA122

FERR-EMI-100-OHM

AUD_SPDIF_OUT_EMI

LA115

LA123

MIN_LINE_WIDTH=12MIL
MIN_NECK_WIDTH=8MIL
PP5V_AUDIO_SPDIF_EMI

FERR-EMI-100-OHM
1
SM

LA124

FERR-EMI-100-OHM
AUD_LO_DET1

FERR-EMI-100-OHM

AUD_LO_DET1_EMI

SM

AUD_LO_R

LA125

MIN_LINE_WIDTH=12MIL
MIN_NECK_WIDTH=8MIL
AUD_LO_R_EMI

FERR-EMI-100-OHM
98

FERR-EMI-100-OHM
1

SM

2
SM

LA119

FERR-EMI-100-OHM
101

AUD_LO_DET2

AUD_LO_DET2_EMI

SM

LA120

AUD_LO_GND

2
SM

LA121

FERR-EMI-100-OHM

98

AUD_LO_GND_PRB

AUD_LO_GND_PRB_EMI

SM

CA123

CA111

100PF

100PF

CA124
100PF

5%
2 50V
CERM
402

CA117
0.1UF

20%
2 10V
CERM
402

1000PF

5%
25V
2 CERM
603

1000PF

CA107
1000PF

AUDIO_LO_DET_L = LOW: PLUG INSERTED


AUDIO_LO_DET_L = HIGH: PLUG NOT INSERTED
AUDIO_LO_OPTICAL_PLUG_L = LOW: OPTICAL DIGITAL AUDIO PLUG INSERTED
AUDIO_LO_OPTICAL_PLUG_L = HIGH: ANALOG AUDIO PLUG INSERTED

PP3V3_AUDIO
1

RA104
47K

RA103

5%
1/16W
MF-LF
2 402

100K
5%
1/16W
MF-LF
2 402

47K

TO SHASTA GPIO
AUDIO_LO_DET_L

3
D
5

AUD_LO_DET1_1

5%
1/16W
MF-LF
402

6 25

QA101

2N7002DW
SOT-363

S
4

CA109
0.1UF

20%
2 10V
CERM
402

F-ST-TH
9
10

AUD_LO_GND_JACK
AUD_LO_DET1_JACK
AUD_LO_R_JACK
AUD_LO_L_JACK

AUD_LO_DET2_JACK

102 101 100 95 7

PP3V3_AUDIO
1

RA107

RA106

4
2

5%
1/16W
MF-LF
2 402

100K

5%
1/16W
MF-LF
2 402

AUDIO_LO_OPTICAL_PLUG_L
6

6
7
8

VIN
VDD
GND

RA108
101

AUD_LO_DET2

11

NOSTUFF

12

RA109

47K

AUD_LO_DET2_1

5%
1/16W
MF-LF
402

2N7002DW
SOT-363

S
1

CA110

20%
2 10V
CERM
402

5%
1/16W
MF-LF
2 402

MIN_LINE_WIDTH=12MIL
MIN_NECK_WIDTH=8MIL
AUD_SPDIF_GND

25

QA101

0.1UF

100K

SM

TO SHASTA GPIO

47K

FERR-EMI-100-OHM

RA1121
0

LA129

PLACE NEAR
J9801

5%
1/16W
MF-LF
402 2

FERR-EMI-100-OHM
2

XCA100
50R28

SM
1

AUD_LI_GND_EMI

5%
50V
2 CERM
402

CA114

PLACE NEAR
J700

AUDIO: Q45 CONNECTORS

XCA101
50R28

NOTICE OF PROPRIETARY PROPERTY

CA115
100PF

5%
50V
2 CERM
402

DZA101
1

CA116

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

101

101 7

GND_CHASSIS_AUDIO_INTERNAL

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

MMBZ15DLT1

II NOT TO REPRODUCE OR COPY IT

15V

0.01UF

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SOT23

10%
16V
2 CERM
402

SIZE

DRAWING NUMBER

SHT
NONE

REV.

051-6772

D
SCALE

CA127

5%
25V
2 CERM
603

5%
25V
2 CERM
603

APPLE COMPUTER INC.

LINE OUT PLUG DETECTS

JA103

GND_CHASSIS_AUDIO_EXTERNAL

CA126

JFJ8210

5%
25V
2 CERM
603

APPLE P/N 514-0204

1UF

100

NOSTUFF

CA106
1000PF

LINE OUT JACK

10%
2 10V
CERM
805

MIN_LINE_WIDTH=12MIL MIN_NECK_WIDTH=8MIL
MIN_LINE_WIDTH=12MIL MIN_NECK_WIDTH=8MIL

RA105

CA118

MIN_LINE_WIDTH=12MIL MIN_NECK_WIDTH=8MIL

1000PF

101 AUD_LO_DET1

LA128

100PF

5%
2 50V
CERM
402

102 101 100 95 7

SM

100PF

1000PF

FERR-EMI-100-OHM

CA113

CA112

APPLE P/N 518-0034

MIC CABLE CONNECTOR

LA127

5%
50V
2 CERM
402
1

SM

100PF

5%
50V
2 CERM
402

5%
2 50V
CERM
402

102 101 7

FERR-EMI-100-OHM

MIN_LINE_WIDTH=12MIL
MIN_NECK_WIDTH=8MIL
AUD_LO_GND_EMI

FERR-EMI-100-OHM
98

LA126

MIN_LINE_WIDTH=12MIL
MIN_NECK_WIDTH=8MIL
AUD_LO_L_EMI

FERR-EMI-100-OHM
AUD_LO_L

SM

LA118

98

SM

LA117

CA122

10%
2 25V
X7R
402

10%
2 25V
X7R
402

AUD_SPKR_OUTL_P

2
0603

101

1000PF

NOSTUFF

CA105

5%
25V
2 CERM
603

MIN_LINE_WIDTH=12MIL
MIN_NECK_WIDTH=8MIL
PP5V_AUDIO_SPDIF_JACK

e
r

SM

LA116

CA121

AUD_SPDIF_OUT_JACK

SM

FERR-EMI-100-OHM

GND_CHASSIS_AUDIO_INTERNAL

SM

PP5V_AUDIO

10%
2 25V
X7R
402

FERR-EMI-100-OHM
1

CA120
1000PF

LA114

AUD_SPDIF_OUT

AUD_MIC_IN_N_EMI

101 7

95

LA113
SM

20%
10V
2 CERM
402

5%
25V
2 CERM
603

HF28

SM

0.1UF

1000PF

GND_AUDIO_MIC_CONN
6 AUD_MIC_IN_P_CONN
6 AUD_MIC_IN_N_CONN

FERR-EMI-100-OHM

NOSTUFF

CA104

M-ST-TH

SM

AUD_LI_DET_H

AUD_MIC_IN_P_EMI

FERR-EMI-100-OHM

2N7002

NOSTUFF
1

AUD_SPKR_OUTL_P_CONN

101

47K

LA110

QA100

1000PF

JA102

FERR-EMI-100-OHM

SM

25

CA125

5%
2 25V
CERM
603

FERR-EMI-100-OHM

1
1

GND_CHASSIS_AUDIO_INTERNAL

LA111

FERR-EMI-100-OHM

PP3V3_AUDIO

CA119

a
n
i

AUDIO_IN_DET0_L = LOW: PLUG INSERTED


AUDIO_IN_DET0_L = HIGH: PLUG NOT INSERTED

5%
2 25V
CERM
603

101 7

2
0603

1000PF

0405

LINE IN PLUG DETECT

LA132

1000-OHM-200MA
AUDIO_GPIO_12

100

LA134

y
r

RA113

NOSTUFF

100PF

5%
2 50V
CERM
402

102 101 100 95 7

AUD_SPKR_OUTL_N_CONN

AUD_SPKR_OUTR_N

NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=12MIL
180-OHM-1.5A

25

102 101 7

SM

GND_CHASSIS_AUDIO_EXTERNAL

101

SM

PP3V3_AUDIO

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
AUD_LI_GND 96

FERR-EMI-100-OHM

NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=12MIL

0603
102 101 100 95 7

2
0603

M-ST-TH

47K

LA107

FERR-EMI-100-OHM

102 101 7

AUD_SPKR_OUTL_N

SM

LA103

100

AUD_SPKR_OUTR_N_CONN

10-89-7082

LA131

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
AUD_LI_R 96

FERR-EMI-100-OHM

SM

LA133

JA101

AUD_SPKR_OUTR_P_CONN

180-OHM-1.5A

LA106

FERR-EMI-100-OHM

NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=12MIL
180-OHM-1.5A

0603

SM

LA102

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
AUD_LI_R_JACK

AUD_SPKR_OUTR_P

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
AUD_LI_DET_H 101

FERR-EMI-100-OHM

SM

NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=12MIL

LA130

180-OHM-1.5A

MIN_LINE_WIDTH=8MIL
MIN_NECK_WIDTH=6MIL
AUD_LI_L_JACK

AJR23

LA104

AUDIO_GPIO_12_CONN

LA100

LED

JA100

OF

101

04
102

RA226

RA227

5%
1/16W
MF-LF
402

5V POWER SUPPLY FOR THE HEADPHONES/LINE OUT AMP

NET_SPACING_TYPE=AUDIO
I2S0_BITCLK_8NS_DELAY
ELECTRICAL_CONSTRAINT_SET=8NS

UNUSED GPIO TERMINATIONS

5%
1/16W
MF-LF
402

NOSTUFF

RA225
25

APPLE P/N 353S0539

DIFFERENTIAL_PAIR=AUD_CODEC_PWR
NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=40MIL
MIN_NECK_WIDTH=12MIL
VOLTAGE=12V

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=12MIL
VOLTAGE=12V

LA200

PP12V_AUDIO_CODEC

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=12MIL
VOLTAGE=12V

AUD_12V_CODEC

SM-1

10

102 101 100 95 7

I2S0_BITCLK_DELAYED

5%
1/16W
MF-LF
402

RA228

5%
1W
FF
2512

SOT223-4

PP5V_AUDIO_ANALOG

IN

CA200

1UF

CA201
220UF

20%
16V
2 CERM
1206

20%
2 16V
ELEC
SM-2

CA209
220UF

CA203

RA216

20%
2 16V
ELEC
SM

100

GND_AUDIO_SPKRAMP_PLANE

1%
1/16W
MF-LF
402 2

20%
16V 2
ELEC
SM

GND_AUDIO_CODEC

95 96 98 102

25

a
n
i

634

100UF

5%
1/8W
MF-LF
805

RA202

CA202 1

25

NOSTUFF

100UF

AUD_V5_REF
FC=7HZ

PLACE NEAR ENTRY TO SPEAKER


AMP GROUND PLANE

GND_AUDIO_CODEC

NOSTUFF

RA217

100 7

CRITICAL

VRA201
MAX8510EXK45+T
SC70-5

PP5V_AUDIO_ANALOG

RA2031
NOSTUFF

102 101 100 95 7

PP4V5_AUDIO_ANALOG

BP 4

100K 2

10%
16V
2 CERM
402

GND
2

102 98 96 95

CA204
10UF

CA205
0.1UF

20%
6.3V
2 CERM
805

NOT USED: C9906

10%
16V
2 X7R
603

GND_AUDIO_CODEC

CA207

10%
2 10V
CERM
805

CA208
10UF

20%
2 16V
ELEC
SM-1

101 7

e
r

AUDIO GROUND RETURNS


DIFFERENTIAL_PAIR=AUD_CODEC_PWR
NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=40MIL
MIN_NECK_WIDTH=12MIL
7

XWA200
OMIT
SM

GND_AUDIO

XWA201
OMIT
SM
1

XWA202
OMIT
SM

A
XWA203
OMIT
SM

XCA201
50R28

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=4.5V

GND_AUDIO_CODEC

95 96 98 102

MIN_LINE_WIDTH=10MIL
MIN_NECK_WIDTH=6MIL
VOLTAGE=4.5V

GND_AUDIO_MIC

101 102

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=4.5V

GND_AUD_LOAMP

RA208
1

AUDIO_SPKR_DET_L

RA210
1

AUDIO_GPIO_11

165

1%
1/16W
MF-LF
402

I2S2_BITCLK

RA221

I2S2_SYNC

AUDIO_HP_MUTE_L

47K

AUDIO_EXT_MCLK_SEL

47K

5%
1/16W
MF-LF
402

AUD_PCM_MBIAS

CA210

I2S2_RESET_L

47K

95

MAKE_BASE=TRUE
TP_I2S2_SB_TO_DEV_DTO

I88

MAKE_BASE=TRUE
TP_I2S2_MCLK

I89

MAKE_BASE=TRUE
I2S0_MCLK

I116

I2S2_SB_TO_DEV_DTO

I2S2_MCLK

AUD_CODEC_MCLK

25

25

95

CA211
10UF

20%
2 16V
ELEC
SM-1

GND_AUDIO_CODEC

165

1%
1/16W
MF-LF
402

CA213
0.1UF

95 96 98 102

100K
1%
1/16W
MF-LF
402 2

AUDIO: Q45 POWER SUPPLIES

CA214
0.1UF
1

AUD_MIC_M1
DIFFERENTIAL_PAIR=AUDIO_MIC_1
NET_SPACING_TYPE=AUDIO

DIFFERENTIAL_PAIR=AUDIO_MIC_2
NET_SPACING_TYPE=AUDIO
AUD_MICIN_P 95

10%
16V
X7R
603

RA2221

RA224

NOTICE OF PROPRIETARY PROPERTY

DIFFERENTIAL_PAIR=AUDIO_MIC_2
NET_SPACING_TYPE=AUDIO
AUD_MICIN_N 95

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY


PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

10%
16V
X7R
603

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT

1K

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

1%
1/16W
MF-LF
2 402

SIZE

GND_AUDIO_MIC

APPLE COMPUTER INC.

DRAWING NUMBER

REV.

051-6772
SHT
NONE

RA214
25

SCALE

47K

5%
1/16W
MF-LF
402

1%
1/16W
MF-LF
2 402

RA215

AUD_MIC_P1

1K

47K

5%
1/16W
MF-LF
402

25

DIFFERENTIAL_PAIR=AUDIO_MIC_1
NET_SPACING_TYPE=AUDIO

RA220
1

1%
1/16W
MF-LF
2 402

NOSTUFF

5%
1/16W
MF-LF
402

1K

RA219

AUD_MIC_IN_N

47K

RA223

1%
1/16W
MF-LF
2 402

98

1K

DIFFERENTIAL_PAIR=AUDIO_MIC
NET_SPACING_TYPE=AUDIO

47K

5%
1/16W
MF-LF
402

RA213
25

5%
1/8W
MF-LF
805

20%
6.3V
2 CERM
805

RA218

10%
25V 2
X7R
402

RA209

I2S2_DEV_TO_SB_DTI

RA229

NOSTUFF

AUD_MIC_IN_P

47K

5%
1/16W
MF-LF
402

5%
1/16W
MF-LF
402

25

RA212
25

PLACE AT J5903

GND_CHASSIS_AUDIO_EXTERNAL

47K

5%
1/16W
MF-LF
402

10UF

1000PF

102 101

RA207

AUDIO_HP_DET_L

5%
1/16W
MF-LF
402

5%
1/10W
MF-LF
603

CA212

101

GND_AUD_LOAMP_CHGPMP

25

NOSTUFF

98

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=4.5V

RA211

MICROPHONE IMPEDANCE MATCHING CIRCUIT

DIFFERENTIAL_PAIR=AUDIO_MIC
NET_SPACING_TYPE=AUDIO

101

GND_AUDIO_CODEC

m
il

AUD_4V5_FB

1UF

25

47K

5%
1/16W
MF-LF
402

RA205

CA206

AUD_4V5_SHDN*

95 96

0.01UF

1%
1/16W
MF-LF
402

102 98 96 95

SHDN*

1%
1/16W
MF-LF
402 2

RA204
PP3V3_AUDIO

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=4.5V

100K

25

PLACE ACROSS GROUND SPLIT


AT CODEC U9500

OUT 5

IN

5%
1/8W
MF-LF
805

APPLE P/N 353S0733

102 98

GND_AUDIO_SPKRAMP

4.5V POWER SUPPLY FOR CODEC AND LINE IN AMP

AUDIO_LI_OPTICAL_PLUG_L

y
r

PLACE ACROSS GROUND SPLIT


AT RIGHT SIDE OF CA007

1%
1/16W
MF-LF
402 2

20%
2 16V
ELEC
SM-2

25

98 102

RA2011

RA206

5%
1/16W
MF-LF
2 402

VOUT 4
OUT 2
ADJ/GND

95

LM1117MPX
AUD_12V_CODEC2

MIN_LINE_WIDTH=12MIL
MIN_NECK_WIDTH=8MIL
PP3V3_AUDIO

NOSTUFF

205

102 98 96 95

NET_SPACING_TYPE=AUDIO

MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL
VOLTAGE=5V

VRA200

RA200

FERR-250-OHM
7

CRITICAL

I2S0_BITCLK

04

OF

102

102

Das könnte Ihnen auch gefallen