SR Master-Slave Flip-Flop

Read input at first half of clock cycle Output only changed at second half of clock cycle

Master S C S C Y S C

Slave Q

Y
R R

SR Master-Slave Flip-Flop
An RS Master-Slave Flip-Flop is pulse-triggered. This means:
Data are entered on the rising edge of the clock pulse But, output is only changed on the falling edge of the clock pulse

Note: Changes while the clock pulse is HIGH can affect the eventual output.
Hence, to avoid ambiguity, make sure that the inputs are stable during the entire period while the clock pulse is HIGH.

Symbol
S C R SR Master-Slave Flip-Flop

Timing Diagram
C

Counters
Counters are a specific type of sequential circuit. Like registers, the state, or the flip-flop values themselves, serves as the output. The output value increases by one on each clock cycle. After the largest value, the output wraps around back to 0. Using two bits, wed get something like this:

Present State A B 0 0 1 1 0 1 0 1

Next State A B 0 1 1 0 1 0 1 0

00 1

01
1

1 11 10

A slightly fancier counter

Lets try to design a slightly different two-bit counter: Again, the counter outputs will be 00, 01, 10 and 11. Now, there is a single input, X. When X=0, the counter value should increment on each clock cycle. But when X=1, the value should decrement on successive cycles. Well need two flip-flops again. Here are the four possible states:
00 01

11

10

The complete state diagram and table Heres the complete state diagram and state table for this circuit.

0 00 01

Present State Q1 Q0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1

Inputs X 0 1 0 1 0 1 0 1

Next State Q1 Q0 0 1 1 0 1 0 0 1 1 1 0 0 1 1 0 0

1
0 1 1 1 10 0

11 0

Henry Hexmoor