Verilog - 00 (Design) Basics of Digital Design (v01!26!2013)

Verilog Design
Digital Design & Synthesis
Basics of Digital Design

Author: Kyle Gilsdorf Contact Info: Kyle.Gilsdorf@asu.edu Website: https://myasucourses.asu.edu
Today, we are going to talk about the following concepts:
Basics of Digital Design (Combinational Elements) AND, OR NOT BOOLEAN algebra (Synchronous Elements) Latches Examples of how timing works Clocks Synchronous Latch Design (Flip-Flop) Positive, Edge, and Level Triggers (schematic representation) Timing Diagrams for Flip-Flops Introduction to Setup/Hold Concepts Discrete & TTL Components AND, OR, NOT, and Flop Breadboard Based Design Converting Breadboard Based Design into HDL
Kyle.Gilsdorf@asu.edu
Verilog Design
Review of Logic Gates [AND]
Lets assume that: True has the value of 1 or +5 Volts False has the value of 0 or +0 Volts Using transistors we can create a component that performs the AND operation using voltage to represent the logical values. An AND gate is represented in schematic form as seen below:
A B
Transistor Analogy
C = A & B
AND Logical Operator/Gate
A T (1) T (1) F (0) F (0) B T (1) F (0) T (1) F (0) C = A & B T (1) F (0) F (0) F (0)
+
+5V
Switch Analogy
0 1
10K A
0
1
Lamp (out)
B On = 1 Off = 0
10K out
10K
Analogies taken from P. Scherz
Verilog Design
Review of Logic Gates [OR]
Lets assume that: True has the value of 1 or +5 Volts False has the value of 0 or +0 Volts Using transistors we can create a component that performs the OR operation using voltage to represent the logical values. An OR gate is represented in schematic form as seen below:
A
B
A + B C
Transistor Analogy
+5V
10K
OR Logical Operator/Gate
A T (1) B T (1) C = A + B T (1)
+
Switch Analogy
0 0 1
A 10K B out 10K
Lamp (out)
1
On = 1 Off = 0
T (1)
F (0) F (0)
F (0)
T (1) F (0)
T (1)
T (1) F (0)
Verilog Design
Review of Logic Gates [NOT]

NOT Logical operator/gate X Y = X
Transistor Analogy Switch Analogy
1 Lamp (out) +5V
10K out 10K
X T (1) F (0)
Y = X F (0) T (1)
0
-
in
On = 1 Off = 0 in
Note: All digital computers are built using ONLY these three gate types: AND, OR, and NOT. We will show some examples of how more complex gates can be constructed using only these three gates.
Kyle.Gilsdorf@asu.edu 4
Verilog Design
Review of Logic Gates [NAND & NOR]

NAND Gate = NOT (AND)
A B
A & B
NOR Gate = NOT(OR)

A B
A B
A T (1) T (1) F (0) F (0) B T (1) F (0) T (1) F (0)
A + B
A + B
A & B
C = A & B
C = A + B
A B
A T (1) T (1) F (0) B T (1) F (0) T (1)
C = A & B
C = A & B F (0) T (1) T (1)
C = A + B
C = A + B F (0) F (0) F (0) T (1)
5
F (0)
F (0)
T (1)
Verilog Design
Review of Logic Gates [XOR]

A
XOR Gate = AB + AB
A
Y = A B = AB + AB
+
B
T F T F (1) (0) (1) (0)
+ B C = A +
T T F F
(1) (1) (0) (0)
F T T F
(0) (1) (1) (0)

6
Verilog Design
Boolean Expressions and Math

Commutative a + b = b + a ab = ba Associative (a + b) + c = a + (b + c) (ab) c = a (bc) Distributive a + (bc) = (a + b)(a + c) a(b + c) = (ab) + (ac) Identity a+0=a a*1=a Complement a+a=1 a*a=0
a
b
ab
a
b a
a+b
a a b
ab
ab
a
b
a
b
a+b
Verilog Design
What if we only use NANDs or NORs

NAND equivalent circuit NOR equivalent circuit
NOT
AND
OR
Verilog Design

Combinational Logic Design
y bc 00 a 0 0
A) Problem description
y is 1 if a is to 1, or b and c are 1. z is 1 if b or c is to 1, but not both, or if all are 1.
D) Minimized output equations

z
01 0 1
11 1 1
10 0 1
00 0 0 1 0
bc
01 1 1
11 0 1
10 1 1
B) Truth Table
a 0 0 0 0 1 1 1 1 Inputs b c 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 Outputs y z 0 0 0 1 0 1 1 0 1 0 1 1 1 1 1 1
y = a + bc
z = ab + bc + bc
E) Logic Gates
a b c y
C) Output equations
y = a'bc + ab'c' + ab'c + abc' + abc
z = a'b'c + a'bc' + ab'c + abc' + abc

Verilog Design
Review of Storage Elements [Latch]

R Q Latch Logical Element S
S R F (0) F (0) F (0) T (1) T (1) F (0) T (1) T (1)

Q Q F (0) T (1) INVALID
Q Next State of the Latch Q Present State of the Latch
10
Verilog Design
Review of Storage Elements [Latch...]

0
Q
1
Write (Store 1)
11
Verilog Design

0
Q
1
Write (Store 1)
12
Verilog Design

0
R
0
X 1
Q
0
Write (Store 1)
13
Verilog Design

0
R
0
X 1
X 1 1
Q
0 0
Write (Store 1)
14
Verilog Design

Clocks
Falling Edge of Clock
1 0
Rising Edge of Clock
Hi
Low
Time Clock Period High Level of Clock
Low Level of Clock
Clocks electrical signals that follow a high/low pattern at some fixed period or frequency. Some examples of electronic components that can generate clocks are crystal oscillators and phase locked loops.
Clocks are used to make a design synchronous. In digital design we primarily deal with Synchronous Latches as inputs and outputs to combinational logic (more on this later).
Verilog Design

Synchronous Latches
To make the latch work synchronously (SET or RESET is only evaluated during the rising edge of the clock), we add NAND gates to the inputs S and R.
S Q S Q
Synchronous RS Latch`
CLK
Q R
CLK S Q
CLK
R Q
16
Verilog Design
Flip-Flops from Synchronous Latches

A Flip-Flop is a latch that synchronizes the input. The most common type of Flip-Flop used in ASIC design is the Data Flip-Flop.
D
CLK
D Q
S
CLK R
17 17
Verilog Design

Timing for Flip-Flops
There are three variations of flip-flop latch timing available: Level Triggered: Flip can only change state when the clock input is at a specific logic level. Positive-Edge Triggered: Flip flop changes state on the rising (leading) edge of the clock. Negative-Edge Triggered: Flip flop changes state on the falling (trailing) edge of the clock.
CLK
CLK Positive Edge-Triggered
CLK
Level Triggered
Negative Edge-Triggered
18
Verilog Design
Timing Diagrams for Flip-Flops

CLK
D
QLEVEL
Q+EDGE
Q-EDGE
Note: For the majority of this course (and in most digital designs in the real world) we will be using Positive-Edge Triggered DFFs.
Verilog Design

Timing for Flip-Flops
Different triggering types are indicated by different symbols on the clock input.
D CLK
D CLK
D CLK
Q Level Triggered
Q Positive Edge-Triggered
Q Negative Edge-Triggered
20
Verilog Design
Setup and Hold Timing for Flip-Flops...

TSU
CLK D Q+EDGE

TH
TSU Setup Time This is the period of time BEFORE the clock transition that the input signal must remain stable at in order to be flopped correctly. TH Hold Time This is the period of time AFTER the clock transition that the input signal must remain stable at in order to be flopped correctly.
Verilog Design
What does this really mean?

D
Logic Cloud Q
Setup Period
Hold Period
CLK
D
TSU
TH
22
Verilog Design
Setup/Hold Timing Understanding Check

Which of the following signal are invalid?
IN3
IN2 IN1
Clk
su
23
Verilog Design
Basic Structure of a HDL Design

Sequential / Synchronous Logic
Asynchronous / Combinational Logic
INPUTS
Logic Cloud
OUTPUTS
DFF
CLK
DFF
Q CLK Q
24
Verilog Design
TTL Discrete Components (Quad AND)

module SN74LS08 (input wire A0, input wire B0, output wire C0, input wire A1, input wire B1, output wire C1, input wire A2, input wire B2, output wire C2, input wire A3, input wire B3, output wire C3);
assign assign assign assign

C0 C1 C2 C0
= = = =
(A0 (A1 (A2 (A0
& & & &
B0); B1); B2); B0);

25
endmodule
Verilog Design
TTL Discrete Components (Dual DFF)

VCC and GND are handled outside of the HDL Standard
module SN74AC7 (input wire input wire input wire input wire output reg output wire input wire input wire input wire input wire output reg output wire CLR1_B, D1, CLK1, PRE1_B, Q1, Q1_B, CLR2_B. D2, CLK2, PRE_B, Q2, Q2_B);
14
CLR1 D1 CLK1 PRE1 Q1 Q1 GND

7
VCC CLR2 D2 CLK2 PRE2 Q2 Q2

8
SN74AC74
assign Q1_B <= ~Q1; assign Q2_B <= ~Q2; always@(posedge CLK1, if (~CLR1_B) else if (~PRE1_B) else always@(posedge CLK2, if (~CLR2_B) else if (~PRE2_B) else negedge CLR1_B) Q1 <= 1'b0; Q1 <= 1'b1; Q1 <= D1; negedge CLR2_B) Q2 <= 1'b0; Q2 <= 1'b1; Q2 <= D2;
endmodule
26
Verilog Design

TTL Based Edge Detect
1CLR 1D 1CLK 1PRE 1Q 1Q GND

SN74AC74
A0 B0 C0 A1 B1 C1 GND
SW1
SW2
SW3
SW4
7 8
&
& &
LS7408N
&
14
14
VCC 2CLR 2D 2CLK 2PRE 2Q 2Q
VCC A2 B2 C2 A3 B3 C3
LED1
LED2
LED3
27
Verilog Design
TTL Based Edge Detect Module Definition

edge_detect CLK RESET_B
module edge_detect (input wire CLK, input wire RESET_B, input wire LONG_SIG, output wire SHORT_SIG); ... ... endmodule
SW1 LED1
SW1
SW2
SW3
SW4
LED1
LED2
LED3
28
Verilog Design

Connect Everything Up
module edge_detect (input wire CLK, input wire RESET_B, input wire LONG_SIG, output wire SHORT_SIG); SN74AC74 I_DFF_2 // Name Based Connectivity (.CLR1_B (RESET_B), .D1 (LED1), .CLK1 (CLK), .PRE1_B (1b1), .Q ( ), .Q1_B (my_sig), .CLR2_B (RESET_B), .D2 (1b0), .CLK2 (CLK), .PRE2_B (1b1), .Q2 (nc), .Q2_B ( )); SN74LS08 I_AND // Position Based Connectivity (LONG_SIG, my_sig , SHORT_SIG, /* NC */, /* NC */, /* NC */ , /* NC */, /* NC */, /* NC */, /* NC */, /* NC */, /* NC */);
1CLR 1D 1CLK 1PRE 1Q 1Q GND

SN74AC74
A0 B0 C0 A1 B1 C1 GND
7 8
&
& &
14
LS7408N
&
14 8
VCC 2CLR 2D 2CLK 2PRE 2Q 2Q
VCC A2 B2 C2 A3 B3 C3
endmodule
29
Verilog Design

TTL Discrete Components (Voltage Levels)
BACKUP
30

Verilog - 00 (Design) Basics of Digital Design (v01!26!2013)

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Verilog Design

Digital Design & Synthesis

Basics of Digital Design

Digital Design & Synthesis

Review of Logic Gates [AND]

Basics of Digital Design

Analogies taken from P. Scherz

Digital Design & Synthesis

Review of Logic Gates [OR]

Basics of Digital Design

A 10K B out 10K

Analogies taken from P. Scherz

Digital Design & Synthesis

Review of Logic Gates [NOT]

Basics of Digital Design

10K out 10K

Analogies taken from P. Scherz

Digital Design & Synthesis

Review of Logic Gates [NAND & NOR]

Basics of Digital Design

NOR Gate = NOT(OR)

Digital Design & Synthesis

Review of Logic Gates [XOR]

Basics of Digital Design

(1) (1) (0) (0)

(0) (1) (1) (0)

Digital Design & Synthesis

Boolean Expressions and Math

Basics of Digital Design

Digital Design & Synthesis

What if we only use NANDs or NORs

Basics of Digital Design

Digital Design & Synthesis

Basics of Digital Design

D) Minimized output equations

z = a'b'c + a'bc' + ab'c + abc' + abc

Digital Design & Synthesis

Review of Storage Elements [Latch]

Basics of Digital Design

S R F (0) F (0) F (0) T (1) T (1) F (0) T (1) T (1)

Q Q F (0) T (1) INVALID

Q Next State of the Latch Q Present State of the Latch

Digital Design & Synthesis

Review of Storage Elements [Latch...]

Basics of Digital Design

Digital Design & Synthesis

Review of Storage Elements [Latch...]

Basics of Digital Design

Digital Design & Synthesis

Review of Storage Elements [Latch...]

Basics of Digital Design

Digital Design & Synthesis

Review of Storage Elements [Latch...]

Basics of Digital Design

Digital Design & Synthesis

Basics of Digital Design

Rising Edge of Clock

Time Clock Period High Level of Clock

Low Level of Clock

Digital Design & Synthesis

Basics of Digital Design

Digital Design & Synthesis

Flip-Flops from Synchronous Latches