5

See 'TEXT' in 0MEMO or 1MEMO property in component

Bolsena-E(AB2) Block Diagram

Dummy when use '10/100'

Dummy when use 'GIGA'

200-PIN DDR SODIMM

Dummy when use 'UMA'

CLK GEN
IDT CV1373

Dummy when use 'DIS'

D

AMD CPU

Dummy when use 'IDE'

HyperTransport
6.4GB/S 16b/8b

tv

LVDS

ATI

1* Slot Cardbus

AGTL+ CPU I/F + UMA

25

MS/MS Pro/xD/
MMC/SD 5 in 1 28

1394
CONN

28

PCI Express x16

11,12,13,14

ATI
M52P

RGB CRT

ATI
PCI

BlueTooth
miniUSB

ACPI 2.0

6xUSB 2.0

23

USB x 4
24

CODEC
ALC883

AZALIA
AZALIA
1000Mb

31

TXFM
31

10/100Mb

15

VRAM x4

SB450

PCI Bus / 33MHz

TXFM

Power Block Diag -> Page 40

54,55

27,28

31

CRT

16

PCI-Express
x2

29

LCD

49,50,51,52,53

RICOH
R5C832
1394
CardReader

Mini-PCI
802.11a/b/g

RJ45

16

RS482M

L1: Signal 1
L2:VCC
L3: Signal 2
L4: Signal 3
L5: GND
L6: Signal 4

CB1410

PCMCIA I/F

26

PCB Layer Stackup

4,5,6,7

ENE

26

DDR x2
8,9,10

16
LEDs
RTC BAT. 17
BUTTONs 33

PWR SW
CP2211

DDR 333/400

35W/25W

Dummy when use 'SATA'

PCMCIA
SLOT
Support
TypeII

Project Code: 91.4G401.001

REVISION: 05236-SA

PCI LAN
Realtek
RTL8110SBL
1000/100/10
RTL8100C
100/10
30

MODEM
MDC Card

RJ11
CONN

23

OP AMP
G1421

31

Line In 3
MIC In

32

Line Out33
33

Int. SPKR33
B

LPC I/F

24

NS SIO
PC87381

SIDE

SATA

17,18,19,20,21

PIDE

ATA 133

LPC Bus / 33MHz

HDD

DVD/
CD-RW

24

Thermal
& Fan
G792 23

37

XBUS

KBC
KB3910
34

24

Touch
Pad

FIR
TFDU6102

35

37

Int.
KB

ISA ROM
36

35

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

BLOCK DIAGRAM
Size
A3

Document Number

Rev
SA

Bolsena-E

Date: Thursday, October 13, 2005

Sheet

1
1

of

58

PCI Routing
IDSEL
MiniPCI

21

LAN
7411

IRQ

REQ/GNT

23

22

E (CardBus)

7411

17

G (1394)

7411

17

E (FlashMedia)

www.kythuatvitinh.com
B

Ref. function
schematic
------------------------U81 cpu socket
62.10055.121
U80 north bridge 71.RS482.M03
U43 south bridge 71.SB400.B0U
U32 clock gen.
71.00137.C0W
--U70
U64
U65
U69
U71

VGA M52
VRAM FOR
VRAM FOR
VRAM FOR
VRAM FOR

BOM
(DON'T CHANGE) (3mm high)
71.RS482.M03 (ver A12)
71.SB400.D0U (ver A13)
71.00137.C0W

71.0M52P.A0U
M52
M52
M52
M52

--U66 BIOS SOCKET 72.39040.G03 62.10002.032

U66 BIOS IC
72.39040.G03 72.39040.H03
--U75 GIGA LAN 71.08110.00G 71.08110.A0G
U75 10/100 LAN 71.08110.00G 71.08100.C0G

(NO NEED WHEN PD)

(DIP STAGE IN LAB, SMT IN PD)

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

HISTORY
Size
A3

Document Number

Rev

SA

Bolsena-E

Date: Thursday, October 13, 2005

Sheet
1

of

58

3D3V_S0

C496
SC10U10V5ZY-1GP

C487
SCD1U16V2ZY-2GP

C490
C476
C443
C445
C444
SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SC10U10V5ZY-1GP

L15 2
1
0R0603-PAD

3D3V_CLK_VDDA

1
2

3D3V_CLK_VDD

L13 2
1
0R0603-PAD

3D3V_S0

RN53

3D3V_CLK_VDD
U23

C485
C486
C489
C488 3D3V_S0
SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2

3D3VDD48_S0
1

L14 2
1
0R0603-PAD

C446
SC2D2U16V5ZY-GP

XI_CLK
2 C459
SC33P50V2JN-3GP

R223
DUMMY-R3

X2
X-14D318MHZ-18GP

20 CLK48_USB
8,20 SMBD_SB
8,20 SMBC_SB

RN48

2
1

USB_48M
SMBC_CLK
SMBD_CLK

XO_CLK
2 C472
SC33P50V2JN-3GP

3 SRN33J-5-GP-U
4

SBLINK_CLK# 13
SBLINK_CLK 13

1
2

4 RN47
3
SRN33J-5-GP-U

SBSRC_CLK# 17
SBSRC_CLK 17

3D3V_CLK_VDDA

2
1

R218 2 22R2J-2-GP

3
4
SRN33J-5-GP-U

3
39
32

VDD_48
VDDA
VDD_SRC

21
14
35

VDD_SRC
VDD_SRC
VDD_SRC

56
51
43
48

VDD_REF
VDD_PC1
VDD_CPU
VDD_HTT

1
2

XIN
XOUT

4
7
8

USB_48
SCL
SDA

10
11

CLKREQ0#
CLKREQ1#

9
53
54

SEL24/24_48#
REF1
REF0

52

REF2

SRCC0
SRCT0
SRCC3
SRCT3
SRCC4
SRCT4
SRCC5
SRCT5
SRCC6
SRCT6
SRCC7
SRCT7

33
34
25
24
23
22
19
18
17
16
13
12

CPUC1
CPUT1
CPUC0
CPUT0

40
41
44
45

SRC_CLK0#
SRC_CLK0
SRC_CLK3#
SRC_CLK3

CPUCLKJ_CY
CPUCLK_CY

R247 2 15R2J-L1-GP
R248 2 15R2J-L1-GP

1
1

CPUCLK# 6
CPUCLK 6

RN52
SRCC1
SRCT1
SRCC2
SRCT2

29
30
28
27

VSS_SRC
VSS_SRC
RESET#
TURBO1

36
20
15
26

VSS_CPU
VSS_PCI
VSS_HTT
VSS_SRC
VSSA
VSS_48
VSS_REF

42
49
46
31
38
5
55

ATI_CLK0#
ATI_CLK0
ATI_CLK1#
ATI_CLK1

2
1

3
4

NBSRC_CLK# 13
NBSRC_CLK 13

SRN33J-5-GP-U
RN46

13 CLK14_NB
20 SB_OSC_CLK

2
1

RN54

FS2
FS1
3
FS0
4
SRN33J-5-GP-U
R242 2 33R2J-2-GP

1
2

4
3

GFX_CLK# 49
GFX_CLK 49

SRN33J-5-GP-U

www.kythuatvitinh.com
37 CLK14_SIO
13
HTREF_CLK

2
R241 75R2F-2-GP

CLK_HTT66 47
50

R249
100R2F-L1-GP-U

37

HTT66
PCI0
IREF

IREF_CLKGEN

R240
475R2F-L1-GP

NC#6

Dummy when use UMA

IDTCV137PAG-2-GP
71.00137.C0W

SBLINK_CLK
SBLINK_CLK#

2
1

SBSRC_CLK#
SBSRC_CLK

2
1

GFX_CLK#
GFX_CLK

1
2

RN58

SRN49D9F-GP
3
4

RN38

SRN49D9F-GP
3
4

RN37

SRN49D9F-GP
4
3

Dummy when use UMA

RN57
NBSRC_CLK#
NBSRC_CLK

2
1

SRN49D9F-GP
3
4

3D3V_CLK_VDD

DY

R245 2
2K2R2J-2-GP
1
2
DUMMY-R2
R246

FS0

R243 2
DY
2K2R2J-2-GP
2
DUMMY-R2
R244

FS1

1
1
1

1 R216
1

2
DY
2K2R2J-2-GP
2
DUMMY-R2
R217
for ICS

<Variant Name>

FS2

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CLKGEN_IDTCV137
Size
A3

Document Number

Rev

SA

Bolsena-E

Date: Thursday, October 13, 2005

Sheet
E

of

58

HTT for CPU sideA

Transmit power
and NB sideA Receive
power

C269
SCD22U16V3ZY-GP

VLDT0_A
VLDT0_A
VLDT0_A
VLDT0_A
VLDT0_A
VLDT0_A
VLDT0_A

VLDT0_B
VLDT0_B
VLDT0_B
VLDT0_B
VLDT0_B
VLDT0_B
VLDT0_B

AH29
AH27
AG28
AG26
AF29
AE28
AF25

LAYOUT: Place bypass cap on topside of board near

HTT power pins that are not connected directly to
HTT device, but connected internally to
other HTT power pins.

D29
D27
D25
C28
C26
B29
B27

1D2V_HT0B_S0

C273
SCD22U16V3ZY-GP

C268
SCD22U16V3ZY-GP

U62A

1
C289
SCD22U16V3ZY-GP

1D2V_S0

HTT for CPU sideB

Receive power
and NB sideA
Transmit power

C267
downstream
SC4D7U10V5ZY-3GP

www.kythuatvitinh.com
NB0CADOUT15
NB0CADOUTJ15
NB0CADOUT14
NB0CADOUTJ14
NB0CADOUT13
NB0CADOUTJ13
NB0CADOUT12
NB0CADOUTJ12
NB0CADOUT11
NB0CADOUTJ11
NB0CADOUT10
NB0CADOUTJ10
NB0CADOUT9
NB0CADOUTJ9
NB0CADOUT8
NB0CADOUTJ8
NB0CADOUT7
NB0CADOUTJ7
NB0CADOUT6
NB0CADOUTJ6
NB0CADOUT5
NB0CADOUTJ5
NB0CADOUT4
NB0CADOUTJ4
NB0CADOUT3
NB0CADOUTJ3
NB0CADOUT2
NB0CADOUTJ2
NB0CADOUT1
NB0CADOUTJ1
NB0CADOUT0
NB0CADOUTJ0

11 NB0CADOUT[15..0]
11 NB0CADOUTJ[15..0]

Used SideB Power Plane

1D2V_HT0B_S0

11
11
11
11

NB0HTTCLKOUT1
NB0HTTCLKOUTJ1
NB0HTTCLKOUT0
NB0HTTCLKOUTJ0

NB0HTTCLKOUT1
NB0HTTCLKOUTJ1
NB0HTTCLKOUT0
NB0HTTCLKOUTJ0
1
1

R141 2 49D9R2F-GPCPUHTTCTLIN1
R140 2 49D9R2F-GPCPUHTTCTLINJ1
NB0HTTCTLOUT
NB0HTTCTLOUTJ

11 NB0HTTCTLOUT
11 NB0HTTCTLOUTJ

T25
R25
U27
U26
V25
U25
W27
W26
AA27
AA26
AB25
AA25
AC27
AC26
AD25
AC25
T27
T28
V29
U29
V27
V28
Y29
W29
AB29
AA29
AB27
AB28
AD29
AC29
AD27
AD28

L0_CADIN_H15
L0_CADIN_L15
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H0
L0_CADIN_L0

L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0

N26
N27
L25
M25
L26
L27
J25
K25
G25
H25
G26
G27
E25
F25
E26
E27
N29
P29
M28
M27
L29
M29
K28
K27
H28
H27
G29
H29
F28
F27
E29
F29

CPUCADOUT15
CPUCADOUTJ15
CPUCADOUT14
CPUCADOUTJ14
CPUCADOUT13
CPUCADOUTJ13
CPUCADOUT12
CPUCADOUTJ12
CPUCADOUT11
CPUCADOUTJ11
CPUCADOUT10
CPUCADOUTJ10
CPUCADOUT9
CPUCADOUTJ9
CPUCADOUT8
CPUCADOUTJ8
CPUCADOUT7
CPUCADOUTJ7
CPUCADOUT6
CPUCADOUTJ6
CPUCADOUT5
CPUCADOUTJ5
CPUCADOUT4
CPUCADOUTJ4
CPUCADOUT3
CPUCADOUTJ3
CPUCADOUT2
CPUCADOUTJ2
CPUCADOUT1
CPUCADOUTJ1
CPUCADOUT0
CPUCADOUTJ0

CPUCADOUT[15..0] 11
CPUCADOUTJ[15..0] 11

Used SideA Power Plane

Y25
W25
Y27
Y28

L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKIN_H0
L0_CLKIN_L0

L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0

J26
J27
J29
K29

CPUHTTCLKOUT1
CPUHTTCLKOUTJ1
CPUHTTCLKOUT0
CPUHTTCLKOUTJ0

CPUHTTCLKOUT1 11
CPUHTTCLKOUTJ1 11
CPUHTTCLKOUT0 11
CPUHTTCLKOUTJ0 11

R27
R26
T29
R29

L0_CTLIN_H1
L0_CTLIN_L1
L0_CTLIN_H0
L0_CTLIN_L0

L0_CTLOUT_H1
L0_CTLOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0

N25
P25
P28
P27

CPUHTTCTLOUT0
CPUHTTCTLOUTJ0

CPUHTTCTLOUT0 11
CPUHTTCTLOUTJ0 11

62.10055.121

ME : 62.10055.121
2nd:62.10055.101
<Variant Name>

Digitally signed by fdsf

Wistron Corporation
DN: cn=fdsf, o=fsdfsd,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
ou=ffsdf,
Title
email=fdfsd@fsdff,
CPU(1/4)_HyperTransport I/F
Size
Document Number
Rev
c=US
A3
SA
Bolsena-E
Date:
Sheet
Thursday,
October
13,
2005
4
58
of
Date: 2010.02.16
D

VREF_DDR_MEM
NOTE: Test with passive probes only.

1D25V_S3
U62B

VTT_SENSE

2D5V_S3

VREF_DDR_CLAW

R222
C470
100R2F-L1-GP-USCD1U25V3ZY-3GP

AG12
1 R169
1 R163

2 34D8R2F-N1-GP
2 34D8R2F-N1-GP

MEMZN
MEMZP

D14
C14

MEMZN
MEMZP

D17
A18
B17
C17
AF16
AG16
AH16
AJ17

MEMRESET_L

AG10

MEMRESET#

AE8
AE7

M_CKE#0
M_CKE#1

M_CKE#0 8,9
M_CKE#1 8,9

D10
C10
E12
E11
AF8
AG8
AF10
AE10
V3
V4
K5
K4
R5
P5
P3
P4

M_CLK7
M_CLK#7
M_CLK6
M_CLK#6
M_CLK5
M_CLK#5
M_CLK4
M_CLK#4

M_CLK7 8
M_CLK#7 8
M_CLK6 8
M_CLK#6 8
M_CLK5 8
M_CLK#5 8
M_CLK4 8
M_CLK#4 8

MEMCS_L7
MEMCS_L6
MEMCS_L5
MEMCS_L4
MEMCS_L3
MEMCS_L2
MEMCS_L1
MEMCS_L0

D8
C8
E8
E7
D6
E6
C4
E5

M_CS#7
M_CS#6
M_CS#5
M_CS#4
M_CS#3
M_CS#2
M_CS#1
M_CS#0

M_CS#3
M_CS#2
M_CS#1
M_CS#0

MEMRASA_L
MEMCASA_L
MEMWEA_L

H5
D4
G5

M_ARAS#
M_ACAS#
M_AWE#

M_ARAS# 8,9
M_ACAS# 8,9
M_AWE# 8,9

MEMBANKA1
MEMBANKA0

K3
H3

M_ABS#1
M_ABS#0

M_ABS#1 8,9
M_ABS#0 8,9

NC_E13
NC_C12
MEMADDA13
MEMADDA12
MEMADDA11
MEMADDA10
MEMADDA9
MEMADDA8
MEMADDA7
MEMADDA6
MEMADDA5
MEMADDA4
MEMADDA3
MEMADDA2
MEMADDA1
MEMADDA0

E13
C12
E10
AE6
AF3
M5
AE5
AB5
AD3
Y5
AB4
Y3
V5
T5
T3
N5

RSVD_M_AA15
RSVD_M_AA14
M_AA13
M_AA12
M_AA11
M_AA10
M_AA9
M_AA8
M_AA7
M_AA6
M_AA5
M_AA4
M_AA3
M_AA2
M_AA1
M_AA0

MEMRASB_L
MEMCASB_L
MEMWEB_L

H4
F5
F4

M_BRAS#
M_BCAS#
M_BWE#

M_BRAS# 8,9
M_BCAS# 8,9
M_BWE# 8,9

MEMBANKB1
MEMBANKB0

L5
J5

M_BBS#1
M_BBS#0

M_BBS#1 8,9
M_BBS#0 8,9

NC_E14
NC_D12
MEMADDB13
MEMADDB12
MEMADDB11
MEMADDB10
MEMADDB9
MEMADDB8
MEMADDB7
MEMADDB6
MEMADDB5
MEMADDB4
MEMADDB3
MEMADDB2
MEMADDB1
MEMADDB0

E14
D12
E9
AF6
AF4
M4
AD5
AC5
AD4
AA5
AB3
Y4
W5
U5
T4
M3

RSVD_M_BA15
RSVD_M_BA14
M_BA13
M_BA12
M_BA11
M_BA10
M_BA9
M_BA8
M_BA7
M_BA6
M_BA5
M_BA4
M_BA3
M_BA2
M_BA1
M_BA0

MEMCHECK7
MEMCHECK6
MEMCHECK5
MEMCHECK4
MEMCHECK3
MEMCHECK2
MEMCHECK1
MEMCHECK0

N3
N1
U3
V1
N2
P1
U1
U2

LAYOUT: Locate close to DIMMs.

NOTE: Remove to bypass op-amp

3

MEMCKEA
MEMCKEB

9 M_DATA[63..0]

C474
C473
SCD1U25V3ZY-3GP
SC1000P50V2JN-N1

R229
100R2F-L1-GP-U

VREF_DDR_MEM

MEMVREF1

VTT_A
VTT_A
VTT_A
VTT_A
VTT_B
VTT_B
VTT_B
VTT_B

VREF_DDR_CLAW

M_DATA63
M_DATA62
M_DATA61
M_DATA60
M_DATA59
M_DATA58
M_DATA57
M_DATA56
M_DATA55
M_DATA54
M_DATA53
M_DATA52
M_DATA51
M_DATA50
M_DATA49
M_DATA48
M_DATA47
M_DATA46
M_DATA45
M_DATA44
M_DATA43
M_DATA42
M_DATA41
M_DATA40
M_DATA39
M_DATA38
M_DATA37
M_DATA36
M_DATA35
M_DATA34
M_DATA33
M_DATA32
M_DATA31
M_DATA30
M_DATA29
M_DATA28
M_DATA27
M_DATA26
M_DATA25
M_DATA24
M_DATA23
M_DATA22
M_DATA21
M_DATA20
M_DATA19
M_DATA18
M_DATA17
M_DATA16
M_DATA15
M_DATA14
M_DATA13
M_DATA12
M_DATA11
M_DATA10
M_DATA9
M_DATA8
M_DATA7
M_DATA6
M_DATA5
M_DATA4
M_DATA3
M_DATA2
M_DATA1
M_DATA0

A16
B15
A12
B11
A17
A15
C13
A11
A10
B9
C7
A6
C11
A9
A5
B5
C5
A4
E2
E1
A3
B3
E3
F1
G2
G1
L3
L1
G3
J2
L2
M1
W1
W3
AC1
AC3
W2
Y1
AC2
AD1
AE1
AE3
AG3
AJ4
AE2
AF1
AH3
AJ3
AJ5
AJ6
AJ7
AH9
AG5
AH5
AJ9
AJ10
AH11
AJ11
AH15
AJ15
AG11
AJ12
AJ14
AJ16

MEMDATA63
MEMDATA62
MEMDATA61
MEMDATA60
MEMDATA59
MEMDATA58
MEMDATA57
MEMDATA56
MEMDATA55
MEMDATA54
MEMDATA53
MEMDATA52
MEMDATA51
MEMDATA50
MEMDATA49
MEMDATA48
MEMDATA47
MEMDATA46
MEMDATA45
MEMDATA44
MEMDATA43
MEMDATA42
MEMDATA41
MEMDATA40
MEMDATA39
MEMDATA38
MEMDATA37
MEMDATA36
MEMDATA35
MEMDATA34
MEMDATA33
MEMDATA32
MEMDATA31
MEMDATA30
MEMDATA29
MEMDATA28
MEMDATA27
MEMDATA26
MEMDATA25
MEMDATA24
MEMDATA23
MEMDATA22
MEMDATA21
MEMDATA20
MEMDATA19
MEMDATA18
MEMDATA17
MEMDATA16
MEMDATA15
MEMDATA14
MEMDATA13
MEMDATA12
MEMDATA11
MEMDATA10
MEMDATA9
MEMDATA8
MEMDATA7
MEMDATA6
MEMDATA5
MEMDATA4
MEMDATA3
MEMDATA2
MEMDATA1
MEMDATA0

M_ADM8
M_ADM7
M_ADM6
M_ADM5
M_ADM4
M_ADM3
M_ADM2
M_ADM1
M_ADM0
M_DQS8
M_DQS7
M_DQS6
M_DQS5
M_DQS4
M_DQS3
M_DQS2
M_DQS1
M_DQS0

R1
A13
A7
C2
H1
AA1
AG1
AH7
AH13
T1
A14
A8
D1
J1
AB1
AJ2
AJ8
AJ13

MEMDQS17
MEMDQS16
MEMDQS15
MEMDQS14
MEMDQS13
MEMDQS12
MEMDQS11
MEMDQS10
MEMDQS9
MEMDQS8
MEMDQS7
MEMDQS6
MEMDQS5
MEMDQS4
MEMDQS3
MEMDQS2
MEMDQS1
MEMDQS0

MEMCLK_H7
MEMCLK_L7
MEMCLK_H6
MEMCLK_L6
MEMCLK_H5
MEMCLK_L5
MEMCLK_H4
MEMCLK_L4
MEMCLK_H3
MEMCLK_L3
MEMCLK_H2
MEMCLK_L2
MEMCLK_H1
MEMCLK_L1
MEMCLK_H0
MEMCLK_L0

DDRVTT_SENSE AE13
4

C320
C309
SCD1U25V3ZY-3GP
SC1000P50V2JN-N1
2

TP44

TPAD30

NOTE: Install to bypass op-amp

2D5V_S3

For REGISTED DIMM Only

UNBUFFER DIMM NC

2D5V_S3
RN29

M_CLK#1
M_CLK#0
M_CLK1
M_CLK0

M_CLK1
M_CLK#1
M_CLK0
M_CLK#0

8
7
6
5

1
2
3
4
SRN10KJ-6-GP
3

www.kythuatvitinh.com
1

2D5V_S3

VREF_DDR_CLAW

C338
C349
SCD1U25V3ZY-3GP
SC1000P50V2JN-N1
2

R162
100R2F-L1-GP-U

R166
C348
100R2F-L1-GP-USCD1U25V3ZY-3GP

LAYOUT: Locate close to CPU.

Place it near CPU

R173

1 R168

2
121R2F-GP

M_CLK7
M_CLK#7

2
121R2F-GP

M_CLK6
M_CLK#6
9

R172

2
121R2F-GP

M_CLK5
M_CLK#5

R167

2
121R2F-GP

M_CLK4
M_CLK#4

M_ADM[7..0]

M_DQS[7..0]

8,9
8,9
8,9
8,9

M_AA[13..0] 8,9

AMD suggested M_AA13

connect to DIMM pin123

M_DQS8
M_ADM8

MEMRESET#
M_CS#7
M_CS#6
M_CS#5
M_CS#4
RSVD_M_AA15
RSVD_M_AA14
RSVD_M_BA15
RSVD_M_BA14

M_BA[13..0] 8,9

TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30

NOT SUPPORT ECC CHECK

AMD suggested remove
<Variant
Name>
PULL-HI
resistor.

CB7
CB6
CB5
CB4
CB3
CB2
CB1
CB0

TP58 TPAD30
TP117TPAD30
TP57 TPAD30
TP110TPAD30
TP116TPAD30
TP115TPAD30
TP111TPAD30
TP112TPAD30

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CPU(2/4)_DDR
Document Number

Rev

SA

Bolsena-E

Date: Thursday, October 13, 2005

B

TP50
TP53
TP56
TP54
TP55
TP46
TP48
TP41
TP47

AMD suggested M_BA13

connect to DIMM pin123

Size
A3
A

TP113TPAD30
TP114TPAD30

Sheet
E

of

58

2D5V_CPUA_S0

DY

G913CF-GP

DY

L0_REF1
L0_REF0

differentially impedance 100

CPUCLK

COREFB
COREFB#

VDDA1
VDDA2

AF20
AE18
AJ27

RESET_L
PWROK
LDTSTOP_L

AF27
AE26

L0_REF1
L0_REF0

COREFB
COREFB#
CORE_SENSE

A23
A24
B23

COREFB_H
COREFB_L
CORE_SENSE

VDDIOFB
VDDIOFBJ
VDDIOSENSE

AE12
AF12
AE11

VDDIOFB_H
VDDIOFB_L
VDDIO_SENSE

AJ21
AH21

CLKIN_H
CLKIN_L

CLKIN
2 C803
SC3900P50V3KX-GP
R519
169R2F-GP

THERMTRIP_L

A20

THERMDA
THERMDC

A26
A27

THERMTRIP#

VID4
VID3
VID2
VID1
VID0

AG13
AF14
AG14
AF15
AE15

VID4
VID3
VID2
VID1
VID0

NC_AG18
NC_AH18
NC_AG17
NC_AJ18

AG18
AH18
AG17
AJ18

NC_AG18
NC_AH18
NC_AG17
NC_AJ18

THERMDP 22
THERMDN 22
VID[4..0] 41

TP40 TPAD30
TP39 TPAD30

LAYOUT: Route FBCLKOUT_H/L

differentially impedance 80

FBCLKOUT

1
2

AMD suggest voltege

from 2D5V_S0 to 2D5V_S3

SANYO, NT$:6.1
Iripple=1.1A,ESR=70mohm
3.5/2.8/2.0
77.21071.031

41
C257
41
SC1000P50V2JN-N1

C256
SC1000P50V2JN-N1

DY

U62C

C288
C287
17 LDT_RST#
SC3300P50V2KX-1GPSCD22U16V3ZY-GP
17 SB_CPUPWRGD
13,17 LDT_STP#

2 44D2R2F-L1-GP
2 44D2R2F-L1-GP

KEMET,NT:5.7, B2 size
ST100U4VBM-1 (80.10716.321)
Iripple=1.1A,ESR=70mohm

C768
SC1U10V3KX-3GP

AH25
AJ25

1 R133
1 R134

AMD SUGGEST TO USE 2D5V_CPUA_S0

R129
20KR2F-L-GP
R2

DY

C286
SC4D7U10V5ZY-3GP
1D2V_HT0B_S0

Vout = 1.25*(1+ R1/R2)

C242
SC1U10V3KX-3GP

TC8
ST100U4VBM-U

DY

LAYOUT: Route VDDA trace approx.

50 mils wide (use 2x25 mil traces to
exit ball field) and 500 mils long.

1 R143
2
0R0805-PAD

R136 2
0R3J-3-GP

LAYOUT: Route trace 50 mils wide and

500 to 750 mils long between these
caps.

2D5V_VDDA_S0

2D5V_CPUA_S0

SET
OUT

DY

C262
SC10U10V5ZY-1GP

2D5V_CPUR_S0

SHDN#
GND
IN

2D5V_VDDA_VREF

1
2
3

U57

DY

R509
R1
20KR2F-L-GP
C767
SC22P50V2JN-4GP

Iomax=120mA

AMD SUGGEST TO USE 100 ~ 300UH

1 R139
2
0R0603-PAD

3D3V_S0

2D5V_S0

2D5V_VDDA_S0

www.kythuatvitinh.com
CLKIN#
2 C796
SC3900P50V3KX-GP NC_AJ23
NC_AH23
NC_AE24
1D25V_S3
NC_AF24

2D5V_S0

LDT_RST#
SB_CPUPWRGD
LDT_STP#

R154
R158
R512

1
1
1

DBRDY

2 680R3F-GP
2 680R3F-GP
2 680R3F-GP

2D5V_S0

R120
R119
680R3F-GP 680R3F-GP

SRN680J-GP

DY

NC_C15
TMS
TCK
TRST_L
TDI

NC_C18

C18

NC_C18

NC_A19

A19

NC_A19

DY

DY

1
2
3
4

NC_B19
NC_C19
NC_D20
NC_C21

1
2
3
4

Validation Test Points

LAYOUT: Place close to the CPU.

8
7
6
5
RN25

NC_C15
NC_AE23
NC_AF23
NC_AF22
NC_AF21

SRN680J-GP

TP42
TP33
TP31
TP32
TP38

TPAD30
TPAD30
TPAD30
TPAD30
TPAD30

NC_AE23
NC_AF23
NC_AF22
NC_AF21

C1
J3
R3
AA2
D3
AG2
B18
AH1
AE21
C20
AG4
C6
AG6
AE9
AG9

NC_C1
NC_J3
NC_R3
NC_AA2
NC_D3
NC_AG2
NC_B18
NC_AH1
NC_AE21
NC_C20
NC_AG4
NC_C6
NC_AG6
NC_AE9
NC_AG9

DBREQJ

NC_D20
NC_C21
NC_D18
NC_C19
NC_B19

D20
C21
D18
C19
B19

NC_D20
NC_C21
NC_D18
NC_C19
NC_B19

TDO

A22

TDO

NC_AF18

AF18

2
DUMMY-R3

2D5V_S3

Connect to VDDIO for AMD suggest.

KEY1
KEY0

AE23
AF23
AF22
AF21

AE19

NC_D22
NC_C22

LDT_RST#
CLKIN
CLKIN#
CORE_SENSE
VDDIOFB
VDDIOFBJ
VDDIOSENSE
NC_AE24
NC_AF24

TP37
TP35
TP36
TP34
TP45
TP43
TP51
TP30
TP29

D22
C22

THERMTRIP#Level shift to SB400

2D5V_S0

NC_B13
NC_B7
NC_C3
NC_K1
NC_R2
NC_AA3
NC_F3
NC_C23
NC_AG7
NC_AE22
NC_C24
NC_A25
NC_C9

R152
680R3F-GP

B13
B7
C3
K1
R2
AA3
F3
C23
AG7
AE22
C24
A25
C9

Q7
THERMTRIP#

TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30

CPU_THERMTRIP# 22

MMBT3904-2-GP

NS3 1

NC_AG17
NC_AJ18
NC_D18

RN23 SRN680J-GP
8
7
6
5

R155

DBRDY

E20
E17
B21
A21

2
680R3F-GP

CHANGE FROM 1KR3 TO 680R2 FOR AMD

CHECK LIST

FBCLKOUTJ

DBREQ_L

C15

R520
80D6R2F-L-GP

AH19
AJ19

8
7
6
5
1
2
3
4

RN22

1 R164

VTT_A
VTT_B

FBCLKOUT_H
FBCLKOUT_L

DY

SRN680J-GP
2D5V_S3

C16
AG15

TMS
TCK
TRST_L
TDI

NC_AE23
NC_AF23
NC_AF22
NC_AF21

1
2
3
4

DBREQJ
DBRDY
TCK
TMS
TDI
TRST_L
TDO

NC_AE24
NC_AF24

AH17

DY

8
7
6
5
C234
SCD1U25V3ZY-3GP

1
2

DY

AE24
AF24

A28
AJ28

RN21

NC_AJ23
NC_AH23

NC_C15

R159 2
680R3F-GP
R156 2
680R3F-GP

2D5V_S0

AJ23
AH23

CPUCLK#
820R3-GP
820R3-GP

R157 2
1KR2J-1-GP

SB_CPUPWRGD 17

2
2

1 R518
1 R514

2D5V_S3

C304
SCD1U16V2ZY-2GP

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CPU(3/4)_Control & Debug

Size
A3

Document Number

Rev

SA

Bolsena-E

Date: Thursday, October 13, 2005

Sheet
E

of

58

U62E

U62D

SC10U10V5ZY-1GP

C809
2

SC10U10V5ZY-1GP

LAYOUT: Place on backside of processor.

C828
2

1
2

SC10U10V5ZY-1GP

C323

C339
SC10U10V5ZY-1GP

C821
SCD22U16V3ZY-GP

1
2

C362
SCD22U16V3ZY-GP

10u x 4

C360
2

SCD22U16V3ZY-GP

C813
2

SCD22U16V3ZY-GP

C294

SCD22U16V3ZY-GP

1
C295
2

SCD22U16V3ZY-GP
1

SCD22U16V3ZY-GP
2

C808

10u x 2

DY

DY

2D5V_S3

C827

SC10U10V5ZY-1GP

C814

DY

C818

DY

C819

SC10U10V5ZY-1GP
2

C820

0.22u x 4

VCC_CORE_S0

SCD22U16V3ZY-GP
1

N28
U28
AA28
AE27
R7
U7
W7
K8
M8
P8
T8
V8
Y8
J9
N9
R9
U9
W9
AA9
H10
K10
M10
P10
T10
Y10
AB10
G11
J11
AA11
AC11
H12
K12
Y12
AB12
J13
AA13
AC13
H14
AB26
E28
J28

0.22u x 6

SCD22U16V3ZY-GP

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

LAYOUT: Place in uPGA socket cavity.

VCC_CORE_S0

E4
G4
J4
L4
N4
U4
W4
AA4
AC4
AE4
D5
AF5
F6
H6
K6
M6
P6
T6
V6
Y6
AB6
AD6
D7
G7
J7
AA7
AC7
AF7
F8
H8
AB8
AD8
D9
G9
AC9
AF9
F10
AD10
D11
AF11
F12
AD12
D13
AF13
F14
AD14
F16
AD16
D15
R4

SCD22U16V3ZY-GP
1

VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

L7
AC15
H18
B20
E21
H22
J23
H24
F26
N7
L9
V10
G13
K14
Y14
AB14
G15
J15
AA15
H16
K16
Y16
AB16
G17
J17
AA17
AC17
AE17
F18
K18
Y18
AB18
AD18
AG19
E19
G19
AC19
AA19
J19
F20
H20
K20
M20
P20
T20
V20
Y20
AB20
AD20
G21
J21
L21
N21
R21
U21
W21
AA21
AC21
F22
K22
M22
P22
T22
V22
Y22
AB22
AD22
E23
G23
L23
N23
R23
U23
W23
AA23
AC23
B24
D24
F24
K24
M24
P24
T24
V24
Y24
AB24
AD24
AH24
AE25
K26
P26
V26

2D5V_S3

SC4D7U10V5ZY-3GP

4.7u x 6

SC4D7U10V5ZY-3GP

C396

C398

SC4D7U10V5ZY-3GP

C361

SCD22U16V3ZY-GP

C395
SC4D7U10V5ZY-3GP

SCD22U16V3ZY-GP
2

SCD22U16V3ZY-GP
2

C359

SCD22U16V3ZY-GP
2

SC4D7U10V5ZY-3GP

C319

4.7u x 2

SC4D7U10V5ZY-3GP

SCD22U16V3ZY-GP

0.22u x 2

C310

C326

C325

10u x 1

C350

SC4D7U10V5ZY-3GP

SCD22U16V3ZY-GP
2

1D25V_S3

1D25V_S3

C351

SC4D7U10V5ZY-3GP

C369

C363

C324

C367

C368

SC10U10V5ZY-1GP

C321

SCD22U16V3ZY-GP
2

www.kythuatvitinh.com
VCC_CORE_S0

SCD22U16V3ZY-GP

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

2D5V_S3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VCC_CORE_S0

Y17
K17
H17
F17
E18
AJ26
AE29
AC16
AA16
J16
G16
E16
AH14
AD15
AB15
K15
E15
D16
AE14
AC14
AA14
J14
G14
AF17
AD13
AB13
Y13
K13
H13
F13
AH12
AC12
AA12
G12
B12
AD11
AB11
Y11
K11
H11
F11
AH10
AC10
W10
U10
R10
N10
L10
J10
G10
B10
AD9
Y9
V9
T9
P9
M9
K9
H9
F9
AH8
AC8
W8
U8
R8
N8
L8
J8
G8
B8
AD7
AB7
V7
T7
P7
M7
K7
H7
F7
AH6
AC6
AA6
U6
R6
N6
L6
J6
G6
B6
AH4
B4
AH2
AD2
AB2
Y2
V2
T2
P2
M2
K2
H2
F2
C29
AH28
AF28
AC28
W28
R28
L28

N20
L20
J20
AF19
AD19
AB19
Y19
K19
H19
F19
D19
AC18
AA18
G18
B16
AD17
AB17
H15
F15
G28
D28
B28
C27
AH26
AF26
AD26
Y26
T26
M26
H26
D26
B26
C25
B25
AJ24
AG24
AC24
AA24
W24
U24
R24
N24
J24
G24
E24
AG23
AD23
AB23
Y23
V23
T23
P23
K23
H23
F23
D23
AJ22
AH22
AG22
AC22
AA22
AG29
U22
R22
N22
L22
J22
G22
E22
B22
AG21
AD21
Y21
V21
T21
P21
M21
K21
H21
F21
D21
AJ20
AG20
AE20
AC20
AA20
W20
U20
R20
G20
J18
AE16
Y15
B14
J12
AA10
AB9
AA8
Y7
W6
AF2
D2
AG27
AG25
L24
M23
W22
AB21
AH20
B2

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CPU(4/4)_Power
Size
A3

Document Number

Rev

SA

Bolsena-E

Date: Thursday, October 13, 2005

Sheet
E

of

58

DDR1

M_AA0
M_AA1
M_AA2
M_AA3
M_AA4
M_AA5
M_AA6
M_AA7
M_AA8
M_AA9
M_AA10
M_AA11
M_AA12

112
111
110
109
108
107
106
105
102
101
115
100
99

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10 / AP
A11
A12

M_ABS#0
M_ABS#1

117
116

BA0
BA1

M_DATA_R_0
M_DATA_R_1
M_DATA_R_2
M_DATA_R_3
M_DATA_R_4
M_DATA_R_5
M_DATA_R_6
M_DATA_R_7
M_DATA_R_8
M_DATA_R_9
M_DATA_R_10
M_DATA_R_11
M_DATA_R_12
M_DATA_R_13
M_DATA_R_14
M_DATA_R_15
M_DATA_R_16
M_DATA_R_17
M_DATA_R_18
M_DATA_R_19
M_DATA_R_20
M_DATA_R_21
M_DATA_R_22
M_DATA_R_23
M_DATA_R_24
M_DATA_R_25
M_DATA_R_26
M_DATA_R_27
M_DATA_R_28
M_DATA_R_29
M_DATA_R_30
M_DATA_R_31
M_DATA_R_32
M_DATA_R_33
M_DATA_R_34
M_DATA_R_35
M_DATA_R_36
M_DATA_R_37
M_DATA_R_38
M_DATA_R_39
M_DATA_R_40
M_DATA_R_41
M_DATA_R_42
M_DATA_R_43
M_DATA_R_44
M_DATA_R_45
M_DATA_R_46
M_DATA_R_47
M_DATA_R_48
M_DATA_R_49
M_DATA_R_50
M_DATA_R_51
M_DATA_R_52
M_DATA_R_53
M_DATA_R_54
M_DATA_R_55
M_DATA_R_56
M_DATA_R_57
M_DATA_R_58
M_DATA_R_59
M_DATA_R_60
M_DATA_R_61
M_DATA_R_62
M_DATA_R_63

5
7
13
17
6
8
14
18
19
23
29
31
20
24
30
32
41
43
49
53
42
44
50
54
55
59
65
67
56
60
66
68
127
129
135
139
128
130
136
140
141
145
151
153
142
146
152
154
163
165
171
175
164
166
172
176
177
181
187
189
178
182
188
190

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DDR2
/CS0
/CS1

121
122

CKE0
CKE1

96
95

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8

11
25
47
61
133
147
169
183
77

M_DQS_R0
M_DQS_R1
M_DQS_R2
M_DQS_R3
M_DQS_R4
M_DQS_R5
M_DQS_R6
M_DQS_R7

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8

12
26
48
62
134
148
170
184
78

M_ADM_R0
M_ADM_R1
M_ADM_R2
M_ADM_R3
M_ADM_R4
M_ADM_R5
M_ADM_R6
M_ADM_R7

CK0
/CK0
CK1
/CK1
CK2
/CK2

35
37
160
158
89
91

DDR_CLK0
DDR_CLK#0

SCL
SDA

195
193

SMBC_SB
SMBD_SB

SA0
SA1
SA2

194
196
198

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

9
10
21
22
33
34
36
45
46
57
58
69
70
81
82
92
93
94
113
114
131
132
143
144
155
156
157
167
168
179
180
191
192

3
4
15
16
27
28
38
39
40
51
52
63
64
75
76
87
88
90
103
104
125
126
137
138
149
150
159
161
162
173
174
185
186
202

M_CS#0 5,9
M_CS#1 5,9
M_CKE#0

M_CKE#0 5,9

M_ADM#0
M_ADM#1
M_ADM#2
M_ADM#3
M_ADM#4
M_ADM#5
M_ADM#6
M_ADM#7
M_CLK5 5
M_CLK#5 5
M_CLK7 5
M_CLK#7 5

M_BA0
M_BA1
M_BA2
M_BA3
M_BA4
M_BA5
M_BA6
M_BA7
M_BA8
M_BA9
M_BA10
M_BA11
M_BA12

112
111
110
109
108
107
106
105
102
101
115
100
99

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10 / AP
A11
A12

M_BBS#0
M_BBS#1

117
116

BA0
BA1

M_DATA_R_0
M_DATA_R_1
M_DATA_R_2
M_DATA_R_3
M_DATA_R_4
M_DATA_R_5
M_DATA_R_6
M_DATA_R_7
M_DATA_R_8
M_DATA_R_9
M_DATA_R_10
M_DATA_R_11
M_DATA_R_12
M_DATA_R_13
M_DATA_R_14
M_DATA_R_15
M_DATA_R_16
M_DATA_R_17
M_DATA_R_18
M_DATA_R_19
M_DATA_R_20
M_DATA_R_21
M_DATA_R_22
M_DATA_R_23
M_DATA_R_24
M_DATA_R_25
M_DATA_R_26
M_DATA_R_27
M_DATA_R_28
M_DATA_R_29
M_DATA_R_30
M_DATA_R_31
M_DATA_R_32
M_DATA_R_33
M_DATA_R_34
M_DATA_R_35
M_DATA_R_36
M_DATA_R_37
M_DATA_R_38
M_DATA_R_39
M_DATA_R_40
M_DATA_R_41
M_DATA_R_42
M_DATA_R_43
M_DATA_R_44
M_DATA_R_45
M_DATA_R_46
M_DATA_R_47
M_DATA_R_48
M_DATA_R_49
M_DATA_R_50
M_DATA_R_51
M_DATA_R_52
M_DATA_R_53
M_DATA_R_54
M_DATA_R_55
M_DATA_R_56
M_DATA_R_57
M_DATA_R_58
M_DATA_R_59
M_DATA_R_60
M_DATA_R_61
M_DATA_R_62
M_DATA_R_63

5
7
13
17
6
8
14
18
19
23
29
31
20
24
30
32
41
43
49
53
42
44
50
54
55
59
65
67
56
60
66
68
127
129
135
139
128
130
136
140
141
145
151
153
142
146
152
154
163
165
171
175
164
166
172
176
177
181
187
189
178
182
188
190

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

/CS0
/CS1

121
122

CKE0
CKE1

96
95

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8

11
25
47
61
133
147
169
183
77

M_DQS_R0
M_DQS_R1
M_DQS_R2
M_DQS_R3
M_DQS_R4
M_DQS_R5
M_DQS_R6
M_DQS_R7

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8

12
26
48
62
134
148
170
184
78

M_ADM_R0
M_ADM_R1
M_ADM_R2
M_ADM_R3
M_ADM_R4
M_ADM_R5
M_ADM_R6
M_ADM_R7

CK0
/CK0
CK1
/CK1
CK2
/CK2

35
37
160
158
89
91

SCL
SDA

195
193

SA0
SA1
SA2

194
196
198

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

9
10
21
22
33
34
36
45
46
57
58
69
70
81
82
92
93
94
113
114
131
132
143
144
155
156
157
167
168
179
180
191
192

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

3
4
15
16
27
28
38
39
40
51
52
63
64
75
76
87
88
90
103
104
125
126
137
138
149
150
159
161
162
173
174
185
186

GND

202

M_CS#2 5,9
M_CS#3 5,9
M_CKE#1 5,9

! NOT THIS LIBRARY

M_ADM_R[7..0] 9

M_ADM#0
M_ADM#1
M_ADM#2
M_ADM#3
M_ADM#4
M_ADM#5
M_ADM#6
M_ADM#7

M_DATA_R_[63..0] 9
M_DQS_R[7..0] 9
M_AA[13..0] 5,9
M_ABS#[1..0] 5,9
M_BA[13..0] 5,9

M_CLK4 5
M_CLK#4 5
M_CLK6 5
M_CLK#6 5

DDR_CLK1
DDR_CLK#1

M_BBS#[1..0] 5,9

SMBC_SB 3,20
SMBD_SB 3,20
DM_SA0

R255
2
3D3V_S0
4K7R2J-2-GP

2D5V_S3
3

RN62
DDR_CLK#1
DDR_CLK#0
DDR_CLK1
DDR_CLK0

8
7
6
5

1
2
3
4

www.kythuatvitinh.com
118
120
119

/RAS
/CAS
/WE

VREF_DDR_MEM

1
2
197
199

VREF
VREF
VDDSPD
VDDID
GND

GND

5,9
5,9
5,9

3D3V_S0

TP59 TPAD30
C492
201
SCD1U25V3ZY-3GP
2

C493
SCD1U25V3ZY-3GP

Layout trace 20 mil

71
73
79
83
72
74
80
84

1ST 62.10017.701 - 2ND 62.10017.201

M_BA13

Part Number = 62.10017.701

SKT-SODIMM200-24GP

ME : 62.10017.701
2nd :62.10017.691

5,9
5,9
5,9

M_BRAS#
M_BCAS#
M_BWE#

CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7

85
86
97
98
123
124
200

NC#85
NC#86/(RESET#)
NC#97/A13
NC#98/BA2
NC#123
NC#124
NC#200

118
120
119

/RAS
/CAS
/WE

VREF_DDR_MEM

1
2
197
20 mil
3D3V_S0
199
C516
TP60 TPAD30
SCD1U25V3ZY-3GP
201

Layout trace

M_ARAS#
M_ACAS#
M_AWE#

M_AA13

CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7

C515
SCD1U25V3ZY-3GP

VREF
VREF
VDDSPD
VDDID

NC#85
NC#86/(RESET#)
NC#97/A13
NC#98/BA2
NC#123
NC#124
NC#200

71
73
79
83
72
74
80
84

2D5V_S3

NOT SUPPORT ECC CHECK

AMD suggested pull-low

85
86
97
98
123
124
200

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

GND

SRN10KJ-6-GP

AMD CPU

MD63
SMA11

2D5V_S3

DDR1(Reverse 5.2mm)

DDR2(Reverse 9.2mm)

Pin 199

Pin 1

Pin 200

Pin 2

Pin 199

Pin 1

Pin 200

Pin 2

(Bottom view)
<Variant Name>

Wistron Corporation

62.10017.391
ME : 62.10017.391

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

DDR SO-DIMM SKT

Size
A3

Document Number

Rev

SA

Bolsena-E

Date: Thursday, October 13, 2005

SKT-SODIMM2006U1GP
A

SMA10
SMA0 SMA14
SMA12
MD0

Sheet
E

of

58

PARALLEL TERMINATION
PULL HIGH STUBS < 0.8", PLACE RPs CLOSE TO SECOND DM ( DM2 )
NO EQUAL LENGTH LIMITATION

8
7
6
5
4
3
2
1

M_DATA_R_4
M_DATA_R_5
M_ADM_R0
M_DATA_R_6
M_DATA_R_7
M_DATA_R_13
M_DATA_R_12
M_ADM_R1

9
10
11
12
13
14
15
16

M_DATA37
M_DATA36
M_ADM4
M_DATA39

4
3
2
1

M_DATA32
M_DATA33
M_DQS4
M_DATA34

4
3
2
1

8
7
6
5
4
3
2
1

M_DATA_R_1
M_DATA_R_0
M_DQS_R0
M_DATA_R_2
M_DATA_R_3
M_DATA_R_8
M_DATA_R_9
M_DQS_R1

9
10
11
12
13
14
15
16

M_DATA35
M_DATA41
M_DATA40
M_DQS5
M_DATA42
M_DATA43
M_DATA49
M_DATA48

8
7
6
5
4
3
2
1

M_DATA38
M_DATA45
M_DATA44
M_ADM5
M_DATA47
M_DATA46
M_DATA53
M_DATA52

8
7
6
5
4
3
2
1

SRN10J-3

M_DATA_R_38
M_DATA_R_45
M_DATA_R_44
M_ADM_R5
M_DATA_R_47
M_DATA_R_46
M_DATA_R_53
M_DATA_R_52

9
10
11
12
13
14
15
16

M_DQS_R6
M_DATA_R_50
M_DATA_R_51
M_DATA_R_56
M_DATA_R_57
M_DQS_R7
M_DATA_R_58
M_DATA_R_59

9
10
11
12
13
14
15
16

M_ADM_R6
M_DATA_R_54
M_DATA_R_55
M_DATA_R_61
M_DATA_R_60
M_ADM_R7
M_DATA_R_62
M_DATA_R_63

SRN10J-3
M_DATA_R_11
M_DATA_R_10
M_DATA_R_17
M_DATA_R_16
M_DQS_R2
M_DATA_R_19
M_DATA_R_18
M_DATA_R_25

9
10
11
12
13
14
15
16

M_DQS6
M_DATA50
M_DATA51
M_DATA56
M_DATA57
M_DQS7
M_DATA58
M_DATA59

8
7
6
5
4
3
2
1

8
7
6
5
4
3
2
1

9
10
11
12
13
14
15
16

1D25V_S3

4
3
2
1

5
6
7
8

M_DATA_R_32
M_DATA_R_33
M_DQS_R4
M_DATA_R_35

1
2

4
3

RN56 SRN68J-3-GP
4
3
2
1

RN113

5
6
7
8

M_DATA_R_1
M_DATA_R_0
M_DQS_R0
M_DATA_R_2
M_DATA_R_3
M_DATA_R_8
M_DATA_R_9
M_DQS_R1

8
7
6
5
4
3
2
1

M_DATA_R_36
M_DATA_R_37
M_ADM_R4
M_DATA_R_38

M_BA12
M_BA5

1
2

M_DATA_R_28
M_DATA_R_23
M_DATA_R_22
M_ADM_R2
M_DATA_R_21
M_DATA_R_20
M_DATA_R_15
M_DATA_R_14

8
7
6
5
4
3
2
1

8
7
6
5
4
3
2
1

RN59
SRN68J-4-GP

9
10
11
12
13
14
15
16

M_DATA_R_[63..0] 8

4
3

M_DQS_R[7..0] 8

SRN47J-6-GP
M_AA11
M_AA9
M_AA7
M_AA5
M_AA4
M_AA8
M_AA6
M_AA3

M_DATA_R_48
M_DATA_R_49
M_DATA_R_43
M_DATA_R_42
M_DQS_R5
M_DATA_R_41
M_DATA_R_40
M_DATA_R_34

8
7
6
5
4
3
2
1

M_AA[13..0] 5,8

9
10
11
12
13
14
15
16

M_ABS#[1..0] 5,8
M_BA[13..0] 5,8
M_BBS#[1..0] 5,8
M_AWE# 5,8
M_ACAS# 5,8
M_ARAS# 5,8

RN63SRN47J-4-GP
M_CS#3
M_BCAS#
M_BRAS#
M_BBS#1

4
3
2
1

5
6
7
8

M_BWE# 5,8
M_BCAS# 5,8
M_BRAS# 5,8

RN109

RN66
SRN68J-4-GP

9
10
11
12
13
14
15
16

8
7
6
5
4
3
2
1

9
10
11
12
13
14
15
16

M_DATA_R_39
M_DATA_R_44
M_DATA_R_45
M_ADM_R5
M_DATA_R_46
M_DATA_R_47
M_DATA_R_52
M_DATA_R_53

RN65
1
2

M_AWE#
M_ABS#0

M_CS#0
M_CS#1
M_CS#2
M_CS#3

SRN47J-7-GP
4
3

5,8
5,8
5,8
5,8

RN68
M_BA3
M_BA7

1
2

M_DQS[7..0] 5

RN55

SRN68J-4-GP

9
10
11
12
13
14
15
16

M_ADM[7..0] 5
M_DATA[63..0] 5

RN50
SRN47J-7-GP

RN110SRN68J-3-GP

SRN68J-4-GP

M_ADM_R[7..0] 8

SRN47J-7-GP
M_CKE#0
M_AA12

SRN47J-7-GP
4
3
SRN47J-6-GP

5,8

M_CKE#0

M_CKE#0

M_CKE#1

www.kythuatvitinh.com
RN32

M_DATA24
M_DQS3
M_DATA26
M_DATA27

9
10
11
12
13
14
15
16
RN44

8
7
6
5
4
3
2
1

1D25V_S3
SRN68J-4-GP
M_ADM_R1
M_DATA_R_13
M_DATA_R_12
M_DATA_R_7
M_DATA_R_6
M_ADM_R0
M_DATA_R_5
M_DATA_R_4

M_DATA_R_35
M_DATA_R_41
M_DATA_R_40
M_DQS_R5
M_DATA_R_42
M_DATA_R_43
M_DATA_R_49
M_DATA_R_48

9
10
11
12
13
14
15
16

SRN10J-3
M_DATA_R_14
M_DATA_R_15
M_DATA_R_21
M_DATA_R_20
M_ADM_R2
M_DATA_R_23
M_DATA_R_22
M_DATA_R_28

9
10
11
12
13
14
15
16
RN41

M_DATA29
M_ADM3
M_DATA31
M_DATA30

M_DATA_R_32
M_DATA_R_33
M_DQS_R4
M_DATA_R_34

RN35

SRN10J-3

M_DATA11
M_DATA10
M_DATA17
M_DATA16
M_DQS2
M_DATA19
M_DATA18
M_DATA25

5
6
7
8

8
7
6
5
4
3
2
1

RN31

RN43 SRN10J-5-GP
5 M_DATA_R_37
6 M_DATA_R_36
7 M_ADM_R4
8 M_DATA_R_39

RN34 SRN10J-5-GP
SRN10J-3

SRN10J-3

M_DATA14
M_DATA15
M_DATA21
M_DATA20
M_ADM2
M_DATA23
M_DATA22
M_DATA28

SERIES DAMPING

RN40

M_DATA1
M_DATA0
M_DQS0
M_DATA2
M_DATA3
M_DATA8
M_DATA9
M_DQS1

PLACE RNs CLOSE TO FIRST DIMM, < 0.75"

STRICT EQUAL LENGTH LIMITATION WITH DQS,
CB PINS
SRN10J-3
M_DATA4
M_DATA5
M_ADM0
M_DATA6
M_DATA7
M_DATA13
M_DATA12
M_ADM1

4
3
2
1

RN36

RN42 SRN10J-5-GP
5 M_DATA_R_29
6 M_ADM_R3
7 M_DATA_R_31
8 M_DATA_R_30

4
3
2
1

5
6
7
8

M_DATA_R_24
M_DQS_R3
M_DATA_R_26
M_DATA_R_27

SRN10J-3

M_ADM6
M_DATA54
M_DATA55
M_DATA61
M_DATA60
M_ADM7
M_DATA62
M_DATA63

8
7
6
5
4
3
2
1

RN45

RN114
SRN68J-4-GP

M_DATA_R_11
M_DATA_R_10
M_DATA_R_16
M_DATA_R_17
M_DQS_R2
M_DATA_R_19
M_DATA_R_18
M_DATA_R_24

8
7
6
5
4
3
2
1

RN111
SRN68J-4-GP

9
10
11
12
13
14
15
16

8
7
6
5
4
3
2
1

RN60

M_DATA_R_27 1
M_DATA_R_26 2
M_DQS_R3
3
M_DATA_R_25 4

RN61 SRN68J-3-GP
8
7
6
5

RN33 SRN10J-5-GP

M_DATA_R_31 4
M_DATA_R_30 3
M_ADM_R3
2
M_DATA_R_29 1

5
6
7
8

9
10
11
12
13
14
15
16

M_DATA_R_59
M_DATA_R_58
M_DQS_R7
M_DATA_R_57
M_DATA_R_56
M_DATA_R_51
M_DATA_R_50
M_DQS_R6

9
10
11
12
13
14
15
16

M_ADM_R6
M_DATA_R_54
M_DATA_R_55
M_DATA_R_60
M_DATA_R_61
M_ADM_R7
M_DATA_R_62
M_DATA_R_63

M_BA9
M_BA6
M_BA10
M_BA1
M_BA2
M_BA0
M_BBS#0
M_BWE#

8
7
6
5
4
3
2
1

9
10
11
12
13
14
15
16

5,8

M_CKE#1

9
10
11
12
13
14
15
16

RN69
SRN47J-4-GP

RN112

M_BA4
M_BA8
M_BA11
M_CKE#1

RN115SRN68J-3-GP

8
7
6
5
4
3
2
1

RN64
SRN47J-6-GP

RN67
SRN68J-4-GP

8
7
6
5
4
3
2
1

M_AA1
M_AA10
M_AA2
M_AA0
M_ABS#1
M_ARAS#
M_CS#2
M_BA13

4
3
2
1

5
6
7
8

RN108
SRN47J-4-GP
M_AA13
M_CS#0
M_CS#1
M_ACAS#

4
3
2
1

5
6
7
8
RN51

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

DDR DAMPING & TERMINATION

05/10
Remove the damping resistor for AMD suggest.

Size
A3

Document Number

Date: Thursday, October 13, 2005

A

Rev

SA

Bolsena-E
Sheet
E

of

58

DY
1

2
1

DY
1

DY

DY
1

DY

DY

C866
C868
C870
C860
C862
C864
C394
C417
C430
C437
C457
C469
C383
C491
C425
C358
C498
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP

DY

DY

DY

DY

DY

C861
C863
C865
C867
C869
C871
C509
C481
C464
C456
C436
C418
C424
C416
C401
C382
C419
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
2

1D25V_S3

LAYOUT:Place altemating caps to GND and 2D5_S3

2D5V_S3

DY

2D5V_S3

C501
C500
C494
C503
C499
C520
C357
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP

DY

DY

DY

DY

DY

DY

DY

DY

DY

DY

DY

DY

DY

C875
C879
C881
C883
C873
C877
C511
C403
C451
C365
C379
C388
C422
C442
C397
C475
C497
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
2

DY

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C872
C874
C876
C878
C880
C882
C510
C402
C450
C364
C378
C409
C421
C441
C458
C471
C495
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
2

1D25V_S3

1D25V_S3

DY

LAYOUT:Place close to Power Pin of DDR socket.

2D5V_S3

LAYOUT:Place at end of the DIMMs

2D5V_S3

DY

2 C466
SCD22U16V3ZY-GP

2 C504
SCD22U16V3ZY-GP

2 C465
SCD22U16V3ZY-GP

2 C519
SCD22U16V3ZY-GP

2 C484 DY
SCD22U16V3ZY-GP

2 C518
SCD22U16V3ZY-GP

2 C483
SCD22U16V3ZY-GP

2 C502
SCD22U16V3ZY-GP

2 C482
SCD22U16V3ZY-GP

2 C517
SCD22U16V3ZY-GP

C889
C886
C888
C887
SC10U10V5ZY-1GP SC10U10V5ZY-1GP SC10U10V5ZY-1GP SC10U10V5ZY-1GP
2

TC26
SE100U10VM-4GP

1
TC15
ST100U4VBM-U

1D25V_S3

79.10111.40L

DY

DY

DY

0.22u x 10

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

DDR DECOUPLING
Size
A3

Document Number

Rev

SA

Bolsena-E

Date: Thursday, October 13, 2005

Sheet
E

10

of

58

CLAW HAMMER TO NB

NB TO CLAW HAMMER

4 CPUCADOUT[15..0]
4 CPUCADOUTJ[15..0]

U61A

T26
R26
U25
U24
V26
U26
W25
W24
AA25
AA24
AB26
AA26
AC25
AC24
AD26
AC26

HT_RXCAD15P
HT_RXCAD15N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD8P
HT_RXCAD8N

PART 1OF6

HYPER TRANSPORT CPU I/F

CPUCADOUT15
CPUCADOUTJ15
CPUCADOUT14
CPUCADOUTJ14
CPUCADOUT13
CPUCADOUTJ13
CPUCADOUT12
CPUCADOUTJ12
CPUCADOUT11
CPUCADOUTJ11
CPUCADOUT10
CPUCADOUTJ10
CPUCADOUT9
CPUCADOUTJ9
CPUCADOUT8
CPUCADOUTJ8

NB0CADOUT[15..0] 4
NB0CADOUTJ[15..0] 4

NB0CADOUT15
NB0CADOUTJ15
NB0CADOUT14
NB0CADOUTJ14
NB0CADOUT13
NB0CADOUTJ13
NB0CADOUT12
NB0CADOUTJ12
NB0CADOUT11
NB0CADOUTJ11
NB0CADOUT10
NB0CADOUTJ10
NB0CADOUT9
NB0CADOUTJ9
NB0CADOUT8
NB0CADOUTJ8

HT_TXCAD15P
HT_TXCAD15N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD8P
HT_TXCAD8N

R24
R25
N26
P26
N24
N25
L26
M26
J26
K26
J24
J25
G26
H26
G24
G25

HT_TXCAD7P
HT_TXCAD7N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD0P
HT_TXCAD0N

L30
M30
L28
L29
J29
K29
H30
H29
E29
E28
D30
E30
D28
D29
B29
C29

NB0CADOUT7
NB0CADOUTJ7
NB0CADOUT6
NB0CADOUTJ6
NB0CADOUT5
NB0CADOUTJ5
NB0CADOUT4
NB0CADOUTJ4
NB0CADOUT3
NB0CADOUTJ3
NB0CADOUT2
NB0CADOUTJ2
NB0CADOUT1
NB0CADOUTJ1
NB0CADOUT0
NB0CADOUTJ0

HT_TXCLK1P
HT_TXCLK1N

L24
L25

NB0HTTCLKOUT1
NB0HTTCLKOUTJ1

NB0HTTCLKOUT1 4
NB0HTTCLKOUTJ1 4

HT_TXCLK0P
HT_TXCLK0N

F29
G29

NB0HTTCLKOUT0
NB0HTTCLKOUTJ0

NB0HTTCLKOUT0 4
NB0HTTCLKOUTJ0 4

HT_TXCTLP
HT_TXCTLN

M29
M28

NB0HTTCTLOUT
NB0HTTCTLOUTJ

HT_TXCALP
HT_TXCALN

B28
A28

HT_TXCALP
HT_TXCALN

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CPUCADOUT7
CPUCADOUTJ7
CPUCADOUT6
CPUCADOUTJ6
CPUCADOUT5
CPUCADOUTJ5
CPUCADOUT4
CPUCADOUTJ4
CPUCADOUT3
CPUCADOUTJ3
CPUCADOUT2
CPUCADOUTJ2
CPUCADOUT1
CPUCADOUTJ1
CPUCADOUT0
CPUCADOUTJ0

C254
C248
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2

1D2V_S0

4 CPUHTTCLKOUT1
4 CPUHTTCLKOUTJ1
4 CPUHTTCLKOUT0
4 CPUHTTCLKOUTJ0

DY

AROUND NB

4 CPUHTTCTLOUT0
4 CPUHTTCTLOUTJ0
1 R124
1 R123

1D2V_S0

CPUHTTCLKOUT1
CPUHTTCLKOUTJ1

R29
R28
T30
R30
T28
T29
V29
U29
Y30
W30
Y28
Y29
AB29
AA29
AC29
AC28

HT_RXCAD7P
HT_RXCAD7N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD0P
HT_RXCAD0N

Y26
W26

HT_RXCLK1P
HT_RXCLK1N

CPUHTTCLKOUT0
CPUHTTCLKOUTJ0

W29
W28

CPUHTTCTLOUT0
CPUHTTCTLOUTJ0

P29
N29

HT_RXCALN
2 49D9R2F-GP
HT_RXCALP
2 49D9R2F-GP

D27
E27

HT_RXCLK0P
HT_RXCLK0N
HT_RXCTLP
HT_RXCTLN
HT_RXCALN
HT_RXCALP

NB0HTTCTLOUT 4
NB0HTTCTLOUTJ 4
1 R498

2
100R2F-L1-GP-U

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

ATI-RS482M (1 of 4) HT
Size
A3

Document Number

Rev

SA

Bolsena-E

Date: Thursday, October 13, 2005

Sheet
E

11

of

58

49 PEG_TXP[15..0]
49 PEG_TXN[15..0]
49 PEG_RXP[15..0]
49 PEG_RXN[15..0]
U61B

U61C

NC#AG26
NC#AJ29
NC#AE21
NC#AH24
NC#AH12
NC#AG13
NC#AH18
NC#AE8

AF25
AH30
AG20
AJ25
AH13
AF14
AJ7
AG8

NC#AF25
NC#AH30
NC#AG20
NC#AJ25
DVO_IDCKP
NC#AF14
NC#AJ7
NC#AG8

AG25
AH29
AF21
AK25
AJ12
AF13
AK7
AF9

NC#AG25
NC#AH29
NC#AF21
NC#AK25
DVO_IDCKN
NC#AF13
NC#AK7
NC#AF9

AE17
AH18
AE18
AJ19
AF18

NC#AE17
NC#AH18
NC#AE18
NC#AJ19
NC#AF18

AK16
DVO' AJ16

NC#AK16
NC#AJ16

NC#AH5
NC#AD30

AH5
AD30

PART 2 OF 6
PEG_TXP15
PEG_TXN15
PEG_TXP14
PEG_TXN14
PEG_TXP13
PEG_TXN13
PEG_TXP12
PEG_TXN12
PEG_TXP11
PEG_TXN11
PEG_TXP10
PEG_TXN10
PEG_TXP9
PEG_TXN9
PEG_TXP8
PEG_TXN8
PEG_TXP7
PEG_TXN7
PEG_TXP6
PEG_TXN6
PEG_TXP5
PEG_TXN5
PEG_TXP4
PEG_TXN4
PEG_TXP3
PEG_TXN3
PEG_TXP2
PEG_TXN2
PEG_TXP1
PEG_TXN1
PEG_TXP0
PEG_TXN0

D8
D7
D5
D4
E4
F4
G5
G4
H4
J4
H5
H6
G1
G2
K5
K4
L4
M4
N5
N4
P4
R4
P5
P6
P2
R2
T5
T4
U4
V4
W1
W2

GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N

PCIE I/F TO VIDEO

AG26
AJ29
AE21
AH24
AH12
AG13
AH8
AE8

PART 3 OF

NC#AF28
6 NC#AF27
NC#AG28
NC#AF26
NC#AE25
NC#AE24
NC#AF24
NC#AG23
NC#AE29
NC#AF29
NC#AG30
NC#AG29
NC#AH28
NC#AJ28
NC#AH27
NC#AJ27
NC#AE23
NC#AG22
NC#AF23
NC#AF22
NC#AE20
NC#AG19
NC#AF20
NC#AF19
NC#AH26
NC#AJ26
NC#AK26
NC#AH25
NC#AJ24
NC#AH23
NC#AJ23
NC#AH22
NC#AK14
DVO_D11
DVO_D10
DVO_D9
DVO_D8
DVO_D7
DVO_D6
DVO_D4
NC#AE15
NC#AF15
NC#AG14
NC#AE14
NC#AE12
NC#AF12
NC#AG11
NC#AE11
DVO_D5
DVO_D1
DVO_D2
DVO_D3
DVO_D0
DVO_DE
DVO_HSYNC
DVO_VSYNC
NC#AG10
NC#AF11
NC#AF10
NC#AE9
NC#AG7
NC#AF8
NC#AF7
NC#AE7

LANE REVERSE

NC#AF17
NC#AK17
NC#AH16
NC#AF16
NC#AJ22
NC#AJ21
NC#AH20
NC#AH21
NC#AK19
NC#AH19
NC#AJ17
NC#AG16
NC#AG17
NC#AH17
NC#AJ18

AF28
AF27
AG28
AF26
AE25
AE24
AF24
AG23
AE29
AF29
AG30
AG29
AH28
AJ28
AH27
AJ27
AE23
AG22
AF23
AF22
AE20
AG19
AF20
AF19
AH26
AJ26
AK26
AH25
AJ24
AH23
AJ23
AH22
AK14
AH14
AK13
AJ13
AJ11
AH11
AJ10
AH10
AE15
AF15
AG14
AE14
AE12
AF12
AG11
AE11
AJ9
AH9
AJ8
AK8
AH7
AJ6
AH6
AJ5
AG10
AF11
AF10
AE9
AG7
AF8
AF7
AE7

GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N

A7
B7
B6
B5
A5
A4
B3
B2
C1
D1
D2
E2
F2
F1
H2
J2
J1
K1
K2
L2
M2
M1
N1
N2
R1
T1
T2
U2
V2
V1
Y2
AA2

PEG_RXP15_NB
PEG_RXN15_NB
PEG_RXP14_NB
PEG_RXN14_NB
PEG_RXP13_NB
PEG_RXN13_NB
PEG_RXP12_NB
PEG_RXN12_NB
PEG_RXP11_NB
PEG_RXN11_NB
PEG_RXP10_NB
PEG_RXN10_NB
PEG_RXP9_NB
PEG_RXN9_NB
PEG_RXP8_NB
PEG_RXN8_NB
PEG_RXP7_NB
PEG_RXN7_NB
PEG_RXP6_NB
PEG_RXN6_NB
PEG_RXP5_NB
PEG_RXN5_NB
PEG_RXP4_NB
PEG_RXN4_NB
PEG_RXP3_NB
PEG_RXN3_NB
PEG_RXP2_NB
PEG_RXN2_NB
PEG_RXP1_NB
PEG_RXN1_NB
PEG_RXP0_NB
PEG_RXN0_NB

C752
C753
C754
C755
C756
C757
C758
C759
C771
C770
C775
C774
C776
C784
C783
C789
C792
C791
C790
C794
C795
C801
C799
C798
C800
C805
C804
C810
C811
C812
C816
C817

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP

PEG_RXP15
PEG_RXN15
PEG_RXP14
PEG_RXN14
PEG_RXP13
PEG_RXN13
PEG_RXP12
PEG_RXN12
PEG_RXP11
PEG_RXN11
PEG_RXP10
PEG_RXN10
PEG_RXP9
PEG_RXN9
PEG_RXP8
PEG_RXN8
PEG_RXP7
PEG_RXN7
PEG_RXP6
PEG_RXN6
PEG_RXP5
PEG_RXN5
PEG_RXP4
PEG_RXN4
PEG_RXP3
PEG_RXN3
PEG_RXP2
PEG_RXN2
PEG_RXP1
PEG_RXN1
PEG_RXP0
PEG_RXN0

LANE REVERSE

AF17
AK17
AH16
AF16
AJ22
AJ21
AH20
AH21
AK19
AH19
AJ17
AG16
AG17
AH17
AJ18

Dummy when 'USE

C829 SCD47U10V3ZY-GP
1
2MEM_CAP1
AE28
1
2MEM_CAP2
AJ4

MEM_A I/F

www.kythuatvitinh.com
NC#AE28
NC#AJ4

C837 SCD47U10V3ZY-GP
RS480_MEM_VMODE AJ20

NC#AK20

AJ15
AJ14

VDD_18
VSS

GPP_RX0P/SB_RX2P
GPP_RX0N/SB_RX2N

GPP_TX0P/SB_TX2P
GPP_TX0N/SB_TX2N

AD2
AD1

AB2
AC2

GPP_RX1P/SB_RX3P
GPP_RX1N/SB_RX3N

GPP_TX1P/SB_TX3P
GPP_TX1N/SB_TX3N

AA1
AB1

AB5
AB4

GPP_RX2P
GPP_RX2N

Y4
AA4

GPP_RX3P
GPP_RX3N

17 PCIE_RX0P_SB
17 PCIE_RX0N_SB

AG1
AH1

SB_RX0P
SB_RX0N

17 PCIE_RX1P_SB
17 PCIE_RX1N_SB

AC5
AC6

PCE_ISETAH3
1 R531
2 10KR2J-2-GP
PCE_TXISETAJ3
1
2
R532 8K25R3F-2-GP

PCIE I/F TO SLOT GPP_TX2P

PCIE I/F TO SB

SB_RX1P
SB_RX1N
PCE_ISET
PCE_TXISET

GPP_TX2N

Y5
Y6

GPP_TX3P
GPP_TX3N

W5
W4

SB_TX0P
SB_TX0N

AF2
AG2

SB_TX0P C824 1
SB_TX0N C825 1

SB_TX1P
SB_TX1N

AC4
AD4

SB_TX1P C826 1
SB_TX1N C830 1

PCE_PCAL
PCE_NCAL

AH2
AJ2

PCE_PCAL
PCE_NCAL

Dummy when use UMA

2
PCIE_TX0P_SB 17
2 SCD1U16V2ZY-2GP PCIE_TX0N_SB 17
SCD1U16V2ZY-2GP
2
PCIE_TX1P_SB 17
2 SCD1U16V2ZY-2GP PCIE_TX1N_SB 17
SCD1U16V2ZY-2GP
1 R528
2 150R2F-1-GP
100R2F-L1-GP-U
1 R529
2
1D2V_S0

<Variant Name>

C366
SC1U10V3KX-3GP

1D8V_S0

AK20

MPVDD_PLL
1
2

1 R178
2
0R0603-PAD

1D8V_S0

NC#AJ20

MEM_VREF

AE1
AE2

RS480_MEM_VMODE

MEM_VREF

R170
1KR2J-1-GP

R174
1KR2F-3-GP

Dummy when 'USE DVO'

R175
1KR2F-3-GP
2

NO DVO:
MEM_COMPP = NC
MEM_COMPN = NC
MEM_CAP1 = 470nF
MEM_CAP2 = 470nF
MEM_VMODE = GND (IF VDD_MEM = 2.5V)
MEM_VREF = VDD_MEM / 2

WITH DVO:
MEM_COMPP = 61.9 OHM TO GND
MEM_COMPN = 61.9 OHM TO VDD_MEM
MEM_CAP1 = NC
MEM_CAP2 = NC
MEM_VMODE = 1.8V(IF VDD_MEM = 1.8V)
MEM_VREF = VDD_MEM / 2

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

ATI-RS482M (2 of 4) PCIE
Size
A3

Document Number

Date: Thursday, October 13, 2005

A

Rev

SA

Bolsena-E
Sheet
E

12

of

58

AVDD

AVDDQ

1
2

1D8V_S0

C751
SC2D2U16V5ZY-GP

5
6
7
8

TXBCLK+
TXBCLKTXBOUT2+
TXBOUT2-

5
6
7
8

4
3
2
1

UMA_VS
UMA_HS

1 R125
2
715R2F-GP

15 UMA_CRT_DDC_C
15 UMA_CRT_DDC_D

C741
SCD1U16V2ZY-2GP

C748

SC2D2U16V5ZY-GP
2

1
2

C747

SC10U10V5ZY-1GP
2

1
2
BLM11A121S-GP

IRSET_NB

E24
D24

AVDDQ
AVSSQ

B25
A25
A24

C
Y
COMP

C25
A26
B26

RED
GREEN
BLUE

A11
B11
C26
E11
F11

DAC_VSYNC
DAC_HSYNC
RSET
DAC_SCL
DAC_SDA

A14
B14

PLLVDD
PLLVSS

M23
L23

HTPVDD
HTPVSS

D14
B15
B12
C12
AH4

SYSRESET#
POWERGOOD
LDTSTOP#
ALLOW_LDTSTOP
NC

TXOUT_U0P
TXOUT_U0N
TXOUT_U1P
TXOUT_U1N
TXOUT_U2P
TXOUT_U2N
TXOUT_U3P
TXOUT_U3N

TXBOUT0+
D18
TXBOUT0C18
TXBOUT1+
B19
TXBOUT1A19
TXBOUT2+
D19
TXBOUT2C19
D20 TXBOUT3+
TXBOUT3C20

4
3
2
1

TXOUT_L0P
TXOUT_L0N
TXOUT_L1P
TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P
TXOUT_L3N

TXAOUT0+
B16
TXAOUT0A16
TXAOUT1+
D16
TXAOUT1C16
TXAOUT2+
B17
TXAOUT2A17
TXAOUT3+
E17
D17 TXAOUT3-

TXCLK_UP
TXCLK_UN
TXCLK_LP
TXCLK_LN

B20
A20
B18
C17

LPVDD
LPVSS
LVDDR18D
LVDDR18A_1
LVDDR18A_2

E18
F17
E19
G20
H20

LVSSR1
LVSSR2
LVSSR3
LVSSR4
LVSSR5
LVSSR6
LVSSR7
LVSSR8

G19
E20
F20
H18
G18
F19
H19
F18

LVDS_DIGON
LVDS_BLON
LVDS_BLEN

E14
F14
F13

4
3
2
1

2 R137

LCD_TXAOUT1+
LCD_TXAOUT1LCD_TXAOUT0+
LCD_TXAOUT0-

16,57
16,57
16,57
16,57

LCD_TXBOUT1+
LCD_TXBOUT1LCD_TXBOUT0+
LCD_TXBOUT0-

16,57
16,57
16,57
16,57

LCD_TXBCLK+
LCD_TXBCLKLCD_TXBOUT2+
LCD_TXBOUT2-

16,57
16,57
16,57
16,57

SRN0J-4-GP

1
0R2J-GP

LCD_VDD_ON 16,57

Dummy when use Discrete

TP23
TP20

1D8V_S0

R486
TP28
TP27

TXBCLK+
TXBCLKTXACLK+
TXACLK-

1
C746
1D8VLPVDD_S0

2
BLM11A121S-GP

C251

R485

3 CLK14_NB

C280
SC1U10V3ZY-6GP

TP97

NB_SUS_STAT#

DO NOT SUPPORT SIDEPORT MEMORY

DO NOT SUPPORT SERIAL STRAP ROM
DUMMY IT

TPAD30
TPAD30
TPAD30

A13
B13

NB_OSC_OUT

TPAD30

10KR2J-2-GP
R497 2

B9

DFT_GPIO0
DFT_GPIO1
DFT_GPIO2

TP25
TP22
TP21

OSCIN
OSCOUT

CLOCKs

F12
E13
D13

DFT_GPIO0
DFT_GPIO1
DFT_GPIO2

RN104

16,50 EDID_CLK
16,50 EDID_DAT

4
3

RN105
3 SRN0J-6-GP
2
4
1

1
2
SRN10KJ-5-GP

17

BMREQ#

RS480_CLK
RS480_DAT

F10
C10
C11
AF4
AE4

BMREQ#
I2C_CLK
I2C_DATA
THERMALDIODE_P
THERMALDIODE_N

MIS.

TPAD30

HTTSTCLK
HTREFCLK

2
P23 HTTST_CLK 1 R153
10KR2J-2-GP
N23
HTREF_CLK 3

NBSRC_CLK 3
NBSRC_CLK# 3

E8
E7

TMDS_HPD

A10
E10

2
BLM11A121S-GP

C250

C249

R484

2
BLM11A121S-GP

SBLINK_CLK 3
SBLINK_CLK# 3
DFT_GPIO3
DFT_GPIO4
DFT_GPIO5

C13
C14
C15

STRP_DATA

1
2

TP24

B8
A8

DFT_GPIO3
DFT_GPIO4
DFT_GPIO5

3D3V_S0

C744

LCDVDD_ON
LVDS_BLON
LVDS_BLEN_NB

GFX_CLKP
GFX_CLKN

SB_CLKP
SB_CLKN

TVCLKIN

C745

SCD1U16V2ZY-2GP

VDDR3_1
VDDR3_2

LVDDR18A_S0

SC1U10V3ZY-6GP

H13
H12

3D3VDDR_S0

1 R151
2
0R0603-PAD

R535
4K7R2J-2-GP
2

NB_SUS_STAT#

3D3V_S0

1D8V_S0

SC10U10V5ZY-1GP
2

RS480_RST#

39,52 NB_PWRGD
6,17 LDT_STP#
17 ALLOW_LDTSTOP

LVDDR18D_S0

SCD1U16V2ZY-2GP

C788

PM

C787

SCD1U16V2ZY-2GP
2

C793

150R5F

PLL PWR

www.kythuatvitinh.com
HTPVDD

SRN0J-4-GP

RN86
LCDVDD_ON

16,57
16,57
16,57
16,57

SRN0J-4-GP

15
15

PLVDD
R487

AVDD1
AVDD2
AVSSN1
AVSSN2
AVDDDI
AVSSDI

LVDS

1
2

C263
SC1U10V3ZY-6GP

PART 4 OF 6

CRT/TVOUT

1
2
1
2
1
2
150R2F-1-GP R495
150R2F-1-GP R494
150R2F-1-GP R496

R491 150R2F-1-GP
1
2
R492 150R2F-1-GP
1
2
R493 150R2F-1-GP
1
2

AVDDQ

57 UMA_R
57 UMA_G
57 UMA_B

1D8V_S0

1
R515

TXBOUT1+
TXBOUT1TXBOUT0+
TXBOUT0-

LCD_TXACLK+
LCD_TXACLKLCD_TXAOUT2+
LCD_TXAOUT2-

SRN0J-4-GP

RN84
U61D
B27
C27
D26
D25
C24
B24

57 UMA_CRMA
57 UMA_LUMA
57 UMA_COMP

1D8V_S0

5
6
7
8

C247
SC2D2U16V5ZY-GP

Dummy when use Discrete

TXAOUT1+
TXAOUT1TXAOUT0+
TXAOUT0-

4
3
2
1

RN78
1D8VAVDDD1_S0

1 R126
2
0R0603-PAD

DY

SCD1U16V2ZY-2GP

5
6
7
8
RN80

C781

SC10U10V5ZY-1GP
2

C782

1 R511
2
0R0603-PAD

1 R490
2
0R0603-PAD

TXACLK+
TXACLKTXAOUT2+
TXAOUT2-

1D8V_S0

3D3V_S0

SCD1U16V2ZY-2GP
SC2D2U16V5ZY-GP

2
1
SC1U10V3ZY-6GP SC1U10V3ZY-6GP

TP98
TP96
TP95

TPAD30
TPAD30
TPAD30

TP99 TPAD28
TP26 TPAD28

DDC_DATA

B10 DDC_DATA

TESTMODE

E12 TESTMODE_NB

TP100 TPAD28

VCC_CORE_S0
1

Dummy when use Discrete

1 2

R147
DUMMY-R2

R142
4K7R2J-2-GP

<Variant Name>
1

Wistron Corporation
RS480_RST#
C235
DUMMY-C3

1 R475
R474
1KR2J-1-GP

2
0R2J-GP

Title
R305
10KR2J-2-GP

Dummy when use Discrete

2

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

BL_ON 34,52
2

LVDS_BLON
1

R118 2
33R2J-2-GP

17,34,37,49 LPC_RST#

ATI-RS482M (3 of 4) LVDS CRT

Size
A3

Document Number

Date: Thursday, October 13, 2005

A

Rev

SA

Bolsena-E
Sheet
E

13

of

58

DY
2

U13
BAV99PT-GP-U

3D3V_S0

R177

DY

0R2J-GP

2
BLM11A121S-GP
1

DY
C373

R176
0R2J-GP
1
C332

SC1U10V3KX-3GP

C279 C333

SCD1U16V2ZY-2GP
2

C371
C342
C356

1
C372

C355

SCD1U16V2ZY-2GP

C340

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SC10U10V5ZY-1GP

C313

C329

C328

C296

C327

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C312

SCD1U16V2ZY-2GP

C278

C277

C258

C259

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C276

SCD1U16V2ZY-2GP

1D8V_S0

VDDHT30
VDDHT31

L12
1D8VDD_S0

1D2V_S0

N27
U27
V27
G27
V24
H27
K24
AB24
P27
J27
AA27
K27
P24
AB27
AB23
V23
G23
E23
W23
K23
J23
H23
U23
AA23
D23
F23
C23
B23
A23
A29
AC30
VDD_HT1
VDD_HT2
VDD_HT3
VDD_HT4
VDD_HT5
VDD_HT6
VDD_HT7
VDD_HT8
VDD_HT9
VDD_HT10
VDD_HT11
VDD_HT12
VDD_HT13
VDD_HT14
VDD_HT15
VDD_HT16
VDD_HT17
VDD_HT18
VDD_HT19
VDD_HT20
VDD_HT21
VDD_HT22
VDD_HT23
VDD_HT24
VDD_HT25
VDD_HT26
VDD_HT27
VDD_HT28
VDD_HT29
VDD_HT30
VDD_HT31

AK23
AK28
AK11
AK4
AE30
AC14
AD12
AC18
AC20
AD10
AD14
AD15
AD20
AC10
AD18
AC12
AD22
AC22
AH15
VDD_DVO_1
VDD_DVO_2
VDD_DVO_3
VDD_DVO_4
VDD_DVO_5
VDD_DVO_6
VDD_DVO_7
VDD_DVO_8
VDD_DVO_9
VDD_DVO_10
VDD_DVO_11
VDD_DVO_12
VDD_DVO_13
VDD_DVO_14
VDD_DVO_15
VDD_DVO_16
VDD_DVO_17
VDD_DVO_18
VDD_DVO_19

H15
AC17
AC15
VDD_18_1
VDD_18_2
VDD_18_3

B21
C21
A22
B22
C22
F21
F22
E21
G21

PART 5 OF 6 VDDA_12_14

VDD_CORE47
VDD_CORE46
VDD_CORE45
VDD_CORE44
VDD_CORE43
VDD_CORE42
VDD_CORE41
VDD_CORE40
VDD_CORE39

VDDA_12_1
VDDA_12_2
VDDA_12_3
VDDA_12_4
VDDA_12_5
VDDA_12_6
VDDA_12_7
VDDA_12_8
VDDA_12_9
VDDA_12_10
VDDA_12_11
VDDA_12_12
VDDA_12_13
VDDA_18_1
VDDA_18PLL_1
VDDA_18_2
VDDA_18_3
VDDA_18_4
VDDA_18_5
VDDA_18PLL_2
VDDA_18PLL_3
VDDA_18_6
VDDA_18_7
VDDA_18_8
VDDA_18_9
VDDA_18_10
VDD_CORE1
VDD_CORE2
VDD_CORE3
VDD_CORE4
VDD_CORE5
VDD_CORE6
VDD_CORE7
VDD_CORE8
VDD_CORE9
VDD_CORE10
VDD_CORE11
VDD_CORE12
VDD_CORE13
VDD_CORE14
VDD_CORE15
VDD_CORE16
VDD_CORE17
VDD_CORE18
VDD_CORE19
VDD_CORE20
VDD_CORE21
VDD_CORE22
VDD_CORE23
VDD_CORE24
VDD_CORE25
VDD_CORE26
VDD_CORE27
VDD_CORE28
VDD_CORE29
VDD_CORE30
VDD_CORE31
VDD_CORE32
VDD_CORE33
VDD_CORE34
VDD_CORE35
VDD_CORE36
VDD_CORE37
VDD_CORE38

C316
C315
C314

SCD1U16V2ZY-2GP

C305
C317

DY

C270

DY

C336

U14
BAV99PT-GP-U

DY

C307

C292
C301

TC9
ST100U6D3VDM-6GP

SB 0127

L11 2
MLB-201209-21-GP

TC10
ST100U6D3VDM-6GP

DY

Size
A3

Date: Thursday, October 13, 2005

L10 2
MLB-201209-21-GP

VSSA22

Sheet
E

1D2V_S0

VDDA12_13

VSSA59

1D2V_VDDA_RS480_S0

SC10U10V5ZY-1GP

VSSA22

VSSA68
VSSA67
VSSA66
VSSA65
VSSA64
VSSA63
VSSA62
VSSA61
VSSA60
VSSA59
VSSA58
VSSA57
VSSA56
VSSA55
VSSA54
VSSA53
VSSA52
VSSA51
VSSA50
VSSA49
VSSA48
VSSA47
VSSA46
VSSA45
VSSA44
VSSA43
VSSA42
VSSA41
VSSA40
VSSA39
VSSA38
VSSA37
VSSA36
VSSA35
VSSA34
VSSA33
VSSA32
VSSA31
VSSA30
VSSA29
VSSA28
VSSA27
VSSA26
VSSA25
VSSA24
VSSA23
VSSA22
VSSA21
VSSA20
VSSA19
VSSA18
VSSA17
VSSA16
VSSA15
VSSA14
VSSA13
VSSA12
VSSA11
VSSA10
VSSA9
VSSA8
VSSA7
VSSA6
VSSA5
VSSA4
VSSA3
VSSA2
VSSA1

GROUND

VSS30

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

VSSA59

T8
L5
E5
U6
U5
E6
F6
V7
M7
AJ1
L6
AG3
C2
H8
V6
M3
H7
K7
AD6
Y7
T7
AB8
K3
C4
D6
AD5
J3
R6
J5
C7
C9
AA5
P7
B4
G3
AB7
M5
AF3
AE3
F3
V8
AD3
C8
J6
P8
AB3
A2
AA3
C6
D3
K8
W3
C3
V3
Y8
M8
F8
C5
M6
T3
AA6
R3
F5
F7
N3
V5
AE5
R5

VSS120
VSS119
VSS118
VSS117
VSS116
VSS115
VSS114
VSS113

VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34
VSS33
VSS32
VSS31
VSS30
VSS29
VSS28
VSS27
VSS26
VSS25
VSS24
VSS23
VSS22
VSS21
VSS20
VSS19
VSS18
VSS17
VSS16
VSS15
VSS14
VSS13
VSS12
VSS11
VSS10
VSS9
VSS8
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2
VSS1

VSS72
VSS71
VSS70
VSS69
VSS68
VSS67
VSS66
VSS65
VSS64
VSS63
VSS62
VSS61
VSS60
VSS59
VSS58
VSS57
VSS56
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45

F15
E15
D10
E16
H14
H16
H10
H17
AD25
H11
D11
W27
F26
T24
B30
F25
G16
C28
Y27
R19
AC9
Y23
G17
AA28
AD24
D12
AB25
AB28
G30
F16
G11
AD9
D9
D15
E9
G13
Y24
G14
G15
AC27
AD27
AD29
G12
G10

P16
M16
M12
M14
T18
V16
W15
N17
U13
M18
V18
P18
W17
W13
R13
T12
P12
R17
T16
U17
P14
N13
V12
N15
T14
R15
V14
U15

VSS30

VSS89

1D2V_S0
VSS89
2

L27
T23
K28
N19
J28
M24
H28
F28

VSS132
VSS131
VSS130
VSS129
VSS128
VSS127
VSS126
VSS125
VSS124
VSS123
VSS122

AE27
AE26
W19
AK29
AK22
AD21
AC13
AK10
AK5
AC21
AJ30
AD7
AC11
AG27
AC19
AG9
AG24
AF30
AG12
AG15
AD17
AG21
AG6
AG5
AD23
AD19
AD16
AD13
AD11
AD8
AC23
AG18
AC16
U19

G28
F27
F24
AD28
R27
T27

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C335

SCD1U16V2ZY-2GP

C306

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C293

SCD1U16V2ZY-2GP

C302

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C303

SCD1U16V2ZY-2GP

SC1U10V3KX-3GP

C282

SCD1U16V2ZY-2GP

DY

C300

2
C299
SCD1U16V2ZY-2GP

SC1U10V3KX-3GP

C318

SCD1U16V2ZY-2GP

VDDA18_13

1D8V_VDDA

C298
SC10U10V5ZY-1GP

C352

SCD1U16V2ZY-2GP

C281

SC10U10V5ZY-1GP

H9
AA7
G9
U8
N7
N8
U7
F9
AA8
G8
G7
J8
J7
B1
AG4
R8
AC8
AC7
AF6
AE6
L8
W8
W7
L7
R7
AF5
AK2
N16
M13
M15
W16
N18
P19
N12
P15
N14
M17
T19
G22
R12
P13
R14
V19
R18
U16
U12
T13
U14
T17
U18
E22
R16
V13
T15
P17
W18
D22
W12
V15
W14
V17
M19
H22
H21
D21
2

POWER

R23
V28
V25
U28
K25
E26
P28
P25
N28
H24
M27

VSS106
VSS105
VSS104
VSS103
VSS102
VSS101
VSS100
VSS99
VSS98
VSS97
VSS96
VSS95
VSS94
VSS93
VSS92
VSS91
VSS90
VSS89
VSS88
VSS87
VSS86
VSS85
VSS84
VSS83
VSS82
VSS81
VSS80
VSS79
VSS78
VSS77
VSS76
VSS75
VSS74
VSS73

VSS112
VSS111
VSS110
VSS109
VSS108
VSS107

SCD1U16V2ZY-2GP

U61F

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

DY

C345

SCD1U16V2ZY-2GP
2

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C331

C341

C344

SCD1U16V2ZY-2GP

2
SCD1U16V2ZY-2GP

C291

DY

SCD1U16V2ZY-2GP
2

1
SCD1U16V2ZY-2GP

C343

DY
2

SCD1U16V2ZY-2GP

C330

www.kythuatvitinh.com
DY

SCD1U16V2ZY-2GP

2
C823

SCD1U16V2ZY-2GP

2
C822

SC10U10V5ZY-1GP

C311

2
C334

SCD1U16V2ZY-2GP

DY

2
C297

PAR 6 OF 6

1D8V_S0

C354

SCD1U16V2ZY-2GP

A
E

14

U61E
1D2V_S0
VDDA12_13
3

C264
SC4D7U10V5ZY-3GP

DY

1D8V_S0

VDDA18_13

C353
SC4D7U10V5ZY-3GP

VDDHT30

C769
SC4D7U10V5ZY-3GP

VDDHT31
2
C815
SC4D7U10V5ZY-3GP

<Variant Name>
1

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

Title
Document Number

ATI-RS482M (4 of 4) PWR, GND

Bolsena-E
of
Rev
58

SA

3D3V_S0

CRT
CONN
200mA Rating/Spec 500mA

8
7
6
5

5V_CRT_S0

U3A

14

HSYNC_5_1

14

SRN0J-6-GP

Dummy when use Discrete

SYS_VS

RN1

SRN10KJ-6-GP

2
1
SRN0J-6-GP

CRT_DDC_D_1
CRT_DDC_C_1

SYS_CRT_DDC_D5
SYS_CRT_DDC_C5

2
1
SRN0J-6-GP

Dummy when use UMA

D28
1

5V_CRT_S0

RB751V-40-1-GP
C653
SCD01U25V2KX-3GP

DUMMY-C2

C1

2
1

3
4

50 DIS_CRT_DDC_D
50 DIS_CRT_DDC_C

5V_S0

C2
DUMMY-C2

TSAHCT125PW-GP

RN5
3
4

RN2
5

DIS_HS
DIS_VS

U2
2N7002DW-7F-GP

Dummy when use Discrete

TSAHCT125PW-GP

U3B

3
4

13 UMA_CRT_DDC_D
13 UMA_CRT_DDC_C

SYS_HS

2
1VSYNC_5_1

3
4

RN3

RN4
UMA_HS
UMA_VS

1
2
3
4

5V_S0

SRN0J-6-GP

Dummy when use UMA

L18

57

CRT_R_1

57

CRT_G_1

CRT_R

2 BLM11B750S-GP

CRT1
SYS_CRT_DDC_D5

L19
CRT_G

2 BLM11B750S-GP

6
1

www.kythuatvitinh.com
CRT_R

SYS_HS

L20

CRT_G

SYS_VS

CRT_B
5V_CRT_S0

DY

C285
SC100P50V2JN-U

TV_COMP_CON
2
IND-1D2UH-5-GP

TV_LUMA_CON

1
BAV99PT-GP-U
D32
2
3

SC270P50V2JN-2GP

SC10P50V2JN-1

SC10P50V2JN-1
2

SC100P50V2JN-U

CHROMA

LUMA

8
1

4
2
5
7
6
3

5 4
7 2 1

3D3V_S0

DY

MINDIN7-11-U-GP

C255
2

C261

SC100P50V2JN-U

TV1

3D3V_S0

TV_COMP_CON
TV_CRMA_CON

SC100P50V2JN-U

1
2

1
2
150R2F-1-GP R148
1
2
150R2F-1-GP R138
1
2
150R2F-1-GP R132

-1 0302

TV CONN

DY

C266
SC270P50V2JN-2GP

TV_CRMA_CON
2
IND-1D2UH-5-GP

VIDEO-15-42-GP

ME : 20.20378.015

D34

L6
1

57 TV_CRMA
1

20.20378.015

BAV99PT-GP-U

2 C260
SC47P50V2JN-3GP

COMPOSIT
<Variant Name>

22.10021.D81
ME : 22.10021.D81

1
BAV99PT-GP-U

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CRT/TV
Size
A3

Document Number

Rev

SA

Bolsena-E

Date: Thursday, October 13, 2005

A

SYS_CRT_DDC_C5

16

3D3V_S0

1
2

C272
SC100P50V2JN-U

SYS_VS

15

C284
SC270P50V2JN-2GP

L8
1

SYS_HS

14

DY

DY

2 C271
SC47P50V2JN-3GP

57 TV_COMP

DY

SYS_CRT_DDC_D5

13

5V_S0

BAV99PT-GP-U

57 TV_LUMA

BAV99PT-GP-U

12

D37

L9
TV_LUMA_CON
2
IND-1D2UH-5-GP

D25

D26

D27

2 C283
SC47P50V2JN-3GP

11

7
2
8
3
9
4
10
5

C654

BAV99PT-GP-U

C651

C655
C652

SYS_CRT_DDC_C5

1
2

C661
SC8D2P50V2CC

C660
SC8D2P50V2CC

SC8D2P50V2CC

2
1
150R2F-1-GPR381
150R2F-1-GP
R381
2
1
150R2F-1-GPR382
150R2F-1-GPR382
2
1
150R2F-1-GPR383
150R2F-1-GPR383

DY

C659

SC47P50V2JN-3GP

DY

C665

SC47P50V2JN-3GP

C664

C663
SC47P50V2JN-3GP

DY

CRT_B

2 BLM11B750S-GP

CRT_B_1

57

17

Sheet
E

15

of

58

LEDs

5V_S0
NUM_LED#

1 R19
2
100R2F-L1-GP-U

CAP_LED#

1 R26
2
100R2F-L1-GP-U

MAIL_LED#

1 R10
2
100R2F-L1-GP-U

MEDIA_LED#

1 R20
2
100R2F-L1-GP-U

D5

LED-G-106-GP
A

on KB Cover

D4

LED-G-106-GP
A

on KB Cover

D3

LED-G-106-GP
A

on KB Cover

D6

LED-G-106-GP
A

on KB Cover

K
D48

WLAN_LED#

1 R580
2
1
22R2J-2-GP
1 R4
2
100R2F-L1-GP-U

1 R24
2
100R2F-L1-GP-U

FRONT_PWRLED# 1 R378
2
100R2F-L1-GP-U

Dummy when use IDE

18

1 R11

SATA_LED#

2
0R2J-GP

D2

LED-G-106-GP
A

D9

LED-G-106-GP
A

D46

LED-G-106-GP
A

D7
24

HDD_LED#_5

R21 2
0R2J-GP

24 CDROM_LED#_5

MEDIA_LED#

34
34
34
34
29

on KB Cover

on Front Panel

LED-G-106-GP
A

D44
DC_BATFULL#

1 R376
2
100R2F-L1-GP-U

BAW56PT-U

on Front Panel

5V_S5

Dummy when use SATA

LED-Y-22
2

BLT_LED#

NUM_LED#
CAP_LED#
MAIL_LED#
BLT_LED#

5V_S0

R579
470R2J-2-GP
2

D47
2

on Front Panel

1
LED-B-27-U-GP

WLAN_LED#

STDBY_LED#

34 STDBY_LED#
34 CHARGE_LED#
34 DC_BATFULL#

CHARGE_LED#

on Front Panel

1 R377
2
100R2F-L1-GP-U

D45

LED-Y-22
2

on Front Panel

D43

LED-Y-22
2

on Front Panel

1 R375
2
100R2F-L1-GP-U

5V_S5

www.kythuatvitinh.com
34 FRONT_PWRLED#

DY

RC2

NUM_LED#
CAP_LED#
MAIL_LED#
MEDIA_LED#

1
2
3
4

SRC100P50V-2-GP
8
7
6
5

on KB cover

-2 0408

LED

Button

PROGRAM CAPS

POWER1 E-MAIL INTERNET e-BTN

DY

RC11

WLAN_LED#
STDBY_LED#
BLT_LED#
CHARGE_LED#

1
2
3
4

SRC100P50V-2-GP
8
7
6
5

DY C646 SC100P50V2JN-U

DC_BATFULL#

NUM

HDD

Front panel

LED

Button

Charger:
Green : DC only with Battery full with DC
Orange : Charging
Orange Blink : Battery low

BlutTooth Wireless Charger Power2

DY C512 SC100P50V2JN-U
FRONT_PWRLED# 1
2

Power2:
Green : S0
Orange : S3
Orange Blinking : Enter S4

(Please See M.E. drawing LED position)

2

C658

SC10U35V0ZY-1GP
2
1
2
1

C667 C668

C662
SCD1U25V3ZY-3GP

1
2
SC100P50V2JN-U

DCBATOUT

3D3V_S0

U7

1 R48

LCDVDD_ON_1
2
1KR2J-1-GP

ODD CHANNEL

OUT
GND
ON/OFF#

IN
GND
IN

6
5
4
1

13,57 LCD_VDD_ON

1
2
3

EVEN CHANNEL

LCD_TXBCLK+ 13,57
LCD_TXBCLK- 13,57
LCD_TXBOUT2+ 13,57
LCD_TXBOUT2- 13,57
LCD_TXBOUT1+ 13,57
LCD_TXBOUT1- 13,57
LCD_TXBOUT0+ 13,57
LCD_TXBOUT0- 13,57
LCD_TXACLK+ 13,57
LCD_TXACLK- 13,57
LCD_TXAOUT2+ 13,57
LCD_TXAOUT2- 13,57
LCD_TXAOUT1+ 13,57
LCD_TXAOUT1- 13,57
LCD_TXAOUT0+ 13,57
LCD_TXAOUT0- 13,57

LCDPOWER_S0

DY

C23
C69
SCD1U25V3ZY-3GP

AAT4280IGU-3-T1GP

SB 0202

34 BRIGHTNESS
FPBACK
1
2
SC100P50V2JN-U

34

DY

Layout 40 mil

SCD1U25V3ZY-3GP

13,50 EDID_CLK
13,50 EDID_DAT

3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

LCD POWER

C31

SC1U10V3KX-3GP
2

2
3D3V_S0

4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
41

C22

C44

SCD1U25V3ZY-3GP

LCD1
42
2

LCDPOWER_S0

SC10U10V5ZY-1GP
2
1

LCD CONN

C70
SC1U10V3KX-3GP

<Variant Name>

ACES-CONN40A-GP

Wistron Corporation

20.F0737.040

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
1ST 20.D0198.108 - 2ND 20.F0687.040
Title

LCD / LEDs
Size
A3

Document Number

Rev

SA

Bolsena-E

Date: Thursday, October 13, 2005

Sheet
E

16

of

58

5V_S5

PCIE_VDDR

1D8V_S0

1 L24
2
0R0603-PAD

2
2

150R2F-1-GP PCIE_CALRP
150R2F-1-GP PCIE_CALRN

G27
H27

PCIE_CALRP
PCIE_CALRN

1 R483

4K12R2F-GP PCIE_CALI

G28

PCIE_CALI

R30

PCIE_PVDD

F26
R29
G26
P26
K26
L26
P28
N26
P27

PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR

PCIE_PVDD

PCIE_VDDR

PCIRST#
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_AD[31..0]

14
7

21,25,27,29,30

3D3V_S0

DY

PCB-Ver
3D3V_S0

R92
DUMMY-R2

PCI_GNT#5
PCI_GNT#6

R430
DUMMY-R2

1 R482
1 R473

A11, A12 4K53 1%

A21, A22 5K5 1%
A23 4K12 1%
PA_IXP400AC10.PDF

C725
2

SC1U10V3KX-3GP

C727
2

SC10U10V5ZY-1GP

C728

SCD1U16V2ZY-2GP

MLB-201209-21-GP

AJ7
W3
Y2
W4
Y3
V1
Y4
V2
W2
AA4
V4
AA3
U1
AA2
U2
AA1
U3
T4
AC1
R2
AD4
R3
AD3
R4
AD2
P2
AE3
P3
AE2
P4
AF2
N1
AF1
V3
AB4
AC2
AE4
T3
AC4
AC3
T2
U4
T1
AB2
AB3
AF4
AF3
AG2
AG3
AH1
AH2
AH3
AJ2
AK2
AJ3
AK3
AG4
AH4
AJ4
AG1
AB1

L23
1

PCIRST#
AD0/ROMA18
AD1/ROMA17
AD2/ROMA16
AD3/ROMA15
AD4/ROMA14
AD5/ROMA13
AD6/ROMA12
AD7/ROMA11
AD8/ROMA9
AD9/ROMA8
AD10/ROMA7
AD11/ROMA6
AD12/ROMA5
AD13/ROMA4
AD14/ROMA3
AD15/ROMA2
AD16/ROMD0
AD17/ROMD1
AD18/ROMD2
AD19/ROMD3
AD20/ROMD4
AD21/ROMD5
AD22/ROMD6
AD23/ROMD7
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
CBE0#/ROMA10
CBE1#/ROMA1
CBE2#/ROMWE#
CBE3#
FRAME#
DEVSEL#/ROMA0
IRDY#
TRDY#/ROMOE#
PAR/ROMA19
STOP#
PERR#
SERR#
REQ0#
REQ1#
REQ2#
REQ3#/PDMA_REQ0#
REQ4#/PLL_BP33/PDMA_REQ1#
REQ5#/GPIO13
REQ6#/GPIO31
GNT0#
GNT1#
GNT2#
GNT3#/PLL_BP66/PDMA_GNT0#
GNT4#/PLL_BP50/PDMA_GNT1#
GNT5#/GPIO14
GNT6#/GPIO32
CLKRUN#
LOCK#

R93
DUMMY-R2

RN15
SRN10KJ-L1-GP-U

R429
DUMMY-R2

1D8V_S0

EPSON
KDS

PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N

PCLK_R5C832 21,27
CLK33_CBUS 25
CLK33_LAN 21,30
CLK33_MINI 21,29
CLK33_KBC 21,34
CLK33_SIO 21,37
CLK33_LPCROM 21

MAIN SOURCE: 82.30001.031

2ND SOURCE: 82.30001.341

PCIE_PVDD

M29
N29
M28
N28
J29
K29
J28
K28

PCLK_R5C832
CLK33_CBUS
CLK33_LAN
CLK33_MINI
CLK33_KBC
CLK33_SIO
CLK33_LPCROM

PCIE_TX0P_SB
PCIE_TX0N_SB
PCIE_TX1P_SB
PCIE_TX1N_SB

PCI_CLK9_R
PCI_CLK9_FB

CLK32_G791 22

TSLCX08MTCX-GP

12
12
12
12

PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N

R280 2
10R2J-2-GP

1
R451

32K_X2

PCIE_RCLKP
PCIE_RCLKN

M30
N30
K30
L30
H30
J30
F30
G30

3D3V_S0
2
8K2R2J-3-GP

2
1

32K_X1

2 C760
SC12P50V2JN-LGP
CHANGE TO - 3.9P -> 78.3R974.1F1
SB

L27
M27

10
9
8
7
6

TX0P
TX0N
TX1P
TX1N

PCI_CLK1_R
PCI_CLK2_R
PCI_CLK3_R
PCI_CLK4_R
PCI_CLK5_R
PCI_CLK6_R
PCLK_R5C833_R

RN102 SRN22J-2-GP
CLK33_CBUS
8
CLK33_LAN
7
CLK33_MINI
6
CLK33_KBC
5
CLK33_SIO
5
PCLK_R5C832
6
CLK33_LPCROM
7
8
RN98
SRN22J-2-GP
PCI_CLK8 21
1 R459
2
22R2J-2-GP
1
2
SC100P50V2JN-U
C724

1
2
3
4
4
3
2
1

1
2
3
4
5

SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP

PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
PCICLK7
PCICLK8
PCICLK9
PCICLK_FB

L4
L3
L2
L1
M4
M3
M2
M1
N4
N3
N2

3D3V_S0

PCIE_RX0P_SB
PCIE_RX0N_SB
PCIE_RX1P_SB
PCIE_RX1N_SB

2
2
2
2

20MR3-GP

X-32D768KHZ-38GPU

12
12
12
12

R479
20MR3-GP

1
1
1
1

PCI CLKS

X7

C736
C733
C740
C737

A_RST#

PCI INTERFACE

R488

3 SBSRC_CLK
3 SBSRC_CLK#

AH8

U33A

1 OF 4

PCI EXPRESS INTERFACE

A_RST#
CHANGE TO - 3.9P -> 78.3R974.1F1
2 C742
SC12P50V2JN-LGP

20,34,38,39,45,56 PM_SLP_S3#
21 RTC_CLK
U55A

?3.9p need app PN

32K suspend clock output

R83
8K2R2J-3-GP

DY

RN13
SRN10KJ-L1-GP-U
1
2
3
4
5

10
9
8
7
6

1
2

SCD1U16V2ZY-2GP

1
2

SCD1U16V2ZY-2GP

3D3V_S0

SB_CPUSTP#
SB_PCISTP#
INT_PIRQA#
INT_PIRQB#
INT_PIRQC#
INT_PIRQD#
INT_PIRQE#
INT_PIRQF#
INT_PIRQG#
INT_PIRQH#

TP86
TP85

SRN10KJ-L3-GP

12

11

RSTDRV#_R

1 R8

2
33R2J-2-GP

RSTDRV#_5 24

TSAHCT125PW-GP

B2

X1

32K_X2

B1

X2

PCIRST# 3V to 5V level shift for HDD & CDROM

SB400 asserts PLTRST# to reset
devices on the platform.
3D3V_S5

TP92
TP107
TP18
TP93
TP91

R307 2

14

U39A

6,13

R298

PLT_RST#_R

2
33R2J-2-GP

LDT_STP# TP94
TP11
TP12
LPC_RST# 13,34,37,49
13 ALLOW_LDTSTOP
6 SB_CPUPWRGD
TP14

SB_C29
SB_A28
H_NMI
FWH_INIT#
SB_D29
SB_B30
H_A20M#
H_FERR#
H_DPRSLP#

3D3V_S5
RTC_AUX_S5

SERIRQ

R296 2
10R2J-2-GP

PCIRST_BUF# 25,27,29,30
2

TSLCX08MTCX-GP
RTC1

DY
R295 2

AG25
AH25
AJ25
AH24
AG24
AH26
AG26

RN12

AK27

RTCCLK
RTC_IRQ#/ACPWR_STRAP

C2
F3

VBAT
RTC_GND

A2
A1

Secondary PCI Bus reset signal.

LPC_LFRAME# 21,34,37
LPC_LDRQ0# 37
3D3V_AUX_S5

LPC_LDRQ0#
LPC_LDRQ1#

P_SERIRQ 27,34,37

Close to chip 3D3V_S0

RTC_CLK 21
AUTO_ON# 21
VBAT

C761

4
1

PCI_RST#

PCI_LOCK#

C762

1
LPC_LAD0 2
LPC_LAD3 3
LPC_LAD2 4
LPC_LAD1 5

U58
BAT54C-1-GP

3D3V_S0

SRN10KJ-L1-GP-U
1

EC71
SC470P50V2KX

Wistron Corporation

RTC_AUX_S5

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

ATI-SB450 (1 of 5) PCI, PCIE

Size
A3

MLX-CON3-9-GP
20.D0198.103

Document Number

Rev

Bolsena-E

Date: Thursday, October 13, 2005

B

LPC_LDRQ1#
LPC_LDRQ0#
P_SERIRQ

SC1U10V3KX-3GP

0R2J-GP
A

10
9
8
7
6

RTC_AUX_S5_1

1
1KR2J-1-GP

TP10

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

14

U39B

4
PCIRST#

CPU_PG
INTR/LINT0
NMI/LINT1
INIT#
SMI#
SLP#/LDT_STP#
IGNNE#
A20M#
FERR#
STPCLK#/ALLOW_LDTSTP
LDT_PG/SSMUXSEL/GPIO0
DPRSLPVR
BMREQ#
LDT_RST#

LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
LDRQ1#

R510

R297
8K2R2J-3-GP

DY

C29
A28
C28
B29
D29
E4
B30
F28
E28
E29
D25
E27
D27
D28

2
3
5

13 BMREQ#
6 LDT_RST#
1

PCI_GNT#3
PCI_GNT#4
PCI_GNT#5
PCI_GNT#6

DY

TSLCX08MTCX-GP

PCI_GNT#0 29
PCI_GNT#1 25
PCI_GNT#2 30
PCI_GNT#3 27
PM_CLKRUN# 25,27,29,30,34,37

LPC_LAD[0..3] 34,37

0R2J-GP

A_RST#

32K_X1

PCI_REQ#3
PCI_REQ#4
PCI_REQ#5
PCI_REQ#6

13

14
A_RST#

U3D

INT_PIRQE#
INT_PIRQF#
INT_PIRQG#
INT_PIRQH#

CPU_STP#/DPSLP_3V#
DPSLP_OD#/GPIO37
INTA#
INTB#
INTC#
INTD#
INTE#/GPIO33
INTF#/GPIO34
INTG#/GPIO35
INTH#/GPIO36

25,27
25,29
27
30

AJ8
AK7
AG5
AH5
AJ5
AH6
AJ6
AK6
AG7
AH7

PCI_CBE#0 25,27,29,30
PCI_CBE#1 25,27,29,30
PCI_CBE#2 25,27,29,30
PCI_CBE#3 25,27,29,30
PCI_FRAME# 25,27,29,30
PCI_DEVSEL# 25,27,29,30
PCI_IRDY# 25,27,29,30
PCI_TRDY# 25,27,29,30
PCI_PAR 25,27,29,30
PCI_STOP# 25,27,29,30
PCI_PERR# 25,27,29,30
PCI_SERR# 25,27,29,30
PCI_REQ#0 29
PCI_REQ#1 25
PCI_REQ#2 30
PCI_REQ#3 27

5V_S0

PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS

SCD1U16V2ZY-2GP
2

INT_PIRQD#
INT_PIRQC#
INT_PIRQB#
INT_PIRQA#

H28
F29
H29
H26
F27
G29
L29
J26
L28
J27
N27
M26
K27
P29
P30

LPC

SCD1U16V2ZY-2GP

DY

C734

RTC

10
9
8
7
6

DY

C183

CPU

3D3V_S0

1
2
3
4
5

C233

XTAL

RP1

INT_PIRQG#
INT_PIRQE#
INT_PIRQF#
INT_PIRQH#

1
2

SCD1U16V2ZY-2GP

C179

SC22U6D3V5MX-2GP

DY

C184
SCD1U16V2ZY-2GP

www.kythuatvitinh.com
C735

SA

Sheet
E

17

of

58

24
24

SATA_RXN0
SATA_RXP0

1
1

SCD01U50V3KX-4GP SATA_TP0 AK22

SCD01U50V3KX-4GP SATA_TN0 AJ22

SATA_TX0+
SATA_TX0-

2 C630
2 C629

SCD01U50V3KX-4GP SATA_RN0 AK21

SCD01U50V3KX-4GP SATA_RP0 AJ21

SATA_RX0SATA_RX0+

AK19
AJ19

SATA_TX1+
SATA_TX1-

AK18
AJ18

SATA_RX1SATA_RX1+

AK14
AJ14

SATA_TX2+
SATA_TX2-

AK13
AJ13

SATA_RX2SATA_RX2+

AK11
AJ11

SATA_TX3+
SATA_TX3-

AK10
AJ10

SATA_RX3SATA_RX3+

AJ15

SATA_CAL

AJ16
AK16

SATA_X1
SATA_X2

Close to SouthBridge

Close to SouthBridge
1
1

R431 2
1KR2F-3-GP
2 C700
SCD01U50V3KX-4GP
SATA_X1
SATA_X2

DY

16

SATA_LED#

AK8

1D8V_SP_S0
1D8V_SX_S0

PRIMARY ATA 66/100

SATA_TXP0
SATA_TXN0

2 C704
2 C703

SERIAL ATA

24
24

1
1

SATA_ACT#

AH15
AH16

PLLVDD_SATA
XTLVDD_SATA

AG10
AG14
AH12
AG12
AG18
AG21
AH18
AG20

AVDD_SATA
AVDD_SATA
AVDD_SATA
AVDD_SATA
AVDD_SATA
AVDD_SATA
AVDD_SATA
AVDD_SATA

AG9
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AH9
AG11
AG15
AG17
AG19
AG22
AG23
AF9
AH17
AH23
AH13
AH20
AK9
AJ12
AK17
AK23

AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA

2 OF 4

U55B

PIDE_IORDY
PIDE_IRQ
PIDE_A0
PIDE_A1
PIDE_A2
PIDE_DACK#
PIDE_DRQ
PIDE_IOR#
PIDE_IOW#
PIDE_CS1#
PIDE_CS3#

AD30
AE28
AD27
AC27
AD28
AD29
AE27
AE30
AE29
AC28
AC29

PIDE_D0
PIDE_D1
PIDE_D2
PIDE_D3
PIDE_D4
PIDE_D5
PIDE_D6
PIDE_D7
PIDE_D8
PIDE_D9
PIDE_D10
PIDE_D11
PIDE_D12
PIDE_D13
PIDE_D14
PIDE_D15

AF29
AF27
AG29
AH30
AH28
AK29
AK28
AH27
AG27
AJ28
AJ29
AH29
AG28
AG30
AF30
AF28

SIDE_IORDY
SIDE_IRQ
SIDE_A0
SIDE_A1
SIDE_A2
SIDE_DACK#
SIDE_DRQ
SIDE_IOR#
SIDE_IOW#
SIDE_CS1#
SIDE_CS3#

PIDE_IORDY 24
PIDE_IRQ14 24
PIDE_A0 24
PIDE_A1 24
PIDE_A2 24

R361
2

0R0402-PAD
1

PIDE_DACK# 24
PDACK# 21

PIDE_DREQ 24
PIDE_IOR# 24
PIDE_IOW# 24
PIDE_CS#0 24
PIDE_CS#1 24
PIDE_D0
PIDE_D1
PIDE_D2
PIDE_D3
PIDE_D4
PIDE_D5
PIDE_D6
PIDE_D7
PIDE_D8
PIDE_D9
PIDE_D10
PIDE_D11
PIDE_D12
PIDE_D13
PIDE_D14
PIDE_D15

also strap function

PIDE_D[15..0]

24

V29
T27
T28
U29
T29
V30
U28
W29
W30
R27
R28

SIDE_IORDY 24
SIDE_IRQ15 24
SIDE_A0 24
SIDE_A1 24
SIDE_A2 24
SIDE_DACK# 24
SIDE_DREQ 24
SIDE_IOR# 24
SIDE_IOW# 24
SIDE_CS#0 24
SIDE_CS#1 24

1D8V_SATA_S0
SATA_X1
1

R102
0R2J-GP

R433
0R2J-GP

Dummy when use SATA

1D8V_S0

R105 2
0R5J-5-GP

1D8V_S0

AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA
AVSS_SATA

AG13
AH22
AK12
AH11
AJ17
AH14
AH19
AJ20
AH21
AJ9
AG16
AH10
AJ23
AK15
AK20

1D8V_SP_S0

L4
2
0R3J-3-GP

SIDE_D0
SIDE_D1
SIDE_D2
SIDE_D3
SIDE_D4
SIDE_D5
SIDE_D6
SIDE_D7
SIDE_D8
SIDE_D9
SIDE_D10
SIDE_D11
SIDE_D12
SIDE_D13
SIDE_D14
SIDE_D15

1D8V_S0

C129
SCD1U50V3ZY-GP

SCD1U50V3ZY-GP

1
SCD1U50V3ZY-GP

C128

SCD1U50V3ZY-GP

1
C160
2

C155
2

C127
SC10U10V5ZY-1GP

1D8V_SATA_S0

V28
W28
Y30
AA30
Y28
AA28
AB28
AB27
AB29
AA27
Y27
AA29
W27
Y29
V27
U27

SIDE_D[15..0]

24

1D8V_SX_S0

L5
2
0R3J-3-GP

C157
SC2D2U16V5ZY-GP

<Variant Name>

Dummy when use IDE

SIDE_D0/GPIO15
SIDE_D1/GPIO16
SIDE_D2/GPIO17
SIDE_D3/GPIO18
SIDE_D4/GPIO19
SIDE_D5/GPIO20
SIDE_D6/GPIO21
SIDE_D7/GPIO22
SIDE_D8/GPIO23
SIDE_D9/GPIO24
SIDE_D10/GPIO25
SIDE_D11/GPIO26
SIDE_D12/GPIO27
SIDE_D13/GPIO28
SIDE_D14/GPIO29
SIDE_D15/GPIO30

2 C702
SC27P50V2JN-2-GP

XTAL-25MHZ-70GP

SATA_X1

R432
10MR2J-L-GP

2 C701
SC27P50V2JN-2-GP

X6

SECONDARY ATA 66/100

SATA_X2

SERIAL ATA POWER

www.kythuatvitinh.com
1D8V_SATA_S0

C159
SC2D2U16V5ZY-GP

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Capacitor PLACE NEAR Capacitor PLACE NEAR

THE ACCORDED BALLS
THE ACCORDED BALLS

ATI-SB400 (2 of 5) IDE
Size
A3

Dummy when use IDE

Document Number

Rev

Bolsena-E

Date: Thursday, October 13, 2005

A

Sheet
E

SA
18

of

58

1D8V_S0

1
2

2
SCD1U16V2ZY-2GP

1
2

C170

DY

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

1
C156
2

C182
2

C203

DY

C171

DY

SCD1U16V2ZY-2GP

DY

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C738

3D3V_SB_S0

DY

SCD1U16V2ZY-2GP

C177
2

SCD1U16V2ZY-2GP

C169

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C202

1
2

SCD1U16V2ZY-2GP

C154

1D8V_S0

1
2

C232
SCD1U16V2ZY-2GP

DY

C173
SCD1U16V2ZY-2GP

1
2

SCD1U16V2ZY-2GP

C698

C699
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C743

SCD1U16V2ZY-2GP

DY

C145

SCD1U16V2ZY-2GP

C766

SCD1U16V2ZY-2GP

C705

SCD1U16V2ZY-2GP

DY

C144

SCD1U16V2ZY-2GP

C726

SCD1U16V2ZY-2GP

C143

3D3V_SB_S5

3D3V_SB_S5

1D8V_S5

R114 1
2
0R0805-PAD

1D8V_S5

C221

1D8V_S5

SCD1U16V2ZY-2GP

C222
SCD1U16V2ZY-2GP

DY

C239

SCD1U16V2ZY-2GP
2

1
2

SCD1U16V2ZY-2GP

DY

C240

C238
SCD1U16V2ZY-2GP

SC10U10V5ZY-1GP

C180

3D3V_S5

DY

1D8V_S5

D33
1

2
1D2V_S0

RB751V-40-1-GP

1D8V_S5

1 R489
2
0R0402-PAD

D30

C750
2
1

1
C765

DY

SCD1U16V2ZY-2GP

5V_S0

SC1U10V3KX-3GP
2

C773

SC10U10V5ZY-1GP
2

C779

SCD1U16V2ZY-2GP
2

SCD1U16V2ZY-2GP

C231

1
2

C226
SCD1U16V2ZY-2GP

DY

SCD1U16V2ZY-2GP

C228
2

SCD1U16V2ZY-2GP

C230
2

SCD1U16V2ZY-2GP

DY

C223
2

C225
SCD1U16V2ZY-2GP

DY

SCD1U16V2ZY-2GP

C778
2

SC10U10V5ZY-1GP

1
2

C777

1D8VAVDDCK_S0

L26
1
2
MLB-201209-21-GP

RB751V-40-1-GP
V5_VREF

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

E12
E15
E18
E19
E22
K4
J1
J4
R5
T5
F4
P1
L5
M5
W1
AK25
W5
AJ24
R26
E26
Y5
T26
AF5
T30
AC5
W26
AG8
AF8
AB26
AK5
AC26
AD1
AF23
AF26
A29
AB30
AJ1
AJ30
P12
R12
T12
U12
P13
R13
T13
U13
M14
N14
P14
R14
T14
U14
V14
W14
M15
N15
P15
R15
T15
U15
V15
W15
M16
N16
P16
R16
T16
U16
V16
W16
M17
N17
P17
R17
T17
U17
V17
W17
P18
R18
T18
U18
P19
R19
T19
U19

CPU_1D2V C30

S5_3.3V
S5_3.3V
S5_3.3V
S5_3.3V
S5_3.3V
S5_3.3V

S5_1.8V
S5_1.8V
USB_PHY_1.8V
USB_PHY_1.8V
USB_PHY_1.8V
USB_PHY_1.8V
S5_1.8V
S5_1.8V
CPU_PWR

V5_VREF AG6

V5_VREF

A24
B24

AVDDCK
AVSSCK

A4
A8
B28
E30
E23
C1
E5
G5
F1
H5
E8
E11

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

MIN 4.5
NORMAL 5.0
MAX 5.5

Wistron Corporation

SCD1U16V2ZY-2GP

RB751V-40-1-GP

C142
2

2
2

SC1U10V3KX-3GP

C717
D31
1

<Variant Name>

V5_VREF

2
1KR2J-1-GP

1 R440
3D3V_S0

Vf = 0.38v (@1mA)
1v (@40mA)

A3
A7
E6
E7
E1
F5

E9
E10
E13
E14
E16
E17
E20
E21

3D3V_S5

1D8V_S0

DY

M12
N12
V12
W12
M13
N13
V13
W13
M18
N18
V18
W18
M19
N19
V19
W19

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

www.kythuatvitinh.com

C161

DY

SCD1U16V2ZY-2GP

SC10U10V5ZY-1GP

C722

C721

3D3V_S0
R450 1
2
0R0805-PAD

3 OF 4

U55C
D30
A30
J5
K1
K5
N5
R1
P5
Y1
U5
E24
E25
V5
U26
AA5
V26
AK4
Y26
AF25
AB5
AA26
AD5
AD26
AE1
AE5
AF6
U30
AF24
AF7
AE26
AC30
AK1
AK26
AK30

SCD1U16V2ZY-2GP

1
2

SCD1U16V2ZY-2GP

DY

C719

C780
2

SCD1U16V2ZY-2GP

C181
2

SCD1U16V2ZY-2GP

C165

DY

C158

DY

C172

SCD1U16V2ZY-2GP

SC10U10V5ZY-1GP

C204
2

DY

SC10U10V5ZY-1GP

C178

SCD1U16V2ZY-2GP

3D3V_SB_S0

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

ATI-SB400 (3 of 5) POWER
Size
A3

Document Number

Rev

SA

Bolsena-E

Date: Thursday, October 13, 2005

Sheet
E

19

of

58

8
7
6
5

3D3V_S5
3D3V_S5
3D3V_S0
RN107

RN19
SRN10KJ-6-GP

SRN10KJ-5-GP

DY DY

34,44 RSMRST#_KBC

A23
B23
SIO_CLK_SB
TP87
GPIO1
GPIO6

3D3V_S5

39,41 VRM_PWRGD
AGP_STP#
10KR2J-2-GP
1 R131
2
AGP_BUSY#
10KR2J-2-GP
1 R130
2
34 KBC_SLP_WAKE
32
SPKR_SB
SMBC_SB
SMBC_SB_1
R507
33R2J-2-GP
1
2
SMBD_SB
SMBD_SB_1
1 R508
2 33R2J-2-GP
DDC1_SCL
DDC1_SDA
DDC2_SCL
DDC2_SDA
10KR2J-2-GP
1 R476
2
R465
10KR2J-2-GP
1 DY
2

SIO_CLK
ROM_CS#/GPIO1
GHI#/GPIO6
VGATE/GPIO7
GPIO4
GPIO5
FANOUT0/GPIO3
SPKR/GPIO2
SCL0/GPOC0#
SDA0/GPOC1#
DDC1_SCL/GPIO9
DDC1_SDA/GPIO8
DDC2_SCL/GPIO11
DDC2_SDA/GPIO12

A15
B15
USB_PCOMP
1 R503
2
C15
11K8R3F-GP
USB_VREFOUT TP17
D16
USB_TE1
TP16
C16
USB_TE0
TP15
D15
B8
USB_OC#01 23
C8
USB_OC#4
B6
USB_OC#2
C7
USB_OC#2 23
USB_OC#3
B7
USB_OC#3 23
AZ_RST#_ICH
A6
USB_OC#6 1 R499
2 ECSWI#
B5
LUSB1#
0R0402-PAD
TP19
A5

USB_HSDP7+
USB_HSDM7-

A11 USB_PP7
B11 USB_PN7

TP103
TP104

USB_HSDP6+
USB_HSDM6-

A10 USB_PP6
B10 USB_PN6

TP101
TP102

USB_HSDP5+
USB_HSDM5-

A14 USB_PP5
B14 USB_PN5

USB_HSDP4+
USB_HSDM4-

A13 USB_PP4
B13 USB_PN4

USB_PP4 23
USB_PN4 23

USB_HSDP3+
USB_HSDM3-

A18 USB_PP3
B18 USB_PN3

USB_PP3 23
USB_PN3 23

USB_HSDP2+
USB_HSDM2-

A17
B17

USB_PP2 23
USB_PN2 23

USB_HSDP1+
USB_HSDM1-

A21
B21

USB_PP1 23
USB_PN1 23

USB_HSDP0+
USB_HSDM0-

A20
B20

USB_PP0 23
USB_PN0 23

AVDDTX_0
AVDDTX_1
AVDDTX_2
AVDDTX_3

C21
C18
D13
D10

AVDDRX_0
AVDDRX_1
AVDDRX_2
AVDDRX_3

D20
D17
C14
C11

AVDDC

A16

RP2
USB_OC#4
USB_OC#01
USB_OC#2
3D3V_S5

3D3V_S5
10
9 USB_OC#6
LUSB1#
8
7USB_OC#3
6

1
2
3
4
5
SRN10KJ-L3-GP

TP105
TP106

BlueTooth

www.kythuatvitinh.com
3D3V_S5 R116 1

21 SPDIF_OUT_STRAP

32 ACZ_RST#
23 ACZ_RST#_MDC

R478 1
R470 1

AZ_RST#_ICH

2 33R2J-2-GP
2 33R2J-2-GP
1 R471

10KR2J-2-GP

DY

1
2

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

1
2

DY

C224
SC10U10V5ZY-1GP

3D3V_AVDDC
L25
1
2
MLB-201209-21-GP

4
3

3D3V_S0

C241

C227
SCD1U16V2ZY-2GP

R115 2

10KR2J-2-GP

DY

DY

1 R457

AC_BITCLK
AC_SDOUT
ACZ_SDIN0
ACZ_SDIN1
ACZ_SDIN2
AC_SYNC
AC_RST#
SPDIF_OUT

G1
G2
H4
G3
4K7R2J-2-GP
1
G4
H1
2 10KR2J-2-GP H3
H2

C229

32 ACZ_SDATAIN0
23 ACZ_SDATAIN1

C236

C772
C764
C763
SC10U10V5ZY-1GP
SC1U10V3KX-3GP
SCD1U16V2ZY-2GP
2

1 4K7R2J-2-GP

R472 2
21 AC97_DOUT

B16

A9
A12
A19
A22
B9
B12
B19
B22
C9
C10
C12
C13
C17
C19
C20
C22
D9
D11
D12
D14
D18
D19
D21
D22

10KR2J-2-GP

DY
2

USB PWR

1 R463

AVSSC

AVSS_USB
AVSS_USB
AVSS_USB
AVSS_USB
AVSS_USB
AVSS_USB
AVSS_USB
AVSS_USB
AVSS_USB
AVSS_USB
AVSS_USB
AVSS_USB
AVSS_USB
AVSS_USB
AVSS_USB
AVSS_USB
AVSS_USB
AVSS_USB
AVSS_USB
AVSS_USB
AVSS_USB
AVSS_USB
AVSS_USB
AVSS_USB

C265

3D3V_AVDDC

10KR2J-2-GP

DY

1 L7
2
0R0603-PAD

SC10U10V5ZY-1GP

AZ_SYNC_ICH

AVDD_USB

3D3V_S5

1 R464

AZ_BITCLK
48M_AZ
AZ_SDOUT
AZ_SYNC

2 33R2J-2-GP
2 33R2J-2-GP

J2
K3
J3
K2

AVDD_USB

2 47R2J-L2-GP ACZ_DOUT_ICH
2 33R2J-2-GP

R467 1
R462 1

32 ACZ_SYNC
23 ACZ_SYNC_MDC

AZ_BITCLK_ICH

(NTO USED)

1
2
3
4

2 33R2J-2-GP
2 22R2J-2-GP

R477 1
R468 1

32 ACZ_DOUT
23 ACZ_DOUT_MDC

DDC1_SCL
DDC1_SDA
DDC2_SCL
DDC2_SDA

DY

R469 1
R466 1

32
AZ_BITCLK
23 ACZ_BITCLK_MDC

SRN10KJ-6-GP

B25
C25
C23
D24
D23
A27
C24
A26
B26
B27
C26
C27
D26

14M_X1/OSC
14M_X2

AC97

RN20

8
7
6
5

3D3V_S0

AK24

RSMRST#

48M_X1/USBCLK
48M_X2
USB_RCOMP
USB_VREFOUT
USB_ATEST1
USB_ATEST0
USB_OC0#/GPM0#
USB_OC1#/GPM1#
USB_OC4#/GPM4#
USB_OC2#/FANOUT1/LLB#/GPM2#
USB_OC3#/GPM3#
USB_OC5#/AZ_RST#/GPM5#
USB_OC6#/GEVENT6#
USB_OC7#/GEVENT7#

2
0R2J-GP

D1

3 SB_OSC_CLK

R504

2
SCD1U16V2ZY-2GP

ECSWI#

TALERT#/TEMP_ALERT#/GPIO10
BLINK/AZ_SDIN3/GPM6#
PCI_PME#/GEVENT4#
RI#/EXTEVNT0#
SLP_S3#
SLP_S5#
PWR_BTN#
PWR_GOOD
SUS_STAT#
TEST1
TEST0
GA20IN
KBRST#
SMBALERT#/THRMTRIP#/GEVENT2#
LPC_PME#/GEVENT3#
LPC_SMI#/EXTEVNT1#
S3_STATE/GEVENT5#
SYS_RESET#/GPM7#
WAKE#/GEVENT8#

USB INTERFACE

34 ECSCI#_KBC
34 ECSMI#_KBC
34 ECSWI#

34
34

TP13

GPM6#

ACPI/WAKE UP EVENTS

2
2
LUSB2#

S3_STATE
RI#
PM_SUS_STAT#
KA20GATE
KBRCIN#
ECSCI#_KBC
ECSMI#_KBC

PM_THRM#

CLK/RST

PM_SLP_S3#_SB
PME#_SB
PCIE_WAKE#
GPM6#
PM_SLP_S5#
PM_PWRBTN#
SYS_REST
PM_THRM#

3D3V_S5

1
1

R505
R127 1
1

10
9
8
7
6

SRN4K7J-9-GP-U1
RN18

DY

C6
D5
C4
30
PME#_SB
RI#
D3
PM_SLP_S3#_SB
B4
E3
34,45 PM_SLP_S5#
B3
34 PM_PWRBTN#
C3
39 SB_PWRGD
D4
34 PM_SUS_STAT# R480
1
2 10KR2J-2-GPF2
1 R481 2 10KR2J-2-GPE2
AJ26
KA20GATE
AJ27
KBRCIN#
LUSB2#
D6
ECSCI#
R128
0R0402-PAD
1
2
C5
ECSMI#
R506 2 0R0402-PAD
1
A25
S3_STATE
1 R500
2 0R2J-GP
D8
SYS_REST
DY
D7
PCIE_WAKE#
D2
22

R501 10KR2J-2-GP

4 OF 4

U55D

GPIO

R502 10KR2J-2-GP

2
1
10KR2J-2-GP2
1
10KR2J-2-GP
2
R87 10KR2J-2-GP2
R86 10KR2J-2-GP
1
2

1
2
3
4
5

4
3

1
2
3
4

CLK48_USB 3
KBC_SLP_WAKE
GPIO1
GPIO6

DY

RN39
SRN2K2J-1-GP

1
2

3D3V_S5

U30B

14
1

SMBC_SB
SMBD_SB

SMBC_SB
SMBD_SB

<Variant Name>

4
PM_SLP_S3#_SB

6
5

PM_SLP_S3# 17,34,38,39,45,56

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

TSLCX08MTCX-GP

3,8
3,8

Title

ATI-SB450 (4 of 5) USB GPIO

Size
A3

Document Number

Rev

SA

Bolsena-E

Date: Thursday, October 13, 2005

Sheet
E

20

of

58

3D3V_S5

4
3

4
3

R458
10KR2J-2-GP

1
2

SRN10KJ-5-GP

1
2

1
2

SRN10KJ-5-GP

SRN10KJ-5-GP

1
2

1
2

SRN10KJ-5-GP

LPC_LFRAME#
AUTO_ON#
AC97_DOUT
RTC_CLK
SPDIF_OUT_STRAP
CLK33_LAN
CLK33_MINI
CLK33_KBC
CLK33_SIO
CLK33_LPCROM
PCLK_R5C832
PCI_CLK8

RN97

Place these R close to

SouthBridge if possible

17,34,37
17
20
17
20
17,30
17,29
17,34
17,37
17
17,27
17

RN101
SRN10KJ-5-GP

RN103
RN100

DY

3D3V_S0

4
3

RN106

4
3

R85
10KR2J-2-GP

3D3V_S0 3D3V_S0
4
3

3D3V_S0

R84
10KR2J-2-GP

DY

ACPWRON

LFRAME#

REQUIRED SYSTEM STRAPS

STRAP
HIGH

Thermal Trip is not

enable as default

MANUAL
PWR ON

Optional

AC_SDOUT

USE DEBUG
STRAPS

SPDIF_OUT

RTC_CLK

SIO 24MHz
INTERNAL RTC

PCI_CLK3

PCI_CLK2

(CLK33_LAN)

(CLK33_MINI)

48MHZ
-Crytsal Pad

USB PHY
PWRDOWN
DISABLE

DEFAULT

DEFAULT

PCI_CLK5

PCI_CLK4

(CLK33_KBC)

(CLK33_LPCROM)

PCIE_CM_SET
HIGH

USB INT
PLL48

DEFAULT

48MHZClock
Input
Buffer

PCI_CLK6

(CLK33_SIO)

PCI_CLK7

(PCLK_R5C832)

PCI_CLK8

ROM TYPE
CPU I/F=K8

H,H=PCI (X Bus) ROM

DEFAULT

H,L=LPC ROM I

DEFAULT

www.kythuatvitinh.com
AUTO
PWR
ON

Thermal Trip is
STRAP enable as default
LOW

IGNORE
DEBUG
STRAPS
DEFAULT

Optional

EXTENNAL
RTC (NOT
SUPPORTED
W/IT8712)

SIO 48MHz

USB PHY
PWRDOWN
ENABLE

DEFAULT

USB
EXT.
48MHZ

PCIE_CM_SET
LOW

L,H=LPC ROM II

CPU I/F=P4

L,L=Firmware Hub ROM

Use External only

DEFAULT

3D3V_S0

PDACK#
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23

1
2

R443
10KR2J-2-GP

SRN10KJ-5-GP

DY

4
3

4
3
2

DEBUG STRAPS

1
2

RN16

1
2

R444
10KR2J-2-GP

SRN10KJ-5-GP

RN14
R362
1KR2J-1-GP

SRN10KJ-5-GP

18
17,25,27,29,30
17,25,27,29,30
17,25,27,29,30
17,25,27,29,30
17,25,27,29,30
17,25,27,29,30
17,25,27,29,30
17,25,27,29,30
17,25,27,29,30

RN17

1
2

RN95
SRN10KJ-5-GP

R360
10KR2J-2-GP

4
3

4
3

3D3V_S0

3D3V_S0

DY

PDACK#

STRAP
HIGH

USE LONG
RESET

PCI_AD31

RESERVED

PCI_AD30

RESERVED

PCI_AD29

RESERVED

PCI_AD28

RESERVED

PCI_AD27

PCI_AD26

BYPASS
PCI PLL

BYPASS IDE PLL USE

BYPASS ACPI BCLK
EEPROM
PCIE
STRAPS

PCI_AD25

PCI_AD24

PCI_AD23
RESERVED
<Variant Name>

DEFAULT

STRAP
LOW

USE SHORT
RESET

Wistron Corporation
USE PCI
PLL

USE ACPI
BCLK

DEFAULT

DEFAULT

USE
IDE
PLL
DEFAULT

USE
DEFAULT
PCIE
STRAPS

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

ATI-SB400 STRAPPING(5 of 5)

DEFAULT
Size
A3

Document Number

Rev

SA

Bolsena-E

Date: Thursday, October 13, 2005

Sheet

21

of

58

FAN1_VCC
5V_S0

DY

*Layout* 15 mil

C252
SC2200P50V2KX-2GP

R117
10KR2J-2-GP

FAN1_VCC

FAN1
4
1

S1N4148-U2
1

2
3
5

FAN1_FB
1

SCD1U25V3ZY-3GP

C243
SC10U10V5ZY-1GP

D11

C244

DY

*Layout* 15 mil

C185
SC100P50V2JN-3GP

MLX-CON3-9-GP
20.D0198.103

ME : 20.D0198.103
2nd:20.F0714.003
*Layout* 30 mil
5V_S0

U11

ALERT#
PR_HW_SDN#

15
13
3
2

ALERT#
THERM#
THERM_SET
RESET#

DGND
DGND

5
17

SGND1
SGND2
SGND3

8
10
12

2 G792_RST#
R144 0R2J-GP

THERMDN 6

R149
10KR2J-2-GP

G792SFUF-GP

C308

Q27
MMBT3904-U1

1
THERM_SYS_DN

SC470P50V2KX

3904 on system
(Thermal Sensor)

DY

THERM_SYS_DP

C275
SC2200P50V2KX-2GP

DY

THERMDP 6

To CPU

C274
SC2200P50V2KX-2GP

1
R122
10KR2J-2-GP

CLK32_G791 17
SMBD_G792 34
SMBC_G792 34

DXP1
DXP2
DXP3

1
4
14
16
18
19

7
9
11

FAN1
FG1
CLK
SDA
SCL
NC

R145
49K9R2F-L-GP

Setting T8 as
100 Degree

VCC
DVCC

RUNPWROK

6
20

C237
SCD1U25V3ZY-3GP

39

C246

SCD1U25V3ZY-3GP
2

V_DEGREE

1
2

R146
10KR2J-2-GP

C245

SC4D7U10V5ZY-3GP
2

5V_S0

C290
SCD1U25V3ZY-3GP

C253
SC2200P50V2KX-2GP
USE 0R2 63.R0034.1D1 WHEN UMA

R121 2
0R2J-GP

PM_THRM# 20

DY

G8

GAP-CLOSE

ALERT#

G7

HW thermal shut down tempature

setting 95 degree . Put Near CPU .

DXP1:108 Degree
DXP2:H/W Setting
DXP3:88 Degree

V_DEGREE
=(((Degree-72)*0.02)+0.34)*VCC

www.kythuatvitinh.com
SB

GAP-CLOSE

VGA_LOCAL_DP 50
VGA_LOCAL_DN 50

Dummy when G792 enhanced T8 function

T8_RSET:27K SET TO 80C
T8_RSET:20K SET TO 90C
T8_RSET:15K SET TO 100C

Dummy when use UMA

5V_AUX_S5

R161
150R2F-1-GP
U12
SET
GND
OUT#

VCC

HYST

5V_G709_AUX_S5

By Sourcer requset:
Main souce 74.00709.07F
Second souce
74.00710.03P
74.06509.07F
74.06510.A7P

C322
SC4D7U10V5ZY-3GP

R160
20KR2F-L-GP G709T1UF-GP

1
2
3

T8_SET

5V_G792_S0

R150 2
200R3-GP

5V_S0

Put under CPU Socket

3D3V_AUX_S5

PURE_THRM_SDN#

D40

6 CPU_THERMTRIP#

D36

RSMRST# 34

R513
10KR2J-2-GP

3D3V_AUX_S5

U59

BAW56PT-U

C785
SCD1U16V2ZY-2GP

BAW56PT-U
34

S5_ENABLE

GND

VCC

DY

DY

Wistron Corporation
Title

LOW3_OFF

2
48

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

S5PWR_ENABLE 43,45

NC7S08M5X-NL-GP

D38
(dummy, KBC already delay)

<Variant Name>

BAT54PT-GP

DY

R516 2
0R2J-GP

THERMAL G792
Size
Document Number
Custom

Rev

SA

Bolsena-E

Date: Thursday, October 13, 2005

Sheet

22

of

58

100 mil

5V_USB0_S0

5V_USB1_S0

USB PORT

5V_USB0_S0

5V_USB0_S0

G5258B2 Active Low 1.5A

A
D1
SSM5817PT-GP-U
U1

5V_S5

2
3

20 USB_PP0
RN26
3
4

2
1

5V_USB0_S0

SRN0J-6-GP

5V_USB2_S0

100 mil
5V_USB2_S0

OUT
OUT
OUT
FLG

R1

1KR2J-1-GP
2

G528P1UF-GP

6
1

USB_OC#3 20

TR3

USB_1USB_1+

SB 0127

2
3
4
5

DY

SKT-USB-97-UGP
3

L-63UH-GP68.03216.20B

1
2

C4
SC1000P50V2JN-N1

SCD1U25V3ZY-3GP

SE100U10VM-4GP

C5

SCD1U25V3ZY-3GP

C3

G528P1U Active Low

TC1

USB3

USB_1-

20 USB_PN1

USB_PWR_EN#

GND
IN
IN
EN#/EN

8
7
6
5

SKT-USB-97-UGP

22.10218.H01

USB_0+

1
2
3
4

2
3
4
5

L-63UH-GP68.03216.20B

C848
SC1000P50V2JN-N1

C463
SCD1U25V3ZY-3GP

SE100U10VM-4GP

TC14

USB_0USB_0+

DY

5V_S0

TR2

C429
2

C428

G546A2P1UF-GP

USB_OC#2 20

USB2
6
1

R200
1KR2J-1-GP
1
2
1

USB_OC#01 20

SE150U10VM-2GP

8
7
6
5

OC1#
OUT1
OUT2
OC2#

SCD1U25V3ZY-3GP

5V_USB1_S0

34 USB_PWR_EN#

GND
IN
EN1/EN1#
EN2/EN2#

R204
1KR2J-1-GP
1
2

SCD1U25V3ZY-3GP

100 mil

C836
SC1000P50V2JN-N1

C838
SCD1U25V3ZY-3GP

TC23

1
2
3
4

USB_0-

20 USB_PN0

U73

5V_S5

22.10218.H01
USB_1+

20 USB_PP1
RN30
3
4

2
1
5V_USB1_S0

SRN0J-6-GP

www.kythuatvitinh.com
USB_2-

20 USB_PN2

TR4

USB_2USB_2+

3D3V_S0

3D3V_BT_S0

U4

L-63UH-GP68.03216.20B

TPAD30

SC1000P50V2JN-N1
2

ME :20.D0198.108
2ND : 20.F0714.008

DY
DY

BT_COEX2 29
BT_COEX1 29

20

USB_3-

USB_PN3

TR1

EC5

20

USB_3+

USB_PP3

SKT-USB-97-UGP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

C671
R393
DUMMY-C2 100KR2J-1-GP
Title

USB / MDC / BLUETOOTH

<Variant Name>

20.F0582.012

2nd source: 20.F0604.012

ME : 22.10218.H01
2ND : 22.10245.H11

ACZ_BITCLK_MDC 20

AMP-CONN12A-GP
C16
SC22P50V2JN-4GP

SRN0J-6-GP

C669
SC1U10V3KX-3GP

AC_DIN1A_R

1 R25
2
39R2J-L-GP

22.10218.H01

2
1

4
6
8
10
12
17
18

2
3
5
7
9
11
MH2
16

2
3
4
5

RN77

MDC1

20 ACZ_SYNC_MDC
20 ACZ_SDATAIN1
20 ACZ_RST#_MDC

USB_3USB_3+

L-63UH-GP68.03216.20B

3
4

20 ACZ_DOUT_MDC

6
1

DY

3D3V_LAN_S5
15
14
2

5V_USB2_S0

USB1

DY

MDC 1.5 CONN

13
MH1
1

2
1
SRN0J-6-GP

DY

EC8

10

2 0R2J-GP
2 0R2J-GP

USB_PN4 20
USB_PP4 20

TP1
TPAD30

MLX-CON8-9-GP
20.D0198.108

R27
R23

1
1

3D3V_BT_S0

3
4

SC1000P50V2JN-N1

BT_AUX TP2
BT_GPIO2
BT_GPIO1
BT_LINK_LED

RN49

34 BLUETOOTH_EN

8
7
6
5
4
3
2

22.10218.H01

USB_2+

20 USB_PP2

AAT4250IGV-T1-GP

BLUE1

SKT-USB-97-UGP

OUT
IN
GND
NC#3 ON/OFF#

1
2
3

2
3
4
5

DY

3D3V_BT_S0

BLUETOOTH MODULE

USB4

6
1

Size
A3

Document Number

Rev

Bolsena-E

Date: Thursday, October 13, 2005

Sheet

SA
23

of

58

HDD
18 PIDE_D[15..0]

HDD1

CDROM

R363
4K7R2J-2-GP

PIDE_A2 18
PIDE_CS#1 18

ODD1

18 SIDE_D[15..0]

PWR TRACE 100mil

5V_S0

1
45

SIDE_D8
SIDE_D9
SIDE_D10
SIDE_D11
SIDE_D12
SIDE_D13
SIDE_D14
SIDE_D15

20.80175.044
CHANGE TO 20.80592.044

ME : 20.80592.044
(DIFFERENT FROM ORCAD P/N)

Dummy when use SATA

18 SIDE_DREQ
18 SIDE_IOR#
18 SIDE_DACK#

BAY_ID0
BAY_ID1

TPAD30 TP52
TPAD30 TP49

4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

51
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
52

5V_S0
RSTDRV#_5
SIDE_D7
SIDE_D6
SIDE_D5
SIDE_D4
SIDE_D3
SIDE_D2
SIDE_D1
SIDE_D0

PIDE_IORDY

R171
4K7R2J-2-GP

SIDE_IORDY

DY

SCD1U25V3ZY-3GP

2
1

5V_S0

C642

SC10U10V5ZY-1GP
2

R353
C643
4K7R2J-2-GP

5V_S0
1

16

18 PIDE_DREQ
18 PIDE_IOW#
18 PIDE_IOR#
18 PIDE_IORDY
18 PIDE_DACK#
18 PIDE_IRQ14
18 PIDE_A1
18 PIDE_A0
18 PIDE_CS#0
HDD_LED#_5

5V_S0
PIDE_D8
PIDE_D9
PIDE_D10
PIDE_D11
PIDE_D12
PIDE_D13
PIDE_D14
PIDE_D15

PIDE_D7
PIDE_D6
PIDE_D5
PIDE_D4
PIDE_D3
PIDE_D2
PIDE_D1
PIDE_D0

46
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3

44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4

17 RSTDRV#_5

SIDE_IOW# 18
SIDE_IORDY 18
SIDE_IRQ15 18
SIDE_A1 18
SIDE_A0 18
SIDE_CS#0 18

www.kythuatvitinh.com
18 SIDE_A2
18 SIDE_CS#1

A
1

TC17
ST22U6D3VBM

C626
SCD1U16V2ZY-2GP

1
2

1
2

C346

CDROM_LED#_5 16

R165 2
4K7R2J-2-GP

5V_S0

CSEL

SPD-CONN50-4R-14GP

20.80338.050

ME : 20.80338.050

1
2

TC18
ST100U6D3VDM-5

D24
B240LA-13F-GP

3D3V_S0

5V_S0

C347

SCD1U25V3ZY-3GP

SATA Connector

C337

SCD1U25V3ZY-3GP

For HDD & SATA both

SC10U10V5ZY-1GP

5V_S0

C631
SCD1U25V3ZY-3GP
2

SATA1
23
MH1
1
2
3
4
5
6
7

18 SATA_TXP0
18 SATA_TXN0
18 SATA_RXN0
18 SATA_RXP0

5V_S0

PWR TRACE 100mil

1

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
MH2
24
SPD-CON22-7-GP

20.F0777.022

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

ME : 20.F0777.022

HDD / CDROM / SATA

Size
A3

Dummy when use IDE

Document Number

Rev

SA

Bolsena-E

Date: Thursday, October 13, 2005

Sheet
E

24

of

58

CBB_D[0..15] 26
CBB_A[0..25] 26

3D3V_S0
3D3V_S0

3D3V_S0
RN117

CB1410_GBRST#

2
1

C908
C907
C912
SC1000P50V2JN-N1
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2

R569
4K7R2J-2-GP
R570

CB_MFUNC2
CB_MFUNC3
CB_MFUNC4
CB_MFUNC5

CB1410_GBRST#_1
C903

0R2J-GP
2

3D3V_S0

1
2
3
4

SCD1U16V2ZY-2GP

3D3V_S0

8
7
6
5

SRN10KJ-6-GP
VCC_ASKT_S0

90
126

8
7
6
5
RN116
SRN47KJ-L1-GP

REG#/CCBE3#
A25/CAD19
A24/CAD17
A23/CFRAME#
A22/CTRDY#
A21/CDEVSEL#
A20/CSTOP#
A19/CBLOCK#
A18/RFU
A17/CAD16
A16/CCLK#
A15/CIRDY#
A14/CPERR#
A13/CPAR
A12/CCBE2#
A11/CAD12
A10/CAD9
A9/CAD14
A8/CCBE1#
A7/CAD18
A6/CAD20
A5/CAD21
A4/CAD22
A3/CAD23
A2/CAD24
A1/CAD25
A0/CAD26
D15/CAD8
D14/RFU
D13/CAD6
D12/CAD4
D11/CAD2
D10/CAD31
D9/CAD30
D8/CAD28
D7/CAD7
D6/CAD5
D5/CAD3
D4/CAD1
D3/CAD0
D2/RFU
D1/CAD29
D0/CAD27
OE#/CAD11
WE#/CGNT#
IORD#/CAD13
IOW#/CAD15
WP/IOIS16/CCLKRUN#
INPACK#/CREQ#
RDY_IREQ#/CINT#
WAIT#/CSERR#
CD2/CCD2#
CD1/CCD1#
CE2/CAD10
CE1#/CCBE0#
RESET/CRST#
BVD2/SPKR/LED/AUDIO
BVD1/STSCHG/RI/CSTSCHG
VS2/CVS2
VS1/CVS1

125
116
113
111
109
107
105
103
100
98
108
110
104
101
112
95
89
97
99
115
118
120
121
124
127
128
129
87
84
82
80
77
144
142
140
85
83
81
79
76
143
141
139
92
106
93
96
136
123
132
133
137
75
91
88
119
134
135
117
131

CBB_REG#
CBB_A25
CBB_A24
CBB_A23
CBB_A22
CBB_A21
CBB_A20
CBB_A19
CBB_A18
CBB_A17
A_CCLKXX
CBB_A15
CBB_A14
CBB_A13
CBB_A12
CBB_A11
CBB_A10
CBB_A9
CBB_A8
CBB_A7
CBB_A6
CBB_A5
CBB_A4
CBB_A3
CBB_A2
CBB_A1
CBB_A0
CBB_D15
CBB_D14
CBB_D13
CBB_D12
CBB_D11
CBB_D10
CBB_D9
CBB_D8
CBB_D7
CBB_D6
CBB_D5
CBB_D4
CBB_D3

CBB_REG# 26
CBB_A25 26
CBB_A24 26
CBB_A23 26
CBB_A22 26
CBB_A21 26
CBB_A20 26
CBB_A19 26
CBB_A18 26
CBB_A17 26
R568 1
2 33R2J-2-GP
CBB_A15 26
CBB_A14 26
CBB_A13 26
CBB_A12 26
CBB_A11 26
CBB_A10 26
CBB_A9 26
CBB_A8 26
CBB_A7 26
CBB_A6 26
CBB_A5 26
CBB_A4 26
CBB_A3 26
CBB_A2 26
CBB_A1 26
CBB_A0 26
CBB_D15 26
CBB_D14 26
CBB_D13 26
CBB_D12 26
CBB_D11 26
CBB_D10 26
CBB_D9 26
CBB_D8 26
CBB_D7 26
CBB_D6 26
CBB_D5 26
CBB_D4 26 VCC_ASKT_S0

1
2
3
4

63
AUX_VCC

14
66
86
102
122
138

C906
SCD1U16V2ZY-2GP

U79

SOCKET_VCC
SOCKET_VCC

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

CORE_VCC
CORE_VCC
CORE_VCC
CORE_VCC
CORE_VCC

3
4
5
7
8
9
10
11
15
16
17
19
23
24
25
26
38
39
40
41
43
45
46
47
49
51
52
53
54
55
56
57

GRST# CORE_VCC

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

GND
GND
GND
GND
GND
GND
GND
GND

17,21,27,29,30 PCI_AD[31..0]

PCI_VCC
PCI_VCC
PCI_VCC
PCI_VCC

18
30
44
50

6
22
42
58
78
94
114
130

C900
SC1000P50V2JN-N1

C915
C904
C899
SC1000P50V2JN-N1
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2

3D3V_S0

CBB_OE#
CBB_CE1#
CBB_RESET
CBB_CE2#

CBB_A16 26
3

CLK33_CBUS
17,27,29,30 PCIRST_BUF#

CLK33_PCM12

DY

PCI_GNT#1
PCI_REQ#1

C913
SC10P50V2JN-1

DY

SC22P50V2JN-4GP

C914

1
2

TP120
17
17

R575
10R2J-2-GP

17

26
26
26
26

VCCD1#
VCCD0#
VPPD1
VPPD0
3D3V_S0

1
R567

2
10KR2J-2-GP

CBB_IORD#
CBB_IOWR#

CBB_D3 26
CBB_D2 26
CBB_D1 26
CBB_D0 26
CBB_OE# 26
CBB_WE# 26
CBB_IORD# 26
CBB_IOWR# 26

CBB_D1
CBB_D0
CBB_OE#

10KR2J-2-GP
R574
2

17,27,29,30 PCI_FRAME#
17,27,29,30 PCI_IRDY#
17,27,29,30 PCI_TRDY#
R576
17,27,29,30 PCI_STOP#
1
2
100R2F-L1-GP-U
17,27,29,30 PCI_DEVSEL#
17,27,29,30 PCI_PERR#
17,27,29,30 PCI_SERR#
17,27,29,30 PCI_PAR

C_BE3#
C_BE2#
C_BE1#
C_BE0#
FRAME#
IRDY#
TRDY#
STOP#
IDSEL
DEVSEL#
PERR#
SERR#
PAR
PCI_CLK
RST#
RI_OUT#/PME#
GNT#
REQ#

CBB_WP 26
CBB_INPACK# 26
CBB_RDY 26
CBB_WAIT# 26
CBB_CD2#_1 26
CBB_CD1#_1 26
CBB_CE2# 26
CBB_CE1# 26
CBB_RESET 26
CBB_BVD2# 26
CBB_BVD1# 26
CBB_VS2# 26
CBB_VS1# 26

CBB_CE2#
CBB_CE1#

CB1410B0-1-U

RC12 1
PCM_INTA# R573 1
PCM_INTB# R572 1
CB_MFUNC2
CB_MFUNC3
CB_MFUNC4
CB_MFUNC5

2 43KR3-GP
2 0R0402-PAD
2 0R0402-PAD

INTA#
INTB#
INTC#
INTD#

CB_SPKR 32
INT_PIRQE# 17,27
INT_PIRQF# 17,29

CARBUS 1 (INT_PIRQE#)
(WIFI) (INT_PIRQF#)
1394 (INT_PIRQG#)
CardReader (INT_PIRQE#) share

PCI_AD22

12
27
37
48
28
29
31
33
CARD_IDESL 13
32
34
35
36
21
20
59
2
1

R571
47KR2J-2-GP

Wistron Corporation

PCI_CBE#3
PCI_CBE#2
PCI_CBE#1
PCI_CBE#0

74
73
72
71
CBUS_SUSPEND70
69
68
67
65
64
61
60
62

17,27,29,30 PCI_CBE#[3..0]

VCCD1#/SMBCLK/SCLK
VCCD0#/SMBDATA/SDATA
VPPD1
VPPD0/SLATCH
SUSPEND
O2MF6
O2MF5
O2MF4
O2MF3
O2MF2
O2MF1
O2MF0
SPKR_OUT#

www.kythuatvitinh.com

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

PM_CLKRUN# 17,27,29,30,34,37
Title

CardBus_ENE CB1410
Size
A3

Document Number

Rev

Bolsena-E

Date: Thursday, October 13, 2005

A

SA

Sheet
E

25

of

58

PCMCIA Socket

Power switch

Cardbus I/F
CBB_D[0..15] 25
CBB_A[0..25] 25

CBB_A8
CBB_A17
CBB_A13
C575
SCD1U25V3ZY-3GPCBB_A18
CBB_A14
CBB_A19

C574
SC1000P50V2JN-N1

CBB_WE#
CBB_A20
CBB_RDY
CBB_A21

VPP_ASKT_S0

CBB_A16
CBB_A22
CBB_A15
CBB_A23
CBB_A12
CBB_A24
CBB_A7
CBB_A25
CBB_A6

2
1

C621
2

C622

VCCD0#
VCCD1#
3.3V
3.3V
5V
5V
GND
OC#

SHTDN#
VPPD0
VPPD1
VCCOUT
VCCOUT
VCCOUT
VPPOUT
12V

16
15
14
13
12
11
10
9

2211_SHDN#

VPPD0 25
VPPD1 25
VCC_ASKT_S0
VPP_ASKT_S0

CP2211F-GP

PC1
1

R281
CBB_CD1#

DY CARD-SKT18-U

CBB_CD1#_1 25
1

1
2

SC10U10V5ZY-1GP

1
2
3

C576

SC10U10V5ZY-1GP
2

CBB_IOWR#
C577

5V_S0
C623

SC1U10V3ZY-6GP

CBB_IORD#
CBB_A9

C624

CBB_VS1# 25
CBB_VS2# 25

CBB_A11

3D3V_S0

SCD1U16V2ZY-2GP

CBB_CE2#
CBB_OE#
CBB_VS1#

VCC_ASKT_S0

1
2
3
4
5
6
7
8

25 VCCD0#
25 VCCD1#

CBB_CE1# 25
CBB_CE2# 25
CBB_BVD1# 25
CBB_BVD2# 25

SCD1U16V2ZY-2GP

CBB_A10

4K7R2J-2-GP

U43

CBB_CE1#
CBB_D15

R354

25
25

CBB_D4
CBB_D11
CBB_D5
CBB_D12
CBB_D6
CBB_D13
CBB_D7
CBB_D14

3D3V_S0
25
25

CBB_CD1#

SC1U10V3ZY-6GP

CBB_D3
4

CBB_IORD# 25
CBB_IOWR# 25
CBB_OE# 25
CBB_WE# 25
CBB_REG# 25
CBB_RDY
CBB_WP
CBB_RESET 25
CBB_WAIT#
CBB_INPACK#

PCH1
NP1
1
35
2
36
3
37
4
38
5
39
6
40
7
41
8
42
9
43
10
44
11
45
12
46
13
47
14
48
15
49
16
50
17
51
18
52
19
53
20
54
21
55
22
56
23
57
24
58
25
59
26
60
27
61
28
62
29
63
30
64
31
65
32
66
33
67
34
68
NP2

0R2J-GP

C543
SC270P50V2JN-2GP

CBB_A16

CBB_A5

CBB_RESET

CBB_A4

CBB_WAIT#

CBB_A3

CBB_INPACK#

CBB_A2

CBB_REG#

CBB_A1

Place close to pin 19.

CBB_BVD2#

CBB_A0

C902
DUMMY-C2

CBB_BVD1#
CBB_D0
CBB_D8
CBB_D1
CBB_D9
CBB_D2
CBB_D10
CBB_WP
CBB_CD2#

VCC_ASKT_S0

CBB_CD2#

CBB_CD2#_1 25

0R2J-GP

C628
SC270P50V2JN-2GP

DY

CARDBUS68P-11-GP

Clock AC termination
33MHz clock for 32-bit
Cardbus card I/F

R346

CBB_VS2#

DY

ME : 21.H0056.001

www.kythuatvitinh.com
C901
SCD1U25V3ZY-3GP

21.H0056.001

R320
DUMMY-R2

ME : 62.10024.131

47K

C598
SCD01U16V2KX-3GP

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

PCMCA / 1394 / CARD READER

Size
A3

Document Number

Rev

SA

Bolsena-E

Date: Thursday, October 13, 2005

Sheet
E

26

of

58

3D3V_S0

SB
Add 0.01U*4 for TQFP
3D3V_S0

C578

VCC_ROUT1
VCC_ROUT2
VCC_ROUT3
VCC_ROUT4
VCC_ROUT5
VCC_MD

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

125
126
127
1
2
3
5
6
9
11
12
14
15
17
18
19
36
37
38
39
40
42
43
44
46
47
48
49
50
51
52
53
33
7
21
35
45
8

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
PAR
C/BE3#
C/BE2#
C/BE1#
C/BE0#
IDSEL

C587
2

1
2

VCC_RIN

67

86

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10

4
13
22
28
54
62
63
68
118
122

AGND1
AGND2
AGND3
AGND4
AGND5

99
102
103
107
111

3D3V_S0

1
2

1
2

C561
SCD01U16V2KX-3GP

2
1

61

VCC_3V

SC10U6D3V5MX-LGP

VCC_PCI1
VCC_PCI2
VCC_PCI3
VCC_PCI4
VCC_PCI5
VCC_PCI6

16
34
64
114
120

R5C832_VCCROUT

10
20
27
32
41
128

SCD01U16V2KX-3GP

C602
SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

C588

C585
SCD47U10V3KX-LGP

C565
SCD01U16V2KX-3GP

SCD47U10V3KX-LGP

C613

C584
SCD01U16V2KX-3GP

C581
SCD01U16V2KX-3GP

C563
SCD01U16V2KX-3GP

C559
SCD01U16V2KX-3GP

SCD1U10V2KX-LGP

SC10U6D3V5MX-LGP

C562

SCD01U16V2KX-3GP

C558

C564

SC10U6D3V5MX-LGP

C579

IC1B

3D3V_S0

R304
10KR2J-2-GP

www.kythuatvitinh.com
3D3V_S0

DY

DY

17,25,29,30 PCI_PAR

R339
100KR2J-1-GP

R342
10KR2J-2-GP

D22

GBUS_GRST#

PCI_AD17

R318

DY CH751H-40PT-1GP
2

1
R341

DY

17
PCI_REQ#3
17
PCI_GNT#3
17,25,29,30 PCI_FRAME#
17,25,29,30 PCI_IRDY#
17,25,29,30 PCI_TRDY#
17,25,29,30 PCI_DEVSEL#
17,25,29,30 PCI_STOP#
17,25,29,30 PCI_PERR#
17,25,29,30 PCI_SERR#

2
0R2J-GP

PCIRST_BUF#
1
R330

PCI_CBE#3
PCI_CBE#2
PCI_CBE#1
PCI_CBE#0
2 R5C834_IDSEL
10R2J-2-GP

2
0R2J-GP

GBUS_GRST#_1

SB
17,25,29,30 PCIRST_BUF#
Solve S3 wake up and leakage issue
1
R309

17,25,29,30,34,37 PM_CLKRUN#

REQ#
GNT#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR#

71
119

GBRST#
PCIRST#

121

PCICLK

CBUS_PME#
70
10KR2J-2-GP
1
2PM_CLKRUN#_R5C832117
0R2J-GP
R328
2

58

MSEN

XDEN

55

XDEN

UDIO5

57

UDIO5

UDIO3
UDIO4

65
59

UDIO3
UDIO4

UDIO2

56

KGBUS_GRST#_3 1
R289
CH751H-40PT-1GP
3D3V_S0

1
R292
1
R294

R293

2
2

2
0R2J-GP

GBUS_GRST# 34

10KR2J-2-GP
10KR2J-2-GP

2
100KR2J-1-GP

1
R2901
R291

2
2 10KR2J-2-GP
10KR2J-2-GP

60

PCI_SPKR

32

UDIO0/SRIRQ#

72

P_SERIRQ

17,34,37
2

PME#

INTA#

115

INT_PIRQG#

17

INTB#

116

INT_PIRQE#

17,25

TEST

66

R5C832_TEST
1

1394 : INTA#
7in1 : INTB#(INT_PIRQE#)share

TP78 TPAD30

CLKRUN#
R300
100KR2J-1-GP

R329
1KR2J-L1-GP
R5C832-1-GP

PCLK_R5C832_PL1

DY

MSEN

DY

D20

UDIO1

R331
10R2J-2-GP

3D3V_S0

SHIELD
GND

17,21 PCLK_R5C832

124
123
23
24
25
26
29
30
31

69

3D3V_S5

GBUS_GRST#_2

HWSPND#

17,21,25,29,30 PCI_AD[31..0]

DY

PCI / OTHER

17,25,29,30 PCI_CBE#[3..0]

C614
SC10P50V2JN-4GP

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

R5C832_1394_7IN1(2/2)
Size
A3

Document Number

Rev

Bolsena-E

Date: Thursday, October 13, 2005

A

Sheet
E

SA
27

of

58

U78
+3VRUN_CARD
1
2
3

FIL0

RICHO_VREF
100
SCD01U16V2KX-3GP

VREF

2
1 R525
2
0R3J-3-GP

L27

GUARD GND
C

XD_DATA7

MDIO16

92

XD_DATA6

MDIO15

89

XD_DATA5

MDIO14

91

XD_DATA4

MDIO13

90

SD/XD/MS_DATA3_1

MDIO12

93

SD/XD/MS_DATA2_1

MDIO11

81

SD/XD/MS_DATA1_1

MDIO10

82

SD/XD/MS_DATA0_1

MDIO05

75

XD_WP#

MDIO08

88

SD/XD/MS_CMD

MDIO19

83

XD_ALE

MDIO18

85

XD_CLE

MDIO02

78

DY
TPB0+

GAP-CLOSE
G51
2

L29

TPB01

87

MDIO17

R337

1
2
1
2
R324
5K11R2F-L1-GP
56R2J-4-GP 1394_TPB1_R
1
2
1
2
R32556R2J-4-GP C611
SC270P50V2JN-2GP

DY

1 R522
2
0R3J-3-GP

G50
1

TPBIAS0
TPA0P
TPA0N
TPB0P
TPB0N

1
C601
GUARD_GND

SKT1
SKT-1394-4P-14GP
22.10218.M01

REXT

NCMS20C900-GP

101

C625 R327 R326

1

TPA0P

C612

109

2RICHO_REXT
10KR2F-2-GP

96

TPA0+
TPA0-

RICHO_FILO
SCD01U16V2KX-3GP

IEEE1394/SD

R323

4
3
2
1

NCMS20C900-GP

1
C599

TPAP0

GUARD_GND

TPA0N

108

TPAN0

DY

XO

95

CLOSE TO CHIP

1 R523
2
0R3J-3-GP

1394_XO
2
SC15P50V2JN-2-GP

1
C593

TPB0P

105

check with EMI, can change to 0 ohm

56R2J-4-GP

TPBP0

XI

X4
X-24D576MHZ-39GP

94

Reserve R547,R548,R550,R551 for co-layout

For SD/MS Card Power

56R2J-4-GP

TPB0N

SC

AAT4250IGV-T1-GP
C898

C897

SCD33U10V3KX-2GP

TPBN0

104

TPBIAS0

SCD1U10V2KX-LGP

1394_XI
2
SC15P50V2JN-2-GP

1
C591

C610

MC_PWR_CTRL_0

SCD01U16V2KX-3GP

113

SC10U6D3V5MX-LGP

C600

SCD1U10V2KX-LGP

TPBIAS0

C609

GUARD GND

20mil

OUT
IN
GND
NC#3 ON/OFF#

SC1U10V3ZY-6GP

98
106
110
112

SCD01U16V2KX-3GP

AVCC_PHY1
AVCC_PHY2
AVCC_PHY3
AVCC_PHY4

1
2
L17 MLB1608080600A1GP

+3VRUN_PHY

+3VRUN_PHY

3D3V_S0

3D3V_S0

IC1A

GAP-CLOSE

www.kythuatvitinh.com
GUARD_GND

1 R526
2
0R3J-3-GP
DY

+3VRUN_CARD

XD_CE#

SD_WP#(XDR/B#)

MDIO03

77

MDIO00

80

MDIO01

79

MS_INS#

MDIO09

84

SD/XD/MS_CLK

MDIO04

76

MC_PWR_CTRL_0

MDIO06

74

MS_LED#

SD_CD#

C905

D19

SC1U10V3ZY-6GP
2

C896

SCD1U16V2ZY-2GP

CARD1

C894
SCD1U16V2ZY-2GP

SD/XD/MS_DATA0_1
SD/XD/MS_DATA1_1
SD/XD/MS_DATA2_1
SD/XD/MS_DATA3_1

RSV
MDIO07

7
6
12
11

XD_SW#
3

MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3

SD/XD/MS_DATA1_1
SD/XD/MS_DATA2_1
SD/XD/MS_DATA3_1
XD_DATA4
XD_DATA5
XD_DATA6
XD_DATA7

33
32
31
21
22
23
24

S.M/XD-D1
S.M/XD-D2
S.M/XD-D3
S.M/XD-D4
S.M/XD-D5
S.M/XD-D6
S.M/XD-D7

BAS16-1-GP

SD/XD/MS_DATA0_1

25
30
34

S.M-LVD
S.M-CD#
S.M-D0

TP80

R566
100KR2J-1-GP

73

R5C832-1-GP

SM-CD-COM
SM-CD-SW
SM-WP-SW

2
3
43

MS-BS
MS-INS
MS-SCLK

13
17
19

SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3

15
14
16
18

BAS16-1-GP
D18
1

XD-VCC
S.M-VCC
MS-VCC
SD-VCC

SD/XD/MS_DATA0_1
SD/XD/MS_DATA1_1
SD/XD/MS_DATA2_1
SD/XD/MS_DATA3_1

97

40
29
20
9

SD/XD/MS_CMD
MS_INS#
SD/XD/MS_CLK

RSV#4
XD-CD

4
39

SD-CD-COM
SD-CD-SW
SD-WP-SW
SD-CLK
SD-CMD

41
42
5
8
10

SD_CD#
SD_WP#(XDR/B#)
SD/XD/MS_CLK
SD/XD/MS_CMD

S.M#/XD-CLE
S.M#/XD-ALE
S.M#/XD-WE
S.M#/XD-CE
S.M#/XD-RE
S.M#/XD-R/B
S.M/XD-WP-IN

38
37
36
28
27
26
35

XD_CLE
XD_ALE
SD/XD/MS_CMD
XD_CE#
SD/XD/MS_CLK
SD_WP#(XDR/B#)
XD_WP#

GND
GND
GND
GND

46
45
44
1

XD_SW#
B

SD
SKT-MEMO-12-GP

62.10051.431

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

R5C832_1394_7IN1(2/2)
Size
A3

Document Number

Rev

Bolsena-E

Date: Thursday, October 13, 2005

5

Sheet
1

SA
28

of

58

MINI-PCI
4

C834
C802
C835
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP
2

C806
SC4D7U10V5ZY-3GP

17,21,25,27,30 PCI_AD[31..0]
17,25,27,30 PCI_CBE#[3..0]

3D3V_S0

DY
MINI1

17,21 CLK33_MINI
17

PCI_REQ#0

DY

MINI_P_IRQF# 1
R521 2
0R0402-PAD

C833

WLAN_LED# 16

DY

R517
100KR2J-1-GP

D
3

124
126

C807
SC4D7U10V5ZY-3GP
2

123

3D3V_S0
1

4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122

INT_PIRQF# 17,25

Q26
2N7002PT-U

80211_ACTIVE

1
3

G
PCIRST_BUF# 17,25,27,30

MINI_P_IRQF#
3D3V_S0

3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121

5V_S0
RING

WIRELESS_EN

125
2

SCD1U25V3ZY-3GP

80211_ACTIVE
34

TIP

S
PCI_GNT#0 17

www.kythuatvitinh.com
23 BT_COEX2

PCI_CBE#3
PCI_AD23
PCI_AD21
PCI_AD19

3D3V_S0

PCI_AD17
PCI_CBE#2

R533
17,25,27,30 PCI_IRDY#
10KR2J-2-GP

17,25,27,30,34,37 PM_CLKRUN#
17,25,27,30 PCI_SERR#

17,25,27,30 PCI_PERR#

PCI_CBE#1
PCI_AD14
PCI_AD12
PCI_AD10

PCI_AD8
PCI_AD7
PCI_AD5
PCI_AD3
5V_S0

PCI_AD1

BT_COEX1 23

PCI_AD30

TP109
TPAD30

PCI_AD28
PCI_AD26
PCI_AD24
MINI_IDSEL

R534 2 PCI_AD21
100R2F-L1-GP-U

PCI_AD27
PCI_AD25

PME#_MINI

PCI_AD22
PCI_AD20

Q25
2N7002PT-U

PCI_PAR 17,25,27,30

PCI_AD18
PCI_AD16

WIRELESS_EN

PCI_AD31
PCI_AD29

PCI_FRAME# 17,25,27,30
PCI_TRDY# 17,25,27,30
PCI_STOP# 17,25,27,30

PCI_DEVSEL# 17,25,27,30
PCI_AD15
PCI_AD13
PCI_AD11

PCI_AD9
PCI_CBE#0
PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0

Q24

(VCC)

2
IN

34 WLAN_TEST_LED

3 OUT

R1

1 GND

R2

(M66EN)

DTC124EKA-1-GP

PCISLT124-4-GP

62.10032.061

<Variant Name>

ME : 62.10032.061
2ND : 62.10043.221

Wistron Corporation

62.10032.031 - 2ND

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

MINI-PCI
Size
A3

Document Number

Rev

SA

Bolsena-E

Date: Thursday, October 13, 2005

Sheet
E

29

of

58

TGP0

TGP1

TGP2

TGP3

RN92
SRN49D9F-GP

17,25,27,29 PCI_CBE#[3..0]
17,21,25,27,29 PCI_AD[31..0]

CLOSE TO
LAN CHIP

RN93
SRN49D9F-GP

RN94
SRN49D9F-GP

=> LED1 : LINK

LAN_X2
1 R47

2 0R0402-PAD

10M_LED# 31

X5

1
2

1
2

1
2

RTL_LED1#
1
2

2 C690
SC12P50V2JN-LGP

2 C691
SC12P50V2JN-LGP

RN91
SRN49D9F-GP

4
3

TGN3

4
3

TGN2

4
3

TGN1

4
3

TGN0

LAN_X1

C674
SCD01U50V3KX-4GP

C675
SCD01U50V3KX-4GP

C673
SCD01U50V3KX-4GP

Dummy when use 10/100

3D3V_LAN_S5

LAVDDH

U10

LAN_X2

1
2
3
4

CS
SK
DI
DO

CTRL18
ACT_LED#
LDVDD

LAN_EESK
LDVDD
LAN_EEDI
LAN_EEDO
3D3V_LAN_S5
LAN_EECS_3
PCI_AD0
PCI_AD1

C56

C670
SCD1U25V3ZY-3GP

C96

SCD1U25V3ZY-3GP

C88

SCD1U25V3ZY-3GP
2

SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

SC10U10V5ZY-1GP

C80

C678

AVDDH
VSSPST
GND
LED0
VDD18
LED1
LED2
LED3
GND
EESK
VDD18
EEDI
EEDO
VDD33
EECS
LANWAKE
PCIAD0
PCIAD1

PCI_PAR 17,25,27,29
PCI_SERR# 17,25,27,29

3D3V_LAN_S5

PCI_AD23

R413 2 LAN_IDSEL
100R2F-L1-GP-U

PCI_AD25
PCI_AD24
PCI_CBE#3
LDVDD
LAN_IDSEL
PCI_AD23
PCI_AD22
PCI_AD21

PCI_AD19
LDVDD
PCI_AD20

Dummy when use 10/100

1
SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

LAVDDL

PCI_IRDY# 17,25,27,29
PCI_FRAME# 17,25,27,29

C41

C39

C38

C17

PM_CLKRUN# 17,25,27,29,34,37
C40

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

G59

3D3V_LAN_S5
3D3V_S5

RTL8110SBL/RTL8100C

3D3V_LAN_S5
Size
A3

GAP-CLOSE-PWR

Document Number

Rev

SA

Bolsena-E

Date: Thursday, October 13, 2005

A

R68
0R3J-3-GP

SCD1U25V3ZY-3GP

3D3V_LAN_S5

1
Q3
BCP69T1-1-GP

SCD1U25V3ZY-3GP
2

PM_CLKRUN#

CTRL25

PCI_PERR# 17,25,27,29
PCI_STOP# 17,25,27,29
PCI_DEVSEL# 17,25,27,29
PCI_TRDY# 17,25,27,29

Dummy when use Giga

PCI_PERR#
PCI_STOP#
PCI_DEVSEL#
PCI_TRDY#

<Variant Name>

LDVDD
PCI_IRDY#
PCI_FRAME#
PCI_CBE#2
PCI_AD16
PCI_AD17
PCI_AD18

SCD1U25V3ZY-3GP
2

PCI_AD15
LDVDD
PCI_CBE#1
PCI_PAR
PCI_SERR#

SCD1U25V3ZY-3GP
2

PCI_AD13
PCI_AD14

SCD1U25V3ZY-3GP
2

PCI_AD27
PCI_AD26

C68

C55

GIGALAN: RTL8110SBL
10/100 LAN:RTL8100C

39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

RTL8110SBL
C679
SC10P50V2JN-1

C73

C87

C89

CLK33_LAN

C694

(10/100) 71.08100.C0G - (GIGA ver:D) 71.08110.C0G

C74

C57

SCD1U25V3ZY-3GP
2

PCI_AD29
PCI_AD28

C42

CLK33_LAN
PCI_GNT#2
PCI_REQ#2
PME#_LAN
LDVDD
PCI_AD31
PCI_AD30

C43

SC10U10V5ZY-1GP
2

3D3V_LAN_S5
17,25,27,29 PCIRST_BUF#
17,21 CLK33_LAN
17
PCI_GNT#2
17
PCI_REQ#2
R396 2
1
PME#_SB
0R0402-PAD

PCI_AD10
PCI_AD11
PCI_AD12

17

PCI_AD8
PCI_AD9

LDVDD_A

L3
1
2
0R0603-PAD

-1 0308 2 D8

Dummy when use 10/100

SCD1U25V3ZY-3GP
2

TGP3
TGN3
LAVDDL
R395 2 1KR2J-1-GP
3 1
BAT54PT-GP
ISOLATE#
R394 2
15KR2F-GP
LDVDD
INT_PIRQH#
INT_PIRQH#
TGP3
TGN3

45 Ohm,
600mA

LDVDD

PCI_AD7
PCI_CBE#0

SCD1U25V3ZY-3GP
2

31
31

3D3V_S0

2
0R2J-GP

SCD1U25V3ZY-3GP
2

TGP2
TGN2

TGP2
TGN2
LAVDDL

Q5
BCP69T1-1-GP

CTRL18 1
R70

SCD1U25V3ZY-3GP
2

Dummy when use Giga

LDVDD
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6

SCD1U25V3ZY-3GP
2

LV_12P

3D3V_LAN_S5

1 R28

LAVDDH

2
0R2J-GP
2
0R2J-GP

0R2J-GP
1 R69
2

SCD1U25V3ZY-3GP
2

XTAL1

XTAL2

VSS

VSS

CTRL18

AVDD18

TGP1
TGN1
LAVDDL
CTRL25

PCIAD2
VSSPST
GND
VDD18
PCIAD3
PCIAD4
PCIAD5
PCIAD6
VDD33
PCIAD7
CBEB0
VSSPST
PCIAD8
PCIAD9
M66EN
PCIAD10
PCIAD11
PCIAD12
VDD33
PCIAD13
PCIAD14
VSSPST
GND
PCIAD15
VDD18
CBEB1
PAR
SERR#
NC#74
GND
NC#72
VDD33
PERR#
STOP#
DEVSEL#
TRDY#
VSSPST
CLKRUN#

PCI_AD2

TGP1
TGN1

MDI0+
MDI0AVDDL
VSS
MDI1+
MDI1AVDDL
CTRL25
VSS
AVDDH
HSDAC+
HSDACVSS
MDI2+
MDI2AVDDL
VSS
MDI3+
MDI3AVDDL
VSSPST
GND
ISOLATE#
VDD18
INTA#
VDD33
PCIRST#
PCICLK
GNT#
REQ#
PME#
VDD18
PCIAD31
PCIAD30
GND
PCIAD29
PCIAD28
VSSPST

102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65

31
31

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

TGP0
TGN0
LAVDDL

TGP0
TGN0

1 R29

LDVDD

C683

PCIAD27
PCIAD26
VDD33
PCIAD25
PCIAD24
CBEB3
VDD18
IDSEL
PCIAD23
GND
PCIAD22
PCIAD21
VSSPST
GND
PCIAD20
VDD18
PCIAD19
VDD33
PCIAD18
PCIAD17
PCIAD16
CBEB2
FRAME#
GND
IRDY#
VDD18

LAVDDH

20

1
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103

121

122

123

124

125

126

128
127
VSS
RSET

31
31

Dummy when use 10/100

C676

www.kythuatvitinh.com
Dummy when use Giga
CTRL25

31
31

LAVDDH

L21 2
1
0R0603-PAD
C86

SCD1U25V3ZY-3GP

Dummy when use 10/100 RSET

U52

45 Ohm,
600mA

3D3V_LAN_S5

3D3V_LAN_S5

1 R38
2
2K49R3F-GP

TPAD28
TPAD28

TP6
TP5
R43 2
5K6R3F-GP

=> LED0 : ACT

SCD1U25V3ZY-3GP
2

Dummy when use Giga

EEPROM LED OPTION USE '01'

(DEFINED IN SPEC)
=> LED0 : ACT
=> LED1 : LINK
(BOTH 10/100 AND GIGA CHIP)

ACT_LED# 31
RTL_LED1#

C696
SCD1U25V3ZY-3GP

AT93C46-10SU-1GP

LDVDD_A

8
7
6
5

VCC
DC
ORG
GND

R427 2 10KR2J-2-GP
R426 2 3K6R3-GP

1
1

3D3V_LAN_S5
3D3V_LAN_S5

LAN_EECS_3
LAN_EESK
LAN_EEDI
LAN_EEDO

DY

LAN_X1

SCD1U25V3ZY-3GP
2

C672
SCD01U50V3KX-4GP

XTAL-25MHZ-70GP

Sheet
E

30

of

58

Link: Green - 10Mbps/802.11b

Orange - 100Mbps/802.11a
Yellow - 1Gbps

Activity: Yellow

LAN1

3D3V_LAN_S5
30

2 R6

ACT_LED#

A3:ORANGE

B2
10

B2:YELLOW

10M_LED#
ACT_LED#
C9
SC1000P50V2JN-N1

ACT:YELLOW BLINKING

SKT-RJ45+RJ11-2GPU
22.10177.711 - 2ND

22.10177.721
ME : 22.10177.721
2nd : (canceled)

1
EC2

EC3
4

RJ45-8
RJ45-7
RJ45-5
RJ45-4

C8
SC1000P50V2JN-N1

A3
RJ45_1
RJ45_2
RJ45_3
RJ45_4
RJ45_5
RJ45_6
RJ45_7
RJ45_8
B1

TDP_RJ45-1
TDN_RJ45-2
RDP_RJ45-3
RJ45-4
RJ45-5
RDN_RJ45-6
RJ45-7
RJ45-8
1 CONN_PWR_B2
470R2J-2-GP
ACT_LED#

A2

SCD1U25V3ZY-3GP

1CONN_PWR
470R2J-2-GP

R5

CONN_PWR_B2
CONN_PWR

SCD1U25V3ZY-3GP

3D3V_LAN_S5

A1

10M_LED#

10M_LED#

30

LINK:GREEN ON

22.10177.721
22.10177.711
LED COLOR
A1:GREEN

9
RJ11_1
RJ11_2

TIP
RING

MDCW1
MLXCON2
L1
TIP_MDC
RING_MDC

1
2

21.D0010.102
ME : 21.D0010.102

1
1

2 BLM18HG601SN-GP TIP
2 BLM18HG601SN-GP RING

L2

10/100M Lan Transformer

U46

www.kythuatvitinh.com
6
14
11
3

MCT3
MCT4
V_DAC

TD+
TDCT
CT
CT
CT

TX+
TX-

10
9

RD+
RD-

1
2

RX+
RX-

16
15

TDP_RJ45-1
TDN_RJ45-2

8
7
6
5

7
8

TGP0
TGN0

TGP1
TGN1

RDP_RJ45-3
RDN_RJ45-6

MCT1

XFORM-112

RN6

30
30

1
2
3
4

30
30

SRN0J-4-GP
MCT2

LANKOM 68.0H80P.301

68.0H80P.301

Dummy when use Giga

LANKOM 68.02402.30A
netSWAP 68.62401.301 (GIGA ,Thick)

GIGA Lan Transformer

NETSWAP GIGA THICK PN IS 68.62401.301, DON'T USE NETSWAP THIN

U47
TGP3
TGN3

2
3

TD1+
TD1-

MX1+
MX1-

23
22

RJ45-7
RJ45-8

30
30

TGP2
TGN2

5
6

TD2+
TD2-

MX2+
MX2-

20
19

RJ45-4
RJ45-5

30
30

TGP1
TGN1

8
9

TD3+
TD3-

MX3+
MX3-

17
16

RDP_RJ45-3
RDN_RJ45-6

30
30

TGP0
TGN0

11
12

TD4+
TD4-

MX4+
MX4-

14
13

TDP_RJ45-1
TDN_RJ45-2

1
4
7
10

TCT1
TCT2
TCT3
TCT4

MCT1
MCT2
MCT3
MCT4

24
21
18
15

MCT1
MCT2
MCT3
MCT4

C20

8
7
6
5

XFORM-207-GP

68.62401.30A

1.route on bottom as differential pairs.

2.Tx+/Tx- are pairs. Rx+/Rx- are pairs.
3.No vias, No 90 degree bends.
4.pairs must be equal lengths.
5.6mil trace width,12mil separation.
6.36mil between pairs and any other trace.
7.Must not cross ground moat,except
RJ-45 moat.

RN7

Dummy when use 10/100

Wistron Corporation
C14
C11
SCD1U25V3ZY-3GP
2

Dummy when use 10/100

1
2
3
4

1
2

SCD01U50V3KX-4GP

C19

SCD01U50V3KX-4GP

SCD01U50V3KX-4GP
2

C21

SCD01U50V3KX-4GP
2

C18

V_DAC

R398 2
0R2J-GP

LAVDDL

30
30

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

SRN75J-1-GP

LAN_TC_GND
SC1KP2KV8KX-GP

Title

LAN CONN

2 C10
DY
SC1000P50V2JN-N1

Size
A3

Dummy when use Giga

Document Number

Rev

SA

Bolsena-E

Date: Thursday, October 13, 2005

Sheet
E

31

of

58

5VA_S0

5V_S0

R334
28K7R2F

2
U42

C595

27

PCI_SPKR

C605

OUT

R335
10KR2F-2-GP

C616
SC10U10V5ZY-1GP

G923-330T1UF-GP

AUD_AGND
AUD_AGND

R336
1KR2J-1-GP

C607
SC100P50V3JN-2GP

C597

C589

C620
SCD1U10V2KX-LGP

KBC_BEEP

2AUDIP_PC_BEEP

SC1U10V3KX-3GP

RN75
34

C596
1

AUDIO_BEEP

C582
SCD1U10V2KX-LGP
2

5
6
7
8

CB_SPKR_1 4
3
KBC_BEEP_12
SPKR_SB_1 1

C594

SPKR_SB

SCD1U10V2KX-LGP
2
1

SRN47KJ-L1-GP
20

IN

"VAUX" Pull high to enable standby mode

SCD1U10V2KX-LGP
2
1

C606

CB_SPKR

5VA_SET
5V_AUDIO_S0

5VA_S0

3D3V_S0
25

GND

SC1U10V3KX-3GP

C604

SHDN# SET

SC22P50V2JN-4GP
1
2

C615

AUD_AGND

AUD_AGND

ACZ_RST# 20
ACZ_SYNC 20
AZ_BITCLK 20
2
1
10KR2J-2-GP
R316

PCI_SPKR_1

www.kythuatvitinh.com
R338

AUD_AGND

32
28
30

MIC1-VREFO-R
MIC1-VREFO-L
MIC2-VREFO

34
13

33

SENSE_B
SENSE_A

SDATA-OUT
SDATA-IN

5
8

SPDIFO
SPDIFI/EAPD

48
47

SIDESURR-OUT-L
SIDESURR-OUT-R

45
46

SURR-OUT-L
SURR-OUT-R

39
41

FRONT-OUT-L
FRONT-OUT-R

35
36

ACZ_DOUT 20
ACZ_SDATAIN0 20

AC97_DATIN
1 R319
2
39R2J-L-GP

SPDIF
33
G1421_MUTE 33

AUD_LOL 33
AUD_LOR 33

CD-L
CD-R
CD-GND
18
20
19

GPIO0
GPIO1
2
3

VREF

JDREF
PIN37_VREFO

R313
4K7R2J-2-GP

71.00883.A0G

27
SC10U10V5ZY-1GP

AUD_AGND

MIC_JKIN#_1

C608

40
37

AVSS1
AVSS2
DVSS1
DVSS2

C590

ALC883-1-GP

44
43

ALC 883

26
42
4
7

C583 C592

20KR2F-L-GP

MIC1V_R
MIC1V_L
MIC2_0
2

MIC1-L
MIC1-R
MIC2-L
MIC2-R

SC4D7U10V5ZY-3GP

2K2R2J-2-GP

C617
1 R314
2
1 R322
2
1
2
R317

21
22
16
17

2K2R2J-2-GP
2K2R2J-2-GP

MIC1_L
MIC1_R
MIC2_L

SC4D7U10V5ZY-3GP
1

LINE1-VREFO
LINE2-VREFO

SC1U10V3ZY-6GP
SC1U10V3ZY-6GP
SC1U10V3ZY-6GP

29
31

AUD_MICIN_L
AUD_MICIN_R
INT_MIC

LINE1-L
LINE1-R
LINE2-L
LINE2-R

SC4D7U10V5ZY-3GP
1

33
33
33

C618
C619
1
2
1
2
1
2

23
24
14
15

LFE-OUT
CEN-OUT

DVDD1
DVDD2
AVDD1
AVDD2

U40

PCBEEP
RESET#
SYNC
BIT-CLK
VAUX

1
9
25
38

12
11
10
6
33

AUD_AGND

G49
1

2
GAP-CLOSE

AUD_AGND

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

AUDIO (1/2) -- CODEC ALC655

Size
A3

Document Number

Rev

SA

Bolsena-E

Date: Thursday, October 13, 2005

Sheet
1

32

of

58

5V_S0

5VA_OP_S0
ALL AUD_AGND -> AMPGND

G53

Internal Speaker

SB 0203

G55
2

GAP-CLOSE
1

G56
2

GAP-CLOSE
1

G52
2

GAP-CLOSE
1

G54
2

GAP-CLOSE
1

SPK1

1 R356

2
10KR2J-2-GP

SC2D2U16V5ZY-GP

SPKR_R+

SPKR_R-

R578 2
L_LINE_IN
15KR2F-GP

R577 2
18KR2F-GP

U3C
8

SC2D2U16V5ZY-GP

1 R347
2
AMPGND
10KR2J-2-GP
1 R343
2
AMPGND
10KR2J-2-GP

14

C911
1
2CSOUTL2 1

AUD_LOL

5V_S0

D23

DY

U44

R_BYPASS
HP_R
R352
10KR2J-2-GP

DY

SHUTDOWN
TJ
HP-IN
VOL

18
19
20
21

RVDD
RBYPASS
RHPIN
RLINEIN

14
16
11
9
1
12
13
24

ROUTROUT+

15
22

SPKR_L+
SPKR_L-

3
10

TSAHCT125PW-GP

HP_IN
AUD_MUTE

R340
100KR2J-1-GP

SPKR_RSPKR_R+

KBC_MUTE 34
SYS_LOUT_IN

R344
100KR2J-1-GP

AMPGND

AMPGND

LINE IN/MIC IN
LIN1

AMPGND

32 AUD_MICIN_R

R370 2
1KR2J-1-GP

AUD_LINE_R

32 AUD_MICIN_L

R368 2
1KR2J-1-GP

AUD_LINE_L

DY

AMPGND
C632
1
2

1
1

AMPGND

HP_R
2
10KR2J-2-GP

SC2D2U16V5ZY-GP

SC4D7U10V5ZY-3GP

1
2

1
2

AUDIO-JK60-GP

22.10088.B41
22.10271.051 - 2ND

ME : 22.10088.B41
2ND : 22.10271.051

SYS_LOUT_IN#=LOW after PLUG-IN

R348
2K2R2J-2-GP

R372
10KR2J-2-GP

3D3V_S0

AMPGND

LOUT1

SYS_LOUT_IN

1 R364

79.10111.40L

AMPGND

GND
VCC
VIN

MINDIN9-7-GP

AMPGND

C650

C649

EC45

22.10147.111

R373

EC50

22.10251.231 2ND

2
SC330P50V2KX-3GP

SE100U10VM-4GP
R374

SPKR_L_A1
2
22R2J-2-GP
SPKR_R_A1
2
22R2J-2-GP

1
TC28

1KR2J-1-GP
2

AMPGND

1 R365

SPKR_R+1

2
SC330P50V2KX-3GP

SC680P50V2KX-2GP

SE100U10VM-4GP
SPKR_L+1
2

SPKR_R+

SC680P50V2KX-2GP
2

SPKR_L+

SYS_LOUT_IN#

2
IN

SYS_LOUT_IN#

R1

R2
DTC124EKA-1-GP

9
8
7
16
6
5
4
2
3
1

SPDIF

TC29

GND 1

32

79.10111.40L

Q21

1KR2J-1-GP

OUT 3

1
SC4D7U10V5ZY-3GP

AMPGND

LINE OUT

R350

GAP-CLOSE

C633

C635

C648

HP_IN_1

5VA_OP_S0

C647

SC100P50V2JN-U

AUD_LOR

R359 2
18KR2F-GP
1
2 C637
SC220P50V2KX-3GP
1 R358
2
10KR2J-2-GP
1
2 C641
SC220P50V2KX-3GP

SC100P50V2JN-U

SC2D2U16V5ZY-GP
C636
R355
1
2 CSOUTR2
1

R_LINE_IN
2
15KR2F-GP

AMPGND

CSOUTR1
1 R349

2
2
AMPGND
10KR2J-2-GP
10KR2J-2-GP

32

AMPGND

www.kythuatvitinh.com
AMPGND

R_BYPASS
L_BYPASS

3
6

R369
R371

R1

DY

MIC_JKIN#_1

R351
10KR2J-2-GP

Q20

ME : 20.D0198.104
2ND : 20.F0714.004

25

1
R2
R345
10KR2J-2-GP

20.D0198.104

G1421BF3UF-GP

PDTA124EU-1-GP

MLX-CON4-19-GP

C918

G1421_MUTE 32

32

34 AMP_SHUTDOWN
3

C919

RB731U-1GP-U

8
2
17
23

LOUT+
LOUTSE/BTL#
HP/LINE#
MUTEIN
MUTEOUT
GND/HS
GND/HS
GND/HS
GND/HS

LLINEIN
LHPIN
LBYPASS
LVDD

AMPGND

5VA_OP_S0

AMPGND

HP_IN_1

SCD1U25V3ZY-3GP

C634

4
5
6
7

1
C909

SC10U10V5ZY-1GP

C910

SC1U10V3KX-3GP

HP_L
L_BYPASS

GND

5VA_OP_S0

C917
SC680P50V2KX-2GP

32

2 C638
SC220P50V2KX-3GP

10

AMPGND

SC680P50V2KX-2GP

C916

R357 2
HP_L
10KR2J-2-GP

SC680P50V2KX-2GP

C640
1
2CSOUTL1

AMPGND

6
4
3
2

SPKR_L+

SC220P50V2KX-3GP

SPKR_L-

SC680P50V2KX-2GP

2 C639

C627
SC4D7U10V5ZY-3GP

GAP-CLOSE-PWR

MIC1

3
1

INT_MIC

C6

DY

SC1000P50V2JN-N1

ME : 20.D0173.102
2ND :20.F0714.002

2
4

32

MLX-CON2-5-GP
20.D0173.102

<Variant Name>

R3

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

0R3J-3-GP
Title

AUDIO (2/2)
Size
Document Number
Custom

Rev

SA

Bolsena-E

Date: Thursday, October 13, 2005

Sheet
E

33

of

58

KCOL[1..16] 35
KROW[8..1] 35

5V_S0
KBC_XO

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

15
14
13
10

LAD0
LAD1
LAD2
LAD3

9
18
7

LFRAME#
LCLK
SERIRQ

150
151
173
152

RD#
WR#
MEMCS#
IOCS#

138
139
140
141
144
145
146
147

D0
D1
D2
D3
D4
D5
D6
D7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18

124
125
126
127
128
131
132
133
143
142
135
134
130
129
121
120
113
112
104
103

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19

TDATA_5
TCLK_5

117
116
115
114
111
110

PSDAT3
PSCLK3
PSDAT2
PSCLK2
PSDAT1
PSCLK1

17,21,37 LPC_LFRAME#
17,21 CLK33_KBC
17,27,37 P_SERIRQ
36 KBCBIOS_RD#
36 KBCBIOS_WE#
36 KBCBIOS_CS#
TP79
36

KBCBIOS_RD#
KBCBIOS_WE#
KBCBIOS_CS#

KBC_D[0..7]

KBC_D0
KBC_D1
KBC_D2
KBC_D3
KBC_D4
KBC_D5
KBC_D6
KBC_D7

36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36

3D3V_AUX_S5

2 C569
SC22P50V2JN-4GP

X3
X-32D768KHZ-15

2 C568
SC22P50V2JN-4GP

160
158

2
1

RN74

22

SMBC_G792

KBC_SCL2
KBC_SDA2

XCLKO
XCLKI

SCL1
SDA1
SCL2
SDA2

SRN10KJ-5-GP
U38

SRN10KJ-5-GP

KBC_SDA2

LPC

KB3910

GPIO29
GPIO28
GPIO27
GPIO26
GPIO25
GPIO24
GPIO23
GPIO22
GPIO21
GPIO20
GPIO19
GPIO18
GPIO17
GPIO16
GPIO15
GPIO14
GPIO13
GPIO12
GPIO11
GPIO10
GPIO09
GPIO08
GPIO07
GPIO06
GPIO05
GPIO04
GPIO03
GPIO02
GPIO01
GPIO00

155
149
148
119
118
109
108
107
106
105
86
85
75
70
69
63
62
55
54
48
22
21
20
12
11
8
6
5
4
3

GPIO0F
GPIO0E
GPIO0D
GPIO0C
GPIO0B
GPIO0A

41
28
27
25
24
23

GPIO1F
GPIO1E
GPIO1D
GPIO1C
GPIO1B
GPIO1A

98
97
94
93
92
91

GPIOI2D
GPIO2F
GPIO2E
GPIO2C
GPIO2B
GPIO2A

168
175
171
165
162
156

MATRIXID2# 36
MATRIXID1# 36
PRE_CHG 47
BLT_BTN# 35
CHG_ON#
47
AD_OFF
48

A20
E51TXD
E51RXD
E51CS#

1 R251

TP71

TPAD28

2N7002DW-7F-GP

3
4

U32

KB Matrix

X-bus
ROM

RN72

BAT_SCL_5
BAT_SDA_5
KBC_SCL2
KBC_SDA2

KBC_XI

163
164
169
170

71
72
73
74
77
78
79
80
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

49
50
51
52
53
56
57
58
59
60
61
64
65
66
67
68
153
154

KROW1
KROW2
KROW3
KROW4
KROW5
KROW6
KROW7
KROW8

KCOL1
KCOL2
KCOL3
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9
KCOL10
KCOL11
KCOL12
KCOL13
KCOL14
KCOL15
KCOL16

3
4

3D3V_S0

KBC_SCL2

SMBC_G792
SMBD_G792

SMBD_G792 22

3D3V_AUX_S5
2

17,37 LPC_LAD[0..3]

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

2
16
34
45
123
136
157
166
95
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCA

161

SCD1U16V2ZY-2GP

3D3V_KBC_AUX_S5

C529
C525
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
D

L16
1
2
BLM11P600S

VCCBAT

1
2

3D3V_AUX_S5

C513
C534
C545
C570
C567
C552
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP

TP73 TPAD28
TP72

STDBY_LED# 16
GBUS_GRST# 27
INTERNET# 35
MAIL# 35
PM_SLP_S5# 20,45
4S1P_I 47
2 DY
PM_SUS_STAT# 20
0R2J-GP
TP66

R270
100KR2J-1-GP

3D3V_AUX_S5

2
1

3D3V_AUX_S5

RN73
48
48

2
1

BAT_SCL_5
BAT_SDA_5

3
4
SRN8K2J-3-GP

CAP_LED# 16
FRONT_PWRLED# 16
TP75
KBC_MUTE
33
KEY5# 35
TP76
TP77

WIRELESS_BTN# 35
KBCRST#
2
1
KBRCIN#
R286 10KR2J-2-GP
2
1
KA20GATE
20
R287 10KR2J-2-GP
KEY4# 35
BAT_THERMAL 47,48

www.kythuatvitinh.com
4
3
2
1

5
6
7
8

PS/2

1
2

R302
100KR2J-1-GP
C571

VCC3VSB

AMP_SHUTDOWN 33
R306 2
LPC_RST#
13,17,37,49
0R0402-PAD
BL_ON
13,52
CHK_PW# 36

1KR2J-1-GP

TP118

TP119

TP67

TP65
TP64TP63

TP70
TP69

GND
GND
GND
GND
GND
GND
17
35
46
122
137
167

96
159

ECRST#
ECSCI#

1
R278
10KR2J-2-GP
1KR2J-1-GP
R265 2
1

ECSCI#_KBC 20

3S
3S2P_I

20 PM_PWRBTN#
20,44 RSMRST#_KBC
22 S5_ENABLE
16 BRIGHTNESS

47
47

C553

17,20,38,39,45,56 PM_SLP_S3#
35 KBC_PWRBTN#
47
AC_IN#
35
KBC_LID#
20 KBC_SLP_WAKE
SB 0201

A1 for the internal pull-up resistors on XIOCS[F:0] pins==>High=enable,Low=Disable

A4 for DMRP==>High=Disable,Low=Enable

A5 for EMWB==>High=Enable,Low=Disable

AD_IA 47
KBC_BB_ENABLE# 36

R284
10KR2J-2-GP

19
31

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
81
82
83
84
87
88
89
90

DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7

GPWU0
GPWU1
GPWU2
GPWU3
GPWU4
GPWU5
GPWU6
GPWU7
TP74

R261 2

KBC_BEEP

KB3910SF-2-GP
CHANGE TO 71.03910.B0G

SCD1U16V2ZY-2GP
2

DUMMY-R2

ECSWI#

A1

20

B
2
Q15
CH3906PT-GP

R272

1
10KR2J-2-GP

RSMRST# 22

<Variant Name>

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

KBC KB3910

23 USB_PWR_EN#
Size
A3

Document Number

Date: Thursday, October 13, 2005

4

Wistron Corporation

GPIO05 for Clock test mode==>High=test Mode,Low=32KHz clock in normal running(Recommended)

GPIO06 for DPLL test mode==>High=Test Mode,Low=Normal operation(Recommended)
5

3D3V_AUX_S5
EC_RST#

32
R285

KBC_BB_ENABLE#
AD_IA

3D3V_AUX_S5

99
100
101
102
1
42
47
174

SRN10KJ-5-GP

RSMRST#_KBC

43
40
39
38
37
36
33
32

TDATA_5
TCLK_5

4
3

2
26
29
30
44
76
172
176

PWM7
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0

RN71
1
2

AGND
BATGND

RN70
5V_S0

3D3V_S5

BLUETOOTH_EN 23
DC_BATFULL# 16
BLT_LED# 16
WLAN_TEST_LED 29
MAIL_LED#
16
CHARGE_LED# 16

KBC_PCIRST#

R301
10KR2J-2-GP

ECSMI#_KBC 20
WIRELESS_EN 29
PM_CLKRUN# 17,25,27,29,30,37
FPBACK 16
NUM_LED# 16

35
35

TP68
R271 2 1KR2J-1-GP

SRN47J-4-GP

PRE_CHG

SC1U10V3ZY-6GP

5V_S0

20

Rev

Bolsena-E
Sheet
1

SA
34

of

58

POWER BUTTON

3D3V_AUX_S5

Cover Up Switch

3D3V_S5
1

Power
PWRBTN#_1
1 PWR1
2

R7
10KR2J-2-GP

R9

KBC_PWRBTN# 34

2
470R2J-2-GP

62.40009.431

34

C12
SCD1U25V3ZY-3GP

LID_SW
2
100R2F-L1-GP-U

1
2
4

C13
SC1000P50V2JN-N1

MLX-CON2-5-GP

20.D0173.102

3D3V_S5
SRN10KJ-6-GP
8
7
6
5

1
2
3
4

SRN470J-3-GP
MAIL#_1
KEY4#_1
KEY5#_1
INTERNET#_1

4
3
2
1

5
6
7
8

MAIL#
34
KEY4#
34
KEY5#
34
INTERNET# 34

5V_S0

TOUCH PAD

5V_S0

RN8
1
2

RN9

3
4
SW-TACT-59-GP-U1

3
4
SW-TACT-59-GP-U1

62.40009.431

1 P2

5
3
4
SW-TACT-59-GP-U1

62.40009.431

TDATA_5
TCLK_5

3
4
SW-TACT-59-GP-U1

62.40009.431

1
2
TP_SCROLL_UP
1 SCRL1
2

1
2
TP_DATA
TP_CLK

4
3
SRN100J-3-GP

C385

C374

62.40009.431

3
4
SW-TACT-59-GP-U1

62.40009.431
BlueTooth ON/OFF

RN27
34
34

SC47P50V2JN-3GP

P1

TP_SCROLL_LEFT
1 SCRL2
2

Wireless ON/OFF

MLX-CON12-10-GP

SRN10KJ-5-GP
KEY5#_1
2

P2
KEY4#_1
2

P1

INTERNET#_1
1 NET1
2

TPAD1
C390
SC1U10V3KX-3GP

4
3

Internet
MAIL#_1
2

C389
SCD1U25V3ZY-3GP

5
6
7
8

Mail

4
3
2
1

RN28

RC1
SRC100P50V-2-GP

SC47P50V2JN-3GP

Buttons

1 MAIL1

R12

KBC_LID#

ME : 62.40009.241
(ALL 11 PCS)

LID1

PWRBTN#_1

3
4
SW-TACT-59-GP-U1

Main : 20.D0173.102
2nd:20.F0714.002

R22
47KR2J-2-GP

TP_SCROLL_RIGHT
1 SCRL3
2

TP_RIGHT
TP_SCROLL_RIGHT
TP_SCROLL_UP
TP_SCROLL_LEFT
TP_SCROLL_DOWN
TP_LEFT

14
12
11
10
9
8
7
6
5
4
3
2

1
13

www.kythuatvitinh.com
BLUE2

BLT_BTN#_1

4
PUSH-SW89

?ESD ?

ME : 22.40082.081
2nd:22.40069.811

3
4
PUSH-SW89

3
4
SW-TACT-59-GP-U1

62.40009.431

TP_SCROLL_DOWN
1 SCRL4
2

C644
C645
SCD1U25V3ZY-3GP
SCD1U25V3ZY-3GP

3D3V_S5

RN76

34 WIRELESS_BTN#
34
BLT_BTN#

1
1

WIRELESS_BTN#_1
R367 2 470R2J-2-GP
R366 2 470R2J-2-GP BLT_BTN#_1

1 LEFT1

SRN10KJ-5-GP
4
3

TP_RIGHT
1 RIGHT1
2

3
4
SW-TACT-59-GP-U1

3
4
SW-TACT-59-GP-U1

62.40009.431

3
4
SW-TACT-59-GP-U1

62.40009.431

62.40009.431

RC10

KROW[8..1] 34
KCOL[1..16] 34

KB1

25

NC#26
C01
C02
C03
R01
R02
R03
C04
R04
R05
R06
R07
R08
R09
C05
R10
C06
C07
R11
R12
C08
R13
R14
R15
R16
NC#25
NC#27

........

26
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
27

KROW1
KROW2
KROW3
KCOL1
KCOL2
KCOL3
KROW4
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9
KROW5
KCOL10
KROW6
KROW7
KCOL11
KCOL12
KROW8

MLX-CON25-1-GP

20.K0192.025

KCOL13
KCOL14
KCOL15
KCOL16

TP_RIGHT
TP_SCROLL_RIGHT
TP_SCROLL_UP
TP_SCROLL_LEFT

RC7

Pin1 ==>*R01
Pin2 ==>*R02
Pin3 ==>*R03
Pin4 ==> C01
Pin5 ==> C02
Pin6 ==> C03
Pin7 ==>*R04
Pin8 ==> C04
Pin9 ==> C05
Pin10 ==> C06
Pin11 ==> C07
Pin12 ==> C08
Pin13 ==> C09
Pin14 ==>*R05
Pin15 ==> C10
Pin16 ==>*R06
Pin17 ==>*R07
Pin18 ==> C11
Pin19 ==> C12
Pin20 ==>*R08
Pin21 ==> C13
Pin22 ==> C14
Pin23 ==> C15
Pin24 ==> C16
Pin25 ==> NC

KROW7
KCOL11
KCOL12
KROW8

1
2
3
4

8
7
6
5

KCOL5
KCOL6
KCOL7
KCOL8

1
2
3
4

SRC100P50V-2-GP
RC5
8
7
6
5

KCOL2
KCOL3
KROW4
KCOL4

1
2
3
4

SRC100P50V-2-GP
RC4
8
7
6
5

KCOL9
KROW5
KCOL10
KROW6

1
2
3
4

SRC100P50V-2-GP
RC6
8
7
6
5

KROW1
KROW2
KROW3
KCOL1

1
2
3
4

SRC100P50V-2-GP
RC3
8
7
6
5

1
2
3
4

SRC100P50V-2-GP
RC8
8
7
6
5

KCOL13
KCOL14
KCOL15
KCOL16

ME :20.K0192.025
2nd:20.K0197.025

1
2
3
4

8
7
6
5

DY SRC100P50V-2-GP

RC9
TP_LEFT
TP_SCROLL_DOWN

1
2
3
4

8
7
6
5

DY SRC100P50V-2-GP

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

BUTTONs / KB / TOUCHPAD
Size
A3

SRC100P50V-2-GP

Document Number

Rev

SA

Bolsena-E

Date: Thursday, October 13, 2005

A

TP_LEFT
2

EMI Bypass cap.

Internal KeyBoard CONN

1

1
2

20.K0185.012
ME : 20.K0185.012
2nd:20.K0174.012

3
4
SW-TACT-59-GP-U1

62.40009.431

1
2

WIRELESS_BTN#_1

WIRELESS_BTN#
BLT_BTN#

WLAN1

Sheet
E

35

of

58

KBC_D[0..7] 34

34 KBCBIOS_WE#
34 KBCBIOS_RD#
34 KBCBIOS_CS#
A18
A17
A16

34
34
34

22
24
31

1
30
2
A18
A17
A16

3
29
28
4
25
23
26
27

A15
A14
A13
A12
A11
A10
A9
A8

34
34
34
34
34
34
34
34

A0
A1
A2
A3
A4
A5
A6
A7

A15
A14
A13
A12
A11
A10
A9
A8

16

SST39VF040-70-1

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

12
11
10
9
8
7
6
5

13
14
15
17
18
19
20
21

KBC_D0
KBC_D1
KBC_D2
KBC_D3
KBC_D4
KBC_D5
KBC_D6
KBC_D7

VSS

34
34
34
34
34
34
34
34

CE#
OE#
WE#

32

C895
U77
SCD1U16V2ZY-2GP
VDD

3D3V_AUX_S5

(SOCKET) 62.10002.032 - (IC)72.39040.H03 IN DIP,SMT

C

34
34
34
34
34
34
34
34

A0
A1
A2
A3
A4
A5
A6
A7

www.kythuatvitinh.com
ROM SIZE MAX. 512KBYTE

PLCC32 Socket P/N:

SSKT3262.10002.032
SSKT32 62.10005.032

8
7
6
5

3D3V_S0
3D3V_S0

1
2
3
4

RN24
SRN10KJ-6-GP

SW1
34 KBC_BB_ENABLE#

34 CHK_PW#

34 MATRIXID1#

34 MATRIXID2#

5
SW-2184LPSTR-1GP

Keyboard matrix ( from vendor )

<Variant Name>

US

Jap

Eur

Other

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Low Bit

MATRIXID1#

High Bit

MATRIXID2#

Title

BIOS ROM
Size
A3

Document Number

Date: Thursday, October 13, 2005

5

Rev

Bolsena-E

SA
Sheet
1

36

of

58

17,21,34 LPC_LFRAME#
17,27,34 P_SERIRQ

17

PCIRST_BUF#_SIO
2
33R2J-2-GP

1
RB1

13,17,34,49 LPC_RST#
LPC_LDRQ0#

C524

1
SC10P50V2JN-1

17,34 LPC_LAD[0..3]

CLK14_SIO 3

DY

SC10P50V2JN-1
DY
CLK33_SIO 17,21

CTS1#
DCD1#
DSR1#
RI1#
SIN1
CLKRUN#/GPIO22
VCORF

2
47
48

DTR1#_BOUT1/BADDR
RTS1#/TRIS#
SOUT1/TEST#

42
43
25
NC
CLKIN
LCLK

32
36
38
40

16
27
28
30
LDRQ#/XOR_OUT
LRESET#
SERIRQ
LFRAME#

1
44
45
3
46
19
10

LAD0
LAD1
LAD2
LAD3

8
24
35

U31

VDD
VDD
VDD

2
R282

1CLK33_SIO_T2
10R2J-2-GP C544

C533
SCD1U16V2ZY-2GP

C550
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

C540

SC4D7U10V5ZY-3GP

C551

DY

LPC_LAD3
LPC_LAD2
LPC_LAD1
LPC_LAD0

3D3V_S0

NC
NC
NC
NC
NC
NC
NC
NC
NC

33
37
39
41
4
18
26
29
31

RESERVED/GPO24

20

VSS
VSS
VSS

IRRX1
IRRX2_IRSL0/GPIO17
IRTX

9
23
34

11
12
13
14
15
17
21
22

5
7
6

R264
10KR2J-2-GP

VCORF

PC87381-VBH-GP

IRTX_3
IRSL0_3
IRRX_3

Infineon FIR Module

3D3V_S0

IR1

40mil
1

SCD1U16V2ZY-2GP
BADRR_STRAP

10mil

C857
C885
10mil
SC1U10V3KX-3GP SC4D7U10V5ZY-3GP 10mil
2

17,25,27,29,30,34 PM_CLKRUN#

GPIO00
GPIO01
GPIO02
GPIO03
GPIO04
GPIO20
GPIO21/LPCPD#
GPIO23

www.kythuatvitinh.com
C541

DY

1
R559

IRTX_3
IRRX_3
IRSL0_3
2 IRMODE
10KR2J-2-GP

1
2
3
4
5
6
7
8

VCC2/IRED_ANODE
IRED_CATHODE
TXD
RXD
SD
VCC1
MODE
GND

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

FIR-TFDU6102-GP
Title

56.15001.051

SUPER IO NC87381
Size
A3

Document Number

Rev
-2

SNIPE

Date: Thursday, October 13, 2005

Sheet

37

of

58

Run Power

41

12VGATE_S0

SCD1U25V3ZY-3GP
C566

5V_S0

5V_S5
U36

DY

3D3V_S5
U26
1
2
3
4

3D3V_S0
SCD1U25V3ZY-3GP
C505
1
2

Q18
2N7002PT-U

1
G

2
3

SC1U10V3KX-3GP

C586

AO4422-1-GP
Q19
PDTC144EU-1-GP

C506
SCD1U25V3ZY-3GP

2
1K5R3-GP

8
7
6
5

1
R315

17,20,34,39,45,56 PM_SLP_S3#

C549
SCD1U25V3ZY-3GP

AO4422-1-GP
D21
MMGZ5242BPT-GP

2C

2
3

SCD22U16V3ZY-GP

C580
580

DY

R310
1KR2J-1-GP

8
7
6
5
1

1
2
3
4

R308
330KR2J-L1-GP

R303
47KR2J-2-GP

R311 2 PM_RUNCTL_G
330KR2J-L1-GP

Q17
TP0610T

G
S
S
S

D
D
D
D

R312 2 PM_RUNCTL 2
10KR2J-2-GP

G
S
S
S

1
1

D
D
D
D

DCBATOUT

SB 0201
3

2D5V_S3

2D5V_S0
SCD1U25V3ZY-3GP
DY C786

U60
1
2
3
4

8
7
6
5

www.kythuatvitinh.com
2

D35

RB751V-40-1-GP

G
S
S
S

2D5V_S0

D
D
D
D

1D8V_S0

C797
SCD1U25V3ZY-3GP

AO4422-1-GP

1D8V_S5

1D8V_S0

DY C749 SCD1U25V3ZY-3GP U56

AO4422-1-GP

8
7
6
5
1

1
2
3
4

G
S
S
S

D
D
D
D

C405
SCD1U25V3ZY-3GP

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

PWR CTL LOGIC / PWR PLANE

Size
A3

Document Number

Rev

SA

Bolsena-E

Date: Thursday, October 13, 2005

Sheet
E

38

of

58

U41A

U41B

R332 2
270KR2F-L-GP

1D2V_S0_EN 45

TSLCX08MTCX-GP
73.07408.02B
4

3D3V_S5

C603
SC1U10V3ZY-6GP

U30A

1
3

NB_PWRGD

R258 2
330R2J-3-GP

SB_PWRGD 20

TSLCX08MTCX-GP

C526
DUMMY-C3

SB_PWRGD IS 35MS
AFTER NB_PWRGD

1D2V_S0_EN

?U54 CHOOSE CHEAPER

VRM_PWRGD

1KR2J-1-GP
2

DY

220KR2J-L2-GP

R333

TSLCX14MTC-L-U

U33B

TSLCX14MTC-L-U

14

NB_PWRGD_N

5V_S5

17,20,34,38,45,56 PM_SLP_S3#
R321

NB_PWRGD

Reduce leakage
(WHEN 3D3V_AUX_S5 ON, 3D3V_S0 OFF)

3D3V_AUX_S5

14

14

3D3V_AUX_S5

14

2D5V_S0
2

5V_S5
R279
10KR2J-2-GP
U33C

14
1

VTT_VDDA_PG

13
11

VCORE_EN 41,52

12
C542
SCD1U25V3ZY-3GP
PM_SLP_S3#

TSLCX08MTCX-GP

1
2

73.07408.02B

3D3V_S5

www.kythuatvitinh.com
3D3V_S5

PM_SLP_S3#

14

14

U30C

13

11

VTT_VRM_PG

12

VRM_PWRGD

22

NB_PWRGD 13,52

TSLCX08MTCX-GP

73.07408.02B

20,41 VRM_PWRGD

U30D

10

TSLCX08MTCX-GP

RUNPWROK

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

POWERGOOD&ENABLES
Size
Document Number
Custom

Rev

SA

Bolsena-E

Date: Thursday, October 13, 2005

Sheet
E

39

of

58

5V_AUX_S5

CPU_CORE
MAX1544ETL
VID0_PWM
VID1_PWM
4

VID2_PWM
VID3_PWM
VID4_PWM

VID Setting

DCBATOUT

Output Signal

VID0(I / 3.3V)

INPUT

AUX_SD

VROK()

VID1(I / 3.3V)

5V_AUX_S5

OUT

SD

MAX1544_VRM

LP2951ACM
4

VID2(I / 3.3V)

1D25V_S3
2D5V_S3

VID3(I / 3.3V)

Output Power

VID4(I / 3.3V)

TI TPS5130
2D5V/1D2V/1D8V

VCC_CORE_S0(Imax=27.3A)

VCC_CORE_PWR(O)

VIN

5V_S5
APL5331_1D25V_VREF

Input Signal

Output Signal

1D25V_S0

VOUT

VCNTL
VREF

APL5331KAC
FOR
PM_SLP_S5#
SS_STBY1(I / 5V) 2.5V

Input Signal
VCORE_EN

EN (I / 3.3V)

1D2V_S0_EN
S5PWR_ENABLE

Voltage Sense
COREFB

VSEN(I / Vcore)

COREFB#

RGND(I / Vcore)

GND

DCBATOUT
5V_S0

DCBATOUT_5130

FAN5234_VGA_Core
1D15V or 1D20V

Pull High (5V)

Input Power

SS_STBY3(I / 5V) FOR

1.8V
STBY_LDO(I / 5V)

5V_S0

2D5(O)

STBY_VREF5(I / 28V)

Output Power

VCC

DCBATOUT

Output Power

Input Power

PGOUT(OD / 5V)

FOR
SS_STBY2(I / 5V) 1.2V

1D15V (O)
or
1D20V (O)

VIN

1D15V (5.2A)
or
1D20V (9A)
3

2D5V (9A)

www.kythuatvitinh.com

3D3V_S0

VCC(I)

DCBATOUT_5130

VCC(I)

VCC(I)

5V_S5

5V_AUX_S5

TPS51120
5V/3D3V

5V_S0
Input Signal

1D2V(O)

Input Power

DCBATOUT

STBY_VREF3.3(I / 28V)

Output Signal

1D8V(O)

Input Signal

PM_SLP_S3#

1D2V (5A)

EN

Output Signal

1D8V (5A)

PG

VIN (I / 28V)

LDO(O)

REG5V_IN(I / 5V)

Adapter

5V_AUX_S5

AD_OFF

Input Signal

(O)

For PGOUT

Output Power

Input Power
SHUTDOWN_S5
SHUTDOWN_S5
DCBATOUT
PM_SLP_S3#

ON3

MAX1999_PGD

Output Power

BT_TH

SHDN#
SKIP#

V+

5V(O)

5V_S5 (6A)

BAT+SENSE
BT_SCL_5

3D3V(O)

LDO5(O)

3D3V_S5 (4A)

MAX1999_LDO5 (30mA)

BT_SDA_5
FLASH_GPIO1
FLASH_GPIO2

LDO3 (O)

MAX1999_LDO3 (30mA)

AD_JK

Charger_Max8725
CHARGE_OFF

ON5

Input Power
DCBATOUT

PGOOD(OD / 5V)

AD_IN

Output Signal

(I)

AC_IN

Input Signal

Output Signal
LDO (O / 5.4V)

CLS (I / 3.3V)
THM (I / 3.3V)
BATT (I / 3.3V)

XTAL2/PB4 (O/5V)
XTAL1/PB3 (O/5V)

5V_AUX_S5
AD_IN

AD+

VCC(O)

VCC(I)
VCC(I)

CHARGE_LED#
BL2#

SCL (IO / 5V)

SDA (IO / 5V)
RESET#/PB5 (I/5V)
PB0/MOSI/AIN0

Output Power
VCC (O)
VCC (O)

DCBATOUT
BT+

<Variant Name>

PB0/MOSI/AIN0

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

AD+

Input Power

Title

DCIN (I)

POWER BLOCK DIAGRAM

(Power Team)

Size
A3

Document Number

Date: Thursday, October 13, 2005

A

Rev

SA

Bolsena-E
Sheet
E

40

of

58

5V_S0

CPU_VCORE
VID=1.20V
Iomax=27.3A (35W)
OCP=40A~45A

D39
MAX1544_BSTS

2
1

MAX1544_VCC
1

2
MAX1544_REF 1 R208

2
121KR2F-L-GP

MAX1544_ILIM

R206
60K4R3F-GP

MAX1544_V+

MAX1544_CMN 42
MAX1544_CMP 42
1 R205

TIME
TON
SUS
OFS
REF
CCI

DLM
DHM

29
28

LXM
BSTM
VROK

27
26
25

VID0_PWM
24
VID1_PWM
23
VID2_PWM
22
VID3_PWM
21
VID4_PWM
20
MAX1544_OVP19

D0
D1
D2
D3
D4
OVP

CCV
DLS
LXS
ILIM

12
32
34
9

1 R183

MAX1544_CSP 42
MAX1544_CSN 42

40
39

MAX1544_TIME1
2
3
MAX1544_OFS 7
MAX1544_REF 8
2 R209
1
100KR2F-L1-GP MAX1544_CCI 14

MAX1544_VCC

For Dummy Phase 2

MAX1544_VCC

DY

CSP
CSN

38
37

33
DHS

CMN
CMP

V+

0R2J-GP

18
6

36

MAX1544_VCC
10
30

U18

VCC
VDD

C420

SC1U25V5ZY-4GP

C426

DY

VCORE_EN 39,52
MAX1544_DHS 42

SKIP#
SHDN#

1
1

1544_AGND

R201
12K7R2F-GP

R186
100KR2J-1-GP

MAX1544_SKIP#

SC2D2U10V5KX-LGP SC1U10V3KX-3GP
2
1

C431

MAX1544_V+

R202
0R0603-PAD

TABLE 1. VOLTAGE IDENTIFICATION CODES

VID4 VID3 VID2 VID1 VID0 DAC
0
0
0
0
0
1.550
0
0
0
0
1
1.525
0
0
0
1
0
1.500
0
0
0
1
1
1.475
0
0
1
0
0
1.450
0
0
1
0
1
1.425
0
0
1
1
0
1.400
0
0
1
1
1
1.375
0
1
0
0
0
1.350
0
1
0
0
1
1.325
0
1
0
1
0
1.300
0
1
0
1
1
1.275
0
1
1
0
0
1.250
0
1
1
0
1
1.225
0
1
1
1
0
1.200
0
1
1
1
1
1.175
1
0
0
0
0
1.150
1
0
0
0
1
1.125
1
0
0
1
0
1.100
1
0
0
1
1
1.075
1
0
1
0
0
1.050
1
0
1
0
1
1.025
1
0
1
1
0
1.000
1
0
1
1
1
0.975
1
1
0
0
0
0.950
1
1
0
0
1
0.925
1
1
0
1
0
0.900
1
1
0
1
1
0.875
1
1
1
0
0
0.850
1
1
1
0
1
0.825
1
1
1
1
0
0.800
1
1
1
1
1
Shutdown

1 MAX1544_BSTM
R214
10R2J-2-GP BAW56PT-U

DCBATOUT_MAX1544

MAX1544_DLM 42
MAX1544_DHM 42
MAX1544_LXM 42,58
1
2 C404
SCD22U16V3KX-2-GP
R185 2
3D3V_S0
100KR2J-1-GP

MAX1544_BSTM

VRM_PWRGD 20,39

MAX1544_CCV
MAX1544_DLS 42
MAX1544_LXS 42,58

MAX1544_ILIM

GND
GND

1
2

R203
100R2F-L1-GP-U

1544_AGND
1544_AGND

C434
SC270P50V2JN-2GP

R210
26K7R2F

SC470P50V3JN-2GP
2

R198
1MR2J-1-GP

COREFB# 6

1544_AGND

R194
1KR2F-3-GP MAX1544_CCI
2

MAX1544_BSTS
2 C423
SCD22U16V3KX-2-GP

41
11

C432
SC1000P50V3JN-GP
1

BSTS

GNDS
PGND

13
31

35

15

2
2

1544_AGND

R196
R197
1KR3F-GP
1KR2F-3-GP R193
1KR3F-GP

1
2
0R0402-PAD

1544_AGND
MAX1544_GNDS

C427

R187
511R3F-GP

R199
511R3F-GP
1

R192

1
2

1544_AGND

MAX1544_BSTS

C438
SCD22U16V3KX-2-GP

MAX1544_FB

R207
80K6R3F-1-GP
C433
SC100P50V3JN-2GP

1544_AGND

MAX1544_OAIN+
MAX1544_OAIN-

Frequency:
550KHz
300KHz
200KHz
100KHz

4
5

MAX1544ETL-1-GP

TON:
GND
REF
OPEN
VCC

S0
S1

OAINOAIN+

16
17

1544_AGND
1544_AGND

FB

www.kythuatvitinh.com
100KR2J-1-GP

For alone test==>short C395 pin1 and pin2

MAX1544_CMP
COREFB 6

12VGATE_S0 38
U16
2N7002DW-7F-GP

VID3

MAX1544_FB
MAX1544_CMN
MAX1544_CSN

VID2

VCC_CORE_S0

VID3_PWM

U17
2N7002DW-7F-GP
VID1_PWM

R188
0R0402-PAD

VID0
2

VID0_PWM

MAX1544_CSP

VCC_CORE_S0 feedback
6

VID[4..0]

VID1

VID2_PWM
<Variant Name>

Wistron Corporation
G

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

VID4

From KBC

VID4_PWM

Title

CPU Vcore 1

2N7002PT-U
Q8

Size
A3

(Power Team)
A

Document Number

Date: Thursday, October 13, 2005

Rev

SA

Bolsena-E
Sheet
E

41

of

58

GAP-CLOSE-PWR
GAP-CLOSE-PWR

2 DUMMY-C3

TC24
SE100U25VM-7GPU

DY

1
TC3

TC5

TC7
2

TC6

DY

AO4422-1-GP
U64

4
3
2
1

G
S
S
S

D
D
D
D

5
6
7
8

SC1U25V5ZY-4GP

C384

TC22
SE330U2VDM-L-GP

TC4

C832

SE330U2VDM-L-GP

DCBATOUT_MAX1544

2 C843
SC10U35V0ZY-1GP

GAP-CLOSE-PWR

G79

2 C831
SC10U35V0ZY-1GP

SE330U2VDM-L-GP

VCC_CORE_S0

GAP-CLOSE-PWR

G78

SE330U2VDM-L-GP

2 C842
SC10U35V0ZY-1GP

SE330U2VDM-L-GP

SE330U2VDM-L-GP

GAP-CLOSE-PWR
2

G72

SC1U25V5ZY-4GP

GAP-CLOSE-PWR

C370

2
G70

G74

DCBATOUT

2
G73

GAP-CLOSE-PWR

G71

VCC_CORE_S0
L28

41 MAX1544_DHM
1

41,58 MAX1544_LXM
U63

D001R7520F-1-GP
3

IND-D56UH-15-GP
D
D
D
D

41 MAX1544_DLM

1 R524

5
6
7
8

R527
0R0402-PAD

www.kythuatvitinh.com
4
3
2
1

S
S
S
G

AO4430-1-GP

MAX1544_CMN 41
MAX1544_CMP 41

2 C841
SC10U35V0ZY-1GP

AO4422-1-GP
U65

4
3
2
1

G
S
S
S

D
D
D
D

5
6
7
8

DCBATOUT_MAX1544

VCC_CORE_S0

L30

41 MAX1544_DHS
1

41,58 MAX1544_LXS
41 MAX1544_DLS

D001R7520F-1-GP

U67

5
6
7
8

IND-D56UH-15-GP

1 R530

D
D
D
D
2

AO4430-1-GP

<Variant Name>

4
3
2
1

S
S
S
G

SB 0203
R536
0R0402-PAD

Wistron Corporation

MAX1544_CSN 41
MAX1544_CSP 41

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

CPU Vcore 2
(Power Team)

Size
A3

Document Number

Date: Thursday, October 13, 2005

A

Rev

SA

Bolsena-E
Sheet
E

42

of

58

DCBATOUT_51120

G97
1

G33

22,45 S5PWR_ENABLE

TP61 TPAD30
TP62 TPAD30
R260 0R3J-3-GP
1
2
1
2
51120_V5FILT
R262 0R3J-3-GP

29
12
10
9

4
3
2
1

GAP-OPEN-PWR
G93
1
2

TC27
ST220U6D3VDM-13GP

SANYO 220uF ESR=25mohm

Iripple=2.4A

GAP-OPEN-PWR
G92
1
2

R563
7K5R3F-L1-GP

DY

5V_S5

GAP-OPEN-PWR
G96
1
2

1
1
2

R562

51120_DRVL1

3D3V_S0

GAP-OPEN-PWR
G91
1
2
GAP-OPEN-PWR

G47
51120_GND

COMP2
COMP1

V5FILT
VIN

5
6
7
8
D
D
D
D
G
S
S
S
4
3
2
1

2
0R3J-3-GP
2
0R3J-3-GP

7
2

20
22

28
13

19
21

0R3J-3-GP
R275
51120_EN1
1
2
51120_EN2
1
2
R2530R3J-3-GP

51120_VFB1

DY

GAP-OPEN-PWR
G94
1
2

C523

51120_GND

C859

51120_COMP2 1
R257
51120_COMP1
1
R263

VBST1
VBST2

51120_VREG3

VREG3
VREG5

51120_GND

DY

51120_V5FILT

5V_PWR

IND-3D3UH-43-GP

C532
SCD1U50V3ZY-GP

C531

SC10U10V5KX-2GP

SC10U10V5KX-2GP

251120_LL1_1 1
251120_VBST1
0R3J-3-GP
SCD1U50V3ZY-GP
51120_VREG5

GAP-OPEN-PWR
G95
1
2

5V Iomax=5A
OCP>10A

30KR3F-2-GP

C538
51120_LL11
R274

5V_PWR
1

SC33P50V3JN-GP

U34
AO4702-1-GP

C557
SCD1U50V3ZY-GP

L36

DCBATOUT_51120

C573

SC10U35V0ZY-1GP

51120_DRVH1
51120_LL1

251120_LL2_1 1
251120_VBST2
0R3J-3-GP
SCD1U50V3ZY-GP

GAP-OPEN-PWR

C572

R276

EN1
EN2
EN3
EN5

LL2
LL1

51120_LL2
51120_LL1

15
26

100KR2J-1-GP

DY

GAP-OPEN-PWR
G46
1
2

C514
51120_LL21
R252

S
S
S
G

DCBATOUT

C527
51120_GND

SC1U10V3KX-3GP

51120_VREG5 1
2
5D1R3F-GP

1
R259

GAP-OPEN-PWR
G35
1
2
GAP-OPEN-PWR
G37
1
2

D
D
D
D

U37
AO4422-1-GP

GAP-OPEN-PWR
G36
1
2

5
6
7
8

51120_V5FILT

SC10U35V0ZY-1GP

GAP-OPEN-PWR
G34
1
2

GAP-OPEN-PWR
G98
1
2

DCBATOUT_51120

DY

GAP-OPEN-PWR
G44
1
2

1
2

IND-2D5UH-6-GP

4
3
2
1

DY

290k/CH1
440k/CH2

220k/CH1
330k/CH2

180k/CH1
280k/CH2

VFB1

N/A

not use

ADJ.

VFB2

N/A

not use

ADJ.

5V
Fixed Output
3.3V
Fixed Output

EN1,EN2 Switcher OFF

not use

Swithchr ON

Switcher ON

EN3,EN5

not use

LDO ON

LDO OFF

C539

51120_GND

VREG3 on

1
2

51120_GND

DY
C855

51120_GND

For TPS51120,
Vout=5V
1. If you use
2. If you use
3. If you use
Vout=3.3V
1. If you use
2. If you use
3. If you use

<Variant Name>

a 6.8uH inductor, the minimum ESR is 70m ohm.

a 4.7uH inductor, the minimum ESR is 48m ohm.
a 3.3uH inductor, the minimum ESR is 34m ohm.

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

a 4.7uH inductor, the minimum ESR is 51m ohm.

a 3.3uH inductor, the minimum ESR is 36m ohm.
a 2.5uH inductor, the minimum ESR is 27m ohm.

TPS51120 / 3D3V / 5V
Size
A3

Document Number

Date: Thursday, October 13, 2005

5

GAP-CLOSE-PWR

380k/CH1
590k/CH2

DY

TONSEL

D-Cap
MODE

CURRENT
MODE

N/A

Vout=1V*(R1+R2)/R2
SC680P50V3JN-GP

N/A

C856

G48

SANYO 220uF ESR=25mohm

Iripple=2.4A

51120_GND
51120_COMP2_PL

COMP

PWM

SC390P50V3JN-GP

PWM

DY
R558
22KR3F-GP

DY

SC1000P50V3JN-GP

AUTOSKIP
/FAULTS
OFF

SC390P50V3JN-GP

AUTOSKIP

51120_COMP1_PL

C537

SKIPSEL

R269
30KR3F-2-GP

DY

DY

V5FILT

FLOAT

VREF2

GND

TC16
ST220U6D3VDM-13GP

R561
13KR3F-GP

DY

51120_COMP2

51120_COMP1

R560

51120_VFB2
51120_DRVL2

DY
2

C858

51120_GND

3D3V Iomax=5A
OCP>10A

30K9R3F-GP

11KR3F-GP
R256

U25
AO4702-1-GP

3D3V_PWR

L35

0R2J-GP
R277
0R3J-3-GP

51120_CS2

GAP-OPEN-PWR

SC10U35V0ZY-1GP

CS1
CS2

PGND1
PGND2
GND
GND

23
18

151120_SKIPSEL 32
31

51120_DRVH2
51120_LL2

251120_VREF2

GAP-OPEN-PWR
G45
1
2

C508

R268

51120_TONSEL1

G
S
S
S

51120_GND
51120_CS1

GAP-OPEN-PWR
G43
1
2

C507

SC33P50V3JN-GP

24
17
5
33

11KR3F-GP
1
2
R266

U27
AO4422-1-GP

SC10U35V0ZY-1GP

TPS51120RHBR-GPU1

51120_DRVH1
51120_DRVH2

S
S
S
G

51120_V5FILT

U28

27
14

D
D
D
D

51120_GND

SC1000P50V3JN-GP

C528

DRVH1
DRVH2

VREF2

5
6
7
8

4
3
2
1

51120_VREF2

DRVL1
DRVL2

3D3V_S5

GAP-OPEN-PWR
G42
1
2

DCBATOUT_51120

5
6
7
8

VO1
VO2

DY

3D3V_PWR

D
D
D
D

1
8

5V_PWR
3D3V_PWR

25
16

2
0R2J-GP
2
0R2J-GP

VFB2
VFB1

51120_PGD1
1
51120_PGD2 R2671
R254
51120_DRVL1
51120_DRVL2

SKIPSEL
TONSEL

6
3

30
11

www.kythuatvitinh.com
51120_VFB2
51120_VFB1

PGOOD1
PGOOD2

Rev

-1

Bolsena-E
Sheet
1

43

of

58

5V_S5

R273
10KR2J-2-GP
2

Aux Power

3D3V_AUX_S5

CH3906PT-GP
Q16

B
1

20,34 RSMRST#_KBC

5V_S5

3D3V_AUX_S5

3D3V_AUX_S5

2
8
7
6

OUTPUT
INPUT
SENSE
FEEDBACK
SHUTDOWN
VO TAP
GND 100mA
ERROR# OUTPUT

1
2
3
4

C522
DUMMY-C5

1
2

1
2

C535
SC1U10V3ZY-6GP

C536
SCD1U16V2ZY-2GP

C521
SC1U25V5ZY-4-GP

G913CF-GP
C547
SC10U10V5ZY-1GP

OUT

3D3V_G913_SET

1
2

C548

SC1U10V3ZY-6GP

SC10U10V5ZY-1GP

U29 SCD1U16V2ZY-2GP

DUMMY-C3

C556

DCBATOUT

C530
1
2

1
C555

SET

C554

C546

2
SC1U10V3ZY-6GP

DY

SHDN#
GND
IN

SC1U10V3ZY-6GP

CH521S-30-GP-U

1
2
3

Rx
R288
16K5R2F-1-GP

Output = 3.3
output=1.25(

U35
D16
1

C560

R299
10KR2F-2-GP
2

5V_AUX_2951

SC22P50V2JN-4GP
2
1

5V_S5_G913

2
CH521S-30-GP-U

D17
1

R283
10KR2J-2-GP

Ry

DY

www.kythuatvitinh.com
LP2951CDR2G-GP

5V_S5

C892
SC10U10V5ZY-1GP
78.10693.41L

1D25V_S3
Iomax=1.5A

1
2

2D5V_S3DY

C891
SCD1U25V3ZY-3GP

G88 GAP-CLOSE-PWR
2

G87 GAP-CLOSE-PWR
2

GND
GND

NC
NC
NC

8
7
5

DY

G89 GAP-CLOSE-PWR
2
1D25V_S3

G90 GAP-CLOSE-PWR
2

2
9

TC25
SE100U10VM-4GP

C884
SC22U10V6ZY-1-GP

79.10111.40L

R565
1KR2F-3-GP C890
SCD1U25V3ZY-3GP

VOUT

VIN
VREF
VCNTL

1
3
6

1D25V_LDO

U76

APL5331_1D25V_VREF

Vo(cal.)=1.250V
R564
1KR2F-3-GP

C893
SC10U10V5ZY-1GP
78.10693.41L
2

1
2

2D5V_S3

APL5331KAC-TRLGP

SO-8-P

KEMET
100uF / 4V / B2 Size / NTD:5.615
Iripple=1.1A / ESR=70mohm

Trace Length=1cm (500mils)

Trace Width=8mils
Trace Resistance>25mohm

<Variant Name>
1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

1D2V_S3 / 3D3V_AUX
Size
A3

(Power Team)
A

Document Number

Date: Thursday, October 13, 2005

Rev

SA

Bolsena-E
Sheet
E

44

of

58

4
2D5V_PWR

1
1

R195
2KR2F-3-GP

5130_5V_LDO

close to IC

1
R189
2KR2F-3-GP

5130_LH1
C391
5130_LL1
1
2
SCD1U50V3KX-GP

Voltage

L : PWM fixed (300KHz)

~0.3V(Max)

R181
5130_OUT1U 46
5130_OUT1D 46
5130_TRIP3

T(soft)=1.736ms

GAP-CLOSE-PWR
G84
2

GAP-CLOSE-PWR
G83
2

GAP-CLOSE-PWR
G76
2

GAP-CLOSE-PWR
G82
2

GAP-CLOSE-PWR
G86
2

5130_OUT2D

5130_OUT2D 46

GAP-CLOSE-PWR

OCP
12A=>R225=18K
18A=>R225=28K

close to IC
5130_FLT
5130_INV1

G80
1

GAP-CLOSE
ZZ.CON2C.XX1

U15

48
47
46
45
44
43
42
41
40
39
38
37

C408

GAP-CLOSE-PWR
G77
2

18KR2F-GP
C392
1
2
SCD1U25V3ZY-3GP

DCBATOUT_5130

5130_FLT
C399
SCD01U16V2KX-3GP

DCBATOUT_5130

5130_TRIP1
5130_TRIP2

OCP
8.4A=>R229=12.65K
10A=>R229=22K

5130_FB1
SB 0201

SCD1U25V3ZY-3GP

close to IC
2D5V_OCP

5130_LL1 46,58

5130_OUT1U
5130_OUT1D

2.2V(Min)~

SC3300P50V3KX-1GP

H : Auto PWM/SKIP

5130_INV1
2

C380
1
2

D12
BAT54PT-GP

4K32R2F-GP

PWM_SEL

DCBATOUT_5130

5130_TRIP2

1 2

5130_FB2

close to IC

1 2

R179

5130_INV2

Condition

2
GAP-CLOSE-PWR
G85
2

1
2
12K1R2F-L1-GP

SC4700P50V3KX-1GP
R544

1
2
10KR2F-2-GP

OCP
8.4A=>R226=13K
10A=>R226=22K

1D8V_OCP

D14
BAT54PT-GP

C412

close to IC

1
1 2
2

R539

1D2V_PWR

C406
1 R184
2
680R3F-GP

5130_5V_LDO

11K3R2F-2-GP
C386
1
2
SCD1U25V3ZY-3GP

11K5R2F-GP

5130_INV3
5130_FB3

680R3F-GP SC5600P50V3KX-GP
1 R547

SC3900P50V3KX-GP

SC3900P50V3KX-GP

close to IC

For 1.2V
SETTING=1.2172V

C410

2
10KR2F-2-GP

1 R190

DCBATOUT_5130

1
5130_TRIP1

C844
2
1

G75

R180

1D8V_PWR
R548

DCBATOUT_5130

1D2V_OCP

(1D2V=>CH1 , 1D8V=>CH2 , 2D5V =>CH3)

For 1.8V
SETTING=1.8275V

19K6R3F-GP

R541
2KR2F-3-GP

DCBATOUT

Vo=(R1*0.85)/R2+0.85

C393
1
2

330R2J-3-GP SC5600P50V3KX-GP
R543
1
2

R542 2
10KR2F-2-GP

C407

R182
1

For 2.5V
SETTING=2.516V
1

TI TPS5130 for 2.5V, 1.2V, 1.8V

G81

www.kythuatvitinh.com
2

R550

PM_SLP_S3#

R545
100KR2J-1-GP

C411

5130_FB1
R549
100KR2J-1-GP 5130_SS_STBY1
5130_INV2
5130_FB2
5130_SS_STBY2
5130_PWMSEL
5130_CT

1
2
3
4
5
6
7
8
5130_REF
9
10
STBY_REF
11
5130_STBY_LDO 12

DUMMY-R2

SC1500P50V3KX-GP

5130_SS_STBY1 6

5130_SS_STBY3

1D2V_S0_EN#

DCBATOUT_5130

1 R191
2
100KR2J-1-GP

5130_LL2 46,58

SCD1U50V3KX-GP

-1 0310

FB1
SS_STBY1
INV2
FB2
SS_STBY2
PWM_SEL
CT
GND
REF
STBY_VREF5
STBY_VREF3.3
STBY_LDO

LL2
OUT2_U
LH2
VIN
VREF3.3
VREF5
REG5V_IN
LDO_IN
LDO_CUR
LDO_GATE
LDO_OUT
INV_LDO

TPS5130

36
35
34
33
32
31
30
29
28
27
26
25

close to IC

5130_OUT2U

5130_REGIN

1 R538
2
0R0805-PAD

DCBATOUT_5130

5130_OUT2U 46

5130_5V_LDO
2 C375
SCD1U50V3KX-GP

5V_AUX_S5

1 R537

C377
C376
SC4D7U10V5ZY-3GP SC4D7U10V5ZY-3GP
78.47593.41L
78.47593.41L

0R3J-3-GP

SS_STBY3
FB3
INV3
PGOUT
PG_DELAY
TRIP3
VIN_SENSE3
LH3
OUT3_U
LL3
OUT3_D
OUTGND3

5130_CT

U41D

GAP-CLOSE
ZZ.CON2C.XX1

1D2V_S0_EN

1D2V_S0_EN#

39

C414
SC47P50V2JN-3GP

U70

5130_OUT3D
5130_LL3
5130_OUT3U
C387
5130_LH3 1
2

2N7002DW-7F-GP

R540
10KR2J-2-GP

S5PWR_ENABLE 22,43
5130_SS_STBY2

DY

1
2

84.27002.C3F

C413
SC4700P50V3KX-1GP

5130_PG_DELAY

TPS5130_1D8V_EN#
R546 2
100KR2J-1-GP

5130_OUT3D 46
5130_OUT3U 46
5130_LL3 46,58

SCD1U50V3KX-GP
5130_5V_LDO
1

5V_S0
1

TPS5130PTRG4-GP-U

5130_SS_STBY3
5130_FB3
5130_INV3

TSLCX14MTC-L-U

5V_AUX_S5

13
14
15
16
17
18
19
20
21
22
23
24

14

5130_3D3V_LDO

5V_S5

5130_3D3V_LDO

LDO SETTING
3D3V_AUX_S5

GAP-CLOSE
ZZ.CON2C.XX1
G24
1
2

PM_SLP_S5 5

5130_LL2

10

C381
5130_LH2 1
2

11

20,34 PM_SLP_S5#

5130_3D3V_LDO

14

U41E
TSLCX14MTC-L-U

SC1500P50V3KX-GP

2N7002DW-7F-GP

U69

INV1
FLT
LH1
OUT1_U
LL1
OUT1_D
OUTGND1
TRIP1
VIN_SENSE12
TRIP2
OUTGND2
OUT2_D

3D3V_AUX_S5

PWM_SEL
*

BAT54PT-GP
2
D13

H : Auto PWM/SKIP

2.2V(Min)~

L : PWM fixed (300KHz)

~0.3V(Max)

DCBATOUT_5130

5130_TRIP3

Wistron Corporation

DY

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

R552
0R0402-PAD

5130_REF

<Variant Name>
C400
SC2200P50V2KX-2GP

C415
SC1U10V3ZY-6GP

Title

TPS5130 1D2V/1D8V2D5V/ (1/2)

Size
A3

DY

5130_STBY_LDO

1 R551
2
0R2J-GP

Voltage

SB 0201

A
17,20,34,38,39,56 PM_SLP_S3#

Condition

(Power Team)

Document Number

Rev

Bolsena-E

Date: Thursday, October 13, 2005

Sheet

SA
45

of

58

TI TPS5130 for 2D5V, 1D2V, 1D8V

(1D2V=>CH1 , 1D8V=>CH2 , 2D5V =>CH3)

1D2V_PWR

1D2V_S0

G
S
S
S
4
3
2
1

1D2V_PWR

L32

GAP-CLOSE-PWR
G18
2

GAP-CLOSE-PWR
G21
2

GAP-CLOSE-PWR
G20
2

GAP-CLOSE-PWR
G22
2

GAP-CLOSE-PWR
G23
2

GAP-CLOSE-PWR
G19
2

5
6
7
8
D
D
D
D
G
S
S
S

TC12

KEMET, NTD:10.5 (Q1)

ESR=25mohm
Iripple=2.2A
7.3*4.3*1.9

4
3
2
1

SE220U4VDM-3GP

IND-3D3UH-57GP
U71
AO4422-1-GP

5130_OUT1U
5130_LL1

45 5130_OUT1D

1D2V
Iomax=5A
OCP>10A

5130_OUT1D

DCBATOUT_5130

2
GAP-CLOSE-PWR
G17
2

45 5130_OUT1U
45,58 5130_LL1

Imax=9.3A
Rdson=19.6~24mohm

G15

C846
SC10U35V0ZY-1GP

D
D
D
D

U72
AO4422-1-GP

C845
SCD1U25V3ZY-3GP

5
6
7
8

DCBATOUT_5130

GAP-CLOSE-PWR
C839
SCD1U25V3ZY-3GP

C840
SC10U35V0ZY-1GP

D
D
D
D

5
6
7
8

www.kythuatvitinh.com
U66
AO4422-1-GP

1D8V_PWR

1D8V_S5

G16

1D8V_PWR

L31

5130_OUT2U
5130_LL2

5
6
7
8

Imax=9.3A
Rdson=19.6~24mohm

GAP-CLOSE-PWR
G13
2

GAP-CLOSE-PWR
G10
2

GAP-CLOSE-PWR
G14
2

GAP-CLOSE-PWR
G12
2

GAP-CLOSE-PWR
G9
2

GAP-CLOSE-PWR
G11
2

TC11

B
45 5130_OUT2D

4
3
2
1

G
S
S
S

D
D
D
D

U68
AO4422-1-GP

SE220U4VDM-3GP

IND-4D7UH-88-GP

1D8V
Iomax=5A
OCP>10A

45 5130_OUT2U
45,58 5130_LL2

Imax=9.3A
Rdson=19.6~24mohm

4
3
2
1

G
S
S
S

5130_OUT2D

GAP-CLOSE-PWR

DCBATOUT_5130

2D5V_S3

1
2

C847
SC10U35V0ZY-1GP

G31
1

GAP-CLOSE-PWR
G29
2

2D5V_PWR

L33

GAP-CLOSE-PWR
G30
2

GAP-CLOSE-PWR
G26
2

GAP-CLOSE-PWR
G28
2

GAP-CLOSE-PWR
G27
2

GAP-CLOSE-PWR
G25
2

5
6
7
8
D
D
D
D
4
3
2
1

G
S
S
S

45 5130_OUT3D

5130_OUT3D

Imax=9.3A
Rdson=19.6~24mohm

SE220U4VDM-3GP

IND-4D7UH-88-GP
U75
AO4422-1-GP

5130_OUT3U
5130_LL3

2D5V
Iomax=9A
OCP>18A

TC13
2

G
S
S
S
4
3
2
1
45 5130_OUT3U
45,58 5130_LL3

Imax=9.3A
Rdson=19.6~24mohm

D
D
D
D

U74
AO4422-1-GP

5
6
7
8

2D5V_PWR
C849
SCD1U25V3ZY-3GP

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

GAP-CLOSE-PWR

(Power Team)

<Variant Name>

TPS5130 1D2V/1D8V2D5V/ (2/2)

Size
A3

Document Number

Date: Thursday, October 13, 2005

Rev
SA

Bolsena-E
Sheet

46

of

58

AC_IN Threshold 2.089V Max.

AC_IN > 2.089V --> AC DETECT
BT+
DCBATOUT

ACOK is 17.8V

2
MAX1909_PDL

D
D
D
D

8
7
6
5

GAP-CLOSE-PWR
GAP-CLOSE-PWR
AO4433-GP

R219

DUMMY-R3

C460

Icharge=3.5A

1
2

DHIV
PDL
LDO

1
C447

C439
SC10U35V0ZY-GP

MAX1909_DLOV

DLOV

21

DHI

23

MAX1909_DHI

DLO

20

MAX1909_DLO

PGND

19

5
6
7
8

CSSN

PDS
SRC
DCIN

R238
10KR2J-L2-GP

U20
AO4411-1-GP
84.04411.B37

R220
33R2J-2-GP

22
28
2

R232
R237
100KR2F-L1-GP
49K9R2F-L-GP

25

26
CSSP

1
1

3D3V_S5

MAX1909_PDS 27
AD+_TO_SYS 24
MAX1909_DC_IN 1

SC1U10V3KX-3GP

D
D
D
D

MAX1909_REF

S
S
S
G

U24

MAX1909_DHIV

MAX1909_LDO

Near MAX1909
2

1
2

MAX1909_LDO
C454
Pin
SCD1U25V3ZY-3GP

C453
SCD1U25V3ZY-3GP
MAX1909_CSSN

Icharge=3.2A

C461
SCD1U25V3ZY-3GP

DCBATOUT

SCD1U25V3ZY-3GP

MAX1909_CSSP

Q9
CH521S-30-GP-U
2N7002PT-U

C452
SCD1U25V3ZY-3GP

3S2P_I

AD+_TO_SYS

AD+

DY

C449
SCD1U25V3ZY-3GP

U22
S
S
S
G

Near MAX1909
Pin 21

CHG_PWR-3 58
CHG_PWR-2 58

C468
SC1U10V3KX-3GP

-1 0310

BT+

-1 0310
R221

L34

CCV
CCI
CCS

G32

GAP-CLOSE
2

R231
68KR2F-GP

R228
49K9R2F-L-GP

Q13
2N7002PT-U

PKPRES#

R227
100KR2J-1-GP
R226
63K4R3F-GP
64.63425.55L

Rx

90W ADAPTER

2
1

R555
150KR2J-GP

C854

ISOURCE_MAX = (0.075/Rx)*(VCLS/VREF)
TOTAL_POWER :
Adapter=90W,Total_Power=79.7W

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

R230
34,48 BAT_THERMAL

MAX1909_CLS

0R0402-PAD
C467

MAX1909_LDO

GAP-CLOSE
2

14
3

SC1U10V3KX-3GP

MAX1909_IINP

MAX1909_ACOK

13

TSLCX14MTC-L-U
D

U41F

12

AC_IN#

34

R557
100KR2J-1-GP

SC1U10V3KX-3GP

MAX1909_LDO
3D3V_AUX_S5

G40

C479
SCD1U16V3KX-3GP
C477
SCD1U16V3KX-3GP

20KR2F-L-GP

BAT+SENSE 48

From Battery Connector

R235

C462

SB 0127

MAX1909_CSIP
MAX1909_CSIN

V_REF :4.2235V (<500uA)

I Source = 4.5A ---> V (IINP) = 2.7V

I Source = 3.42A ---> V (IINP) = 2.05V

17
16
15

MAX8725ETI-GP-U

C480
SCD01U50V3KX-4GP
C478
SCD01U50V3KX-4GP

MAX1909_REF

GAP-CLOSE-PWR

CSIN
BATT
GND

C455

1
2

AD_IA

13
12
14

R239
10KR2J-2-GP
G41

MAX1909_CCV
MAX1909_CCI
MAX1909_CCS

PKPRES

REF

SB 0202

18

From Battery Connector

C448

GAP-CLOSE-PWR

2N7002PT-U
Q11

29

CSIP

3 2

1
G

PRE_CHG

34

PKPRES#

PGND

GAP-CLOSE-PWR

2N7002PT-U
Q12

4
3
2
1

1
G

DY

ACOK

G39

G38

MAX1909_ACOK

AO4422-1-GP
84.04422.B37
U21

CLS

IINP

MAX1909_CLS

SC10U25V0KX-3GP

ACIN

MAX1909_IINP

S
4 Cell
Icharge=1.4A

Pre charge=0.3A

D015R2512F-5-GP

SC10U25V6KX-1GP

IND-15UH-41-GP

S
S
S
G

34
4S1P_I
R234
2K94R2F-GPCELL is

2 CHG_PWR-3 1

5
6
7
8

2N7002PT-U
Q10

VCTL
ICTL
MODE

SC10U25V0KX-3GP

R236
73K2R2F-GP

R233
37K4R2F-1-GP

CHG_PWR-2

D
D
D
D

1
G

CHG_ON#

From KBC

MAX1909_VCTL 11
MAX1909_ICTL 10
MAX1909_MODE 7

www.kythuatvitinh.com
R224
100KR2J-1-GP

34

1
2

G57

D15

34

1
2
3
4

2
1

G58

34

R215
DUMMY-R3

4
3
2
1

3S

C440
SCD1U25V3ZY-3GP

R225
330KR2F-L-GP

C677

Close to
MAX1909 pin 24

R385
13K3R2F-L1-GP

3
34

For EMI

AO4433-GP

MAX1909_ACIN

Q14
2N7002PT-U
MAX1909_ICTL

D01R2512F-4-GP

V (MODE) >=2.8V = 4Cell

V (MODE) =1.8V = 3Cell

R399

1
1

R384
100KR2F-L1-GP

Rx
AD+_TO_SYS

1
2
3
4

SC1U25V5ZY-4GP

R250
49K9R2F-L-GP

U48
S
S
S
G

D
D
D
D

8
7
6
5

AD+
MAX1909_MODE

Title

-1 0302

CHARGER MAX8725
Size
Document Number
Custom

Rev

Bolsena-E

(Power Team)

Date: Thursday, October 13, 2005

SA
Sheet

47

of

58

Adaptor in to generate DCBATOUT

D29
K

AD+

DY
MMPZ5252BPT-GP

AD_JK
DC1

C7
SCD1U50V3ZY-GP

C666
SCD1U25V3ZY-3GP

R2
CHDTA124EUPT-GP

R380
100KR2J-1-GP
3

R1

OUT

22.10037.701
ME : 22.10037.701
2nd:22.10037.B02

CHDTC124EU-1GP
Q1
2

R2
GND

IN

AD_OFF

OUT

R1

34

8
7
6
5

Q2

DC-JACK75-U1-GP

D
D
D
D

ID = -10A/70deg
Rds(ON) = 24mohm
SO-8

1
2

2
5
6
MH1

GND

IN

R379
200KR2J-L1-GP

U45
S
S
S
G
AO4433-GP

C657
SCD1U50V3ZY-GP

AD+_2
C656
SCD1U50V3ZY-GP

1
2
3
4

R2
1KR2J-1-GP

www.kythuatvitinh.com
5V_AUX_S5

BATTERY CONNECTOR

BAV99PT-GP-U
D41

D42

DY

BAT1

BAV99PT-GP-U

DY

2
3
4
5
6
7

BTSMCLK
BTSMDATA

AMP-CON7-S-GP

SC10P50V2JN-1
2
1

SC10P50V2JN-1

20.80604.007
ME :20.80604.007
2nd:20.80269.007

L3# at 11.25V

1
2
3

HTH
GND
LTH

11.25V (Low)
VCC

RESET#/RESET

Turn Off
LOW3_OFF 22

DY

R212
15KR2F-GP
2

G680LT1F-GP

<Core Design>

Output type: DY
Open-Drain RESET#

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

DY
Title

R211
110KR2F-GP

AD/BATT CONN

Size
A3

Document Number

Rev

SA

Bolsena-E

Date: Thursday, October 13, 2005

A

EC66

1
C850
2

1
2

1
2

EC68

Turn On

U19
HTH

2
27R3F-GP

12.78V (High)

DY

C853

SC1KP50V2JN-2GP

DY

C852

SC1KP50V2JN-2GP

DY

C435
SCD1U10V2KX-LGP

R213
1MR2J-1-GP

HTH

1 R553

MAX1999_LDO5

DCBATOUT

C851

SCD1U50V3ZY-GP

Put close to battery connector

SCD1U50V3ZY-GP

Low3 Circuit :

R556 2
27R3F-GP

R554 2
0R0402-PAD

34
BAT_SCL_5
34
BAT_SDA_5
BT+ 34,47
BAT_THERMAL
47
BAT+SENSE

Sheet
E

48

of

58

U54A

PCIE TEST PADS

PCIE TEST POINTS MUST BE WITHIN 250 MILS
OF THE ASIC BALL WITH POSITIVE AND NEGATIVE
SIGNALS THE SAME DISTANCE

AJ31
AH31

PCIE_RX0P
PCIE_RX0N

PEG_RXP1
PEG_RXN1

AH30
AG30

PCIE_RX1P
PCIE_RX1N

PEG_RXP2
PEG_RXN2

AG32
AF32

PCIE_RX2P
PCIE_RX2N

PEG_RXP3
PEG_RXN3

AF31
AE31

PCIE_RX3P
PCIE_RX3N

PEG_RXP4
PEG_RXN4

AE30
AD30

PEG_RXP5
PEG_RXN5
PEG_RXP6
PEG_RXN6
TPAD28 TP108
TPAD28 TP90

PEG_RXP7
PEG_RXN7

1
1

AD32
AC32
AC31
AB31
AB30
AA30

PCIE_RX4P
PCIE_RX4N
PCIE_RX5P
PCIE_RX5N
PCIE_RX6P
PCIE_RX6N
PCIE_RX7P
PCIE_RX7N

P
C
I
E
X
P
R
E
S
S
I
N
T
E
R
F
A
C
E

PIN

STRAPS

PART 1 OF 7

PEG_RXP0
PEG_RXN0

DESCRIPTION OF RECOMMENDED SETTING

PCIE_TX0P
PCIE_TX0N

AK27
AJ27

C219 1
C220 1

2 SCD1U16V2ZY-2GP
2 SCD1U16V2ZY-2GP

PEG_TXP0
PEG_TXN0

STRAP_B_PTX_PWRS_ENB

GPIO0

PCIE_TX1P
PCIE_TX1N

AJ25
AH25

C200 1
C201 1

2 SCD1U16V2ZY-2GP
2 SCD1U16V2ZY-2GP

PEG_TXP1
PEG_TXN1

STRAP_B_PTX_DEEMPH_EN

GPIO1

PCIE_TX2P
PCIE_TX2N

AH28
AG28

C217 1
C218 1

2 SCD1U16V2ZY-2GP
2 SCD1U16V2ZY-2GP

PEG_TXP2
PEG_TXN2

PCIE_TX3P
PCIE_TX3N

AG27
AF27

C198 1
C199 1

2 SCD1U16V2ZY-2GP
2 SCD1U16V2ZY-2GP

PEG_TXP3
PEG_TXN3

PCIE_TX4P
PCIE_TX4N

AF25
AE25

C215 1
C216 1

2 SCD1U16V2ZY-2GP
2 SCD1U16V2ZY-2GP

PEG_TXP4
PEG_TXN4

PCIE_TX5P
PCIE_TX5N

AE28
AD28

PCIE_TX6P
PCIE_TX6N

AD27
AC27

PCIE_TX7P
PCIE_TX7N

AC25
AB25

PCIE_TX8P
PCIE_TX8N

AB28
AA28

C211 1
C212 1

2 SCD1U16V2ZY-2GP
2 SCD1U16V2ZY-2GP

PEG_TXP8
PEG_TXN8

ROMIDCFG(3:0)

GPIO[9,13:11]

MEMORY APERTURE SIZE

GPIO[13:11]

GPIO(3:2)

RSVD
REVERSE LANES

C213 1
C214 1

PEG_TXP5
PEG_TXN5

2 SCD1U16V2ZY-2GP
2 SCD1U16V2ZY-2GP

GPIO4

GPIO5

PCIE_RX8P
PCIE_RX8N

PEG_RXP9
PEG_RXN9

Y31
W31

PCIE_RX9P
PCIE_RX9N

PCIE_TX9P
PCIE_TX9N

AA27
Y27

C192 1
C193 1

2 SCD1U16V2ZY-2GP
2 SCD1U16V2ZY-2GP

PEG_TXP9
PEG_TXN9

PEG_RXP10
PEG_RXN10

W30
V30

PCIE_RX10P
PCIE_RX10N

PCIE_TX10P
PCIE_TX10N

Y25
W25

C209 1
C210 1

2 SCD1U16V2ZY-2GP
2 SCD1U16V2ZY-2GP

PEG_TXP10
PEG_TXN10

DO NOT INSTALL
10K RESISTORS

NO ATI FEATURE ENABLED

DO NOT INSTALL
10K RESISTOR
INSTALL
10K RESISTORS

NORMAL RANGE (M26X)

DO NOT INSTALL
10K RESISTORS

NO ATI FEATURE ENABLED (M52P,M54P,M56P)

NO DEBUG ACCESS (M26X)

GPIO8

FORCE_COMPLIANCE

AA32
Y32

GPIO6

DEBUG ACCESS

PEG_RXP8
PEG_RXN8

TBD

NO ATI FEATURE ENABLED (M52P,M54P,M56P)

COMMON MODE RANGE

PEG_TXP7
PEG_TXN7

2 SCD1U16V2ZY-2GP
2 SCD1U16V2ZY-2GP

TRANSMITTER DE-EMPHASIS ENABLE

DEPENDS ON PCIE CHIPSET BEING USED
FOR M26X,M5X
INSTALL WITH ATI RS480,RS400,RX480,
RC410,RS482 CHIPSETS
FOR M26X ONLY
DO NOT INSTALL WITH INTEL 915PM CHIPSET

DO NOT FORCE COMPLIANCE STATE QUICKLY (M26X)

RSVD
C194 1
C195 1

INSTALL
10K RESISTOR

NO DEBUG ACCESS (M52P,M54P,M56P)

STRAP_FORCE_COMPLIANCE
sets the desired PCIE PLL
bandwidth for M5x parts.

PEG_TXP6
PEG_TXN6

2 SCD1U16V2ZY-2GP
2 SCD1U16V2ZY-2GP

TRANSMITTER POWER SAVINGS ENABLE

- FULL TX OUTPUT SWING

NOT REVERSED LANE (M26X)

DEBUG ACCESS
C196 1
C197 1

RECOMMENDED

DO NOT INSTALL
10K RESISTORS

DON'T FORCE COMPLIANCE STATE(M52P,M54P,M56P)

MEM_TYPE

MEMID

1011

SERIAL FLASH ROM TYPE (M26X,M52P,M54P,M56P)

- SERIAL M25P10 ROM
IF NO ROM
GPIO11(M26X) AND GPIO12,13(M52,M54,M56)
SET MEMORY APERTURE SIZE
SEE M26X,M54X,M56X DATA BOOK FOR
MEMORY,FRAME BUFFER APERATURE SETTINGS

TBD

MEMORY TYPE AND SPEED SELECT

TBD

www.kythuatvitinh.com

12 PEG_RXP[15..0]

12 PEG_RXN[15..0]
12 PEG_TXP[15..0]

12 PEG_TXN[15..0]

PEG_RXP11
PEG_RXN11

V32
U32

PCIE_RX11P
PCIE_RX11N

PCIE_TX11P
PCIE_TX11N

W28
V28

C190 1
C191 1

2 SCD1U16V2ZY-2GP
2 SCD1U16V2ZY-2GP

PEG_TXP11
PEG_TXN11

PEG_RXP12
PEG_RXN12

U31
T31

PCIE_RX12P
PCIE_RX12N

PCIE_TX12P
PCIE_TX12N

V27
U27

C207 1
C208 1

2 SCD1U16V2ZY-2GP
2 SCD1U16V2ZY-2GP

PEG_TXP12
PEG_TXN12

PEG_RXP13
PEG_RXN13

T30
R30

PCIE_RX13P
PCIE_RX13N

PCIE_TX13P
PCIE_TX13N

U25
T25

C188 1
C189 1

2 SCD1U16V2ZY-2GP
2 SCD1U16V2ZY-2GP

PEG_TXP13
PEG_TXN13

2 SCD1U16V2ZY-2GP
2 SCD1U16V2ZY-2GP

PEG_TXP14
PEG_TXN14

2 SCD1U16V2ZY-2GP
2 SCD1U16V2ZY-2GP

PEG_TXP15
PEG_TXN15

PEG_RXP[15..0]

(3:0)

RSVD

PEG_RXN[15..0]
PEG_TXP[15..0]

PEG_TXN[15..0]

H2SYNC
V2SYNC
GENERICC

NO STRAP FUNCTION

RSVD

PCIE_TEST

NO STRAP FUNCTION

REFER TO PCI EXPRESS DESIGN GUIDE

FOR RECOMMENDED AC COUPLING CAPS
PLACEMENT ALONG THE TX INTERCONNECT

PEG_RXP14
PEG_RXN14

R32
P32

PCIE_RX14P
PCIE_RX14N

PCIE_TX14P
PCIE_TX14N

T28
R28

C205 1
C206 1

PEG_RXP15
PEG_RXN15

P31
N31

PCIE_RX15P
PCIE_RX15N

PCIE_TX15P
PCIE_TX15N

R27
P27

C186 1
C187 1

Clock
3
3

AL28
AK28

GFX_CLK
GFX_CLK#

R107
13,17,34,37 LPC_RST#

2
0R2J-GP

PCIE SIGNALS CONNECT TO ROOT COMPLEX

AG_RST#_1

AG24

PERSTB

PCIE_TEST

AA24

PCIE_TEST

AF24

PERSTB_MASK

PCIE_CALRN
PCIE_CALRP

AE24
AD24

PCIE_CALRN_VGA
PCIE_CALRP_VGA

R110 1
R111 1

2 2KR2F-3-GP
2 562R3F-GP

PCIE_CALI

AB24

PCIE_CALI_VGA

R108 1

2 1K47R3F-GP

R103
1

2PERSTB_MASK

Tie To VSS

10KR2F-2-GP
71.0M52P.00U

FOR M26X
PCIE_CALRN = 100R
PCIE CALRP = 150R
PCIE CALI = 10K
FOR M52P,M54P,M56P
PCIE_CALRN = 2K
PCIE CALRP = 562R
PCIE CALI = 1.47K

M52P:71.0M52P.A0U

23

22

1D2V_S0

21

20

MEM_ID0
MEM_ID2
MEM_ID1
MEM_ID3
1
1
0
0
0
1
1
0

0
1
1
0
1
1
0
0

1
1
1
1
0
0
0
0

0
0
0
0
0
0
0
0

MEM
64M
64M
128M
256M
128M
256M
128M
256M

SIZE
16M*16
16M*16
16M*16
32M*16
16M*16
32M*16
16M*16
32M*16

VENDOR CHIPs
Infineon
Hynix
Samsung
Samsung
Infineon
Infineon
Hynix
Hynix

DO NOT INSTALL
10K RESISTORS

NO STRAP (M26X)

ATI FEATURE NOT ENABLED (M52P,M54P,M56P)

NO STRAP (M26X)

Calibration

PCIE_REFCLKP
PCIE_REFCLKN

ATI FEATURE NOT ENABLED (M52P,M54P,M56P)

x2
x2
x4
x4
x4
x4
x4
x4

50
50
50
50
50
50
50
50

VGA_GPIO0
VGA_GPIO1
VGA_GPIO2
VGA_GPIO3
VGA_GPIO4
VGA_GPIO5
VGA_GPIO6
VGA_GPIO8

50
50
50
50

VGA_GPIO11
VGA_GPIO12
VGA_GPIO13
VGA_GPIO9

50
50
50
50
50
50
50

DY
DY
DY
DY
DY
DY
DY

R62
R412
R409
R411
R402
R403
R408
R58
R67

1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2

10KR2J-2-GP
10KR2J-2-GP
10KR2J-2-GP
10KR2J-2-GP
10KR2J-2-GP
10KR2J-2-GP
10KR2J-2-GP
10KR2J-2-GP
10KR2J-2-GP

R397 1
R59 1
1
1
for 256M
R65 1
R64 1
R63 1
R66 1
R88 1
R89 1
R100 1
R113 1

2
2
2
2

10KR2J-2-GP
10KR2J-2-GP
10KR2J-2-GP
10KR2J-2-GP

2
2
2
2
2
2
2
2

10KR2J-2-GP
10KR2J-2-GP
10KR2J-2-GP
10KR2J-2-GP
10KR2J-2-GP
10KR2J-2-GP
10KR2J-2-GP
10KR2J-2-GP

DY R56
DY R60
GPIO[9,13:11]=0010

MEM_ID3
MEM_ID2
MEM_ID1
MEM_ID0
DAC2_HSY
DAC2_VSY
GENERICC

When no ROM
GPIO[13:12]
GPIO[13:12]
GPIO[13:12]
GPIO[13:12]
GPIO[13:12]

DY
DY
DY
128V
DY
DY
DY
PCIE_TEST
DY

3D3V_S0

is attached, GPIO[9] is set to 0.

is used to select the frame buffer aperture size.
= 00: 128M frame buffer, same as ROM strap 00
= 01: 256M frame buffer, same as ROM strap 01
= 10: 64M frame buffer, same as ROM strap 10
= 11: reserved, same as ROM strap 11

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

ATI M5X-P PCIE 1/4

Size
A3

Document Number

Rev

SA

AG1

Date: Thursday, October 13, 2005

Sheet
1

49

of

58

U54B

Integrated TXCM
TXCP
TMDS

Center
Spread
+-0.5%

+-1.0%

SEL1 SEL0

3D3V_S0

+-1.5%

4
3

FOR M26X
CONNECT TO +1.8V OR VSS
TO DEFINE DVO SIGNAL LEVEL
FOR M52P,M54P,M56P
NOT CONNECTED

&

TX4M
TX4P

AK11
AJ11

M
U
L
T
I
M
E
D
I
A

TX5M
TX5P

AK12
AJ12
AM8

TPVSS

AL8

TXVDDR_1
TXVDDR_2
TXVDDR_3
TXVDDR_4

AJ6
AK6
AL6
AM6

TXVSSR_1
TXVSSR_2
TXVSSR_3
TXVSSR_4
TXVSSR_5

C697
SC1U6D3V2KX-GP

AJ7
AK7
AL7
AM7
AK8
AK24
AM24
AL24

HSYNC
VSYNC
GENERICA

AJ23
AJ22
AK22

VGA_TXVDDR
C695
C104
SC1U6D3V2KX-GP

R
G
B

DAC / CRT

R428
VGA_TPVDD
1

TPVDD

DUAL LINK IS
ONLY SUPPORTED ON M56P
DO NOT CONNECT TXM,P[3:5]
WITH M52P,M54P,M26X

Placed close to ASIC end.

2D5V_S0

FOR M26X TPVDD

CONNECT TO +1.8V
FOR M52P,M54P,M56P
CONNECT TO +2.5V

0R3J-3-GP

C103
SCD1U10V2KX-LGP

FOR M26X TXVDDR

CONNECT TO +1.8V
FOR M52P,M54P,M56P
CONNECT TO +2.5V

R425
1

2D5V_S0

0R3J-3-GP

DIS_R
DIS_G
DIS_B
DIS_HS 15
DIS_VS 15

1
0R3J-3-GP

C708
SC10U10V5KX-2GP

22 VGA_LOCAL_DN

VGA_PVDD
C126
SC1U6D3V2KX-GP
VGA_MPVDD

R79

XTALIN_M24
TPAD28 TP89

R99
1
2
1KR2J-1-GP

VOLTAGE DIVIDER 3.3V MEM SS

MODOUT TO 1.2V XTALIN/OUT

3D3V_S0

H2SYNC
V2SYNC

AF15
AG15

Y
C
COMP

AJ15
AJ13
AH15

R2SET

AK14

A2VDD_1
A2VDD_2

AM16
AL16

DPLUS

AH12

DMINUS

AJ14

PVDD

AH14

PVSS

XTALIN
XTALOUT

AG14

PLLTEST

VGA_TESTEN AG22

1 R61
2
10KR2J-2-GP

AC7

NC_A2VDDQ

AK13

VDD2DI

AJ16

VSS2DI

AJ17

Monitor
Interface

57
57
57

AE12
AF12

GENERICC

AE23

LPVSS

AE18

LVSSR_10
LVSSR_9
LVSSR_8

AF22
AF17
AF21

SC4D7U6D3V3KX-GP
2
1

R94
R91
R90

FOR M26X VDD1DI

CONNECT TO +1.8V
FOR M52P,M54P,M56P
CONNECT TO +2.5V

2D5V_S0

DIS_LUMA
DIS_CRMA
DIS_COMP

57
57
57

FOR M26X A2VDDQ

CONNECT TO +1.8V
FOR M52P,M54P,M56P
IT IS NO CONNECT

FOR M26X VDD2DI

CONNECT TO +1.8V
FOR M52P,M54P,M56P
CONNECT TO +2.5V

TPAD28
1 100KR2J-1-GP

For THERMAL SENSOR

DDC3DATA
DDC3CLK

2D5V_S0

C715
SCD1U10V2KX-LGP

For DVI

ROM

2D5V_S0

FOR M26X AVDD

CONNECT TO +1.8V
FOR M52P,M54P,M56P
CONNECT TO +2.5V

DAC2 CAN BE TV SIGNALS OR SECONDARY CRT

SIGNALS AS CONTROLLED BY AN INTERNAL MUX

SC4D7U6D3V3KX-GP 1
2
C716
R449 0R3J-3-GP

TP9

2 0R3J-3-GP
R447

R439
C710 1
2 0R3J-3-GP
SC1U6D3V2KX-GP

VGA_VDD2DI
C125

AH22
AH23

ROMCSb

TPAD28 TP88

DDC1DATA
DDC1CLK
DDC2DATA
DDC2CLK

C713

VGA_A2VDDQ 1

1
R80 2

Test

C711

AF11

TESTEN

LVDS PLL
and I/O
GND

VGA_A2VDD

C718

2 715R2F-GP

HPD1

AH13
AG13

External
SSC

2D5V_S0

AM17
AL17
AL14

A2VSSQ

DAC2_HSY 49
DAC2_VSY 49

SC1U6D3V2KX-GP

LVSSR_1
LVSSR_2 LVDS PLL
LVSSR_3 and I/O
LVSSR_4 GND
LVSSR_5
LVSSR_6
LVSSR_7

C714
SC1U6D3V2KX-GP

VGA_TV_RSET R438 1

A2VSSN_1
A2VSSN_2

PLL &
XTAL

MPVDD
MPVSS

AL26
1AM26

AK17
AJ19
AF18
AH17
AG17
AG19
AH19
4

VGA_VDD1DI

Thermal
Diode

2
150R2F-1-GP 2
150R2F-1-GP 2
150R2F-1-GP

G2
B2

R2
DAC2 (TV/CRT2)

AK15
AM15
AL15

2 0R3J-3-GP

AL23

DY

adjust SWING at 1.2v

AM23

VSS1DI

VREFG

AG12

A6
A5

1
2

C101
C102
SC1U6D3V2KX-GP
SCD1U10V2KX-LGP

1
2
0R3J-3-GP

FOR M26X MPVDD

CONNECT TO +1.8V
FOR M52P,M54P,M56P
CONNECT TO VDDC

AC8

VDD1DI

C720 R455 1
SC1U6D3V2KX-GP

150R2F-1-GP
2
1
150R2F-1-GP
2
1
150R2F-1-GP
2
1

22 VGA_LOCAL_DP

R437

VGA_CORE_S0

VGA_VREF

AVSSQ
AVSSN_1
AVSSN_2

AK23
AK25
AJ24

VGA_AVDD

PLACE VREF DIVIDER AND CAP CLOSE TO ASIC

56 GPIO_PWRCNTL

AL25
AM25

C107

FOR M26X PVDD

CONNECT TO +1.8V
FOR M52P,M54P,M56P
CONNECT TO +2.5V
2D5V_S0

VGA_GPIO11
VGA_GPIO12
VGA_GPIO13

GPIO_0
General
GPIO_1
Purpose
GPIO_2
I/O
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7_BLON
GPIO_8
GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14
GPIO_15
GPIO_16
GPIO_17
NC_AB6

2 499R2F-1-GP

RSET

AVDD_1
AVDD_2

SCD1U10V2KX-LGP

R78
499R2F-1-GP

49
49
49
SCD1U10V2KX-LGP

AD4
AD2
AD1
AD3
AC1
AC2
AC3
1
AB2
AC6
AC5
TPAD30
TP7
AC4
AB3
AB4
AB5
0R2J-GP
AD5
VGA
POW_SW
R82
1
2
AB8
VGA_GPIO16 AA8
VGA_ALERT#
AB7
AB6

2 1KR2F-3-GP

VGA_CRT_RSET R441 1

TPAD28 TP82

VGA_GPIO8
VGA_GPIO9

VGA_ALERT#

VGA_GPIO0
VGA_GPIO1
VGA_GPIO2
VGA_GPIO3
VGA_GPIO4
VGA_GPIO5
VGA_GPIO6

R77
49
499R2F-1-GP
49

MEM_ID3
MEM_ID2
MEM_ID1
MEM_ID0

VGA_GENERICB R104 1

49
49
49
49
49
49
49

3D3V_S0

R57
10KR2J-2-GP

49
49
BE49
49

AF23

AL22

1
2

13,16 EDID_DAT
13,16 EDID_CLK

TPAD30
TP84
TPAD30
TP83
EDID_DAT
EDID_CLK

GENERICB

RN11
SRN4K7J-8-GP

No Spread

SCD1U10V2KX-LGP

AK9
AJ9

ANY UNUSED GPIO CAN OPTIONALLY

MEMORY TYPE CONFIG STRAPS

DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
DVPCLK
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23

TX3M
TX3P

www.kythuatvitinh.com
H

ANY UNUSED GPIO CAN OPTIONALLY BE

PANEL TYPE CONFIG STRAPS

3D3V_S0

AF2
AF1
AF3
AG1
AG2
AG3
AH2
AH3
AJ2
AJ1
AK2
AK1
AK3
AL2
AL3
AM3
AE6
AF4
AF5
AG4
AJ3
AH4
AJ4
AG5
AH5
AF6
AE7
AG6

AL12
AM12

1
R4521
R4451
R446

Modulation Rate

NC_DVOVMODE_0
NC_DVOVMODE_1

TX2M
TX2P

SCD1U10V2KX-LGP

R423 1KR2J-1-GP

DVPCNTL,DVPDATA[23..0]
ARE CONFIGURED FOR
+3.3V SIGNALING MODE
ON THIS DESIGN

AK4
AL4

AL11
AM11

R31
0R2J-GP

R44
105R3F-2-GP

TX1M
TX1P

V
I
D
E
O

VIP Host/External TMDS

adjust SWING
at 1.2v

AK10
AL10

SS_SEL

TX0M
TX0P

DY

AL9
AM9

XTALIN_M24

R51
0R2J-GP

VGA_GPIO16

TC2

GPIO_34
GPIO_33
GPIO_32
GPIO_31
GPIO_30
GPIO_29
GPIO_28
GPIO_27
GPIO_26
GPIO_25
GPIO_24
GPIO_23
GPIO_22
GPIO_21
GPIO_20
GPIO_19
GPIO_18

Expand GPIO

2
2 1

R50
180R2F-1-GP

MK1726-08SLF-GPU

R30
0R2J-GP

DY

SS_PD
MK1726_REF
1

C64
3D3V_S0
SC27P50V2JN-2-GP

DY

8
7
6
5

X2
VDD
PD#
REFCLK

MK1726_XO

X1/CLK
GND
SO
SSCLK

AG8
AH7
AG9
AH8
AJ8
AH9
AG10
AF10
AH6
AF8
AF7
AE9
AE10
AG7
AF9
AF13
AE13

SC22U6D3V5MX-2GP

1
2
1
2
3
4

SCD1U25V3ZY-3GP
2

X1
XTAL-27MHZ-31-GP

1MR2J-1-GP

1
1
2

C71

U5

R39

SC27P50V2JN-2-GP
2
12

C36

3D3V_S0

[USE ICS MK1726-08]

MK1726_XI

PART 2 OF 7

DIS_CRT_DDC_D 15
DIS_CRT_DDC_C 15

For CRT

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

GENERICC 49

FOR M26X GENERICC

NO CONNECT OR
EXT SPREAD SPECTRUM INPUT
FOR M52P,M54P,M56P
IT IS GPIO
2

Title

ATI M5X-P IO 2/4

Size
A3

Document Number

Rev

SA

Bolsena-E

Date: Thursday, October 13, 2005

Sheet
1

50

of

58

DQA_0
DQA_1
DQA_2
DQA_3
DQA_4
DQA_5
DQA_6
DQA_7
DQA_8
DQA_9
DQA_10
DQA_11
DQA_12
DQA_13
DQA_14
DQA_15
DQA_16
DQA_17
DQA_18
DQA_19
DQA_20
DQA_21
DQA_22
DQA_23
DQA_24
DQA_25
DQA_26
DQA_27
DQA_28
DQA_29
DQA_30
DQA_31
DQA_32
DQA_33
DQA_34
DQA_35
DQA_36
DQA_37
DQA_38
DQA_39
DQA_40
DQA_41
DQA_42
DQA_43
DQA_44
DQA_45
DQA_46
DQA_47
DQA_48
DQA_49
DQA_50
DQA_51
DQA_52
DQA_53
DQA_54
DQA_55
DQA_56
DQA_57
DQA_58
DQA_59
DQA_60
DQA_61
DQA_62
DQA_63

C31
C30

MVREFD_0
MVREFS_0

read strobe

M31
M30
L31
L30
H30
G31
G30
F31
M27
M29
L28
L27
J27
H29
G29
G27
M26
L26
M25
L25
J25
G28
H27
H26
F26
G26
H25
H24
H23
H22
J23
J22
E23
D22
D23
E22
E20
F20
D19
D18
B19
B18
C17
B17
C14
B14
C13
B13
D17
E18
E17
F17
E15
E14
F14
D13
H18
H17
G18
G17
G15
G14
H14
J14

MEMORY INTERFACE A

MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8
MAA_9
MAA_10
MAA_11
MAA_12
MAA_13
MAA_14
MAA_15

D26
F28
D28
D25
E24
E26
D27
F25
C26
B26
D29
B27
E27
E29
B25
C25

DQMAb_0
DQMAb_1
DQMAb_2
DQMAb_3
DQMAb_4
DQMAb_5
DQMAb_6
DQMAb_7

H31
J29
J26
G23
E21
B15
D14
J17

QSA_0
QSA_1
QSA_2
QSA_3
QSA_4
QSA_5
QSA_6
QSA_7

J31
K29
K25
F23
D20
B16
D16
H15

QSA_0B
QSA_1B
QSA_2B
QSA_3B
QSA_4B
QSA_5B
QSA_6B
QSA_7B

K31
K28
K26
G24
D21
C16
D15
J15

ODTA
ODTA1

F29
D24

U54D

Ch-A
FOR M52P,M54P,M26X
PIN B25 IS MA12 (BA0)
PIN C25 IS MA13 (BA1)
PIN E29 IS MA15 (BA2)
PIN E27 IS MA14
FOR M56P
PIN B25 IS MA14 (BA0)
PIN C25 IS MA15 (BA1)
PIN E29 IS MA13 (BA2)
PIN E27 IS MA12

Part 3 of 7

Ch-B
FOR M52P,M54P,M26X
PIN H2 IS MAB12 (BA0)
PIN H3 IS MAB13 (BA1)
PIN D5 IS MAB15 (BA2)
PIN F5 IS MAB14
FOR M56P
PIN H2 IS MA14 (BA0)
PIN H3 IS MA15 (BA1)
PIN D5 IS MA13 (BA2)
PIN F5 IS MAB12

Part 4 of 7
MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63

B12
C12
B11
C11
C8
B7
C7
B6
F12
D12
E11
F11
F9
D8
D7
F7
G12
G11
H12
H11
H9
E7
F8
G8
G6
G7
H8
J8
K8
L8
K9
L9
K5
L4
K4
L5
N5
N6
P4
R4
P2
R2
T3
T2
W3
W2
Y3
Y2
T4
R5
T5
T6
V5
W5
W6
Y4
R8
T8
R7
T7
V7
W7
W8
W9

DQB_0
DQB_1
DQB_2
DQB_3
DQB_4
DQB_5
DQB_6
DQB_7
DQB_8
DQB_9
DQB_10
DQB_11
DQB_12
DQB_13
DQB_14
DQB_15
DQB_16
DQB_17
DQB_18
DQB_19
DQB_20
DQB_21
DQB_22
DQB_23
DQB_24
DQB_25
DQB_26
DQB_27
DQB_28
DQB_29
DQB_30
DQB_31
DQB_32
DQB_33
DQB_34
DQB_35
DQB_36
DQB_37
DQB_38
DQB_39
DQB_40
DQB_41
DQB_42
DQB_43
DQB_44
DQB_45
DQB_46
DQB_47
DQB_48
DQB_49
DQB_50
DQB_51
DQB_52
DQB_53
DQB_54
DQB_55
DQB_56
DQB_57
DQB_58
DQB_59
DQB_60
DQB_61
DQB_62
DQB_63

read strobe

U54C

MEMORY INTERFACE B

MAB_0
MAB_1
MAB_2
MAB_3
MAB_4
MAB_5
MAB_6
MAB_7
MAB_8
MAB_9
MAB_10
MAB_11
MAB_12
MAB_13
MAB_14
MAB_15

G4
E6
E4
H4
J5
G5
F4
H6
G3
G2
D4
F2
F5
D5
H2
H3

DQMBb_0
DQMBb_1
DQMBb_2
DQMBb_3
DQMBb_4
DQMBb_5
DQMBb_6
DQMBb_7

B8
D9
G9
K7
M5
V2
W4
T9

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11

MAB12_14 54,55
TP8 TPAD28

B_BA0
B_BA1

54,55
54,55

DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7

RDQSB0
RDQSB1
RDQSB2
RDQSB3
RDQSB4
RDQSB5
RDQSB6
RDQSB7

QSB_0
QSB_1
QSB_2
QSB_3
QSB_4
QSB_5
QSB_6
QSB_7

B9
D10
H10
K6
N4
U2
U4
V8

QSB_0B
QSB_1B
QSB_2B
QSB_3B
QSB_4B
QSB_5B
QSB_6B
QSB_7B

B10
E10
G10
J7
M4
U3
V4
V9

WDQSB0
WDQSB1
WDQSB2
WDQSB3
WDQSB4
WDQSB5
WDQSB6
WDQSB7

D6
J4

ODTB0
ODTB1

54
54,55

RASB0#
RASB1#

54
54,55

CASB0#
CASB1#

54
54,55

WEB0#
WEB1#

54

CSB0_0#

54,55

CSB1_0#

54
54,55

CKEB0
CKEB1

54
54

CLKB0
CLKB0#

55
55

CLKB1
CLKB1#

RASB0#
RASB1#
CASB0#
CASB1#
WEB0#
WEB1#
CSB0_0#
CSB1_0#
C

CKEB0
CKEB1

D31
E31

CKEA0

B30

RASA0b

B28

CASA0b

C29

WEA0b

B31

CSA0b_0
CSA0b_1

B29
C28

1D8V_S0

CLKA0
CLKA0b

R71

ODTB
ODTB1

CLKB0
CLKB0b

B4
B5

CLKB0
CLKB0#

CKEB0

C2

CKEB0

RASB0b

E2

RASB0#

CASB0b

D3

CASB0#

WEB0b

B2

WEB0#

CSB0b_0
CSB0b_1

D2
E3

CSB0_0#
CSB0_1#

CLKB1
CLKB1b

N2
P3

CLKB1
CLKB1#
CKEB1

write strobe

CLKB0
CLKB0#
CLKB1
CLKB1#

RDQSB[7..0]

54,55 RDQSB[7..0]

ODTB0 54
ODTB1 54,55

DQMB#[7..0]

54,55 DQMB#[7..0]

MDB[63..0]

54,55 MDB[63..0]

MAB[11..0]

54,55 MAB[11..0]

WDQSB[7..0]

54,55 WDQSB[7..0]

TP81 TPAD28

TP4

WEA1b

B21

CSA1b_0
CSA1b_1

B23
C23

B22

MEM_RST

100R2F-L1-GP-U

1D8V_S0

CASA1b

R72

B24

SCD1U10V2KX-LGP

CKEA1
RASA1b

MVREFD1
MVREFS1

C90

B3
C3

MVREFD_1
MVREFS_1

CKEB1

L3

AA3

DRAM_RST

RASB1b

J2

RASB1#

AA5

TEST_MCLK

CASB1b

L2

CASB1#

AA2

TEST_YCLK

WEB1b

M2

WEB1#

AA7

MEMTEST

CSB1b_0
CSB1b_1

K2
K3

CSB1_0#
CSB1_1#

TPAD28

8
7
6
5

B20
C19
C22

CLKA1
CLKA1b

100R2F-L1-GP-U

write strobe

www.kythuatvitinh.com
For GDDR2

R49

RN10
SRN4K7J-6-GP

PLACE MVREF DIVIDERS

AND CAPS CLOSE TO ASIC

R55
2

1
2
3
4

C75
SCD1U10V2KX-LGP

100R2F-L1-GP-U

<Variant Name>

100R2F-L1-GP-U

Wistron Corporation

PLACE MVREF DIVIDERS

AND CAPS CLOSE TO ASIC

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title

ATI M5X-P MEM 3/4

Size
A3

Document Number

Rev

SA

Bolsena-E

Date: Thursday, October 13, 2005

Sheet
1

51

of

58

R106

0R5J-5-GP

U54E

1
2

1
2

SC1U6D3V2KX-GP

R460
1
SC1U6D3V2KX-GP

C118

C151

C93

C148

1
2

C114

C121

VGA_CORE_S0

C120

C138

FOR M26X VDD25

CONNECT TO +1.5V
FOR M52P,M54P,M56P
CONNECT TO +2.5V

R75
C123 1
2
0R3J-3-GP

C124
SCD1U10V2KX-LGP

C712
SC4D7U6D3V3KX-GP

2
0R5J-5-GP

C168

C130

VGA_VDDPLL

R112

0R5J-5-GP

1
2
1
2
1
2

SC1U6D3V2ZY-GP
2
1

SC1U6D3V2KX-GP
1
2
1

SC1U6D3V2KX-GP

1
2

SC1KP16V2KX-GP

SC1U6D3V2KX-GP
2
1

1
2

1
2

C122

C136

VGA_VDD25

C176

C152

1 SC1U6D3V2KX-GP
2
1
2

W10
T14
W17
P16
T23
K14
U19

C137

VDDCI_1
VDDCI_2
VDDCI_3
VDDCI_4
VDDCI_5
VDDCI_6
VDDCI_7

C115

AC15

C731

VDDPLL

C730

VDDR3_1
VDDR3_2
VDDR3_3
VDDR3_4
VDDR3_5
VDDR3_6
VDDR3_7
VDDR3_8

AC13
AC16
AC18

C111
1

VDD25_1
VDD25_2
VDD25_3

C732

PCI-Express

1
2

SCD01U25V2KX-3GP

AC11
AC12
P14
U15
W14
W15
R17
R15
V15
V16
T16
U16
T17
U17
V14
R18
T18
V18
P18
P19
R19
W19
AD11

I/O Internal

2
1
SC10U10V5KX-2GP
SCD01U25V2KX-3GP
2
1

SCD01U25V2KX-3GP

1
2
1
2

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDDC_23

VGA_PCIE_VDDR12_2

C166

SCD1U10V2KX-LGP

C106

AL31
AM31
AM30
AL32
AL30
AM28
AL29
AM29
AM27

C167

SCD1U10V2KX-LGP

AB9
AB10
AA9
AC19
AD18
AC20
AD19
AD20

P
O
W
E
R

PCIE_VDDR_12_1
PCIE_VDDR_12_2
PCIE_VDDR_12_3
PCIE_VDDR_12_4
PCIE_VDDR_12_5
PCIE_VDDR_12_6
PCIE_VDDR_12_7
PCIE_VDDR_12_8
PCIE_VDDR_12_9

C164

1D2V_S0

FOR M26X PCIE_VDDR12

CONNECT TO +1.8V
FOR M52P,M54P,M56P
CONNECT TO +1.2V

SCD1U10V2KX-LGP
SCD1U10V2KX-LGP

SCD01U25V2KX-3GP SCD01U25V2KX-3GP
SC1U6D3V2KX-GP
2
1
2
1
2
1

TC21
ST100U6D3VDM-5

C175

SCD1U10V2KX-LGP
SCD1U10V2KX-LGP

2
1
2
1
SC1U6D3V2KX-GP
SCD01U25V2KX-3GP SCD01U25V2KX-3GP
2
1

C112

VGA_PCIE_VDDR12_1

SCD1U10V2KX-LGP
SCD1U10V2KX-LGP

C117

N29
N28
N27
N26
N25

SCD1U10V2KX-LGP
SCD1U10V2KX-LGP

VGA_VDDR3

C76

SC1U6D3V2KX-GP
2
1
1
2
1
2

C739

C163

PCIE_VDDR_12_10
PCIE_VDDR_12_11
PCIE_VDDR_12_12
PCIE_VDDR_12_13
PCIE_VDDR_12_14

SCD1U10V2KX-LGP
SCD1U10V2KX-LGP

SCD01U25V2KX-3GP SCD01U25V2KX-3GP

C77

C116

C78

1
C147
SCD1U10V2KX-LGP

C150
SC1KP16V2KX-GP

SCD1U10V2KX-LGP
SCD1U10V2KX-LGP

K23

C709

C105

PCIE_PVDD_12_1
PCIE_PVDD_12_2
PCIE_PVDD_12_3
PCIE_PVDD_12_4

V23
N23
P23
U23

SCD1U10V2KX-LGP

VSS_159

C135

C109

Memory I/O

2D5V_S0

R442
1
2
0R3J-3-GP

FOR M26X VDDPLL

CONNECT TO VDDC
FOR M52P,M54P,M56P
CONNECT TO +1.2V

1D2V_S0

C723

1
2

1
2
1
2

VGA_CORE_S0

2D5V_S0

FOR M26X LPVDD

CONNECT TO +1.8V
FOR M52P,M54P,M56P
CONNECT TO +2.5V

R98

C141

1
2

1
2
0R3J-3-GP

0R5J-5-GP

C153

2D5V_S0

FOR M26X LVDDR PINS

AE20,AF20,AF19
CONNECT TO +1.8V
FOR M52P,M54P,M56P
CONNECT TO +2.5V

2D5V_S0

FOR M26X LVDDR PINS

AC21,AC22,AD21,AD22,AE21,AE22
CONNECT TO +2.8V
FOR M52P,M54P,M56P
CONNECT TO +2.5V

0R5J-5-GP

R109

0R5J-5-GP

VGA_VDDRH1

1
2

C174

SC1U6D3V2KX-GP
R422
1
2
0R3J-3-GP

VGA_LVDDRL1

VSSRH0
VSSRH1

LVDDR/VDDL1_1
LVDDR/VDDL1_2
LVDDR/VDDL1_3
LVDDR/VDDL2_1
LVDDR/VDDL2_2
LVDDR/VDDL2_3

AC21
AC22
AD22
AE21
AD21
AE22

C133

A28
E1

VGA_LVDDRL0
C134

VGA_VDDRH0

VDDRH0
VDDRH1

AF20
AE20
AF19

R101

C132

SCD1U10V2KX-LGP

R454
1
2
0R3J-3-GP

A27
F1

LVDDR/VDDL0_1
LVDDR/VDDL0_2
LVDDR/VDDL0_3

SC1U6D3V2ZY-GP
2
1

SC1U6D3V2ZY-GP

VDDR4 AND VDDR5

IN M26X CAN BE 1.8V OR 3.3V
DEPENDING ON M26X DVOMODE
OR M52P,M54P,M56P REGISTER
CONFIGURATION
1D8V_S0

VDDR5_1
VDDR5_2
VDDR5_3
VDDR5_4

SC1U6D3V2KX-GP

AE2
AE3
AE4
AE5

AE19

SC1U6D3V2ZY-GP
2
1

1
2

VGA_VDDR5

C91

VGA_LPVDD

LPVDD/VDDL0

SCD1U10V2KX-LGP

SC1U6D3V2ZY-GP
1
2
1

C85

VDDR4_1
VDDR4_2
VDDR4_3
VDDR4_4

LVDS PLL, I/O

R76
1
2
0R3J-3-GP

AJ5
AM5
AL5
AK5

SCD1U10V2KX-LGP

VGA_VDDR4
C693
SC1U6D3V2KX-GP

C92

SCD1U10V2KX-LGP

C689

SC1U6D3V2KX-GP
2 R453
1
0R3J-3-GP

PART 7 OF 7
Forward

3D3V_S0

R96

VGA_CORE_S0

M56P

2
0R2J-GP
R95
2

VGA_BBN

VGA_BBP

0R2J-GP

Q23
2N7002PT-U
1
G

VARY_BL
DIGON
GENERICD

AD12
AE11
AD23

TXCLK_UP
TXCLK_UN
TXOUT_U3P
TXOUT_U3N
TXOUT_U2P
TXOUT_U2N
TXOUT_U1P
TXOUT_U1N
TXOUT_U0P
TXOUT_U0N

AJ21
AK21
AH21
AG21
AG20
AH20
AK20
AJ20
AG18
AH18

ATI_TXBCLK+ 57
ATI_TXBCLK- 57

TXOUT_L0N
TXOUT_L0P
TXOUT_L1N
TXOUT_L1P
TXOUT_L2N
TXOUT_L2P
TXOUT_L3N
TXOUT_L3P
TXCLK_LN
TXCLK_LP

AK19
AL19
AL20
AM20
AL21
AM21
AK18
AJ18
AL18
AM18

ATI_TXAOUT0- 57
ATI_TXAOUT0+ 57
ATI_TXAOUT1- 57
ATI_TXAOUT1+ 57
ATI_TXAOUT2- 57
ATI_TXAOUT2+ 57

BL_ON 13,34
ATI_LCDVDD_ON 57
1

M56P

R448
100KR2J-1-GP

PWROK#

Control and External SSC

Compatibility

BLON CAN ALSO BE A PWM OUTPUT

FOR BRIGHTNESS CONTROL

U54G

Q22
SI2301BDS-T1-GP

BACK BIASING APPLIES TO M56P ONLY

IF BACK BIAS NOT USED ON M56,CONNECT
BBN PINS TO VSS AND BBP PINS TO VDDC
BBN,BBP PINS ARE NO CONNECT FOR
M26X,M54P,M52P

Y23
K15
R10
AC17
AC14
M23
V10
K18

BBN_4
BBN_3
BBN_2
BBN_1
BBP_4
BBP_3
BBP_2
BBP_1

L10
K22
AA10

VDD25_4
VDD25_5
VDD25_6

Only used in
dual-channel
LVDS mode.
LVDS channel

This channel is
used as the
transmitting
channel in single
channel LVDS mode.

FOR M26X GENERICD

NO CONNECT OR
EXT SPREAD SPECTRUM OUTPUT
FOR M52P,M54P
IT IS A GPIO
FOR M56P
IT IS A BACK BIAS REGULATOR CONTROL

R81
10KR2J-2-GP
2

DY

CORE GND

1
2
0R3J-3-GP

SCD1U10V2KX-LGP
C119 C131
C149
SCD1U10V2KX-LGP

SCD1U10V2KX-LGP

ATI_TXBOUT2+ 57
ATI_TXBOUT2- 57
ATI_TXBOUT1+ 57
ATI_TXBOUT1- 57
ATI_TXBOUT0+ 57
ATI_TXBOUT0- 57

ATI_TXACLK- 57
ATI_TXACLK+ 57

R461
NB_PWRGD 13,39

1
2

C108

C146
SCD1U10V2KX-LGP

C113

<Variant Name>
2D5V_S0

VCORE_EN 39,41

SCD1U10V2KX-LGP

1
2
0R2J-GP
R456 2
1
0R2J-GP DY

SC1U6D3V2ZY-GP
2
1

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37

R424

R97

VGA_VDDCI
C110
SCD1U10V2KX-LGP

PCIE_PVSS

C139

www.kythuatvitinh.com
C140

SC1U6D3V2KX-GP
SC1U6D3V2KX-GP

I/0

B1
H1
L1
P1
U1
Y1
AD7
AE8
AL1
A2
AM2
AD10
E8
H5
K10
M8
T10
E12
AC9
AF14
AD8
C5
F10
J3
L6
M6
P6
AA4
AG11
V3
AG16
R3
C6
C9
F6
H7
J6

C729

VDDR1_1
VDDR1_2
VDDR1_3
VDDR1_4
VDDR1_5
VDDR1_6
VDDR1_7
VDDR1_8
VDDR1_9
VDDR1_10
VDDR1_11
VDDR1_12
VDDR1_13
VDDR1_14
VDDR1_15
VDDR1_16
VDDR1_17
VDDR1_18
VDDR1_20
VDDR1_21
VDDR1_22
VDDR1_23
VDDR1_24
VDDR1_25
VDDR1_26
VDDR1_27
VDDR1_28
VDDR1_29
VDDR1_30
VDDR1_31
VDDR1_32
VDDR1_33
VDDR1_34
VDDR1_35
VDDR1_36
VDDR1_37
VDDR1_38
VDDR1_39
VDDR1_40
VDDR1_41
VDDR1_42
VDDR1_43
VDDR1_45
VDDR1_46

Memory
I/O
Clock

VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158

SCD1U10V2KX-LGP

W23

PCI-Express GND

PCIE_VSS_1
PCIE_VSS_2
PCIE_VSS_3
PCIE_VSS_4
PCIE_VSS_5
PCIE_VSS_6
PCIE_VSS_7
PCIE_VSS_8
PCIE_VSS_9
PCIE_VSS_10
PCIE_VSS_11
PCIE_VSS_12
PCIE_VSS_13
PCIE_VSS_14
PCIE_VSS_15
PCIE_VSS_16
PCIE_VSS_17
PCIE_VSS_18
PCIE_VSS_19
PCIE_VSS_20
PCIE_VSS_21
PCIE_VSS_22
PCIE_VSS_23
PCIE_VSS_24
PCIE_VSS_25
PCIE_VSS_26
PCIE_VSS_27
PCIE_VSS_28
PCIE_VSS_29
PCIE_VSS_30
PCIE_VSS_31
PCIE_VSS_32
PCIE_VSS_33
PCIE_VSS_34
PCIE_VSS_35
PCIE_VSS_36
PCIE_VSS_37
PCIE_VSS_38
PCIE_VSS_39
PCIE_VSS_40
PCIE_VSS_41
PCIE_VSS_42
PCIE_VSS_43
PCIE_VSS_44
PCIE_VSS_45
PCIE_VSS_46
PCIE_VSS_47
PCIE_VSS_48
PCIE_VSS_49
PCIE_VSS_50
PCIE_VSS_51
PCIE_VSS_52
PCIE_VSS_53
PCIE_VSS_54
PCIE_VSS_55
PCIE_VSS_56
PCIE_VSS_57
PCIE_VSS_58
PCIE_VSS_59
PCIE_VSS_60
PCIE_VSS_61
PCIE_VSS_62
PCIE_VSS_63
PCIE_VSS_64
PCIE_VSS_65
PCIE_VSS_66
PCIE_VSS_67
PCIE_VSS_68
PCIE_VSS_69
PCIE_VSS_70
PCIE_VSS_71
PCIE_VSS_72
PCIE_VSS_73
PCIE_VSS_74
PCIE_VSS_75
PCIE_VSS_76
PCIE_VSS_77
PCIE_VSS_78
PCIE_VSS_79
PCIE_VSS_80
PCIE_VSS_81
PCIE_VSS_82

AD16
AA6
P7
P5
M3
M9
L7
M7
AD17
AH11
A8
U7
C10
E9
F3
J9
N7
N3
Y5
AM13
AC10
Y6
U6
E5
AL13
A11
U8
U9
U10
R6
AD6
V6
AD14
AD13
D11
J12
K12
A13
F13
E13
F15
K16
J21
H16
T15
V17
C15
C4
U14
P15
A16
E16
G13
G16
P17
R16
R14
W16
C18
F16
W18
U18
AE16
AE17
A19
H32
F19
G19
N8
Y7
T19
V19
G21
C21
F21
AE14
AK16
U5
F22
F18
K30
C24
F24
M24
A25
D30
E25
G25
G20
G22
F27
E28
H21
C27
E32
H28
J30
K17
K27
M32
A22
C20
E19
H20
J24
M28
J28
J16
F30
L29
A31
B32
E30
AE15
AG23
AD9
AF16
AH10
AJ10
AD15
AH16

C1
J1
M1
R1
V1
AA1
A3
P9
J10
N9
P10
A9
Y10
P8
R9
Y9
J11
A21
M10
N10
Y8
J18
J19
K21
A12
H13
A15
J20
J13
K11
K19
A18
L23
K20
K24
L24
H19
A24
K13
J32
A30
C32
F32
L32

AH27
AC23
AL27
R23
P25
R25
T26
U26
W26
Y26
AB26
AC26
AD25
AE26
AF26
AD26
AG25
AH26
AC28
Y28
U28
P28
AH29
AF28
V29
AC29
W27
AB27
V26
AJ26
AJ32
AK29
P26
P29
R29
T29
U29
W29
Y29
AA29
AB29
AD29
AE29
AF29
AG29
AJ29
AK26
AK30
AG26
N30
R31
AF30
AC30
V31
P30
AA31
U30
AD31
AK32
AJ28
Y30
AJ30
AK31
AA23
AG31
N24
AB23
P24
R24
T24
U24
V24
W24
Y24
AC24
AH24
V25
AA25
R26
AA26
T27
AE27

VGA_PCIE_PVDD12
SC4D7U6D3V3KX-GP
C162

PART 5 OF 7

SC4D7U6D3V3KX-GPSC4D7U6D3V3KX-GP
2
1
2
1

1D8V_S0

Part 6 of 7

Core

U54F

CONNECT THESE VDD25 PINS TO 2.5V FOR M52P,M54P,M56P

THESE VDD25 PINS ARE NO CONNECT FOR M26X

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

ATI M5X-P Power 4/4

Size
C

Document Number

Rev

SA

Bolsena-E

Date: Thursday, October 13, 2005

Sheet
1

52

of

58

Ideal Power Up Sequence

Real Power Up Sequence

VBBN

VBBN

VBBP

VBBP

VDDC

VDDC

MVDDC
PCIE_VDDR_12

MVDDC
PCIE_VDDR_12

1mS

PCIE_PVDD_12

PCIE_PVDD_12

www.kythuatvitinh.com
VDD25

VDD25

VDDR1

VDDR1

<5mS

VDDR3

VDDR3

RESISTOR

Value

Symbol name

Tolerance
(J: 5%, F: 1%, D: 0.5%, B: 0.1 %)

Rating
0402=> 1/16W, 25V
0603 => 1/16W, 75V
0805 => 1/10W, 100V

Size
2=>0402, 3=>0603, 5=>0805,
6=>1206, 0=>1210

10KR3

10K Ohm

If no letter, it means J: 5%

1/16W, 75V

0603

33D3R5

33.3 Ohm

If no letter, it means J: 5%

1/10W, 100V

0805

1KR3F

1K Ohm

F: 1%

1/16W, 75V

0603

The naming rule is value + R + size + tolerance

For the value, it can be read by the number before R. (R means resistor)
For the tolerance, it can be read from the last letter.
For the rating, we don't show on the symbol name.
For the size, R2=>0402, R3=>0603, R5=>0805,....

General Guidelines:
BBN and BBP must ramp up before or at the same time as VDDC but not after.
VDDC and MVDDC must be ramped up first, followed by PCIE_VDDR_12, PCIE_PVDD12, VDD25, VDDR1 and
VDDR3 (and other I/O powers).
All powers must be ramped up within 5ms of each other (from the ramp of VDDC to 90% of VDDR3).
VDD25 can be ramped with VDDC or VDDR1 but it cannot be ramped later than VDDR1.
The power down is the opposite of the power on sequence: VDDR3/VDDR1 -> VDD25
->VDDC/MVDDC/BBN/BBP.
Due to the level shifter design in the memory I/Os, in order to avoid over-stressing the thin oxide transistors when
VDDR1 is powered on but VDDC is not, VDDC must ramp up before VDDR1. Similarly, VDDC must ramp up before
VDDR3. The level shifter design is a function of the transistor types used in 90nm technology and of the voltage level support.
The drawback of ramping up VDDC before the I/O voltages (such as VDDR1 and VDDR3) is that parasitic P/N junctions
are forward biased, thus creating a conduction path. These conduction paths will pump up VDDR1 (from the memory
IOs) and VDDR3 (from the GPIOs).
The real power up sequence will appear as follows:
Figure 2-2. Real Power Up Sequence
As long as MVDDC ramps up with VDDC, the pump voltage on VDDR1 should be all right since the DRAM spec will
not be violated.

CAPACITOR
Symbol name

Value

Tolerance
(J: +/-5, K: +/-10,
M: +/-20, Z: +80/-20)

Rating
( X5R / X7R < 80%,
Y5V/Y5U/Z5U < 1/3 )

Size
2=>0402, 3=>0603, 5=>0805,
6=>1206, 0=>1210

SCD1U10V2MX-1 0.1uF

M/X5R

10V

0402

SC10U6D3V5MX

10uF

M/X5R

6.3V

0805

SC2D2U16V5ZY

2.2uF

Z/Y5V

16V

0805

The naming rule is

Capacitor type + value + rating + size + tolerance + material
SCD1U10V2MX-1
SC=> SMT Ceremic, TC=> POS cap or SP cap
D1U => 0.1uF
10V => the voltage rating is 10V
2=> 0402, 3=>0603, 5=>0805
M=>tolerance J, K, M, Z
X=> X7R/X5R, Y=> Y5V
-1 => symbol version, nonsense to EE characteristic

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

ATI M5X-P POWER SEQUENCE

Size
A3

Document Number

Rev

Bolsena-E

Date: Thursday, October 13, 2005

Sheet

SA
53

of

58

CHAN B DDR2 84BGA 32MX16 MEMORY

D

C46
SC1U6D3V2KX-GP

SCD1U10V2KX-LGP

SCD1U10V2KX-LGP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

C98

C99

C81

C82

SCD1U10V2KX-LGP

SC1U6D3V2KX-GP

SCD1U10V2KX-LGP

C83

C84

C100

1D8V_S0

DDR_VREF_S0

M56P
RN88
MAB6
1
MAB2
2
MAB1
3
MAB10
4
SRN56J-2-GP RN89
MAB8
1
MAB0
2
MAB11
3
MAB5
4
SRN56J-2-GP RN90
MAB4
1
MAB3
2
MAB7
3
MAB9
4
SRN56J-2-GP
B_BA0
R388 1
B_BA1
R387 1
MAB12_14
R386 1

51,55
51,55

B_BA0
B_BA1

51,55

MAB12_14

L2
L3

BA0
BA1

MAB11
MAB10
MAB9
MAB8
MAB7
MAB6
MAB5
MAB4
MAB3
MAB2
MAB1
MAB0

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

CLKB0#
CLKB0

K8
J8

CK
CK

CKEB0

K2

CKE

CSB0_0#

L8

CS

WEB0#

K3

WE

RASB0#

K7

RAS

CASB0#

L7

CAS

DQMB#2
DQMB#0

F3
B3

LDM
UDM

1
2

U49
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

MDB7
MDB0
MDB5
MDB2
MDB3
MDB4
MDB1
MDB6
MDB23
MDB18
MDB20
MDB16
MDB17
MDB21
MDB19
MDB22

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

51
51

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

B_BA0
B_BA1

L2
L3

BA0
BA1

MAB12_14
MAB11
MAB10
MAB9
MAB8
MAB7
MAB6
MAB5
MAB4
MAB3
MAB2
MAB1
MAB0

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

K8
J8

CK
CK

CKEB0

K2

CKE

CSB0_0#

L8

CS

WEB0#

K3

WE

RASB0#

K7

RAS

CASB0#

L7

CAS

DQMB#1
DQMB#3

F3
B3

LDM
UDM

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

MDB27
MDB28
MDB24
MDB31
MDB30
MDB25
MDB29
MDB26
MDB15
MDB9
MDB12
MDB8
MDB11
MDB13
MDB10
MDB14

8
7
6
5
8
7
6
5
8
7
6
5
2
2
2

56R2J-4-GP
56R2J-4-GP
56R2J-4-GP

ODTB0
ODTB1

R418 1
R18 1

2
2

56R2J-4-GP
56R2J-4-GP

RASB0#
RASB1#

R416 1
R14 1

2
2

56R2J-4-GP
56R2J-4-GP

CASB0#
CASB1#

R414 1
R16 1

2
2

56R2J-4-GP
56R2J-4-GP

WEB0#
WEB1#

R419 1
R17 1

2
2

56R2J-4-GP
56R2J-4-GP

CSB0_0#
CSB1_0#

R415 1
R15 1

2
2

56R2J-4-GP
56R2J-4-GP

CKEB0
CKEB1

R417 1
R13 1

2
2

56R2J-4-GP
56R2J-4-GP

www.kythuatvitinh.com

SCD1U10V2KX-LGP

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

VSS1
VSS2
VSS3
VSS4
VSS5

F7
E8

LDQS
LDQS

RDQSB3
WDQSB3

B7
A8

UDQS
UDQS

VRAM_VREF2

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

(SSTL-1.8) VREF = .5*VDDQ

SCD1U10V2KX-LGP

1 R404
VRAM_VDDL

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

RASB0#
RASB1#

51
51,55

CASB0#
CASB1#

51
51,55

WEB0#
WEB1#

51
51,55

CSB0_0#
CSB1_0#

51
51,55

CKEB0
CKEB1

0R2J-GP
51
51

C684

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

51
51,55

FOR M56P AT DDR2 MEMORY SPEEDS ABOVE 350MHZ

MEMORY CONTROL SIGNALS WE,CAS,RAS,CS,CKE,ODT
AND MEMORY ADDRESS SIGNALS REQUIRE 55 OHM PULLUP
TO A VTT RAIL (50% OF VDDQ)

ODT

RDQSB1
WDQSB1

R390
1KR2F-3-GP C680

A3
E3
J3
N1
P9

K9

J1
J7

ODTB0
ODTB1

1
1
2
2
1
2

R389
1KR2F-3-GP

ODTB0

VDDL
VSSDL

51
51,55

CLKB0
CLKB0#

CLKB0
CLKB0#

SCD1U10V2KX-LGP
51,55 RDQSB[7..0]
51,55 DQMB#[7..0]

RDQSB[7..0]
DQMB#[7..0]
MDB[63..0]

51,55 MDB[63..0]

MAB[11..0]

51,55 MAB[11..0]
51,55 WDQSB[7..0]

WDQSB[7..0]

<Variant Name>

HY5PS561621A-25GP
72.55616.C0U

HY5PS561621A-25GP
72.55616.C0U

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

72.55616.C0U IC VRAM HY5PS561621AFP-25 FBGA(16M*16, 400Mhz)

72.51216.D0U IC VRAM HY5PS121621BFP-25 FBGA(32M*16, 400Mhz)

Title

VRAM 1/2
Size
A3

Document Number

Rev

SA

Bolsena-E

Date: Thursday, October 13, 2005

5

1D8V_S0

J2

1D8V_S0

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VRAM_VREF1

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

UDQS
UDQS

CLOSE TO MEM !!

1
C707

B7
A8

C688

SCD1U10V2KX-LGP

RDQSB0
WDQSB0

0R2J-GP

LDQS
LDQS

F7
E8

(SSTL-1.8) VREF = .5*VDDQ

R435
1KR2F-3-GP C706

VRAM_VDDL

ODT

RDQSB2
WDQSB2

1
1

R434
1KR2F-3-GP

1 R436

R421
56R2J-4-GP

SC470P50V2KX-3GP

1D8V_S0

K9

J1
J7

R420
56R2J-4-GP

BC857_1

ODTB0

VDDL
VSSDL

CLKB0#
CLKB0

CLKB0#
CLKB0

1D8V_S0

C25
SC1U6D3V2KX-GP

U53
C

C24
SCD1U10V2KX-LGP

SC1U6D3V2KX-GP

C32

C47
SC1U6D3V2KX-GP

SCD1U10V2KX-LGP

SCD1U10V2KX-LGP

SC1U6D3V2KX-GP

SCD1U10V2KX-LGP

C58

C59

C45

C97

1D8V_S0

Sheet
1

54

of

58

C61
SC10U10V5ZY-1GP

SCD1U10V2KX-LGP

C52

C51
SCD1U10V2KX-LGP

SC1U6D3V2KX-GP

C50

C15
SCD1U10V2KX-LGP

SC1U6D3V2KX-GP

C60

C49
SC1U6D3V2KX-GP

SC1KP16V2KX-GP

C26

1D8V_S0

C63
SC10U10V5ZY-1GP

SCD1U10V2KX-LGP

C35

C28
SCD1U10V2KX-LGP

SC1U6D3V2KX-GP

C53

C62
SCD1U10V2KX-LGP

SC1U6D3V2KX-GP

C27

C33
SC1U6D3V2KX-GP

SC1KP16V2KX-GP

C48

1D8V_S0

U50
51,54
51,54

B_BA0
B_BA1

51,54

MAB12_14

B_BA0
B_BA1

L2
L3

BA0
BA1

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

MDB39
MDB32
MDB38
MDB34
MDB33
MDB37
MDB35
MDB36
MDB44
MDB43
MDB47
MDB40
MDB41
MDB46
MDB42
MDB45

U51
B_BA0
B_BA1

L2
L3

BA0
BA1

MAB12_14
MAB11
MAB10
MAB9
MAB8
MAB7
MAB6
MAB5
MAB4
MAB3
MAB2
MAB1
MAB0

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

MDB59
MDB60
MDB58
MDB62
MDB63
MDB56
MDB61
MDB57
MDB51
MDB53
MDB48
MDB55
MDB52
MDB49
MDB54
MDB50

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

www.kythuatvitinh.com
CK
CK

L8

CS

WEB1#

K3

WE

F3
B3
K9

LDM
UDM

VDDL
VSSDL
ODT

C686

CKEB1

K2

CKE

L8

CS

WEB1#

K3

WE

RASB1#

K7

RAS

CASB1#

L7

CAS

F3
B3

LDM
UDM

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

SCD1U10V2KX-LGP
1D8V_S0
1

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

C687

R391
1KR2F-3-GP
2

UDQS
UDQS

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

R392
1KR2F-3-GP

DQMB#6
DQMB#7
ODTB1

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

VDDL
VSSDL

K9

ODT

RDQSB6
WDQSB6

F7
E8

LDQS
LDQS

RDQSB7
WDQSB7

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

VRAM_VREF4
(SSTL-1.8) VREF = .5*VDDQ

C681
2

C685
SCD1U10V2KX-LGP

(SSTL-1.8) VREF = .5*VDDQ

B7
A8

0R2J-GP

LDQS
LDQS

F7
E8

1
2
1

1
R405
1KR2F-3-GP

1 R410

J1
J7

CAS

VRAM_VREF3

CK
CK

R406
56R2J-4-GP CSB1_0#

L7

CLOSE TO MEM !!

RAS

CASB1#

RDQSB4
WDQSB4

K8
J8

SC470P50V2KX-3GP

R400
1KR2F-3-GP

R407
56R2J-4-GP

K7

RDQSB5
WDQSB5

1D8V_S0

BC856_1

RASB1#

ODTB1

CLKB1#
CLKB1

2
2

CSB1_0#

DQMB#5
DQMB#4

1D8V_S0

CKE

K2

CKEB1

51
51

CLKB1#
CLKB1

J1
J7

SCD1U10V2KX-LGP

HY5PS561621A-25GP
72.55616.C0U

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

RASB1#

51,54

CASB1#

51,54

WEB1#

51,54

CSB1_0#

51,54

CKEB1

51,54

ODTB1

51
51

1D8V_S0

RASB1#
CASB1#
WEB1#

CSB1_0#
CKEB1

ODTB1

CLKB1
CLKB1#

CLKB1
CLKB1#

RDQSB[7..0]

51,54 RDQSB[7..0]

DQMB#[7..0]

51,54 DQMB#[7..0]

MDB[63..0]

51,54 MDB[63..0]
1 R401

MAB[11..0]

51,54 MAB[11..0]

0R2J-GP

WDQSB[7..0]

51,54 WDQSB[7..0]

C682

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

51,54

K8
J8

SCD1U10V2KX-LGP

CLKB1#
CLKB1

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

1
1

MAB12_14
MAB11
MAB10
MAB9
MAB8
MAB7
MAB6
MAB5
MAB4
MAB3
MAB2
MAB1
MAB0

C34
SC1U10V3KX-3GP

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

HY5PS561621A-25GP
72.55616.C0U
Title

VRAM 2/2
Size
A3

Document Number

Rev

SA

Bolsena-E

Date: Thursday, October 13, 2005

Sheet
1

55

of

58

FAN5234 FOR VGA_Core

VGA_CORE_PWR
DCBATOUT

VGA_CORE_S0

DCBATOUT_5234
GAP-CLOSE-PWR

G60
G2
1

GAP-CLOSE-PWR

GAP-CLOSE-PWR

GAP-CLOSE-PWR

GAP-CLOSE-PWR

2
GAP-CLOSE-PWR

G67

Dummy when use 'UMA' (whole page)

G3
1

2
GAP-CLOSE-PWR

G64
G1
1

2
GAP-CLOSE-PWR

G63

G4
1

GAP-CLOSE-PWR

G69
G6
1

GAP-CLOSE-PWR

GAP-CLOSE-PWR

2
GAP-CLOSE-PWR

G66
G5
1

2
GAP-CLOSE-PWR

G65
1

2
GAP-CLOSE-PWR

G61
DCBATOUT_5234

SSM5818SLPT-GP

2
GAP-CLOSE-PWR

G62
1

C79

1
2

4
3
2
1

SCD1U25V3ZY-1GP

5
6
7
8

5234_BOOT

17,20,34,38,39,45 PM_SLP_S3#

SC10U25V6KX-1GP

SC10U25V6KX-1GP

C37

D10
5V_S0

U8
AO4422-1-GP

C95

C94

2
G68

S
S
S
G

C66
SCD1U16V2ZY-2GP

D
D
D
D

C67
SC10U10V5KX-2GP

GAP-CLOSE-PWR
5V_S5

M52/M54:1.1V
M56: 1.08V
Iomax=17A
OCP>28A

SCD1U25V3KX-GP

www.kythuatvitinh.com
U6

C30
SCD1U25V3KX-GP

R40
402R3F-GP
C692
SCD1U25V3ZY-1GP

TC19

M56P

DY

M54P

DY

R34
DUMMY-R3

PWM Mode:
FPWM (High)=>Fixed PWM Mode.
FPWM (Low)=>Hysteretic Mode.

TC20

442R2F-GP

R41

C54

R37
10KR2J-2-GP
2

TP3
TPAD30

5
6
7
8

74.05234.A7G

300KHz

4
3
2
1

Panasonic V Size 330uF 2V

ESR=9mohm, Iripple=3.0A
USD:0.250 (Q3/05)

R46
2KR2F-3-GP

5234_VSEN
2

5V_S0

SC2200P50V2KX-2GP

FAN5234MTCX-1GP

U9
AO4430-1-GP

S
S
S
G

1
2

SE330U2VDM-L-GP

R35
44K2R3F-2-GP

C65

PGOOD

SE330U2VDM-L-GP

C29
SCD22U16V3ZY-GP

IND-1UH-42-GP

5234_HDRV
5234_LDRV

14
10

HDRV
LDRV

D
D
D
D

6
5
1
11

5234_VIN

R33 2
1
0R0603-PAD

VGA_CORE_PWR

Vosetting=1.0809V

L22

VSEN
VOUT
VIN
VCC

10KR2J-2-GP DCBATOUT_5234

R42
1K2R3F-GP
1
2

5234_ISEN
5234_SW

ISNS
SW

12
13

9
8

SCD01U16V2KX-3GP

PGND
AGND

Vout Setting:
0.9V/Rlow=(Vout-0.9V)/Rhigh

FPWM
BOOT
SS
ILIM
EN

5234_SS
5234_ILIM
5234_EN

1 R36

16
15
7
4
3

R32
DUMMY-R2

3D3V_S0

SC4D7U10V5ZY-3GP

1 R53
2
20KR2J-L2-GP

C72

1 E

Q6
CHT2222APT-GP

GPIO_PWRCNTL 50

1
G

M56P

M54P

R45
2KR2F-3-GP

R52
10KR2J-2-GP

Q4
2N7002PT-U

R54

High :R800 + R59 set Vout to 1V.

Low : R800 set Vout to 1.08V.

1K62R2F-GP
2
1

POWERPLAY:
high (3.3V) = set lower core voltage (e.g. VDDC = 1.0V)
low (0V) = set higher core voltage (e.g. VDDC = 1.08V)
1

Rilim=(11.2/Iilim)*((100+Rsense)/Rdson)

R74
R73
1KR2J-1-GP 100KR2J-1-GP

<Variant Name>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

VGA CORE 1D1V

Size
A3

(Power Team)
A

Document Number

Date: Thursday, October 13, 2005

Rev

SA

Bolsena-E
Sheet
E

56

of

58

TV SWITCH

Function

A to B0

A to B1

RN96
D

50
50
50

1
2
3
4

DIS_COMP
DIS_LUMA
DIS_CRMA

TV_COMP
TV_LUMA
TV_CRMA

8
7
6
5

TV_COMP 15
TV_LUMA 15
TV_CRMA 15

SRN0J-4-GP

Dummy when use UMA

RN99
13
13
13

1
2
3
4

UMA_CRMA
UMA_LUMA
UMA_COMP

8
7
6
5

TV_CRMA
TV_LUMA
TV_COMP

SRN0J-4-GP

Dummy when use Discrete

-1 0308

www.kythuatvitinh.com
SRN0J-4-GP

RN83

50
50
50

DIS_B
DIS_G
DIS_R

1
2
3
4

8
7
6
5

CRT_B_1
CRT_G_1
CRT_R_1

CRT_B_1 15
CRT_G_1 15
CRT_R_1 15

SRN0J-4-GP

Dummy when use UMA

13
13
13

UMA_R
UMA_G
UMA_B

4
3
2
1

52
52
52
52

ATI_TXBOUT1+
ATI_TXBOUT1ATI_TXBOUT0+
ATI_TXBOUT0-

4
3
2
1

ATI_TXACLK+
ATI_TXACLKATI_TXAOUT2+
ATI_TXAOUT2-

4
3
2
1

ATI_TXAOUT1+
ATI_TXAOUT1ATI_TXAOUT0+
ATI_TXAOUT0-

4
3
2
1

5
6
7
8

LCD_TXBCLK+ 13,16
LCD_TXBCLK- 13,16
LCD_TXBOUT2+ 13,16
LCD_TXBOUT2- 13,16

RN87
SRN0J-4-GP

52
52
52
52

RN82
8
7
6
5

ATI_TXBCLK+
ATI_TXBCLKATI_TXBOUT2+
ATI_TXBOUT2-

5
6
7
8

LCD_TXBOUT1+
LCD_TXBOUT1LCD_TXBOUT0+
LCD_TXBOUT0-

13,16
13,16
13,16
13,16

RN85
SRN0J-4-GP

1
2
3
4

52
52
52
52

CRT_R_1
CRT_G_1
CRT_B_1

5
6
7
8

LCD_TXACLK+ 13,16
LCD_TXACLK- 13,16
LCD_TXAOUT2+ 13,16
LCD_TXAOUT2- 13,16

RN81
SRN0J-4-GP
52
52
52
52

SRN0J-4-GP

Dummy when use Discrete

5
6
7
8

LCD_TXAOUT1+
LCD_TXAOUT1LCD_TXAOUT0+
LCD_TXAOUT0-

13,16
13,16
13,16
13,16

RN79
1 R135

52 ATI_LCDVDD_ON

2
0R2J-GP

LCD_VDD_ON 13,16

<Variant Name>
A

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

VGA SELECTOR
Size
A3

Document Number

Date: Thursday, October 13, 2005

5

Rev
SA

Bolsena-E
Sheet
1

57

of

58

2
SCD1U16V2ZY-2GP

1
1

1
2

DY

DY

EC19

EC60

DY

MAX1544_LXS 41,42
1

MAX1544_LXM 41,42

DY

EC59

EC37

2
SCD1U16V2ZY-2GP

EC47

HOLE P/N: 34.42E05.001

SCD1U16V2ZY-2GP

EC46
SCD1U16V2ZY-2GP

DY

EC31

EC54
2
SCD1U16V2ZY-2GP

2
SCD1U16V2ZY-2GP

2
SCD1U16V2ZY-2GP

EC1

5VA_OP_S0

EC56

EC40

SCD1U16V2ZY-2GP

EC15

EC43

3D3V_S5

2
SCD1U16V2ZY-2GP

EC42

2
SCD1U16V2ZY-2GP
1

EC7

SCD1U16V2ZY-2GP

EC16

1
1
2
SCD1U16V2ZY-2GP

1
2
SCD1U16V2ZY-2GP
EC23

EC53

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

EC6

SCD1U16V2ZY-2GP

SCD1U25V3ZY-3GP

EC70

SCD1U16V2ZY-2GP

2D5V_S0
EC69
SCD1U25V3ZY-3GP

1
2
SCD1U16V2ZY-2GP

EC41

SCD1U25V3ZY-3GP

EC25

2
SCD1U16V2ZY-2GP

2
SCD1U16V2ZY-2GP

EC52

DY

DY

EC51

2
SCD1U16V2ZY-2GP

1
EC74

SCD1U16V2ZY-2GP

DCBATOUT

DCBATOUT

3D3V_LAN_S5

3D3V_BT_S0

EC55

DY

1
2

EC44
DCBATOUT
2D5V_S0

5130_LL3 45,46
EC63

SC1000P50V2JN-N1

DY

3D3V_S0

EC28
SCD1U16V2ZY-2GP

EC18

EC58

DY

DY

EC22

1
2

DY

EC26

DY

EC61

DY

EC29

SCD1U25V3ZY-3GP

EC36

1
2

EC35
SCD1U25V3ZY-3GP

1
2

EC17
SCD1U25V3ZY-3GP

1
EC12
2
SCD1U16V2ZY-2GP

EC4
2
SCD1U16V2ZY-2GP

EC32
2
SCD1U16V2ZY-2GP

1
2

1
EC65

EC30

1D2V_PWR

EC33
SCD1U16V2ZY-2GP

5130_LL1 45,46
5130_LL2 45,46

2
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

2
1

CHG_PWR-2 47

AD+

SC1500P50V3KX-GP

EC21
SCD1U16V2ZY-2GP

HOLE24
HOLE

CHG_PWR-3 47

SCD1U16V2ZY-2GP
DY
EC39
EC75
SCD1U16V2ZY-2GP

3D3V_LAN_S5

SC1000P50V2JN-N1

2D5V_PWR

HOLE5
HOLE

HOLE

2D5V_S0

5V_AUX_S5

EC49

SC1500P50V3KX-GP

1D8V_PWR

1HOLE20

HOLE22
HOLE

3D3V_S5

EC20

HOLE3
HOLE

SC1000P50V2JN-N1

2
SCD1U16V2ZY-2GP

HOLE13
HOLE

SC1500P50V3KX-GP

HOLE1
HOLE

SC1000P50V2JN-N1

EC9

EC27
SCD1U16V2ZY-2GP

HOLE9
HOLE

SC1500P50V3KX-GP

EC72
SCD1U16V2ZY-2GP

HOLE

SC1000P50V2JN-N1

2D5V_S3

2HOLE6

HOLE11
HOLE

SC1500P50V3KX-GP

HOLE10
HOLE

SC1000P50V2JN-N1

SCD1U16V2ZY-2GP

DY

HOLE8
HOLE

HOLE12
HOLE

SC1500P50V3KX-GP

DY

EC11

HOLE7
HOLE

1D2V_S0

HOLE4
HOLE

1D8V_S0

HOLE25
HOLE

VGA_CORE_PWR

HOLE2
HOLE

HOLE17

HOLE14

ZZ.0HOLE.XXX
HOLE18

ZZ.0HOLE.XXX

SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

1
2

SCD1U25V3ZY-3GP

SCD1U25V3ZY-3GP

EC38

SCD1U25V3ZY-3GP

EC64

EC24

EC62

SCD1U25V3ZY-3GP

2
1

EC34

EC48

SCD1U25V3ZY-3GP

EC10

EC13

ZZ.0HOLE.XXX

BT+

EC57
SCD1U25V3ZY-3GP

IMPORTANT:
SCD1U => VOLTAGE 25V
SCD1U16V => VOLTAGE 16V

HOLE15

EC73

SCD1U => VOLTAGE 25V

FOR MDC

HOLE16

SCD1U25V3ZY-3GP

1
2

EC14
SCD1U16V2ZY-2GP

FAN1_VCC

www.kythuatvitinh.com
DCBATOUT

FOR VGA CHIP

EC67
SCD1U25V3ZY-3GP

ZZ.0HOLE.XXX

ZZ.0HOLE.XXX
GREEN COLOR FOR INSTALL

FOR NORTH BRIDGE

HOLE19

DY
HOLE21
1

34.42T14.001

GND16
SPRING-29-GP

GND14

GND13

GNDPAD

SPRING-23-GP

34.40V16.001

34.39S07.001

34.39S07.001

34.39S07.001

SPRING-23-GP SPRING-23-GP SPRING-23-GP SPRING-1-GP

GND9

GNDPAD

GND17

34.39S07.001

GND22

GND21

ZZ.NDPAD.XXX

DY

GND15

ZZ.NDPAD.XXX

DY

ZZ.0HOLE.XXX
GND18

GND19

GND4

DY
GND10

GND12
34.40V16.001

DY

DY

DY

34.40V16.001

34.40V16.001

DY

34.40V16.001

34.45T31.001

DY

34.45T31.001

34.40V16.001

SPRING-1-GP SPRING-24-GP SPRING-24-GP SPRING-1-GP SPRING-1-GP SPRING-1-GP SPRING-1-GP

DY

<Variant Name>

ZZ.0HOLE.XXX

GND11

GND6

Wistron Corporation

SPRING-1-GP

SPRING-1-GP

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.

GND3

34.40V16.001

34.49U24.001

GND5

34.40V16.001

GND1

ZZ.0HOLE.XXX

SPRING-1-GP
34.49U24.001

GND2

34.40V16.001

34.45T31.001

SPRING-24-GP SPRING-1-GP

HOLE23

GND8

GND20

34.40V16.001

GND7

DY

DY

Title
Size
A3

EMI
Document Number

Rev
SA

Bolsena-E

Date: Thursday, October 13, 2005

Sheet

58

of

58