6.

Block Diagram
6-1 Video ControllerBlock Diagram

32

DAT A(0:31)

ROM
ADD R(2:22) 100PIN DIM M 29LV 160
16Mbit Flash Memory 21 A 20

ADD R( 0:31)

DATA(0:31)

29LV 160
16Mbit Flash Memory Mask Font ROM K3P5V 1000D-GC, High Mask Font ROM K3P5V 1000D-GC,L ow RD_FL A SH* W R_FL A SH1,2,3 32 TS* , TT1, nTSB T,TSIZ(0:2) nTA, RST* , I NT* , nTS, nBG 4 SYSCL K 22

32

Regulator 2.7V

CPU POWER PC PPC603ei 166M Hz

74F32
3 RCS(0:3) 4 2

FS781
nW R F_W R_E Frequency Scaling EMI Attenuator

74F04

System clock 11.1M Hz(OSC)

SPGPi
Memory Data Bus

nFSYNC VCL K *

V ideo-Clock
61.23307M Hz

SDRA M
100PIN DIMM 64M bi t SDRAM K4S641632C 64M bi t SD RAM K4S641632C

32 DRA MD(0:3 1)

A DDR(2:18) 11 DATA (16:31) nW AI T nW R nRD I NT* 3 4 6 nW A IT nRD nW R TT1 B RDIN* I OCS1 I OCS2 EI RQ2

60Pin Network Connector

Memory Address Bus

DRA MA (0:1 1)
SDRAM _CAS ,SDRAM_RAS, BA0*,BA1* ,SDRAM_W E* , SDRAM _CS( 0:1) ,SDQM (0:3) , SD_CLK (1:2) ,CL KE

OPTION Network Card

14 EIRQ(0:3)* nI OCS(0:5)*

93C66
4Mbit Serial EEPROM

C7733
Supply Voltage Supervi sor

RESET*

Centronics Connector

74A CT245 Transceiver

ACK *, BUSY, SELECT, ERROR, FAULT* PD(0:7) SELI N* STROBE* A UTOFD* INI * 38

THV_PWM * ,MHV _PWM*, DEV_PWM,THV EN*, L DON* ,PMOTOR*, LSUCL K ,nVI DEO*

To HVPS & L REA DY * , LSYNC* LSU

DATA (0:7)

I OCS0

Engi ne I/F Connector

PANEL 8Pi n

74HCT273
D Fli p-Flop

Computer
Engine Controller B'd
OP Panel

6-1

Block Diagram

6-2 Engine Block Diagram

A0 - A15 PROGRAM MEMORY (27C512) SENSOR

Feed_Sensor Cover_Open SCF_RDY P_Empty P_Exit MP_Empty Output_Full Fuser_SW -------------------Size1 Size2 Size3 D_T_Sensor DET_CRU

HVPS control ADC PWM THV READ THV / MHV / DEV PWM

D0 - D7 STEP MOTR DRIVER (TEA3718 for Main Motor & 2916 for Sub-Motor)

A0 74HC245

74HC245

A8

CPU (KS88C4616)
11.59158MHz

SOLENOID DRIVE MAIN CLUTCH MP CLUTCH

2nd cassette Feeder (option)

ADC

Thermister value

FUSER CONTROL

PTL FAN VIDEO CONTROLLER Interface

CPU Clock (X-tal) 11.59158MHz

6-2