Part (a)

module Datapath_BEH(
output [R2_width -1: 0] count, output reg E, output Zero, input [dp_width
-1: 0] data,
input Load_regs, Shift_left, Incr_R2, clock, reset_b);

#(parameter dp_width = 16, R2_width = 5)

reg [dp_width -1: 0] R1;

reg [R2_width -1: 0] R2;
assign count = R2;
assign Zero = ~(| R1);

always @ (posedge clock) begin

E <= R1[dp_width -1] & Shift_left;
if (Load_regs) begin R1 <= data; R2 <= {R2_width{1'b1}}; end
if (Shift_left) {E, R1} <= {E, R1} << 1;
if (Incr_R2) R2 <= R2 + 1;
end

endmodule

// Test bench for datapath

module t_Datapath_Unit( );

#(parameter dp_width = 16, R2_width = 5)

wire [R2_width -1: 0] count;
wire E, Zero;
reg [dp_width -1: 0] data;
reg Load_regs, Shift_left, Incr_R2, clock, reset_b;

Datapath_BEH M0 (count, E, Zero, data, Load_regs, Shift_left, Incr_R2,

clock, reset_b);

initial #250 $finish;

initial begin clock = 0; forever #5 clock = ~clock; end
initial begin reset_b = 0; #2 reset_b = 1; end
initial

fork
data = 16'hAAAA;
 Load_regs = 0;
Incr_R2 = 0;
Shift_left = 0;
#10 Load_regs = 1;
#20 Load_regs = 0;
#50 Incr_R2 = 1;
#120 Incr_R2 = 0;
#90 Shift_left = 1;
#200 Shift_left = 0;
join

endmodule

Part(b)

// Control Unit

module Controller_BEH (
output Ready,
output reg Load_regs,
output Incr_R2, Shift_left,
input Start, Zero, E, clock, reset_b
);

parameter S_idle = 0, S_1 = 1, S_2 = 2, S_3 = 3;

reg [1:0] state, next_state;

assign Ready = (state == S_idle);

assign Incr_R2 = (state == S_1);
assign Shift_left = (state == S_2);
always @ (posedge clock, negedge reset_b)
if (reset_b == 0) state <= S_idle;
else state <= next_state;

always @ (state, Start, Zero, E) begin

Load_regs = 0;
case (state)
S_idle: if (Start) begin Load_regs = 1; next_state = S_1; end
else next_state = S_idle;
S_1: if (Zero) next_state = S_idle; else next_state = S_2;
S_2: next_state = S_3;
S_3: if (E) next_state = S_1; else next_state = S_2;
endcase
 end
endmodule

// Test plan for Control Unit

module t_Control_Unit ();

wire Ready, Load_regs, Incr_R2, Shift_left;

reg Start, Zero, E, clock, reset_b;

Controller_BEH M0 (Ready, Load_regs, Incr_R2, Shift_left, Start, Zero, E,

clock, reset_b);

initial #250 $finish;

initial begin clock = 0; forever #5 clock = ~clock; end
initial begin reset_b = 0; #2 reset_b = 1; end
initial
fork
Zero = 1;
E = 0;
Start = 0;
#20 Start = 1; // Cycle from S_idle to S_1
#80 Start = 0;
#70 Zero = 0; // S_idle to S_1 to S_2 to S_3 and cycle to S_2.
#130 E = 1; // Cycle to S_3 to S_1 to S_2 to S_3
#150 Zero = 1; // Return to S_idle
join

endmodule

Part(c)

// Integrated system

module Count_Ones_BEH_BEH
# (parameter dp_width = 16, R2_width = 5)
(
output [R2_width -1: 0] count,
input [dp_width -1: 0] data,
input Start, clock, reset_b
);
 wire Load_regs, Incr_R2, Shift_left, Zero, E;
Controller_BEH M0 (Ready, Load_regs, Incr_R2, Shift_left, Start, Zero, E,
clock, reset_b);
Datapath_BEH M1 (count, E, Zero, data, Load_regs, Shift_left, Incr_R2,
clock, reset_b);

endmodule

// Test plan for integrated system

// Test for data values of 8'haa, 8'h00, 8'hff.
// Test bench for integrated system

module t_count_Ones_BEH_BEH ();

parameter dp_width = 16, R2_width =5;
wire [R2_width -1: 0] count;
reg [dp_width -1: 0] data;
reg Start, clock, reset_b;

Count_Ones_BEH_BEH M0 (count, data, Start, clock, reset_b);

initial #700 $finish;

initial begin clock = 0; forever #5 clock = ~clock; end
initial begin reset_b = 0; #2 reset_b = 1; end
initial
fork
data = 16'hAAAA; // Expect count = 5
Start = 0;
#20 Start = 1;
#30 Start = 0;
#40 data = 16'b0000; // Expect count = 0
#250 Start = 1;
#260 Start = 0;
#280 data = 16'hFFFF;
#280 Start = 1;
#290 Start = 0;
join

endmodule