SIMULATION OF FOUR BIT ALU:

module alu(s0,s1,ci,ai,bi,m,f,c0);
input s0,s1,ci,ai,bi,m;
output c0,f;
reg c0,f;
always @ (s0,s1,ci,ai,bi,m)
begin
if(m==1)
case ({s0,s1,ci})
3'b000:{c0,f}=ai;
3'b001:{c0,f}=ai+1;
3'b010:{c0,f}=ai+bi;
3'b011:{c0,f}=ai+bi+1;
3'b100:{c0,f}=ai+(!bi);
3'b101:{c0,f}=ai+(!bi)+1;
3'b110:{c0,f}=ai-bi;
3'b111:{c0,f}=1-(ai-bi);
endcase
if(m==0)
case({s0,s1})
2'b00:{c0,f}=ai&bi;
2'b01:{c0,f}=ai|bi;
2'b10:{c0,f}=ai^bi;
2'b11:{c0,f}=~(ai&bi);
endcase
end
endmodule
module test(s0,s1,ci,a,b,m,f,cout);
input [3:0]a,b;
input s0,s1,ci,m;
output cout;
output[3:0]f;
wire c1,c2,c3;
alu m1(s0,s1,ci,a[0],b[0],m,f[0],c1);
alu m2(s0,s1,c1,a[1],b[1],m,f[1],c2);
alu m3(s0,s1,c2,a[2],b[2],m,f[2],c3);
alu m4(s0,s1,c3,a[3],b[3],m,f[3],cout);
endmodule

SIMULATION OF FOUR BIT MAGNITUDE COMPARATOR:

module mag(a0,a1,a2,a3,b0,b1,b2,b3, g,h,i);
input a0,a1,a2,a3,b0,b1,b2,b3;
output g,h,i;
wire x0,x1,x2,x3;
assign x0=(a0&b0)|(~a0&~b0);
assign x1=(a1&b1)|(~a1&~b1);
assign x2=(a2&b2)|(~a2&~b2);
assign x3=(a3&b3)|(~a3&~b3);
assign g=x0&x1&x2&x3;
assign h=(a3&~b3)|(x3&a2&~b2)|(x3&x2&a1&~b1)|(x3&x2&x1&a0&~b0);
assign i=(~a3&b3)|(x3&~a2&b2)|(x3&x2&~a1&b1)|(x3&x2&x1&~a0&b0);
endmodule

SIMULATION OF SINE WAVE GENERATOR:

module kj(clk,reset,sin,sin1);
reg mclk,mreset;
input reset,clk;
output reg [7:0]sin,sin1;
reg [3:0]count,count1;
reg [7:0]mem[16:0],mem1[16:0];
always@(posedge clk or posedge reset)
begin
if(reset)
begin
count=4'b0000;
sin=8'b00000000;
end
else
begin
mem[0]=8'b00000000;
mem[1]=8'b00000101;
mem[2]=8'b00001010;
mem[3]=8'b00001100;
mem[4]=8'b00001111;
mem[5]=8'b00001100;
mem[6]=8'b00001010;
mem[7]=8'b00000101;
mem[8]=8'b00000000;
mem[9]=8'b11111011;
mem[10]=8'b11110110;
mem[11]=8'b11110100;
mem[12]=8'b11110001;
mem[13]=8'b11110100;
mem[14]=8'b11110110;
mem[15]=8'b11111011;
mem[16]=8'b11110000;
sin=mem[count];
count=count+1;
mclk=count[3];
end
end
always@(posedge mclk or posedge mreset)
begin
if(mreset)
begin
count1=4'b0000;
sin1=8'b00000000;
end
else

begin
mem1[0]=8'b00000000;
mem1[1]=8'b0000101;
mem1[2]=8'b00001010;
mem1[3]=8'b00001100;
mem1[4]=8'b00001111;
mem1[5]=8'b00001100;
mem1[6]=8'b00001010;
mem1[7]=8'b00000101;
mem1[8]=8'b00000000;
mem1[9]=8'b11111011;
mem1[10]=8'b11110110;
mem1[11]=8'b11110100;
mem1[12]=8'b11110001;
mem1[13]=8'b11110100;
mem1[14]=8'b11110110;
mem1[15]=8'b11111011;
mem1[16]=8'b11110000;
sin1=mem1[count1];
count1=count1+1;
end
end
endmodule
SIMULATION OF COSINE WAVE GENERATOR:
module cos(clk,reset,cos,cos1);
reg mclk,mreset;
input reset,clk;
output reg[7:0]cos,cos1;
reg[3:0]count,count1;
reg[7:0]mem[15:0],mem1[15:0];
always@(posedge clk or posedge reset)
begin
if (reset)
begin
count=4'b0000;
cos=8'b00000000;
end
else
begin
mem[0]=8'b00001111;
mem[1]=8'b00001100;
mem[2]=8'b00001010;
mem[3]=8'b00000101;
mem[4]=8'b00000000;
mem[5]=8'b11111011;

mem[6]=8'b11110110;
mem[7]=8'b11110100;
mem[8]=8'b11110000;
mem[9]=8'b11110100;
mem[10]=8'b11110110;
mem[11]=8'b11111011;
mem[12]=8'b00000000;
mem[13]=8'b00000101;
mem[14]=8'b00001010;
mem[15]=8'b00001100;
cos=mem[count];
count=count+1;
mclk=count[3];
end
end
always @(posedge mclk or posedge mreset)
begin
if(mreset)
begin
count1=4'b0000;
cos1=8'b00000000;
end
else
begin
mem1[0]=8'b00001111;
mem1[1]=8'b00001100;
mem1[2]=8'b00001010;
mem1[3]=8'b00000101;
mem1[4]=8'b00000000;
mem1[5]=8'b11111011;
mem1[6]=8'b11110110;
mem1[7]=8'b11110100;
mem1[8]=8'b11110000;
mem1[9]=8'b11110100;
mem1[10]=8'b11110110;
mem1[11]=8'b11111011;
mem1[12]=8'b00000000;
mem1[13]=8'b00000101;
mem1[14]=8'b00001010;
mem1[15]=8'b00001100;
cos1=mem1[count1];
count1=count1+1;
end
end
endmodule

SIMULATION OF VARIOUS CODE CONVERTERS:

BINARY TO GRAY:
module gray(p,q,r,s,reset,clk);
input clk,reset;
reg [3:0]a;
output reg p,q,r,s;
always @(posedge clk)
begin
if(reset)
begin
a=4'b0000;
end
else
begin
assign p=a[3];
assign q=(~a[3]&a[2])|(a[3]&~a[2]);
assign r=(~a[2]&a[1])|(a[2]&~a[1]);
assign s=(~a[1]&a[0])|(a[1]&~sa[0]);
a=a+1;
end
end
endmodule
BCD TO EXCESS-3:
module c(clk,reset,p,q,r,s);
input clk,reset;
reg [3:0]a;
output reg p,q,r,s;
always @(posedge clk)
begin
if(reset)
begin
if(reset)
begin
a=4'b0000;
end
end
begin
if(a<9)
begin
assign p=(a[3])|(a[2]&a[0])|(a[2]&a[1]);
assign q=(a[2]&~a[1]&~a[0])|(~a[2]&a[0])|(~a[2]&a[1]);
assign r=(~a[1]*~a[0])|(a[1]&a[0]);
assign s=(~a[0]);

a=a+1;
end
else
begin
a=4'b0000;
end
end
end
endmodule

SIMULATION OF BIT PATTERN GENERATOR:

module bit(clk,reset,bitsel,aitsel,txdata);
input clk,reset,bitsel,aitsel;
output txdata;
wire patt8,patt4,txdata;
reg [7:0]outt1;
reg [3:0]outt2;
reg [2:0]count;
reg [1:0]count1;
parameter tap=8'b00101011;
parameter tap1=4'b1101;
assign patt8=outt1[7];
assign patt4=outt2[3];
assign txdata=(!aitsel)?patt4:patt8;
always@(posedge clk or negedge reset)
begin
if(!reset)
begin
outt1<=tap;
outt2<=tap1;
count<=3'b000;
count1<=2'b00;
end
else if(bitsel==1'b1&&reset==1'b1)
begin
count <=count+1;
if (outt1==8'b00110010)
begin
outt1<=tap;
end
else
begin
outt1[7]<=outt1[7]^outt1[0];
outt1[6:0]<=outt1[7:1];
count<=count+1;
end
end
else if(bitsel==1'b0&&reset==1'b1)
begin
count1<=count+1;
if(outt2==4'b1001)
begin
outt2<=tap1;
end
else

begin
outt2[3]<=outt2[3]^outt2[0];
outt2[2:0]<=outt2[3:1];
count1<=count1+1;
end
end
end
endmodule

SIMULATION OF VARIOUS MODULATION SCHEMES:

BPSK:
module mod(clk,reset,a,bpsk,sin);
input clk,reset,a;
reg [3:0]count;
reg [7:0]m[16:0];
output reg[7:0]sin;
output reg[7:0]bpsk;
always@(posedge clk or posedge reset)
begin
if(reset)
begin
count=4'b0000;
sin=8'b00000000;
end
else
begin
m[0]=8'b00000000;
m[1]=8'b00000101;
m[2]=8'b00001010;
m[3]=8'b00001100;
m[4]=8'b00001111;
m[5]=8'b00001100;
m[6]=8'b00001010;
m[7]=8'b00000101;
m[8]=8'b00000000;
m[9]=8'b11111011;
m[10]=8'b11111011;
m[11]=8'b11110100;
m[12]=8'b11110001;
m[13]=8'b11110100;
m[14]=8'b11110110;
m[15]=8'b11111011;
m[16]=8'b11110000;
sin =m[count];
count=count+1;
if(a)
begin
bpsk=sin;
end
else
begin
bpsk=~sin;
end

end
end
endmodule
QPSK:
module qpsk(clk,reset, a,qpsk,sin);
input clk,reset;
input [1:0] a;
reg [3:0]count;
reg [7:0]m[15:0];
output reg[7:0]sin;
output reg[7:0]qpsk;
always@(posedge clk or posedge reset)
begin
if(reset)
begin
count=4'b0000;
sin=8'b00000000;
end
else
begin
m[0]=8'b00000000;
m[1]=8'b00000101;
m[2]=8'b00001010;
m[3]=8'b00001100;
m[4]=8'b00001111;
m[5]=8'b00001100;
m[6]=8'b00001010;
m[7]=8'b00000101;
m[8]=8'b00000000;
m[9]=8'b11111011;
m[10]=8'b11111011;
m[11]=8'b11110100;
m[12]=8'b11110001;
m[13]=8'b11110100;
m[14]=8'b11110110;
m[15]=8'b11111011;
m[16]=8'b11110000;
sin=m[count];
count=count+1;
if(a==00)
begin
qpsk=~m[count+2];
end
else if(a==01)
begin

qpsk=~m[count+5];
end
else if(a==11)
begin
qpsk=m[count+2];
end
else
begin
qpsk=m[count+5];
end
count=count+1;
end
end
endmodule

SIMULATION OF BCD TO 7 SEGMENT DECODER:

module 7seg(out,in);
output reg[6:0]out;
input [3:0]in;
always@(in)
begin
case(in)
4'h0:out=70111111';
4'h1:out=7'0000110;
4'h2:out=7'1011011;
4'h3:out=7'10011111;
4'h4:out=7'1100110;
4'h5:out=7'1101101;
4'h6:out=7'1111101;
4'h7:out=7'0000111;
4'h8:out=7'1111111;
4'h9:out=7'1100111;
4'hA:out=7'1110111;
4'hB:out=7'1111100;
4'hC:out=7'0111001;
4'hD:out=7'1011110;
4'hE:out=7'1011001;
4'hF:out=7'1110011;
endcase
endmodule