CAD for VLSI 1

Homework #2

The module interfaces for a few circuits are described below. Use appropriate Verilog design style to model these circuits. For all these designs, indicate the nature of the circuit that is implied from your Verilog code. Draw figures if necessary.

Problems:
1. A parity generator circuit takes 8 bit data as input and gives one output. If there is odd number of ones in the input, the circuit drives a 1 in the output and it drives 0 otherwise. Model the circuit in Verilog. The module interface is provided below for consistency across the class.
module parity(output oddparity, input [7:0]data);

2. Design a 2:1 multiplexer using Verilog. Use these multiplexers and design a 4:1 multiplexer. Module interface is shown below.
module mux4to1(output x, input [3:0]datain, input [1:0]select); module mux2to1(output x, input [1:0]datain, input select);

3. Design a circuit in Verilog that takes a 4 bit number and which counts the number of ones in the input. Circuit must have the following interface:
module countones(no_of_ones, number); input [3:0]number; output [1:0]no_of_ones;

4. Design a binary comparator that compares two 5-bit unsigned numbers a and b and generates the following code : 00 if both are equal, 01 if a < b and 10 if a > b.
module comparator(output [1:0] result, input [4:0]a, input [4:0]b);

Deliverables: Attach the Verilog code and the testbench that you designed to test these modules.
Include waveforms from the resulting verification of your designs. Annotate your waveforms appropriately to show details that are of interest.