A

Compal confidential

Schematics Document
Mobile Yonah uFCPGA with Intel
Calistoga_P/GM+ ICH7-M core logic
2006-04-28

REV:1.0

Compal Secret Data

Security Classification
2005/05/26

Issued Date

2006/07/26

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Cover Sheet
Rev
1.0

LA-2952P

Date:

Sheet

Friday, April 28, 2006

E

of

47

Compal confidential

Caymus

File Name : LA-2952P

Fan Control
page 4

Mobile Yonah/Merom
uFCPGA-478 CPU

Thermal Sensor
ADM1032AR

page 4,5,6

CRT / TV-OUT

page 4

H_A#(3..31)

533/667MHz

H_D#(0..63)

DDR2 -400/533/667

LCD CONN
page 17

Intel Calistoga MCH

945GM

DVI
CH7307C

page 7,8,9,10,11,12

USB2.0

USB conn x3

PCI BUS

Mini-Card WWAN

TI PCI6612

AD1981HD

page 18,19,20,21

SATA

Slot 0/Smart Card

RJ45/11 CONN

page 19

PATA Slave

MAX9710

page 19

LPC BUS
page 34

page 31

TPM 1.2

SMSC Super I/O

LPC47N217
page 34

SMSC KBC 1021

page 29

page 30

Touch Pad CONN.

DC/DC Interface CKT.

page 31

Int.KBD
page 37

COM1
( Docking )

page 32

*RJ-45(LED*2)
*RJ-11(Pass Through)
*CRT
*COMPOSITE Video Out
*TVOUT
*DVI
*LINE IN
*LINE OUT
*PCI-E x2
*Serial Port
*Parallel Port
*PS/2 x2
*USB x2
*DC JACK

Power OK CKT.

Power On/Off CKT.

page 26

Docking CONN.

Multi-bay II Connector

25LF080A
page 29

page 23

AMP & Audio Jack

page 25

page 19

SPI ROM

SD/MMC Slot

page 31

SATA HDD Connector

SPI

MDC

Audio CKT

mBGA-652

CardBus Controller

page 27

page 24

AC-LINK/Azalia

Intel ICH7-M

daughter board

page 27

BT Conn

page 22/23

RTC CKT.

page 32

PCI-E BUS

daughter board

page 24

page 13,14

FingerPrinter AES2501
page 29
USBx1
DMI

page 29

BANK 0, 1, 2, 3

USB conn x2
(Docking)

PCBGA 1466

page 16

LED

DDR2-SO-DIMM X2

Dual Channel

10/100/1000 LAN
BCM5753M

page 24

page 15

FSB

page 16

Mini-Card
WLAN

Clock Generator
ICS9LP306BGLFT

Accelerometer
LIS3LV02DQ

LPT
( Docking )

page 34

page 32

page 33

Compal Secret Data

Security Classification

Power Circuit DC/DC

2005/05/26

Issued Date

Page 35,36,37,38,39,40,41,42,43

2006/07/26

Deciphered Date

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Block Diagram
Rev
1.0

LA-2952P

Date:

Sheet

Friday, April 28, 2006

E

of

47

Symbol Note :

Voltage Rails

Power Plane

Description

VIN
B+
+CPU_CORE
+VCCP

S0-S1

S3

S5

Adapter power supply (18.5V)

N/A

N/A

N/A

AC or battery power rail for power circuit

N/A

N/A

N/A

Core voltage for CPU

ON

OFF

OFF

1.05V power rail for Processor I/O and MCH/ICH core power ON
0.9V switched power rail for DDRII Vtt

+0.9VS

OFF

OFF

ON

OFF

OFF

+1.5VS

1.5V switched power rail for PCI-E interface

ON

OFF

OFF

+1.8V

1.8V power rail for DDRII

ON

ON

OFF

+1.8VS

1.8V switched power rail

ON

OFF

OFF

+2.5VS

2.5V switched power rail for MCH video PLL

ON

OFF

OFF

+3VALW

3.3V always on power rail

ON

ON

ON*

+3VS

3.3V switched power rail

ON

OFF

OFF

+5VALW

5V always on power rail

ON

ON

ON*

+5VS

5V switched power rail

ON

OFF

OFF

+RTC_VCC

RTC power

ON

ON

ON

: means Digital Ground

: means Analog Ground

@ : means just reserve , no build

M52@ : means build discrete sku with ATI VGA M52 .
UMA@ : means build UMA sku with Intel 945GM .
SPI@ : means just build when SPI I/F BIOS function reserve.
FWH@ : means just build when FWH I/F BIOS function reserve.
NOXDP@ : means just build when XDP function disable.
XDP@ : means just build when XDP function enable. When this time, docking PCI express will not work.
1021@ : means just build when SMsC KBC1021 chip selected.
LP@ : means just build when Low power clock gen. install
NOLP@ : means just build when Low power clock gen. NO install

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
C

45@ : means need be mounted when 45 level assy or rework stage.

Internal PCI Devices

DEVICE

Bus

Azalia
PCI-E
USB1.1/2.0
PCI to PCI (DMI to PCI)
AC97 MODEM
AC97 Audio
PATA/SATA
LPC I/F
SMBUS
CPU I/F
B

PCI Device ID

1
0
0
0
0
0
0
0
0
0
0
0
0

LAN

DMA
PMU

IDSEL #

D8

AD24

D27

AD11

D28

AD12

D29

AD13

D30

AD14

D30

AD14

D30

AD14

D31

AD15

D31

AD15

D31

AD15

D31

AD15

D31

AD15

D31

AD15

External PCI Devices

DEVICE

PCI Device ID

CARD BUS

IDSEL #

D6

REQ/GNT #

AD22

PIRQ
CDEG

I2C / SMBUS ADDRESSING

DEVICE

HEX

ADDRESS

DDR SO-DIMM 0

A0

10100000

DDR SO-DIMM 1

A4

10100100

CLOCK GENERATOR (EXT.)

D2

11010010

Compal Secret Data

Security Classification
2005/05/26

Issued Date

2006/07/26

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.

Notes List
Document Number

Rev
1.0

LA-2952P
Sheet

Friday, April 28, 2006

1

of

47

<7>

H_A#[3..31]

H_D#[0..63]

JP12A

+3VS

<7>
R1294

<7>
<7>
<7>
<7>
<7>
<7>
R172
<7>
56_0402_5%
<7>
1
2
<7>
<7>

+VCCP

<7>

H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#

H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_RESET#

H_RS#[0..2]

<7>

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

H_TRDY#

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3

<42> H_PROCHOT#
1 R410
2
56_0402_5%
<19> H_PWRGOOD
<7> H_CPUSLP#

R1264
R1265

2 @ 1K_0402_5%
51_0402_5%
1

1
2

BCLK0
BCLK1

H1
E2
G5
F1
H5
F21
G6
E4
D20
H4
B1

ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#
HITM#
IERR#
LOCK#
RESET#

F3
F4
G3
G2

RS0#
RS1#
RS2#
TRDY#

AD4
AD3
AD1
AC4

BPM0#
BPM1#
BPM2#
BPM3#

XDP_DBRESET# C20
H_DBSY#
E1
H_DPSLP#
B5
H_DPRSTP#
E5
H_DPWR#
D24
XDP_BPM#4 AC2
XDP_BPM#5 AC1
H_PROCHOT# D21

<20> XDP_DBRESET#
<7>
H_DBSY#
<19> H_DPSLP#
<19,42> H_DPRSTP#
<7>
H_DPWR#

+VCCP

A22
A21

H_PWRGOOD
H_CPUSLP#
XDP_TCK
XDP_TDI
XDP_TDO
TEST1
TEST2
XDP_TMS
XDP_TRST#

D6
D7
AC5
AA6
AB3
C26
D25
AB5
AB6

H_THERMDA
A24
H_THERMDC
A25
H_THERMTRIP# C7

<7,19> H_THERMTRIP#

CONTROL

DBR#
DBSY#
DPSLP#
DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H23
M24
W24
AD23
G22
N25
Y25
AE24

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

A20M#
FERR#
IGNNE#
INIT#
LINT0
LINT1

A6
A5
C4
B3
C6
B4

H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI

STPCLK#
SMI#

D5
A3

H_STPCLK#
H_SMI#

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

MISC

PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#

2
1
C948 0.1U_0402_16V4Z
ICH_SMBDATA
ICH_SMBCLK
XDP_TCK

XDP_TMS
XDP_TDO

R236 1
R238 1

2
2

56_0402_1%
56_0402_5%

XDP_BPM#5

R241 1

56_0402_5%

XDP_TRST#

R237 1

56_0402_5%

XDP_TCK

R239 1

56_0402_5%

CLK_CPU_XDP
CLK_CPU_XDP#
+VCCP 1K_0402_1%
H_RESET#_R
1 R242
2 H_RESET#
XDP_DBRESET#_R 2 R243
1 XDP_DBRESET#
200_0402_1%
XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
XDP_PRE
1 R1296 2 0_0402_5%

LEGACY CPU

THERMAL
THERMDA DIODE
THERMDC
THERMTRIP#

CLK_CPU_XDP <15>
CLK_CPU_XDP# <15>

SAMTE_BSH-030-01-L-D-A
C

Thermal Sensor ADM1032AR-2

+3VS

C273
0.1U_0402_16V4Z

R227
U16

C264
1
2

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

SCLK

ICH_SMBCLK

D+

SDATA

ICH_SMBDATA

D-

ALERT#

THERM_SCI#

THERM#

GND

VDD

H_THERMDA

H_THERMDC
THERM#

2200P_0402_50V7K

J26
M26
V23
AC20

DINV0#
DINV1#
DINV2#
DINV3#

+VCCP

10K_0402_5%

THERM_SCI# <20>

R228

<7>
<7>
<7>
<7>

+3VS

ADM1032AR-2_MSOP8

Address:1001_101

10K_0402_5%

ICH_SMBCLK
ICH_SMBDATA

<13,14,15,20,22,24> ICH_SMBCLK
<13,14,15,20,22,24> ICH_SMBDATA

H_DSTBN#[0..3] <7>

H_DSTBP#[0..3] <7>

+5VS

PWM Fan Control circuit

H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI

JP8
1

D11

<19>
<19>
<19>
<19>
<19>
<19>

CH751H-40_SC76

+3VS

H_STPCLK# <19>
H_SMI#
<19>
<30>

FAN_PWM

C122
4.7U_0805_10V4Z

1
2

C125
0.1U_0402_16V4Z

ACES_85205-0200

FAN

THERM# 2

FOX_PZ47903-2741-42_YONAH

U24
G

INB

Q33
AO6402_TSOP6

TC7SH00FU_SSOP5

@ ZD1

INA

H_THERMDA, H_THERMDC routing together.

Trace width / Spacing = 10 / 10 mil

HOST CLK

R1295
H_PWRGOOD 2
1H_PWRGOOD_R
1K_0402_5%

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

GND1
OBSFN_C0
OBSFN_C1
GND3
OBSDATA_C0
OBSDATA_C1
GND5
OBSDATA_C2
OBSDATA_C3
GND7
OBSFN_D0
OBSFN_D1
GND9
OBSDATA_D0
OBSDATA_D1
GND11
OBSDATA_D2
OBSDATA_D3
GND13
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
GND15
TD0
TRST#
TDI
TMS
GND17

CLK_CPU_BCLK
CLK_CPU_BCLK#

<15> CLK_CPU_BCLK
<15> CLK_CPU_BCLK#

XDP_BPM#1
XDP_BPM#0

GND0
OBSFN_A0
OBSFN_A1
GND2
OBSDATA_A0
OBSDATA_A1
GND4
OBSDATA_A2
OBSDATA_A3
GND6
OBSFN_B0
OBSFN_B1
GND8
OBSDATA_B0
OBSDATA_B1
GND10
OBSDATA_B2
OBSDATA_B3
GND12
PWRGOOD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
GND14
SDA
SCL
TCK1
TCK0
GND16

XDP_BPM#3
XDP_BPM#2

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

This shall place near CPU

R246 1
56_0402_5%
2

XDP_TDI

ADSTB0#
ADSTB1#

+VCCP

JP19
XDP_BPM#5
XDP_BPM#4

2 @ 1K_0402_5%

L2
V4

XDP_DBRESET#_R

ITP-XDP Connector

RLZ5.1B_LL34
2

H_ADSTB#0
H_ADSTB#1

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

REQ0#
REQ1#
REQ2#
REQ3#
REQ4#

E22
F24
E26
H22
F23
G25
E25
E23
K24
G24
J24
J23
H26
F26
K22
H25
N22
K25
P26
R23
L25
L22
L23
M23
P25
P22
P23
T24
R24
L26
T25
N24
AA23
AB24
V24
V26
W25
U23
U25
U22
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26

1
2
5
6

K3
H2
K2
J3
L5

DATA GROUP

ADDR GROUP

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

YONAH

<7> H_ADSTB#0
<7> H_ADSTB#1

A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#

<7> H_REQ#[0..4]

J4
L4
M3
K5
M1
N2
J1
N3
P5
P2
L1
P4
P1
R1
Y2
U5
R3
W6
U4
Y5
U2
R4
T5
T3
W3
W5
Y4
W2
Y1

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

+VCCP

R1266
H_DPSLP#

@ 56_0402_5%

@ 56_0402_5%
R1267
H_DPRSTP# 1
2

2 2

R1255

1 OCP#
Q85
@ MMBT3904_SOT23

OCP#

Compal Secret Data

Security Classification
2005/05/26

Issued Date

@ 56_0402_5%

H_PROCHOT# 3

2006/07/26

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

<20,43>

Date:

Compal Electronics, Inc.

Yonah CPU in mFCPGA479
Document Number

Rev
1.0

LA-2952P
Sheet

Friday, April 28, 2006

1

of

47

+VCC_CORE

2
1

R1269
100_0402_1%
2

R1270
100_0402_1%
1
2

VCCSENSE

+1.5VS

C520
0.01U_0402_16V7K

R1268
1K_0402_1%

VSSSENSE

R1271
2K_0402_1%

Close to CPU pin AD26

within 500mils.

C531
10U_0805_10V4Z

Length match within 25 mils

The trace width 18 mils space
<42> VCCSENSE
7 mils
<42> VSSSENSE

+VCCP
D

V_CPU_GTLREF

+VCC_CORE

AF7
AE7

VCCSENSE
VSSSENSE

B26

VCCA

K6
J6
M6
N6
T6
R6
K21
J21
M21
N21
T21
R21
V21
W21
V6
G21

VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP

H_PSI#

AE6

PSI#

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

AD6
AF5
AE5
AF4
AE3
AF2
AE2

VID0
VID1
VID2
VID3
VID4
VID5
VID6

Close to CPU pin

within 500mils.

CPU_BSEL

CPU_BSEL2

CPU_BSEL1

CPU_BSEL0

133

166

H_PSI#

<42>
<42>
<42>
<42>
<42>
<42>
<42>

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

AD26

V_CPU_GTLREF
<15> CPU_BSEL0
<15> CPU_BSEL1
<15> CPU_BSEL2

R1220
54.9_0402_1%
2
1

R355
27.4_0402_1%
2
1

R245
54.9_0402_1%
2
1

GTLREF

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

B22
B23
C21

BSEL0
BSEL1
BSEL2

COMP0
COMP1
COMP2
COMP3

R26
U26
U1
V1

COMP0
COMP1
COMP2
COMP3

+VCC_CORE

R244
27.4_0402_1%
2
1

JP12C
D

VCCSENSE
VSSSENSE

+VCCP

<42>

JP12B

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
mils away from any
other toggling signal.

E7
AB20
AA20
AF20
AE20
AB18
AB17
AA18
AA17
AD18
AD17
AC18
AC17
AF18
AF17

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

YONAH

POWER, GROUNG, RESERVED SIGNALS AND NC

D2
F6
D3
C1
AF1
D22
C23
C24
AA1
AA4
AB2
AA3
M4
N5
T2
V3
B2
C3
T22
B25

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AB26
AA25
AD25
AE26
AB23
AC24
AF24
AE23
AA22
AD22
AC21
AF21
AB19
AA19
AD19
AC19
AF19
AE19
AB16
AA16
AD16
AC16
AF16
AE16
AB13
AA14
AD13
AC14
AF13
AE14
AB11
AA11
AD11
AC11
AF11
AE11
AB8
AA8
AD8
AC8
AF8
AE8
AA5
AD5
AC6
AF6
AB4
AC3
AF3
AE4
AB1
AA2
AD2
AE1
B6
C5
F5
E6
H6
J5
M5
L6
P6
R5
V5
U6
Y6
A4
D4
E3
H3
G4
K4
L3
P3
N4
T4
U3
Y3
W4
D1
C2
F2
G1

AE18
AE17
AB15
AA15
AD15
AC15
AF15
AE15
AB14
AA13
AD14
AC13
AF14
AE13
AB12
AA12
AD12
AC12
AF12
AE12
AB10
AB9
AA10
AA9
AD10
AD9
AC10
AC9
AF10
AF9
AE10
AE9
AB7
AA7
AD7
AC7
B20
A20
F20
E20
B18
B17
A18
A17
D18
D17
C18
C17
F18
F17
E18
E17
B15
A15
D15
C15
F15
E15
B14
A13
D14
C13
F14
E13
B12
A12
D12
C12
F12
E12
B10
B9
A10
A9
D10
D9
C10
C9
F10
F9
E10
E9
B7
A7
F7

FOX_PZ47903-2741-42_YONAH

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

YONAH

POWER, GROUND

K1
J2
M2
N1
T1
R2
V2
W1
A26
D26
C25
F25
B24
A23
D23
E24
B21
C22
F22
E21
B19
A19
D19
C19
F19
E19
B16
A16
D16
C16
F16
E16
B13
A14
D13
C14
F13
E14
B11
A11
D11
C11
F11
E11
B8
A8
D8
C8
F8
E8
G26
K26
J25
M25
N26
T26
R25
V25
W26
H24
G23
K23
L24
P24
N23
T23
U24
Y24
W23
H21
J22
M22
L21
P21
R22
V22
U21
Y21

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

FOX_PZ47903-2741-42_YONAH

Compal Secret Data

Security Classification
2005/05/26

Issued Date

2006/07/26

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.

Yonah CPU in mFCPGA479
Document Number

Rev
1.0

LA-2952P
Sheet

Friday, April 28, 2006

1

of

47

+VCC_CORE

1
Place these capacitors on L8
(North side,Secondary Layer)

C899
10U_0805_6.3V6M

C900
10U_0805_6.3V6M

C901
10U_0805_6.3V6M

C902
10U_0805_6.3V6M

C903
10U_0805_6.3V6M

C904
10U_0805_6.3V6M

C905
10U_0805_6.3V6M

C906
10U_0805_6.3V6M

+VCC_CORE

1
Place these capacitors on L8
(North side,Secondary Layer)

C907
10U_0805_6.3V6M

C908
10U_0805_6.3V6M

C909
10U_0805_6.3V6M

C910
10U_0805_6.3V6M

C911
10U_0805_6.3V6M

C912
10U_0805_6.3V6M

C913
10U_0805_6.3V6M

C914
10U_0805_6.3V6M

+VCC_CORE

1
Place these capacitors on L8
(Sorth side,Secondary Layer)

C915
10U_0805_6.3V6M

C916
10U_0805_6.3V6M

C917
10U_0805_6.3V6M

C918
10U_0805_6.3V6M

C919
10U_0805_6.3V6M

C920
10U_0805_6.3V6M

C921
10U_0805_6.3V6M

C922
10U_0805_6.3V6M

+VCC_CORE

1
Place these capacitors on L8
(Sorth side,Secondary Layer)

C923
10U_0805_6.3V6M

C924
10U_0805_6.3V6M

C925
10U_0805_6.3V6M

C926
10U_0805_6.3V6M

C927
10U_0805_6.3V6M

C928
10U_0805_6.3V6M

C929
10U_0805_6.3V6M

C930
10U_0805_6.3V6M

Mid Frequence Decoupling

+VCC_CORE
330U_D2E_2.5VM_R7

C931
330U_D2E_2.5VM_R7

1
+

C932

C933

330U_D2E_2.5VM_R7

C935

1
C936

1
C937

ESR <= 1.5m ohm

Capacitor > 1980uF

1
C934

45@
820U_E9_2_5V_M_R7

@ 330U_D2E_2.5VM_R7

330U_D2E_2.5VM_R7

330U_D2E_2.5VM_R7

+VCCP

1
+

C983
330U_D2E_2.5VM_R9

C940
0.1U_0402_10V6K

C941
0.1U_0402_10V6K

C942
0.1U_0402_10V6K

C943
0.1U_0402_10V6K

C944
0.1U_0402_10V6K

C945
0.1U_0402_10V6K

Compal Secret Data

Security Classification
2005/05/26

Issued Date

2006/07/26

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.

CPU Bypass capacitors
Document Number

Rev
1.0

LA-2952P
Sheet

Friday, April 28, 2006

1

of

47

H_XSCOMP/H_YSCOMP trace
width and spacing is 5/20.

J13
H_VREF
K13
H_XRCOMP E1
H_XSCOMP E2
H_YRCOMP Y1
H_YSCOMP U1
H_SWNG0
E4
H_SWNG1 W1
R1200
24.9_0402_1%
2
1

R1199
24.9_0402_1%
2
1

HVREF0
HVREF1
HXRCOMP
HXSCOMP
HYRCOMP
HYSCOMP
HXSWING
HYSWING

HADSTB#0
HADSTB#1

B9
C13

H_ADSTB#0
H_ADSTB#1

HCLKN
HCLKP

AG1
AG2

CLK_MCH_BCLK#
CLK_MCH_BCLK

HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3

K4
T7
Y5
AC4
K3
T6
AA5
AC5

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

J7
W8
U3
AB10

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

B7
E8
E7
J9
H8
C3
D4
D3
B3
C7
C6
F6
A7
E3

H_RESET#
H_ADS#
H_TRDY#
H_DPWR#
H_DRDY#
H_DEFER#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
H_CPUSLP#

HCPURST#
HADS#
HTRDY#
HDPWR#
HDRDY#
HDEFER#
HHITM#
HHIT#
HLOCK#
HBREQ0#
HBNR#
HBPRI#
HDBSY#
HCPUSLP#
HRS0#
HRS1#
HRS2#

<13>
<13>
<14>
<14>
H_ADSTB#0 <4>
H_ADSTB#1 <4>

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

<20>
<20>
<20>
<20>

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

<20>
<20>
<20>
<20>

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

CLK_MCH_BCLK# <15>
CLK_MCH_BCLK <15>
H_DSTBN#[0..3] <4>

H_DSTBP#[0..3] <4>

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

<13>
<13>
<14>
<14>

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

AC35
AE39
AF35
AG39

DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

AE37
AF41
AG37
AH41

DMITXN0
DMITXN1
DMITXN2
DMITXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

AC37
AE41
AF37
AG41

DMITXP0
DMITXP1
DMITXP2
DMITXP3

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

AY35
AR1
AW7
AW40

SM_CK0
SM_CK1
SM_CK2
SM_CK3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

AW35
AT1
AY7
AY40

SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

AU20
AT20
BA29
AY29

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

AW13
AW12
AY21
AW21

SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#

M_OCDOCMP0
M_OCDOCMP1

AL20
AF10

SM_OCDCOMP0
SM_OCDCOMP1

M_ODT0
M_ODT1
M_ODT2
M_ODT3

BA13
BA12
AY20
AU21

SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3

M_ODT0
M_ODT1
M_ODT2
M_ODT3
2 80.6_0402_1%
2
80.6_0402_1%

SMRCOMPN
SMRCOMPP

AV9
AT9

V_DDR_MCH_REF

<20,42> DPRSLPVR

<16,18,19,20,22,24,30> PLT_RST#

<20,42> VGATE_INTEL
<20,30> PM_POK

R1304
R1305

1
1

2 @ 0_0402_5%
2 0_0402_5%

PM_BMBUSY#
PM_EXTTS0#
PM_EXTTS1#
PM_THERMTRIP#
PWROK
RSTIN#
ICH_SYNC#

CALISTOGA_FCBGA1466~D

A3
A39
A4
A40
AW1
AW41
AY1
BA1
BA2
BA3
BA39
BA40
BA41
C1
AY41
B2
B41
C41
D1

RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
RESERVED6
RESERVED7
RESERVED8
RESERVED9
RESERVED10
RESERVED11
RESERVED12
RESERVED13

T32
R32
F3
F7
AG11
AF11
H7
J19
A41
A34
D28
D27
A35

CLK_MCH_REF# <15>
CLK_MCH_REF <15>
CLK_MCH_SS# <15>
CLK_MCH_SS <15>

R1205
DDR_THERM#

PM_EXTTS#1

1
1
R1207

2
1
10K_0402_5%
R1209
2
1
@ 10K_0402_5%

M_OCDOCMP0
M_OCDOCMP1

R1203
40.2_0402_1%
2
1

@ 100_0402_1%

R1202
40.2_0402_1%
2
1

2
1
R1204

R1344
GMCH_H32

2 CLKREQC#
0_0402_5%

CLKREQC# <15>

221_0603_1%

1
R1206
2

H_SWNG0

V_DDR_MCH_REF
C895
0.1U_0402_16V4Z

+VCCP

221_0603_1%

100_0402_1%

CLK_MCH_3GPLL <15>
CLK_MCH_3GPLL# <15>

H_SWNG1

0.1U_0402_16V4Z
C897

1
R1211
2

100_0402_1%

0.1U_0402_16V4Z
C896

1
R1210
2

100_0402_1%

0.1U_0402_16V4Z

C898

H_VREF
200_0402_1%

1
R1208

NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18

@ 100_0402_1%
<13,14,41> V_DDR_MCH_REF

+VCCP

H32

GMCH_H32

+1.8V

+VCCP

CLK_MCH_SS#
CLK_MCH_SS

H_RS#[0..2] <4>

Layout Note:
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /
H_SWNG1 trace width and spacing is 18/20.

R1212

D_REF_SSCLKN
D_REF_SSCLKP

C40
D41

Layout Note:
Route as short
as possible

R1201

CLK_MCH_REF#
CLK_MCH_REF

MCH_CLKSEL0 <15>
MCH_CLKSEL1 <15>
MCH_CLKSEL2 <15>
T72
T73
CFG5
<11>
T74
CFG7
<11>
T75
CFG9
<11>
T76
CFG11
<11>
CFG12
<11>
CFG13
<11>
T77
T78
CFG16
<11>
T79
CFG18
<11>
CFG19
<11>
CFG20
<11>

+3VS

Layout Note:
V_DDR_MCH_REF
trace width and
spacing is 20/20.

CALISTOGA_FCBGA1466~D

AG33 CLK_MCH_3GPLL
AF33 CLK_MCH_3GPLL#
A27
A26

CLK_REQ#

PWROK

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2
CFG3
PAD
CFG4
PAD
CFG5
CFG6
PAD
CFG7
CFG8
PAD
CFG9
CFG10
PAD
CFG11
CFG12
CFG13
CFG14
PAD
CFG15
PAD
CFG16
CFG17
PAD
CFG18
CFG19
CFG20

K16
K18
J18
F18
E15
F15
E18
D19
D16
G16
E16
D15
G15
K15
C15
H16
G18
H15
J25
K27
J26

D_REF_CLKN
D_REF_CLKP

SM_VREF0
SM_VREF1

PM_BMBUSY# G28
DDR_THERM#
F25
0_0402_5%
PM_EXTTS#1
H26
1
2
H_THERMTRIP#
G6
<4,19> H_THERMTRIP#
PWROK
AH33
PLTRST_R#
AH34
2
1
R1198
100_0402_1%
K28
<18> MCH_ICH_SYNC#

R1309

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
G_CLKP
G_CLKN

SM_RCOMPN
SM_RCOMPP

AK1
AK41

<20> PM_BMBUSY#
<13,14> DDR_THERM#

H_RESET# <4>
H_ADS# <4>
H_TRDY# <4>
H_DPWR# <4>
H_DRDY# <4>
H_DEFER# <4>
H_HITM# <4>
H_HIT#
<4>
H_LOCK# <4>
H_BR0#
<4>
H_BNR# <4>
H_BPRI# <4>
H_DBSY# <4>
H_CPUSLP# <4>

DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

R1194 1
1
R1195

<4>
<4>
<4>
<4>

AE35
AF39
AG35
AH39

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

+1.8V

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

CFG

<20>
<20>
<20>
<20>

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

<13>
<13>
<14>
<14>

H_RS#0
H_RS#1
H_RS#2

B4
E6
D6

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

<13>
<13>
<14>
<14>

H_REQ#[0..4] <4>

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

HDINV#0
HDINV#1
HDINV#2
HDINV#3

<20>
<20>
<20>
<20>

<13>
<13>
<14>
<14>

D8
G8
B8
F8
A8

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

Description at page11.

U15B

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

CLK

H9
C9
E11
G11
F11
G12
F9
H11
J12
G14
D9
J14
H13
J15
F14
D12
A11
C11
A12
A13
E13
G13
F12
B12
B14
C12
A14
C14
D14

PM

R1197
54.9_0402_1%
2
1

+VCCP

HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#

DDR MUXING

HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

DMI

F1
J1
H1
J6
H3
K2
G1
G2
K9
K1
K7
J8
H4
J3
K11
G4
T10
W11
T3
U7
U9
U11
T11
W9
T1
T8
T4
W7
U5
T9
W6
T5
AB7
AA9
W4
W3
Y3
Y7
W5
Y10
AB8
W2
AA4
AA7
AA2
AA6
AA10
Y8
AA1
AB4
AC9
AB11
AC11
AB3
AC2
AD1
AD9
AC1
AD7
AC6
AB5
AD10
AD4
AC8

H_A#[3..31] <4>

U15A
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

R1196
54.9_0402_1%
2
1

NC

H_D#[0..63]

HOST

<4>

RESERVED

Stuff R1202 & R1203 for A1 Calistoga

Compal Secret Data

Security Classification
2005/05/26

Issued Date

2006/07/26

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.

Calistoga (1/6)
Document Number

Rev
1.0

LA-2952P
Sheet

Friday, April 28, 2006

1

of

47

<13> DDR_A_DQS[0..7]

<13> DDR_A_DQS#[0..7]

<13> DDR_A_MA[0..13]

AU12
AV14
BA20

SA_BS0
SA_BS1
SA_BS2

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

AJ33
AM35
AL26
AN22
AM14
AL9
AR3
AH4

SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

AK33
AT33
AN28
AM22
AN12
AN8
AP3
AG5

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

AK32
AU33
AN27
AM21
AM12
AL8
AN3
AH5

SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

AY16
AU14
AW16
BA16
BA17
AU16
AV17
AU17
AW17
AT16
AU13
AT17
AV20
AV12

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
SA_RCVENIN#
SA_RCVENOUT#

AY13
AW14
AY14
AK23
AK24

SA_CAS#
SA_RAS#
SA_WE#
SA_RCVENIN#
SA_RCVENOUT#

U15E
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

DDR SYS MEMORY A

<13> DDR_A_DM[0..7]

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

<13> DDR_A_CAS#
<13> DDR_A_RAS#
<13> DDR_A_WE#
T68 PAD
T70 PAD

AJ35
AJ34
AM31
AM33
AJ36
AK35
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AW2
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_D[0..63]

<13>
<14> DDR_B_BS#0
<14> DDR_B_BS#1
<14> DDR_B_BS#2
<14> DDR_B_DM[0..7]

<14> DDR_B_DQS[0..7]

<14> DDR_B_DQS#[0..7]

<14> DDR_B_MA[0..13]

<14> DDR_B_CAS#
<14> DDR_B_RAS#
<14> DDR_B_WE#
T69 PAD
T71 PAD

DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2

AT24
AV23
AY28

SB_BS0
SB_BS1
SB_BS2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

AK36
AR38
AT36
BA31
AL17
AH8
BA5
AN4

SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

AM39
AT39
AU35
AR29
AR16
AR10
AR7
AN5

SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

AM40
AU39
AT35
AP29
AP16
AT10
AT7
AP5

SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

AY23
AW24
AY24
AR28
AT27
AT28
AU27
AV28
AV27
AW27
AV24
BA27
AY27
AR23

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
SB_RCVENIN#
SB_RCVENOUT#

AR24
AU23
AR27
AK16
AK18

SB_CAS#
SB_RAS#
SB_WE#
SB_RCVENIN#
SB_RCVENOUT#

CALISTOGA_FCBGA1466~D

DDR SYS MEMORY B

U15D
<13> DDR_A_BS#0
<13> DDR_A_BS#1
<13> DDR_A_BS#2

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

AK39
AJ37
AP39
AR41
AJ38
AK38
AN41
AP41
AT40
AV41
AU38
AV38
AP38
AR40
AW38
AY38
BA38
AV36
AR36
AP36
BA36
AU36
AP35
AP34
AY33
BA33
AT31
AU29
AU31
AW31
AV29
AW29
AM19
AL19
AP14
AN14
AN17
AM16
AP15
AL15
AJ11
AH10
AJ9
AN10
AK13
AH11
AK10
AJ8
BA10
AW10
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AT4
AK5
AJ5
AJ3

DDR_B_D[0..63]

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

<14>

CALISTOGA_FCBGA1466~D

Compal Secret Data

Security Classification
2005/05/26

Issued Date

2006/07/26

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.

Calistoga (2/6)
Document Number

Rev
1.0

LA-2952P
Sheet

Friday, April 28, 2006

1

of

47

PEGCOMP trace width

and spacing is 18/25 mils.
U15C
H27
H28

SDVOCTRL_DATA
SDVOCTRL_CLK

<17> TXOUT_L0+
<17> TXOUT_L1+
<17> TXOUT_L2+

B37
B34
A36

LA_DATA0
LA_DATA1
LA_DATA2

<17> TXOUT_L0<17> TXOUT_L1<17> TXOUT_L2-

C37
B35
A37

LA_DATA#0
LA_DATA#1
LA_DATA#2

<17> TXOUT_U0+
<17> TXOUT_U1+
<17> TXOUT_U2+

F30
D29
F28

LB_DATA0
LB_DATA1
LB_DATA2

<17> TXOUT_U0<17> TXOUT_U1<17> TXOUT_U2-

G30
D30
F29

LB_DATA#0
LB_DATA#1
LB_DATA#2

A32
A33
E26
E27

LA_CLK
LA_CLK#
LB_CLK
LB_CLK#

D32
J30
H30
H29
G26
G25
F32
B38
C35
C33
C32

LBKLT_CTL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL

A16
C18
A19

TVDAC_A
TVDAC_B
TVDAC_C

TXCLK_L+
TXCLK_LTXCLK_U+
TXCLK_UBKLT_CTL
ENABLT

<17> BKLT_CTL
<17> ENABLT

<17> LCD_CLK
<17> LCD_DAT
<17> ENAVDD
R351

LCD_CLK
LCD_DAT
ENAVDD
1 LIBG
1.5K_0402_1%

R9
10K_0402_5%

R393
4.99K_0603_1%
2
1

C_COMP
C_LUMA
C_CRMA
R10

10K_0402_5%

LCD_CLK
LCD_DAT

<16>
<16>

C_VSYNC

C_HSYNC

C_VSYNC
C_HSYNC
C_BLU

C_VSYNC
C_HSYNC

D67

C_GRN
C_RED
1

@ PACDN042_SOT23~D

CRT_IREF

TV_IREF
TV_IRTNA
TV_IRTNB
TV_IRTNC

J29
K30

TV_DCONSEL1
TV_DCONSEL0

C26
C25

DDCCLK
DDCDATA

H23
G23
E23
D23
C22
B22
A21
B21

VSYNC
HSYNC
BLUE
BLUE#
GREEN
GREEN#
RED
RED#

J22

CRT_IREF

CRT

<16> C_DDCCLK
<16> C_DDCDATA

J20
B16
B18
B19

TV

+3VS

R390
255_0402_1%
CALISTOGA_FCBGA1466~D
<BOM Structure>

PCI-EXPRESS GRAPHICS

<17>
<17>
<17>
<17>

EXP_COMPI
EXP_COMPO

LVDS

<16> SDVO_SDAT
<16> SDVO_SCLK

D40
D38

PEGCOMP

+1.5VS_PCIE
R1176
24.9_0402_1%
2

EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

F34
G38
H34
J38
L34
M38
N34
P38
R34
T38
V34
W38
Y34
AA38
AB34
AC38

EXP_RXP0
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

D34
F38
G34
H38
J34
L38
M34
N38
P34
R38
T34
V38
W34
Y38
AA34
AB38

EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
EXP_TXN4
EXP_TXN5
EXP_TXN6
EXP_TXN7
EXP_TXN8
EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

F36
G40
H36
J40
L36
M40
N36
P40
R36
T40
V36
W40
Y36
AA40
AB36
AC40

PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3

C1045 1
C1046 1
C1047 1
C1048 1

2
2
2
2

0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

SDVOB_R- <16>
SDVOB_G- <16>
SDVOB_B- <16>
SDVOB_CLK- <16>

EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
EXP_TXP4
EXP_TXP5
EXP_TXP6
EXP_TXP7
EXP_TXP8
EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

D36
F40
G36
H40
J36
L40
M36
N40
P36
R40
T36
V40
W36
Y40
AA36
AB40

PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3

C1049 1
C1050 1
C1051 1
C1065 1

2
2
2
2

0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

SDVOB_R+ <16>
SDVOB_G+ <16>
SDVOB_B+ <16>
SDVOB_CLK+ <16>

PEG_RXN1

PEG_RXN1 <16>

PEG_RXP1

PEG_RXP1 <16>

TV-Out Termination/EMI Filter

CRT Termination/EMI Filter

C_COMP

L38 1
2
CHB1608U301_0603

COMP

C_LUMA

L37 1
2
CHB1608U301_0603

LUMA

<16,32>

L17 1
2
CHB1608U301_0603

CRMA

<16,32>

82P_0402_50V8J

C_BLU_L

75_0402_1%

R174 12P_0402_50V8J
2

R173

75_0402_1%
75_0402_1%

R177

C7

1
C251

C238

2
2
82P_0402_50V8J

75_0402_1%
75_0402_1%

C333
82P_0402_50V8J

82P_0402_50V8J

C354

C355
82P_0402_50V8J

82P_0402_50V8J

Compal Secret Data

Security Classification

12P_0402_50V8J

2005/05/26

Issued Date

12P_0402_50V8J

2006/07/26

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

75_0402_1%

Date:

1
1
C193 C237 C232

R171

R176

INTEL_GREEN <32>
INTEL_BLUE <32>

<16,32>

1
R175

C_BLU

INTEL_RED <32>

C_GRN_L

C_GRN

L31
1
2
MCI1608HQ39NJA_0603
L34
1
2
MCI1608HQ39NJA_0603
L26
1
2
MCI1608HQ39NJA_0603

C_RED_L

L28
1
2
0_0603_5%
L35
1
2
0_0603_5%
L27
1
2
0_0603_5%

C_CRMA
C_RED

Compal Electronics, Inc.

Calistoga (3/6)
Document Number

Rev
1.0

LA-2952P
Sheet

Friday, April 28, 2006

1

of

47

+1.5VS_DPLLA

Place close to Pin G41

1
2
R260
0_1206_5%
+2.5VS

+1.5VS

+3VS_TVDACC

10U_0805_6.3V6M

+3VS

+3VS_TVDACB

+3VS

B26
C39
AF1

+1.5VS_DPLLA
+1.5VS_DPLLB
+1.5VS_HPLL

VCCA_LVDS
VSSA_LVDS

A38
B39

+2.5VS

VCCA_MPLL

AF2

+1.5VS_MPLL

VCCA_TVBG
VSSA_TVBG

H20
G20

+3VS_TVBG

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

E19
F19
C20
D20
E20
F20

+3VS_TVDACA

VCCD_HMPLL0
VCCD_HMPLL1

AH1
AH2

+2.5VS

+3VS

1
0_0805_5%
1

R97

1
0_0805_5%

C146
0.1U_0402_16V4Z

VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL

C149
0.1U_0402_16V4Z

E21
F21
G21

C143
0.1U_0402_16V4Z

MCH_CRTDAC

VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC2

BLM11A601S_0603
L39
1

C154
2200P_0402_50V7K

C981
220U_D2_2VM_R9

+3VS_TVDACA

R115
C145
2200P_0402_50V7K

R179

2
1
0_0805_5%
1

PCI-E/MEM/PSB PLL decoupling

C839

2
VCCAUX32
VCCAUX33
VCCAUX34
VCCAUX35
VCCAUX36
VCCAUX37
VCCAUX38
VCCAUX39
VCCAUX40

AK31
AF31
AE31
AC31
AL30
AK30
AJ30
AH30
AG30
AF30
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
P15
AH14

+1.5VS_TVDAC
+1.5VS_HPLL

+1.5VS_MPLL
+3VS

R1173
2
1
0_0805_5%

45mA Max.

C846

10U_0805_6.3V6M

+1.5VS

C860
10U_0805_6.3V6M

R1174
2
1
0_0805_5%

45mA Max.

+1.5VS

C862
10U_0805_6.3V6M

+1.5VS

+3VS_TVBG

+3VS

+VCCP

R61

+1.5VS

1
0_0805_5%

VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8
VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31

D12
CH751H-40_SOD323
@

D21
CH751H-40_SOD323
@

1 1

VCCHV0
VCCHV1
VCCHV2

A23
B23
B25

+2.5VS

R127

+3VS

R520

@ 10_0402_5%

@ 10_0402_5%

D21
H19

C861

VCCD_TVDAC
VCCDQ_TVDAC

10U_0805_6.3V6M

+1.5VS

0.1U_0402_16V4Z

A28
B28
C28

C859

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

+1.5VS

R118
0_0603_5%
2
1

C172
0.1U_0402_16V4Z

C153
0.1U_0402_16V4Z

+1.5VS

+1.5VS_TVDAC

R1168
3GPLL 2
1
0_0805_5%

C841
0.1U_0402_16V4Z

+3VS_TVDACC

+1.5VS
R1339
1
2
0.5_0805_1%

C614
2200P_0402_50V7K

+1.5VS_3GPLL

+3VS_TVDACB

C838
0.1U_0402_16V4Z

P O W E R

AG14
AF14
AE14
Y14
AF13
AE13
AF12
AE12
AD12

2
+1.5VS_3GPLL
+2.5VS

1 1

+1.5VS

MCH_D2
C856
0.47U_0603_10V7K
MCH_AB1

C853
0.22U_0603_10V7K

C849
0.22U_0603_10V7K

1
1

1 C824 1 C825

0.1U_0402_16V4Z

2
B

C151
0.1U_0402_16V4Z

C844
0.47U_0603_10V7K

MCH_A6

AC33
G41
H41

C152
2200P_0402_50V7K

VCCA_3GPLL
VCCA_3GBG
VSSA_3GBG

10U_0805_6.3V6M

W=40 mils

C845
0.1U_0402_16V4Z

C830
220U_D2_2VM_R9

AB41
AJ41
L41
N41
R41
V41
Y41

R1163
0_0805_5%
2
1

C850
0.1U_0402_16V4Z

C837
2.2U_0805_16V4Z

C836
4.7U_0805_10V4Z

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

+1.5VS_PCIE

1
1

L40
@ CHB1608U301_0603
1
+1.5VS

C666
330U_D2E_2.5VM

B30
C30
A30

+2.5VS

C253
0.1U_0402_16V4Z

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

+1.5VS

C616
330U_D2E_2.5VM

VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
VTT33
VTT34
VTT35
VTT36
VTT37
VTT38
VTT39
VTT40
VTT41
VTT42
VTT43
VTT44
VTT45
VTT46
VTT47
VTT48
VTT49
VTT50
VTT51
VTT52
VTT53
VTT54
VTT55
VTT56
VTT57
VTT58
VTT59
VTT60
VTT61
VTT62
VTT63
VTT64
VTT65
VTT66
VTT67
VTT68
VTT69
VTT70
VTT71
VTT72
VTT73
VTT74
VTT75
VTT76

H22

C158
0.1U_0402_16V4Z

AC14
AB14
W14
V14
T14
R14
P14
N14
M14
L14
AD13
AC13
AB13
AA13
Y13
W13
V13
U13
T13
R13
N13
M13
L13
AB12
AA12
Y12
W12
V12
U12
T12
R12
P12
N12
M12
L12
R11
P11
N11
M11
R10
P10
N10
M10
P9
N9
M9
R8
P8
N8
M8
P7
N7
M7
R6
P6
M6
A6
R5
P5
N5
M5
P4
N4
M4
R3
P3
N3
M3
R2
P2
M2
D2
AB1
R1
P1
N1
M1

VCC_SYNC

+1.5VS_DPLLB

L41
CHB1608U301_0603
2
1

C157
0.1U_0402_16V4Z

U15H

+VCCP

C144
2200P_0402_50V7K

+1.5VS_DPLLA

C155
2200P_0402_50V7K

C162
0.1U_0402_16V4Z

C831
0.1U_0402_16V4Z

+2.5VS

+1.5VS_DPLLB

CALISTOGA_FCBGA1466~D

Compal Secret Data

Security Classification
2005/05/26

Issued Date

2006/07/26

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.

Calistoga (4/6)
Document Number

Rev
1.0

LA-2952P
Friday, April 28, 2006

Sheet
1

10

of

47

Strap Pin Table

CFG[3:17] have internal pull up

10U_0805_6.3V6M

1
+
2

1
+
2

330U_D2E_2.5VM_R9

C980

C806
220U_D2_2VM_R9

C811

1
+
2

330U_D2E_2.5VM_R9

VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8
VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12

AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17

+VCCP
+1.8V
VCC_SM100
VCC_SM101
VCC_SM102
VCC_SM103
VCC_SM104
VCC_SM105
VCC_SM106
VCC_SM107

AR6
AP6
AN6
AL6
AK6
AJ6
AV1 VCCSM_LF2
AJ1 VCCSM_LF1

CALISTOGA_FCBGA1466~D

C814
0.47U_0603_10V7K

VCC100
VCC101
VCC102
VCC103
VCC104
VCC105
VCC106
VCC107
VCC108
VCC109
VCC110

C813
0.47U_0603_10V7K

M19
L19
N18
M18
L18
P17
N17
M17
N16
M16
L16

Place near pin AV1 & AJ1

C795
0.47U_0603_10V7K

C794
0.47U_0603_10V7K

CFG5
CFG7

0 = Reserved
1 = Mobile Yonah CPU *(Default)

CFG9

0 = Lane Reversal Enable *

1 = Normal Operation (Default)

CFG11

(According to Intel Napa Schematic Checklist & CRB

Rev1.301 document 2.2Kohm pull-down resistor request)

00
01
10
11

CFG[13:12]
+1.8V

=
=
=
=

Reserved
XOR Mode Enabled
All Z Mode Enabled
Normal Operation *(Default)

CFG16

0 = Dynamic ODT Disabled

1 = Dynamic ODT Enabled *(Default)

CFG18

0 = 1.05V
1 = 1.5V

CFG19

0 = Normal Operation * (Default)

1 = DMI Lane Reversal Enable

*(Default)

0 = No SDVO Device Present *

(Default)

SDVO_CTRLDATA

1 = SDVO Device Present

CFG20
(PCIE/SDVO select)

0 = Only PCIE or SDVO is

operational. *(Default)
1 = PCIE/SDVO are operating
simu.

Place near pin BA23

1
C809

1 = Reserved

Place near pin AT41 & AM41

= 667MT/s FSB
= 533MT/s FSB

0 = DMI x 2
1 = DMI x 4 *(Default)

0 = Calistoga

C802

P O W E R

011
001

CFG[2:0]

VCCSM_LF4
VCCSM_LF5

0.1U_0402_16V4Z

CFG[19:18] have internal pull down

C801

AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6

0.1U_0402_16V4Z

C804

VCC_SM0
VCC_SM1
VCC_SM2
VCC_SM3
VCC_SM4
VCC_SM5
VCC_SM6
VCC_SM7
VCC_SM8
VCC_SM9
VCC_SM10
VCC_SM11
VCC_SM12
VCC_SM13
VCC_SM14
VCC_SM15
VCC_SM16
VCC_SM17
VCC_SM18
VCC_SM19
VCC_SM20
VCC_SM21
VCC_SM22
VCC_SM23
VCC_SM24
VCC_SM25
VCC_SM26
VCC_SM27
VCC_SM28
VCC_SM29
VCC_SM30
VCC_SM31
VCC_SM32
VCC_SM33
VCC_SM34
VCC_SM35
VCC_SM36
VCC_SM37
VCC_SM38
VCC_SM39
VCC_SM40
VCC_SM41
VCC_SM42
VCC_SM43
VCC_SM44
VCC_SM45
VCC_SM46
VCC_SM47
VCC_SM48
VCC_SM49
VCC_SM50
VCC_SM51
VCC_SM52
VCC_SM53
VCC_SM54
VCC_SM55
VCC_SM56
VCC_SM57
VCC_SM58
VCC_SM59
VCC_SM60
VCC_SM61
VCC_SM62
VCC_SM63
VCC_SM64
VCC_SM65
VCC_SM66
VCC_SM67
VCC_SM68
VCC_SM69
VCC_SM70
VCC_SM71
VCC_SM72
VCC_SM73
VCC_SM74
VCC_SM75
VCC_SM76
VCC_SM77
VCC_SM78
VCC_SM79
VCC_SM80
VCC_SM81
VCC_SM82
VCC_SM83
VCC_SM84
VCC_SM85
VCC_SM86
VCC_SM87
VCC_SM88
VCC_SM89
VCC_SM90
VCC_SM91
VCC_SM92
VCC_SM93
VCC_SM94
VCC_SM95
VCC_SM96
VCC_SM97
VCC_SM98
VCC_SM99

0.1U_0402_16V4Z

VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99

C800

C803

C805
1U_0603_10V4Z

10U_0805_6.3V6M

AA33
W33
P33
N33
L33
J33
AA32
Y32
W32
V32
P32
N32
M32
L32
J32
AA31
W31
V31
T31
R31
P31
N31
M31
AA30
Y30
W30
V30
U30
T30
R30
P30
N30
M30
L30
AA29
Y29
W29
V29
U29
R29
P29
M29
L29
AB28
AA28
Y28
V28
U28
T28
R28
P28
N28
M28
L28
P27
N27
M27
L27
P26
N26
L26
N25
M25
L25
P24
N24
M24
AB23
AA23
Y23
P23
N23
M23
L23
AC22
AB22
Y22
W22
P22
N22
M22
L22
AC21
AA21
W21
N21
M21
L21
AC20
AB20
Y20
W20
P20
N20
M20
L20
AB19
AA19
Y19
N19

0.1U_0402_16V4Z

AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15

C799

VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8
VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36
VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57

+1.8V

U15G

C807
0.47U_0603_10V7K

C798
0.22U_0603_10V7K

C797
0.22U_0603_10V7K

C796
0.22U_0603_10V7K

VCC_NCTF0
VCC_NCTF1
VCC_NCTF2
VCC_NCTF3
VCC_NCTF4
VCC_NCTF5
VCC_NCTF6
VCC_NCTF7
VCC_NCTF8
VCC_NCTF9
VCC_NCTF10
VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14
VCC_NCTF15
VCC_NCTF16
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
VCC_NCTF22
VCC_NCTF23
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
VCC_NCTF27
VCC_NCTF28
VCC_NCTF29
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
VCC_NCTF33
VCC_NCTF34
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
VCC_NCTF39
VCC_NCTF40
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
VCC_NCTF46
VCC_NCTF47
VCC_NCTF48
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55
VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64
VCC_NCTF65
VCC_NCTF66
VCC_NCTF67
VCC_NCTF68
VCC_NCTF69
VCC_NCTF70
VCC_NCTF71
VCC_NCTF72

P O W E R

AD27
AC27
AB27
AA27
Y27
W27
V27
U27
T27
R27
AD26
AC26
AB26
AA26
Y26
W26
V26
U26
T26
R26
AD25
AC25
AB25
AA25
Y25
W25
V25
U25
T25
R25
AD24
AC24
AB24
AA24
Y24
W24
V24
U24
T24
R24
AD23
V23
U23
T23
R23
AD22
V22
U22
T22
R22
AD21
V21
U21
T21
R21
AD20
V20
U20
T20
R20
AD19
V19
U19
T19
AD18
AC18
AB18
AA18
Y18
W18
V18
U18
T18

+VCCP

+1.5VS

C810

2
10U_0805_6.3V6M

+ C808
2

@ 220U_D2_4VM

<7>

CFG5

<7>

CFG7

<7>

CFG9

<7>

CFG11

<7>

CFG12

<7>

CFG13

<7>

CFG16

R1151

2 @

2.2K_0402_5%

R1152

2 @

2.2K_0402_5%

R1153

2 @

2.2K_0402_5%

R1154

2 @

2.2K_0402_5%

R1155

2 @

2.2K_0402_5%

R1156

2 @

2.2K_0402_5%

R1157

2 @

2.2K_0402_5%

10U_0805_6.3V6M
+3VS

C812
0.47U_0603_10V7K

U15F

+VCCP

<7>
<7>
<7>

R1158
R1159
R1160

CFG18
CFG19
CFG20

2 @ 1K_0402_5%
2 @ 1K_0402_5%
2 @ 1K_0402_5%

1
1
1

Place near pin BA15

CALISTOGA_FCBGA1466~D
A

Compal Secret Data

Security Classification
2005/05/26

Issued Date

2006/07/26

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.

Calistoga (5/6)
Document Number

Rev
1.0

LA-2952P
Sheet

Friday, April 28, 2006

1

11

of

47

U15I
AC41
AA41
W41
T41
P41
M41
J41
F41
AV40
AP40
AN40
AK40
AJ40
AH40
AG40
AF40
AE40
B40
AY39
AW39
AV39
AR39
AN39
AJ39
AC39
AB39
AA39
Y39
W39
V39
T39
R39
P39
N39
M39
L39
J39
H39
G39
F39
D39
AT38
AM38
AH38
AG38
AF38
AE38
C38
AK37
AH37
AB37
AA37
Y37
W37
V37
T37
R37
P37
N37
M37
L37
J37
H37
G37
F37
D37
AY36
AW36
AN36
AH36
AG36
AF36
AE36
AC36
C36
B36
BA35
AV35
AR35
AH35
AB35
AA35
Y35
W35
V35
T35
R35
P35
N35
M35
L35
J35
H35
G35
F35
D35
AN34
AK34
AG34
AF34

VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99

U15J

P O W E R

VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199

AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21

AN21
AL21
AB21
Y21
P21
K21
J21
H21
C21
AW20
AR20
AM20
AA20
K20
B20
A20
AN19
AC19
W19
K19
G19
C19
AH18
P18
H18
D18
A18
AY17
AR17
AP17
AM17
AK17
AV16
AN16
AL16
J16
F16
C16
AN15
AM15
AK15
N15
M15
L15
B15
A15
BA14
AT14
AK14
AD14
AA14
U14
K14
H14
E14
AV13
AR13
AN13
AM13
AL13
AG13
P13
F13
D13
B13
AY12
AC12
K12
H12
E12
AD11
AA11
Y11
J11
D11
B11
AV10
AP10
AL10
AJ10

VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS265
VSS264
VSS263
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279

P O W E R

VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS292
VSS291
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359
VSS360

AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1

CALISTOGA_FCBGA1466~D

CALISTOGA_FCBGA1466~D
A

Compal Secret Data

Security Classification
2005/05/26

Issued Date

2006/07/26

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.

Calistoga (6/6)
Document Number

Rev
1.0

LA-2952P
Sheet

Friday, April 28, 2006

1

12

of

47

+1.8V

+1.8V
V_DDR_MCH_REF

<8> DDR_A_DQS#[0..7]

Layout Note:
Place near JP34

DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11

+1.8V

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
203

DDR_A_D21
DDR_A_D17

C235

C280

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C242

0.1U_0402_16V4Z

C255

C465

0.1U_0402_16V4Z

C491

2.2U_0805_16V4Z

2.2U_0805_16V4Z

C473

2.2U_0805_16V4Z

C498

2.2U_0805_16V4Z

C458

2.2U_0805_16V4Z

DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D22
DDR_A_D19

DDR_A_D25
DDR_A_D24
DDR_A_DM3
DDR_A_D27
DDR_A_D30

<7> DDR_CKE0_DIMMA
<8> DDR_A_BS#2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

DDR_CKE0_DIMMA
DDR_A_BS#2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

<8> DDR_A_BS#0
<8> DDR_A_WE#

+0.9V

<8> DDR_A_CAS#
<7> DDR_CS1_DIMMA#

M_ODT1

DDR_A_CAS#
DDR_CS1_DIMMA#
M_ODT1

DDR_A_D34
DDR_A_D38

DDR_A_DQS#4
DDR_A_DQS4

C227

C234

C241

C252

C268

C274

C281

C279

C272

C257

C250

C239

C229

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

<7>

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_A_D39
DDR_A_D35
DDR_A_D45
DDR_A_D41

DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D52
DDR_A_D53
+0.9V

DDR_A_MA5
DDR_A_MA8

RP27
1
2

DDR_A_MA1
DDR_A_MA3

RP29 56_0404_4P2R_5% RP26 56_0404_4P2R_5%

1
4
4
1 DDR_A_MA7
2
3
3
2 DDR_A_MA6

4
3

Layout Note:
Place these resistor
closely JP34,all
trace length Max=1.5"

RP22 56_0404_4P2R_5%
4
1 DDR_A_BS#2
3
2 DDR_CKE0_DIMMA

DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D51
DDR_A_D55
DDR_A_D56
DDR_A_D61
DDR_A_DM7

RP32 56_0404_4P2R_5% RP25 56_0404_4P2R_5%

DDR_A_RAS#
1
4
4
1 DDR_A_MA9
DDR_CS0_DIMMA# 2
3
3
2 DDR_A_MA12
DDR_A_BS#0
DDR_A_MA10

RP31 56_0404_4P2R_5% RP28 56_0404_4P2R_5%

1
4
4
1 DDR_A_MA4
2
3
3
2 DDR_A_MA2

DDR_A_CAS#
DDR_A_WE#

RP33 56_0404_4P2R_5% RP30 56_0404_4P2R_5%

1
4
4
1 DDR_A_MA0
2
3
3
2 DDR_A_BS#1

DDR_A_D58
DDR_A_D59
<4,14,15,20,22,24> ICH_SMBDATA
<4,14,15,20,22,24> ICH_SMBCLK

ICH_SMBDATA
ICH_SMBCLK
+3VS
C308

RP35 56_0404_4P2R_5% RP34 56_0404_4P2R_5%

DDR_CS1_DIMMA# 2
3
4
1 M_ODT0
M_ODT1
1
4
3
2 DDR_A_MA13

0.1U_0402_16V4Z

56_0404_4P2R_5% RP24 56_0404_4P2R_5%

4
1 DDR_CKE1_DIMMA
3
2 DDR_A_MA11

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
GND

VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
GND

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
204

FOX_ASOA426-M4R-TR

SO-DIMM A
REVERSE

DDR_A_DM0
DDR_A_D5
DDR_A_D6

<7,14,41>

DDR_A_D12
DDR_A_D13
DDR_A_DM1
M_CLK_DDR0
M_CLK_DDR#0

M_CLK_DDR0 <7>
M_CLK_DDR#0 <7>

DDR_A_D9
DDR_A_D15

DDR_A_D20
DDR_A_D16
DDR_THERM# <7,14>

DDR_A_DM2
DDR_A_D18
DDR_A_D23
DDR_A_D29
DDR_A_D28
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D26
DDR_A_D31
DDR_CKE1_DIMMA

DDR_CKE1_DIMMA <7>

DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
DDR_A_MA13

DDR_A_BS#1 <8>
DDR_A_RAS# <8>
DDR_CS0_DIMMA# <7>
M_ODT0

<7>

DDR_A_D36
DDR_A_D33
DDR_A_DM4
DDR_A_D37
DDR_A_D32
DDR_A_D40
DDR_A_D44
B

DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D47
DDR_A_D46
DDR_A_D48
DDR_A_D49
M_CLK_DDR1
M_CLK_DDR#1

M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>

DDR_A_DM6
DDR_A_D50
DDR_A_D54
DDR_A_D60
DDR_A_D57
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63

Top side
Compal Secret Data

Security Classification
2005/05/26

Issued Date

2006/07/26

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

V_DDR_MCH_REF

R453
10K_0402_5%
2
1

DDR_A_D8
DDR_A_D14

DDR_A_D7
DDR_A_D1

R455
10K_0402_5%
2
1

DDR_A_D2
DDR_A_D3

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

C362

DDR_A_DQS#0
DDR_A_DQS0

<8> DDR_A_MA[0..13]

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS

C363

DDR_A_D0
DDR_A_D4

<8> DDR_A_DQS[0..7]

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

0.1U_0402_16V4Z

<8> DDR_A_DM[0..7]

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

2.2U_0805_16V4Z

JP34

<8> DDR_A_D[0..63]

Compal Electronics, Inc.

DDRII-SODIMM SLOT1
Document Number

Rev
1.0

LA-2952P
Sheet

Friday, April 28, 2006

1

13

of

47

+1.8V

<8> DDR_B_DQS#[0..7]

+1.8V

<8> DDR_B_D[0..63]

V_DDR_MCH_REF

<8> DDR_B_DM[0..7]

+1.8V

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D30
DDR_B_D31

<7> DDR_CKE2_DIMMB

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V

<8> DDR_B_BS#2

DDR_CKE2_DIMMB
DDR_B_BS#2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

+0.9V

<8> DDR_B_CAS#
<7> DDR_CS3_DIMMB#
1

<7>

M_ODT3

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#
DDR_B_CAS#
DDR_CS3_DIMMB#
M_ODT3
DDR_B_D37
DDR_B_D36

2
C177

C163

C218

C173

C199

C210

C183

C220

C213

C197

C186

C179

C176

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

<8> DDR_B_BS#0
<8> DDR_B_WE#

DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D35
DDR_B_D34

DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D47

+0.9V

DDR_B_MA1
DDR_B_MA3

RP14
1
2

DDR_B_BS#0
DDR_B_MA10

RP17 56_0404_4P2R_5% RP11 56_0404_4P2R_5%

DDR_CKE3_DIMMB
1
4
4
1
DDR_B_MA11
2
3
3
2

DDR_B_MA0
DDR_B_BS#1

RP16 56_0404_4P2R_5% RP12 56_0404_4P2R_5%

DDR_B_MA5
1
4
4
1
DDR_B_MA8
2
3
3
2

4
3

4
3

RP10 56_0404_4P2R_5%
DDR_B_MA9
1
DDR_B_MA12
2

DDR_B_D48
DDR_B_D53

Layout Note:
Place these resistor
closely JP10,all
trace length Max=1.5"

DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D51
DDR_B_D50
DDR_B_D60
DDR_B_D61
DDR_B_DM7
DDR_B_D58
DDR_B_D59

RP18 56_0404_4P2R_5% RP13 56_0404_4P2R_5%

DDR_B_RAS#
DDR_B_MA7
1
4
4
1
DDR_CS2_DIMMB# 2
DDR_B_MA6
3
3
2

<4,13,15,20,22,24> ICH_SMBDATA
<4,13,15,20,22,24> ICH_SMBCLK

+3VS

DDR_B_CAS#
DDR_B_WE#
A

56_0404_4P2R_5% RP9
4
3

1
2

C301
0.1U_0402_16V4Z

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
204

VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SA0
SA1
GND

FOX_ASOA426-M2RN-7F

SO-DIMM B
STANDARD

DDR_B_DM1
M_CLK_DDR3
M_CLK_DDR#3

M_CLK_DDR3 <7>
M_CLK_DDR#3 <7>

DDR_B_D14
DDR_B_D15

DDR_B_D16
DDR_B_D18
DDR_THERM# <7,13>

DDR_B_DM2
DDR_B_D17
DDR_B_D19
DDR_B_D26
DDR_B_D28
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D29
DDR_B_D27

DDR_CKE3_DIMMB

DDR_CKE3_DIMMB <7>

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#

DDR_B_BS#1 <8>
DDR_B_RAS# <8>
DDR_CS2_DIMMB# <7>

M_ODT2
DDR_B_MA13

M_ODT2

<7>

DDR_B_D33
DDR_B_D32
DDR_B_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45

DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D43
DDR_B_D46
DDR_B_D49
DDR_B_D52
M_CLK_DDR2
M_CLK_DDR#2

M_CLK_DDR2 <7>
M_CLK_DDR#2 <7>

DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
R257
1

+3VS

10K_0402_5%
A

Bottom side

DDR_B_BS#2
DDR_CKE2_DIMMB

Compal Secret Data

Security Classification

56_0404_4P2R_5%

2005/05/26

Issued Date

2006/07/26

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

R254

RP19 56_0404_4P2R_5% RP15 56_0404_4P2R_5%

DDR_B_MA4
1
4
4
1
DDR_B_MA2
2
3
3
2
RP23
56_0404_4P2R_5% RP21 56_0404_4P2R_5%
DDR_CS3_DIMMB# 2
M_ODT2
3
4
1
M_ODT3
DDR_B_MA13
1
4
3
2

ICH_SMBDATA
ICH_SMBCLK

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
GND

DDR_B_D12
DDR_B_D13

10K_0402_5%

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
203

DDR_B_D21
DDR_B_D20

C161

C188

0.1U_0402_16V4Z

C219

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C166

0.1U_0402_16V4Z

C164

C159

2.2U_0805_16V4Z

2.2U_0805_16V4Z

C247

2.2U_0805_16V4Z

C265

C236

2.2U_0805_16V4Z

2.2U_0805_16V4Z

DDR_B_D6
DDR_B_D2

DDR_B_D10
DDR_B_D11

DDR_B_DM0

DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1

<7,13,41>

C90

DDR_B_D7
DDR_B_D3

Layout Note:
Place near JP34

DDR_B_D4
DDR_B_D1

C89

DDR_B_DQS#0
DDR_B_DQS0
D

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS

0.1U_0402_16V4Z

DDR_B_D0
DDR_B_D5

<8> DDR_B_MA[0..13]

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

2.2U_0805_16V4Z

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

<8> DDR_B_DQS[0..7]

V_DDR_MCH_REF

JP10

Compal Electronics, Inc.

DDRII-SODIMM SLOT2
Document Number

Rev
1.0

LA-2952P
Sheet

Friday, April 28, 2006

1

14

of

47

+CK_VDD_MAIN1

FSLA

CLKSEL1

CLKSEL0

0
0

SRC
MHz

133

CPU
MHz

PCI
MHz

100

33.3
1
R1067

+3VS

2
0_0805_5%

*(Default)
533MHz

667MHz

No Stuff

CLK_Rd CLK_Re CLK_Rf

No Stuff

CLK_Ra CLK_Rb CLK_Rc

+3VS

R1389
1
2
NOXDP@0_0805_5%

+VCCP

R1390
1
2
XDP@ 0_0805_5%

Stuff

CLK_Rd CLK_Rf

No Stuff

CLK_Ra CLK_Rb CLK_Rc

C1061

2
CPU_BSEL0

1
R1083
0_0402_5%

C1062
10U_0805_10V4Z

@ 0.1U_0402_16V4Z

+CK_VDD_MAIN1

CK_VDD_REF

R1077
CLK_48M_ICH
2
CLK_48M_CB
2
R1080
CLK_14M_ICH

<20> CLK_14M_ICH

12_0402_5%
1
1 FSA
12_0402_5%
FSB

2
R1087

R1092

2
1K_0402_5%
2

CLK_DEBUG_PORT 2
DEBUG@
33_0402_5%
10K_0402_5%2
33_0402_5% 2
<30> CLK_PCI_EC

CLK_Rb

@ R1113

0_0402_5%

CLK_Re

C735
0.1U_0402_16V4Z

+3VS
R1394

CK_VDD_48

10

VDD48

VDDPCI

24

VDDSRC

33

VDDSATA

C361 2

X2

56

CLK_XTAL_OUT

SATACLKT

28

R1352 1

LP@0_0402_5%

SATACLKC

29

R1333 1

LP@0_0402_5%

CPUCLKT0
CPUCLKC0

51

55

VDDREF
CPUCLKT1

49

CPUCLKC1

48

59

FSLC/TEST_SEL/REF1

CLKIREF
910_0402_1%

46

MCH_SS

LCDCLK_SSC/SRCCLKC0

19

MCH_SS#

PCI/SRC_STOP#

SRCCLKT2

22

Vtt_PwrGd#/PD

SRCCLKC2

23

PCIE_LOM#

**SEL_LCDCLK#/PCICLK_F1
SATA1/SRCCLKT4

30

PCIE_SATA

SATA1/SRCCLKC4

31

REF0/PCICLK1

62

*REQ_SEL/PCICLK2

*SEL_PCI1/PCICLK3

*CLKREQB#

63

**SEL_SATA1/PCICLK4

SRCCLKT1

20

SRCCLKC1

21

SRCCLKT3

26

PCIE_DOCK

SRCCLKC3

27

PCIE_DOCK#

SATA2/SRCCLKT5

35

PCIE_ICH

SATA2/SRCCLKC5

34

**SEL_SATA2/PCICLK5

PCICLK6

1
R1131
1K_0402_5%

CLK_Rc

<28> CLK_PCI_SIO
@ R1139

ICH_SMBDATA

54

SDATA

ICH_SMBCLK

53

SCLK

24_0402_5% 2

1R1148 MCH_REF 13

DOTT_96MHz

CLK_MCH_REF# 24_0402_5% 2

1R1149 MCH_REF# 14

DOTC_96MHz

33_0402_5% 2

1 R1114

PCI_CLK3

2
1

+3VS

SRCCLKT8

43

GND

SRCCLKC8

42

58

GND

47

GNDCPU

*CPUCLKC2_ITP/CLKREQD#

44

25

GNDSRC

SRCCLKT7

39

+3VS

40

GNDSRC

SRCCLKC7

38

32

GNDSATA

R1245

10K_0402_5%

10K_0402_5%

C374

C375

C376

C378

C379

C380

R1247

@ 10K_0402_5%

@ 10K_0402_5%

R1246

CLK_DEBUG_PORT
1
@ 5P_0402_50V8C

CLK_CPU_BCLK <4>
CLK_CPU_BCLK# <4>
CLK_MCH_BCLK <7>
CLK_MCH_BCLK# <7>

CLK_MCH_SS
24_0402_5%
CLK_MCH_SS#
24_0402_5%

1
R1093
1
R1095

CLK_PCIE_LOM
2
24_0402_5%
CLK_PCIE_LOM#
2
24_0402_5%

CLKREQB#

2
R1106
T92 PAD

2
2

CLK_PCIE_SATA
24_0402_5%
CLK_PCIE_SATA#
24_0402_5%

CPPE#
1
10K_0402_5%

CLK_MCH_SS <7>
CLK_MCH_SS# <7>

CLKREQA# 1

2 C740
@ 1000P_0402_50V4Z

CLK_PCIE_LOM <22>

CLKREQB# 1

2 C741
@ 1000P_0402_50V4Z

CPU_XDP

2 C744
@ 1000P_0402_50V4Z

CPU_XDP# 1

2 C745
@ 1000P_0402_50V4Z

CLK_PCIE_LOM# <22>
CLK_PCIE_SATA <19>
CLK_PCIE_SATA# <19>

CPPE#

<18,32>

T93 PAD
1
R1144
1
R1145

CLK_PCIE_DOCK
2
24_0402_5%
CLK_PCIE_DOCK#
2
24_0402_5%

CLK_PCIE_DOCK <32>
CLK_PCIE_DOCK# <32>

CLK_PCIE_ICH
2
CLK_PCIE_ICH <20>
24_0402_5%
PCIE_ICH#
CLK_PCIE_ICH#
2
CLK_PCIE_ICH# <20>
24_0402_5%
R1120 2
1 NOXDP@10K_0402_5%
+3VS
CLKREQC#
2
1
CLKREQC# <7>
R1142 NOXDP@0_0402_5%
CPU_XDP
CLK_CPU_XDP
1
2
CLK_CPU_XDP <4>
R1133 XDP@ 24_0402_5%
MCH_3GPLL 1
CLK_MCH_3GPLL
2
CLK_MCH_3GPLL <7>
R1111
24_0402_5%
MCH_3GPLL# 1
CLK_MCH_3GPLL#
2
CLK_MCH_3GPLL# <7>
R1115
24_0402_5%
1
R1123
1
R1126

R1147 2

1 NOXDP@10K_0402_5%

CLKREQD#
2
1
R1254 NOXDP@0_0402_5%
CPU_XDP#
CLK_CPU_XDP#
1
2
R1143 XDP@ 24_0402_5%
PCIE_MCARD 1
CLK_PCIE_MCARD
2
R1249
24_0402_5%
PCIE_MCARD# 1
CLK_PCIE_MCARD#
2
R1251
24_0402_5%

+3VS

CLKREQD# <24>
CLK_CPU_XDP# <4>
CLK_PCIE_MCARD <24>
CLK_PCIE_MCARD# <24>

ICS9LP306_TSSOP64
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor

High:Pin44/45 = CLKREQ

*Low:Pin44/45 = CPUCLK2_ITP

Compal Secret Data

Security Classification
2005/05/26

Issued Date

= 100MHz
*High:Pin18/19
Low:Pin18/19 = 96MHz

2006/07/26

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Place close to U25

PCI_MINI

J29
NO SHORT PADS

PCI_ICH

300_0402_5%
1 2

R1351

R1108

CLK_ENABLE#
A

36

GND

R1146
@ 10K_0402_5%

SRCCLKC6

17

Pin44/45 function select

+3VS

37

12

XDP@ : means just build when XDP function enable.

When this time, docking PCI express will not work.
LCD(Low)/SRC(High)
clock select

45

SRCCLKT6
GND

0_0402_5%

CLK_Rf

*CPUCLKT2_ITP/CLKREQC#

NOXDP@ : means just build when XDP function disable.

CLKREQA# <22>
1
R1129
1
R1132

1
R1257
PCIE_SATA# 1
R1259

60

<7> CLK_MCH_REF

CLKREQA#

18

1 R1141 PCI_PCM

<7> CLK_MCH_REF#
MCH_CLKSEL2 <7>

CLK_MCH_BCLK
2
24_0402_5%
CLK_MCH_BCLK#
2
24_0402_5%

1
R1075
MCH_BCLK# 1
R1081

64

1
R1135
0_0402_5%

MCH_BCLK

*CLKREQA#

2
CPU_BSEL2

CLK_CPU_BCLK
2
24_0402_5%
CLK_CPU_BCLK#
2
24_0402_5%

33_0402_5% 2

CLK_MCH_REF

C373

18P_0402_50V8J

1
R1070
CPU_BCLK#
1
R1072

PCIE_LOM

<24> CLK_PCI_PCM

CPU_BCLK

CPU_STOP#

<29> CLK_PCI_TCG

C364

LCDCLK_SST/SRCCLKT0
IREF

1@ 10K_0402_5% PCI_EC

<5>

1K_0402_5%

C372

Routing the trace at least 10mil

CLK_XTAL_IN

VDDCPU

1 CLKREF1
33_0402_5%

Y3
14.31818MHZ_16P

57

VDDSRC

R1128
R1130
8.2K_0402_5%
CLKREF1 2
1

C357

1 CLK_48M_ICH
@ 5P_0402_50V8C
1 CLK_48M_CB
@ 5P_0402_50V8C
1 CLK_14M_ICH
4.7P_0402_50V8C
1 CLK_PCI_ICH
4.7P_0402_50V8C
1 CLK_14M_KBC
4.7P_0402_50V8C
1 CLK_14M_SIO
4.7P_0402_50V8C
1 CLK_PCI_EC
4.7P_0402_50V8C
1 CLK_PCI_TCG
4.7P_0402_50V8C
1 CLK_PCI_PCM
4.7P_0402_50V8C
1 CLK_PCI_SIO
4.7P_0402_50V8C

1
18P_0402_50V8J

X1

50

1 R1140 PCI_CLK5

<4,13,14,20,22,24> ICH_SMBCLK

0.1U_0402_16V4Z

52

FSLB/TEST_MODE

1 R1109 PCI_CLK3
1 R1110 PCI_EC

C356

C736

41

15

2 R1097 1 PCI_ICH
33_0402_5%
R1101
12_0402_5%
2
1 CLKREF0
2
1
R1104
12_0402_5%
1 R1117 PCI_MINI

Place crystal within

500 mils of CK410

VDD

33_0402_5% 2

<4,13,14,20,22,24> ICH_SMBDATA

+VCCP

CLK_PCI_ICH

MCH_CLKSEL1 <7>
<24> CLK_DEBUG_PORT

R1105
1K_0402_5%

U25

61

CLK_14M_KBC
CLK_14M_SIO

<30> CLK_14M_KBC
<28> CLK_14M_SIO

1
1
2

CK_VDD_REF

R1069
2.2_0805_1%

0.1U_0402_16V4Z

FSLA/USB_48MHz

CLK_ENABLE#

<18> CLK_PCI_ICH

R1098

FSB

R1068
1
2
1_0805_1%

C353

C739

11

H_STP_CPU#
H_STP_PCI#

<20> H_STP_CPU#
<20> H_STP_PCI#
<34,42> CLK_ENABLE#

1
R1107
0_0402_5%

C733
0.01U_0402_16V7K

R1086

+VCCP

CPU_BSEL1

0.1U_0402_16V4Z

2
<20> CLK_48M_ICH
<24> CLK_48M_CB

MCH_CLKSEL0 <7>

1K_0402_5%

<5>

R1079
1K_0402_5%

CLK_Ra

C734

0.1U_0402_16V4Z

CLK_Rd

0.1U_0402_16V4Z

0.1U_0402_16V4Z
CLKIREF
C743

<5>

C742

+CK_VDD_DP
2 R1393 1
@ 0_0402_5%

CK_VDD_48

CLK_Re

10U_0805_10V4Z

+CK_VDD_DP

+VCCP

C738

16

@ R1074
56_0402_5%

1
C732
0.01U_0402_16V7K

+CK_VDD_DP

CLK_Rd CLK_Re CLK_Rf

Stuff

R1078
8.2K_0402_5%
FSA 2
1

1
C731
0.01U_0402_16V7K

C737

CLK_Ra CLK_Rb CLK_Rc

Stuff

10U_0805_10V4Z

FSB Frequency Selet:

CPU Driven

C730

+CK_VDD_MAIN2

Table : ICS954306
D

2
0_0805_5%

33.3

100

166

1
R1066

+3VS

FSLB

CLKSEL2

FSLC

Compal Electronics, Inc.

Clock generator
Document Number

Rev
1.0

LA-2952P
Sheet

Friday, April 28, 2006

1

15

of

47

+5VS

+RCRT_VCC

G
3

R54 51K_0402_5%
1
2

R545
1
2
0_0603_5%

VSYNC_G_A 1

D_HSYNC

<32>

D_VSYNC

U54
SN74AHCT1G125GW_SOT353-5
1
C351
2

D_HSYNC

R546
2
0_0603_5%

@ 5P_0402_50V8C

D20
@ DAN217_SC59

+3VS

SUYIN_070912FR015S207CR

+CRTVDD

+CRTVDD

D_VSYNC <32>
C352

R162

@ 5P_0402_50V8C

R183

2.2K_0402_5%

2.2K_0402_5%
2

Q46

D_DDCDATA

<32> D_DDCDATA

C_DDCDATA <9>
2
G

R53 51K_0402_5%
1
2

Place close to docking connector

16
17

R4
1
2
2.2K_0402_5%

5
1
P
OE#

BLUE_R

R2
1
2
2.2K_0402_5%

U33
SN74AHCT1G125GW_SOT353-5
HSYNC_G_A
4

2
0.1U_0402_16V4Z

+CRTVDD

2
G

5
1
C_VSYNC

P
OE#

<9>

GREEN_R

RED_R

1
2
0_0603_5%
R543
1
2
0_0603_5%
R544
1
2
0_0603_5%

C_HSYNC

RED

JP2
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

R542

C370

0.1U_0402_16V4Z

<9>

<32>

C310
18P_0402_50V8C

GREEN

C314
18P_0402_50V8C

+5VS

C359

BLUE

<32>

C313
18P_0402_50V8C

+5VS

<32>

C315
0.1U_0402_16V4Z

BLUE_R
GREEN_R
RED_R

CH491D_SC59

D19
DAN217_SC59

1
1.1A_6VDC_FUSE

W=40mils

CRT Connector

+CRTVDD

D18

F1

D4
DAN217_SC59

RHU002N06_SOT323

C_DDCCLK <9>

D_DDCCLK

<32> D_DDCCLK

Q52
RHU002N06_SOT323

+2.5VS

R1369
CHB1608U301_0603
2
1 DVI_DVDD_2.5V
C178

C142

DVI_AVDD_2.5V
C150

C174

C141

+2.5VS

TV-Out Connector

R1367
1
2
+2.5VS
KC FBM-L11-201209-221LMA30T_0805
1
C371
C140
22U_0805_6.3V4Z
2

0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

R497

R1368
DVI_AVDD_3V 1
2
+3VS
KC FBM-L11-201209-221LMA30T_0805
1
C368
C369
10U_0805_10V4Z
2

C358

0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

10K_0402_5%
2

DVI_AVDD_3V
AS
DVI_DVDD_2.5V

U11

COMP

R549

TV_LUMA
TV_CRMA
TV_COMP

1
2
3
4
5
6
7

SDVOB_G+
SDVOB_G-

<9> SDVOB_B+
<9> SDVOB_B-

43
44

SDVOB_B+
SDVOB_B-

<9> SDVOB_CLK+
<9> SDVOB_CLK-

46
47

SDVOB_CLK+
SDVOB_CLK-

<7,18,19,20,22,24,30> PLT_RST#

AS
3
PLT_RST# 2
DVI_VSWING 25
27
26

R103

AS
RESET#
VSWING
ATPG
SCEN

R114

R498

1.3K_0402_1%

TLC#
TLC
TDC0#
TDC0
TDC1#
TDC1
TDC2#
TDC2

13
14
16
17
19
20
22
23

HPDET

29

SC_DDC
SD_DDC

11
10

SC_PROM
SD_PROM

9
8

SPD
SPC

5
4

DVI_DETECT

DVI_DETECT <32>
DVI_CLK
DVI_DAT

SDVO_SDAT
SDVO_SCLK

<32>
<32>

SDVO_SDAT <9>
SDVO_SCLK <9>

+2.5VS

CH7307C_LQFP48
SDVO_SDAT
SDVO_SCLK

R143 1
R142 1

2 5.6K_0402_5%
2 5.6K_0402_5%

DVI_CLK- <32>
DVI_CLK+ <32>
DVI_TX0- <32>
DVI_TX0+ <32>
DVI_TX1- <32>
DVI_TX1+ <32>
DVI_TX2- <32>
DVI_TX2+ <32>

10K_0402_5%

SUYIN_33007SR-07T1-C

DGND
DGND
AGND
AGND
AGND
TGND
TGND
AGND_PLL

<9,32>

R548

2
0_0603_5%
2
0_0603_5%
2
0_0603_5%

40
41

PAD

CRMA

SDVOB_R+
SDVOB_R-

<9> SDVOB_G+
<9> SDVOB_G-

<9,32>

R547

<9> SDVOB_R+
<9> SDVOB_R-

LUMA

SDVOB_INT+
SDVOB_INT-

37
38

<9,32>

SDVOB_INT+
SDVOB_INT0.1U_0402_16V4Z

7
30
31
39
45
18
24
6

1
3

1
2

1
3

JP1

C1043
C1042

32
33

PEG_RXP1
PEG_RXN1

49

<9>
<9>

DVDD
DVDD
AVDD_PLL
TVDD
TVDD
AVDD
AVDD
AVDD

0.1U_0402_16V4Z

NC
NC

Place close to JP1

DVI Transnitter

12
28
1
15
21
36
42
48

34
35

W=20 mils

+3VS
D3
D5
D1
@ DAN217_SC59
@ DAN217_SC59
@ DAN217_SC59

DVI_AVDD_2.5V

10K_0402_5%

Compal Secret Data

Security Classification
2005/05/26

Issued Date

2006/07/26

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.

CRT & TVout Connector
Document Number

Rev
1.0

LA-2952P
Sheet

Friday, April 28, 2006

E

16

of

47

LVDS CONN

B+_LCD

LCD POWER CIRCUIT

2
0.1U_0603_50V4Z
2
68P_0402_50V8J

LCDVDD

+3VALW

3
Q8
SI2301BDS_SOT23
R12

JP35

LCDVDD
1

1
C586
1
C587

1
@ KC FBM-L11-201209-221LMA30T_0805
1
KC FBM-L11-201209-221LMA30T_0805

100_0402_1%

B+

D
Q5

+3VS

RHU002N06_SOT323

2
G

47K_0402_5%

C29

LCDVDD

ALS_EN <18>
BKLT_CTL <9>
<9>
<9>

<9>

0.047U_0402_16V7K

C31
4.7U_0805_10V4Z

C20
@ 4.7U_0805_10V4Z

0.1U_0402_16V4Z

ENAVDD

R509
2.2K_0402_5%

TXOUT_U1+ <9>
TXOUT_U1- <9>

Q53
DTA114YKA_SC59

TXOUT_U0+ <9>
TXOUT_U0- <9>

+5VS_INV

10K

47K

+5VS
TXOUT_L0- <9>
TXOUT_L0+ <9>
+3VS

<20,31> LID_SW#
TXCLK_L- <9>
TXCLK_L+ <9>

<9>

ENABLT

U43A
SN74LVC08APW_TSSOP14

O
7

R360

Q36
BSS138_SOT23

2
G

R501
100K_0402_5%

100K_0402_5%
1

ACES_88316-4000

3
2

LID_SW#

TXOUT_L2- <9>
TXOUT_L2+ <9>

14

TXOUT_L1- <9>
TXOUT_L1+ <9>

TXOUT_U2+ <9>
TXOUT_U2- <9>

TXCLK_U+ <9>
TXCLK_U- <9>

LCD_CLK
LCD_DAT

Q6
DTC124EK_SC59

+5VS_INV

1M_0402_5%
C28
1
2

R474

1 2

L62

L76

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

2
G

R19

Compal Secret Data

Security Classification
2005/05/26

Issued Date

2006/07/26

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.

LCD CONN.
Document Number

Rev
1.0

LA-2952P
Sheet

Friday, April 28, 2006

1

17

of

47

+5VS
2

+3VS

R433
R1041 1

2 8.2K_0402_5%

PCI_DEVSEL#

R1042 1

2 8.2K_0402_5%

PCI_STOP#

R1043 1

2 8.2K_0402_5%

PCI_TRDY#

R1044 1

2 8.2K_0402_5%

PCI_FRAME#

R1045 1

2 8.2K_0402_5%

PCI_PLOCK#

R1046 1

2 8.2K_0402_5%

PCI_IRDY#

R1047 1

2 8.2K_0402_5%

PCI_SERR#

R1048 1

2 8.2K_0402_5%

PCI_PERR#

R1049 1

2 8.2K_0402_5%

PCI_REQ4#

R1050 1

2 8.2K_0402_5%

PCI_REQ3#

330_0402_5%

R1052 1

2 8.2K_0402_5%

PCI_PIRQA#

R1053 1

2 8.2K_0402_5%

PCI_PIRQB#

R1054 1

2 8.2K_0402_5%

PCI_PIRQC#

R1055 1

2 8.2K_0402_5%

PCI_PIRQD#

R1056 1

2 8.2K_0402_5%

PCI_PIRQE#

R1058 1

2 8.2K_0402_5%

PCI_PIRQF#

R1059 1

2 8.2K_0402_5%

PCI_PIRQG#

R1060 1

2 8.2K_0402_5%

PCI_PIRQH#

R1061 1

2 8.2K_0402_5%

PCI_REQ0#

R1062 1

2 8.2K_0402_5%

PCI_REQ1#

R1063 1

2 8.2K_0402_5%

PCI_REQ2#

R1064 1

2 8.2K_0402_5%

CPPE#

R1262 1

2 @ 8.2K_0402_5% IDE_RESET#

<24> PCI_PIRQC#
<24> PCI_PIRQD#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

A3
B4
C5
B5
AE5
AD5
AG4
AH4
AD9

PCI_REQ0#
PCI_GNT0#
PCI_REQ1#

PCI_REQ0#
PCI_GNT0#

PCI_REQ2#
PCI_GNT2#
PCI_REQ3#

PCI_REQ2# <24>
PCI_GNT2# <24>

C/BE0#
C/BE1#
C/BE2#
C/BE3#

B15
C12
D12
C15

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#

A7
E10
B18
A12
C9
E11
B10
F15
F14
F16

PCI_IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

C26
A9
B19

PCI_PLTRST#
CLK_PCI_ICH
PCI_PME#

G8
F7
F8
G7

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

PLTRST#
PCICLK
PME#

Interrupt
PIRQA#
PIRQB#
PIRQC#
PIRQD#

I/F

GPIO2 / PIRQE#
GPIO3 / PIRQF#
GPIO4 / PIRQG#
GPIO5 / PIRQH#

MISC
RSVD[1]
RSVD[2]
RSVD[3]
RSVD[4]
RSVD[5]

RSVD[6]
RSVD[7]
RSVD[8]
RSVD[9]
MCH_SYNC#

Q45
RHU002N06_SOT323

+3VS
5

IDE_RESET# <19>
CPPE#
<15,32>

U56

PCI_RST#

PCI_RST# <19,24>

PCI_PCIRST#

<24>
<24>
<24>
<24>

@ TC7SH08FU_SSOP5

PCI_IRDY# <24>
PCI_PAR <24>

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

R1051
0_0402_5%
1

PCI_DEVSEL# <24>
PCI_PERR# <24>

+3VS

PCI_SERR# <24,30>
PCI_STOP# <24>
PCI_TRDY# <24>
PCI_FRAME# <24>

PCI_PLTRST#

U59
4

CLK_PCI_ICH <15>
PCI_PME#

PLT_RST#

PLT_RST# <7,16,19,20,22,24,30>

@ TC7SH08FU_SSOP5

PCI_PIRQE# <24>

R1057
0_0402_5%
1

PCI_PIRQG# <24>
2

AE9
AG8
AH8
F21
AH20

1
D7
E7
C16
D16
C17
D17
E13
F13
A13
A14
C8
D8

PCI_REQ4#
IDE_RESET#
CPPE#
ALS_EN#

REQ0#
GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#
GNT3#
REQ4# / GPIO22
GNT4# / GPIO48
GPIO1 / REQ5#
GPIO17 / GNT5#

PCI

+3VS

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

E18
C18
A16
F18
E16
A18
E17
A17
A15
C14
E14
D14
B12
C13
G15
G13
E12
C11
D11
A11
A10
F11
F10
E9
D9
B9
A8
A6
C7
B6
E6
D6

<17>

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

ALS_EN

<24> PCI_AD[0..31]

ALS_EN
D

ALS_EN# 2
G

U26B

1
0_0402_5%

ACCEL_INT <24>

R1388

MCH_ICH_SYNC#

<7>

Place closely pin A9

ICH7_BGA652~D

CLK_PCI_ICH
B

R1065

@10_0402_5%

C729
@ 8.2P_0402_50V

Boot BIOS destination

ALS_EN#

BIOS_SEL1 Short

LPC@
Open

SPI@

R1290
1K_0402_5%

The pad must be placed on PCB easily

contact space for BIOS team setting.
Compal Secret Data

Security Classification
2005/05/26

Issued Date

2006/07/26

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.

ICH7-M(1/4)
Document Number

Rev
1.0

LA-2952P
Sheet

Friday, April 28, 2006

1

18

of

47

PLT_RST_B# 2
13
1
R1036
0_0402_5%
LPC_AD[0..3] <24,28,29,30>

1
2
@ 10_0402_5%
@ 10P_0402_25V8K

2 R402

<25> AC97_SYNC_CODEC

33_0402_5% 2

1 R376

<31> AC97_RST#_MDC

33_0402_5% 1

2 R1315

AC97_BITCLK
AC97_SYNC

U1
R6

ACZ_BCLK
ACZ_SYNC

<25> AC97_RST#_CODEC

33_0402_5% 2

1 R1029

AC97_RST#

R5

ACZ_RST#

AC97_SDIN0
AC97_SDIN1

T2
T3
T1

ACZ_SDIN0
ACZ_SDIN1
ACZ_SDIN2

AC97_SDOUT

T4

ACZ_SDOUT

<25> AC97_SDOUT_CODEC

33_0402_5% 2

1 R367

<31> AC97_SDOUT_MDC

33_0402_5% 2

1 R405

SATA_LED#

+3VS

R88
10K_0402_5%
2

SATA_RXN0_C
SATA_RXP0_C
SATA_TXN0_C
SATA_TXP0_C

SATA_LED#
1
D16

2
CH751H-40_SC76

MB2_LED#

2
CH751H-40_SC76

D15

IDE_LED#

IDE_LED# <24>

R1256
1

SATALED#

AF3
AE3
AG2
AH2

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

AF7
AE7
AG6
AH6

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

IGNNE#
INIT3_3V#
INIT#
INTR

AG22
AG21
AF22
AF25

H_IGNNE#
FWH_INIT#
H_INIT#
H_INTR

RCIN#

AG23

KB_RST#

SMI#
NMI

AF23
AH24

H_SMI#
H_NMI

STPCLK#

AH22

SATARBIASN
SATARBIASP

R1263

1 R1033 PD_IORDY
1 R1034 PD_IRQ
PD_DACK#
PD_IOW#
PD_IOR#

R1240

AG16
AH16
AF16
AH15
AF15

IORDY
IDEIRQ
DDACK#
DIOW#
DIOR#

332K_0402_1%

H_PWRGOOD <4>
H_IGNNE# <4>
FWH_INIT#
H_INIT#
<4> +3VS +VCCP
H_INTR
<4>
1 10K_0402_5%
KB_RST# <30>
H_SMI#
H_NMI

DCS1#
DCS3#

AE16
AD16

PD_CS#1
PD_CS#3

<4>
<4>

R1030

H_STPCLK# <4>

+3VS

56_0402_5%

1
2
R1031 24.9_0402_1%

H_THERMTRIP# <4,7>

R72
4.7K_0402_5%

Place close to ICH7

MBAY_DET#
1

<20> MBAY_DET#
C628

AB15
AE14
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AB13
AC14
AF14
AH13
AH14
AC15

PD_D0
PD_D1
PD_D2
PD_D3
PD_D4
PD_D5
PD_D6
PD_D7
PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15

DDREQ

AE15

PD_DREQ

IDE

55
56
57
58

GND
GND
GND
GND

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54

JAE_WM2M054JKB
+5VS

C640

R93
1
D

2
G

MB_PWR

Q38
RHU002N06_SOT323

PD_IORDY
PD_DACK#
PD_IRQ
PD_A1
PD_A0
PD_A2
PD_CS#1
PD_CS#3
MB2_LED#

+5VS_MB
MBAY_DET#

R1032
0_0402_5%

+5VS_MB

8
7
6
5

10U_0805_10V4Z

<20>

PD_IOR#
PD_IOW#

1
2
3

R83
470K_0402_5%

Q92
AO4407_SO8

+5VS

ICH7_BGA652~D

ODD_RST#
PD_D8
PD_D7
PD_D9
PD_D6
PD_D10
PD_D5
PD_D11
PD_D4
PD_D12
PD_D3
PD_D13
PD_D2
PD_D14
PD_D1
PD_D15
PD_D0
PD_DREQ

1
C625

2
C624
10U_0805_10V4Z

2
0.1U_0402_16V4Z

2
220K_0402_5% 1C633
B

0.1U_0402_16V4Z
2

@ 332K_0402_1%

ICH_INTVRMEN
1

+5VS_MB

JP42
ACES_85205-0200

+3VL
+RTCVCC

JP45

+5VS_MB

3900P_0402_50V7K
SATA_TXP0
2

Near ICH7(U26) side.

SATA_RXN0_C

3900P_0402_50V7K
SATA_RXN0
2

3900P_0402_50V7K
SATA_RXP0
2

C958
SATA_RXP0_C

26
25

C957

GND
GND

100_0402_5%

1U_0603_10V4Z

3.3V
3.3V
3.3V
GND
GND
GND
5V
5V
5V
GND
Rsv
GND
12V
12V
12V

RTC_R 1
R976
DAN202U_SC70
2

RTC
2
1K_0402_5%

R98

W=20mils

Q39
RHU002N06_SOT323

+3VS

+5VS

2
C629
10U_0805_10V4Z

1
C630

1
C631
0.1U_0402_16V4Z

<7,16,18,20,22,24,30> PLT_RST#

U43B
SN74LVC08APW_TSSOP14

PLT_RST_B#

OCTEK_SAT-22DD1G

ZZZ

PCB-MB

Compal Secret Data

Security Classification
2005/05/26

Issued Date

2006/07/26

Deciphered Date

Title

Date:

ZZZ

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

0.1U_0402_16V4Z
2

Place close to JP37

PLT_RST_B# <24,28,29>

0.1U_0402_16V4Z

Near Device(JP45) side.

1
C627

0.1U_0402_16V4Z
2

100_0402_5%

2
G

1
C626

14

C956
SATA_TXP0_C

P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15

C665

SATA_RXN0
SATA_RXP0

SATA_TXN0_C

3900P_0402_50V7K
SATA_TXN0
2

1
1

D14

R133
SATA_TXP0
SATA_TXN0

C955

S1
S2
S3
S4
S5
S6
S7

boss
boss

SATA CONN

GND
RX+
RXGND
TXTX+
GND

24
23

@ 0_0402_5%

1
2

R1241

1 2

4.7K_0402_5% 2
8.2K_0402_5% 2

PD_A0
PD_A1
PD_A2

H_DPRSTP# <4,42>
H_DPSLP# <4>
+VCCP

+3VS

+RTCVCC

1 0_0402_5%
1 0_0402_5%
1 56_0402_5%
H_FERR# <4>

R1244 2

DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15

SATA_CLKN
SATA_CLKP

AH10
AG10

AH17
AE17
AF17

+3VS

T86

PAD

2
1 H_STPCLK#
R1408
0_0402_5%
THRMTRIP_ICH#
AF26

DA0
DA1
DA2

<28>

0.1U_0402_16V4Z

24.9_0402_1%
+3VALW

H_PWRGOOD

THERMTRIP#

AF18

CLK_PCIE_SATA# AF1
CLK_PCIE_SATA AE1

<15> CLK_PCIE_SATA#
<15> CLK_PCIE_SATA

AG24

SATA

R90
10K_0402_5%

GPIO49 / CPUPWRGD

AC-97/AZALIA

33_0402_5% 1

FERR#

AG26

LAN_TXD0
LAN_TXD1
LAN_TXD2

1
@ 0_0402_5%

1 R1243 10K_0402_5%
GATEA20 <30>
H_A20M# <4>

DPRSLP# R1025 2
DPSLP#
R1035 2
R1027 2
H_FERR#

U7
V6
V7

<31> AC97_SYNC_MDC

GATEA20
H_A20M#
H_CPUSLP_R#

LAN_RXD0
LAN_RXD1
LAN_RXD2

<25> AC97_BITCLK_CODEC

AE22
AH28

LPC_FRAME# <24,28,29,30>

AF24
AH25

U5
V4
T5

2 R371

A20GATE
A20M#

LPC_DRQ#0
T88
PAD

AG27

LAN_RSTSYNC

2 R1314

LPC_FRAME#

CPUSLP#

LAN_CLK

33_0402_5% 1

AB3

TP1 / DPRSTP#
TP2 / DPSLP#

V3
U3

33_0402_5% 1

<25> AC97_SDIN0
<31> AC97_SDIN1
+5VS

EE_CS
EE_SHCLK
EE_DOUT
EE_DIN

<31> AC97_BITCLK_MDC

LFRAME#

R1037

R1028

LPC_DRQ#0

<18,24> PCI_RST#

U43D
SN74LVC08APW_TSSOP14

C721
2
1

LDRQ0#
LDRQ1# / GPIO23

AC3
AA5

LAN

W1
Y1
Y2
W3

C287
1U_0603_10V4Z
1
2

INTVRMEN
INTRUDER#

1
2
1M_0402_5%

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54

1 ODD_RST#
33_0402_5%

+RTCVCC

NO SHORT PADS

AA6
AB5
AC4
Y6

11

CMOS_CLR1
1
2

ICH_INTVRMENW4
SM_INTRUDER#Y5

RTCRST#

R301
2

R1026

LAD0
LAD1
LAD2
LAD3

JP5

0.1U_0402_16V4Z

ICH_RTCRST# AA3

RTXC1
RTCX2

LPC

1
R230 1
20K_0402_5%

+RTCVCC

AB1
AB2

ICH_RTCX2

RTC

C528
2
15P_0402_50V8J

CPU

32.768KHZ_12.5P_MC-146

U26A

10M_0402_5%

12

1
4

Y4

14

<18> IDE_RESET#
R432

Multi Bay II connector

C641

ICH_RTCX1

2
15P_0402_50V8J

+3VS

C516
1

Audio-wire

Compal Electronics, Inc.

ICH7-M(2/4)
Document Number

Rev
1.0

LA-2952P
Sheet

Friday, April 28, 2006

1

19

of

47

HDD_HALTLED# <24>

HDD_HALTLED

C22
B22
A26
B25
A25

SMBCLK
SMBDATA
LINKALERT#
SMLINK0
SMLINK1

ICH_RI#

A28

RI#

SB_SPKR
LPC_PD#
XDP_DBRESET#

A19
A27
A22

SPKR
SUS_STAT#
SYS_RST#

1
@ 2.2K_0402_5%
Q23
@ RHU002N06_SOT323

@ 2.2K_0402_5%

ICH_SMB_DATA

1
D

ICH_SMBCLK

3
2

<4,43>

Q24
@ RHU002N06_SOT323

OCP#

OCP#

+5VS
<24> WXMIT_OFF#
PAD T94
PAD T90

+3VS
R532
1K_0402_5%
1
2

@ 10K_0402_5%
R993 1
2 THERM_SCI#
+3VALW

10K_0402_5%
R994 1
2 SIRQ

FWH_WP#
FWH_TBL#

+3VALW

10K_0402_5%
R1004 1
2 LINKALERT#

<22>

10K_0402_5%
R1005 1
2 XDP_DBRESET#

<7,42> VGATE_INTEL

10K_0402_5%
R1006 1
2 OCP#

<7,30>

PM_POK

+3VS
1

R1007

R1374

R1373

2 @ 0_0402_5%

0_0402_5%

LP_EN#

PREP# 1

CH751H-40_SC76

ISO_PREP#

A21

GPIO26

B21
E23

GPIO27
GPIO28

AG18
AC19
U2

WAKE#
SERIRQ
THRM#

RUNSCI_EC#
ISO_PREP#
10K_0402_5%

AC21
AC18
E21

GPIO6
GPIO7
GPIO8

R998

@ 10_0402_5%

@ 10_0402_5%

SUSCLK

C20

ICH_SUSCLK

B24
D23
F22

SLP_S3#
SLP_S4#
SLP_S5#

PWROK

AA4

PM_POK

AC22

DPRSLPVR

TP0 / BATLOW#

C21

ICH_LOW_BAT#

PWRBTN#

C23

ON/OFFBTN#

LAN_RST#

C19

RSMRST#

Y4

GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO24
GPIO25
GPIO35 / SATAREQ#
GPIO38
GPIO39

SLP_S3#
SLP_S4#
SLP_S5#

<22,24,25,26,30,32,33,40,41>
<41>
<33,41>

F26
F25
E28
E27

PERn1
PERp1
PETn1
PETp1

<24>
<24>
<24>
<24>

PCIE_RXN2
PCIE_RXP2
PCIE_TXN2
PCIE_TXP2

0.1U_0402_16V4Z 2
0.1U_0402_16V4Z 2

1 C710
1 C711

PCIE_RXN2
PCIE_RXP2
PCIE_C_TXN2
PCIE_C_TXP2

H26
H25
G28
G27

PERn2
PERp2
PETn2
PETp2

K26
K25
J28
J27

PERn3
PERp3
PETn3
PETp3

0.1U_0402_16V4Z 2
0.1U_0402_16V4Z 2

1 C952
1 C953

PCIE_RXN4
PCIE_RXP4
PCIE_C_TXN4
PCIE_C_TXP4

R1292/R1293 should be placed

less than 100 mils from U26.

SPI_SI
SPI_SO

SPI_CLK
SPI_CS#
SPI_SI
SPI_SO

R1292 1

47_0402_5%
2

R1293 1

47_0402_5%
2

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7

1
R1284

2SPI_CS#
10K_0402_5%

1
R1285

2 SPI_SI
10K_0402_5%

1
R1286

2 SPI_SO
10K_0402_5%

M26
M25
L28
L27

PERn4
PERp4
PETn4
PETp4

P26
P25
N28
N27

PERn5
PERp5
PETn5
PETp5

T25
T24
R28
R27

PERn6
PERp6
PETn6
PETp6

R2
P6
P1

SPI_CLK
SPI_CS#
SPI_ARB

P5
P2

SPI_MOSI
SPI_MISO

D3
C4
D5
D4
E5
C3
A2
B3

OC0#
OC1#
OC2#
OC3#
OC4#
OC5# / GPIO29
OC6# / GPIO30
OC7# / GPIO31

LOW_BAT# <30>

CH751H-40_SC76

ON/OFFBTN# <31>

R1013
10K_0402_5%
2
1

PLT_RST# <7,16,18,19,22,24,30>
PM_RSMRST# <30>

+3VL

DPRSLPVR 2

1
R1015
@ 100K_0402_5%

T89 PAD

CB_IN#
LID_SW#
LANLINK_STATUS#
XMIT_OFF
GPIO25
NPCI_RST#

MBAY_DET# <19>
LID_SW# <17,31>
LANLINK_STATUS# <22,23,32>
T80 PAD
XMIT_OFF <24>

1
R1386

NPCI_RST# <28>
2
@ 0_0402_5%

2
1
R1017 @ 0_0402_5%

LOM_LOW_PWR <22>

J28
2

CABLE_DETECT <22,23>

PAD-SHORT 2x2m

DOCK_ID <32>

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP

V26
V25
U28
U27

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP

Y26
Y25
W28
W27

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP

AB26
AB25
AA28
AA27

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP

AD25
AD24
AC28
AC27

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

DMI_CLKN
DMI_CLKP

AE28
AE27

CLK_PCIE_ICH#
CLK_PCIE_ICH

C25
D25

DMI_IRCOMP

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P

F1
F2
G4
G3
H1
H2
J4
J3
K1
K2
L4
L5
M1
M2
N4
N3

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7

USBRBIAS#
USBRBIAS

D2
D1

USBRBIAS

DMI_ZCOMP
DMI_IRCOMP

USB

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

<7>
<7>
<7>
<7>

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

<7>
<7>
<7>
<7>

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

<7>
<7>
<7>
<7>

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

<7>
<7>
<7>
<7>

GPIO25

R1395 1

R1284,R1285 and R1286 should

be placed close to U26.

2005/05/26

Issued Date

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7

BT_OFF

<27>

Within 500 mils

+1.5VS

RP64
USB_OC#3
USB_OC#0
USB_OC#1
USB_OC#2

<27>
<27>
<24>
<24>
<29>
<29>
<27>
<27>
<27>
<27>
<27>
<27>
<32>
<32>
<32>
<32>

R1019 22.6_0402_1%
1
2

Within 500 mils

2006/07/26

Deciphered Date

Title

Date:

4
3
2
1

5
6
7
8

+3VALW

10K_1206_8P4R_5%

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

0_0402_5%

CLK_PCIE_ICH# <15>
CLK_PCIE_ICH <15>
R1016 24.9_0402_1%
1
2

Compal Secret Data

Security Classification

USB_OC#4

R1018
10K_0402_5%
1
2

USB_OC#5

R1261
10K_0402_5%
1
2

USB_OC#6

R1020
10K_0402_5%
1
2

USB_OC#7

R1237
10K_0402_5%
1
2

ICH7_BGA652~D

+3VALW

D58

PAD

SPI

SPI_CLK
SPI_CS#

+3VALW

@ 4.7P_0402_50V8C

R1015 need be removed when ICH7M ES2 samples used,

but need be stuffed when ICH7M ES1 samples used.
PCIE_RXN1
PCIE_RXP1
PCIE_C_TXN1
PCIE_C_TXP1

R1011
8.2K_0402_5%
2
1

R1010
PM_POK <7,30>
1
2 10K_0402_5%
DPRSLPVR <7,42>

PLT_RST#

T91

T67 PAD

PM_RSMRST#
R1014 10K_0402_5%
1
2

E20
A20
F19
E19
R4
E22
R3
D20
AD21
AD20
AE20

@ 4.7P_0402_50V8C

CLK_14M_ICH <15>
CLK_48M_ICH <15>

SLP_S3#
SLP_S4#
SLP_S5#

GPIO16 / DPRSLPVR

C707
D

2
100_0402_5%

CLK_14M_ICH
CLK_48M_ICH

C706

U26D
1 C708
1 C709

<29>
<29>

1
R1002

PWROK_ICH7

0.1U_0402_16V4Z 2
0.1U_0402_16V4Z 2

<29>
<29>

AC1
B2

MB_PWR <19>

HDD_HALTLED

ICH7_BGA652~D

PCIE_RXN1
PCIE_RXP1
PCIE_TXN1
PCIE_TXP1

PCIE_RXN4
PCIE_RXP4
PCIE_TXN4
PCIE_TXP4

GPIO

LP_EN#

<22>
<22>
<22>
<22>

<32>
<32>
<32>
<32>

CLK14
CLK48

AF19
AH18
AH19
AE19

GPIO33 / AZ_DOCK_EN#
GPIO34 / AZ_DOCK_RST#

VRMPWRGD

R997

GPIO32 / CLKRUN#

AD22

10K_0402_5%

D57

GPIO18 / STPPCI#
GPIO20 / STPCPU#

PWROK_ICH7

R1008

10K_0402_5%

AC20
AF21

PCI-EXPRESS

V_3P3_LAN
1

10K_0402_5%
R1009 1
2 LID_SW#

<23,25,32> PREP#

<30> RUNSCI_EC#
<32> ISO_PREP#
R1322 1

GPIO21 / SATA0GP
GPIO19 / SATA1GP
GPIO36 / SATA2GP
GPIO37 / SATA3GP

GPIO11 / SMBALERT#

ICH_PCIE_WAKE# F20
SIRQ
AH21
THERM_SCI#
AF20

<24,28,29,30> SIRQ
<4> THERM_SCI#

+3VALW

FWH_WP#
FWH_TBL#

<22,24> ICH_PCIE_WAKE#

8.2K_0402_5%
R999 1
2 PM_CLKRUN#

PM_CLKRUN#

<24,28,29,30> PM_CLKRUN#

GPIO0 / BM_BUSY#

B23

H_STP_PCI#
H_STP_CPU#

<15> H_STP_PCI#
<15> H_STP_CPU#

AB18

GPIO

PM_BMBUSY#

<7> PM_BMBUSY#

ICH_SMB_CLK

<4,13,14,15,22,24> ICH_SMBCLK

<25>
SB_SPKR
<29,30> LPC_PD#
<4> XDP_DBRESET#

SYS

ICH_SMBDATA

<4,13,14,15,22,24> ICH_SMBDATA

R1003
1
2
8.2K_0402_5%

R204

DIRECT MEDIA INTERFACE

+3VALW
R206

ICH_SMB_CLK
ICH_SMB_DATA
LINKALERT#
ICH_SMLINK0
ICH_SMLINK1

SATA
GPIO

2 0_0402_5%
2 0_0402_5%

Clocks

R1320

SMB

+3VS

1
1

POWER MGT

ICH_SMBCLK
ICH_SMBDATA

CLK_14M_ICH

U26C

2.2K_0402_5%
2

2.2K_0402_5%
R1319

10K_0402_5%

Q43
RHU002N06_SOT323

2
G

R1437
100K_0402_5%

R213,R233 change from 2.2Kohm to

10Kohm when Q23,Q24,R206,R204 stuffed.

R233

R1001

10K_0402_5%
D

1
2

2
R1000

R213

Place closely pin AC1

CLK_48M_ICH
1

+3VALW

+3VALW

Place closely pin B2

Compal Electronics, Inc.

ICH7-M(3/4)
Document Number

Rev
1.0

LA-2952P
Sheet

Friday, April 28, 2006

1

20

of

47

+VCCP
U26F

F6

+3VS
2

R989

C570
150U_D_6.3VM

+5VS
1

0.1U_0402_16V4Z

D55

1
+

C672

C673

2
0.1U_0402_16V4Z

CH751H-40_SC76

C674

2
0.1U_0402_16V4Z

100_0402_5%

AA22
AA23
AB22
AB23
AC23
AC24
AC25
AC26
AD26
AD27
AD28
D26
D27
D28
E24
E25
E26
F23
F24
G22
G23
H22
H23
J22
J23
K22
K23
L22
L23
M22
M23
N22
N23
P22
P23
R22
R23
R24
R25
R26
T22
T23
T26
T27
T28
U22
U23
V22
V23
W22
W23
Y22
Y23

ICH_V5REF_RUN
1

C676
0.1U_0402_16V4Z

Place closely pin

D28,T28,AD28.

C677
0.1U_0402_16V4Z

+5VALW +3VALW

R990

D56

CH751H-40_SC76
2

10_0402_5%

ICH_V5REF_SUS
C684
0.1U_0402_16V4Z

+3VS

C688
0.1U_0402_16V4Z

Place closely pin AG28 within 100mlis.

+1.5VS_DMIPLLR

+1.5VS_DMIPLL

B27

0.5_0805_1%

2
0_0805_5%

C698

+1.5VS
1

+3VALW
C702
0.1U_0402_16V4Z

0.1U_0402_16V4Z

C694
0.01U_0402_16V7K

R992
2

AG28

+1.5VS

C697
0.1U_0402_16V4Z

Place closely pin AG5.

+3VS
1

+1.5VS
C700
1U_0603_10V4Z

+1.5VS
C703
0.1U_0402_16V4Z

1
T84
T85

PAD
PAD

ICH_AA2
ICH_Y7

Vcc3_3 / VccHDA

U6

VccSus3_3/VccSusHDA

R7

Vcc3_3[1]
VccDMIPLL

AD2

VccSATAPLL

AH11

Vcc3_3[2]

AB10
AB9
AC10
AD10
AE10
AF10
AF9
AG9
AH9

Vcc1_5_A[10]
Vcc1_5_A[11]
Vcc1_5_A[12]
Vcc1_5_A[13]
Vcc1_5_A[14]
Vcc1_5_A[15]
Vcc1_5_A[16]
Vcc1_5_A[17]
Vcc1_5_A[18]

E3

VccSus3_3[19]

C1

VccUSBPLL

V5
V1
W2
W7

+3VALW

Vcc1_5_B[1]
Vcc1_5_B[2]
Vcc1_5_B[3]
Vcc1_5_B[4]
Vcc1_5_B[5]
Vcc1_5_B[6]
Vcc1_5_B[7]
Vcc1_5_B[8]
Vcc1_5_B[9]
Vcc1_5_B[10]
Vcc1_5_B[11]
Vcc1_5_B[12]
Vcc1_5_B[13]
Vcc1_5_B[14]
Vcc1_5_B[15]
Vcc1_5_B[16]
Vcc1_5_B[17]
Vcc1_5_B[18]
Vcc1_5_B[19]
Vcc1_5_B[20]
Vcc1_5_B[21]
Vcc1_5_B[22]
Vcc1_5_B[23]
Vcc1_5_B[24]
Vcc1_5_B[25]
Vcc1_5_B[26]
Vcc1_5_B[27]
Vcc1_5_B[28]
Vcc1_5_B[29]
Vcc1_5_B[30]
Vcc1_5_B[31]
Vcc1_5_B[32]
Vcc1_5_B[33]
Vcc1_5_B[34]
Vcc1_5_B[35]
Vcc1_5_B[36]
Vcc1_5_B[37]
Vcc1_5_B[38]
Vcc1_5_B[39]
Vcc1_5_B[40]
Vcc1_5_B[41]
Vcc1_5_B[42]
Vcc1_5_B[43]
Vcc1_5_B[44]
Vcc1_5_B[45]
Vcc1_5_B[46]
Vcc1_5_B[47]
Vcc1_5_B[48]
Vcc1_5_B[49]
Vcc1_5_B[50]
Vcc1_5_B[51]
Vcc1_5_B[52]
Vcc1_5_B[53]

Vcc1_5_A[1]
Vcc1_5_A[2]
Vcc1_5_A[3]
Vcc1_5_A[4]
Vcc1_5_A[5]
Vcc1_5_A[6]
Vcc1_5_A[7]
Vcc1_5_A[8]
Vcc1_5_A[9]

AA2
Y7

V5REF_Sus

AB7
AC6
AC7
AD6
AE6
AF5
AF6
AG5
AH5

Place closely pin AG9.

+1.5VS_DMIPLL

C699
0.1U_0402_16V4Z

R991
1

C693
10U_0805_10V4Z

+1.5VS

V5REF[2]

VccSus1_05/VccLAN1_05[1]
VccSus1_05/VccLAN1_05[2]

1
C974

Vcc3_3[12]
Vcc3_3[13]
Vcc3_3[14]
Vcc3_3[15]
Vcc3_3[16]
Vcc3_3[17]
Vcc3_3[18]
Vcc3_3[19]
Vcc3_3[20]
Vcc3_3[21]

A5
B13
B16
B7
C10
D15
F9
G11
G12
G16

VccSus3_3[2]
VccSus3_3[3]
VccSus3_3[4]
VccSus3_3[5]
VccSus3_3[6]

A24
C24
D19
D22
G19

VccSus3_3[7]
VccSus3_3[8]
VccSus3_3[9]
VccSus3_3[10]
VccSus3_3[11]
VccSus3_3[12]
VccSus3_3[13]
VccSus3_3[14]
VccSus3_3[15]
VccSus3_3[16]
VccSus3_3[17]
VccSus3_3[18]

K3
K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7

2
C670

C979
@ 330U_D2E_2.5VM_R9

220U_D2_2VM_R9

+VCCP
C679
1
2

C678
0.1U_0402_16V4Z

0.1U_0402_16V4Z
1
2

+3VS
1

C680
0.1U_0402_16V4Z
1
2

C681
0.1U_0402_16V4Z

C682
4.7U_0805_10V4Z

+3VS

+RTCVCC
1

Vcc1_5_A[19]
Vcc1_5_A[20]

AB17
AC17

Vcc1_5_A[21]
Vcc1_5_A[22]
Vcc1_5_A[23]

T7
F17
G17

Vcc1_5_A[24]
Vcc1_5_A[25]

AB8
AC8

C689
0.1U_0402_16V4Z

C695
0.1U_0402_16V4Z

+3VALW
C690
0.1U_0402_16V4Z

+3VALW
C696
0.1U_0402_16V4Z

+1.5VS

VccSus1_05[1]

K7

C701 0.1U_0402_16V4Z
ICH_K7
PAD

T81

VccSus1_05[2]
VccSus1_05[3]

C28
G20

ICH_C28
ICH_G20

T82
T83

Vcc1_5_A[26]
Vcc1_5_A[27]
Vcc1_5_A[28]
Vcc1_5_A[29]
Vcc1_5_A[30]

+3VS

AA7
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG19

P7

+3VS

Vcc3_3[3]
Vcc3_3[4]
Vcc3_3[5]
Vcc3_3[6]
Vcc3_3[7]
Vcc3_3[8]
Vcc3_3[9]
Vcc3_3[10]
Vcc3_3[11]

W5

1U_0603_10V4Z

AE23
AE26
AH26

VccRTC

C975

V_CPU_IO[1]
V_CPU_IO[2]
V_CPU_IO[3]

VccSus3_3[1]

C692
0.1U_0402_16V4Z

ICH_V5REF_SUS

0.1U_0402_16V4Z

L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

C691
0.1U_0402_16V4Z

+1.5VS
D

Vcc1_05[1]
Vcc1_05[2]
Vcc1_05[3]
Vcc1_05[4]
Vcc1_05[5]
Vcc1_05[6]
Vcc1_05[7]
Vcc1_05[8]
Vcc1_05[9]
Vcc1_05[10]
Vcc1_05[11]
Vcc1_05[12]
Vcc1_05[13]
Vcc1_05[14]
Vcc1_05[15]
Vcc1_05[16]
Vcc1_05[17]
Vcc1_05[18]
Vcc1_05[19]
Vcc1_05[20]

C687
0.1U_0402_16V4Z

AD17

U26E

V5REF[1]

C686
0.1U_0402_16V4Z

G10

C685
0.1U_0402_16V4Z

ICH_V5REF_RUN

A1
H6
H7
J6
J7

PAD
PAD
+1.5VS
1

C704
0.1U_0402_16V4Z

VccSus3_3/VccLAN3_3[1]
VccSus3_3/VccLAN3_3[2]
VccSus3_3/VccLAN3_3[3]
VccSus3_3/VccLAN3_3[4]

A4
A23
B1
B8
B11
B14
B17
B20
B26
B28
C2
C6
C27
D10
D13
D18
D21
D24
E1
E2
E4
E8
E15
F3
F4
F5
F12
F27
F28
G1
G2
G5
G6
G9
G14
G18
G21
G24
G25
G26
H3
H4
H5
H24
H27
H28
J1
J2
J5
J24
J25
J26
K24
K27
K28
L13
L15
L24
L25
L26
M3
M4
M5
M12
M13
M14
M15
M16
M17
M24
M27
M28
N1
N2
N5
N6
N11
N12
N13
N14
N15
N16
N17
N18
N24
N25
N26
P3
P4
P12
P13
P14
P15
P16
P17
P24
P27

VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]

VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]

P28
R1
R11
R12
R13
R14
R15
R16
R17
R18
T6
T12
T13
T14
T15
T16
T17
U4
U12
U13
U14
U15
U16
U17
U24
U25
U26
V2
V13
V15
V24
V27
V28
W6
W24
W25
W26
Y3
Y24
Y27
Y28
AA1
AA24
AA25
AA26
AB4
AB6
AB11
AB14
AB16
AB19
AB21
AB24
AB27
AB28
AC2
AC5
AC9
AC11
AD1
AD3
AD4
AD7
AD8
AD11
AD15
AD19
AD23
AE2
AE4
AE8
AE11
AE13
AE18
AE21
AE24
AE25
AF2
AF4
AF8
AF11
AF27
AF28
AG1
AG3
AG7
AG11
AG14
AG17
AG20
AG25
AH1
AH3
AH7
AH12
AH23
AH27

ICH7_BGA652~D

ICH7_BGA652~D
C705

0.1U_0402_16V4Z

Compal Secret Data

Security Classification
2005/05/26

Issued Date

2006/07/26

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.

ICH7-M(4/4)
Document Number

Rev
1.0

LA-2952P
Sheet

Friday, April 28, 2006

1

21

of

47

J7 1

4.7K_0402_5%
Q29
RHU002N06_SOT323

L13
K12
K13

REGOUT25

N13

V_2P5_LAN

REGSUP25

M13

V_3P3_LAN

PCIE_TXDN

N4

PCIE_TXDP

M4

PCIE_RXDN

M8

PCIE_RXDP

N8

WAKE#
REFCLKREFCLK+
REFCLK_SEL

B5
M6
N6
C4

LINKLED#
SPD100LED#
SPD1000LED#
TRAFFICLED#

PCIE_TST
PERST#

PCIE_RXN1 <20>

PCIE_RXP1 <20>

D7
C2

PLT_RST_LAN#

CLK_PCIE_LOM# <15>
CLK_PCIE_LOM <15>

R71

2
4.7K_0402_5%

4.7U_0805_10V4Z

Q104
@ AO7407_SOT323

0_0402_5%
R1088
1
2

0_0402_5%

1
2
R1090
@ 0_0402_5%

0.1U_0402_16V4Z

+3VS

1.21K_0402_1%

NIC_PD#

V_3P3_LAN

4
1

O
NC

+3VS

R540

2
O
NC

4
1

2
R1094

1
0_0402_5%

CLKREQA# <15>
<20,23> CABLE_DETECT

SN74LVC1G17DBVR_SOT23-5
U55

C578

1
10K_0402_5%

R507

CABLE_DETECT

0.1U_0402_16V4Z
R1403
@ 2.2K_0402_5%

0.1U_0402_16V4Z

R506

0.1U_0402_16V4Z

2
C1058

C576

2
D

@ 0_0402_5%

2
R1024 2

100K_0402_5%

2
1
1
121K_0402_1%
R1023

10K_0402_5%

NIC_PD_N 2
0_0402_5%

100U_B2_6.3VM

+3VALW

R1022
0_0402_5%
5 1

1N4148_SOD80
2

R503
I

+3VS

D63
1

+ C976

R34
1K_0402_5%
2
1

R35
1K_0402_5%
2
1

5751_GPIO1
5751_EECLK
5751_EEDAT

LP_EN#
2
G
Q54
RHU002N06_SOT323

LP_EN#

<20>

Q96 @ RHU002N06_SOT323
Q93
D

ICH_SMBDATA

0.1U_0402_16V4Z

U36
LOM_LOW_PWR

<20> LOM_LOW_PWR

R1021
@ 0_0402_5%

0.1U_0402_16V4Z

Place close U6 pin N13

C580
1
2

Q105
RHU002N06_SOT323

2
G

R1392
@ 2.2K_0402_5%

C83

C243
@10U_0805_10V4Z

NIC_PD

V_3P3_LAN
R16
1K_0402_5%
2
1

Layout Notice : No high

speed signal should be
routed near RDAC or on
adjacent layer to RDAC

+3VS

1
C74

V_3P3_LAN

R1085
10K_0402_5%

B9

R70

AT24C64AN-10SU-2.7_SO8

V_2P5_LAN

8
7
6
5

Place close U6 pin M13

R1082
1
2
100K_0402_5%

1 2

RDAC

2
R1091

VCC
WP
SCL
SDA

C348

ICH_PCIE_WAKE# <20,24>

2
G

R1089

A0
A1
NC
GND

VAUX_1.2_CTL

@ SN74LVC1G17DBVR_SOT23-5

U4

C228
10U_0805_10V4Z

V_3P3_LAN

C9

1
2
3
4

1
0.1U_0402_16V4Z

NIC_PD_N

C6
G4
C5
F4
E5

BCM5753MKFBG P3_FPBGA196~D

27P_0402_50V8J

0.1U_0402_16V4Z

PCIE_TXP1 <20>
LOM_PCIE_WAKE#
CLK_PCIE_LOM#
CLK_PCIE_LOM
2
1
V_3P3_LAN
R36 4.7K_0402_5%

XTALI

V_3P3_LAN
2

1
@ 0_0402_5%

27P_0402_50V8J

XTALO

Bias

M10

25MHZ_20P_1BG25000CK1A
2
2
C16
C19
1

Q103
AO7407_SOT323

PCIE_TXN1 <20>

N10

XTALI

C68

0.1U_0402_16V4Z

2
G

V_3P3_LAN
XTALO

1
4.7U_0805_10V4Z

PCIE_C_RXN1
C17 1
0.1U_0402_16V4Z
PCIE_C_RXP1
C18 1
0.1U_0402_16V4Z

1
200_0402_1%

Clock

2
R14
Y1

C55

NIC_PD

TEST

TCK
TDI
TDO
TMS
TRST#

V_1P2_LAN

B10
C10
B11
C9

2
C347

2
G

SLP_S3#

REGSUP12
VAUX_1.2_CTL

REGSUP12
REGCTL12
REGSEN12

V_1P2_LAN
BCP69_SOT223
Q13
4
3
2

<20,24,25,26,30,32,33,40,41>

LED

LAN_ACT#

<23,32> LAN_ACT#

Must having maximized

copper under pin 2 & 4 of Q13

L
REGSUP12

Q30
RHU002N06_SOT323

2
G

LANLINK_STATUS#

<20,23,32> LANLINK_STATUS#

LP_EN#
2
G
Q94
RHU002N06_SOT323

PLT_RST_LAN#

<30,37,38,39,43> ADP_PRES

LOM_LOW_PWR 1

J5

LOW_PWR

CS#

PCI-E

2
4.7K_0402_5%

R73

V_3P3_LAN

SCLK

PWR_IND#
ATTN_IND#
ATTN_BTTN#

Q40
AO7407_SOT323
R1397

@ 0_0402_5%

R1076

Hot Plug
Support

H2
J2
B3

NIC_PD <23>

LOM_PCIE_WAKE#
V_3P3_LAN

<23>
<23>
<23>
<23>
<23>
<23>
<23>
<23>

Media

LAN_TX3+
LAN_TX3LAN_TX2+
LAN_TX2LAN_TX1+
LAN_TX1LAN_TX0+
LAN_TX0-

D11

SI
SO

TRD3+
TRD3TRD2+
TRD2TRD1+
TRD1TRD0+
TRD0-

LAN_TX3+
LAN_TX3LAN_TX2+
LAN_TX2LAN_TX1+
LAN_TX1LAN_TX0+
LAN_TX0-

C12
C13
D12
D13
E12
E13
F12
F13

F11
E10
D10

EECLK
EEDATA

Misc

H10
J11

SMB_CLK
SMB_DATA

R268 2
1
47K_0402_5%

5751_EECLK
5751_EEDAT

GPIO0_TST_CLKOUT
GPIO1

220K_0402_5%

Power
Control

ICH_LAN_SMBCLK D9
ICH_LAN_SMBDATA D8

@ 0_0402_5%

Regulator
Control

J10
J12

1 10K_0402_5%
5751_GPIO1

R277

4.7K_0402_5%

R1419

R1420

BCM5753

V_3P3_LAN

ICH_SMBCLK <4,13,14,15,20,24>
ICH_SMBDATA <4,13,14,15,20,24>

U7A
D

1
C324
4.7U_0805_10V4Z

1
2 @ 0_0402_5% ICH_SMBCLK
2 @ 0_0402_5% ICH_SMBDATA

ICH_LAN_SMBCLK R1396 1
ICH_LAN_SMBDATA R1398 1

2 1K_0402_5%
2 1K_0402_5%

R275 1
R289 1

3
Q31
SI2301BDS_SOT23
R267

V_3P3_LAN

Layout Notice : Place as close

chip as possible.

PAD-NO SHORT 2x2m

+3VALW

C44
0.1U_0402_16V4Z

<7,16,18,19,20,24,30> PLT_RST#

C32
0.1U_0402_16V4Z

C39
0.1U_0402_16V4Z

C41
0.1U_0402_16V4Z

ICH_SMBCLK

@ RHU002N06_SOT323
ICH_LAN_SMBDATA

CKT Notice : CABLE IN, CABLE_DETECT=0

CABLE OUT, CABLE_DETECT=1

ICH_LAN_SMBCLK

Compal Secret Data

Security Classification
+5VS

2005/05/26

Issued Date

2006/07/26

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.

BCM5751M
Document Number

Rev
1.0

LA-2952P
Sheet

Friday, April 28, 2006

1

22

of

47

TD4-

MX4-

13

MDO0-

LAN_TX0+ 11

TD4+

MX4+

14

MDO0+
MCT0
MDO1-

RJ-45 CONN.

T66
LAN_TX0- 12

Layout Notice : 1.2V filter. Place as close

chip as possible.

V_2P5_LAN

TD21+

MX2+

20

TCT2

MCT2

21

LAN_TX3-

TD1-

MX1-

22

TCT1

1:1

TD1+

TRM_CT

MX1+

23

MCT1

24

2 C56

0.1U_0402_16V4Z 1

2 C54

0.1U_0402_16V4Z 1

2 C50

0.1U_0402_16V4Z 1

2 C49

49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%

2
2
2
2
2
2
2
2

2 R271
1
75_0402_1%

V_1P2_LAN

MDO3-

C320
1
2

2 R272
1
75_0402_1%

LAN_TX0LAN_TX0+
LAN_TX1LAN_TX1+
LAN_TX2LAN_TX2+
LAN_TX3LAN_TX3+

LAN_TX0LAN_TX0+
LAN_TX1LAN_TX1+
LAN_TX2LAN_TX2+
LAN_TX3LAN_TX3+

<22>
<22>
<22>
<22>
<22>
<22>
<22>
<22>

V_3P3_LAN

B6
H4
M12
J13
C7
H12
L5

VDDP_0
VDDP_1
VDDP_2
XTALVDD
VAUXPRSNT
VMAINPRSNT
PCIE_SDSVDD

A1
A4
A5
A7
A9
B2
B7
B8
C8
D1
D2
D4
D5
E1
E2
E4
F2
F3
G1
G3
H1
H3
J3
J4
K1
K2
K11
L1
L2
L3
L4
L8
L9
L11
M1
M5
M9
N2
N3
N9
P1
P2

NC_0
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25
NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41

AVDD1
AVDD2

G11
G12
B12
G13

AVDDL_0
AVDDL_1
AVDD_0
AVDD_1

PCIE_PLLVDD
GPHY_PLLVDD

L7
H13

PCIE_PLLVDD
GPHY_PLLVDD

XTALVDD
C35

0.1U_0402_16V4Z

2
1
0_0603_5%

1
V_3P3_LAN XTALVDD V_2P5_LAN

AVDD1
C60

0.1U_0402_16V4Z
R987
2
1
0_0603_5%

1K_0402_5% 1 R276

LAN_AUXPWR
VMAINPRSNT

AVDD2
C46

0.1U_0402_16V4Z

2
PCIE_SDS_VDD
1

V_1P2_LAN
L33
2
1
BLM11A601S_0603
2
C342

JP4

<32>

MDO3+

<32>

MDO1-

<32>

MDO2-

<32>

MDO2+

<32>

MDO1+

<32>

MDO0-

<32>
V_3P3_LAN_LED

MDO0+
R265 2

<20,22,32> LANLINK_STATUS#

14

Yellow LED-

MDO3-

SHLD1
PR4DETECT PIN1

MDO3+

PR4+

MDO1-

PR2-

MDO2-

PR3-

MDO2+

PR3+

MDO1+

PR2+

MDO0-

PR1-

MDO0+

1 300_0402_5%

11

LANLINK_STATUS#

12

4.7U_0805_10V4Z

16
9

CABLE_DETECT <20,22>

2
1
BLM11A601S_0603
2
C331

DETCET PIN2

10

SHLD1

15

PR1+

GPHY_PLLVDD

0.1U_0402_16V4Z

R284

C332

4.7U_0805_10V4Z

0.1U_0402_16V4Z
T59
PCIE_PLLVDD

PAD

C326
0.1U_0402_16V4Z

T59 , T60 place together

V_3P3_LAN

L29
2
1
BLM11A601S_0603
1
C322

Green LED-

V_3P3_LAN

@ 4.7K_0402_5%

4.7U_0805_10V4Z

FOX_JM36113-P1122-7F

0.1U_0402_16V4Z

C579

L30
2
1
BLM11A601S_0603
2
C323

Green LED+

C339

L32

4.7U_0805_10V4Z
2

AVDDL
2

PCIE_SDS_VDD
2

C325

R285 1

2 @ 4.7K_0402_5%

R287 1

T60
PAD
2 @ 4.7K_0402_5%

R286 1

2 @ 4.7K_0402_5%

0.1U_0402_16V4Z

AVDDL
V_3P3_LAN

V_3P3_LAN_LED
D

3
A

R525

Q60
SI2301BDS_SOT23

Disconnected

MDO3-

Yellow LED+

<32>

LAN_ACT#

13

<22,32> LAN_ACT#

1 300_0402_5%

BCM5753

VDDIO_0
VDDIO_1
VDDIO_2
VDDIO_3
VDDIO_4
VDDIO_5
VDDIO_6
VDDIO_7
VDDIO_8
VDDIO_9
VDDIO_10

R985
2
1
0_0603_5%

VDDC_0
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7

A2
A6
A10
B4
D3
E11
G2
H11
K3
M2
P12

V_2P5_LAN

Layout Notice : Place

termination as close as
BCM5751M as possible

R266 2

C338
0.1U_0402_16V4Z

2
D

U7B
E6
E7
E8
E9
J6
J7
J9
K5

Layout Notice : Filter place as close

chip as possible.

MDO3+

R986

V_3P3_LAN_LED

2
R1040

1000P_1808_3KV7K

R50 1
R63 1
R45 1
R48 1
R42 1
R44 1
R40 1
R41 1

MDO2+

24HST1041-3

0.1U_0402_16V4Z 1

@ AO7407_SOT323

GND

Don't care

TRM_CT

Q106

1000P_1808_3KV7K
1
0_0402_5%

LAN_TX2+

LAN_TX3+

2 R270
1
75_0402_1%

C337
0.1U_0402_16V4Z

MDO2-

C343
0.1U_0402_16V4Z

MCT1

19

VMAINPRSNT_R

C336
0.1U_0402_16V4Z

18

MX2-

C335
0.1U_0402_16V4Z

MCT3

TD2-

VMAINPRSNT
C344
1
2

TCT3

MDO1+

Digial power

LAN_TX2-

1:1

2
1
C329
0.01U_0402_16V7K

TRM_CT

17

MX3+

1:1

2
1
C328
0.01U_0402_16V7K

TD3+

C15

2
1
C327
0.01U_0402_16V7K

C65

LAN_TX1+

R871
10K_0402_5%

C340
0.1U_0402_16V4Z

<22>

C334
0.1U_0402_16V4Z

NIC_PD

C341
0.1U_0402_16V4Z

16

C61
0.1U_0402_16V4Z

MX3-

V_1P2_LAN

C66
4.7U_0805_10V4Z

TD3-

MCT4

V_2P5_LAN
+3VS
2 R269
1
75_0402_1%

TCT4

15

2
G

10

0.1U_0402_16V4Z

LAN_TX1-

1:1

TRM_CT

0.1U_0402_16V4Z

2
1
C330
0.01U_0402_16V7K

Analog
power
PLL

BIAS

VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31

A3
A8
A12
A14
B1
C1
C3
C11
F1
F5
F6
F7
F8
F9
F10
G5
G6
G7
G8
G9
G10
H6
H7
H8
H9
J1
M3
M7
N1
N7
P11
P14

DC_0
DC_1
DC_2
DC_3
DC_4
DC_5
DC_6
DC_7
DC_8
DC_9
DC_10
DC_11
DC_12
DC_13
DC_14
DC_15
DC_16
DC_17
DC_18
DC_19
DC_20
DC_21
DC_22
DC_23
DC_24
DC_25
DC_26
DC_27
DC_28
DC_29
DC_30
DC_31
DC_32
DC_33
DC_34
DC_35
DC_36
DC_37
DC_38
DC_39

A11
A13
B14
C14
D6
D14
E3
E14
F14
G14
H5
H14
J8
J14
K4
K6
K7
K8
K9
K10
K14
L6
L10
L12
L14
M11
M14
N5
N11
N12
N14
P3
P4
P5
P6
P7
P8
P9
P10
P13

BIASVDD

B13

BCM5753MKFBG P3_FPBGA196~D

BIASVDD_LAN
1
C63

0.1U_0402_16V4Z
2
1

<20,25,32> PREP#

100K_0402_5%

V_2P5_LAN
L8
1
2
BLM11A601S_0603

2
G

Q61
RHU002N06_SOT323

Compal Secret Data

Security Classification
Issued Date

2005/05/26

2006/07/26

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.

Magnetic & RJ45/RJ11
Document Number

Rev
1.0

LA-2952P
Friday, April 28, 2006

Sheet
1

23

of

47

+3VS

B/B connector with PCI / LED / FIR / SC interface

C538

<18>

<20> PCIE_RXN2
<20> PCIE_RXP2

PCI_AD13
PCI_AD11
PCI_AD9
PCI_CBE#0
PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0

<20> PCIE_TXN2
<20> PCIE_TXP2

PCI_CBE#0 <18>

+3VL

IRRX
<28>
IRTXOUT <28>
IRMODE <28>
SC_CD#
SC_FCB
SC_CLK
SC_RST
SC_DATA
SC_RFU

<30,31,32> STB_LED#
<30,31> NUM_LED#
<30,31> CAPS_LED#

<27>
<27>
<27>
<27>

53
+3VALW

+3V_MINI

Q41

92
94
96

R519

88020-90101

<20,22,25,26,30,32,33,40,41>

+1.5VS

Mini-Express Card--WWAN
+3VALW

JP46

0.1U_0402_16V4Z

+3VS

R1071
0_0603_5%
1
2
1
2
R1073
0_0603_5%

53

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

GND1GND2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

0.1U_0402_16V4Z

C544
4.7U_0805_10V4Z

C291

C547
0.01U_0402_16V7K

2
G
Q42
@ RHU002N06_SOT323

<20>

Q58
@ RHU002N06_SOT323

R1355

ACCELEROMETER

2
@ 0_0805_5%

PLT_RST_B# <19,28,29>
2
+3VALW
@ 0_0402_5%
2
+3VS
0_0402_5%

1
R1365
1
R1366

Vn

Vp

CH2 CH3

0_0402_5%
0_0402_5%

2
DAN217_SC59

UIM_VPP
UIM_DATA

4
5
6

GND
VPP
I/O

R1425

18

Reserved2

20

Reserved3

Reserved1

R1361

JP50
VCC
RST
CLK

1
2
3

UIM_PWR
UIM_RST
UIM_CLK

SUYIN_254021MA006G100ZL

54

R1359

1
7
8
14
15
21
22
23
24
25
26
27
28

0_0402_5%

WW_LED# <29>

C554
4.7U_0805_10V4Z

C960
+3VS_ACL

1
2
@ 0_0402_5%

C994

C995

@ 0.01U_0402_16V7K

SDO

10U_0805_10V4Z

SDA/SDI/SDO

10

SCL/SPC

12

CS

13

CK

16

ICH_SMBDATA <4,13,14,15,20,22>

+3VS_ACL
R1362
1
2
10K_0402_5%
R1391
1

2
0_0402_5%

LIS3LV02DQ_QFN28

Compal Secret Data

Security Classification
2005/05/26

2006/07/26

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

ACCEL_INT <18>

Must be placed in the center of the system.

Issued Date

M_WXMIT_OFF#

2
0_0402_5%

U43C
SN74LVC08APW_TSSOP14

100K_0402_5%
4

RDY/INT

0.1U_0402_16V4Z

R1426

10

14
C986

R521

0.1U_0402_16V4Z
1

SW1
2 1BD002-1101L_4P
1

<20> WXMIT_OFF#

0_0402_5%

+3VS_ACL_IO

ICH_SMBCLK <4,13,14,15,20,22>

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13

C996

+3VS
+3VS

2
0_0603_5%

S DIO(BR) NUP4301MR6T1 TSOP-6

USB20_N1 <20>
USB20_P1 <20>
WW_LED#

U64

R1357
+3VS_ACL

D13

1
D64
CH751H-40_SC76

+3VS_UIM

U72
CH1 CH4

R1356

+3VS_ACL_IO

XMIT_OFF

+3VS_ACL

XMIT_OFF#
D

2
G

SLP_S3#

+3VS_UIM

M_WXMIT_OFF#

@ 100K_0402_5%

@ 10K_0402_5%

R1422

R517

R516

0.01U_0402_16V7K
UIM_PWR
UIM_DATA
UIM_CLK
UIM_RST
UIM_VPP

MOLEX 67910-0002 52P

MOLEX 67910-0002 52P

Vdd

+3VALW

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

0.01U_0402_16V7K

C540

WW_LED# <29>
WL_LED# <29>
WP_LED# <29>

WW_LED#
WL_LED#
WP_LED#

+3VS

C295

ICH_SMBCLK <4,13,14,15,20,22>
ICH_SMBDATA <4,13,14,15,20,22>

54

GND1GND2

<19,28,29,30>

0_0402_5%
PLT_RST_B# <19,28,29>
2
V_3P3_LAN
2
+3VS
@ 0_0402_5%

1
1

+3VS

0.1U_0402_16V4Z

C959

+1.5VS +3VS

LPC_AD[0..3]

XMIT_OFF#
R1363
R1364

1
2
@ 100K_0402_5%

GND
GND
GND

LPC_FRAME# <19,28,29,30>

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

FBMA-L11-201209-102LMA10T

GND
GND
GND

2
2
2
2
2

L78
D

C165
@18P_0402_50V8J

1
1
1
1
1

91
93
95

+3VS

R1413
R1414
R1415
R1416
R1417

@ SI2301BDS_SOT23

<27>
<27>

SC_CD#
SC_FCB
SC_CLK
SC_RST
+SC_PWR
SC_DATA
SC_RFU

+5VS

<19,28,29> PLT_RST_B#
<15> CLK_DEBUG_PORT

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

R106
@ 10_0402_5%

PCI_FRAME# <18>
PCI_TRDY# <18>
PCI_STOP# <18>
PCI_DEVSEL# <18>

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

+3VS

<15> CLK_PCIE_MCARD#
<15> CLK_PCIE_MCARD

+3V_MINI

11

CLK_48M_CB

1
3
5
7
2 CLKREQD#_MC
0_0402_5%
9
11
13
15
PLT_RST_B#
17
1
2
R1412
DEBUG@0_0402_5% 19
R1348
0_0402_5%
21
PCIE_RXN2
PCIE_C_RXN2 23
1
2
PCIE_RXP2
PCIE_C_RXP2 25
1
2
R1349
0_0402_5%
27
29
PCIE_TXN2
31
PCIE_TXP2
33
35
37
39
41
43
R1418 1
45
2 DEBUG@ 0_0402_5%
R1358 1
47
2 DEBUG@ 0_0402_5%
R1353 1
49
2 DEBUG@ 0_0402_5%
R1360 1
51
2 DEBUG@ 0_0402_5%

PCI_PAR <18>

GND

PCI_PAR
PCI_AD18
PCI_AD16
PCI_FRAME#
PCI_TRDY#
PCI_STOP#
PCI_DEVSEL#
PCI_AD15

ICH_PCIE_WAKE#
CH_DATA
CH_CLK
1
R1336
CLK_PCIE_MCARD#
CLK_PCIE_MCARD

<20,22> ICH_PCIE_WAKE#
<27> CH_DATA
<27> CH_CLK
<15> CLKREQD#

DEBUG@0_0402_5%
DEBUG@0_0402_5%
DEBUG@0_0402_5%
DEBUG@0_0402_5%
DEBUG@0_0402_5%

JP44
PCM_SPK <25>

PCI_AD22
PCI_AD20

C954
0.1U_0402_16V4Z

17

<20> HDD_HALTLED#
+3VL
<29,31> WL_BLUE_LED#
<30> GREEN_BATLED#
<30> AMBER_BATLED#
<30,31,32> STB_LED#
<19>
IDE_LED#

PLT_RST# <7,16,18,19,20,22,30>

PCI_AD30
PCI_AD28
PCI_AD26
PCI_AD24

C533
4.7U_0805_10V4Z

+1.5VS

19

PCI_AD14
PCI_AD12
PCI_AD10
PCI_AD8
PCI_AD7
PCI_AD5
PCI_AD3
PCI_AD1

Vdd_IO

PCI_SERR#
PCI_PERR#
PCI_CBE#1

C294
0.1U_0402_16V4Z

Mini-Express Card---WLAN

<18> PCI_CBE#2
<18> PCI_IRDY#
<20,28,29,30> PM_CLKRUN#
<18,30> PCI_SERR#
<18> PCI_PERR#
<18> PCI_CBE#1

GND

PCI_AD19
PCI_AD17
PCI_CBE#2
PCI_IRDY#

Vdd

PCI_AD23
PCI_AD21

PCI_PIRQE# <18>
PCI_PIRQC# <18>
PCI_RST# <18,19>
PCI_GNT2# <18>
SIRQ
<20,28,29,30>
CLK_48M_CB <15>

C293
0.01U_0402_16V7K

PADDLE

<18> PCI_CBE#3

PCI_PIRQE#
PCI_PIRQC#
PCI_RST#
PCI_GNT2#

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90

GND

PCI_REQ2#
PCI_AD31
PCI_AD29
PCI_AD27
PCI_AD25

<18> PCI_REQ2#

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89

C542
4.7U_0805_10V4Z

29

<18> PCI_PIRQG#
<18> PCI_PIRQD#

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89

PCI_PIRQG#
PCI_PIRQD#

CLK_PCI_PCM

<15> CLK_PCI_PCM

0.1U_0402_16V4Z

+3VALW

PCI_AD[0..31]

JP13

+1.5VS

PCI_AD[0..31]

Compal Electronics, Inc.

Mini-Card/Mini-PCI/Accelerometer
Document Number

Rev
1.0

LA-2952P
Sheet

Friday, April 28, 2006

E

24

of

47

VDDA_CODEC

VDDA_CODEC

SLP_S3#

<20,22,24,26,30,32,33,40,41>

+5VAMP

R329

U18

0.1U_0402_16V4Z 150K_0402_1%

R330
S

MONO_IN
2
0.1U_0402_16V4Z

+ C548

C377

22U_B_10V

C552
1U_0603_10V4Z

C551
100P_0402_50V8J

R456

IN
OUT

ADJ

EN

49.9K_0402_1% 1

GND

MIC5205BM5_SOT23-5

1
2
R258
0_1206_5%

0.01U_0402_16V7K

C553

+ C309
R457

22U_B_10V

C307
0.1U_0402_16V4Z
1

0.01U_0402_16V7K
1

143K_0402_1%
2

Q35
RHU002N06_SOT323

1
C430

10K_0402_5%

2
G

<24> PCM_SPK
1

R341
1

10K_0402_5%
C390
1
2

VDDA_CODEC
1

Place R258 between DGND & AGND & close to U14

R350

1
<20>

10K_0402_5%
C396
1
2

R359
1

0.1U_0402_16V4Z 150K_0402_1%

2
G

SB_SPKR

Q37
RHU002N06_SOT323

Place close to U14

R1400
2

0_1206_5%
2

+3VS
2
C409

1
0.1U_0402_16V4Z

2
C427

1
0.1U_0402_16V4Z

2
C431

1
0.1U_0402_16V4Z

VDDA_CODEC
R1399
0.1U_0402_16V4Z +3VS_CODEC

1
U14

GND

GNDA

10U_0805_10V4Z

T16
INT_MIC

<26> INT_MIC

R370
R375
R369
R374

<32> DLINE_IN_L
<32> DLINE_IN_R

2
1
2
1

1
2
1
2

4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%

C425 1

T17
2 1U_0603_10V4Z

PAD
PAD

LINE_OUT_L

35

LINE_OUTL

AUX_R

LINE_OUT_R

36

LINE_OUTR

16

MIC3

MONO_OUT

37

LINE_OUTL <26>
LINE_OUTR <26>
T14
PAD

MIC4

HP_LOUT_L

39

L_HP

L_HP

23

LINE_IN_L

HP_LOUT_R

41

R_HP

DLINE_IN_R_R C422 1

2 1U_0603_10V4Z

DLINE_IN_RC_R

24

LINE_IN_R

R_HP
2
R1038

<26>

MIC1

MIC1

<26>

MIC2

MIC2

1
C204
1
C205

R231

T18

PAD

T19

PAD

T20
PAD
MIC1_C
2
1U_0603_10V4Z
MIC2_C
2
1U_0603_10V4Z
SENSE_A
SENSE_B
2
2.2K_0402_1%
2
@ 0_0402_5%

18

CD_L

20

CD_R

19

CD_GND

21

MIC1

22

MIC2

13
34

SENSEA
SENSEB

<19> AC97_RST#_CODEC

11

<19> AC97_SYNC_CODEC

10

<19> AC97_SDOUT_CODEC

EAPD

L53 1
2
FBM-L10-160808-301-T_0603
PAD

T15

1
R970

2
39.2K_0402_1%

SENSE_A_A <26>

1
R972

2
20K_0402_1%

SENSE_A_B <26>

BIT_CLK

SDATA_IN

1
@ 33_0402_5%

<26>
<26>
1

C1064

@ 10P_0402_25V8K

AC97_BITCLK_CODEC <19>
AC97_SDIN0_CODEC

R373 1
33_0402_5%

AC97_SDIN0 <19>

@
@

PORT_A_SNS <26>

GPIO_0
GPIO_1
GPIO_2
GPIO_3

VREF

27

MIC_BIAS_B
MIC_BIAS_C
MIC_BIAS_F
MIC_BIAS_D
PCBEEP

28
29
30
32
12

N/C
N/C
N/C
NC
NC

31
33
40
45
46

AVSS1
AVSS2

26
42

RESET#
SYNC
SDATA_OUT

47

EAPD

48

SPDIFO

4
7

DVSS1
DVSS2

R168
R167
R136
R32

43
44
2
3

1
1
1
1

2
2
2
2

4.7K_0402_5%
4.7K_0402_5%
10K_0402_5%
4.7K_0402_5%

PREP#

PORT

PLACE TO

MONO_OUT

PORT A

HP OUT, DOCK HP LO

PORT B

M/B MIC

PORT C

DOCK LI

C416

PORT D

M/B SPK

0.1U_0402_16V4Z

PORT E

PORT F

Internal MIC

<20,23,32>

AUD_REF
T21
T13
T12
T11
MONO_IN
T6
T7
T5
T3
T4

1
PAD
PAD
PAD
PAD

C424
1U_0603_10V4Z

PAD
PAD
PAD
PAD
PAD

AD1981HDJSTZ-REEL_LQFP48

VDDA_CODEC

SENSE_A_C
2
10K_0402_1%
1

C977
@ 1U_0402_6.3V4Z

2
G

Q97

S
2N7002_SOT23

R974
@ 0_0402_5%

2
1

AUX_L

15

17

<26,30>

14

DLINE_IN_RC_L

LINE_IN_SENSE

LINE_IN_SENSE <32>

C978

0.1U_0402_16V4Z

Issued Date

2005/05/26

2006/07/26

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

100K_0402_5%

Compal Electronics, Inc.

Compal Secret Data

Security Classification

R988

SENSE_B

0.1U_0402_16V4Z

2 1U_0603_10V4Z

R969
2.67K_0402_1%

1
R973

C393
10U_0805_10V4Z

2 1U_0603_10V4Z

R169

R980
@ 0_0402_5%

C426 1

VDDA_CODEC

SENSE_A

1
2
0_0805_5%

C175

DLINE_IN_R_L C423 1

VDDA_CODEC

AVDD1

0.1U_0402_16V4Z

0.1U_0402_16V4Z
2

1
C156

DVDD2

2
C402

DVDD1

1
C148

38

1
C417

AVDD2

1
C147

25

0.1U_0402_16V4Z 0.1U_0402_16V4Z
1
C395

AC97 CODEC AD1981B

Document Number
Friday, April 28, 2006

Date:

Rev
1.0

LA-2952P
G

Sheet

25
H

of

47

AMP. FOR INTERNAL SPEAKER

+5VALW

AMP. FOR INTERNAL MICROPHONE

Place close to U14 audio CODEC

+5VAMP
R443

1
2 LINE_C_R_OUTL
12.1K_0402_1%
7.6 dB
L_SPK+

OUTL-

17

L_SPK-

NC1
NC2
NC3
NC4

3
10
13
16

14

SHDN

C471
1

0.01U_0402_16V7K

JJ_MIC_REF

Place close to JP15

2
R978
100_0402_5%

<25>

MIC2

2
1

100K_0402_5%

2
G

1
1

S
0.1U_0603_16V4Z

2
2

Q44

C527

R255

2.2U_0603_6.3V6K

MIC1
MIC2
MIC_SENSE
R_HP
L_HP

1
2
3
4
5
6
7
8
9
10
11
12

C441
0.1U_0402_16V4Z

J_MIC1

C489
1
2

47K_0402_5%

1
2
3
4
5
6
7
8
9
10
11
12

C492

4.7U_0805_10V4Z 1

100P_0402_50V8J
R414
1
2

2
R1424

1
0_0402_5%

JJ_MIC_REF

2
R1423

1
@ 0_0402_5%

J_MIC_REF

JJ_MIC_REF

R429
47K_0402_5%

J_VDDA_CODEC

100K_0402_5%

U46B

ACES_87213-1200

DLINE_OUT_L

C536 100K_0402_5%

R_HP
L_HP

<32> DLINE_OUT_L
<32> DLINE_OUT_R
VDDA_CODEC

R251

TLV2462_SO8
O

68P_0402_50V8J

C248
100P_0402_50V8J

1
3

100K_0402_5%

<32> DOCK_HPS#

1 C57210K_0402_5%

MIC1

JP9
<25>

<25>
<25>

VDDA_CODEC
R423

EXT_MICA_2

R427

2
G

3
2

U27B
TLV2462_SO8

MIC_REF

U46A

R211
1

J_VDDA_CODEC

VDDA_CODEC

<25> SENSE_A_A

L58
EXT_MICA_1 1
2
HLC0603CSCCR10JT_0603
0.22U_0603_10V7K

47K_0402_5%

4.7U_0805_10V4Z 1

R428

C276
1
2

100K_0402_5%

Q48
RHU002N06_SOT323
2
G

1 2

1
5

C490

4.7U_0805_6.3V6K

47K_0402_5%

R995
100K_0402_5%
<25> PORT_A_SNS

1
R426

VDDA_CODEC

EXT_MICA

J_VDDA_CODEC

VDDA_CODEC
1 C982

<25>

100P_0402_50V8J
R413
1
2

MIC_REF

Place close to U14 audio CODEC

INT_MIC
2

MAX9710ETP_QFN20

VDDA_CODEC

INT_MIC

C488
1
2

Q32
RHU002N06_SOT323

AMP. FOR EXTERNAL MICROPHONE

2
G

A_SD

Q49
RHU002N06_SOT323

4.7U_0805_6.3V6K

1
@ 0_0402_5%

68P_0402_50V8J
2

19

1 C226

OUTL+

3K_0402_5%

U27A
TLV2462_SO8

MUTE

L57
HLC0603CSCCR11JT_0603
C231
R388
INT_MIC_4
2
1
2INT_MIC_3
1
2 1
2
3K_0402_5%
1
0.22U_0603_10V7K
10K_0402_5%
C571

R193
2INT_MIC_1

R_SPK-

2
2

VDD
PVDD1
PVDD2

OUTR-

R196

1
1

100K_0402_5%

Q28
@ RHU002N06_SOT323

<30>

2 10K_0402_5%

1
@ 0_0402_5%
2
G

EAPD

PGND1
PGND2
PGND3
PGND4
PGND5

2
R1421

1
2 LINE_C_R_OUTR
12.1K_0402_1%
7.6 dB
R_SPK+

OUTR+
INL

6
11
15
20
21

<31> MUTE_LED#

2
R1427

R430 1

SLP_S3#

@ 1200P_0402_50V7K
VDDA_CODEC

R1406
R1407
2
1
0_0402_5%

EAPD

C585
1
2

2 1U_0603_10V4Z

VDDA_CODEC

12
8
18

10 dB

<25,30>

C1044

BIAS

10K_0402_5%

0.1U_0402_16V4Z

<20,22,24,25,30,32,33,40,41>

INR

INT_MIC_2

1
2
ACES_85205-0200

Keep 10 mil width

R1405

LINE_C_R_OUTL

MIC_REF
PACDN042_SOT23~D

JP36

0.1U_0402_16V4Z

U39

R1411
LINE_C_OUTL 1

C502
1
2

LINE_OUTL

2
2
1U_0603_10V4Z

10K_0402_5%

<25>

LINE_C_R_OUTR

C539

@
2

R1410
LINE_C_OUTR 1

C503
1
2

+
2

10 dB

0.1U_0402_16V4Z

1
C660

EXT_MICB

C526

C275
1
2

L61

R210

EXT_MICB_1 1
2
HLC0603CSCCR10JT_0603
0.22U_0603_10V7K

10K_0402_5%

EXT_MICB_2
6
1
C470

C575
68P_0402_50V8J

@ 1U_0603_10V6K
2

RHU002N06_SOT323

TLV2462_SO8
3

C662
@
150U_D_6.3VM

O
-

J_MIC2

0_1206_5%

<25> LINE_OUTR

680P_0402_50V7K
R190
1
2

2
1

C446
100P_0402_50V8J

10U_0805_10V4Z

C230
1
2

D62

C659
10U_0805_10V4Z

C249
100P_0402_50V8J

1
C1098

0.1U_0402_16V4Z

VDDA_CODEC
CHB1608B121_0603
R_CR_HP 1
R_CRL_HP
2
L52

L_C_HP
2
150U_D_6.3VM

2
16_0805_1%

L51
L_CR_HP 1
CHB1608B121_0603

1
4

Vp

CH2 CH3

100P_0402_50V8J
2

100P_0402_50V8J
1
1
C514
C507
2

C984
0.1U_0402_16V4Z

J_VDDA_CODEC

SUYIN_010030FR006G101ZL_6P

C564

MIC_SENSE

R418

1K_0402_1%

470P_0402_50V7K

Place close to U14

+3VS

2
470_0402_5%

1
2
3
4
5
6

2
2
100P_0402_50V8J

1
2
3
4

1
2
3
4
5
6

Place close to JP24

J_MIC1

EXT_MICA

C486

10U_0805_10V4Z
J_MIC_REF

JP28
1
2
3
4
5
6

Place close to JP15

100P_0402_50V8J

ACES_87213-0600

1
2
3
4
5
6

J_R_HP
J_L_HP
J_DLINE_OUT_L
J_DLINE_OUT_R
J_VDDA_CODEC

2005/05/26

Issued Date

L46
CHB1608B121_0603
1
2
L47
CHB1608B121_0603
C508
470P_0402_50V7K

2006/07/26

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C

3
6
2
1
1

C522

SUYIN_010030FR006G101ZL_6P

470P_0402_50V7K

10U_0805_10V4Z

Date:

8
7

Compal Secret Data

Security Classification

5
4

J_MIC2
J_MIC_SENSE

ACES_87213-0600

C518 E&T_3801-04

C487

EXT_MICB

R421
3.9K_0402_1%

JP27

1
2
3
4

JP15
J_MIC_SENSE
R424
3.9K_0402_1%
1
2

1
2
R425
470_0402_5%

JP21

1
C506

2
G
S

Vn

Q50
RHU002N06_SOT323

R446

1K_0402_1%
6

@ S DIO(BR) NUP4301MR6T1 TSOP-6

L_SPK+
L_SPKR_SPK+
R_SPK-

C563

3
6
2
1

L_CRL_HP

470P_0402_50V7K

CH1 CH4

R979
47K_0402_5%

<25> SENSE_A_B
1

R253
1
2
16_0805_1%

R445

8
7

Place close to JP24

U73

JP24
5

+
+

J_L_HP
1
C581

R261
J_R_HP 1
R_C_HP
2
C577
150U_D_6.3VM
J_DLINE_OUT_R
J_DLINE_OUT_L

Compal Electronics, Inc.

AMP & Audio Jack
Document Number

Rev
1.0

LA-2952P
Sheet

Friday, April 28, 2006

E

26

of

47

Left side

Left side

USB CONNECTOR 0

USB CONNECTOR 1

USB_VCCA

+5VALW

USB_VCCA
U57

G548A2P1U

JP23

W=80mils

8
7
6
5

1
1

+
2

C519
1000P_0402_50V7K

4.7U_0805_10V4Z

OUT
OUT
OUT
OC#

C515
0.1U_0402_16V4Z

C550

GND
IN
IN
EN#

C567
150U_D_6.3VM

1
2
3
4

<20>
<20>

0_0603_5%
USB20_N4 1
USB20_P4 1
0_0603_5%

USB20_N4
USB20_P4

R604
2USB20_N4_R
2USB20_P4_R
R605

1
2
3
4
5
6
7
8

R163

1
2
3
4
GND
GND
GND
GND

1
2
3
4
5
6
7
8

0_0603_5%
USB20_N5_R
1
USB20_P5_R
1
0_0603_5%

R606
2USB20_N5
2USB20_P5
R607

USB20_N5 <20>
USB20_P5 <20>

SUYIN_020173MR004S558ZL
SUYIN_020173MR004S558ZL

SLP_S5
1

JP25

1
2
3
4
GND
GND
GND
GND

+5VALW

10K_0402_5%

3
2

D51
PJDLC05_SOT23~D

D52
PJDLC05_SOT23~D

+5VALW

Right side USB CONNECTOR 0

USB20_P5
USB20_N5

USB20_P4
USB20_N4

USB_VCCC
U65

TPS2061DGNRG4_MSOP8~N
2

SLP_S5

SLP_S5

+
2

0_0603_5%
<20>
<20>

USB20_N3
USB20_P3

0_0603_5%

R617
2USB20_N3_R
2USB20_P3_R
R614

1
1

1
2
3
4
5
6
7
8

1
2
3
4
GND
GND
GND
GND
SUYIN_020173MR004S558ZL

<32,33>
R164

+5VALW

10K_0402_5%

USB20_P3
USB20_N3
2

4.7U_0805_10V4Z

C521
1000P_0402_50V7K

JP26

W=40mils

8
7
6
5

OUT
OUT
OUT
OC#

C517
0.1U_0402_16V4Z

C558

GND
IN
IN
EN#

C569
150U_D_6.3VM

1
2
3
4

D61
PJDLC05_SOT23~D

BT Connector
JP22
1
2
3
4
5
6
7
8

SMART Card connector

R458 1
R459 1

2
2

R586
1K_0402_5%
1K_0402_5%

USB20_P0 <20>
USB20_N0 <20>

BT_LED <29>
CH_DATA <24>
CH_CLK
<24>

ACES_87212-0800

+SC_PWR

USB20_P0
USB20_N0

1 0_0402_5%
1 0_0402_5%

2
2

+3VAUX_BT

R562
USB20_P0_R
USB20_N0_R

D53

@ PACDN042_SOT23~D

JP3

SC_CD#

SC_DATA
SC_RFU

SC_FCB
SC_CLK
SC_RST
+SC_PWR
SC_CD#

<24>
<24>
<24>

C367
0.1U_0402_16V4Z

+3VALW

+3VAUX_BT
Q51

<24>

SI2301BDS_SOT23

SC_DATA <24>
SC_RFU <24>

ACES_85203-1002

C306

R518

1U_0603_10V4Z

100K_0402_5%

C546

SC_FCB
SC_CLK
SC_RST

11
12
13
14
15
16
17
18
19
20

11
12
13
14
15
16
17
18
19
20

1
2
3
4
5
6
7
8
9
10

1
2
3
4
5
6
7
8
9
10

1
C549
4.7U_0805_10V4Z
0.1U_0402_16V4Z
2
2
1

C545

0.01U_0402_16V7K

<20>

BT_OFF

R454
1
2
47K_0402_5%

C556
1

0.1U_0402_16V4Z

Compal Secret Data

Security Classification
2005/05/26

Issued Date

2006/07/26

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.

USB & BT Connector
Document Number

Rev
1.0

LA-2952P
Sheet

Friday, April 28, 2006

1

27

of

47

+3VS
RP3
DCD#1
RI#1
CTS#1
DSR#1

1
2
3
4

8
7
6
5

+5VS
2

4.7K_1206_8P4R_5%
IRRX

1
2
R76
1K_0402_5%

D36

CH751H-40_SC76

+5VS_PRN

<20> NPCI_RST#
<19,24,29> PLT_RST_B#
+3VS

10K_1206_8P4R_5%
R120
SIO_IRQ
1
2
R121
10K_0402_5%
SIO_DPIO45
1
2
10K_0402_5%

<19,24,29,30> LPC_FRAME#
<19> LPC_DRQ#0

2 0_0402_5%
2 @ 0_0402_5%
2 10K_0402_5%

1
1
1

+3VS

1
R67

15
16

LFRAME#
LDRQ#

17
18

PCI_RESET#
LPCPD#

19
20
21
6

CLKRUN#
PCI_CLK
SER_IRQ
IO_PME#

PM_CLKRUN#
CLK_PCI_SIO
SIRQ
SIO_PME#

<20,24,29,30> PM_CLKRUN#
<15> CLK_PCI_SIO
<20,24,29,30> SIRQ
2
10K_0402_5%

CLK_14M_SIO

<15> CLK_14M_SIO

SIO_GPIO40
PID0
PID1
SIO_GPIO43
SIO_GPIO44
SIO_DPIO45
CARD_ID#
SER_SHD
SIO_GPIO10
SIO_GPIO11
SIO_GPIO12
SIO_IRQ

R119
CARD_ID#

LPC_FRAME#
LPC_DRQ#0
SIO_RST#
SIO_PD#

+3VS
1

LAD0
LAD1
LAD2
LAD3

10K_0402_5%
<32>

SER_SHD

R68
1

EXPCRD_RST#

EXPCRD_RST#

<32> EXPCRD_RST#

10K_0402_5%
R77
PID0

CLK14

62
63
64
1
2
3
4
5

RXD1
TXD1
DSR#1
RTS#1
CTS#1
DTR#1
RI#1
DCD#1

IRRX2
IRTX2
IRMODE/IRRX3

37
38
39

IRRX

INIT#
SLCTIN#
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
SLCT
PE
BUSY
ACK#
ERROR#
ALF#
STROBE#

41
42
44
46
47
48
49
50
51
53
55
56
57
58
59
60
61

LPTINIT#
LPTSLCTIN#
LPD0
LPD1
LPD2
LPD3
LPD4
LPD5
LPD6
LPD7
LPTSLCT
LPTPE
LPTBUSY
LPTACK#
LPTERR#
LPTAFD#
LPTSTB#

VTR
VCC
VCC
VCC
VCC

7
11
26
45
54

FIR

CLOCK

GPIO40
GPIO41
GPIO42
GPIO43
GPIO44
GPIO45
GPIO46
GPIO47
GPIO10
GPIO11/SYSOPT
GPIO12/IO_SMI#
GPIO13/IRQIN1
GPIO14/IRQIN2
GPIO23

8
22
43
52

+3VS
1

9
23
24
25
27
28
29
30
31
32
33
34
35
36
40

RXD1
TXD1
DSR1#
RTS1#
CTS1#
DTR1#
RI1#
DCD1#

SERIAL I/F

R108
R109
R99

10
12
13
14

VSS
VSS
VSS
VSS

PARALLEL I/F

SIO_GPIO12
SIO_GPIO10
SIO_GPIO44
SIO_GPIO43

1
2
3
4

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

GPIO

RP6
8
7
6
5

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC I/F

U8
<19,24,29,30>
<19,24,29,30>
<19,24,29,30>
<19,24,29,30>

POWER

10K_0402_5%

RXD1

<32>

R64
1
TXD1
DSR#1
RTS#1
CTS#1
DTR#1
RI#1
DCD#1

1K_0402_5%
2
<32>
<32>
<32>
<32>
<32>
<32>
<32>

RP51

IRRX
<24>
IRTXOUT <24>
IRMODE <24>

LPD3
LPD2
LPD1
LPD0

1
2
3
4

4.7K_1206_8P4R_5%
RP52
LPD7
LPD6
LPD5
LPD4

1
2
3
4

C84

C88

C76

8
7
6
5

4.7K_1206_8P4R_5%

LPTINIT# <32>
LPTSLCTIN# <32>
LPD0
<32>
LPD1
<32>
LPD2
<32>
LPD3
<32>
LPD4
<32>
LPD5
<32>
LPD6
<32>
LPD7
<32>
LPTSLCT <32>
LPTPE
<32>
LPTBUSY <32>
LPTACK# <32>
LPTERR# <32>
LPTAFD# <32>
LPTSTB# <32>

RP53
LPTACK#
LPTBUSY
LPTPE
LPTSLCT

1
2
3
4

8
7
6
5

4.7K_1206_8P4R_5%
RP54
1
2
3
4

LPTSTB#
LPTAFD#
LPTERR#

8
7
6
5

4.7K_1206_8P4R_5%
R480
LPTSLCTIN#

LPTINIT#

4.7K_0402_5%
R481
1
2

+3VS

8
7
6
5

4.7K_0402_5%
C57

LPC47N217_STQFP64

PID1

Base I/O Address

0 = 02Eh
* 1 = 04Eh

R79
3

10K_0402_5%

2
3

0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7U_0805_10V4Z

R80
1

SIO_GPIO11

10K_0402_5%
R100
SIO_GPIO40

CLK_PCI_SIO

CLK_14M_SIO

10K_0402_5%

R81
@ 10_0402_5%
2

R96
@ 10_0402_5%

1
C94
@18P_0402_50V8J

C70
@10P_0402_25V8K

Compal Secret Data

Security Classification
2005/05/26

Issued Date

2006/07/26

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.

SUPER I/O LPC47N217
Document Number

Rev
1.0

LA-2952P
Friday, April 28, 2006

Sheet
E

28

of

47

BIOS ROM
+3VALW
+3VS

SPI_WP#

SPI_HOLD#

HOLD

SPI_CS#

R1287
2 SPI_WP#
3.3K_0402_5%
R1288
1
2 SPI_HOLD#
3.3K_0402_5%
1

<20>

SPI_CS#

<20>

SPI_CLK

<20>

SPI_SI

VSS

4
D

47K

SPI_CLK

SPI_SI

Q75
DTA114YKA_SC59

10K

Mini-PCIE Card LED

WW_LED# <24>

R1291
Q

SPI_SO_L 1

SPI_SO
2
47_0402_5%

SPI_SO

<20>

+3VS
1

SST25LF080A_SO8-200mil

R1291 place cloe to U66

47K

10K

BLUE

WL_LED# <24>

Q88
DTA114YKA_SC59

Q79
RHU002N06_SOT323

+3VS
<27>

WP_LED# <24>

R505
100K_0402_5%

Q89
DTA114YKA_SC59

WL_BLUE_LED#

10K

<24,31>
D

2
G

BT_LED
2

47K

0.1U_0402_16V4Z

VCC

+3VALW

U66

C989

WL_LED

D
Q78
RHU002N06_SOT323

2
G
S

R504
100K_0402_5%

TPM1.2

Footprint need to update

+3VS+3VALW

21
22
16
27
15
7

XTALO
XTALI
TPM
SLB 9635 TT 1.1

14
13

TPM_XTALO
TPM_XTALI 1
R101

2
6

TPM_GPIO2
TPM_GPIO

LCLK
LFRAME#
LRESET#
SERIRQ
CLKRUN#
PP

GPIO2
GPIO

1
3
12

2
@ 0_0402_5%
PAD

T87

PAD

T62

R1378
@ 4.7K_0402_5%

SLB9635TT_TSSOP28

TPM_32K_CLK <30>

C1057 1

R1381

18P_0402_50V8J
2
32.768KHZ_12.5P_Q13MC30610018
NC 2

IN

OUT

Y8
TPM_XTALO
C1056 1
10M_0402_5%

0_0402_5%

LPC_PD# <20,30>
1 0_0402_5%

TPM_XTALI
NC
NC
NC

4
11
18
25

R1409

R1379 2

28
9
8

CLK_PCI_TCG
<15> CLK_PCI_TCG
LPC_FRAME#
<19,24,28,30> LPC_FRAME#
PLT_RST_B#
<19,24,28> PLT_RST_B#
SIRQ
<20,24,28,30> SIRQ
PM_CLKRUN#
<20,24,28,30> PM_CLKRUN#
1
2
+3VS
R1380
@ 4.7K_0402_5%

LPC_PD#

LPCPD#
TESTB1/BADD
TEST1

LAD0
LAD1
LAD2
LAD3

26
23
20
17

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

Base I/O Address

+3VS
0 = 02Eh
* 1 = 04Eh

0.1U_0402_16V4Z

R1377
4.7K_0402_5%

GND
GND
GND
GND

<19,24,28,30>
<19,24,28,30>
<19,24,28,30>
<19,24,28,30>

C1052

VDD
VDD
VDD

U69

NC

2
0.1U_0402_16V4Z

0.1U_0402_16V4Z
2

VSB

C1053

24
19
10

0.1U_0402_16V4Z
1
1
C1054
C1055

2
18P_0402_50V8J

Finger printer

+3VS

C206
0.1U_0402_16V4Z

2
JP38

0_0402_5%
2
1
2
1
0_0402_5%

R1334
R1335

<20> USB20_N2
<20> USB20_P2

USB20_N2_R
USB20_P2_R

1
2
3
4

1
2
3
4

ACES_85205-0400

D54
@ PACDN042_SOT23~D

Compal Secret Data

Security Classification
2005/05/26

Issued Date

Deciphered Date

2006/07/26

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.

TCG/BIOS ROM/PS2/LED/SW
Document Number

Rev
1.0

LA-2952P
Sheet

Friday, April 28, 2006

1

29

of

47

+3VL

C37
0.1U_0402_16V4Z

C52
0.1U_0402_16V4Z

C51
0.1U_0402_16V4Z

C36
0.1U_0402_16V4Z

+3VS

C34
4.7U_0805_10V4Z

C75
0.1U_0402_16V4Z

C79
0.1U_0402_16V4Z

C78
0.1U_0402_16V4Z

C81
4.7U_0805_10V4Z

+3VL

BIOS debug port

Place under KB area

RP44

8
7
6
5

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

25
24
23
22
21
20
19
18

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

TP_CLK
TP_DATA
KBD_CLK
KBD_DATA
PS2_CLK
PS2_DATA

26
27
29
31
32
33

IMCLK
IMDAT
KCLK
KDAT
EMCLK
EMDAT

KSI7
KSI6
KSI5
KSI4

10K_1206_8P4R_5%

Pin3 250 : KSO12/OUT8/KBRST

+5VS

<31>

KSI[0..7]

R84
1

TP_CLK

10K_0402_5%
R85
1
2 TP_DATA
10K_0402_5%
RP5

1
2
3
4

8
7
6
5

KBD_CLK
KBD_DATA
PS2_CLK
PS2_DATA

<31>
<31>
<32>
<32>
<32>
<32>

10K_1206_8P4R_5%

10K_0402_5%

<19,24,28,29> LPC_FRAME#
<7,16,18,19,20,22,24> PLT_RST#

Pin34 250 -- LPCPD#

R87 1
R1354 1

<20,29> LPC_PD#
<43>
ADP_EN
1

CLK_PCI_EC

2 @ 0_0402_5%
2 @ 0_0402_5%

R74
@ 2M_0402_5%

LFRAME#
LRESET#
LPCPD#/GPIO23

53
54

XTAL1
XTAL2

51

VCC0

CRY1
CRY2

+RTCVCC

55

41
42
34

4
OUT
NC

IN
2

NC

18P_0402_50V8J
C350

LPC_FRAME#
PLT_RST#

BATSELB_A#
KBRST#
INV_PWM
FAN_PWM
CHGCTRL

GPIO01
GPIO02
GPIO03
GPIO04/KSO14
GPIO05/KSO15

82
62
63
64
66

FWP#
ON/OFFBTN_KBC#
LOW_BAT#
KSO14
KSO15

GPIO07/PWM3
GPIO08/RXD
GPIO09/TXD

68
69
70

PM_RSMRST#
EC_GPIO8
EC_GPIO9

GPIO11/AB2A_DATA
GPIO12/AB2A_CLK
GPIO13/AB2B_DATA
GPIO14/AB2B_CLK
GPIO15/FAN_TACH1
GPIO16/FAN_TACH2
GPIO17/A20M

71
72
73
74
75
76
77

BATCON
ADP_PS1
EC_GPIO13
THM_MBAY#
PCI_SERR#
THM_MAIN#
A20M

GPIO20/PS2CLK
GPIO21/PS2DAT
GPIO24/KSO16
GPIO27

78
80
1
57

NUM_LED#
SLP_S3#

AB1A_DATA
AB1A_CLK

86
87

AB1A_DATA
AB1A_CLK

AB1B_DATA
AB1B_CLK

84
85

AB1B_DATA
AB1B_CLK

PGM Strap/GPIO25

56

PGM R141 1

EA Strap#/GPIO26/KSO17
CLOCK
32KHZ_OUT/GPIO22
RESET_OUT#/GPIO06
PWRGD
VCC1_PWRGD
24MHZ_OUT/GPIO19/WINDMON

83
48
58
49
61
60
50

TEST PIN

52

DMS_LED#/GPIO10
BAT_LED#
PWR_LED#/8051TX
FDD_LED#/8051RX

91
88
90
89

KBC_PWR_ON <39>
GREEN_BATLED# <24>

JP43

BATSELB_A# <38>

18P_0402_50V8J
C349

KB_RST# <19>

@ ACES_85201-0602

ON/OFFBTN_KBC# <31>
LOW_BAT# <20>
KSO14
<31>
KSO15
<31>

+3VL
THM_MAIN# 1 R600
2
210K_0402_1%

PM_RSMRST# <20>

EC_GPIO13 1 R33
2
100K_0402_5%

D10

MODE

ADP_PRES <22,37,38,39,43>

CH751H-40_SC76
2 R31
1
+3VL
THM_MBAY# <36>
10K_0402_5%
PCI_SERR# <18,24>
D6
THM_MAIN# <36>
1
2
GATEA20 <19>
CH751H-40_SC76

ADP_PS1

1
R140

0_0402_5%

EAPD

RP1
AB1A_CLK
AB1A_DATA
AB1B_CLK
AB1B_DATA

Pin1 250 -- TEST Pin ( NC !! )

<25,26> Pin57 250 -- MODE

1
2
3
4

AB1B_DATA <36>
AB1B_CLK <36>
2 0_0402_5%

A_SD

<26>
R282

PGM

PM_POK

10K_0402_5%
B

+3VL
JP31

C67

@
10P_0402_25V8K

R25
FWP#

R62 250@

R62
MODE

2 1

@ 10_0402_5%

ADP_PS0 <43>
AMBER_BATLED# <24>
STB_LED# <24,31,32>
CAPS_LED# <24,31>

AMBER_BATLED#
STB_LED#
CAPS_LED#

C92

CLK_14M_KBC 1

+3VL
2

R58
R59
R60

VCC1_PWRGD
2 100K_0402_5% NUM_LED#
2 100K_0402_5% STB_LED#
100K_0402_5%
CAPS_LED#
2

1
1
1

@ 1K_0402_5%
1U_0603_10V4Z

8
7
6
5

4.7K_1206_8P4R_5%

AB1A_DATA <36>
AB1A_CLK <36>

EA# Pin83 250 -- nEA ( pull up !! )

Pin56 250 -- PGM
CLK_14M_KBC
CLK_14M_KBC <15>
Pin58 250 -- 32KHz_OUT
32K_CLK
Pin49 250 -- Reset Out
PM_POK
PM_POK <7,20>
PWR_GD
PWR_GD <33,34,42,43>
VCC1_PWRGD
VCC1_PWRGD <34>
ADP_ID
<43>
Pin50 250 -- 24MHz_Out
TEST
1
2
Pin52 250 -- XOSEL
R977
300_0402_5%
Pin91 250 -- nDMS_LED

KBC1021_TQFP100

1 R538
2
@ 100K_0402_5%

+3VL

NUM_LED# <24,31>
SLP_S3# <20,22,24,25,26,32,33,40,41>

R52
C69

EC_GPIO9
EC_GPIO8

D7

1
2
INV_PWM
CH751H-40_SC76
FAN_PWM <4>
CHGCTRL <37,38>
Pin82 250 -- nFWP

BATCON <38>
ADP_PS1 <43>

1
2
3
4
5
6

VCC1_PWRGD

10K_0402_5%

@ 10K_0402_5%

2
@ 10P_0402_25V8K

LAD[3]
LAD[2]
LAD[1]
LAD[0]

Power Mgmt/SIRQ

1
120K_0402_5%

@ 10_0402_5%
Y2
1

40
39
37
35

R75
2

C80

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

LPCPD#

R86

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

CLKRUN#
SER_IRQ
PCI_CLK
EC_SCI#

LPC
Bus

<19,24,28,29>
<19,24,28,29>
<19,24,28,29>
<19,24,28,29>

44
46
43
59

OUT7/SMI#
OUT8/KBRST
OUT9/PWM2
OUT10/PWM0
OUT11/PWM1

98
97
96
95
93

Miscellaneous

10K_0402_5%
R1289
1
2 RUNSCI_EC#

PM_CLKRUN#
SIRQ
CLK_PCI_EC
RUNSCI_EC#

KBC_PWR_ON
GREEN_BATLED#

GND
GND
GND
GND
GND
GND
GND

LPCPD#

AGND

99
100

OUT0
OUT1/IRQ8#

Access Bus Interface

92
79
65
45
36
28
8

<20,24,28,29> PM_CLKRUN#
<20,24,28,29> SIRQ
<15> CLK_PCI_EC
<20> RUNSCI_EC#

R94
1

TP_CLK
TP_DATA
KBD_CLK
KBD_DATA
PS2_CLK
PS2_DATA

Note: R94 must be removed when

R1354 stuff and R87 remove.

+3VS

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12/GPIO00/KBRST
KSO13/GPIO18

General Purpose I/O Interface

17
16
15
14
13
12
10
9
7
6
5
4
3
2

Keyboard/Mouse Interface

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13

RP43

+3VL
R30

KSO[0..13]

VCC2
VCC2
VCC2

KSO[0..13]

30
38
47

U47
<31>

10K_1206_8P4R_5%

1
2
3
4

11
67
81
94

+3VL

KSI0
KSI3
KSI2
KSI1

VCC1
VCC1
VCC1
VCC1

8
7
6
5

SMSC_LPC47N250_TQFP-100P

1
2
3
4

1
2
3
4
5
6

0.1U_0402_16V4Z
Remove from daughter board

R29
1

FWP#
32.768KHZ_12.5P_Q13MC30610018

@ ACES_85201-0602

For KBC debugging used.

@ 1K_0402_5%

1. For normal operation:

32K_CLK

R91

R102 1

0_0402_5%

2 @ 0_0402_5%

ADP_EN

<43>

TPM_32K_CLK <29>

AGND FILTER
C58
1

PGM 1

+3VL

R65

J3
2

Un-install R29,R65

NO SHORT PADS

1K_0402_5%

FWP#

2
1
@ 1K_0402_5%

TEST

2
1
@ 1K_0402_5%

R28

2. For KBC internal ROM flash:

Install R29,R65

2
R78

0.1U_0402_16V4Z
A

R27
EA#

250@
R127
R128
R977
R62

1021@
R129
R131
R78

1
1K_0402_5%

Compal Secret Data

Security Classification
2005/05/26

Issued Date

2006/07/26

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.

LPC47N1021
Document Number

Rev
1.0

LA-2952P
Sheet

Friday, April 28, 2006

1

30

of

47

+3VS +5VS

INT_KBD CONN.

SWITCH
BOARD.

JP18
14
13
12
11
10
9
8
7
6
5
4
3
2
1

14
13
12
11
10
9
8
7
6
5
4
3
2
1

R1084
2
2
R1096

28
27
26
25
24
23
22
21
20
19
18
17
16
15

28
27
26
25
24
23
22
21
20
19
18
17
16
15

NUM_LED#
CAPS_LED#
MUTE_LED#
WL_BLUE_LED#
KSO12
KSI0
KSI4
KSI5
KSI6
KSI7

NUM_LED# <24,30>
CAPS_LED# <24,30>
MUTE_LED# <26>
WL_BLUE_LED# <24,29>

0_0402_5%
1
+3VALW
1
+3VL
@ 0_0402_5%

<30>

KSO[0..15]

<30>

KSI[0..7]

GND
GND

1
2
3
4
5
6
7

1
2
3
4
5
6
7

LID_SW#
STB_LED#
ON/OFF#
KSO12
KSI1

<17,20>

JP6
KSO15
KSO10
KSO11
KSO14
KSO13
KSO12
KSO3
KSO6
KSO8
KSO7
KSO4
KSO2
KSI0
KSO1
KSO5
KSI3
KSI2
KSO0
KSI5
KSI4
KSO9
KSI6
KSI7
KSI1

STB_LED# <24,30,32>

ACES_85205-07001

WL,Vol up,Vol down,Mute,Present button

KSI[0..7]

JP20

8
9

conn@
ACES_85203-1402

KSO[0..15]

On/off ,information button

MDC 1.5 Conn.

+3VS

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

conn@
ACES_85203-2402
1

C5

AC97_SDOUT_MDC

<19> AC97_SDOUT_MDC
R1313

<19> AC97_SYNC_MDC
<19> AC97_SDIN1

AC97_SYNC_MDC
1AC97_SDIN1_MDC
33_0402_5%

1
3
5
7
9
11

CP1

0.1U_0402_16V4Z
KSO9
KSI6
KSI7
KSI1

+3VS

JP32
GND1
RES0
IAC_SDATA_OUT
RES1
GND2
3.3V
IAC_SYNC
GND3
IAC_SDATA_IN
GND4
IAC_RESET#
IAC_BITCLK

2
4
6
8
10
12

CP6
5
6
7
8

KSO2
KSO4
KSO7
KSO8

4
3
2
1

KSO6
KSO3
KSO12
KSO13

4
3
2
1

KSO14
KSO11
KSO10
KSO15

4
3
2
1

100P_1206_8P4C_50V8
KSI2
KSO0
KSI5
KSI4

AC97_BITCLK_MDC <19>

13
14
15
16
17
18
19
20

4
3
2
1

CP5
5
6
7
8

100P_1206_8P4C_50V8

100P_1206_8P4C_50V8

13
14
15
16
17
18
19
20

CP7
KSI3
KSO5
KSO1
KSI0

4
3
2
1

CP2
5
6
7
8

100P_1206_8P4C_50V8

5
6
7
8
100P_1206_8P4C_50V8

+3VL

+3VL
1

+3VL

5
6
7
8

TYCO_1-179396-2~D

Connector for MDC Rev1.5

Power button

5
6
7
8
100P_1206_8P4C_50V8

CP3
AC97_BITCLK_MDC

AC97_RST#_MDC

<19> AC97_RST#_MDC

4
3
2
1

R536

R22

1U_0603_10V4Z

2
1

+3VALW

2
G

R8
1
2
100K_0402_5%

Q70
RHU002N06_SOT323

ON/OFFBTN#

+5VS

JP14
SP_DATA

1U_0603_10V4Z

T/P BOARD.

+5VS

ON/OFFBTN# <20>

D42
CH751H-40_SOD323

1
3
5
7

JP17
2
4
6
8

SP_CLK

100K_0402_5%
1
C11

ON/OFFBTN_KBC# <30>

ON/OFFBTN_KBC#
D

1
+5VS

C321

<30>
<30>

TP_DATA
TP_CLK

TP_DATA
TP_CLK

D66

ACES_87153-0801L

2
@ PACDN042_SOT23~D

0.1U_0402_16V4Z

SP_DATA
SP_CLK

C23

13
1

ON/OFF#

U5F
SN74LVC14APWLE_TSSOP14
R26
2
O 12 1

14
P

2
<32>

ON/OFF#

TrackPoint CONN.

100K_0402_5%

100K_0402_5%

+5VS

1
2
3
4
5
6
7
8

C319
0.1U_0402_16V4Z

ACES_87212-0800

Compal Secret Data

Security Classification
Issued Date

2005/05/26

Deciphered Date

2006/07/26

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.

MDC/KBD/ON_OFF/LID
Document Number

Rev
1.0

LA-2952P
Friday, April 28, 2006

Sheet

31

of

47

+5VALW

DOCK CONN. 184PIN

R529
100K_0402_5%

1000P_0402_50V7K
2

2 110_0402_1%

DOCK_DVI_TX2+

R1434

2 110_0402_1%

DOCK_DVI_TX1+

DOCK_DVI_CLK-

R1435

2 110_0402_1%

DOCK_DVI_CLK+

DOCK_DVI_TX0-

R1436

SLP_S5#_5R

<27,33>

DOCK_DVI_TX0+

2 110_0402_1%

DOCK_MOD_RING
DOCK_MOD_TIP

2
1

Q65

2
G

SLP_S5

1000P_0402_50V7K

JP29

R1433

DOCK_DVI_TX1-

DOCK_DVI_TX2-

ACES_85205-0200
3

VIN
1

L10
KC FBM-L18-453215-900LMA90T_1812
2
1
DOCKVIN
1
1
C72
C73

RHU002N06_SOT323
SWAP

JP30B
JP30A

83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127

83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127

MDO0+
MDO0LAN_ACT#_DOCK
LANLINK_STATUS#_DOCK

<9,16>
<9,16>
<9,16>

COMP
CRMA
LUMA

DOCK_RED
DOCK_GRN
DOCK_BLU

2 0_0603_5%
2 0_0603_5%
2 0_0603_5%

1
1
1

R1430 1
R1431 1
R1432 1

2 0_0402_5% DOCK_COMP
2 0_0402_5% DOCK_CRMA
2 0_0402_5% DOCK_LUMA

<25> LINE_IN_SENSE
<43> ACOCP_EN#

<28>
<28>
<28>
<28>
<28>
<28>
<28>
<28>
<28>
<28>
<28>

DCD#1
RI#1
DTR#1
CTS#1
RTS#1
DSR#1
TXD1
RXD1
LPTSTB#
LPTAFD#
LPTERR#

DCD#1
RI#1
DTR#1
CTS#1
RTS#1
DSR#1
TXD1
RXD1
LPTSTB#
LPTAFD#
LPTERR#

<23>
<23>

MDO1+
MDO1-

MDO1+
MDO1-

<23>
<23>

PWR_LED
1
R515
DVI_CLK
DVI_DAT

SLP_S5#_5R
1K_0402_5%
L79

DOCK_DVI_TX2DOCK_DVI_TX2+

DVI_CLK
DVI_DAT

<16>
<16>

3
3 WCM2012F2SF-900T04

2
4

DOCK_DVI_TX1-

DVI_TX2- <16>

2
L80

DVI_TX2+ <16>

DVI_TX1- <16>

WCM2012F2SF-900T04
DOCK_DVI_TX1+

L81
DOCK_DVI_CLKDOCK_DVI_CLK+

<20>

DVI_TX1+ <16>

3
3 WCM2012F2SF-900T04

DOCK_ADP_SIGNAL
DOCK_ID

USB20_P6
USB20_N7

<20>

DVI_CLK+ <16>

DVI_TX0- <16>

DVI_TX0+ <16>

WCM2012F2SF-900T04
DOCK_DVI_TX0+

<20>
<20>

DVI_CLK- <16>

2
L82

DOCK_DVI_TX0-

USB20_N6

USB20_P7
SER_SHD
EXPCRD_RST#
DETECT

<28>
SER_SHD
<28> EXPCRD_RST#

GND
GND
GND
GND
GND
GND

178
180
182
174
171
170

P2

167

DOCK_ID <20>

176
169
175
179
181
177

GND
GND
GND
GND
GND
GND

165

G2

166

DLINE_IN_L
DLINE_IN_R

DLINE_IN_L <25>
DLINE_IN_R <25>

DLINE_OUT_L
DLINE_OUT_R

DLINE_OUT_L <26>
DLINE_OUT_R <26>

PCIE_TXP4

PCIE_TXP4 <20>

PCIE_TXN4

PCIE_TXN4 <20>

PCIE_C_RXP4

1 R1346 2PCIE_RXP4
0_0402_5%
1 R1347 2PCIE_RXN4
0_0402_5%

PCIE_C_RXN4

CLK_PCIE_DOCK

+3VS

PCIE_RXN4 <20>

CLK_PCIE_DOCK# <15>

PREP#
VA_ON#

PREP#
1

<20,23,25>

R66
1K_0402_5%

C59

+5VS

0.1U_0402_16V4Z

C555
1

RING

@ 1000P_0402_50V4Z
2
@1000P_0402_50V4Z
2
@ 1000P_0402_50V4Z
2

168

TIP

DOCK_MOD_TIP

D65
@ PACDN042_SOT23~D

@ 10K_0402_5%

DOCK_ID

ADP_SIGNAL

R1401
2

V_3P3_LAN

2
1
10K_0402_5%

+3VS

LAN_ACT#_DOCK

R527

DOCK_ADP_SIGNAL 1

1K_0402_1%

Q62
RHU002N06_SOT323

2
G

LAN_ACT#

+3VS
1

0.1U_0402_16V4Z
U52
5 VCC
<9> INTEL_BLUE
<16>
BLUE

INTEL_BLUE
BLUE

1
2

A
B

<20> ISO_PREP#

ISO_PREP#

OE

C365

0.1U_0402_16V4Z
U51
5 VCC
<9> INTEL_GREEN
<16>
GREEN

INTEL_GREEN
GREEN
ISO_PREP#

GND

FSA66P5X_SC70-5

1
2

A
B

OE

GND

1
0.1U_0402_16V4Z
U50

<9> INTEL_RED
<16>
RED

VCC

INTEL_RED
RED

1
2

A
B

ISO_PREP#

OE

GND

FSA66P5X_SC70-5

+3VALW
Q63
RHU002N06_SOT323

2
G
S

LANLINK_STATUS#

10K_0402_5%
PWR_LED

2
G
Q59
RHU002N06_SOT323

<20,22,24,25,26,30,33,40,41>

Compal Secret Data

Security Classification
2005/05/26

2006/07/26

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

<24,30,31> STB_LED#

FSA66P5X_SC70-5

Issued Date

R526

LANLINK_STATUS# <20,22,23>

C366

LAN_ACT# <22,23>

LANLINK_STATUS#_DOCK

+3VS

C360
2

PCIE_RXP4 <20>

CLK_PCIE_DOCK <15>

CLK_PCIE_DOCK#

JAE_SP03-14588-PCL03

R1387
3

KBD_DATA <30>
KBD_CLK <30>
CPPE#
<15,18>
PS2_DATA <30>
PS2_CLK <30>
DOCK_HPS# <26>

@ 22U_1206_10V4Z
DOCK_MOD_RING

JAE_SP03-14588-PCL03

C746
INTEL_RED
1
C747
INTEL_GREEN 1
C748
INTEL_BLUE 1

KBD_DATA
KBD_CLK
CPPE#
PS2_DATA
PS2_CLK
DOCK_HPS#

R1404
R1428
R1429

MDO3+
MDO3-

INTEL_RED
INTEL_GREEN
INTEL_BLUE

D_DDCDATA
D_DDCCLK
DVI_DETECT

MDO3+
MDO3-

128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164

<16>
D_VSYNC
<16>
D_HSYNC
<16> D_DDCDATA
<16> D_DDCCLK
<16> DVI_DETECT

DETECT

128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164

MDO0+
MDO0-

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45

MDO2+
MDO2-

46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82

<23>
<23>

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45

ON/OFF#

46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82

MDO2+
MDO2-

P1

LPTACK#
LPTBUSY
LPTPE
LPTSLCT
LPD7
LPD6
LPD5
LPD4
LPD3
LPD2
LPD1
LPD0
LPTSLCTIN#
LPTINIT#

<28>
LPTACK#
<28>
LPTBUSY
<28>
LPTPE
<28>
LPTSLCT
<28>
LPD7
<28>
LPD6
<28>
LPD5
<28>
LPD4
<28>
LPD3
<28>
LPD2
<28>
LPD1
<28>
LPD0
<28> LPTSLCTIN#
<28>
LPTINIT#

DOCKVIN

ON/OFF#

G1

173

<31>
<23>
<23>

172

SLP_S3#

Compal Electronics, Inc.

Docking CONN.
Document Number

Rev
1.0

LA-2952P
Sheet

Friday, April 28, 2006

E

32

of

47

+1.8V to +1.8VS Transfer

VRAM
+1.8V

VDD_MEM18
U10
1
2
3
4

S
S
S
G

+5VALW
1

SI4800DY_SO8
2 10U_0805_10V4Z

C160

C170

D
D
D
D

C91

10U_0805_10V4Z
+VCC_CORE

RUNON

R135
2

+VCCP

100K_0402_5%
2

C171

0.1U_0402_16V4Z

0.1U_0402_16V4Z

<27,32>

C184
+VCCP

<20,41> SLP_S5#

0.1U_0402_16V4Z
C93
+1.5VS

SLP_S5

SLP_S5

+1.5VS

SLP_S5# 2
G
Q22
RHU002N06_SOT323

8
7
6
5

+1.8V

0.1U_0402_16V4Z

+3VALW to +3VS Transfer

+5VALW to +5VS Transfer

+3VALW
+5VALW

+5VS

+3VS

B+

U13

SI4800DY_SO8
2 10U_0805_10V4Z

C71

C127

S
S
S
G

10U_0805_10V4Z

1
2
3
4

C132

+3VL
1

330K_0402_5%
C77

D
D
D
D

C128

R125

SI4800DY_SO8
2 10U_0805_10V4Z

10U_0805_10V4Z

100K_0402_5%

RUNON
1

RUNON
J34

8
7
6
5

0.1U_0402_16V4Z
R469

SLP_S3

470_0402_5%

D
2

SLP_S3 2
G
Q18
RHU002N06_SOT323

1
3

SHORT PADS

1 2

0.1U_0402_16V4Z

<20,22,24,25,26,30,32,40,41>

C120

SLP_S3#

S
2

0.01U_0402_25V7Z

SLP_S3# 2
G
Q19
RHU002N06_SOT323

R139

1
2
3
4

C86

S
S
S
G

D
D
D
D

U9
8
7
6
5

Discharge circuit
+1.8V
1

VDD_MEM18

+2.5VS

+1.5VS

+5VS
R134

R188

R1310

R95

R130

470_0402_5%

470_0402_5%

470_0402_5%

470_0402_5%

+0.9V
1

PWR_GD <30,34,42,43>

+3VS

R116

R151

2
0_0402_5%

R1312

470_0402_5%

SLP_S3 2
G
Q47
RHU002N06_SOT323

1 2

SLP_S3 2
G
Q16
RHU002N06_SOT323

1 2

2
SLP_S3 2
G
Q17
RHU002N06_SOT323

470_0402_5%

SLP_S3 2
G
Q21
RHU002N06_SOT323

1 2

SLP_S3 2
G
Q14
RHU002N06_SOT323

1 2

SLP_S5 2
G
Q90
RHU002N06_SOT323

1 2

2
G

2
@ 0_0402_5%

1 2
SLP_S5 1
R1311
SLP_S3

470_0402_5%

Q27
RHU002N06_SOT323

Compal Secret Data

Security Classification
2005/05/26

Issued Date

2006/07/26

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.

DC/DC Circuits
Document Number

Rev
1.0

LA-2952P
Friday, April 28, 2006

Sheet
E

33

of

47

VDD_MEM18

+3VS

+3VS

+3VL

+3VL

+3VL

E
Q11
PMST3904_SOT323

14

+3VS

0.1U_0402_16V4Z
1
1

+5VS

1
100K_0402_5%

SN74LVC14APWLE_TSSOP14

+3VL

VCC1_PWRGD <30>
U5D

C48

10K_0402_5%

R24

R47

2
G

2
B

C26

SN74LVC14APWLE_TSSOP14
Q10
PMST3904_SOT323

2
B

+3VL

P
3

1
2
47K_0402_5%

D8
CH751H-40_SOD323
1
2

U5B

C
1

R38

U5A

R7

330_0402_5%

14

R281

330_0402_5%

14

R82

1K_0402_5%

R89

+3VL

SN74LVC14APWLE_TSSOP14

Q3
RHU002N06_SOT323

0.1U_0402_16V4Z

10K_0402_5%
C25
J32
R43

0.1U_0402_16V4Z

14

U5C

2
G

560K_0402_5%

PWR_GD

PWR_GD <30,33,42,43>

C47

SN74LVC14APWLE_TSSOP14

Q9
RHU002N06_SOT323

0.1U_0402_16V4Z

R37

SHORT PADS

180K_0402_5%

+2.5VS

+2.5VS

+3VL
FM1

O
7

SN74LVC14APWLE_TSSOP14

H1
HOLEA

H3
HOLEA

CF10
1

H4
HOLEA

CF11
1

H5
HOLEA

CF12
1

H6
HOLEA

CF13
1

CF14

H7
H8
HOLEAHOLEA

H9
HOLEA

H14
HOLEB

H13
HOLEB

H12
HOLEB

1
H11
HOLEB

H15
H16
H17
HOLEC HOLEC HOLEC

O
NC

4
1

PGD_IN

U63
<42>

SN74LVC1G17DBVR_SOT23-5

2005/05/26

Deciphered Date

2006/07/26

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

H37
HOLED

H36
HOLED

H35
HOLED

H34
HOLED

H25
HOLED

H24
HOLED

H33
HOLED

Compal Secret Data

Security Classification

H23
HOLED

H22
HOLED

H32
HOLED

H27
H28
HOLED HOLED

Issued Date

H21
HOLED

H19
H20
HOLED HOLED

H18
HOLED

0.1U_0402_16V4Z

R1303
1
2
@ 0_0402_5%

SN74LVC1G17DBVR_SOT23-5

R1350
1
2
150K_0402_1%

C990

PGD_IN

4
1

C992

CLK_ENABLE#

O
NC

0.47U_0603_10V7K

5
<15,42> CLK_ENABLE#

U62

R1402
1
2
@ 0_0402_5%

P
2

D60
CH751H-40_SOD323
1
2

R123
1
2
0_0402_5%

PWR_GD

+3VS

Need be tune to
3msec time delay

H2
HOLEA

PMST3904_SOT323

CF9
1

PMST3904_SOT323

+3VS

C991

CF8
1

Q2
RHU002N06_SOT323

2
G

H10
HOLEB

0.1U_0402_16V4Z

FM4
1

1
Q15

2
B

VCCP_POK

Q26
E

10

C
2
B

CF7
U5E

330_0402_5%
11

<40>

FM3

R283
14

R113
330_0402_5%

R122
1K_0402_5%

FM2
1

+1.5VS

Compal Electronics, Inc.

POK CKT
Document Number

Rev
1.0

LA-2952P
Friday, April 28, 2006

Sheet

34

of

47

VIN

AC
Adapter
in

LM358
Thermal
Protector

VS

G965
LDO
(2.5V)

+3VS

+5VALWP
SWITCH

ACOK

MAINPWON

VL

+3VALWP

ENBL2 ENBL1

4A
+5VS

B+

+2.5VS 1A

MAX8734A
DC/DC
(3V/5V)

VCC

+5VALWP

VMB

B+

SHDN#

4A

VIN

ISL6260 &ISL6208
DC/DC
(CPU_CORE)

VS
+3VLP 0.1A
BQ24703
Charger

MAX8743
DC/DC
(1.05V/1.5V)

B+
B

SLP_S3#

PWR_GD

+1.5VSP 4.2A
CPU_CORE
( 44A)
+1.05V_VCCP 6.4A

ENBL1/ENBL2

+5VALWP

BATSELB_A

Battery
Selector
Circuit

BATSELB_A#

Battery A
6 Cell

VCC

Battery B
8 Cell

B+
VMB
SWITCH

SWITCH

SWITCH

Battery
Connector
A

VMB_A

VMB_B

Battery
Connector
B

SLP_S5#

TPS51116
DC/DC
(+1.8VP/+0.9VSP)

+1.8VP 7A

+0.9VP 2A

S3/S5

BATT
Title

BATT_A

POWER BLOCK DIAGRAM

BATT_B

Size
Date:

Document Number
Friday, April 28, 2006

Rev
Sheet

35
1

of

47

ADP_SIGNAL

PCN1

GND2
GND1

PWR2

ADPIN

FOX_JPD113E-LB103-7F

AB/I_A

PC2
1000P_0402_50V7K

GND3

4
3

PR1
15K_0402_5%

PWR1

PC4
1000P_0402_50V7K
2
1

GND4

PC3
100P_0402_50V8J
2
1

VIN
PL1
FBM-L18-453215-900LMA90T_1812

GND5

SINGAL

GND6

PC1
100P_0402_50V8J

<38>
VMB_A

BATT_A

PL2

PCN2

PR2

1
1M_0402_1%

1
2
PR10
210K_0402_1%

PC5
1000P_0402_50V7K

PC6
0.01U_0402_50V4Z

+3VL

PR3
1K_0402_5%

TYCO_C-1746706_6P

GND

EC_SMD_A
EC_SMC_A

2
3
4
5

SMD
SMC
RES
TS

BATT+

FBM-L18-453215-900LMA90T_1812
1
2

AB1A_DATA <30>

EC_SMC_A1

AB1A_CLK <30>

EC_SMD_A1

PC145
220P_0402_25V8K

THM_MAIN# <30>

PC144
220P_0402_25V8K

PC143
220P_0402_25V8K

PR4
PR5
100_0402_5% 100_0402_5%

VMB_B

GND

EC_SMD_B
EC_SMC_B
AB/I_B
TS_B

PC8
1000P_0402_50V7K

PC9
0.01U_0402_50V4Z

SUYIN_20163S-06G1-K

PR7 1
2
1K_0402_5%
1
2
+3VL
PR9
PR11
210K_0402_1%
1K_0402_5%

BATT_B

2
3
4
5

SMD
SMC
B/I
TS

PL3
FBM-L18-453215-900LMA90T_1812
1
2

BATT+

PCN3

PR14
100_0402_5%

PR15

THM_MBAY# <30>

100_0402_5%
EC_SMD_B1

AB1B_DATA <30>

EC_SMC_B1

AB1B_CLK <30>

Compal Secret Data

Security Classification
Issued Date

2005/03/10

Deciphered Date

2006/03/10

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

BATTERY CONN
Rev

LA-2952P

Date:

Sheet

Friday, April 28, 2006

D

36

of

47

VIN

P2

BATT
PQ2
AO4407_SO8

P4
1
2
3
P2

CHG_B+

REF

ANODE

CATHODE
NC

NC

3
2
1

1
2

PC20
10U_1206_25V6M

PC19
4.7U_1206_25V6K

1
PR32
3K_0402_1%
2
1
2

PR31
3K_0402_1%

2
S
PR52
7.87K_0402_1%

1 2

RHU002N06_SOT323
2
G

D
PR53
2.8K_0603_0.5%

PQ8
2 RHU002N06_SOT323
G

1 2

PQ9
D

PR266
39.2_0402_1%

2
S

RHU002N06_SOT323

CELLSEL# <38>

Compal Secret Data

Security Classification
Issued Date

2005/03/10

Deciphered Date

2006/03/10

Title

Compal Electronics, Inc.

Charger

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

LMV431ACM5X_SOT23-5

Rev

LA-2952P

Date:

2
1
PC28
100P_0402_50V8J
1
2

1
2

1
D

CV=12.6V(6 CELLS LI-ION)

16.8V(8 CELL LI-ION)
CC=3A for 2.4AHr
CC=3.57A for 2.55AHr

PR44
7.68K_0603_0.1%

PR48
27K_0402_1%

<38>

2
S

RHU002N06_SOT323

PQ11
2
G

Icharger=3A
CELLSEL# =0,Vcharger= 12.6V
CELLSEL# =1,Vcharger= 16.8V

12
1

1.24VREF
3

PU5
4

PQ10
2
G

AC_CHG

1
2
2

33K_0402_1%

<38>

PR49
100_0402_5%

PR54

PR51
@47K_0402_1%

AC_CHG

LM393M_SO8

ALARM

BQ24703VREF
7

VL

Airline detector
High 17.521V
Low 16.871V

1
2

O
-

2
100K_0402_5%

PR41
100K_0603_0.1%

PR42
174K_0603_1%

PR47
1

PC27
@0.1U_0402_16V7K

PC22
1

PR38
866K_0603_1%

+3VL

PU3B

PC29
0.022U_0402_16V7K
2
1

1
2

10K_0603_1%

PD8
SKS30-04AT_TSMA

BATT

PR43
4.7K_0402_5%

2
1M_0402_5%

BATT

1
2

8.2UH_MPL73-8R2_4A_20%

PR35
150_0402_1%

LM393M_SO8

+3VL

PR50

LX_CHG

0.1U_0402_16V7K

PU4
SN74LVC1G17DBVR_SOT23-5
ADP_PRES <22,30,38,39,43>
O 4
NC 1

PR46
PR45
130K_0402_1%

6
1
17
23
14

PR28
0.015_2512_1%
1
2

PL5

SE_CHG-

1
5
I
G

BATSET
BATDEP
GND
NC4
NC3

PQ7
SI4835BDY_SO8

BATT

COMP
NC1
NC2

18
20

DH_CHG

SE_CHG+

PC25
0.1U_0402_10V6K

PU3A

PR39
2.15K_0402_1%
1
2

2
1
PR37
10K_0402_1%

VL

1
PR36
2
1
PR40
2

2
330K_0402_5%

12.4K_0603_1%

AC detector
High 11.689V
Low
9.879V

100K_0603_1%

1
3

+3VL

7
10
11

VS
VHSP

ACDRV#

+3VL

ENABLE
ACSEL
ALARM
SRSET
ACSET
ACPRES
IBAT
VREF

25
22
21
16
15
12
24

BQ24703_QFN28

150P_0402_50V8J
PC24
2
1

1
2
1

PC23

PR34

P2

1U_0603_6.3V6M
2
1

ACDET

PR33
PR30
80.6K_0402_1%
100K_0402_1%
2
1

2 PR27
1
+3VL
100K_0402_5%
BQ24703VREF

PR29
133K_0402_1%

2
1

PC18
1

1U_0603_6.3V6M

2
191K_0402_1%

CHGCTRL

5
28
19
2
3
27
13
4

ACDRV#
VCC
PWM#
SRP
SRN
BATP
BATDRV#

PR26
1
<30,38>

2 PR25
1
1K_0402_1%
ALARM

ACN
ACP
ACDET

5
6
7
8

AC_CHG

PU2
8
9
26

<43>

SRSET

PD5
RLZ16B_LL34

1 2

1SS355_SOD323

PC17
1U_0805_25V4Z

<43>

PC26
4.7U_0805_10V6K

ADP_EN#

PC21
4.7U_0805_6.3V6K

PC16
1U_0603_6.3V6M
1
2
PR24
1K_0402_1%

PR23
0_0402_5%
2
1
1

2
1

PD7

ADP_PRES

PC15
4.7U_1206_25V6K

<43>

PR22
100_0402_1%

PC14
10U_1206_25V6M

PR19
1
2
0_0402_5%

ACN

PR21
150K_0402_5%

PR17
0_0402_5%
1
2

PL4
FBM-L11-322513-151LMAT_1210
1
2

ACDRV#

PR20
0.015_2512_1%
1
2

8
7
6
5
4

B+

PR16
200K_0402_5%

8
7
6
5

8
7
6
5

PQ4
AO4407_SO8
1
2
3

1
2
3

0.1U_0603_16V7K
2
1

47K

47K

PC13
47P_0402_50V8J
1
2
2

PR18
1

PC12
1

PQ5
DTA144EUA_SC70
1

47K_0402_5%
2

PQ3
AO4407_SO8

Sheet

Friday, April 28, 2006

D

37

of

47

PC32
1

PQ13
RHU002N06_SOT323
1

2
1

PU8
Y

BATT

SN74LVC1G14DCKR_SC70-5

D
D
PQ16
RHU002N06_SOT323

2
G

ADP_PRES <22,30,37,39,43>

<30>

PR263
330K_0402_5%

CFET_B

PQ76
2
G
RHU002N06_SOT323

2
G

PR264
330K_0402_5%

1
2
2
1
2
2

PR72
470K_0402_5%

PR73
4.7K_0402_5%

SKS30-04AT_TSMA
2
PQ29
RHU002N06_SOT323

2
G

RHU002N06_SOT323
BATT_IN 2
G
RHU002N06_SOT323

RHU002N06_SOT323

330K_0402_5%

PQ75
2
G

PQ30

BATT_IN

PR262
1

BATT_B

SN74LVC1G17DBVR_SOT23-5

AB/I_A

<43>

Compal Secret Data

Security Classification
Issued Date

2005/03/10

Deciphered Date

2006/03/10

Title

Compal Electronics, Inc.

Battery selector

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2005.8.26

Rev

LA-2952P

Date:

PR67
470K_0402_5%

2
1SS355_SOD323

PQ31

I_A
<36>

1
2
3

PD15

+3VL
1

BATCON

8
7
6
5

CFET_B

1
4
1

1
2

RB715F_SOT323

PU13
O
NC

5
2

CFET_B

CFET_A

PR77
100K_0402_5%

PQ32
2
G

BATT_A

CFET_B

+3VL
I_A#

10K_0402_5%
<43>

CELLSEL#

RHU002N06_SOT323

CELLSEL#

<37>

8
7
6
5

RHU002N06_SOT323
3

+3VL

PQ28
2
G

PD16

PQ22
AO4407_SO8
PQ25
AO4407_SO8

PR75
1

PR76
100K_0402_5%

PR66
470K_0402_5%

3
2
1

SN74AHC1G08DCKR_SC70

PQ26
PMBT2222_SOT23

2
4

IN2

+3VL
ADP_PRES

PD17

1
2
3

1
1

IN1

C
2
B

PR74
10K_0402_5%
1

1 2

BATSELB_A#

PQ27

RHU002N06_SOT323

AC_CHG

<37>

5
6
7
8

PQ21
AO4407_SO8
PQ24
AO4407_SO8

PU12

PR71
10K_0402_1%

BATT

PR68
470K_0402_5%

PR69
220K_0402_5%
1
2

I
3

1
2
PR70
470K_0402_5%

5
P
0.22U_0402_10V4Z

PC35
1

1
1SS355_SOD323

SN74LVC1G17DBVR_SOT23-5
PU11
O 4
NC 1

5
6
7
8

3
2
1

+3VL
PD14

RHU002N06_SOT323

+3VL
3

PR64
4.7K_0402_5%

RHU002N06_SOT323

PC34
220P_0402_50V7K

SN74AHC1G08DCKR_SC70
PQ23
BATT_IN 2
G

1
PR63
10K_0402_5%
PQ20
2
G

2
G

PD13
SKS30-04AT_TSMA

2
4

10K_0402_5%

PQ19
RHU002N06_SOT323

PD12
1

IN2

IN1

PR62
470K_0402_5%

1SS355_SOD323
PR65

SN74LVC1G14DCKR_SC70-5

PU10

BATSELB_A

5
P
2

NC

BATSELB_A#

<30> BATSELB_A#

PU9

PQ17
RHU002N06_SOT323
BATT_IN 2
G

PQ18
PMBT2222_SOT23

1
PR61
470K_0402_5%
+3VL

CFET_A

PD11
RLZ6.2C_LL34

2
B

CHGCTRL

PR58
1.5M_0402_5%

+3VL

30,37>

BATT_IN
PD10
1SS355_SOD323

2
G

2
0_0402_5%

1000P_0402_50V7K

1
2
PR60
22K_0402_5%

PQ15
RHU002N06_SOT323

3 1

+3VL

2
PC33

2
G

NC

1
2
PR59
22K_0402_5%

+3VL

PQ14
D RHU002N06_SOT323

PR56

1
2
100_0402_5%

RB715F_SOT323

74LVC1G02_04_SOT353

PR55

G
74LVC1G02_04_SOT353

INA

INA

PQ12
RHU002N06_SOT323

2
3

PD9

BATT_B
4

2
G

PU6

INB

P
O

1000P_0402_50V7K

BATSELB_A#

1
4

PU7

INB

PC31
BATSELB_A

ALARM

2
PR57
47K_0402_5%

<37>

+3VL

BATT_A

0.1U_0603_50V4Z

PC30
1

@0.1U_0402_10V6K

+3VL

Sheet

Friday, April 28, 2006

D

38

of

47

+3.3V/+5V

B+

PD18
CHP202U_SC70

1
PR97
499K_0402_1%

1
2
1

1
2 1
2
PR87
PR84
499K_0402_1% 200K_0402_1%

DL3

PL8
4.7UH_SIQB74-4R7_3A_30%

DH3

7
2

100K_0402_5%
PR242
1

+3VALWP

+3VLP

1
+
2

+3VL

PJP1
2

PC49
150U_B2_6.3VM

2
2 1
1

2
PR95
0_0402_5%

+3VLP

PR96
PR94
0_0402_5% @ 3.57K_0402_1%

PRO#

+3VALWP

1
2

LX3

PR85
0_0402_5%

28
26
24
27
22

PR98
100K_0402_5%

PAD-OPEN 2x2m

PC52
0.1U_0603_16V7K
PQ36
RHU002N06_SOT323

3HG

10

25

GND
23

11

+3VL

8
7
6
5

AO4916_SO8

D2
G2
D2
D1/S2/K
G1
D1/S2/K
S1/A D1/S2/K

BST3A

1
2

VL

PC50
0.22U_0603_10V7K

MAINPWON

PC51
4.7U_0805_10V4Z
2
1

PR90
47K_0402_5%
2
1
PC48
0.1U_0603_25V7K

LDO3

V+

2 1
2
PR86
PR83
499K_0402_1% 200K_0402_1%

1
2
ILIM3

PC44
1U_0805_16V7K

17

LX5
PU14
DL5
ILIM5
OUT5 MAX1999EEI_QSOP28
FB5
BST3
N.C.
DH3
DL3
SHDN#
LX3
ON5
OUT3
ON3
FB3
SKIP#
PGOOD

VCC

DH5

15
19
21
9
1

REF

PC46
2
1
0.1U_0603_50V4Z
13

BST5

2VREF_1999 1
2
PR89
0_0402_5%
12
1
2
@ 0_0402_5%
2VREF_19998
PR91
PR93
1
2
0_0402_5%

1
2
3
4

2VREF_1999

16

6
4
3

2
1

2
1

PR92
0_0402_5%

PR88
10.2K_0402_1%

B++

PQ35
PC42
4.7U_1206_25V6K

1
2

+5VALWP

PR82
0_0402_5%

14

LD05

BST5A

18

PC45
4.7U_0805_10V4Z
2
1

PL7
10UH_D104C-919AS-100M_20%
2
1

DL5

20

VL

<43> LX_5V

4.7U_1206_25V6K

PC43
2
1

LX5

PC47
150U_B2_6.3VM

PC40
0.1U_0603_16V7K

PC41
2200P_0402_50V7K

PR81
4.7_1206_5%

AO4916_SO8

B++

B++

PR79
0_0402_5%

DH5

PR80
47_0402_5%

8
7
6
5

TON

D2
G2
D2
D1/S2/K
G1
D1/S2/K
S1/A D1/S2/K

1
2
3
4

PR78
0_0402_5%
5HG 1
2

PQ34

PC37
0.1U_0603_50V4Z
1
2

BST3B

VL

PC39
10U_1206_25V6M

BST5B

PC36
0.1U_0603_50V4Z
1
2

B++

PC38
2200P_0402_50V7K
2
1

PL6
FBM-L18-453215-900LMA90T_1812

2
G
1

RHU002N06_SOT323
PQ37
2
G

KBC_PWR_ON <30>

RHU002N06_SOT323
PQ77
2
G

ADP_PRES <22,30,37,38,43>

Compal Secret Data

Security Classification
2005/03/01

Issued Date

2006/03/01

Deciphered Date

Title

3.3V / 5V

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Document Number

Rev
1.0

LA-2952P
Sheet

Friday, April 28, 2006

E

39

of

47

PL9
FBM-L11-322513-151LMAT_1210
2
1

PR99
0_0402_5%

2
1

1
2

PC58
4.7U_1206_25V6K
PC66
220U_B2_2.5VM

1
2

+5VALW

S
PQ41
RHU002N06_SOT323

PR117
100K_0402_1%

2
G
D

2
G
PQ42

Fine tune power sequenceRHU002N06_SOT323

+3VALW

PQ44
RHU002N06_SOT323

PJP11
PAD-OPEN 2x2m

PC70
@0.001U_0402_50V7M

PR115
47K_0402_5%
2
1

1
PR121
0_0402_5%

SLP_S3# <20,22,24,25,26,30,32,33,41>

+2.5VSP
VIN

VO

EN

ADJ

GND

GND

GND

GND

PR244
13K_0603_1%

PR243

PU26

1
PC134
10U_1206_6.3V6M

SLP_S3#

1
1

PQ43
RHU002N06_SOT323

PR109
@0_0402_5%
2
1

VCCP_POK <34>

PR112
100K_0402_5%
2
1

PR114
0_0402_5%
PC69
0.22U_0603_10V7K

1
1

1
PR108
0_0402_5%

2
G

PR123
0_0402_5%

1.5VSP/ +1.05V_VCCP/+2.5VALWP

PR120
0_0402_5%

2
G

PC71
@0.001U_0402_50V7M

<20,22,24,25,26,30,32,33,41> SLP_S3#

1
@0_0402_5%
PR116

PR122
47K_0402_5%
1
2

+5VALW

PR113
0_0402_5%
2
1
2

VCC_MAX8743

REF

2VREF
PR119
100K_0402_5%
2
1

PR118
100K_0402_1%

23

MAX8743EEI_QSOP28

DL_1.5V

13
3

ILIM2
ILIM1

DH_1.5V_2

LX_1.5V

7
5

ON1

PR104
0_0402_5%
2

+1.5VSP

PL11
3.3UH_SIQB74-3R3_4.8A_30%
1
2

PQ39

PC61
22

9
UVP

15
14
12

PGOOD
TON
SKIP

11

FB1

OVP

SLP_S3#

PR110
@0_0402_5%
1
2

OUT2
FB2
ON2

PC62
0.1U_0603_50V4Z
1

8
7
6
5

DH_1.5V_1

CS1
OUT1

BST2
DH2
LX2
DL2
CS2

19
18
17
20
16

28
1

21

LX1
DL1

VDD

DH1

27
24

2
PR107
100K_0402_1%

1
2

2
26

10

1
2
3
4

LX_1.05V
DL_1.05V

BST1

GND

S
S
S
G

PR103
2.2_0402_5% DH_1.05V_1

25

VCC

PU15

PR102
0_0402_5%
1
2

D2
G2
D2
D1/S2/K
G1
D1/S2/K
S1/A D1/S2/K

PR111
10K_0402_1%

2
1

VCC_MAX8743
4
V+ 1U_0805_16V7K
2
1

PR101
0_0402_5%

8
7
6
5

DH_1.05V_2

1
2
3
4

BST_1.05V_1

D
D
D
D

PQ40
AO4702_SO8
PR106
5.1K_0402_1%

1
2

+
2

PC64
2.2U_0603_6.3V6K
1

BST_1.5V_1

PC63
220U_B2_2.5VM

AO4916_SO8

BST_1.5V_2
1

PC60
0.1U_0603_50V4Z
2
1

+1.05V_VCCP

1
2
3
4

PL10
3.3UH_MPL73-3R3_6A_20%

PC55
4.7U_1206_16V4Z

PC59
0.1U_0603_50V4Z

BST_1.05V_2

8
7
6
5
D
D
D
D

CHP202U_SC70

S
S
S
G

PQ38
AO4422_SO8

PR100
20_0603_5%

PR105
5.1K_0402_1%

1U_0805_50V4Z
PC56
PD19

PC57
2200P_0402_50V7K

B+

+5VALW
2

PC53
2200P_0402_50V7K
2
1

PC54
10U_1206_25V6M

MAX8743_B+

PC135
10U_1206_6.3V6M

G965-18P1U_SO8

PJP3
+1.5VS

+5VALWP

<20,22,24,25,26,30,32,33,41> SLP_S3#

+5VALW

(4A,160mils ,Via NO.=8)

PAD-OPEN 3x3m

PR245
12K_0402_1%

10K_0402_5%
1
2

(4.5A,180mils ,Via NO.= 9)

PAD-OPEN 4x4m
PJP5

(7A,280mils ,Via NO.= 14)

+1.05V_VCCP

PJP2
+1.5VSP

+3VALWP

+3VALW

(3A,120mils ,Via NO.= 6)

PAD-OPEN 4x4m

PJP6
PAD-OPEN 4x4m
1
2

+VCCP

(6A,240mils ,Via NO.= 12)

PJP8
+0.9VP

PJP9
2

+0.9V

(2A,80mils ,Via NO.= 4)

+2.5VSP

+2.5VS

(1A,40mils ,Via NO.= 2)

PAD-OPEN 2x2m

PAD-OPEN 3x3m

Compal Secret Data

Security Classification
Issued Date

2005/03/10

Deciphered Date

2006/03/10

Title

Compal Electronics, Inc.

2.5VALW/1.5VS/1.05VCCP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev

LA-2952P

Date:

Sheet

Friday, April 28, 2006

D

40

of

47

DDR_B+

PL12
FBM-L11-322513-151LMAT_1210
2
1

4
3
2
1

LL

20

DRVL

19

PGND

18

CS

16

V5FILT

14

PGOOD

13

S5

11

S3

10

DL_1.8V

PQ46
AO4702_SO8

VDDQSNS

VDDQSET

1
2

PC82
4.7U_0805_10V6K

15

V5IN

Thermal pad

CS_GND
17

PR131
0_0402_5%
2
1
PR132
@ 0_0402_5%
2
1
PR133
0_0402_5%
2
1

TPS51116RGE_QFN24

COMP

4
3
2
1

VTTREF

PR129
20K_0603_1%

MODE

GND

PC83
0.001U_0402_50V7M

25

PR127
0_0402_5%
1
2

+5VALW

VTTSNS

G
S
S
S

PC79
22U_1206_6.3V6M

PC81
0.033U_0402_16V7K

<7,13,14> V_DDR_MCH_REF

2
PL13

PR130
3_0402_5%
2
1

14K_0402_1%
PR128
2

VTTGND

+1.8V

2.2UH_IHLP-2525CZ-01_8A_+-20%_2525CZ

D
D
D
D

PC73
10U_1206_25V6M

DH_1.8V_2

LX_1.8V

21

PC80
22P_0402_50V8J

DRVH

B+

PC78
330U_D2E_2.5VM

VTT

22

PC72
2200P_0402_50V7K
2
1

5
6
7
8
VBST

5
6
7
8

24

VLDOIN

PC74
0.1U_0603_50V4Z
BST_1.8V_2 1
2

G
S
S
S

D
D
D
D
23

PR125
0_0402_5%
BST_1.8V_1
1
2
PR126
0_0402_5%
DH_1.8V_1
1
2

PU17

NC

NC

PC76
10U_0805_10V4Z

+0.9VP

PQ45
AO4422_SO8

PC75
10U_0805_10V4Z

12

1
2

PR124
0_1206_5%

+1.5VS

+5VALWP

SLP_S5# <20,33>
B

SLP_S4# <20>
SLP_S3# <20,22,24,25,26,30,32,33,40>

PR134

SLP_S5# <20,33>

PC85
@0.001U_0402_50V7M

10K_0402_1%
PR135
2

1
2

1
2

PC84
@0.001U_0402_50V7M

2
1
@0_0402_5%

Compal Secret Data

Security Classification
Issued Date

2005/03/10

Deciphered Date

2006/03/10

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.

1.8V/0.9VS
Document Number

Rev

LA-2952P
Friday, April 28, 2006

Sheet
1

41

of

47

PQ50
SI7840DP_SO8
+CPU_B+
PR148
0_0402_5%
2
1

VCC

BOOT

1
8

DH_CPU1

PWM PHASE

LX_CPU1

GND

FCCM UGATE

2
3

PL16

VCC

BOOT

FCCM UGATE

DH_CPU2

PWM PHASE

LX_CPU2

GND

35

VR_ON

12

VSEN

13

RTN

11

VDIFF

10

FB

PGOOD
25

ISEN3

21

1000P_0402_50V7K
PR188
2
1
6.98K_0402_1%

.36UH_MPC1040LR36_ 24A_20%
1

+VCC_CORE

+5VS

PQ57
FDS6676AS_SO8

S
S
S
G

D
D
D
D

8
7
6
5
1
2
3
4

PQ56
FDS6676AS_SO8
1 S
D 8
2 S
D 7
3 S
D 6
4 G
D 5

PC117
0.22U_0603_16V7K
2
1

PR173
5.11K_0402_1%

2 PR175

@0_0402_5%
VSUM

VO

DL_CPU2

PR181
2
1
11.5K_0402_1%

VO

VSUM

PR191
1K_0402_1%
2
1

PR190
6.19K_0603_1%
2
1

17

PC127
1

VSUM

PR170
10K_0402_1%
1
2

PR167
10_0402_1%

PR185
3K_0402_1%

VW

LGATE

PC125
1

220P_0402_25V8K

40

39

18

2
1
0_0402_5%
PWM3

PR189
@1K_0402_1%

1
2
2 PR187
51K_0603_1%
PC121
0.022U_0402_16V7K

COMP

DROOP

2 PR184 1
1.2K_0402_1%

PR183
2
1
0_0402_5%

PC113
10U_1206_25V6M

PL17

PR177

OCSET

14

PR182
PC120
180_0603_1% 1800P_0402_50V7K
2
1
1
2

24

1000P_0402_50V7K

FCCM

10KB_0603_5%_ERTJ1VR103J

PC119
1

CLK_EN#

38

CS_GND

PGD_IN

PC122
1000P_0402_50V7K

PC118
1

<5> VSSSENSE

ISL6208CRZ-T_QFN8

PSI#

41

ISEN2

0.1U_0402_16V7K

DPRSLPVR

ISEN2

22

PH3

1000P_0402_50V7K

PC124
2

VIN

2
DPRSTP#

PWM2

PC123
0.22U_0603_16V7K
1
2

1
PR179
10_0402_1%

37

PWM2

26

PC116
0.22U_0603_16V7K
1
2

PU20

PC126
2
1

2 PR178
0_0402_5%

VID0
VID1
VID2
VID3
VID4
VID5
VID6

VO

499_0402_1%

<5> VCCSENSE

PR180
10_0402_1%
2
1

ISEN1

16

28
29
30
31
32
33
34

36

2 PR174
0_0402_5%
2 PR176
0_0402_5%

23

PR186
4.53K_0402_1%
2
1

2 PR171
2 PR172
0_0402_5%

ISEN1

PC112
4.7U_1206_25V6K
2
1

SOFT

27

PQ54
SI7840DP_SO8

PC111
2200P_0402_50V7K
2
1

NTC

PWM1

PR157
0_0402_5%
2
1

PC110
0.01U_0402_50V4Z
2
1

ISL6260CRZ-T_QFN40

PWM1

DFB

<30,33,34,43> PWR_GD

+CPU_B+

VGATE

PU19
PR1611
2
0_0402_5%
2 PR163 1
0_0402_5%
2 PR165 1
0_0402_5%
2 PR168 1
0_0402_5%

<34> PGD_IN

+VCC_CORE

VO

3
2
1

RBIAS

15

2 PR169
0_0402_5%

<15,34> CLK_ENABLE#

@0_0402_5%

VGATE_INTEL<7,20>

BST_CPU2_1

2
1
PC115
2
1 470KB_0402_5%_ERTJ0EV474J

2 PR162 1
0_0402_5%
2 PR164 1
0_0402_5%
2 PR166 1
0_0402_5%

H_PSI#

2
PR156
0_0402_5%

PC114
1U_0603_10V6K

NTC

VR_TT#

3
PH2

3V3

19

20

VSS
4

VDD

PR158
0_0402_5%
2
1

<7,20> DPRSLPVR
<5>

2 PR154

0.015U_0402_16V7K

PR153
5.11K_0402_1%

VSUM

BST_CPU2_2

2 PR160 1
4.22K_0603_1%

<4,19> H_DPRSTP#

PC107
0.22U_0603_16V7K
2
1

+5VS

PR159 1
2
147K_0402_1%

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

PR151
10K_0402_1%
1
2

PR150
10_0402_1%

DL_CPU1

NTC

<4> H_PROCHOT#

<5>
<5>
<5>
<5>
<5>
<5>
<5>

+VCC_CORE

8
7
6
5
D
D
D
D

PR155
1.91K_0603_1%

0.01U_0402_16V7K

S
S
S
G

PC108
1U_0603_10V6K
2
1

1
2
3
4

PR152
10_0603_5%
2

+3VS

FDS6676AS_SO8
PQ53

FDS6676AS_SO8
PQ52
1 S
D 8
2 S
D 7
3 S
D 6
4 G
D 5

LGATE

PC109
2
1

.36UH_MPC1040LR36_ 24A_20%

ISL6208CRZ-T_QFN8

+5VS

PC103
10U_1206_25V6M

PC105
0.22U_0603_16V7K
1
2

PU18
5

B+

3
2
1

BST_CPU1_1

PC104
1U_0603_10V6K
2
1

0.01U_0402_25V7K
PC106
2
1

PR149
10_0603_5%

4
BST_CPU1_2

+5VS

PL15
FBM-L18-453215-900LMA90T_1812
1
2

PC102
4.7U_1206_25V6K
2
1

PC101
2200P_0402_50V7K
2
1

PC100
0.01U_0402_50V4Z
2
1

+CPU_B+

PC148
68U_25V_M

330P_0402_50V7K

Compal Secret Data

Security Classification
2005/03/10

Issued Date

Deciphered Date

2006/03/10

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.

CPU_CORE
Document Number

Rev

LA-2952P
Friday, April 28, 2006

Sheet

42
1

of

47

PQ72

PR208
10_0402_5%

2
G
2

PC128
1U_0805_16V7K

PR251
220K_0402_5%
1

2
PQ70
DTA144EUA_SC70

LX_5V

PD28
1SS355_SOD323

<32> ACOCP_EN#

PD24

ADP_SIGNAL

+3VS

PD26

1K_0402_5%

PQ71
2
G

1 2

1SS355_SOD323

PQ74
RHU002N06_SOT323

2
G

ADP_PRES

<22,30,37,38,39>

S
<38>

CFET_B

RHU002N06_SOT323

PR255

PD27
1SS355_SOD323

PQ60
RHU002N06_SOT323

PR253
210K_0402_1%

<4,20>

2 2

OCP#

2
G

1 2
PR254
150K_0402_5%

2
0_0402_5%

<39>

VIN

47K

PC131
2
1

2
PR203
604K_0603_1%

47K

80.6K_0402_1%

D
<38>

I_A

E
PR217
47.5K_0402_1%
1
2

8
P
G

LM393M_SO8

2
B

PR257
10K_0402_5%

PR211

1
2
PR215
470K_0402_5%

ADP_PRES

B+

PQ61
<22,30,37,38,39>
C MMBT3904_SOT323

PU21A

0.027U_0402_16V7K

PD22
@CH751H-40_SOD323
1
2
PWR_GD <30,33,34,42>

2
0_0402_5%

PR261
1M_0402_1%

PR212
0_0402_5%

LM393M_SO8

PR207
3.9K_0402_5%

NDS0610_SOT23
PQ73

2
LMV431ACM5X_SOT23-5

3
7

PR205
2

1
PR260
39.2K_0402_1%
3 2

1
1

422_0603_1%

NC

ANODE

7.87K_0402_1%

PR206

2
2

NC

PR210

0.1U_0402_16V7K

PC132
2
1

CATHODE

PR201

PU23

PC130
1U_0805_50V4Z

PC129
0.22U_0603_16V7K

REF

LM358A_SO8

8
0

PR199
10K_0402_1%

2
PR200
100K_0603_0.5%

10K_0402_5%

PU21B

2
6.81K_0402_1%
2
1

PR202
2K_0402_5%
3
2
1
PQ58
MMBT3906_SOT23
1

2
PD21
CH751H-40_SOD323

100K_0402_5%

PR197

PR192
133K_0402_1%

PR256

PU22B

PR193

1
2
PR195
2

LM358A_SO8

PR194
330K_0402_5%
2
1

P4

0_0402_5%

8
P

2
PR196
0_0402_5%

0
G

PU22A

+5VS
PR259
1M_0402_1%

+5VS

NDS0610_SOT23

PD20
CH751H-40_SOD323
1
2

+5VS
+3VS

PR252
220K_0402_5%

1SS355_SOD323

PQ62
NDS0610_SOT23

8
-

PU24A

ADP_PS0

<30>

LM393M_SO8

+3VS

ADP_EN#
2005.8.20

<37>

PQ63
MMBT3904_SOT323

PR234
3.48K_0402_1%

8
+

1
O

7
ADP_PS1

<30>

LM393M_SO8
A

PQ64
RHU002N06_SOT323
S

Compal Secret Data

Security Classification
2005/03/10

Issued Date

Deciphered Date

2006/03/10

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

ADP_OCP
Rev

LA-2952P

Date:

PR227
10K_0402_5%
PU24B

2
1
1 2

2
B

PR232
21K_0603_1%
1
2

1
2

1SS355_SOD323

PR233
100K_0402_5%
<30>
1
2

PR226 +5VS
1M_0402_5%
1
2

1
2

ADP_EN

2
G

PD23

PR218
10K_0402_5%

2
1

1
PR231
220K_0402_5%

LM393M_SO8

PR228
21K_0603_1%

PR230
47K_0402_5%

PU25B

2
1
PR239
220K_0402_5%

1
3

PR240
0_0402_5%
2
1

2
G
PQ65
@RHU002N06_SOT323
PR241
10K_0402_1%

PR225
@100K_0402_5%

8
+

PR222
71.5K_0402_1%

SRSET

VIN

PR238
1M_0402_5%
1
2

PR258
22.6K_0402_1%

<37>

<37>

PR237
47K_0402_5%

ACN

VIN
PR235
10K_0402_1%

PR220
10K_0402_5%
1
2

470K_0402_5%
+3VS

<30>

+5VS
PR219
1M_0402_5%
1
2

ADP_ID
PR229
1M_0402_5%
1
2

1
2

LM393M_SO8

PR216

PR221
10K_0402_5%

PC133
0.1U_0603_16V7K

O
4

PR236
10K_0402_1%

+3VS
B

PC146
1U_0603_16V6K

PU25A

+3VL
PR224
22.6K_0402_1%

VIN

1
1SS355_SOD323

PR223
182K_0402_1%

PC147
3900P_0402_50V7K

3
VIN

PR265
47K_0402_5%

2005.8.24
PD25
3.9K_0402_5%
PR214

ADP_SIGNAL

Friday, April 28, 2006

Sheet
1

43

of

47

EE PIR list

Page38 : Add R58,R59,R60 ,those are removed from daughter board

Page19 : Add T8/T9 for GPIO10/14

06/25/2005

Page39 : JP18 pin3 change from ground to BT_LED

Page23 : Change L1,L2,L63,L6,L7,L9,L11-16,L65,L66 to FB

Page33 : Delete U58, R165,C568,C1,C312,C311 FOR LAYOUT SPACE

Page37 : Remove JP16 & change debug port interface to JP44

Page30 : Disconnect the I2C bus / WL_LED#/WP_LED# on JP46

06/27/2005

Page27 : ICH7M pin R7 change to +3VS

Page10 : 1.
2.
3.
4.
5.
6.
7.
7.
8.

Change All 2N7002_SOT23 to RHU002N06_SOT323 to save layout space

Page33 : Update audio amp to MAX9710

06/03/2005
Page10 : Add R260 to reduce one 330U cap C666
Page25 : 1. R27 change to +3VS
2..Add R1035 for H_DPSLP#
Page26 : 1.Add T80 for GPIO25
2. GPIO21 change net name to VGARST#
3. Add T88 for GPIO23
4. Add T89 for GPIO26
5. GPIO30 change net name to USB_OC#6
6. GPIO31 change net name to USB_OC#7
7. Add R1036/7 for RESET option
8. Remove the connection of USB_OC#3/4/5

Add
Add
Add
Add
Add
Add
Add
Add
Add

Page10
Page9

R504/R505 for VCC_SYNC

R490/R491 for VCCTX_LVDS
R494 for VCCA_CRTDAC
R492/R493 for VCCA_LVDS
R495 for +3VS_TVBG
R500 for +3VS_TVDACA
R502 for +1,5VS_TVDAC
R499 for +3VS_TVDACB
R496 for +3VS_TVDACC

Page28 : Y1 update to smaller package 6x3.5

Page33 : U57 change to 2A current limit power switch G548

07/04/2005
Page17 : Add R131 for inverter PWM when ATI PWM issue

Page04 : R1265 change to 51_0402_5% & install

Page19 : 1. Add R49 , R189 for 1.2V voltage divider

2. Add Q12 for M52_therm# & change to GPIO14
Page32 : The limitation for 5 pin audio jack can't switch
headphone/docking line-out ,so add R1420,R1421,C526,R252
Delete R256,R255,C536.

Page07 : Install R1344

Page39 : Delete C984~C988

Page28 : Delete U70 ,reserve U71 for 200 mil

Page33 : Delete C527

Page35 : Delete U61 , resevre U66 for 200 mil

Page10 : Delete C823 reserved pad

Page29 : Update U7 symbol pinB7/B8/C8

Page25 : Add JP5 slim type ODD connector

06/15/2005

Page18 : 1.R1365 CHANGE TO 2K_0402_1%

2. R1366 change to 562_0402_1%
3. R1367 change to 1.47K_0402_1%

Page25 : Y4 update to smaller package 14M-J

Page23 : Add HW strpping pin on DVPDATA20,21,22,23 for VRAM ID0,1,2,3

Page16 : 1. Add C174,C150,C142,C371,C358 for DVI

2. R103 change to 1%
Page35 : U69 pin7 change to PD

Page35 : Add JP3 for Smart card FFC connector

06/16/2005
Page36 : Delete R32 ,double

Page15 :Add the connection for UMA VGA clock , & SRC0/2 SWAP
1.Add R1148/R1149 , R1129/R1132 , R1118/R1121
2.Add R1242/R1248,R1253/R1272

Page41 : Delete R180,Q49 ,the same function for +1.8VS

Page33 : Swap JP3 samrt card pin assignment for FFC

Page10 : Delete C982 for Lead-free

07/14/2005

Page20 : Add C570 for Lead free

Page25 : Add R133 100 ohm to avoid RTC short

Page32 : 1,Delete Q28 .

2. D49,D50 change to U73
3. Add C577,C581 for Lead free

Page15 : 1. clock gen. pin 5 change to connect to +ck_vdd_dp

2. C731,C732,C733 change from 0.1u to 0.01u
3. C361,C364 change from 33p to 27p

Page19 : Swap I2C bus for LVDS/Thermal sensor

Page25 : Add C629,C630,C631 for SATA connector

Page26 : Separate PCIE_WAKE# to NIC/Mini-card PCIE_WAKE# to avoid battery mode

Page23 : Delete L65,C270,C269,C271 for M52-T

PQ34 pin5/6/7 change netname to LX_5V

Page36 :

Delete R500 & rename to EXPCRD_RST#

Page39 : Add C91,C93,C181 for low speed signal

Page09 : Add R554 , R555 for CRT disable

07/20/2005

Page10 : 1. Add R508,R510 for VCCD_LVDS1/1/2

2. R504,R505 chnage for +2.5VS_GMCH,&delete R490,R491,R492,R493
Page30 : Delete JP48,49 & change screw holes

06/08/2005
:

06/22/2005

Page35 : Add JP3 for Smart card FFC connector

Delete PD resistor R1340~R1343.

can't enter S3 issue

07/19/2005

Page18~23 : ATI VGA controller change to M52T

Page38 : Pin96: INVPWM rename to OUT9 & add T90

Page7

PU

Page33 : Add R163,R164,R165 for USB power switch PU

06/07/2005
Page47 :

07/12/2005

Page31 : JP4 update to RJ45 connector

Page09 : Change 0 ohm resistors before filters ,

and delete the other group of filtes at page 19
Page16 : add R671~R678 ,R530,R531 for DVI

Page15 : Y3 update to smaller package 6x3.5

Page21 : Change L1,L2,L63 to FB

Page10 : A. U71 change to U43D (the fourth gate in U43)

B. Add +3VS_TVBG R/C filters & voltage follower D12,D21,R127,R520
Page34 : audio change-- add R1419 ,R431,R434,R435 for BIASA/B/C

TV/ CRT when using 945PM

07/01/2005

06/14/2005

06/04/2005

TV/ CRT when using 945PM

06/30/2005

Page23 : Add R6 R15,R106,R128,R129 GPIO PD

Enable

Page40 : Change Q10,Q11,Q15,Q26 from SOT23 to SOT323

to save layout space
Page37 : 1 . Update JP20 to 6 pin connector
2. Update JP20 & JP18 pin assignments to follow Taos

06/13/2005

Page32 : 1.JP13 change to 90 pins connector

2.Add U72 for ESD protection

: Enable
:

06/28/2005

Page09 : 1.Add R460,R461, R550,R552,R553 for CRT discrete/uma option

2. Add R462,R463,R464 for TV discrete/uma option

Page24 : Add ALS_EN on JP35 pin24 for light sensor

Page30 : Add R1422 pad for XMIT_OFF

06/23/2005

Page17

Update JP35 LVDS connector

Page26

A. GPIO28 ==Delete R1321 & A_SD , change to VGA_RST#

B. GPIO21 ==Change to MB_PWR
C. GPIO19 ==Change to PD

Page16 : Change SDVOB_INT+/- net name to PEG_RXP1/N1

Page10 : 1.R505 / R510 for M52 , R504 / R508 for UMA
2. R499,R500,R496 connect to +1.5VS for diable CRT
Page36: Delete R49 & CB_CLK

06/09/2005

Page19 : Add LVDS L-shape BOM option resistors

Page32 : JP44 PLT_RST# change to PLT_RST_B# to reduce the loading

06/24/2005

Page28: 1.Delete R15 ,due to Internal PD

2.Delete R69 ,due to Internal PD
3. Add U70,U71,R69,R92 R1297 for serial falsh support.

06/01/2005 schematics review start :

06/02/2005

06/11/2005

Page25: JP42 change to wire to board connector

Page17

Delete Q56 ,R510 ,Caymus support 3V PWM

Page25

Update Q92 to AOS4407

Page26

Delete R252

1.Add CRT,TV filters for M52T

2. Add DVI BOM option 0 ohm
Page16 : Move 0 ohm to TV-out connector for TV

Page37

Add PD RP42,R273

Page38 : Move 0 ohm to docking connector for CRT

Page19:

Delete Cardbus 6612 circuit & move to daughter board LS-2953

06/10/2005
Page17

Add R458,R459 for ch_data,ch_clk

Page33

Add C367 0.1U for +SC_PWR

Compal Secret Data

Security Classification
2005/05/26

Issued Date

2006/07/26

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.

H/W2 EE Dept. PIR SHEET
Document Number

Rev
1.0

LA-2952P
Sheet

Friday, April 28, 2006

5

44

of

47

For DB2 Modification

08/11/2005
Page31/32 : Update Audio portion for jack sensing
Page35 : Delete LED circuit & connect to LS-2953 directly
Page11 : Change R1154 to NI
Page30 : Add C554 for UIM power
1

Page25 : Delete JP37 MB2 conector

12/16/2005

Page32 : Reserve C555

Page16 :Add R1369,R1367,R1368

10/06/2005

Page32 :Add D16 for EMI request

Page24: NI D64 ,install R1355

Page30 :Change C350,C349 to 18pF

Page07: NI R1202,R1203

Page15 :Change C361,C364 to 18pF

Page22: NI R1397,U36Install Q94Add R1076

Page19 :Change C516,C528 to 15pF

Page29:Reserve U61

Page31 :Add D66 for EMI request

Page24:Add R1364Reserve R1363

Page15 :Change R1075,R1081,R1129,R1132,R1148

,R1149,R1111,R1115 to 22ohm

Page30:Install R91

Page19 : Change C611 to NI ,R662 to 0 ohm for clcok spectrum

Page24:Add R1366Reserve R1365

Page15 : Add R1136 PD for clk_pcie_m52 ,R1084 change to NI

Page24 : R1388 change to Install
Page26 : R1364 change to NI
Page36 : R1354 change to NI

Page30 : R1418 , R1360 change to NI

For PV Modification

Page24: Add R1071,R1073

01/16/2006

Page07: NI R1209

Page07 :UI R1201,R1204 for SI-2 shutdown issue

Page22: Install R275,R289NI R1396,R1398

Page15 :Change R1148,R1149,R1070,R1072,R1075,R1081,R1129,R1132

R1093,R1095,R1257,R1259,R1144,R1145,R1123,R1126,R1133,R1111
R1115,R1143,R1249,R1251 to 24 for CLK GEN vendor recommand
Page24 :R996 change to SM010014500 (220ohm impedance)
for improve WLAN performance

Page20: Add R1040,R871Reserve Q106Del R1404

Page22 : Add R1091,R1082,R1088,R1085,Q105,R1023,
R1024,D63,C1042,U55,R1021,R1076
Reserve Q103,Q104,R1090,
Del R601.
Page15 : Del R1084,R1136

08/19/2005
Page35 : Delete FWH , SPI change to +3VALW
Page36 :Delete R538
Page10 : Delete L39

Page24 : Modify R996 to 1000ohm/100MHz bead

Modify R996's location to L78
For power noise impact WLAN performance
Page24 : Connect R1363.2 to V_3P3_LAN, INSTALL R1363 and UI R1364

Page28 :Install Q103NI R1091

08/20/2005
2

02/07/2006

10/08/2005

Page25 : Add D15, D16 , R90 , R88 for HDD LED

For support wake on WLAN from S3.

10/13/2005

Page30 : Change +3VL / Caps_LED# to Pin45/51

Page38 : Delete R551 ,R548,R549,R541
Page25 : Add D15,D16,R88,R90 for HDD_LED

Page33 :Delete J33

Page15 : Install R1245 and UI R1247

Page18 :Delete BIOS_SEL jump

Page31 : Change Num_LED# and CAPS_LED#

Page26 :NI C526

LayoutModify +3VALW power trace width for LCDVDD

Page32 :Add R1404,R1428,R1429,R1430,R1431,R1432,

R609,R608,R611,R610,R613,R612,R616,R615
Page31 :Install CP1~CP6

02/14/2006

08/25/2005
Page31/32 : Add JP16 for audio cable

10/31/2005

Page30 : Internal MIC signal change to JP13

Page06 :NI C933Modify 330U cap from ESR9 to ESR7.

08/24/2005
Page15 : Add C353~C372 for clk cap

Page20 : Add R1437

For HALTLED turn on 100ms when power on.
Page29 : Del U61. (150mil SPI ROM)
Page15 : Add C357,C372,C373,C374,C375,C376,C378,C379

08/26/2005
08/29/2005

Page32 : Add R1433~R1436 on each DVI differential pair for EMI request.

02/20/2006

Page06 :Del C938.

Page23 : R154 change to NI

Page26 : Connect JP24 and JP15's 7,8pin to DGND.

Page19 :Del C646

Page29 : Add C333 for NIC

For ESD concern.

Page24 :NI R1355 , Install D64

08/30/2005

Page31 :exchange netname between JP18's pin 25 and pin 24

Page23 : Add R173 for Therm_SCI#

Page34 :Del U45,U48,R1306,R117,R1307,C33,C993,C87

Page36 : R538 change to NI

12/07/2005

Page21 : Add C140, C172 , C141 , L17 for VDDPLL

Page20 :Del R1384,R1385,R1427

Connect LP_EN# to GPIO8

08/31/2005
Page32 :

02/21/2006

Page30 :Install R33Change RP43,44 to 10K ohm

Page15 : Add C373 for clk_debug_port

Page09 : Reserve ESD diode(D67) for C_HSYNC and C_VSYNC

02/23/2006
Page27 : Add D51,D52,D61 for EMI team request

02/24/2006
Page16 : Change C140 to 22u, R103 to 1.3K to fix DVI EMI issue

03/08/2006

Delete R1419, R1420

Page19 : R189 change to 56_0402_1%

Page15 :Add C740,C741,C744,C745 for EMI request

Page26 : Change R1405 and R1406 to 12.1K

Page20 :Add Q43 HALT LED issue

For MV1 Modification

12/13/2005
12/14/2005

10/04/2005

Page31 :Add R1084 and reserve R1096

Page26 : R251.2/C526.1 connect to DLINE_OUT_L

Page32 : PR255.1 connect to pin 29 of the docking connector.
(ACOCP_EN#)
Page29 : Add discharge circuit for BT_LED and WL_LED(R504,R505)
(this issue occurs when there is no WLAN card)
Page20 : Delete R1323 (EAPD to ICH7)
4

02/16/2006

12/06/2005

Page32 : Add 1423,R1424 for MIC_REF , & MIC_SENSE connection

To improve WWAN performance

For SI2 Modification

Page32 : Add R427,R429,C492 for J_MIC_REF

For LED reverse issue

10/26/2005

Page30 : Add SW1 C986, R521 , D65,D66 for SIM power off

10/07/2005

Page20: Install R1384,R1395Reserve R1385,R1427

Del Q71,R1345

08/15/2005

10/04/2005

03/24/2006

12/15/2005
Page32 :Modify R1404 ,R1428,R1429 to 0603
Add C746,C747,C748 for EMI request

Page19 : Change Y4 to a LF part.

Page22 : Change R70 to 1.21K to improve signal amplitude

12/16/2005
Page22 :Del U71,R69,R92,R1297

Page22 : Add Q40,R1419, reserve R1420

Page24 :UI R1364,Install R1363

Page24 : Add R996,reserve R519,Q41,Q42

Page07 :Install R1201,R1204

Page29 : Install R1409, Make R1380 NIreserve R101

Page30 : Reserve R91,R102
Page27 : Change R454 to 47K , add C556

2005/05/26

Issued Date

Page15 :Delete R1071,R1073,R1076,R1082,R1094,R1096,R1258,R1260

R1112,R1116,R1250,R1252,R1124,R1127,R1134,R1137,R1238
R1239,R1242,R1248,R1253,R1272(NOLP@)
1

Compal Secret Data

Security Classification

Page25 : Install R136

2006/07/26

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.

H/W2 EE Dept. PIR SHEET
Document Number

Rev
1.0

LA-2952P
Sheet

Friday, April 28, 2006

5

45

of

47

04/06/2006
Page32 : Change R1433~R1436 to 110
Change R609~R613,R615,R616 to L79~L82 (common mode choke 90 ohm)
For DVI EMI issue
Page16 : Change C310,C313,C314 to 18P
For CRT EMI issue
Page09 : Change L28,L35,L27 to 0 ohmC193,C232,C237 to 12P
1

Change L31,L34,L26 to 39nH inductor

For CRT EMI issue

04/28/2006
Page22 : Install R1022 and UI R1021
For clock can't shut down under DC mode

Compal Secret Data

Security Classification
2005/05/26

Issued Date

2006/07/26

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.

H/W2 EE Dept. PIR SHEET
Document Number

Rev
1.0

LA-2951
Sheet

Friday, April 28, 2006

5

46

of

47

Version Change List ( P. I. R. List ) for Power Circuit

Item Page#

Title

Date

Request
Owner

Issue Description

Solution Description

Rev.

42,44,50

8/26/2005
(DB)

48

8/30/2005
(DB)

HP

To fix VDD_CORE in 1V(Only for Discrete).

10/18/2005
(SI)

HP

Changes for OCP circuit

43

HP

Add PR2,PR259,PR261(1M ohm),

Add PQ73,PQ74,PQ75,PQ76(RHU002N06_SOT323)
Add PR260(39.2k)

To implement 4 cell main battery

Remove PQ49,PQ66

37

43 37

12/06/2005
(SI2)

HP

Changes for OCP circuit

PR225 is open and PR26.2 connects to PQ63.1

43

12/12/2005
(SI2)

HP

Changes for OCP circuit for 50W adapter

Correct PR223 from 180K to 182K.

Change PR258 from 29.4K to 22.6K

41

42

41

12/19/2005
(SI2)
12/21/2005
(SI2)
01/16/2006
(PV)
02/08/2006
(PV)

10
11

02/17/2006
(PV)

37

HP

DB

Add PC147 3900pF capacitor across PR214

Change PR207 from 0 Ohm to 3.9K_5%
Change PC131 from 0.22uF to 0.027uF
Change PR203 from 649K to 604K_1%
Change PR221 from 47K to 10K_5%
Add a newPR265 47K_5% resistor in series with PR216-2 SI
Add a new PC146 1uF X7R capacitor from PR216-2 to GND
Change PC133 from 10uF to 0.1uF X7R
Change PR228 from 10K to 21K_1%
Change PR234 from 11.5K to 3.48K_1%
Change PR232 from 3.3K to 21K_1%

10/18/2005
(SI)

DB

compal

sets Max charge current to 3.75A

Change PR29 from 100K to 143K_1%

DDR2 issue

SI
SI
SI2
SI2

Change PC78 from 220u to 330u

Delete PC81,PR127

SI2

compal OTS#181928
Add PC148(68uF)
Electrical printed circuit assembly acoustic noise test failcompal
Add PC81,PR127
For 1.8V thermal shut down issue

PV

OTS#184638
compal
SVTP_SI1:PC Card Wireless Radio Interference fail on GSM 850 Change PL8,PL11 to shielded inductors
and GSM 900 channel.
This change will slightly increase the battery life
HP
Change PR38 to 866_1% Ohms
Change PR41 to 100K_0.1%
Change PR44 to 7.68K_0.1%
Change PR53 to 2.80K_0.5%
Add a 39.2_1% resistor in series with PR53.
Connect one end to PR53.2 and the other end to GND.

PV
PV

Compal Secret Data

Security Classification
Issued Date

2005/03/01

2006/03/01

Deciphered Date

Title

PWR PIR Sheet (1)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Rev
1.0

LA-2952P
Sheet

Friday, April 28, 2006

1

47

of

47