There are basically two types of logic gate - a '1' gate and a '3' gate.

These differ only in the clock phases used to drive them. A gate can have any logic function; thus potentially each and every gate has a customized layout. An example 2-input NAND 1 gate and an inverter 3 gate, together with their clock phases (the example uses NMOS transistors), are shown below:

The 1 and 3 clocks need to be non-overlapping, as do the 2 and 4 clocks. Considering the 1 gate, during the 1 clock high time (also known as the precharge time) the output C precharges up to V(1)-Vth, where Vth represents the threshold of the precharge transistor. During the next quarter clock cycle (the sample time), when 1 is low and 2 is high, C either stays high (if A or B are low) or C gets discharged low (if A and B are high). The A and B inputs must be stable throughout this sample time. The output C becomes valid during this time and therefore a 1 gate output can't drive another 1 gate's inputs. Hence 1 gates have to feed 3 gates and they in turn have to feed 1 gates. One more thing is useful - 2 and 4 gates. A 2 gate precharges on 1 and samples on 3:

and a 4 gate precharges on 3 and samples on 1. Gate interconnection rules are: 1 gates can drive 2 gates and/or 3 gates; 2 gates can drive only 3 gates, 3 gates can drive 4 gates and/or 1 gates, 4 gates can drive only 1 gates: