Beruflich Dokumente
Kultur Dokumente
CIC 2006/02
Class Schedule
Day1
Design Flow Over View Prepare Data Getting Started Importing Design Specify Floorplan Power Planning Placement Synthesize Clock Tree
Day2
Timing Analysis Trial Route Power Analysis SRoute NanoRoute Fill Filler Output Data DRC LVS extraction/nanosim
2
Chapter1
GDSII
Routed design
Corner1
I1
VDD
O1
Corner2
I2 IOVDD I3
O2 IOVSS O3
Corner3
I4
VSS
O4
Corner4
6
Specify Floorplan
Hight
Width
Floorplan
I1
VDD
O1
I2
O2
M2
IOVDD IOVSS
M1
I3
M3
O3
I4
VSS
O4
8
Amoeba Placement
Power Planning
10
D D
Q D Q
Q D Q
Q D Q
D D D
Q D D D Q
Q Q Q
Q D D Q D D Q
D D D
Q D Q D Q
Q Q
Q D Q
CLK
CLK
11
Power Analysis
12
Power Route
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Add IO Filler
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Routing
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Prepare Data
Library
Physical Library (LEF) Timing Library (LIB) Capacitance Table Celtic Library FireIce/Voltage Storm Library
User Data
Gate-Level netlist (verilog) SDC constraints IO constraint
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17
Wide metal
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19
a row
a site
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Row Based PR
VDD
VSS
VDD
VSS
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metal1 routing pitch via metal2 routing pitch Horizontal Vertical routing routing Metal1 Metal3 Metal5 Metal2 Metal4 Metal6
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Generated via
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Higher density routing Easier usage of upper layer Must Follow minimum area rule
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25
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VSS
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LIB Format
Operating condition
slow, fast, typical
Pin type
input/output/inout function data/clock capacitance
UDN
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Require
All lef fie lefdef.layermap
9 lef &ICT layer mapping 9 gds &ICT layer mapping
lefdef.layermap
#type metal metal metal metal via via via layer_ict METAL_1 METAL_2 METAL_3 METAL_4 VIA_1 VIA_2 VIA_3 lefdef lefdef lefdef lefdef lefdef lefdef lefdef lefdef layer_lef METAL1 METAL2 METAL3 METAL4 VIA12 VIA23 VIA34
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gate-level netlist
If designing a chip , IO pads , power pads and Corner pads should be added before the netlist is imported. Make sure that there is no assign statement and no *cell* cell name in the netlist.
Use the synthesis command below to remove assign statement. set_boundary_optimization Use the synthesis commands below to remove *cell* cell name define_name_rules name_rule map {{\\*cell\\* cell}} change_names hierarchy output name_rule
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SDC constraint
Clock constraints Input delay / Input drive Output delay/ Output drive False path Multicycle path
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CHIP
I_CLK
CLK1
3,2,4,3 In2
In2
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Out1
5pf
Out2
4~5pf
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2 1 3 1
9
3 2 RAT=10
Path-based:
2+2+3 = 7 2+3+1+3 = 2+3+3+2 = 5+1+1+3 = 5+1+3+2 = 5+1+2 = 8 9 10 10 11 (OK) (OK) (OK) (OK) (Fail) (OK)
AT=5
AT=2
AT=2 RAT=5
AT=5
3 1
AT=5 RAT=4
AT=6 RAT=5
2 1 3 1
AT=7 RAT=7
Block-based:
3 2 RAT=10
AT=11 RAT=10
AT=9 RAT=8
Critical path is determined as collection of gates with the same, negative slack: In our case, we see one critical path with slack = -1
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Vin I1 I2 Dtransition(I1)
Dcell(I2)
TDFF1+Tpath Tarrival
clk2
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PI to Reg
Tarrival = TPI(delay)+ TPATH Trequire = Tclk+ TDFF(hold) Tslack = Tarrival-Trequire
Reg to PO
Tarrival = Tclk+ TDFF(clk->Q)+TPATH Trequire = - TPO(output delay) Tslack = Tarrival-Trequire
PI to PO
Tarrival = TPI(delay)+ TPATH Trequire = - TPO(output delay) Tslack = Tarrival-Trequire
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IO constraint
Create an I/O assignment file manualy using the following template:
Version: 1 MicronPerUserUnit: value Pin: pinName side |corner Pad: padInstanceName side|corner [cellName] Offset: length Skip: length Spacing: length Keepclear: side offset1 offset2
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IO constraint cont.
Version: 1 Pad: CORNER0 NW PCORNERDGZ Pad: PAD_CLK N Pad: PAD_HALT N Pad: CORNER1 NE PCORNERDGZ Pad: PAD_X1 W Pad: PAD_X2 W Pad: CORNER2 SW PCORNERDGZ Pad: PAD_IOVDD1 S PVDD2DGZ Pad: PAD_IOVSS1 S PVSS2DGZ Pad: CORNER3 SE PCORNERDGZ Pad: PAD_VDD1 E PVDD1DGZ Pad: PAD_VSS1 E PVSS2DGZ
PAD_HALT PAD_CLK PAD_IOVDD1
PAD_IOVSS1
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SSO Consideration
SSO
Simultaneously Switch Outputs
SSN
The noise produced by SSO buffers
DI
maximum number of copies for one specific kind of I/O pad switching from high to low simultaneously without making ground voltage level higher than 0.8 volt for one ground pad
DF
Drive Factor, DF = 1/DI
SDF
Sum of Drive Factor
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In SSO case
Required number of ground pads = SDF Required number of power pads = SDF/1.1
SDF Example
IO Type DF Value
2mA 0.02 4mA 0.03 8mA 0.09 12mA 0.18 16mA 0.3 24mA 0.56
If a design has 20 PDB02DGZ(2mA), 10 PDD16DGZ(16mA). then SDF = 20 x 0.02 + 10 x 0.3 = 3.4 In SSO case,
number of VSS pad = 3.4 4 number of VDD pad = 3.4/1.1 = 3.09 4
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Getting Started
Source the encounter environment:
unix% source /usr/cadence/cic_setup/soc.csh
Do not run in background mode. Because the terminal become the interface of command input while running soc encounter. The Encounter reads the following initialization files:
$ENCOUNTER/etc/enc.tcl ./enc.tcl ./enc.pref.tcl
Log file:
encounter.log* encounter.cmd*
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GUI
menus tool widgets design views switch bar
display control
design views
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Tool Wedgits
Design Import
Fit
Zoom In/Out
Zoom Select
Redraw
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Design Views
FloorplanView
displays the hierarchical module and block guides,connection flight lines and floorplan objects
Amoeba View
display the outline of modules after placement
Placement View
display the detailed placements of cells, blocks.
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Display Control
Select Bar
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Action Select Next popup Edit editTrim toggle layer[0-9] visibility hierarchy up/down clear Drc
Import Design
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DesignDesign Import
9 9 9 9
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IO Assignment File:
get a IO assignment template: DesignSaveI/O File
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9 9 9 9
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Delay Name/Footprint:
required to run a fix hold time violation
Inverter Name/Footprint:
required to run IPO and TD placement.
For Cells: BUFXL BUFX1 BUFX2 BUFX3 BUFX4 BUFX8 BUFX12 BUFX16 BUFX20 Footprint : buf
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9 9 9 9
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Specify Floorplan
FloorplanSpecify Floorplan
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9 9
9 9
9 9
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Double-back rows:
Row Spacing = 0
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Place Blocks
FloorplanPlace Blocks/ModulesPlace
automatic place blocks ( blackboxes and partitions) and hard macros at the top-level design. Block halo
Specifies the minimum amount of space around blocks that is preserved for routing.
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Prevent the placement of blocks and standard cells in order to reduce congestion around a block.
9 9 9 9
Bottom
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Block Placement
Flow step
I/O pre-placed Run quick block placement Throw away standard cell placement Manually fit blocks
Block Placement
Preserve enough power pad Create power rings around block Follow default routing direction rule Reserve a rounded core row area for placer
block
Default direction
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9 9 9
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90
Block A
Block B
Block A
Block B
Block C
Block C
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9 9
92
9
93
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Edit Route
Duplicate wire
Change layer
Change width
Delete wire
Trim wire
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instPinName
The design instance input/output pin name
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SCAN IN
D Q
Q D Q
SCAN OUT
SCAN IN
D Q
Q D Q
SCAN OUT
D D D
Q D D D Q
Q Q Q
Q D D Q D D Q
D D D
Q D Q D Q
Q Q
Q D Q
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Placement
PlacePlace Prototyping : Runs quickly, but components may not be placed at legal location. Timing Driven:
Build timing graph before place. meeting setup timing constraints with routability. Limited IPO by upsizeing/downsizing instances.
9 9
100
Floorplan Purposes
Develop early physical layout to ensure design objective can be archived
Minimum area for low cost Minimum congestion for design routable Estimate parasitic for delay calculation Analysis power for reliability
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Logical
Module Constraint
Soft Guide
Guide
Region
Fence
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105
PlaceTieHiLoAdd TieHiLo
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Clock Problem
Clock problem
Heavy clock net loading Long clock insertion delay Clock skew Skew across clocks Clock to signal coupling effect Clock is power hungry Electromigration on clock net
Clock is one of the most important treasure in a chip, do not take it as other use.
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Modify
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9 9 9
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CTS
CTS traces the clock starting from a root pin, and stops at:
A clock pin A D-input pin An instance without a timing arc A user-specified leaf pin or excluded pin
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CTS spec.
A CTS spec. contain the following information.
Timing constraint file (optional) Naming attributes (optional) Macro model data (optional) Clock grouping data (optional) Attributes used by NanoRoute routing solution (optional) Requirement for manual CTS or automatic CTS
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NameDelimiter delimiter
name delimiter used when inserting buffers and updating clock root and net names. NameDelimiter # create names clk##L3#I2 default clk__L3_I2
UseSingleDelim YES|NO
YES clk_L3_I2 NO clk__L3_I2 (default)
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NonDefaultRule ruleName
Specify LEF NONDEFAULTRULE to be used
PreferredExtraSpace [0-3]
add space around clock wires
Shielding PGNetName
Defines the power and ground net names
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ClkGroup
Specifies tow or more clock domains for which you want CTS to balance the skew. ClkGroup +clockRootPinName1 +clockRootPinName2 ..
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numberOfBuffer
9 the total number of buffers CTS should allow on the specified level
Example:
LevelSpec 1 2 CLKBUFX2 LevelSpec 2 2 CLKBUFX2
End
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BufMaxTran number{ns|ps}
maximum input transition time for buffers (defalut 400)
MaxSkew number{ns|ps}
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AddDriverCell driver_cell_name
Place a driver cell at the cloest possible location to the clock port location .
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PostOpt YES|NO
whether CTS resizes buffers of inverters , refines placement,and corrects routing for signal and clock wires. default YES
Treats the port as a non-leaf port, and prevents tracing and skew analysis of the pin.
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PreservePin + inputPinName + .
Preserve
Preserve the netlist for the pin and pins below the pin in the clock tree.
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Clock Tree Specs AutoCTSRootPin / ClkGroup ThroughPin Maxdelay Maxskew BufMaxTran / SinkMaxTran
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Reconvergence clock
Crossover clock
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Clock nets
Saves the generated clock nets used to guide clock net routing
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128
Display trig edge, rise/fall delay, rise/fall skew, input delay, input tran of each cell. Resize/Delete leaf cell or clock buffer Reconnect clock tree
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Optimization
TimingOptimization
IPO
setup time hold time SI DRV (Design Rule Violation)
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Useful Skew
balanced clock
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Trial Route
perform quick routing for congestion and parasitics estimation Prototyping:
Quickly to gauge the feasibility of netlist. components in design might no be routed at legal location
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V=25/20 H=16/18
The vertical (V) overflow is 25/20 (25 tracks are required , but only 20 tracks are available) . The Horizontal (H) overflow is 16/18 (16 tracks are required , and18 tracks are available) .
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Overflow Value One more track required Two more track required Three more track required Four more track required Five more track required Six or more track required
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Timing Analysis
TimingSpecify Analysis ConditionSpecify RC Extraction Mode TimingExtract RC TimingTiming Analysis
No Async/Async:
recovery, removal check
No Skew/Skew:
check with/without clock skew constraint
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Slack Browser
TimingDebug Timing
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Power Analysis
TimingExtract RC PowerEdit Pad Location PowerEdit Net Toggle Probability
9 9 9 9
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9 9
analysis report:
A power graph report contains
9 average power usage 9 worst IR drop 9 worst EM violation
9 9 9 9
VoltageStorm Anaylsis
PowerRun VoltageStorm
9 9 9 9
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Display IR Drop
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144
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SRoute
Route Special Net (power/ground net)
Block pins Pad pins Pad rings Standard cell pins Stripes (unconnected)
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Add IO filler
addIoFiller addIoFiller addIoFiller addIoFiller cell cell cell cell PFILL prefix IOFILLER PFILL_9 prefix IOFILLER PFILL_1 prefix IOFILLER PFILL_01 prefix IOFILLER -fillAnyGap
Connect io pad power bus by inserting IO filler. Add from wider filler to narrower filler.
ADD IO FILLER
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NanoRoute
RouteNanoRoute
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NanoRoute Attributes
RouteNanoRoute/Attributes
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Crosstalk
Crosstalk problem are getting more serious in 0.25um and below for: Smaller pitches Greater height/width ratio Higher design frequency
152
Crosstalk Problem
Delay problem
Aggressor original signal impacted signal
Noise problem
impacted signal
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Crosstalk Prevention
Placement solution
Insert buffer in lines Upsize driver Congestion optimization
Add buffer
Upsize
Routing solution
Limit length of parallel nets Wider routing grid Shield special nets
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Antenna Effect
In a chip manufacturing process, Metal is initially deposited so it covers the entire chip. Then, the unneeded portions of the metal are removed by etching, typically in plasma(charged particles). The exposed metal collect charge from plasma and form voltage potential. If the voltage potential across the gate oxide becomes large enough, the current can damage the gate oxide.
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Antenna Ratio
metal2 via2
Plasma + + + + + ++ + + +
metal2 metal1
Plasma + + +
Antenna Ratio =
metal2
via1
poly
metal1
gate oxide
159
Connect the NWELL/PWELL layer in core rows. Insert Well contact. Add from wider filler to narrower filler.
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PR boundary
Bonding matel
Inner Bonding
Outer Bonding
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162
routed.def routed.def
bondPads.cmd bondPads.cmd addbonding.pl addbonding.pl addbonding.pl routed.def (In unix terminal) bondPads.eco bondPads.eco source bondPads.cmd (In encounter terminal)
ioPad.list ioPad.list
finish
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Output Data
DesignSaveGDS DesignSave->Netlist DesignSave->DEF
Export GDS for DRC,LVS,LPE,and tape out. Export Netlist for LVS and simulation. Export DEF for reordered scan chain.
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Chapter2
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zn
compare with
zn
gnd!
ERC
vdd! short clk
LPE/PRE
vdd!
extract i zn i zn
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gnd!
DRC
Extract Devices
optional
ERC
LVS
LPE/PRE
Post-Layout Simulation
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DRC flow
Prepare Layout
stream in gds2 add power pad text stream out gds2
Prepare command file run DRC View DRC error (DRC summary/RVE)
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Prepare Layout
Stream In design Stream In core gds2 DFII Library Stream In IO gds2 LEF in RAM lef Add power Text Stream Out GDSII GDSII
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File->import->stream 9 9 9
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9 9 9
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Result log
CHIP.drc.summary (ASCII result) CHIP.drc.results (Graphic result)
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LVS Overview
Layout Data
VDDclk rst cin sel GNDVDD
Schematic Netlist
b<0> b<1> b<2> b<3> b<4> b<5> gnd! a<5:0> b<5:0> clk rst cin sel carry s<5:0>
GND
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...
a<0> b<0> initial corresponding node pairs
a<0> b<0>
...
...
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Black-Box LVS
Calibre black-box LVS
One type of hierarchical LVS. Black-box LVS treats every library cell as a black box. Black-box LVS checks only the interconnections between library cells in your design, but not cell inside. You need not know the detail layout of every library cells. Reduce CPU time.
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i1 i2
i1 vs. i2
GND
Black-Box LVS
inv0d1
VDD
nd02d1 z
inv0d1
i1
nd02d1
z GND
i1 vs. i2
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i2
LVS flow
Prepare Layout
The same as DRC Prepare Layout
Prepare Netlist
v2lvs
Prepare calibre command file run calibre LVS View LVS error (LVS summary/RVE)
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umc18lvs.v umc18lvs.v
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v2lvs source.spi
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OVERALL COMPAISON RESULTS CELL SUMMARY INFORMATION AND WARNINGS Initial Correspondence Points
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# # # # # # #
_ *
_ *
| \___/
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************************************************* CELL SUMMARY ************************************************* Result ----------CORRECT Layout ----------CHIP Source -------------CHIP
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Nets: Instances:
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o Initial Correspondence Points: Nets: DVDD VDD DGND GND I_X[2] I_X[3] I_X[4] I_X[5] I_X[6] I_X[7] I_X[8] I_X[9] I_X[10] I_X[11] O_SCAN_OUT O_Z[0] O_Z[1] O_Z[2] O_Z[3] I_HALT I_RESET_ I_DoDCT I_RamBistE I_CLK I_SCAN_IN I_SCAN_EN I_X[0] O_Z[4] I_X[1] O_Z[5] O_Z[6] O_Z[7] O_Z[8] O_Z[9] O_Z[10] O_Z[11]
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-------------------------------------------------------------------------------TEXT OBJECTS FOR CONNECTIVITY EXTRACTION -------------------------------------------------------------------------------O_Z[0] (523.447,31.68) 105 CHIP O_Z[1] (598.068,31.68) 105 CHIP O_Z[2] (821.931,31.68) 105 CHIP O_Z[3] (896.553,31.68) 105 CHIP O_Z[4] (971.175,31.68) 105 CHIP O_Z[5] (1164.455,372.964) 105 CHIP O_Z[6] (1164.455,446.966) 105 CHIP O_Z[7] (1164.455,520.968) 105 CHIP O_Z[8] (1164.455,594.97) 105 CHIP O_Z[9] (1164.455,668.972) 105 CHIP O_Z[10] (1164.455,742.974) 105 CHIP O_Z[11] (1164.455,816.976) 105 CHIP
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-------------------------------------------------------------------------------PORTS -------------------------------------------------------------------------------O_Z[0] (523.447,31.68) 105 CHIP O_Z[1] (598.068,31.68) 105 CHIP O_Z[2] (821.931,31.68) 105 CHIP O_Z[3] (896.553,31.68) 105 CHIP O_Z[4] (971.175,31.68) 105 CHIP O_Z[5] (1164.455,372.964) 105 CHIP
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Chapter3
-- Nanosim
M1 to substrate capacitance
M1
M1 to M1 capacitance
M1 to M2 capacitance
vdd! vdd!
gnd!
gnd!
202
M1 parasitic resistance
VIA
M1
vdd!
vdd!
M2 parasitic resistance
gnd!
gnd!
203
post-layout
204
....
critical path delay
...
. . .data
205
Layout
Delay Calculation
Extraction
Tr-level Analysis
206
netlist/parasitic extraction
Calibre LPE/PRE
SPICE netlist
simulation pattern
Nanosim
207
What is Nanosim
Nanosim is a transistor- level timing simulation tool for digital and mixed signal CMOS and BiCMOS designs. Nanosim handles voltage simulation and timing check. Simulation is event driven, targeting between SPICE ( circuit simulator ) and Verilog ( logic simulator ).
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Example:
Qentry M LPE tech UMC18 f CHIP.gds T CHIP s RAM1.spec t 18ra2sh s RAM2.spec t 18ra1sh_1 s RAM3.spec t 18ra1sh_2 c UMC18 i UMC18 o CHIP.netlist
Use Qstat to check the status of your job. The result is stored in result_# directory.
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Replace/LPE
INPUT
gds2 ram spec
OUTPUT
output netlist TOP_CELL.NAME nodename spice.header nanosim.run log files for strem in, stream out, lpe
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Running Nanosim
Qentry M {NANOSIM} n {CHIP.io} nspice CHIP.netlist spice.header nvec CHIP.vec m Top_cell_name c {CHIP.cfg} z {CHIP.tech.z} o Output_file_name out fsdb t Total_simulation_time Example:
Qentry M NANOSIM nspice CHIP.netlist spice.header nvec CHIP.vec m CHIP c CHIP.cfg z CHIP.tech.z o UMC18 t 100
Use Qstat to check the status of your job. The result is stored in result_# directory.
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in<7:0> 44 ii
xx xx xx
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in[7:0] 44 ii
xx xx xx
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Environment setup
unix% source /usr/debussy/CIC/debussy.csh
Starting nWave
unix% nWave &
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: -3.53355e+05 uA : 3.53388e+05 uA : : : : : -4.54061e+05 -4.34973e+05 -3.88048e+05 -3.87280e+05 -3.84302e+05 uA uA uA uA uA at at at at at 6.78400e+02 4.00000e-01 2.59000e+01 1.27500e+02 5.77800e+02
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ns ns ns ns ns