Class 10: CMOS Gate Design

Topics: 1. Exclusive OR Implementation 2. Exclusive OR Carry Circuit 3. PMOS Carry Circuit Equivalent 4. CMOS Full-Adder 5. NAND, NOR Gate Considerations 6. Logic Example 7. Logic Negation 8. Mapping Logic 0 9. Equivalent Circuits 10. Fan-In and Fan-Out 11. Rise Delay Time 12. Rise Delay Time 13. Rise Delay Time 14. Fall Delay Time 15. Equal Delays
Joseph A. Elias, PhD

Class 10: CMOS Gate Design

Exclusive OR Design (Martin c4.5)
3-input XOR Truth Table

Similar to how one derives a 2-input XOR (Martin, p.183) using (a+b)=(ab) (ab)=(a+b) a XOR b = ab + ab = aa + ab + ab + bb = a(a+b) + b(a+b) = (a+b)(a+b) = (ab)(a+b) = (ab + (ab) ) = (ab + (a + b) )

Joseph A. Elias, PhD

Class 10: CMOS Gate Design

Exclusive OR Carry Circuit (Martin c4.5)

NMOS realization A in parallel with B A||B in series with C AB in parallel with (A||B)C Vout =
Joseph A. Elias, PhD

PMOS equivalent A in series with B AB in parallel with C A||B in series with (AB)||C 3

Class 10: CMOS Gate Design

PMOS Carry Circuit Equivalent (Martin c4.5)

Martin indicates equivalency between these circuits Is this true? (AB+C)(A+B) = (A+B)C + (AB) ABA + ABB + AC + BC = AC +BC +AB AB + AB + AC + BC = AC + BC + AB AB + AC + BC = AB + AC + BC equivalent
Joseph A. Elias, PhD

Class 10: CMOS Gate Design

CMOS Full-Adder (Martin c4.5)

Sum: (A+B+C) Carry + ABC Carry: (A+B)C + AB

Joseph A. Elias, PhD

Class 10: CMOS Gate Design

NAND, NOR Gate Considerations (Martin c4.5)

NAND is preferable to NOR - why? What makes p-ch undesirable? How does one compensate for it?

Joseph A. Elias, PhD

Class 10: CMOS Gate Design

Logic Example (Martin c4.5) Desired Truth Table Corresponding Karnaugh Map

Grouping of 1 (meaning what gates?):

Joseph A. Elias, PhD

Class 10: CMOS Gate Design

Logic Negation (Martin c4.5)

Joseph A. Elias, PhD

Class 10: CMOS Gate Design

Mapping Logic 0 (Martin c4.5)

Using (ab)=(a+b)

Choice of which map to use depends on whether inputs are negated

Joseph A. Elias, PhD

Class 10: CMOS Gate Design

Equivalent Circuits (Martin c4.5)

Joseph A. Elias, PhD

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Class 10: CMOS Gate Design

Fan-In and Fan-Out (Weste p264-267)

Joseph A. Elias, PhD

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Class 10: CMOS Gate Design

Rise Delay Time (Weste p264-267)

Rise time delay where

Joseph A. Elias, PhD

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Class 10: CMOS Gate Design

Rise Delay Time (Weste p264-267)

Re-writing

Joseph A. Elias, PhD

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Class 10: CMOS Gate Design

Rise Delay Time (Weste p264-267)

Has the form:

where

Joseph A. Elias, PhD

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Class 10: CMOS Gate Design

Fall Delay Time (Weste p264-267) Similar to rise time delay, the fall time delay as a function of fan-in and fan-out:

Assuming equal-sized gates (n/p size fixed) is the case (as in standard cells and gate arrays)
Joseph A. Elias, PhD

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Class 10: CMOS Gate Design

Equal Delays (Weste p264-267) Assuming equal delays gives

Where the beta ratios are

So p-ch would be made (n / m p) times wider for equal rise and fall delay

Joseph A. Elias, PhD

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