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  • Class 02 Transistors I - Details

    Hochgeladen von

    kumaranraj
    9 Ansichten24 Seiten
    The document details the process steps for forming CMOS transistors, including depositing insulating and masking layers, patterning wells and gates, and implanting dopants. Key steps include using masks to define active and isolation regions, growing field oxide for isolation, implanting wells, depositing and patterning polysilicon for the gate, and adjusting thresholds with implants. The process outlined takes silicon through masking, etching, deposition, doping, and thermal drive steps to produce n-well and p-MOS transistors.

    Originalbeschreibung:

    Topics: 1. CMOS Formation – process details

    Originaltitel

    Class 02 Transistors I – details

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    © Attribution Non-Commercial (BY-NC)

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    The document details the process steps for forming CMOS transistors, including depositing insulating and masking layers, patterning wells and gates, and implanting dopants. Key steps include using masks to define active and isolation regions, growing field oxide for isolation, implanting wells, depositing and patterning polysilicon for the gate, and adjusting thresholds with implants. The process outlined takes silicon through masking, etching, deposition, doping, and thermal drive steps to produce n-well and p-MOS transistors.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Als PDF, TXT herunterladen oder online auf Scribd lesen
    Markieren Sie unangemessene Inhalte
    9 Ansichten24 Seiten

    Class 02 Transistors I - Details

    Hochgeladen von

    kumaranraj
    The document details the process steps for forming CMOS transistors, including depositing insulating and masking layers, patterning wells and gates, and implanting dopants. Key steps include using masks to define active and isolation regions, growing field oxide for isolation, implanting wells, depositing and patterning polysilicon for the gate, and adjusting thresholds with implants. The process outlined takes silicon through masking, etching, deposition, doping, and thermal drive steps to produce n-well and p-MOS transistors.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Als PDF, TXT herunterladen oder online auf Scribd lesen
    Markieren Sie unangemessene Inhalte
    von 24

    Class 02: Transistors I details

    Topics: 1. CMOS Formation process details

    Joseph A. Elias, PhD

    Class 02: Transistors I details


    CMOS Formation - Isolation, Nwell (Martin p.42)
    Deposit SiO2, Si3N4, photoresist (PR)

    layout mask

    PR Si3N4 SiO2 Starting silicon

    Joseph A. Elias, PhD

    Class 02: Transistors I details


    CMOS Formation - Isolation, Nwell (Martin p.42)
    Use Active (aka moat, diff-tap) mask to define active and isolation regions; expose PR

    layout
    active

    mask

    PR Si3N4 SiO2 Starting silicon

    Joseph A. Elias, PhD

    Class 02: Transistors I details


    CMOS Formation - Isolation, Nwell (Martin p.42)
    Develop PR

    layout mask

    PR Si3N4 SiO2 Starting silicon

    Joseph A. Elias, PhD

    Class 02: Transistors I details


    CMOS Formation - Isolation, Nwell (Martin p.42)
    Etch Si3N4

    layout mask

    PR Si3N4 SiO2 Starting silicon

    Joseph A. Elias, PhD

    Class 02: Transistors I details


    CMOS Formation - Isolation, Nwell (Martin p.42)
    Remove PR

    layout mask

    Si3N4 SiO2 Starting silicon

    Joseph A. Elias, PhD

    Class 02: Transistors I details


    CMOS Formation - Isolation, Nwell (Martin p.42)
    Grow LOCOS

    layout mask

    Si3N4 SiO2 Starting silicon

    Joseph A. Elias, PhD

    Class 02: Transistors I details


    CMOS Formation - Isolation, Nwell (Martin p.42)
    Remove Si3N4

    layout mask

    SiO2 Starting silicon

    Joseph A. Elias, PhD

    Class 02: Transistors I details


    CMOS Formation - Isolation, Nwell (Martin p.42)
    Deposit PR; Use NWELL mask to define PMOS regions; Expose PR

    layout

    mask

    PR SiO2 Starting silicon

    Joseph A. Elias, PhD

    Class 02: Transistors I details


    CMOS Formation - Isolation, Nwell (Martin p.42)
    Develop PR

    layout

    mask PR SiO2 Starting silicon

    Joseph A. Elias, PhD

    10

    Class 02: Transistors I details


    CMOS Formation - Isolation, Nwell (Martin p.42)
    Implant NWELL (high energy, low dose) Phos layout

    mask PR SiO2 Starting silicon

    Joseph A. Elias, PhD

    11

    Class 02: Transistors I details


    CMOS Formation - Isolation, Nwell (Martin p.42)
    Remove PR

    layout

    mask

    SiO2 Starting silicon

    Joseph A. Elias, PhD

    12

    Class 02: Transistors I details


    CMOS Formation - Isolation, Nwell (Martin p.42)
    Thermal Drive of NWELL

    layout

    mask

    SiO2 Starting silicon

    Joseph A. Elias, PhD

    13

    Class 02: Transistors I details


    CMOS Formation NMOS Vt Adjust (Martin p.42)
    Deposit PR; Use NWELL mask to protect PMOS regions; Expose PR; (can be blanket if n-p known)

    layout

    mask

    PR SiO2 Starting silicon

    Joseph A. Elias, PhD

    14

    Class 02: Transistors I details


    CMOS Formation NMOS Vt Adjust (Martin p.42)
    Develop PR

    layout

    mask

    SiO2 Starting silicon

    Joseph A. Elias, PhD

    15

    Class 02: Transistors I details


    CMOS Formation NMOS Vt Adjust (Martin p.42)
    Implant Vt Adjust (low energy, low dose) Phos layout

    mask

    SiO2 Starting silicon

    Joseph A. Elias, PhD

    16

    Class 02: Transistors I details


    CMOS Formation NMOS Vt Adjust (Martin p.42)
    Remove PR

    layout

    mask

    SiO2 Starting silicon

    Joseph A. Elias, PhD

    17

    Class 02: Transistors I details


    CMOS Formation Poly formation (Martin p.42)
    Deposit Poly; Dope Poly Boron layout

    mask Poly SiO2 Starting silicon

    Joseph A. Elias, PhD

    18

    Class 02: Transistors I details


    CMOS Formation Poly formation (Martin p.42)
    Deposit PR; Use Poly mask to define gate; Expose PR

    layout mask Poly SiO2 Starting silicon

    Joseph A. Elias, PhD

    19

    Class 02: Transistors I details


    CMOS Formation Poly formation (Martin p.42)
    Develop PR

    layout

    mask Poly SiO2 Starting silicon

    Joseph A. Elias, PhD

    20

    Class 02: Transistors I details


    CMOS Formation Poly formation (Martin p.42)
    Etch Poly

    layout

    mask Poly SiO2 Starting silicon

    Joseph A. Elias, PhD

    21

    Class 02: Transistors I details


    CMOS Formation Poly formation (Martin p.42)
    Etch SiO2

    layout

    mask Poly SiO2 Starting silicon

    Joseph A. Elias, PhD

    22

    Class 02: Transistors I details


    CMOS Formation Poly formation (Martin p.42)
    Remove PR

    layout

    mask Poly SiO2 Starting silicon

    Joseph A. Elias, PhD

    23

    Class 02: Transistors I details


    CMOS Formation Poly formation (Martin p.42)
    nwell

    Diff-tap poly

    Joseph A. Elias, PhD

    24

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