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Corsica\Gilligan - DISCRETE
M08 M/B PCB

VER : X02

POWER
SYSTEM
RESET CIRCUIT

AC/BATT
CONNECTOR
PG 41

POWER

Merom
PG 38

(478 Micro-FCPGA)

REGULATOR

PG 40

RUN POWER SW

PG 39

PG 43

CPU VR

PG 45

PG 42

DC/DC

PG 44

+1.5V_RUN/+1.05V_VCCP

PG 3,4

BATT
CHARGER

CLOCK
CK505M+LP

REGULATOR

+1.25V/+1.8V_SUS/+0.9V_DDR_VTT

(Symbol Rev.09)

+3.3V_SUS/+5V_SUS/+3.3V_M
+5V/+3.3V/+1.8V/+1.25_RUN

667/800 MHz FSB

LVDS

VGA CONN.
Crestline
B

PG 17

+3.3V_ALW/+5V_ALW/+15V_ALW

533/667 MHZ DDR II

DDR2-SODIMM1

PCI EXPRESS GFX

PCIEx16

Panel Connector

TVOUT

S-Video
PG 19

1299 uFCBGA

PG 15,16

PG 5,6,7,8,9,10

VGA

PG 18

CRT CONN.
PG 19

www.kythuatvitinh.com
533/667 MHZ DDR II

DDR2-SODIMM2

(Symbol Rev.09)

PG 15,16

USB2.0 (P5)

IDE

LAN

DMI interface

CD-ROM

BCM4401 (B0)

PG 23

33MHz PCI

SATA - HDD
PG 23

SATA0

SATA - HDD
PG 23

SATA1

ICH8-M
676 BGA

PG 11,12,13,14
IHDA

MDC

AUDIO/AMP

(Symbol Rev.09)

CONN

Camera
PG 33

33MHz PCI
PCIEx1
USB2.0 (P6)
PCIEx1
USB2.0 (P9)
PCIEx2
USB2.0 (P7)

+3.3V_LAN

RJ45/Magnetics

PG 35
(Symbol Rev.09)

PG 36

CARDBUS/1394
R5C833
PG 20,21,22

EXPRESS-CARD
R5538
PG 26

PG 32
SPI

LPC

MINI-CARD x1
WWAN
PG 25

PG 26
D-Micro
PG 33

Audio
Jacks
PG 33

Tip
Ring

SIO
MEC5025
128KB Flash
TMKBC

BC
Dash BD

TP/KB
&
Media/Dash BD

KB

PS/2

SIO
BC

128 Pins VTQFP


PG 28

MINI-CARD x2
WLAN
PG 24

ECE5011
Expander
USB 2.0 Hub(4)

USB2.0 (P0,P2)
USB2.0 (P3,P8)

128 Pins VTQFP


PG 29

Conn

PG 30

Media BD

EMC4001
PG 34

Title

Schematic Block Diagram1

C
G
31FM5MB0011 31GM2MB0004
41FM5SS0017 41GM2SS0000
3

QUANTA
COMPUTER

FAN & THERMAL

CIR
PG 31

FLASH

PG 31

External USB
PG 27

SPI

Touchpad

(EXT SIDE)
(EXT BACK)

Size

Document Number
M-08

Date:

Tuesday, March 06, 2007


7

Digitally signed by fdsf


DN: cn=fdsf, o=fsdfsd,
ou=ffsdf,
email=fdfsd@fsdff,
c=US
Rev
0.1
Date:
2010.03.29
17:57:21
of
Sheet
1
51
+07'00'
8

INDEX
Pg#

Description

Power & Ground


DNI LIST

Pg#

Label

Control Signal

Description

Schematic Block Diagram

DC_IN+

AC ADAPTER (19V)

Front Page

PBATT+

MAIN BATTERY + (10~17V)

3-4

Merom

PBATT+

SECOND BATTERY + (10~17V)

5-10

Crestline

PWR_SRC

MAIN POWER (10~19V)

11-14

ICH8M

RTC_PWR3_3V

RTC & +3.3V_RTC_LDO(3.3V)

15-16

DDRII SO-DIMM(200P)

+VCC_CORE

CPU CORE POWER (1.5V)

RUNPWROK

Clock Generator

+15V_ALW

LARGE POWER (15V)

SUS_ON

VGA

+3.3V_RUN

SLP_S3# CTRLD POWER

RUN_ON

22

LCD Conn. & SSP

+3.3V_SUS

SLP_S5# CTRLD POWER

SUS_ENABLE

23

1
2

17
18-21

CRT Conn

+3.3V_ALW

8051 POWER (3.3V)

ALWON/THERM_STP#

24

SATA & IDE Conn

+5V_RUN

SLP_S3# CTRLD POWER

RUN_ON

25

PCCARD/Conn & 1394

+5V_SUS

SLP_S5# CTRLD POWER

SUS_ON

26

Express Card & Smart Card

+5V_HDD

HDD POWER (5V)

+5V_RUN

Mini Card

+5V_MOD

MODULE POWER (5V)

HDDC_EN

27

www.kythuatvitinh.com

28

MDC Conn.

+5V_ALW

LCD/CHARGE POWER (5V)

29

SIO (MEC5004)

+VDDA

AUDIO ANALOG POWER (5V)

AUDIO_AVDD_ON

30

SIO (MEC5018)

+1.5V_RUN

CALISTOGA/ICH7 POWER

RUN_ON

31

SERIAL PORT & USB

+1.05V_VCCP

CPU/CALISTOGA/ICH7 POWER

RUN_ON

32

Flash ROM

+1_8V_SUS

SODIMM POWER

SUSPWROK_5V

33

TP,BT & FIR

+1.8V_RUN

SDVO POWER

RUN_ON

34

Switch,Keyboard & LED

+0.9V_DDR_VTT

SODIMM POWER

RUN_ON

35

FAN & Thermal

+3.3V_LAN

LAN POWER

AUX_EN

36-37

Audio CODEC(STAC9200)/Phone Jack

38-39

LOM (BCM5752)/Switch

40-41

Docking Conn/Q-Switch

42

GND

ALL PAGES

DIGITAL GROUND

System Reset Circuit

AGND_ISL6260

CPU GND

Battery Selector & Charger

AGND_TPS51120

DC/DC POWER GND

45

DDR2_1.8VSUS, 0.9V

AGND1

VTT POWER GND

46

43-44

1.5VSUS,1.05V(VTT)

AGND2

VTT POWER GND

47

1.25V,1.05VM

8731AGND

CHARGER GND

48

CPU_MAX8786(3phase)

49

D/D Power

50

RUN Power Switch

51

VGA DC/DC

52

DCIN/Batt Conn.

53

PAD& SCREW

QUANTA
COMPUTER

Title

54

Index, DNI, Power & Ground


Size

Document Number
M-08

Date:

Monday, March 05, 2007

EMI CAP
1

Rev
0.1
Sheet

of

2
8

51

H_A#[3..16]

<5> H_ADSTB#1

H_DEFER# <5>
H_DRDY# <5>
H_DBSY# <5>
H_BR0# <5>

F1

IERR#
INIT#

D20
B3

LOCK#

H4

RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#

C1
F3
F4
G3
G2

HIT#
HITM#

G6
E4

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#

+1.05V_VCCP
H_INIT# <11>

H_RESET# <5>
H_RS#0 <5>
H_RS#1 <5>
H_RS#2 <5>
H_TRDY# <5>

<5> H_DSTBN#0
<5> H_DSTBP#0
<5> H_DINV#0
<5> H_D#[0..63]

D21
A24
B25

R344
56
2
1
R340
CPU_PROCHOT# 1
H_THERMDA
H_THERMDC

+1.05V_VCCP

R402
1K/F

D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#

N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24

D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47

D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

<5> H_DSTBN#1
<5> H_DSTBP#1
<5> H_DINV#1

<28>

COMP[2]
COMP[3]

R26
U26
AA1
Y1

COMP0
COMP1
COMP2
COMP3

DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#

E5
B5
D24
D6
D7
AE6

V_CPU_GTLREF AD26
CPU_TEST1
C23
CPU_TEST2
D25
CPU_TEST3
C24
CPU_TEST4
AF26
CPU_TEST5
AF1
CPU_TEST6
A26

GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

B22
B23
C21

BSEL[0]
BSEL[1]
BSEL[2]

COMP[0]

<5>

H_DSTBN#2 <5>
H_DSTBP#2 <5>
H_DINV#2 <5>
H_D#[0..63]

<5>

H_DSTBN#3 <5>
H_DSTBP#3 <5>
H_DINV#3 <5>

Note:
H_DPRTSTP need to daisy chain
from ICH8 to IMVP6 to CPU.

BCLK[0]
BCLK[1]

A22
A21

CLK_CPU_BCLK <17>
CLK_CPU_BCLK# <17>

<6,17> CPU_MCH_BSEL0
<6,17> CPU_MCH_BSEL1
<6,17> CPU_MCH_BSEL2

Merom Ball-out Rev 1a

H_THERMDC

R331
1K/F_NC
CPU_TEST1
1
2
R106
1K/F_NC
CPU_TEST2
1
2
C520 0.1U/10V_NC
CPU_TEST4
2
1
R332
0_NC
CPU_TEST6
1
2

For Support XDP:


1. ITP_BPM#5 need PU 51ohms to +1.05V_VCCP.
2. Change R4 & R361 to 51 ohms.
3. Changed R6 & R346 to 51 ohms.
4. Depopulate R2 and changed R8 to 1K/F.

R352
51/F

R354
51

R408
39/F

R409
150

+1.05V_VCCP

+3.3V_ALW

For the purpose of testability, route these signals


through a ground referenced Z0 = 55ohm trace that
ends in a via that is near a GND via and is
accessible through an oscilloscope connection.

Place C close to the


CPU_TEST4 pin. Make sure
CPU_TEST4 routing is
reference to GND and away
from other noisy signal.

Layout Note:
Place couple 0.1uF Decoupling
caps with in 0.1" ITP connector.

+1.05V_VCCP

CPU_TEST3
CPU_TEST5

PAD T17
PAD T97

BSEL2

BSEL1

COMP0
COMP1
COMP2
COMP3

BSEL0

FSB

BCLK

533

133

667

166

800

200

R398
54.9/F

+3.3V_SUS

H_RESET#

Layout Note:
Place R8 close ITP.

ITP_TCK

R406 649/F
2
1

RESET#

11

FBO

8
9

<17> CLK_CPU_ITP#
<17> CLK_CPU_ITP

R350 27/F
2
1

12

ITP_TCK
ITP_TRST#

10
14
16
18
20
22

BCLKN
BCLKP
GND0
GND1
GND2
GND3
GND4
GND5

DBR#
DBA#

BPM0#
BPM1#
BPM2#
BPM3#
BPM4#
BPM5#
NC0
NC1
GND_0
GND_1

25
24

23
21
19
17
15
13
4
6
29
30

C472 0.1U/10V
2
1

ITP_DBRESET#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#51
R403

27
28
26

0R416

VTT0
VTT1
VTAP

0_NCR414
0_NC
R414
2

2 0
22.6/F
2

TDI
TMS
TCK
TDO
TRST#

Signal

R412
2

150
1

R351
1

2
R3531

1
2
5
7
3

C476 0.1U/10V
2
1

ITP_TDI
ITP_TMS
ITP_TCK
ITP_TDO
ITP_TRST#

ITP700 layout guidelines


JITP1

Resistor Value Connect To Resistor Placement

TDI

150 ohm 5%

VCCP

TMS

39 ohm 1%

VCCP

Within 200ps of ITP connector

500 to 680
ohm 5%

GND

Place the pull-down near CPU

TCK

27 ohm 1%

GND

Connect to TCK pin of CPU and then


connect it to FBO pin of ITP connector
in daisy chain. Place the pull-down
near TCK0 pin of ITP connector

TDO

51 ohm 5%

VCCP

Place the pull-up near ITP

22.6 ohm 1%
series resistor
and pullup 51
ohm 1%.

VCCP

Connect to CPURST# pin of GMCH through


the series resistor placed within
200ps of ITP connector. Place the
pull-up after the series resistor from
ITP connector.

2
51_NC

RESET#

Reserved for support


XDP debug.

R388
27.4/F

+1.05V_VCCP

ITP700Flex_NC

R392
54.9/F

Comp0,2 connect with Zo=27.4ohm,Comp1,3


connect with Zo=55ohm, make those traces
length shorter than 0.5".Trace should be
at least 25 mils away from any other
toggling signal.

Place the pull-up near CPU

TRST#

R400
27.4/F

2200P/50V_NC

C163
1

H_THERMDA

Merom Ball-out Rev 1a

Populate ITP700Flex for bringup

H_DPRSTP# <6,11,45>
H_DPSLP# <11>
H_DPWR# <5>
H_PWRGOOD <11>
H_CPUSLP# <5>
H_PSI# <45>

RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]
RSVD[10]

R404
2K/F

M4
N5
T2
V3
B2
C3
D2
D22
D3
F6

H_THERMTRIP# <34>

+1.05V_VCCP

H CLK

STPCLK#
LINT0
LINT1
SMI#

THERMTRIP#

H_THERMTRIP#
R330
56
1
2

MISC COMP[1]

D5
C6
B4
A3

C7

H_STPCLK#
H_INTR
H_NMI
H_SMI#

A20M#
FERR#
IGNNE#

www.kythuatvitinh.com
A6
A5
C4

H_D#[0..63]

H_D#[0..63]
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31

Layout Note:
Place voltage
divider within
0.5" of GTLREF
pin

+1.05V_VCCP
0_NC
2
EC_CPU_PROCHOT#
H_THERMDA <34>
H_THERMDC <34>

H_D#[0..63]

E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25

H_D#[0..63]

H_HIT# <5>
H_HITM# <5>

ITP_DBRESET# <13,29>

U15B
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15

H_LOCK# <5>
H_RESET#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
ITP_DBRESET#

THERMAL
PROCHOT#
THERMDA
THERMDC

R346 56
H_IERR# 1
2

AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20

RESERVED

<11>
<11>
<11>
<11>

A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#

ICH

<11> H_A20M#
<11> H_FERR#
<11> H_IGNNE#

REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#

H5
F21
E1

H_D#[0..63]

Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1

BR0#

H_ADS# <5>
H_BNR# <5>
H_BPRI# <5>

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_A#[17..35]

DEFER#
DRDY#
DBSY#

<5> H_D#[0..63]

H1
E2
G5

DATA GRP 1

K3
H2
K2
J3
L1

ADS#
BNR#
BPRI#

ADDR GROUP 1

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#

CONTROL

H_REQ#[0..4]

<5> H_A#[17..35]

DATA GRP 0

J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1

ADDR GROUP 0

<5> H_ADSTB#0
<5> H_REQ#[0..4]

U15A
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

XDP/ITP SIGNALS

<5> H_A#[3..16]

DATA GRP 2

DATA GRP 3

DELL CONFIDENTIAL/PROPRIETARY
Title
Merom Processor (HOST BUS)
Size

Document Number
M-08

Date:

Monday, March 05, 2007


7

Rev
0.1
Sheet

of

3
8

51

+VCC_CORE

+VCC_CORE
U15C

1
C208
10U/4V

C462
10U/4V

C207
10U/4V

1
C507
10U/4V

1
C508
10U/4V

+VCC_CORE

8 inside cavity, north side, secondary layer.

1
C505
10U/4V

C504
10U/4V

C506
10U/4V

1
C502
10U/4V

1
C503
10U/4V

+VCC_CORE

+VCC_CORE

C448
10U/4V

C447
10U/4V

C501
10U/4V

C442
10U/4V

C449
10U/4V

U15D
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

VCCA[01]
VCCA[02]

B26
C26

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

AD6
AF5
AE5
AF4
AE3
AF3
AE2

VCCSENSE

AF7

VCCSENSE

VSSSENSE

AE7

VSSSENSE

A4
A8
A11
A14
A16
A19
A23
AF2
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3

+1.05V_VCCP

C206
10U/4V

C205
10U/4V

VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]

+ C487
220U/4V
2

1
C204
10U/4V

1
C203
10U/4V

C492
10U/4V

All use 10U 4V(+-20%,X6S,0805)Pb-Free.

+VCC_CORE

A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18

VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]

C446
10U/4V

6 inside cavity, north side, primary layer.

1
C188
10U/4V

C430
0.01U/25V

VCCSENSE <45>

C440
10U/4V

Layout Note:
Place C105 near PIN
B26.

VSSSENSE <45>

C189
10U/4V

.
+VCC_CORE
1

C187
10U/4V

<45>
<45>
<45>
<45>
<45>
<45>
<45>

Merom Ball-out Rev 1a

1
C186
10U/4V

C185
10U/4V

1
C184
10U/4V

+VCC_CORE

VID0
VID1
VID2
VID3
VID4
VID5
VID6

C445
10U/4V

C444
10U/4V

C443
10U/4V

C458
10U/4V

C491
10U/4V

+VCC_CORE

+1.5V_RUN

www.kythuatvitinh.com
8 inside cavity, south side, secondary layer.

R413
100/F
2

6 inside cavity, south side, primary layer.

VCCSENSE
VSSSENSE
+PWR_SRC

Layout out:
Place these inside socket cavity on North side secondary.

+ C249
100U/25V

+ C98
100U/25V_NC

Merom Ball-out Rev 1a

R410
100/F

1
C459
0.1U/10V

+ C53
100U/25V

1
C488
0.1U/10V

1
C460
0.1U/10V

1
C489
0.1U/10V

1
C461
0.1U/10V

1
2

1
2

C490
0.1U/10V

+ C250
100U/25V

60

+1.05V_VCCP

Layout Note:
Need to add 100uF cap on PWR_SRC for cap singing.
Place on PWR_SRC near +VCC_CORE.

Route VCCSENSE and VSSSENSE


traces at 27.4ohms and
length matched to within 25
mil. Place PU and PD within
2 inch of CPU.

DELL CONFIDENTIAL/PROPRIETARY
Title
Merom Processor (POWER)

Size

Document Number
M-08

Date:

Monday, March 05, 2007


7

Rev
0.1
Sheet

of

4
8

51

H_A#[3..35]

U19A
H_D#[0..63]

<3> H_D#[0..63]

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

+1.05V_VCCP

R360
221/F

H_SWING

C465
0.1U/10V

R368
100/F

E2
G2
G7
M6
H7
H3
G4
F3
N8
H2
M10
N12
N9
H5
P13
K9
M2
W10
Y8
V4
M3
J1
N5
N3
W6
W9
N2
Y7
Y9
P4
W3
N1
AD12
AE3
AD9
AC9
AC7
AC14
AD11
AC11
AB2
AD7
AB1
Y3
AC6
AE2
AC5
AG3
AJ9
AH8
AJ14
AE9
AE11
AH12
AJ5
AH5
AJ6
AE7
AJ7
AJ2
AE5
AJ3
AH2
AH13

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

H_A#[3..35]

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19

H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#

G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7

H_ADS# <3>
H_ADSTB#0 <3>
H_ADSTB#1 <3>
H_BNR# <3>
H_BPRI# <3>
H_BR0# <3>
H_DEFER# <3>
H_DBSY# <3>
CLK_MCH_BCLK <17>
CLK_MCH_BCLK# <17>
H_DPWR# <3>
H_DRDY# <3>
H_HIT# <3>
H_HITM# <3>
H_LOCK# <3>
H_TRDY# <3>

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

K5
L2
AD13
AE13

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

M7
K3
AD2
AH11

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

<3>
<3>
<3>
<3>

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

L7
K2
AC2
AJ10

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

<3>
<3>
<3>
<3>

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

M14
E13
A11
H13
B12

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#_0
H_RS#_1
H_RS#_2

E12
D7
D8

H_RS#0 <3>
H_RS#1 <3>
H_RS#2 <3>

<3>

R399
54.9/F

R401
54.9/F

H_SCOMP
H_SCOMP#

H_RCOMP

Layout Note:
H_RCOMP trace should be
10-mil wide with 20-mil
spacing.

+1.05V_VCCP

H_SWING
H_RCOMP

B3
C2

H_SWING
H_RCOMP

R361
24.9/F

H_SCOMP
H_SCOMP#

W1
W2

H_SCOMP
H_SCOMP#

B6
E5

H_CPURST#
H_CPUSLP#

<3> H_RESET#
<3> H_CPUSLP#

R357
1K/F

B9
A9

<3>
<3>
<3>
<3>

<3>
<3>
<3>
<3>
<3>

H_AVREF
H_DVREF
CRESTLINE_1p0

C456
0.1U/10V

AJ0QP210T00

R362
2K/F

H_REF

HOST

www.kythuatvitinh.com
+1.05V_VCCP

Layout Note:
Place the 0.1 uF
decoupling capacitor
within 100 mils from
GMCH pins.

DELL CONFIDENTIAL/PROPRIETARY
Title
Crestline (HOST)

Size

Document Number
M-08

Date:

Tuesday, March 06, 2007


7

Rev
0.1
Sheet

of

5
8

51

PM_EXTTS#0
PM_EXTTS#1

2 10K
2 10K

+1.05V_VCCP
THERMTRIP_MCH#

+VCC_PEG

SM_CK#_0
SM_CK#_1
SM_CK#_3
SM_CK#_4

AW30
BA23
AW25
AW23

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

SM_CKE_0
SM_CKE_1
SM_CKE_3
SM_CKE_4

BE29
AY32
BD39
BG37

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

<15,16>
<15,16>
<15,16>
<15,16>

SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3

BG20
BK16
BG16
BE13

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

<15,16>
<15,16>
<15,16>
<15,16>

SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3

BH18
BJ15
BJ14
BE16

M_ODT0
M_ODT1
M_ODT2
M_ODT3

SM_RCOMP
SM_RCOMP#

BL15
BK14

SMRCOMPP
SMRCOMPN

SM_RCOMP_VOH
SM_RCOMP_VOL

BK31
BL31

SM_RCOMP_VOH
SM_RCOMP_VOL

SM_VREF_0
SM_VREF_1

AR49
AW4

<15>
<15>
<15>
<15>

+1.8V_SUS

<15>
<15>
<15>
<15>

<15,16>
<15,16>
<15,16>
<15,16>

R424
20/F

SMRCOMPP
SMRCOMPN

R422
20/F

+1.25V_RUN

LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK

G51
E51
F49

LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2

G50
E50
F48

LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2

G44
B47
B45

LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2

E44
A47
A45

LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2

E27
G27
K27

TVA_DAC
TVB_DAC
TVC_DAC

F27
J27
L27

TVA_RTN
TVB_RTN
TVC_RTN

M35
P33

TV_DCONSEL_0
TV_DCONSEL_1

H32
G32
K29
J29
F29
E29

CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#

K33
G35
F33
C32
E33

CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC

Non-iAMT

L41
L43
N41
N40
D46
C45
D44
E42

GRAPHICS

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

MCH_CLVREF
2

V_DDR_MCH_REF

R405
1K/F

C522
0.1U/10V

R407
392/F

DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#

B42
C42
H48
H47

PEG_CLK
PEG_CLK#

K44
K45

CLK_MCH_3GPLL <17>
CLK_MCH_3GPLL# <17>

TV

R395 56
1
2

AV29
BB23
BA25
AV23

L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN

+3.3V_RUN

RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD36
RSVD37
RSVD38
RSVD39
RSVD40
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45

SM_CK_0
SM_CK_1
SM_CK_3
SM_CK_4

J40
H39
E39
E40
C37
D35
K40

2
DDR_A_MA14
DDR_B_MA14

<15,16> DDR_A_MA14
<15,16> DDR_B_MA14

H10
B51
BJ20
BK22
BF19
BH20
BK18
BJ18
BF23
BG23
BC23
BD24
BJ29
BE24
BH39
AW20
BK20
C48
D47
B44
C44
A35
B37
B36
B34
C34

RSVD

Santa Rosa Platform MOW WW15


For 4Gb DRAM support,
change Pin-BJ29 to DDR_A_MA14,
change Pin-BE24 to DDR_B_MA14.

R375 1
R383 1

MUXING

2
1

1
R426
1K/F

C560
2.2U/10V

LVDS

SM_RCOMP_VOL
C563
0.01U/25V

U19C

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14

CLK

1
R425
3.01K/F

1
2

C559
2.2U/10V

P36
P37
R35
N35
AR12
AR13
AM12
AN13
J12
AR37
AM36
AL36
AM37
D20

DDR

1
2

R421
1K/F

C564
0.01U/25V

U19B

+1.8V_SUS

SM_RCOMP_VOH

PCI-EXPRESS

PEG_COMPI
PEG_COMPO

N43
M43

VCC3G_PCIE_R

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

J51
L51
N47
T45
T50
U40
Y44
Y40
AB51
W49
AD44
AD40
AG46
AH49
AG45
AG41

PCIE_MRX_GTX_N0
PCIE_MRX_GTX_N1
PCIE_MRX_GTX_N2
PCIE_MRX_GTX_N3
PCIE_MRX_GTX_N4
PCIE_MRX_GTX_N5
PCIE_MRX_GTX_N6
PCIE_MRX_GTX_N7
PCIE_MRX_GTX_N8
PCIE_MRX_GTX_N9
PCIE_MRX_GTX_N10
PCIE_MRX_GTX_N11
PCIE_MRX_GTX_N12
PCIE_MRX_GTX_N13
PCIE_MRX_GTX_N14
PCIE_MRX_GTX_N15

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

J50
L50
M47
U44
T49
T41
W45
W41
AB50
Y48
AC45
AC41
AH47
AG49
AH45
AG42

PCIE_MRX_GTX_P0
PCIE_MRX_GTX_P1
PCIE_MRX_GTX_P2
PCIE_MRX_GTX_P3
PCIE_MRX_GTX_P4
PCIE_MRX_GTX_P5
PCIE_MRX_GTX_P6
PCIE_MRX_GTX_P7
PCIE_MRX_GTX_P8
PCIE_MRX_GTX_P9
PCIE_MRX_GTX_P10
PCIE_MRX_GTX_P11
PCIE_MRX_GTX_P12
PCIE_MRX_GTX_P13
PCIE_MRX_GTX_P14
PCIE_MRX_GTX_P15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

N45
U39
U47
N51
R50
T42
Y43
W46
W38
AD39
AC46
AC49
AC42
AH39
AE49
AH44

PCIE_MTX_GRX_N0
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_N4
PCIE_MTX_GRX_N5
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_N8
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_N10
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_N13
PCIE_MTX_GRX_N14
PCIE_MTX_GRX_N15

PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

M45
T38
T46
N50
R51
U43
W42
Y47
Y39
AC38
AD47
AC50
AD43
AG39
AE50
AH43

PCIE_MTX_GRX_P0
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_P4
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_P7
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_P9
PCIE_MTX_GRX_P10
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_P12
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_P14
PCIE_MTX_GRX_P15

R389 24.9/F
1
2

PCIE_MRX_GTX_N[0..15] <18>

PCIE_MRX_GTX_P[0..15] <18>

PCIE_MTX_GRX_N[0..15] <18>
B

1 4.02K/F_NC
1 4.02K/F_NC

PM_EXTTS#0
PM_EXTTS#1

<34> THERMTRIP_MCH#
<13,45> DPRSLPVR

R363

T37
T38
T42
T44
T43
T41
T40
T36
T35
T30
T25
T29
T27
T24
T23
T39

DMI

0
TP_NC1
TP_NC2
TP_NC3
TP_NC4
TP_NC5
TP_NC6
TP_NC7
TP_NC8
TP_NC9
TP_NC10
TP_NC11
TP_NC12
TP_NC13
TP_NC14
TP_NC15
TP_NC16

BJ51
BK51
BK50
BL50
BL49
BL3
BL2
BK1
BJ1
E1
A5
C51
B50
A50
A49
BK2

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16

NC

PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD

PM_BM_BUSY#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR

PM

G41
L39
L36
J36
AW49
PLTRST#_R
AV20
THERMTRIP_MCH# N20
G36
1
2

<13> PM_BMBUSY#
<3,11,45> H_DPRSTP#
<15> PM_EXTTS#0
<15> PM_EXTTS#1
<13,38> ICH_PWRGD

DMI_MRX_ITX_N0
DMI_MRX_ITX_N1
DMI_MRX_ITX_N2
DMI_MRX_ITX_N3

<12>
<12>
<12>
<12>

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

AM47
AJ39
AN41
AN45

DMI_MRX_ITX_P0
DMI_MRX_ITX_P1
DMI_MRX_ITX_P2
DMI_MRX_ITX_P3

<12>
<12>
<12>
<12>

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

AJ46
AJ41
AM40
AM44

DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3

<12>
<12>
<12>
<12>

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

AJ47
AJ42
AM39
AM43

DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3

<12>
<12>
<12>
<12>

E35
A39
C38
B39
E36

T83 PAD
T19 PAD
T20 PAD
T22 PAD
T21 PAD

CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF

AM49
AK50
AT43
AN49
AM50

CFG9

SDVO_CTRL_CLK
SDVO_CTRL_DATA
CLK_REQ#
ICH_SYNC#

H35
K36
G39
G40

TEST_1
TEST_2

A37
R32

CL_CLK0 <13>
CL_DATA0 <13>
ICH_CL_PWROK <13,28>
ICH_CL_RST0# <13>

CFG20

Low=No SDVO Device Present


(default)
SDVO_CRTL_DATA SDVO Present. High=SDVO Device Present
CLK_3GPLLREQ# <17>
MCH_ICH_SYNC# <13>

DELL CONFIDENTIAL/PROPRIETARY
R356
0

100
R415

1
3

CFG19

MCH_CLVREF

R396
20K

Low=DMIx2
DMI X2 Select High=DMIx4(Default)
Low= Reveise Lane
PCI Express
Graphic Lane High=Normal operation
FSB Dynamic
Low=Dynamic ODT Disable
ODT
High=Dynamic ODT Enable(default).
DMI Lane
Low=Normal(default).
Reversal
High=Lane Reversed
Low=Only SDVO or PCIEx1 is
SDVO/PCIE
operational (defaults)
Concurrent
High=SDVO and PCIEx1 are operating
Operation
simultaneously via PEG port

CFG5

CFG16

CRESTLINE_1p0

PCIE_MTX_GRX_P[0..15] <18>

CRESTLINE_1p0
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VR_EN

1 4.02K/F_NC

AN47
AJ38
AN42
AN46

T92
T91

1 4.02K/F_NC

GRAPHICS VID

T95
T89
T90
T79
T82
T88

1 4.02K/F_NC

ME

T94
T84
T85

CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20

MISC

T80
T26

P27
N27
N24
C21
C23
F23
N23
G23
J20
C20
R24
L23
J23
E23
E20
K23
M20
M24
L32
N33
L35

CFG

<3,17> CPU_MCH_BSEL0
<3,17> CPU_MCH_BSEL1
<3,17> CPU_MCH_BSEL2
PAD
PAD
R377 2
PAD
PAD
PAD
R366 2
PAD
PAD
PAD
PAD
PAD
PAD
R391 2
+3.3V_RUN
PAD
PAD
R381 2
R382 2

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

VGA

www.kythuatvitinh.com

Layout Note:
Location of all MCH_CFG strap
resistors needs to be close to
minmize stub.

PLTRST#_R 2

R160
1

0_0402
2

PLTRST# <12,28>

R161
1

0_0402_NC
2

SB_NB_PCIE_RST# <12>

Title
Crestline (VGA,DMI)
Size

Document Number
M-08

Date:

Tuesday, March 06, 2007


7

Rev
0.1
Sheet

of

6
8

51

A
MEMORY

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

SYSTEM

<15> DDR_B_D[0..63]

U19D
DDR_A_D0 AR43
DDR_A_D1AW44
DDR_A_D2 BA45
DDR_A_D3 AY46
DDR_A_D4 AR41
DDR_A_D5 AR45
DDR_A_D6 AT42
DDR_A_D7AW47
DDR_A_D8 BB45
DDR_A_D9 BF48
DDR_A_D10BG47
DDR_A_D11BJ45
DDR_A_D12BB47
DDR_A_D13BG50
DDR_A_D14BH49
DDR_A_D15BE45
DDR_A_D16
AW43
DDR_A_D17BE44
DDR_A_D18BG42
DDR_A_D19BE40
DDR_A_D20BF44
DDR_A_D21BH45
DDR_A_D22BG40
DDR_A_D23BF40
DDR_A_D24AR40
DDR_A_D25
AW40
DDR_A_D26AT39
DDR_A_D27
AW36
DDR_A_D28
AW41
DDR_A_D29AY41
DDR_A_D30AV38
DDR_A_D31AT38
DDR_A_D32AV13
DDR_A_D33AT13
DDR_A_D34
AW11
DDR_A_D35AV11
DDR_A_D36AU15
DDR_A_D37AT11
DDR_A_D38BA13
DDR_A_D39BA11
DDR_A_D40BE10
DDR_A_D41BD10
DDR_A_D42 BD8
DDR_A_D43 AY9
DDR_A_D44BG10
DDR_A_D45AW9
DDR_A_D46 BD7
DDR_A_D47 BB9
DDR_A_D48 BB5
DDR_A_D49 AY7
DDR_A_D50 AT5
DDR_A_D51 AT7
DDR_A_D52 AY6
DDR_A_D53 BB7
DDR_A_D54 AR5
DDR_A_D55 AR8
DDR_A_D56 AR9
DDR_A_D57 AN3
DDR_A_D58 AM8
DDR_A_D59AN10
DDR_A_D60 AT9
DDR_A_D61 AN9
DDR_A_D62 AM9
DDR_A_D63AN11

SA_BS_0
SA_BS_1
SA_BS_2

BB19
BK19
BF29

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

SA_CAS#

BL17

DDR_A_CAS#

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

AT45
BD44
BD42
AW38
AW13
BG8
AY5
AN6

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

AT46
BE48
BB43
BC37
BB16
BH6
BB2
AP3
AT47
BD47
BC41
BA37
BA16
BH7
BC1
AP2

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13

BJ19
BD20
BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28
BC19
BE28
BG30
BJ16

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

SA_RAS#
SA_RCVEN#

BE18
AY20

DDR_A_RAS#

SA_WE#

BA19

DDR_A_CAS# <15,16>
DDR_A_DM[0..7] <15>

<15>

DDR_A_DQS#[0..7]

DDR_A_MA[0..13]

U19E
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_A_BS0 <15,16>
DDR_A_BS1 <15,16>
DDR_A_BS2 <15,16>

DDR_A_DQS[0..7]

<15>

<15,16>

AP49
AR51
AW50
AW51
AN51
AN50
AV50
AV49
BA50
BB50
BA49
BE50
BA51
AY49
BF50
BF49
BJ50
BJ44
BJ43
BL43
BK47
BK49
BK43
BK42
BJ41
BL41
BJ37
BJ36
BK41
BJ40
BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12
BJ10
BL9
BK5
BL5
BK9
BK10
BJ8
BJ6
BF4
BH5
BG1
BC2
BK3
BE4
BD3
BJ2
BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

<15> DDR_A_D[0..63]

MEMORY

SYSTEM

SB_BS_0
SB_BS_1
SB_BS_2

AY17
BG18
BG36

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

SB_CAS#

BE17

DDR_B_CAS#

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

AR50
BD49
BK45
BL39
BH12
BJ7
BF3
AW2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

AT50
BD50
BK46
BK39
BJ12
BL7
BE2
AV2
AU50
BC50
BL45
BK38
BK12
BK7
BF2
AV3

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13

BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

SB_RAS#
SB_RCVEN#

AV16
AY18

DDR_B_RAS#

SB_WE#

BC17

DDR_B_WE#

DDR_B_BS0 <15,16>
DDR_B_BS1 <15,16>
DDR_B_BS2 <15,16>

DDR_B_CAS# <15,16>
DDR_B_DM[0..7] <15>

DDR_B_DQS[0..7]

<15>

DDR_B_DQS#[0..7]

DDR_B_MA[0..13]

<15>

<15,16>

DDR_A_WE#

DDR_A_WE# <15,16>

CRESTLINE_1p0

DDR

DDR

www.kythuatvitinh.com
DDR_A_RAS# <15,16>
T102 PAD

DDR_B_RAS# <15,16>
T103 PAD
DDR_B_WE# <15,16>

CRESTLINE_1p0

DELL CONFIDENTIAL/PROPRIETARY
Title
Crestline (DDR2)

Size

Document Number
M-08

Date:

Monday, March 05, 2007


7

Rev
0.1
Sheet

of

7
8

51

+3.3V_RUN

AU32
AU33
AU35
AV33
AW33
AW35
AY35
BA32
BA33
BA35
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35
BF33
BF34
BG32
BG33
BG35
BH32
BH34
BH35
BJ32
BJ33
BJ34
BK32
BK33
BK34
BK35
BL33
AU30

VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36

R20
T14
W13
W14
Y12
AA20
AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31
AJ20
AN14

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34

+1.05V_VCCP

+VCC_GMCH
1
C513
0.22U/10V

1
C512
0.22U/10V

C192
22U/4V

C202
220U/2.5V

Layout Note:
370 mils from edge.

C517
0.1U/10V

Layout Note:
Inside GMCH cavity.

AB33
AB36
AB37
AC33
AC35
AC36
AD35
AD36
AF33
AF36
AH33
AH35
AH36
AH37
AJ33
AJ35
AK33
AK35
AK36
AK37
AD33
AJ36
AM35
AL33
AL35
AA33
AA35
AA36
AP35
AP36
AR35
AR36
Y32
Y33
Y35
Y36
Y37
T30
T34
T35
U29
U31
U32
U33
U35
U36
V32
V33
V36
V37

VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44
VCC_NCTF_45
VCC_NCTF_46
VCC_NCTF_47
VCC_NCTF_48
VCC_NCTF_49
VCC_NCTF_50

VSS NCTF

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21

T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28

POWER
VSS SCB

POWER

+VCC_SM

D29
1

+VCC_GMCH_L

SDMK0340L-7-F

VCC_13

T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31

10
2

R30

VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83

VCC_1
VCC_2
VCC_3
VCC_5
VCC_4
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12

U19F
R341
1

VCC CORE

+VCC_GMCH AT35
AT34
AH28
AC32
AC31
AK32
AJ31
AJ28
AH32
AH31
AH29
AF32

VCC NCTF

U19G

VSS_SCB1
VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6

A3
B2
C1
BL1
BL51
A51

C526
0.1U/10V

1
C527
0.22U/10V

C529
0.22U/10V

1
2

1
2

C239
22U/4V

Layout Note:
Place close to GMCH edge.

VCC AXM

VCC_AXM_NCTF_1
VCC_AXM_NCTF_2
VCC_AXM_NCTF_3
VCC_AXM_NCTF_4
VCC_AXM_NCTF_5
VCC_AXM_NCTF_6
VCC_AXM_NCTF_7
VCC_AXM_NCTF_8
VCC_AXM_NCTF_9
VCC_AXM_NCTF_10
VCC_AXM_NCTF_11
VCC_AXM_NCTF_12
VCC_AXM_NCTF_13
VCC_AXM_NCTF_14
VCC_AXM_NCTF_15
VCC_AXM_NCTF_16
VCC_AXM_NCTF_17
VCC_AXM_NCTF_18
VCC_AXM_NCTF_19

C534
1U/10V

Layout Note:
Place C901 where LVDS
and DDR2 taps.

1
C253
22U/4V

C572
330U/6.3V

+
C530
0.1U/10V

2
1
C536
1U/10V

1
C557
0.47U/10V

1
C547
0.22U/10V

1
C549
0.22U/10V

1
C537
0.1U/10V

1
C531
0.1U/10V

+VCC_SM

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7

AW45
BC39
BE39
BD17
BD4
AW8
AT6

CRESTLINE_1p0

+1.8V_SUS

VCC GFX NCTF

AL24
AL26
AL28
AM26
AM28
AM29
AM31
AM32
AM33
AP29
AP31
AP32
AP33
AL29
AL31
AL32
AR31
AR32
AR33

AT33 +VCC_AXM
AT31
AK29
AK24
AK23
AJ26
AJ23

VCC AXM NCTF

C521
0.1U/10V

1
2

1
2

C523
0.1U/10V

Non-iAMT

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

+VCC_AXM

VCC SM LF

VCC GFX

VCC SM

www.kythuatvitinh.com
Layout Note:
Inside GMCH cavity.

+1.05V_VCCP

VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_5
VCC_AXM_6
VCC_AXM_7

C254
22U/4V

Layout Note:
Place on the edge.
A

DELL CONFIDENTIAL/PROPRIETARY
CRESTLINE_1p0

Title
Crestline (VCC,NCTF)

Size

Document Number
M-08

Date:

Monday, March 05, 2007

Rev
0.1
Sheet
1

of

51

U19H

K50

VCCA_PEG_BG

K49

VSSA_PEG_BG

C519
0.1U/10V

C466
0.1U/10V

+VCCA_PEG_PLL

U51

VCCA_PEG_PLL

2
1

1
1

2
1

+3.3V_RUN

Non-iAMT
+1.25V_RUN
+1.25V_RUN

Place on the edge.

VCC_AXD_1
VCC_AXD_2
VCC_AXD_3
VCC_AXD_4
VCC_AXD_5
VCC_AXD_6

AT23
AU28
AU24
AT29
AT25
AT30

VCC_AXD_NCTF

AR29

+VCC_AXD_L

C533
1U/10V

PJP17
2+VCC_AXD_R
0

L39

Reserved L81 pad for


inductor.

C251
22U/10V

+VCC_AXF

Place caps close


to VCC_AXD.

+VCCA_MPLL

+ C235
220U/4V

C499
4.7U/10V

+VCCA_SM

C541
22U/4V

C532
22U/4V

C525
4.7U/6.3V

+ C246
100U/6.3V

+1.25V_RUN

C524
1U/10V

BC29
BB29

VCCA_SM_CK_1
VCCA_SM_CK_2

VCC_DMI

AJ50

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

BK24
BK23
BJ24
BJ23

+VCC_AXF

VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
VCCA_SM_10
VCCA_SM_11
VCCA_SM_NCTF_1
VCCA_SM_NCTF_2

AXF

AT22
AT21
AT19
AT18
AT17
AR17
AR16

B23
B21
A21

+1.25V_RUN
+VCC_SM_CK

C452
1U/10V

C453
10U/6.3V

Place caps close


to VCC_AXF

POWER

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

C518
0.1U/10V

PJP16

SM CK

C242
22U/10V

C528
0.1U/10V

VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5

A SM

+VCCA_MPLL_L

AW18
AV19
AU19
AU18
AU17

VSSA_LVDS

C496
0.47U/6.3V

VCCA_LVDS

B41

R342
10_NC

A41

L37
BLM11A121S
1
R411
0.5/F/0603
1
2

+3.3V_RUN

2
2

C241
22U/10V

1
BLM11A121S
1

+VCCA_HPLL

A LVDS

L36

+1.05V_VCCP

VCCA_MPLL

+VCC_HV_L

Place on the edge.

AM2

VTT

VCCA_HPLL

+VCCA_MPLL

AXD

VCCA_DPLLB

AL2

PLL

FB_120ohm+-25%_100mHz
_200mA_0.2ohm DC

+1.25V_RUN

H49
+VCCA_HPLL

A PEG

Non-iAMT 45mA MAx.

D30
CH751H-40HPT_NC

C493
4.7U/10V

VCCA_DPLLA

B49

VSSA_DAC_BG

VCCA_DAC_BG

B32

C497
2.2U/6.3V

A30

VCCA_CRT_DAC_1
VCCA_CRT_DAC_2

+1.05V_VCCP

VCC_HV

U13
U12
U11
U9
U8
U7
U5
U3
U2
U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
R3
R2
R1

A33
B33

VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22

VCCSYNC

CRT

J32

VTTLF1
VTTLF2
VTTLF3

A7
F2
AH1

+VCC_RXR_DMI

C514
10U/6.3V

C216
220U/4V

AH50
AH51

91nH/1.5A

91uH+-20%_1.5A

+1.05V_VCCP

+VTTLF1
+VTTLF2
+VTTLF3

L27
2

C509
0.1U/10V

C233
220U/4V

91uH+-20%_1.5A
C515
10U/6.3V

+
CRESTLINE_1p0

91nH/1.5A

VCCD_LVDS_1
VCCD_LVDS_2

VCC_RXR_DMI_1
VCC_RXR_DMI_2

+1.05V_VCCP

L25

J41
H42

1
2

C500
0.1U/10V

1
C454
0.47U/10V

L38
1uH/300mA
2

+VCC_SM_CK

+1.8V_SUS
1

1uH+-20%_300mA
R423
1/F/0603

C550
0.1U/10V

1 2

1
C252
22U/10V

C473
0.47U/10V

C516
0.47U/10V

+VTTLF1
+VTTLF2
+VTTLF3
1

C494
10U/6.3V

C457
0.1U/10V

+VCC_PEG

VCCD_PEG_PLL

C463
0.1U/10V

U48

AD51
W50
W51
V49
V50

VCCD_HPLL

AN2

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5

VCCD_QDAC

+3.3V_RUN

VTTLF

N28

VCC_HV_1
VCC_HV_2

HV

VCCD_CRT
VCCD_TVDAC

Non-iAMT

+VCCA_PEG_PLL

1
R394
1/F/0603

FB_220ohm+-25%_100MHz
_2A_0.1ohm DC

C451
0.022U/16V

+1.25V_RUN
+VCCA_PEG_PLL

1 2

L35
1
2
BLM21PG221SN1D

C483
0.1U/10V

+1.25V_RUN

1
2

C450
10U/6.3V

A43

C40
B40

PEG

M32
L29

+1.5V_RUN

A CK

VCCA_TVA_DAC_1
VCCA_TVA_DAC_2
VCCA_TVB_DAC_1
VCCA_TVB_DAC_2
VCCA_TVC_DAC_1
VCCA_TVC_DAC_2

DMI

C555
0.1U/10V

C539
1U/10V

C538
1U/10V

1
2

C548
22U/4V

C25
B25
C27
B27
B28
A28

VCC_TX_LVDS

TV

+VCCA_SM_CK

D TV/CRT

PJP18

+1.25V_RUN

LVDS

www.kythuatvitinh.com
Non-iAMT

+VCC_SM_CK_L
C552
10U/6.3V

DELL CONFIDENTIAL/PROPRIETARY
Title
Crestline (POWER)

Size

Document Number
M-08

Date:

Monday, March 05, 2007

Rev
0.1
Sheet
1

of

51

U19I
A13
A15
A17
A24
AA21
AA24
AA29
AB20
AB23
AB26
AB28
AB31
AC10
AC13
AC3
AC39
AC43
AC47
AD1
AD21
AD26
AD29
AD3
AD41
AD45
AD49
AD5
AD50
AD8
AE10
AE14
AE6
AF20
AF23
AF24
AF31
AG2
AG38
AG43
AG47
AG50
AH3
AH40
AH41
AH7
AH9
AJ11
AJ13
AJ21
AJ24
AJ29
AJ32
AJ43
AJ45
AJ49
AK20
AK21
AK26
AK28
AK31
AK51
AL1
AM11
AM13
AM3
AM4
AM41
AM45
AN1
AN38
AN39
AN43
AN5
AN7
AP4
AP48
AP50
AR11
AR2
AR39
AR44
AR47
AR7
AT10
AT14
AT41
AT49
AU1
AU23
AU29
AU3
AU36
AU49
AU51
AV39
AV48
AW1
AW12
AW16

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

U19J
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198

VSS

AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41

C46
C50
C7
D13
D24
D3
D32
D39
D45
D49
E10
E16
E24
E28
E32
E47
F19
F36
F4
F40
F50
G1
G13
G16
G19
G24
G28
G29
G33
G42
G45
G48
G8
H24
H28
H4
H45
J11
J16
J2
J24
J28
J33
J35
J39

VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243

K12
K47
K8
L1
L17
L20
L24
L28
L3
L33
L49
M28
M42
M46
M49
M5
M50
M9
N11
N14
N17
N29
N32
N36
N39
N44
N49
N7
P19
P2
P23
P3
P50
R49
T39
T43
T47
U41
U45
U50
V2
V3

VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286

VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305

W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29
T29
T31
T33
R28

VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313

AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50

VSS

www.kythuatvitinh.com
B

CRESTLINE_1p0

DELL CONFIDENTIAL/PROPRIETARY

CRESTLINE_1p0

Title
Crestline (VSS)

Size

Document Number
M-08

Date:

Monday, March 05, 2007

Rev
0.1
Sheet
1

10

of

51

R282
0_NC
2

R265
0_NC

ICH8M Internal VR Enable Strap


(Internal VR for VccSus1.05, VccSus1.5, VccCL1.5)

+RTC_CELL

ICH_INTVRMEN

ICH_LAN100_SLP

C369
15P/50V

R283
332K/F

ICH_INTVRMEN

1
2

32.768KHZ

+RTC_CELL

R272
332K/F

ICH_RTCX2

R251 0
4 1

2
C378
15P/50V

+RTC_CELL

10M
1

W1
ICH_RTCX1

R259
2

32.768KHZ

ICH8M LAN100 SLP Strap


(Internal VR for VccLAN1.05 and VccCL1.05)

Low = Internal VR Disabled


High = Internal VR Enabled(Default)

ICH_LAN100_SLP

Low = Internal VR Disabled


High = Internal VR Enabled(Default)
+1.05V_VCCP

C46
27P/50V_NC

GLAN_CLK

B24

GLAN_CLK

LAN_RSTSYNC

D22

LAN_RSTSYNC

C21
B21
C22

LAN_RXD0
LAN_RXD1
LAN_RXD2

D21
E20
C20

LAN_TXD0
LAN_TXD1
LAN_TXD2

ACZ_BIT_CLK
T73
T75
T16
T70
T72
T74

23
C47
27P/50V_NC

LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2

PAD
PAD
PAD
PAD
PAD
PAD

G9
E6

LPC_LDRQ0#
LPC_LDRQ1#

AF13
AG26

SIO_A20GATE

DPRSTP#
DPSLP#

AF26
AE26

H_DPRSTP#
H_DPSLP#

FERR#

AD24

H_FERR#

CPUPWRGD/GPIO49

AG29

IGNNE#

AF27

H_IGNNE# <3>

INIT#
INTR
RCIN#

AE24
AC20
AH14

H_INIT# <3>
H_INTR <3>
SIO_RCIN# <28>

NMI
SMI#

AD23
AG28

STPCLK#

AA24

THRMTRIP#

AE27

TP8

AA23

LPC_LFRAME# <28>
PAD
PAD

H_DPRSTP#
H_DPSLP#
H_FERR#

T68
T63

C4

LDRQ0#
LDRQ1#/GPIO23
A20GATE
A20M#

R264
56_NC

R276
56

SIO_A20GATE <28>
H_A20M# <3>
+3.3V_RUN

H_DPRSTP# <3,6,45>
H_DPSLP# <3>

H_FERR# <3>

R256
10K

H_PWRGOOD <3>

R248
10K

+1.5V_PCIE_ICH

R306 24.9/F
1
2 GLAN_COMP

ACZ_SDOUT

ACZ_BIT_CLK
ACZ_SYNC

Place all series terms close to ICH8 except for SDIN input
lines,which should be close to source.Placement of R23, R228,
R230 & R236 should equal distance to the T split trace point as
R24, R229, R231 & R237 respective. Basically,keep the same
distance from T for all series termination resistors.

<32> ICH_AZ_CODEC_SDIN0
<26> ICH_AZ_MDC_SDIN1
T8 PAD
T48 PAD

ACZ_SDOUT

<23> SATA_TX0<23> SATA_TX0+


<23> SATA_TX2<23> SATA_TX2+

C361
C360
C362
C363

1 3900P/25V
1 3900P/25V

2
2

1 3900P/25V
1 3900P/25V

2
2

SATA_TX0-_C
SATA_TX0+_C
<23> SATA_RX0<23> SATA_RX0+

SATA_TX2-_C
SATA_TX2+_C

Distance between the ICH-8 M and cap on the "P"


signal should be identical distance between the
ICH-6 M and cap on the "N" signal for same pair.

This circuit is
only needed if the
platform has the
SNIFFER.

<23> SATA_RX2<23> SATA_RX2+

Place within 500mils


of ICH8 ball

<29,37> LED_MASK#

HDA_BIT_CLK
HDA_SYNC

AE14

HDA_RST#

AJ17
AH17
AH15
AD13

HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3

AE13

HDA_SDOUT

HDA_DOCK_EN#/GPIO33
HDA_DOCK_RST#/GPIO34

AF10

SATALED#

SATA_TX0-_C
SATA_TX0+_C

AF6
AF5
AH5
AH6

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

AG3
AG4
AJ4
AJ3

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

AF2
AF1
AE4
AE3

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

AB7
AC6

SATA_CLKN
SATA_CLKP

AG1
AG2

SATARBIAS#
SATARBIAS

SATA_TX2-_C
SATA_TX2+_C

<17> CLK_PCIE_SATA#
<17> CLK_PCIE_SATA

R263
10K

GLAN_COMPI
GLAN_COMPO

AJ16
AJ15

SATA_ACT#_R

9/20 Move from SATA port 1

+3.3V_RUN

D25
C25

SPEAKER_DET# AE10
RTC_BAT_DET# AG14

<32> SPEAKER_DET#
<30> RTC_BAT_DET#

GLAN_DOCK#/GPIO13

R250 24.9/F
2
1 SATABIAS

SIO_A20GATE
SIO_RCIN#

H_NMI <3>
H_SMI# <3>

+1.05V_VCCP

H_STPCLK# <3>

THERMTRIP#_ICH

PAD

IDE_DD[0..15]

DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15

V1
U2
V3
T1
V4
T5
AB2
T6
T3
R2
T4
V6
V5
U1
V2
U6

IDE_DD0
IDE_DD1
IDE_DD2
IDE_DD3
IDE_DD4
IDE_DD5
IDE_DD6
IDE_DD7
IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15

DA0
DA1
DA2

AA4
AA1
AB3

IDE_DA0
IDE_DA1
IDE_DA2

DCS1#
DCS3#

Y6
Y5

IDE_DCS1#
IDE_DCS3#

DIOR#
DIOW#
DDACK#
IDEIRQ
IORDY
DDREQ

W4
W3
Y2
Y3
Y1
W5

ICH8M REV 1.0

R268
56

T61

IDE_DD[0..15]

<23>

THERMTRIP#_ICH

IDE_DA0 <23>
IDE_DA1 <23>
IDE_DA2 <23>
IDE_DCS1# <23>
IDE_DCS3# <23>
IDE_DIOR# <23>
IDE_DIOW# <23>
IDE_DDACK# <23>
IDE_IRQ <23>
IDE_DIORDY <23>
IDE_DDREQ <23>

AJ0QN230T00

SIO_RCIN#

ACZ_RST#

AH21

PAD

T5

ACZ_SYNC

CPU

33
33
33
33
33
33

IDE

2
2
2
2
2
2

IHDA

1
1
1
1
1
1

SATA

R228
R229
R230
R231
R236
R237

ICH_AZ_MDC_SYNC
ICH_AZ_CODEC_SYNC
ICH_AZ_MDC_RST#
ICH_AZ_CODEC_RST#
ICH_AZ_MDC_SDOUT
ICH_AZ_CODEC_SDOUT

ACZ_RST#

FWH4/LFRAME#

R257
56_NC

INTVRMEN
LAN100_SLP

<28>
<28>
<28>
<28>

INTRUDER#

ICH_INTVRMEN AF25
ICH_LAN100_SLP AD21

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

www.kythuatvitinh.com
1

<26>
<32>
<26>
<32>
<26>
<32>

1
1

<26> ICH_AZ_MDC_BITCLK
<32> ICH_AZ_CODEC_BITCLK
2

2 33
2 10

ICH_INTRUDER# AD22

E5
F5
G8
F6

T76 PAD
R23
R24

RTCRST#

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

Reserved for
Intel Nineveh
design.

RTCX1
RTCX2

AF23

C359
1U/10V

AG25
AF24

ICH_RTCRST#

RTC
LPC

ICH_RTCRST#
ICH_INTRUDER#

U8A
ICH_RTCX1
ICH_RTCX2

LAN / GLAN

R238
20K

R269
1M

+3.3V_RUN

Q29
2N7002W-7-F

+3.3V_RUN

SATA_ACT#_R

ICH RSVD

R244 2
R495 2

R235
1K_NC

XOR Chain Entrance Strap

R278 0_NC
1
2

1 100K RTC_BAT_DET#
1 100K SPEAKER_DET#

RSVD

Enter XOR Chain

Normal Operation (Default)

Set PCIE port config bit 1

ACZ_SDOUT
ICH_RSVD

DELL CONFIDENTIAL/PROPRIETARY

<13>

R22
1K_NC

Title
ICH8-M (CPU,IDE,SATA,LPC,AC97,LAN)

1
1

HDA SDOUT Description


1

<37> SATA_ACT#

Size

Document Number
M-08

Date:

Tuesday, March 06, 2007


7

Rev
0.1
Sheet

of

11
8

51

1
1

2
2

0.1U/10V
0.1U/10V

PCIE_TXN1_C
PCIE_TXP1_C

P27
P26
N29
N28

PERN1
PERP1
PETN1
PETP1

PCIE_TXN2_C
PCIE_TXP2_C

M27
M26
L29
L28

PERN2
PERP2
PETN2
PETP2

PCIE_TXN3_C
PCIE_TXP3_C

K27
K26
J29
J28

PERN3
PERP3
PETN3
PETP3

PCIE_TXN4_C
PCIE_TXP4_C

H27
H26
G29
G28

PERN4
PERP4
PETN4
PETP4

F27
F26
E29
E28

PERN5
PERP5
PETN5
PETP5

D27
D26
C29
C28

PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP

ICH_EC_SPI_CLK_R
ICH_SPI_CS#
ICH_SPI_CS1#_R

C23
B23
E22

SPI_CLK
SPI_CS0#
SPI_CS1#

ICH_EC_SPI_DO_R

D23
F21

SPI_MOSI
SPI_MISO

<25> PCIE_RX1<25> PCIE_RX1+

PCIE_TXN1_C
PCIE_TXP1_C

WWAN
C101
C106

<24> PCIE_TX2<24> PCIE_TX2+

C114
C116

<24> PCIE_TX3<24> PCIE_TX3+

PCIE_TXN2_C
PCIE_TXP2_C

1
1

2
2

0.1U/10V
0.1U/10V

1
1

2
2

0.1U/10V
0.1U/10V

PCIE_TXN3_C
PCIE_TXP3_C

2
2

0.1U/10V
0.1U/10V

PCIE_TXN4_C
PCIE_TXP4_C

<24> PCIE_RX2<24> PCIE_RX2+

WLAN
<24> PCIE_RX3<24> PCIE_RX3+

C127
C120

<26> PCIE_TX4<26> PCIE_TX4+

1
1

WPAN
<26> PCIE_RX4<26> PCIE_RX4+

Non-iAMT

Express Card

+3.3V_SUS
RP27

OC7#
OC9#
OC5#
OC6#

6
7
8
9
10

+3.3V_SUS

5
4
3
2
1

USB_OC0_1#
USB_OC2_3#
OC4#
USB_OC8#

10P8R-10K
R313 1

<28> ICH_EC_SPI_CLK

Layout Note:
Place R313,R311 and R327
within 500 mils from ICH.

2 15

R311 1

<28> ICH_EC_SPI_DO
<28> ICH_EC_SPI_DIN

2 15

USB_OC0_1#

<27> USB_OC0_1#
+3.3V_ALW

U11
R328
1

<30> SPI_CS0#

R327
15

15_NC
2 4

USB_OC2_3#

<27> USB_OC2_3#

OC4#
OC5#
OC6#
OC7#
USB_OC8#
OC9#

ICH_SPI_CS#

SIO_SPI_CS# <28>

<27> USB_OC8#

AJ19
AG16
AG15
AE15
AF15
AG17
AD12
AJ18
AD14
AH18

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP

V27
V26
U29
U28

DMI_MTX_IRX_N0
DMI_MTX_IRX_P0
DMI_MRX_ITX_N0
DMI_MRX_ITX_P0

<6>
<6>
<6>
<6>

DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP

Y27
Y26
W29
W28

DMI_MTX_IRX_N1
DMI_MTX_IRX_P1
DMI_MRX_ITX_N1
DMI_MRX_ITX_P1

<6>
<6>
<6>
<6>

DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP

AB26
AB25
AA29
AA28

DMI_MTX_IRX_N2
DMI_MTX_IRX_P2
DMI_MRX_ITX_N2
DMI_MRX_ITX_P2

<6>
<6>
<6>
<6>

DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP

AD27
AD26
AC29
AC28

DMI_MTX_IRX_N3
DMI_MTX_IRX_P3
DMI_MRX_ITX_N3
DMI_MRX_ITX_P3

<6>
<6>
<6>
<6>

DMI_CLKN
DMI_CLKP

T26
T25

CLK_PCIE_ICH# <17>
CLK_PCIE_ICH <17>

DMI_ZCOMP
DMI_IRCOMP

Y23
Y24

PCI-Express
Direct Media Interface

C90
C97

U8D

Place TX DC blocking caps close ICH8.


<25> PCIE_TX1<25> PCIE_TX1+

SPI

OC0#
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
OC8#
OC9#

USB

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P

G3
G2
H5
H4
H2
H1
J3
J2
K5
K4
K2
K1
L3
L2
M5
M4
M2
M1
N3
N2

USBRBIAS#
USBRBIAS

F2
F3

R281
2

DMI_COMP

24.9/F
1

ICH_USBP0ICH_USBP0+
ICH_USBP1ICH_USBP1+
ICH_USBP2ICH_USBP2+
ICH_USBP3ICH_USBP3+
ICH_USBP4ICH_USBP4+
ICH_USBP5ICH_USBP5+
ICH_USBP6ICH_USBP6+
ICH_USBP7ICH_USBP7+
ICH_USBP8ICH_USBP8+
ICH_USBP9ICH_USBP9+

Place within 500mils of ICH8

+1.5V_PCIE_ICH
<27>
<27>
<27>
<27>
<27>
<27>
<27>
<27>
<24>
<24>
<33>
<33>
<26>
<26>
<37>
<37>
<27>
<27>
<25>
<25>

USB[1B]
PCI Pullups

USB[1A]

+3.3V_RUN

6
7
8
9
10

+3.3V_RUN

PCI_SERR#
6
SB_WLAN_PCIE_RST# 7
PCI_TRDY#
8
SB_MCARD3_PCIE_RST#9
10

USB[2A]
3rd MINI CARD
CAMERA

5
4
3
2
1
10P8R-8.2K
RP34

Express Card
BT
USB[3A]
WWAN USB

+3.3V_RUN

RP35

USB[2B]

PCI_STOP#
PCI_FRAME#
PCI_REQ1#
+3.3V_RUN

5
4
3
2
1

PCI_PIRQD#
SB_NB_PCIE_RST#

PCI_DEVSEL#

www.kythuatvitinh.com
7SH08_NC

10P8R-8.2K
RP31

USBRBIAS

PCI_PERR#
PCI_IRDY#
PCI_PIRQA#
PCI_REQ0#

Short F2 and F3 at the package


and keep length to less than
500mils. Trace Impedance
should be 60ohms +/- 15%.

Boot BIOS Strap

R304
1K

R292
1K_NC

GNT0#

SPI_CS1#

LPC

11

No stuff

No stuff

PCI

10

No stuff

Stuff

SPI

01

Stuff

No stuff

REQ0

LOM

REQ1

1394/MediaCard

<35> PCI_PIRQB#
<20> PCI_PIRQC#
<20> PCI_PIRQD#

PCI_PIRQA# F9
PCI_PIRQB# B5
PCI_PIRQC# C5
PCI_PIRQD# A10

PIRQB

GNT1

PIRQC
PIRQD

Non-iAMT

+3.3V_SUS

C84

0.047U/10V

A4
D7
E18
C18
B19
F18
A11
C10

C/BE0#
C/BE1#
C/BE2#
C/BE3#

C17
E15
F16
E17

IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#

C8
D9
G6
D16
A7
B7
F10
C16
C9
A17

PLTRST#
PCICLK
PME#

AG24 PCI_PLTRST#
B10 CLK_PCI_ICH
G7

PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

F8
G11
F12
B3

SB_LOM_PCIE_RST#

<25>

PCI_IRDY#

SB_NB_PCIE_RST#

PCI_DEVSEL# <20,35>
PCI_PERR# <20,35>
PCI_PLOCK#
PCI_SERR# <20,35>
PCI_STOP# <20,35>
PCI_TRDY# <20,35>
PCI_FRAME# <20,35>
CLK_PCI_ICH <17>
ICH_PME# <29>

SB_MCARD3_PCIE_RST#
SB_WLAN_PCIE_RST#
SB_NB_PCIE_RST#
PCIE_MCARD2_DET#

R307
1K_NC

U28

2
PCI_PLTRST#

PLTRST# <6,28>

PLTRST1# <24,25,26>

1
7SH32

A16 away override strap.


+3.3V_SUS

Low = A16 swap override enabled.


High = Default.

SB_NB_PCIE_RST#

C355
1
2
0.047U/10V

SB_MCARD3_PCIE_RST# R291
SB_WWAN_PCIE_RST# R314
SB_WLAN_PCIE_RST# R300
SB_LOM_PCIE_RST#
R324
SB_NB_PCIE_RST#
R302

2
2
2
2
2

1
1
1
1
1

20K_NC
20K
20K_NC
20K
20K_NC

CLK_PCI_ICH

U27

2
PCI_PLTRST#

R310
10

7SH32

C417
9P/50V

SB_MCARD3_PCIE_RST# <24>
SB_WLAN_PCIE_RST# <24>
SB_NB_PCIE_RST# <6>
PCIE_MCARD2_DET# <25>

Reserved for EMI.


Place resister and cap
close to ICH.

35

C357
1
2
0.047U/10V

<20,35>
<20,35>
<20,35>
<20,35>

PCI_IRDY# <20,35>
PCI_PAR <20,35>

PCI_RST#_G
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

PCI_RST# <20,35>

+3.3V_SUS

SB_LOM_PCIE_RST#
PCI_C_BE0#
PCI_C_BE1#
PCI_C_BE2#
PCI_C_BE3#

1
7SH32

ICH8M REV 1.0


PCI_PIRQB: for LOM
PCI_PIRQC: for Media Card
PCI_PIRQD: for 1394

U10
4

PCI_RST#_G

BIOS should not enable the


internal GPIO pull up resistor.

Interrupt I/F
PIRQA#
PIRQB#
PIRQC#
PIRQD#

PCI_REQ0# <35>
PCI_GNT0# <35>
PCI_REQ1# <20>
PCI_GNT1# <20>
SB_WWAN_PCIE_RST#

PCI

Add Buffers as needed for


Loading and fanout concerns.

PCI_REQ0#
PCI_GNT0#
PCI_REQ1#
PCI_GNT1#
SB_WWAN_PCIE_RST#

REQ0#
GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55

35

2 1

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

PCI_PIRQC#
PCI_PLOCK#
PCI_PIRQB#

D20
E19
D19
A20
D17
A21
A19
C19
A18
B16
A12
E16
A14
G16
A15
B6
C11
A9
D11
B12
C12
D10
C7
F13
E11
E13
E12
D8
A6
E8
D6
A3

GNT0

U8B
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

+3.3V_RUN

5
4
3
2
1

10P8R-8.2K

+3.3V_RUN

<20,35> PCI_AD[0..31]

R301
22.6/F

6
7
8
9
10

0.1U/10V
0.1U/10V
0.1U/10V
0.1U/10V
0.1U/10V
0.1U/10V
0.1U/10V
0.1U/10V

2
2
2
2
2
2
2
2

1
1
1
1
1
1
1
1

C876
C871
C872
C873
C878
C874
C875
C877

ICH_SPI_CS1#_R
PCI_GNT0#

OC4#
OC5#
OC6#
OC7#
OC9#
USB_OC8#
USB_OC0_1#
USB_OC2_3#

18

ICH8M REV 1.0

WWAN Noise - ICH improvements

R93
1

DELL CONFIDENTIAL/PROPRIETARY
Title
ICH8-M (USB,DMI,PCIE,PCI)

Size

Document Number
M-08

Date:

Tuesday, March 06, 2007


7

Rev
0.1
Sheet

of

12
8

51

GG request

Place these close to ICH7.

R247
R273
R271
R255
R252
R261

+3.3V_SUS

9
2
2
2
2
2
2

1
1
1
1
1
1

Non-iAMT

10K_NC ICH_CL_RST1#
10K AMT_SMBCLK
10K AMT_SMBDAT
10K ICH_RI#
10K SIO_EXT_SCI#
1K ICH_PCIE_WAKE#

CLK_ICH_48M

10/1 TDC request

+3.3V_SUS

AMT_SMBDAT
AMT_SMBCLK

+3.3V_RUN

Non-iAMT
R262
8.2K

RI#

F4
AD15

SUS_STAT#/LPCPD#
SYS_RESET#

AG12

BMBUSY#/GPIO0

AG22

SMBALERT#/GPIO11

CLKRUN#

AE20
AG18

STP_PCI#/GPIO15
STP_CPU#/GPIO25

CLKRUN#

AH11

CLKRUN#/GPIO32

ICH_PCIE_WAKE#
IRQ_SERIRQ
RSV_THRM#

AE17
AF12
AC13

WAKE#
SERIRQ
THRM#

AJ20

VRMPWRGD

LOM_SMB_ALERT#

<28> LOM_SMB_ALERT#
<17> H_STP_PCI#
<17> H_STP_CPU#

<20,28,35> CLKRUN#

<29> ICH_PCIE_WAKE#
<20,28> IRQ_SERIRQ
T56 PAD

AJ12
AJ10
AF11
AG11

CLK_ICH_14M
1

AF17

SATA0GP/GPIO21
SATA1GP/GPIO19
SATA2GP/GPIO36
SATA3GP/GPIO37

AG9
G5

CLK_ICH_14M
CLK_ICH_48M

SUSCLK

D3

ICH_SUSCLK

SLP_S3#
SLP_S4#
SLP_S5#

AG23
AF21
AD18

CLK14
CLK48

CLK_ICH_14M <17>
CLK_ICH_48M <17>
PAD

R254
10_NC

T71

1 2

15

ICH_RI#

<6> PM_BMBUSY#

R233
10_NC

SMBCLK
SMBDATA
LINKALERT#
SMLINK0
SMLINK1

RSVD_LPCPD#

T69 PAD
<3,29> ITP_DBRESET#
R234
8.2K

AJ26
AD19
AG21
AC17
AE19

SIO_SLP_S3# <28>
PAD T52
SIO_SLP_S5# <28>

S4_STATE#/GPIO26

AH27

SIO_S4_STATE#

PWROK

AE23

ICH_PWRGD
DPRSLPVR

DPRSLPVR/GPIO16

AJ14

BATLOW#

AE21

PWRBTN#

C2

LAN_RST#

AH20

ICH_LAN_RST#

AG27

ICH_RSMRST#

ICH_BATLOW#

PAD

+3.3V_RUN

ICH_SMBCLK
ICH_SMBDATA
ICH_CL_RST1#
AMT_SMBCLK
AMT_SMBDAT

Clocks SATA
GPIO

<24,25,26> ICH_SMBCLK
<24,25,26> ICH_SMBDATA
ICH_CL_RST1#
T60 PAD
T53 PAD

SMB

U8C

4P2R-2.2K

C412
4.7P/50V_NC

ICH_SMBDATA
ICH_SMBCLK

SYS
GPIO
Power MGT

2
4

RP28
1
3

R297
10_NC
1 2

1 0_NC
1 0_NC

ICH_SMBDATA R518 2
ICH_SMBCLK R519 2

C377
4.7P/50V_NC

T49

ICH_PWRGD <6,38>
DPRSLPVR <6,45>
R270
2

8.2K
1

+3.3V_SUS

ICH_PWRGD

SIO_PWRBTN# <28>

R260 2

1 10K

AJ22

T12 PAD

USB_IDE#

36

<24> USB_MCARD1_DET#

15

RSVD_GPIO6
T10 PAD
SIO_EXT_WAKE#
<29> SIO_EXT_WAKE#
SIO_EXT_SMI#
<28> SIO_EXT_SMI#
SIO_EXT_SCI#
14<28> SIO_EXT_SCI#
PCIE_MCARD1_DET#
<24> PCIE_MCARD1_DET#
USB_MCARD1_DET#
R547 1
2 4.7K
T81 PAD
35
USB_MCARD2_DET#
<25> USB_MCARD2_DET#
USB_MCARD3_DET#
<24> USB_MCARD3_DET#
<23> IDE_RST_MOD#
<17> SATA_CLKREQ#
PLTRST_DELAY#
<18> PLTRST_DELAY#
30<24> WPAN_RADIO_DIS_MINI#
CCD_VDD_ON
26 <33> CCD_VDD_ON
SPKR

<32> SPKR
<6> MCH_ICH_SYNC#

R241 2

1 0 MCH_ICH_SYNC#_R

AD9
AJ13
AJ21

<11> ICH_RSVD
1 100K_NC CCD_VDD_ON

R258 2

AJ8
AJ9
AH9
AE16
AC19
AG8
AH12
AE11
AG10
AH25
AD16
AG13
AF9
AJ11
AD10

TP7

TACH1/GPIO1
TACH2/GPIO6
TACH3/GPIO7
GPIO8
GPIO12
TACH0/GPIO17
GPIO18
GPIO20
SCLOCK/GPIO22
QRT_STATE0/GPIO27
QRT_STATE1/GPIO28
SATACLKREQ#/GPIO35
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48
SPKR
MCH_SYNC#
TP3

RSMRST#

CK_PWRGD

E1

CLPWROK

E3

ICH_RSMRST# <28>

CLK_PWRGD <17>

ICH_CL_PWROK

ICH_CL_PWROK

SLP_M#

AJ25

RSV_SIO_SLP_M#

CL_CLK0
CL_CLK1

F23
AE18

RSV_ICH_CL_CLK1

CL_CLK0 <6>
PAD
T58

CL_DATA0
CL_DATA1

F22
AF19

RSV_ICH_CL_DATA1

CL_DATA0 <6>
PAD
T4

CL_VREF0
CL_VREF1

D24
AH23

CL_RST#

AJ23

MEM_LED/GPIO24
ME_EC_ALERT/GPIO10
EC_ME_ALERT/GPIO14
WOL_EN/GPIO9

AJ27
AJ24
AF22
AG19

CL_VREF0
CL_VREF1

PAD

PAD

<6,28>

T9

Non-iAMT

DPRSLPVR

R232 1

2 100K

WOL_EN

R249 1

2 100K

ICH_RSMRST#

R21

1 10K

ICH_LAN_RST#

R246 2

1 1M

ICH_CL_PWROK
PLTRST_DELAY#

R305 2
R511 2

1 1M
1 10K

PCIE_MCARD3_DET#
ME_EC_ALERT
WOL_EN
R227
2

53

9/26 Add PD 10K

T50

PCIE_MCARD3_DET# <24>
PAD
T11
PAD
T6
10/1 TDC
PAD
T55
8.2K
1

request

9
+3.3V_SUS
+3.3V_RUN

+3.3V_ALW

Non-iAMT
+3.3V_SUS

Low = Default.
High = No Reboot.

SPKR

Q8
1

MEM_SDATA <15>

C416
0.1U/10V

1
R299
453/F

C365
0.1U/10V_NC

R239
453/F_NC

<24,25,26> ICH_SMBDATA

No Reboot strap.

SPKR

1 2.2K_NC IMVP_PWRGD

CL_VREF1
1

RP16
4P2R-2.2K
1

CL_VREF0

These are for


backdrive issue.

R267
1K_NC
+3.3V_RUN

R240
3.24K/F_NC

15

LOM_SMB_ALERT#

2
4

1 10K

R296
3.24K/F

Non-iAMT

1
3

R510 2

+3.3V_RUN

SMbus address D2

SIO_EXT_SMI#
2

1 10K

+3.3V_RUN
R243 2

R84

ICH_CL_RST0# <6>

ICH8M REV 1.0

26

ICH_LAN_RST#

IMVP_PWRGD

<28,38,45> IMVP_PWRGD

MISC
GPIO
Controller Link

www.kythuatvitinh.com

Option to " Disable "


clkrun. Pulling it down
will keep the clks
running.

2N7002W-7-F
+3.3V_RUN
2

+3.3V_RUN
2
2
2
2
1

1
1
1
1
2

10K
10K_NC
10K
10K
100K

+3.3V_RUN

RSV_THRM#
MCH_ICH_SYNC#_R
IRQ_SERIRQ
RSVD_GPIO6
WPAN_RADIO_DIS_MINI#

<24,25,26> ICH_SMBCLK

Q6
1

MEM_SCLK <15>

R277
R245
R266
R274
R540

2N7002W-7-F

DELL CONFIDENTIAL/PROPRIETARY

R25
8.2K

30
1

USB_IDE#

Title
ICH8-M (PM,GPIO,SMB,CL)

9/20 Delete R258

Size

Document Number
M-08

Date:

Tuesday, March 06, 2007


7

Rev
0.1
Sheet

of

13
8

51

+RTC_CELL
2
1

+1.25V_RUN
C59
22U/10V

+1.05V_VCCP

+3.3V_RUN

+V_CPU_IO
1

C375
0.1U/10V

VCC1_5_A[15]
VCC1_5_A[16]
VCC1_5_A[17]

G12
G17
H7

VCC3_3[02]

AD2

VCC1_5_A[13]
VCC1_5_A[14]

AF29

C91
10U/6.3V

0_0603

AA5
AA6

VCC3_3[01]

C95
0.01U/25V

+1.5V_RUN

L18
R52
1uH_800MA
2
1+1.5V_DMIPLL_R 2

+1.5V_DMIPLL

VCC1_5_A[11]
VCC1_5_A[12]

+V_CPU_IO

1uH+-20%_800mA

AC10
AC9

V_CPU_IO[1]
V_CPU_IO[2]

AC23
AC24

2
10/0805

BAT54C

VCC1_5_A[06]
VCC1_5_A[07]
VCC1_5_A[08]
VCC1_5_A[09]
VCC1_5_A[10]

+VCC_DMI

3 1

C394
4.7U/10V

C392
0.1U/10V

C409
0.1U/10V

C381
0.1U/10V

C411
0.1U/10V

WWAN Noise - ICH improvements

+3.3V_RUN

Non-iAMT

VCCHDA

AC12

VCCSUSHDA

AD11

VCCSUS1_05[1]
VCCSUS1_05[2]

J6
AF20

TP_VCCSUS1.05_1
TP_VCCSUS1.05_2

VCCSUS1_5[1]

AC16

TP_VCCSUS1.5_1

VCCSUS1_5[2]

J7

TP_VCCSUS1.5_2

VCCSUS3_3[01]

C3

+VCCSUS3_3[0~6]

VCCSUS3_3[02]
VCCSUS3_3[03]
VCCSUS3_3[04]
VCCSUS3_3[05]
VCCSUS3_3[06]

AC18
AC21
AC22
AG20
AH28

VCCSUS3_3[07]
VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]

P6
P7
C1
N7
P1
P2
P3
P4
P5
R1
R3
R5
R6

+3.3V_SUS

C869
0.1U/10V

C868
0.1U/10V

C867
0.1U/10V

C397
0.1U/10V

C418
0.1U/10V

C415
0.1U/10V

18

A8
B15
B18
B4
B9
C15
D13
D5
E10
E7
F11

VCCP_CORE
IDE

VCC3_3[14]
VCC3_3[15]
VCC3_3[16]
VCC3_3[17]
VCC3_3[18]
VCC3_3[19]
VCC3_3[20]
VCC3_3[21]
VCC3_3[22]
VCC3_3[23]
VCC3_3[24]

C870
0.1U/10V

+3.3V_RUN

VCCGLANPLL

C146
4.7U/6.3V

+1.5V_PCIE_ICH

A26
A27
B26
B27
B28

VCCGLAN1_5[1]
VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]
VCCGLAN1_5[5]

B25

VCCGLAN3_3

+3.3V_RUN
2

1
2

1
2

C387
0.022U/16V

WWAN Noise - ICH improvements 18


1

C864
0.1U/10V

C865
0.1U/10V

C405
0.1U/10V

C748
0.1U/10V

C866
0.1U/10V

+VCCSUS3_3[7~19]

VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]

K7
L1
L13
L15
L26
L27
L4
L5
M12
M13
M14
M15
M16
M17
M23
M28
M29
M3
N1
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
N4
N5
N6
P12
P13
P14
P15
P16
P17
P23
P28
P29
R11
R12
R13
R14
R15
R16
R17
R18
R28
R4
T12
T13
T14
T15
T16
T17
T2
U12
U13
U14
U15
U16
U17
U23
U26
U27
U3
U5
V13
V15
V28
V29
W2
W26
W27
Y28
Y29
Y4
AB4
AB23
AB5
AB6
AD5
U4
W24

VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS_NCTF[05]
VSS_NCTF[06]
VSS_NCTF[07]
VSS_NCTF[08]
VSS_NCTF[09]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]

A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29

VCCCL1_05

G22

TP_VCCCL1.05

VCCCL1_5

A22

+VCCCL1_5

VCCCL3_3[1]
VCCCL3_3[2]

F20
G21

+3.3V_RUN

C419
0.1U/10V_NC

C422
1U/10V_NC

Title
ICH8-M (POWER,GND)

Non-iAMT
4

DELL CONFIDENTIAL/PROPRIETARY

PAD T65

Size

Document Number
M-08

Date:

Tuesday, March 06, 2007

ICH8M REV 1.0

ICH8M REV 1.0

VCCLAN3_3[1]
VCCLAN3_3[2]

A24

GLAN POWER

F19
G20

C128
0.022U/16V

+VCCGLANPLL

VCCLAN1_05[1]
VCCLAN1_05[2]

+3.3V_SUS

Non-iAMT

PAD T64

VCC1_5_A[25]

+3.3V_RUN
C413
0.1U/10V

W23
TP_VCCSUSLAN1 F17
TP_VCCSUSLAN2 G18

C401
0.1U/10V

PAD T59

T67 PAD
T66 PAD

VCC1_5_A[20]
VCC1_5_A[21]
VCC1_5_A[22]
VCC1_5_A[23]
VCC1_5_A[24]

C376
0.1U/10V

Non-iAMT

F1
L6
L7
M6
M7

PAD T62
PAD T7

C398
0.1U/10V

VCCUSBPLL

C414
0.1U/10V

+1.5V_RUN

AA3
U7
V7
W1
W6
W7
Y7

C390
0.1U/10V

2
1

Place C929
close to A24.

VCC1_5_A[18]
VCC1_5_A[19]

D1

USB CORE

+1.5V_RUN

Non-iAMT

C119
0.1U/10V

VCC3_3[07]
VCC3_3[08]
VCC3_3[09]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]

AC7
AD7

+1.5V_RUN

+VCCGLANPLL

AC8
AD8
AE8
AF8

C389
1U/10V

VCCPSUS

C57
10U/6.3V

C368
1U/10V

VCC3_3[03]
VCC3_3[04]
VCC3_3[05]
VCC3_3[06]

+1.5V_RUN

+VCCSATPLL

AC1
AC2
AC3
AC4
AC5

AE28
AE29

R288

1
2

C386
1U/10V

10uH+-20%_100mA

VCC1_5_A[01]
VCC1_5_A[02]
VCC1_5_A[03]
VCC1_5_A[04]
VCC1_5_A[05]

VCCPUSB

1
1 2

+1.5V_RUN

+VCCSATPLL_L
L11
10uH/100MA

AE7
AF7
AG7
AH7
AJ7

PCI

C406
2.2U/10V

+VCCSATPLL

R29
0

VCCSATAPLL

R29

VCC_DMI[1]
VCC_DMI[2]

+1.5V_RUN
D25
1

2
C382
22U/10V

C404
22U/10V

+1.5V_RUN

AJ6

VCCDMIPLL

+1.05V_VCCP

VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]

www.kythuatvitinh.com

C63
220U/4V

1
+

U8E

+1.5V_PCIE_ICH

A13
B13
C13
C14
D14
E14
F14
G14
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

C402
0.1U/10V

L31
BLM21PG331SN1D

FB_330ohm+-25%_100mHz_
1.5A_0.09 ohm DC

VCCA3GP

+1.5V_RUN

VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]
VCC1_05[27]
VCC1_05[28]

2
1

C104
0.1U/10V

VCC1_5_B[01]
VCC1_5_B[02]
VCC1_5_B[03]
VCC1_5_B[04]
VCC1_5_B[05]
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]

C407
0.1U/10V

+ICH_V5REF_SUS

SDMK0340L-7-F

AA25
AA26
AA27
AB27
AB28
AB29
D28
D29
E25
E26
E27
F24
F25
G24
H23
H24
J23
J24
K24
K25
L23
L24
L25
M24
M25
N23
N24
N25
P24
P25
R24
R25
R26
R27
T23
T24
T27
T28
T29
U24
U25
V23
V24
V25
W25
Y25

CORE

1
D7

V5REF_SUS

ATX

10
2

+3.3V_SUS

V5REF[1]
V5REF[2]

ARX

+5V_SUS

R56
1

G4

C144
0.1U/10V

Non-iAMT

VCCRTC

SDMK0340L-7-F

A16
T7

+ICH_V5REF_RUN

U8F
AD25

D9
1

C380
0.1U/10V

C384
0.1U/10V

A23
A5
AA2
AA7
A25
AB1
AB24
AC11
AC14
AC25
AC26
AC27
AD17
AD20
AD28
AD29
AD3
AD4
AD6
AE1
AE12
AE2
AE22
AD1
AE25
AE5
AE6
AE9
AF14
AF16
AF18
AF3
AF4
AG5
AG6
AH10
AH13
AH16
AH19
AH2
AF28
AH22
AH24
AH26
AH3
AH4
AH8
AJ5
B11
B14
B17
B2
B20
B22
B8
C24
C26
C27
C6
D12
D15
D18
D2
D4
E21
E24
E4
E9
F15
E23
F28
F29
F7
G1
E2
G10
G13
G19
G23
G25
G26
G27
H25
H28
H29
H3
H6
J1
J25
J26
J27
J4
J5
K23
K28
K29
K3
K6

1
C374
1U/10V

2 100_0402

+3.3V_RUN

+1.05V_VCCP

2
R91 1

+5V_RUN

Rev
0.1
Sheet

of

14
8

51

DDR_A_D26
DDR_A_D27
<6,16> DDR_CKE0_DIMMA

DDR_B_DQS#1
DDR_B_DQS1

M_CLK_DDR0 <6>
M_CLK_DDR#0 <6>
DDR_A_D10
DDR_A_D11

DDR_B_D15
DDR_B_D11

DDR_A_D20
DDR_A_D21

DDR_B_D16
DDR_B_D21

PM_EXTTS#0
DDR_A_DM2

DDR_B_DQS#2
DDR_B_DQS2

PM_EXTTS#0 <6>

DDR_A_D22
DDR_A_D18

DDR_B_D18
DDR_B_D19

DDR_A_D28
DDR_A_D29

DDR_B_D25
DDR_B_D24

DDR_A_DQS#3
DDR_A_DQS3

DDR_B_DM3

DDR_A_D30
DDR_A_D31

DDR_B_D30
DDR_B_D31

DDR_CKE1_DIMMA

<6,16>

<6,16> DDR_CKE2_DIMMB

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

VSS18
DQ16
DQ17
VSS1
DQS#2
DQS2
VSS19
DQ18
DQ19
VSS22
DQ24
DQ25
VSS23
DM3
NC4
VSS9
DQ26
DQ27
VSS4
CKE0
VDD7
NC1
A16_BA2
VDD9
A12
A9
A8
VDD5
A5
A3
A1
VDD10
A10/AP
BA0
WE#
VDD2
CAS#
S1#
VDD3
ODT1
VSS11
DQ32
DQ33
VSS26
DQS#4
DQS4
VSS2
DQ34
DQ35
VSS27
DQ40
DQ41
VSS29
DM5
VSS51
DQ42
DQ43
VSS40
DQ48
DQ49
VSS52
NCTEST
VSS30
DQS#6
DQS6
VSS31
DQ50
DQ51
VSS33
DQ56
DQ57
VSS3
DM7
VSS34
DQ58
DQ59
VSS14
SDA
SCL
VDD(SPD)

VSS20
DQ20
DQ21
VSS6
NC3
DM2
VSS21
DQ22
DQ23
VSS24
DQ28
DQ29
VSS25
DQS#3
DQS3
VSS10
DQ30
DQ31
VSS8
CKE1
VDD8
A15
A14
VDD11
A11
A7
A6
VDD4
A4
A2
A0
VDD12
BA1
RAS#
S0#
VDD1
ODT0
A13
VDD6
NC2
VSS12
DQ36
DQ37
VSS28
DM4
VSS42
DQ38
DQ39
VSS55
DQ44
DQ45
VSS43
DQS#5
DQS5
VSS56
DQ46
DQ47
VSS44
DQ52
DQ53
VSS57
CK1
CK1#
VSS45
DM6
VSS32
DQ54
DQ55
VSS35
DQ60
DQ61
VSS7
DQS#7
DQS7
VSS36
DQ62
DQ63
VSS13
SA0
SA1

DDR_B_D13
DDR_B_D12

C274
0.1U/10V

C275
2.2U/6.3V

DDR_B_DM1
M_CLK_DDR2 <6>
M_CLK_DDR#2 <6>
DDR_B_D10
DDR_B_D14

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_B_D20
DDR_B_D17
PM_EXTTS#1
DDR_B_DM2

PM_EXTTS#1 <6>

DDR_B_D22
DDR_B_D23

+1.8V_SUS

DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3

C270
2.2U/6.3V

Place these Caps near So-Dimm1.

C269
2.2U/6.3V

C279
2.2U/6.3V

C280
2.2U/6.3V

DDR_B_D9
DDR_B_D8

DDR_A_DM1

DDR_B_D6
DDR_B_D7

DDR_B_D2
DDR_B_D3

V_DDR_MCH_REF

DDR_B_DM0

DDR_B_DQS#0
DDR_B_DQS0
C276
2.2U/6.3V

DDR_B_D0
DDR_B_D4

C281
2.2U/6.3V
B

DDR_B_D26
DDR_B_D27
DDR_CKE3_DIMMB

<6,16>

+1.8V_SUS

www.kythuatvitinh.com
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D54
DDR_A_D51
DDR_A_D56
DDR_A_D60
DDR_A_DM7
DDR_A_D59
DDR_A_D63

<13> MEM_SDATA
<13> MEM_SCLK
+3.3V_RUN

MEM_SDATA
MEM_SCLK

FOX_AS0A426-N2RN-7F

SMbus address A0

Non-iAMT

DDR_A_D43
DDR_A_D47

C580
2.2U/6.3V

C579
0.1U/10V

DDR_B_DM5
DDR_B_D47
DDR_B_D42

DDR_A_D52
DDR_A_D53

DDR_B_D55
DDR_B_D49
M_CLK_DDR1 <6>
M_CLK_DDR#1 <6>

DDR_A_DM6

DDR_B_DQS#6
DDR_B_DQS6

DDR_A_D50
DDR_A_D55

DDR_B_D51
DDR_B_D53

DDR_A_D61
DDR_A_D57

DDR_B_D61
DDR_B_D60

DDR_A_DQS#7
DDR_A_DQS7

DDR_B_DM7

DDR_A_D58
DDR_A_D62

DDR_B_D59
DDR_B_D62

Non-iAMT

MEM_SDATA
MEM_SCLK
+3.3V_RUN
R169
10K

FOX_ AS0A426-N2SN-7F
R170
10K

SMbus address A4

1
2

1
2

1
2

1
2

1
2

Place these Caps near So-Dimm1.

DDR_B_DM4

C271
0.1U/10V

C278
0.1U/10V

C272
0.1U/10V

1
2

DDR_B_D37
DDR_B_D33

C273
0.1U/10V

+1.8V_SUS

Place these Caps near So-Dimm2.

C574
0.1U/10V

C584
0.1U/10V

1
C578
0.1U/10V

DDR_B_DQS#5
DDR_B_DQS5

DDR_B_D45
DDR_B_D44

DDR_B_D38
DDR_B_D35
C577
0.1U/10V

DDR_B_D43
DDR_B_D46
DDR_B_D52
DDR_B_D48
M_CLK_DDR3 <6>
M_CLK_DDR#3 <6>

+3.3V_RUN

DDR_B_DM6
DDR_B_D50
DDR_B_D54
DDR_B_D57
DDR_B_D56
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D58
DDR_B_D63
R449 2
R448
10K

CLOCK 2,3
CKE 2,3

C576
2.2U/6.3V

M_ODT2 <6,16>

DDR_B_D41
DDR_B_D40

M_ODT2
DDR_B_MA13

Non-iAMT

DDR_B_BS1 <7,16>
+1.8V_SUS
DDR_B_RAS# <7,16>
DDR_CS2_DIMMB# <6,16>

DDR_A_DQS#5
DDR_A_DQS5

DDR_B_D34
DDR_B_D39

C587
2.2U/6.3V

DDR_B_BS1
DDR_B_RAS#

+3.3V_RUN

DDR_A_D40
DDR_A_D41

CLOCK 0,1
CKE 0,1

DDR_B_DQS#4
DDR_B_DQS4

DDR_A_D34
DDR_A_D39

C586
2.2U/6.3V

Non-iAMT
1

DDR_A_D48
DDR_A_D49

DDR_A_DM4

C575
2.2U/6.3V

C264
2.2U/6.3V

DDR_A_D42
DDR_A_D46

DDR_B_D32
DDR_B_D36

C588
2.2U/6.3V

DDR_A_DM5

M_ODT3

DDR_A_D36
DDR_A_D37

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_A_D44
DDR_A_D45

DDR_B_CAS#

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6

C268
0.1U/10V

Non-iAMT

+3.3V_RUN
1 10K

DELL CONFIDENTIAL/PROPRIETARY

DDR_A_D35
DDR_A_D38

<6,16> M_ODT3

DDR_B_MA10
DDR_B_BS0
DDR_B_WE#

Place these Caps near So-Dimm2.

DDR_B_MA14

DDR_A_DQS#4
DDR_A_DQS4

<7,16> DDR_B_CAS#
<6,16> DDR_CS3_DIMMB#

DDR_A_D32
DDR_A_D33

M_ODT0 <6,16>

M_ODT1

M_ODT0
DDR_A_MA13

DDR_A_BS1 <7,16>
DDR_A_RAS# <7,16>
<7,16> DDR_B_BS0
DDR_CS0_DIMMA# <6,16>
<7,16> DDR_B_WE#

DDR_A_CAS#

DDR_A_BS1
DDR_A_RAS#

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

<7,16> DDR_A_CAS#
<6,16> DDR_CS1_DIMMA#

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_MA10
DDR_A_BS0
DDR_A_WE#

<7,16> DDR_A_BS0
<7,16> DDR_A_WE#

DDR_B_MA12
DDR_B_MA9
DDR_B_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_B_BS2

<7,16> DDR_B_BS2

DDR_A_MA11
DDR_A_MA7
DDR_A_MA6

DDR_A_MA12
DDR_A_MA9
DDR_A_MA8

DDR_A_MA14

DDR_A_BS2

<7,16> DDR_A_BS2

<6,16> M_ODT1

DDR_A_D13
DDR_A_D9

C277
0.1U/10V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

DDR_A_DM3

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_A_D6
DDR_A_D7

VSS46
DQ4
DQ5
VSS15
DM0
VSS5
DQ6
DQ7
VSS16
DQ12
DQ13
VSS17
DM1
VSS53
CK0
CK0#
VSS41
DQ14
DQ15
VSS54

DDR_A_D24
DDR_A_D25

VSS20
DQ20
DQ21
VSS6
NC3
DM2
VSS21
DQ22
DQ23
VSS24
DQ28
DQ29
VSS25
DQS#3
DQS3
VSS10
DQ30
DQ31
VSS8
CKE1
VDD8
A15
A14
VDD11
A11
A7
A6
VDD4
A4
A2
A0
VDD12
BA1
RAS#
S0#
VDD1
ODT0
A13
VDD6
NC2
VSS12
DQ36
DQ37
VSS28
DM4
VSS42
DQ38
DQ39
VSS55
DQ44
DQ45
VSS43
DQS#5
DQS5
VSS56
DQ46
DQ47
VSS44
DQ52
DQ53
VSS57
CK1
CK1#
VSS45
DM6
VSS32
DQ54
DQ55
VSS35
DQ60
DQ61
VSS7
DQS#7
DQS7
VSS36
DQ62
DQ63
VSS13
SA0
SA1

DDR_A_DM0

VREF
VSS47
DQ0
DQ1
VSS37
DQS#0
DQS0
VSS48
DQ2
DQ3
VSS38
DQ8
DQ9
VSS49
DQS#1
DQS1
VSS39
DQ10
DQ11
VSS50

DDR_A_D23
DDR_A_D19

VSS18
DQ16
DQ17
VSS1
DQS#2
DQS2
VSS19
DQ18
DQ19
VSS22
DQ24
DQ25
VSS23
DM3
NC4
VSS9
DQ26
DQ27
VSS4
CKE0
VDD7
NC1
A16_BA2
VDD9
A12
A9
A8
VDD5
A5
A3
A1
VDD10
A10/AP
BA0
WE#
VDD2
CAS#
S1#
VDD3
ODT1
VSS11
DQ32
DQ33
VSS26
DQS#4
DQS4
VSS2
DQ34
DQ35
VSS27
DQ40
DQ41
VSS29
DM5
VSS51
DQ42
DQ43
VSS40
DQ48
DQ49
VSS52
NCTEST
VSS30
DQS#6
DQS6
VSS31
DQ50
DQ51
VSS33
DQ56
DQ57
VSS3
DM7
VSS34
DQ58
DQ59
VSS14
SDA
SCL
VDD(SPD)

DDR_B_D1
DDR_B_D5

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

DDR_A_DQS#2
DDR_A_DQS2

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

JDIM2

V_DDR_MCH_REF

DDR_A_D17
DDR_A_D16

DDR_A_D1
DDR_A_D0

DDR_A_D15
DDR_A_D14

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

DDR_B_DM[0..7] <7>
DDR_B_D[0..63] <7>
DDR_B_DQS[0..7] <7>
DDR_B_DQS#[0..7] <7>
DDR_B_MA[0..14] <6,7,16>

BOT

DDR_A_DQS#1
DDR_A_DQS1

VSS46
DQ4
DQ5
VSS15
DM0
VSS5
DQ6
DQ7
VSS16
DQ12
DQ13
VSS17
DM1
VSS53
CK0
CK0#
VSS41
DQ14
DQ15
VSS54

+1.8V_SUS

V_DDR_MCH_REF

DDR_A_D8
DDR_A_D12

VREF
VSS47
DQ0
DQ1
VSS37
DQS#0
DQS0
VSS48
DQ2
DQ3
VSS38
DQ8
DQ9
VSS49
DQS#1
DQS1
VSS39
DQ10
DQ11
VSS50

DDR_A_D2
DDR_A_D3

JDIM1

+1.8V_SUS

DDR_A_DM[0..7] <7>
DDR_A_D[0..63] <7>
DDR_A_DQS[0..7] <7>
DDR_A_DQS#[0..7] <7>
DDR_A_MA[0..14] <6,7,16>

TOP
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

DDR_A_DQS#0
DDR_A_DQS0

+1.8V_SUS

V_DDR_MCH_REF

DDR_A_D4
DDR_A_D5

+1.8V_SUS

PC4800 DDR2 SDRAM


SO-DIMM (200P)

A is required to route to Top


SoDIMM for AMTto function.
Ch.A SODIMM needs to be
populated for Intel AMT support.

PC4800 DDR2 SDRAM


SO-DIMM (200P)

Title
DDR2 SO-DIMM (200P) X 2
Size

Document Number
M-08

Date:

Monday, March 05, 2007


7

Rev
0.1
Sheet

of

15
8

51

TOP
+0.9V_DDR_VTT

Layout note: Place 1 cap close to every 1 R-pack terminated to SMDDR_VTERM.

C258
0.1U/10V

2
C594
0.1U/10V

C259
0.1U/10V

2
C595
0.1U/10V

C261
0.1U/10V

2
C593
0.1U/10V

C286
0.1U/10V

2
C591
0.1U/10V

C263
0.1U/10V

2
C597
0.1U/10V

C266
0.1U/10V

2
C596
0.1U/10V

C260
0.1U/10V

2
1

C583
0.1U/10V

C262
0.1U/10V

C284
0.1U/10V

C582
0.1U/10V

C288
0.1U/10V

C592
0.1U/10V

C585
0.1U/10V

C581
0.1U/10V

C257
0.1U/10V

BOT

+0.9V_DDR_VTT

C282
0.1U/10V

C283
0.1U/10V

C285
0.1U/10V

C265
0.1U/10V

C267
0.1U/10V

C287
0.1U/10V

+0.9V_DDR_VTT
<6,7,15> DDR_A_MA[0..14]

DDR_B_MA[0..14]
RP26

<6,7,15>

RP41

www.kythuatvitinh.com
DDR_A_MA7
DDR_A_MA11

2
4

1
3

1
3

4P2R-S-56
RP25

DDR_A_MA4
DDR_A_MA6

2
4

1
3

1
3

4P2R-S-56
RP23

<7,15> DDR_A_RAS#
<7,15> DDR_A_BS1

DDR_A_RAS#
DDR_A_BS1

2
4

DDR_A_MA13
M_ODT0

1
3

2
4

1
3

DDR_A_BS2
DDR_A_MA12

2
4

1
3

1
3

Please these resistor


closely DIMMA,all
trace length<750 mil.

DDR_A_MA9
DDR_A_MA8

2
4

DDR_A_MA5
DDR_A_MA3

2
4

DDR_B_MA13
M_ODT2

2
4

1
3

1
3

1
3

1
3

1
3

1
3

1
3

1
3

4P2R-S-56
RP19

DDR_A_WE#
DDR_A_CAS#

2
4

1
3

<6,15> M_ODT1
<6,15>
<6,15>
<6,15>
<6,15>

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA

R164
DDR_A_MA1 R165
R173
R168
R166
R174
DDR_A_MA14 R171

1
1
1
1
1
1
1

2
4

DDR_B_MA3
DDR_B_MA1

2
4

DDR_B_MA12
DDR_B_MA9

2
4

DDR_B_MA8
DDR_B_MA5

2
4

DDR_B_MA10
DDR_B_BS0

2
4

DDR_B_WE#
DDR_B_CAS#

2
4

DDR_B_MA0
DDR_B_MA2

DDR_A_BS0 <7,15>

Please these resistor


closely DIMMB,all
trace length<750 mil.

DDR_B_BS0 <7,15>

DDR_B_WE# <7,15>
DDR_B_CAS# <7,15>

4P2R-S-56
RP39
1
3

4P2R-S-56
2
2
2
2
2
2
2

DDR_A_MA10
DDR_A_BS0

4P2R-S-56
RP42
1
3

2
4

2
4

DDR_B_RAS# <7,15>
DDR_B_BS1 <7,15>

4P2R-S-56
RP43

4P2R-S-56
RP24
DDR_A_MA0
DDR_A_MA2

DDR_B_RAS#
DDR_B_BS1

4P2R-S-56
RP45

4P2R-S-56
RP17
<7,15> DDR_A_WE#
<7,15> DDR_A_CAS#

2
4

4P2R-S-56
RP46

4P2R-S-56
RP38
<6,15> M_ODT2

DDR_B_MA4
DDR_B_MA6

4P2R-S-56
RP44

4P2R-S-56
RP20

2
4

4P2R-S-56
RP18

4P2R-S-56
RP21

<7,15> DDR_A_BS2

DDR_B_MA7
DDR_B_MA11

4P2R-S-56
RP37

4P2R-S-56
RP22

<6,15> M_ODT0

2
4

4P2R-S-56
RP40

1
3
56
56
56
56
56
56
56

R450
R451
R446
R459
R452
R167
R447

4P2R-S-56
2
2
2
2
2
2
2

1
1
1
1
1
1
1

56
56
56
56
56
56
56

DDR_B_MA14

M_ODT3 <6,15>
DDR_B_BS2 <7,15>
DDR_CS2_DIMMB# <6,15>
DDR_CS3_DIMMB# <6,15>
DDR_CKE2_DIMMB <6,15>
DDR_CKE3_DIMMB <6,15>

DELL CONFIDENTIAL/PROPRIETARY
Title
DDR2 RES ARRAY

Size

Document Number
M-08

Date:

Monday, March 05, 2007


7

Rev
0.1
Sheet

of

16
8

51

Y2
CLK_XTAL_IN 1
+3.3V_RUN

CLK_XTAL_OUT

+3.3V_RUN
CLK_3GPLLREQ#
SATA_CLKREQ#
CARD_CLK_REQ#
MINI1CLK_REQ#
MINI2CLK_REQ#
MINI3CLK_REQ#

C108
27P/50V

14.318MHz

PCI_LOM

PGMODE

R74
10K_NC

Non-iAMT

+3.3V_RUN
R61

2 10K

PCI_PCCARD

+CK_VDD_MAIN2

1 = Disc. GRFX down

+CK_VDD_MAIN
+CK_VDD_48

+3.3V_RUN

34

Non-iAMT

C87

Enable ITP
<3,6> CPU_MCH_BSEL0

10K
R43
1
PCI_ICH

<13> CLK_ICH_48M
L64

<3,6> CPU_MCH_BSEL1
<3,6> CPU_MCH_BSEL2

59
<13>

R28
R38
R31
R71
R72
R59

1
<28> CLK_PCI_5025

BK1005LL330
CX5LL330000

2
R49
2 0_0603 R44

C121 1
2 BLM18SG260

L65

CLK_ICH_14M

C122 1

<20> CLK_PCI_PCCARD

C123 1

<35> CLK_PCI_LOM

4.7P/50V_NC
1
2 33
2.2K_0402

R58

R57
R60
2
R62
2
R63
2

2
2

2 2.2K_0402
4.7P/50V_NC
1 15
1 51
4.7P/50V_NC
2
1 22
6P/50V
2
1 43
6P/50V

1
49
54
65

VDD_SRC_01
VDD_SRC_02
VDD_SRC_03
VDD_SRC_04

30
36

VDD_PCI_01
VDD_PCI_02

12

VDD_CPU

40
18

VDD_REF

20
19

XIN
XOUT

FSA
FSB
FSC

41
45
23

48M/FSA
FSB/TEST_MODE
REF0/FSC_TEST_SEL

CLKREF

22

REF1

PCI_LOM

27
32
33
34

1
1
1
1
1
1

2 10K_NC

+CK_VDD_A

PCI_STP#
CPU_STP#

25
24

CPUT1_MCH
CPUC1_MCH

11
10

MCH_BCLK
MCH_BCLK#

4
2

3 RP12
1 4P2R-S-22

CLK_MCH_BCLK <5>
CLK_MCH_BCLK# <5>

CPUT0
CPUC0

14
13

CPU_BCLK
CPU_BCLK#

4
2

3 RP13
1 4P2R-S-22

CLK_CPU_BCLK <3>
CLK_CPU_BCLK# <3>

CPUT2_ITP/SRCT_10
CPUC2_ITP/SRCC_10

6
5

CPU_ITP
CPU_ITP#

4
2

3 RP10
1 4P2R-S-22

CLK_CPU_ITP <3>
CLK_CPU_ITP# <3>

PGMODE

PGMODE R41

SRCT_9
SRCC_9
CLKREQ9#
SRCT_8
SRCC_8
CLKREQ8#
SRCT_7
SRCC_7
CLKREQ7#
SRCT_6
SRCC_6
CLKREQ6#
SRCT_5
SRCC_5
CLKREQ5#
SRCT_4
SRCC_4
CLKREQ4#
SRCT_3
SRCC_3
CLKREQ3#
SRCT_2
SRCC_2
CLKREQ2#
SRCT_1/SATAT
SRCC_1/SATAC
CLKREQ1#

3
2
72
70
69
71
66
67
38
63
64
62
60
61
29
58
59
57
55
56
28
52
53
26
50
51
46

PCIE_EXPCARD 4
PCIE_EXPCARD# 2

SRCT_0/LCD100MT
SRCC_0/LCD100MC

47
48

VDD_48

CLK_XTAL_IN
CLK_XTAL_OUT

7
8

VDDA
VSSA

CK505

+CK_VDD_REF

PCI_SIO
PCI_PCCARD

R42

10K
10K
10K
10K
10K
10K

2
2
2
2
2
2

Populate for Napa platforms only.

U9

0=UMA

1
2

FSA

R73
10K

R47
10K_NC

C109
27P/50V

2
R39
10K_NC

R55
1

2
14.318MHZ

+3.3V_RUN

Non-iAMT

PCI1
PCI2/TME
PCI3
PCI4/FCTSEL1

PCIE_VGA
PCIE_VGA#

H_STP_PCI# <13>
H_STP_CPU# <13>

23

2 10K_NC

CLK_PCIE_EXPCARD <26>
CLK_PCIE_EXPCARD# <26>
CARD_CLK_REQ# <26>
CLK_PCIE_VGA <18>
CLK_PCIE_VGA# <18> Discrete

3 RP3
1 4P2R-S-33

4
2

23

PCIE_ICH
PCIE_ICH#

2
4

MCH_3GPLL
MCH_3GPLL#
R32
PCIE_MINI2
PCIE_MINI2#
MINI2CLK_REQ#

2
4

PCIE_MINI1
PCIE_MINI1#
MINI1CLK_REQ#
PCIE_MINI3
PCIE_MINI3#
MINI3CLK_REQ#
PCIE_SATA
PCIE_SATA#

2
4

1 RP4
3 4P2R-S-0
1
3
1
1
3

Non-iAMT

+3.3V_RUN

3 RP8
1 4P2R-S-33

CLK_PCIE_ICH <12>
CLK_PCIE_ICH# <12>

RP5
4P2R-S-33
475/F
RP6
4P2R-S-33
R543 1

CLK_MCH_3GPLL <6>
CLK_MCH_3GPLL# <6>
CLK_3GPLLREQ# <6>
CLK_PCIE_MINI2 <24>
CLK_PCIE_MINI2# <24>
2 0
MINI2CLK_REQ#_R

www.kythuatvitinh.com
C124 1
C81

2 4.7P/50V
R48
2

<12> CLK_PCI_ICH

PCI_ICH

1 33

<13> CLK_PWRGD

CLK_SCLK
CLK_SDATA

+3.3V_RUN

C75
0.1U/10V

C85
0.1U/10V

C60
0.1U/10V

C65
0.1U/10V

C64
0.1U/10V

+CK_VDD_MAIN

120 ohms@100Mhz

DOT96T/27M_NSS
DOT96C/27M_SS

37

PCIF0/ITP_SEL

39

VTT_PWRDG#/PD(CKPWRGD/PD#)

16
17

SCLK
SDATA

15
31
35
21
4
42
68

Discrete without iAMT

L12
1
2
BLM21PG600SN1D

43
44

C61
10U/6.3V

VSS_01
VSS_02
VSS_03
VSS_04
VSS_05
VSS_06
VSS_07

2
4

1 RP7
3 4P2R-S-33
R186 1
1 4P2R-S-0
3 RP9
R544 1
1 RP11
3 4P2R-S-33

2
4
2
4

CY28547BLFXC

SMbus address D2
These are for
backdrive issue.

RP30
4P2R-2.2K
Q30
1

<28> CKG_SMBDAT

FSC

FSB

FSA

CPU SRC PCI

100

100

33

133

100

33

166

100

33

200

100

33

266

100

33

333

100

33

400

100

33

RSVD

100

33

<24>
<25>

1
3

C113
10U/6.3V

Non-iAMT

R289
2.2K
1

C72
4.7U/6.3V

1
C111
0.1U/10V

1
C110
0.1U/10V

1
2

120 ohms@100Mhz

+CK_VDD_MAIN2

L19
1
2
BLM21PG600SN1D

C77
0.047U/10V

+3.3V_RUN

2
4

+3.3V_ALW

+CK_VDD_A
1

2.2
2

R37
1

CLK_PCIE_MINI1 <24>
CLK_PCIE_MINI1# <24>
2 0
MINI1CLK_REQ#_R
CLK_PCIE_MINI3 <25>
CLK_PCIE_MINI3# <25>
2
MINI3CLK_REQ#_R
0_0402
CLK_PCIE_SATA <11>
CLK_PCIE_SATA# <11>
SATA_CLKREQ# <13>

<24>

CLK_SDATA

2N7002W-7-F
R287
1

+CK_VDD_48

+3.3V_ALW

1
C93
4.7U/6.3V

PCI_LOM = FCTSEL1

0_NC
2

FCTSEL1
(PIN34)

+3.3V_RUN

0=UMA

C99
0.047U/10V

2.2
2

R53
1

R280
2.2K
+CK_VDD_REF
<28> CKG_SMBCLK

C100
0.047U/10V

R285
1

DOT96C

PIN48

96/
100M_T

27MSSout SRCT0

96/
100M_C
SRCC0
D

Q28
1

CLK_SCLK

DELL CONFIDENTIAL/PROPRIETARY

2N7002W-7-F

DOT96T

PIN47

PIN44

1 = Disc.
GRFX down 27Mout

R54
1

PIN43

0_NC
2

Title
CLOCK GENERATOR

Size

Document Number
M-08

Date:

Wednesday, March 07, 2007


7

Rev
0.1
Sheet

of

17
8

51

YPRPB_DET: SIGNAL FROM SVIDEO CONNECTOR,


TO SWICH TO COMPONENT OUT.
JVDO1

Delete R236,R247
pre ref schematic.

<6> PCIE_MTX_GRX_N[0..15]
PCIE_MTX_GRX_N0
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_N4
PCIE_MTX_GRX_N5
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_N8
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_N10
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_N13
PCIE_MTX_GRX_N14
PCIE_MTX_GRX_N15

2
C66

1
.1U/10V/0402

PCIE_MTX_GRX_P1
PCIE_MTX_GRX_N1

2
C70

1
.1U/10V/0402

PCIE_MTX_GRX_P2
PCIE_MTX_GRX_N2

2
C76

1
.1U/10V/0402

PCIE_MTX_GRX_P3
PCIE_MTX_GRX_N3

2
C80

1
.1U/10V/0402

PCIE_MTX_GRX_P4
PCIE_MTX_GRX_N4

2
C88

1
.1U/10V/0402

2
C69
2
C74
2
C79
2
C83
2
C94

PCIE_MTX_GRX_P0
PCIE_MTX_GRX_N0

C371
.047U/10V/0402

C372
.047U/10V/0402

+3.3V_RUN

C373
.047U/10V/0402

PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0
1
.1U/10V/0402
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1
1
.1U/10V/0402
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
1
.1U/10V/0402
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3
1
.1U/10V/0402
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
1
.1U/10V/0402
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5
1
.1U/10V/0402
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6
1
.1U/10V/0402
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7
1
.1U/10V/0402
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8
1
.1U/10V/0402
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
1
.1U/10V/0402
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10
1
.1U/10V/0402
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
1
.1U/10V/0402
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12
1
.1U/10V/0402
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13
1
.1U/10V/0402
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
1
.1U/10V/0402
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15
1
.1U/10V/0402

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

YPRPB_DET# <19>
+5V_ALW
LCD_SMBCLK <28>
LCD_SMBDAT <28>

SMBUS Address 58 for Inverter.


SMBUS Address 98 for Temp.sensor.
4

TV_Y <19>
TV_CVBS <19>
TV_C <19>
VSYNC <19>
HSYNC <19>
VGA_BLU <19>
VGA_GRN <19>
VGA_RED <19>
G_CLK_DDC2 <19>
G_DAT_DDC2 <19>
LCD_TST <29>
PLTRST_DELAY# <13>
CLK_PCIE_VGA <17>
CLK_PCIE_VGA# <17>
PCIE_MRX_GTX_P0
PCIE_MRX_GTX_N0
PCIE_MRX_GTX_P1
PCIE_MRX_GTX_N1

PCIE_MRX_GTX_N[0..15] <6>
PCIE_MRX_GTX_N0
PCIE_MRX_GTX_N1
PCIE_MRX_GTX_N2
PCIE_MRX_GTX_N3
PCIE_MRX_GTX_N4
PCIE_MRX_GTX_N5
PCIE_MRX_GTX_N6
PCIE_MRX_GTX_N7
PCIE_MRX_GTX_N8
PCIE_MRX_GTX_N9
PCIE_MRX_GTX_N10
PCIE_MRX_GTX_N11
PCIE_MRX_GTX_N12
PCIE_MRX_GTX_N13
PCIE_MRX_GTX_N14
PCIE_MRX_GTX_N15

PCIE_MRX_GTX_P2
PCIE_MRX_GTX_N2
PCIE_MRX_GTX_P3
PCIE_MRX_GTX_N3

www.kythuatvitinh.com
2
C139
2
C156

+3.3V_SUS

1
C429
.1U/10V/0402

For Discrete:
Populate C178,C181

+1.8V_RUN
C428
.1U/10V/0402

+15V_ALW
<28,29,38,45> RUNPWROK
+2.5V_RUN

1
R94
100K_0402

C160
.1U/50V/0603

PCIE_MRX_GTX_P13
PCIE_MRX_GTX_N13

6
5
2
1

PCIE_MRX_GTX_P12
PCIE_MRX_GTX_N12

80 mil

80 mil

Q9
SI3457BDV-T1-E3
2

PCIE_MRX_GTX_P11
PCIE_MRX_GTX_N11

+G_PWR_SRC

+PWR_SRC

INV_PWR_SRC_ON
PCIE_MRX_GTX_P14
PCIE_MRX_GTX_N14

PCIE_MTX_GRX_P15
2
1
PCIE_MTX_GRX_N15 C148 .1U/10V/0402

2
C138

PCIE_MRX_GTX_P10
PCIE_MRX_GTX_N10

PCIE_MRX_GTX_P15
PCIE_MRX_GTX_N15

R103
100K_0402
2

PCIE_MTX_GRX_P14
2
1
PCIE_MTX_GRX_N14 C136 .1U/10V/0402

2
C134

PCIE_MRX_GTX_P9
PCIE_MRX_GTX_N9

+3.3V_RUN
GFX_PWRGD <38>
LCDVCC_TST_EN <28>
THERMATRIP_VGA# <34>
+5V_RUN
PANEL_BKEN <29>
+G_PWR_SRC

C166
.1U/50V/0402

C169
.1U/50V/0402

C175
.1U/50V/0402

PCIE_MTX_GRX_P13
2
1
PCIE_MTX_GRX_N13 C135 .1U/10V/0402
2

2
C131

PCIE_MRX_GTX_P0
PCIE_MRX_GTX_P1
PCIE_MRX_GTX_P2
PCIE_MRX_GTX_P3
PCIE_MRX_GTX_P4
PCIE_MRX_GTX_P5
PCIE_MRX_GTX_P6
PCIE_MRX_GTX_P7
PCIE_MRX_GTX_P8
PCIE_MRX_GTX_P9
PCIE_MRX_GTX_P10
PCIE_MRX_GTX_P11
PCIE_MRX_GTX_P12
PCIE_MRX_GTX_P13
PCIE_MRX_GTX_P14
PCIE_MRX_GTX_P15

INV_PWR_SRC_ON_R
2

PCIE_MTX_GRX_P12
2
1
PCIE_MTX_GRX_N12 C132 .1U/10V/0402

2
C129

PCIE_MRX_GTX_P[0..15] <6>

PCIE_MRX_GTX_P8
PCIE_MRX_GTX_N8

RUN_ON <28,38,39>

Q11
2N7002W-7-F

PCIE_MTX_GRX_P11
2
1
PCIE_MTX_GRX_N11 C130 .1U/10V/0402

2
C125

PCIE_MRX_GTX_P7
PCIE_MRX_GTX_N7

C177
.1U/50V/0402

PCIE_MTX_GRX_P10
2
1
PCIE_MTX_GRX_N10 C126 .1U/10V/0402

2
C117

2
1
C118 .1U/10V/0402

2
1
C115 .1U/10V/0402

PCIE_MTX_GRX_P9
PCIE_MTX_GRX_N9

PCIE_MRX_GTX_P6
PCIE_MRX_GTX_N6

PCIE_MTX_GRX_P8
PCIE_MTX_GRX_N8

2
C112

PCIE_MRX_GTX_P5
PCIE_MRX_GTX_N5

2
1
C105 .1U/10V/0402

2
C107

PCIE_MRX_GTX_P4
PCIE_MRX_GTX_N4

C425
10U/25V/1206

+3.3V_RUN

PCIE_MTX_GRX_P7
PCIE_MTX_GRX_N7

2
C96

2
1
C102 .1U/10V/0402

PCIE_MTX_GRX_P6
PCIE_MTX_GRX_N6

1
.1U/10V/0402

PCIE_MTX_GRX_P0
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_P4
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_P7
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_P9
PCIE_MTX_GRX_P10
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_P12
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_P14
PCIE_MTX_GRX_P15

2
C89

<6> PCIE_MTX_GRX_P[0..15]

PCIE_MTX_GRX_P5
PCIE_MTX_GRX_N5

U13
CFX_PWR_LIMIT

SIO_GFX_PWR <34>

ACAV_IN <28,34,40>

HONDA_LPF-SC200SMYGA+

7SH08_NC

1
R109

2
0_NC

Title

QUANTA
COMPUTER
VGA CARD Connector

Size

Document Number
FM1

Date:

Monday, March 05, 2007

Rev
0.1
Sheet
A

18

of

51

+5V_RUN

D22
SDM10K45-7-F

Setting R,G,B treac


impedance to 50 ohm.

L13
RED

2
BLM11B750SB
PAD

T14

<18> VGA_RED

M_SEN#_R

R279
0/1206

L14
4

L16

1
C73
10P/50V_NC

C82
10P/50V_NC

C62
22P/50V_NC

C68
22P/50V_NC

BLUE

2
BLM11B750SB
C67
10P/50V_NC

C86
22P/50V_NC

R33
150/F

R35
150/F

2
R45
150/F

<18> VGA_BLU

Place D23,D24,D26 close


to JVGA1 <200 mils

GREEN

2
BLM11B750SB

<18> VGA_GRN

PAD

T15

M_ID2#

CRT_VCC
CRT_VCC

JVGA1
6
CRT_VCC_R
11
1
7
12
2
8
13
3
9
14
4
10
15
5

+3.3V_RUN

1
3

D23

RED

2
DA204U_NC

3
1

FOX_DZ11A91-NB211-9F
+3.3V_RUN
RP29
4P2R-2.2K
1

+5V_RUN

SDM10K45-7-F
1

4
2

D27
2

<18> G_DAT_DDC2
2

U29
2

<18> HSYNC

DA204U_NC
3

R286
VGAHSYNC_R 1

10
2

<18> G_CLK_DDC2

C408
0.1U/10V
2
1

Place near U29


, U30 < 200 mil

+3.3V_RUN

C395
10P/50V_NC

www.kythuatvitinh.com
74AHCT1G125GW

C399
10P/50V_NC

JVGA_HS

2
BLM11A121S

DA204U_NC

L17

C5

C71
10P/50V_NC

C78
10P/50V

C103
10P/50V_NC

+3.3V_RUN

1
2

74AHCT1G125GW

JVGA_VS

2
BLM11A121S

Place All of those


Inductors Caps close
to JTV <200 mils

10
2

R293
VGAVSYNC_R 1

BLUE

U30

D26

L15

<18> VSYNC

GREEN

C400
0.01U/25V

R290 1K
2
1

D24

C92
10P/50V

SVIDEO_C

22P_NC

1
R6
150/F_0402

C6
6P/50V/0402

JTV1

Update it
per ref
schematic.

D20
DA204U_NC

Place near JVGA1 connector <


200 mil

C10
6P/50V/0402

<18> TV_C

1
2
L4
BLM18BD151SN1D

3
6
7
5
2
4
1

SVIDEO_C
SVIDEO_CVBS

D21
1
SVIDEO_Y

3
2

C11
6P/50V/0402

SVIDEO_Y

1
2
L5
BLM18BD151SN1D

<18> TV_Y

R7
150/F_0402

22P_NC

C7

+3.3V_RUN

FOX_MH1177L-BG6N-7FL

C8
6P/50V/0402

DA204U_NC

11/1 Update FP
+3.3V_RUN
1
SP_DIF_E
2

10K

SP_DIF

1
R214

2
220_0603

U4
74AHCT1G125GW

SP_DIFB

2
C337

SP_DIFC
1
.01U/25V/0402

1
R213

R211
110_0603

R215
0_NC

2
0_0805

2
0_0603_NC

YPRPB_DET# <18>

SP_DIF_D

Title

Add R213 pre


ref
schematic.

SVIDEO_CVBS

D19
DA204U_NC

Populate R218 & De-populate R216


when component VIDEO is enable.

QUANTA
COMPUTER
CRT&TV CONN

1
R210

2
0_0805

C342
300P_NC

1
R216

<32> AUD_SPDIF_OUT

3
2

C4
6P/50V/0402

R212

+3.3V_RUN
R218
47K_0603

C9
6P/50V/0402

2
1
C336
.1U/10V/0402

R5
150/F_0402

1
2
L3
BLM18BD151SN1D

<18> TV_CVBS
+5V_RUN

22P_NC

C3

Size

Document Number
M-08

Date:

Monday, March 05, 2007

Rev
0.1
Sheet
E

19

of

51

+3.3V_R5C832
+3.3V_R5C832

+3.3V_R5C832
C149
10U/10V/0805

C152
.01U/25V/0402

C154
.01U/25V/0402

C155
.01U/25V/0402

C438
.01U/25V/0402

C162
.01U/25V/0402
+3.3V_RUN

C455
10U/10V/0805

C471
.01U/25V/0402

C468
.1U/10V/0402

C464
.01U/25V/0402

Place the power caps close


to the relation pins.

C153
.01U/25V/0402

C433
.01U/25V/0402

C173
.47U/10V/0603

C477
.47U/10V/0603

10
20
27
32
41
128

VCC_PCI1
VCC_PCI2
VCC_PCI3
VCC_PCI4
VCC_PCI5
VCC_PCI6

61

VCC_RIN

16
34
64
114
120

67

VCC_3V

<12,35> PCI_AD[31..0]

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

PowerOnReset for VccCore

1
R142
C480
.01U/25V/0402

2
0_0805

C220
10U/10V/0805

VCC_ROUT1
VCC_ROUT2
VCC_ROUT3
VCC_ROUT4
VCC_ROUT5
86

VCC_MD

PCI Bus

+3.3V_R5C832

Place the power caps close


to the relation pins.

U12B

125
126
127
1
2
3
5
6
9
11
12
14
15
17
18
19
36
37
38
39
40
42
43
44
46
47
48
49
50
51
52
53
33
7
21
35
45
8

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
PAR
C/BE3#
C/BE2#
C/BE1#
C/BE0#
IDSEL

124
123
23
24
25
26
29
30
31

REQ#
GNT#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR#

71
119

GBRST#
PCIRST#

121

PCICLK

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10

4
13
22
28
54
62
63
68
118
122

AGND1
AGND2
AGND3
AGND4
AGND5

99
102
103
107
111

www.kythuatvitinh.com
C219
1U/10V/0603

PCI Bus

<12,35> PCI_PAR
<12,35> PCI_C_BE3#
<12,35> PCI_C_BE2#
<12,35> PCI_C_BE1#
<12,35> PCI_C_BE0#

PCI_AD17

1
R87

2
100_0402

<12> PCI_REQ1#
<12> PCI_GNT1#
<12,35> PCI_FRAME#
<12,35> PCI_IRDY#
<12,35> PCI_TRDY#
<12,35> PCI_DEVSEL#
<12,35> PCI_STOP#
<12,35> PCI_PERR#
<12,35> PCI_SERR#
<12,35> PCI_RST#
<17> CLK_PCI_PCCARD
<29,35> SYS_PME#

CoreLogic CLOCKRUN#

2
R135

70

1
0_NC

117

<13,28,35> CLKRUN#

+3.3V_R5C832
Route to GPIOG6 (pin 94) on the
SIO companion chip ECE5011, with
the signal named CB_HWSPND#

PME#

+3.3V_R5C832

HWSPND#

69

MSEN

58

Memory Stick Enable

XDEN

55

XD Card Enable

UDIO5

57

UDIO3
UDIO4

65
59

UDIO2

56

R367
10K_0402

R365
100K_0402

UDIO1

60

UDIO0/SRIRQ#

72

Serial ROM disable


SD Card Enable
MMC Card Enable
3

IRQ_SERIRQ <13,28>

PCI Bus
INTA#

115

PCI_PIRQD# <12>

INTB#

116

PCI_PIRQC# <12>

TEST

66

T33

1394 Interrupt
Media card Interrupt

PAD

CLKRUN#
2

The ICH schematics need to include a


pull-up resistor to implement CLKRUN#,
and the ICH schematics must have a
pull-down, or constantly drive thesignal
low, in order to disable CLKRUN#.

R134
10K_0402

GBRST# should be asserted only


when system power supply is on.

+3.3V_R5C832

R136
100K_0402

PCI / OTHER

+3.3V_R5C832

R5C833T_V00
AJ5C8320H00
1

R133
100K_0402

CLK_PCI_PCCARD
1

Refer to DELL
M07 schematic
X06

1 2

R102
33

C167
12P

Title

QUANTA
COMPUTER
CRT&TV CONN

Size

Document Number
M-08

Date:

Monday, March 05, 2007

Rev
0.1
Sheet
E

20

of

51

+3.3V_R5C832

80 mils
+3.3V_RUN_PHY
L22
BLM18PG181SN1D
1

U12A

C168
10U/10V/0805

AVCC_PHY1
AVCC_PHY2
AVCC_PHY3
AVCC_PHY4

98
106
110
112

TPBIAS0

113

C178
.1U/10V/0402

C176
.01U/25V/0402

C196 modify
1000P/50V/0402

Place these caps as close to the U26 as possible.

AS CLOSE AS POSSIBLE TO R5C832


GUARD GND

1394_XI

94

C214 22P/50V/0402

XI

95
2
0_0402

XO

Populate C197 for


R5C832 chip
RICOH_FILO 96
C197 .01U/25V/0402_NC

FIL0

R124

RICOH_REXT101
10K/F_0402

IEEE1394/SD

1394_XO 1
R132

C180 .33U/16V/0603

R110
56.2/F_0603

Y4
24.576MHz
C215 22P/50V/0402

TPBIAS0

R115
56.2/F_0603

C181 .01U/25V/0402

TPBN0

104

TPB0N

TPBP0

105

TPB0P

TPAN0

108

TPA0N

TPAP0

109

TPA0P

*TPA0P/TPA0N,TPB0P/TPB0N pair trace : As close as possible.


*TPA0P/TPA0N,TPB0P/TPB0N pair trace : Same length electrically.
*Termination resistor for TPA+/- TPB+/- : As close as possible to its cable driver (device pin out).
2

REXT
R117
56.2/F_0603

R121
56.2/F_0603

C183

270P/25V/0402

www.kythuatvitinh.com
RICOH_VREF100
C191 .01U/25V/0402

VREF

R122

5.11K/F_0402

Circuit area : As small as possible.

87

XD_DATA7

MDIO16

92

XD_DATA6

MDIO15

89

XD_DATA5

MDIO14

91

XD_DATA4

MDIO13

90

SD/XD/MS_DATA3

MDIO12

93

SD/XD/MS_DATA2

MDIO11

81

SD/XD/MS_DATA1

MDIO10

82

SD/XD/MS_DATA0

MDIO05

75

MDIO08

88

MDIO19

83

XD_ALE <22>

MDIO18

85

XD_CLE <22>

MDIO02

78

XD_CE# <22>

MDIO03

77

SD_WP#(XDR/B#)

MDIO00

80

SD_CD#

MDIO01

79

MS_INS#

XD_DATA7 <22>
XD_DATA6 <22>

L24
DLW21HN121SQ2_NC
4 4

AS CLOSE AS POSSIBLE TO
1394 CONNECTOR.

XD_DATA5 <22>

CON2
UV31413-WSU0D-7F

XD_DATA4 <22>

TPB0N

SD/XD/MS_DATA3 <22>

R119

0_0805

R114

0_0805

R79

0_0805

R86

0_0805

TPB0P

SD/XD/MS_DATA2 <22>

TPA0N

SD/XD/MS_DATA1 <22>

TPA0P

SD/XD/MS_DATA0 <22>

TPB0-

TPB0+

TPA0-

TPA0+

MDIO17

5
6
7
8

Place these caps as close


to the U26 as possible.

5
6
7
8

XD_WP# <22>
SD/XD/MS_CMD

SD/XD/MS_CMD <22>

+3.3V_R5C832

97

MDIO04

76

MDIO06

74

MDIO07

73

RSV

11/1 Update FP

R146
10K_NC
1

MS_INS# <22>
84

SD_WP#(XDR/B#) <22>

SD_CD# <22>

MDIO09

L20
DLW21HN121SQ2_NC

2
D11

1
1SS355

2
D10

1
1SS355

close to the Chip


XD_CDSW# <22>

SD/XD/MS_CLK <22>
MC_PWR_CTRL_0 <22>
T34 PAD

R5C833T_V00

Title

QUANTA
COMPUTER
CRT&TV CONN

Size

Document Number
M-08

Date:

Monday, March 05, 2007

Rev
0.1
Sheet
E

21

of

51

+3.3V_RUN_CARD
+3.3V_RUN_CARD
1

CON6
<21> SD_CD#

49

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

SD_CD#
SD_WP#
XD_DATA7
XD_DATA6
XD_DATA5
SD/XD/MS_DATA1
XD_DATA4
SD/XD/MS_DATA0
SD/XD/MS_DATA3
SD/XD/MS_DATA2
SD/XD/MS_DATA1
SD/XD/MS_CMD
SD/XD/MS_CLK
SD/XD/MS_DATA1
SD/XD/MS_DATA0
SD/XD/MS_DATA0

2
R149

1
0_0402

SD(CD2/WP2/GND)
SD(CD1)
SD(WP1)
XD-18(VCC)
XD-17(D7)
XD-16(D6)
XD-15(D5)
SD-8(DAT1)
XD-14(D4)
SD-7(DAT0)
XD-13(D3)
XD-12(D2)
SD-6(GND/VSS2)
MS-1(VSS)
XD-11(D1)
MS-2(BS)
SD-5(CLK)
MS-3(VCC/DATA1)
XD-10(D0)
MS-4(SDIO/DATA0)
SD-4(VCC/VDD)

MS-5(DATA2)
XD-9(GND)
MS-6(INS)
SD-3(VSS1)
MS-7(DATA3)
XD-8(-WP)
MS-8(SCLK)
SD-2(CMD)
MS-9(VCC)
XD-7(WE)
MS-10(VSS)
SD-1(DAT3)
XD-6(ALE)
SD-9(DAT2)
XD-5(CLE)
XD-4(CE)
XD-3(RE)
XD-2(R/-B)
XD-1(CD)
XD-0(GND)

22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41

SD/XD/MS_DATA2
MS_INS# <21>

2
R131

SD/XD/MS_DATA3
XD_WP#
SD/XD/MS_CLK
1
0_0402SD/XD/MS_CMD

+3.3V_RUN_CARD

SD/XD/MS_CMD
SD/XD/MS_DATA3
XD_ALE
SD/XD/MS_DATA2
XD_CLE
XD_CE#
SD/XD/MS_CLK
SD_WP#(XDR/B#)
XD_CDSW#

C229
.01U/25V/0402

C225
.01U/25V/0402

C511
.01U/25V/0402

R397
150K_0402

TAI-SOL144-2400000900
C243
2.2U/6.3V/0603

8 IN1 CARD READER

www.kythuatvitinh.com
<21> XD_CDSW#

<21> SD_WP#(XDR/B#)

<21> XD_DATA7
<21> XD_DATA6
<21> XD_DATA5
<21> XD_DATA4

+3.3V_R5C832

<21> SD/XD/MS_DATA3
<21> SD/XD/MS_DATA2

U16

<21> SD/XD/MS_DATA1
<21> SD/XD/MS_DATA0

<21> MC_PWR_CTRL_0

5
3

IN OUT
NC

EN GND

+3.3V_RUN_CARD

<21> SD/XD/MS_CMD
TPS2051BDBV

C199
1U/10V/0603

<21> XD_WP#
3

C198
.1U/10V/0402

<21> XD_ALE

AAT4250 will be tested


by 2'nd source after
proto2 build.

<21> XD_CLE
<21> XD_CE#
<21> SD/XD/MS_CLK

SD Protect
R558

0_0402_NC

49

Q77
2N7002W-7-F
3

SD_WP#

SD_WP#(XDR/B#)

XD_CDSW#

Title

QUANTA
COMPUTER
CRT&TV CONN

Size

Document Number
M-08

Date:

Monday, March 05, 2007

Rev
0.1
Sheet
E

22

of

51

SATA 1 & 2 Connector.

+5V_MOD

ODD Connector.

CON4

+5V_MOD

+3.3V_RUN

+5V_HDD

Corsica

30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

3.3V_0
3.3V_1
3.3V_2
GND4
GND5
GND6
5V_0
5V_1
5V_2
GND7
RSVD
GND8
12V_0
12V_1
12V_2

3.3V_0
3.3V_1
3.3V_2
GND4
GND5
GND6
5V_0
5V_1
5V_2
GND7
RSVD
GND8
12V_0
12V_1
12V_2

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

SATA_TX2+ <11>
SATA_TX2- <11>
SATA_RX2-_C
SATA_RX2+_C

R500
56
IDE_RST_MOD# 1
IDE_DD7
IDE_DD6
+3.3V_RUN
IDE_DD5
IDE_DD4
IDE_DD3
IDE_DD2
0506: ref
IDE_DD1
CL1301
R486
IDE_DD0
P52
4.7K_0402
IDE_DIOW#
IDE_DIORDY
R191 2
IDE_IRQ
1 8.2K
+3.3V_RUN
IDE_DA1
IDE_DA0
+5V_MOD
IDE_DCS1#
IDE_LED#
2
1
R483
510/F_0402_NC

+3.3V_RUN

+5V_HDD

PLATFORM_BID <29>
R554
0

+5V_MOD

Low : Gilligan
2
R482

( with 2nd HDD )

IDE_DDACK#_R 2
R488
2
IDE_DA2
R484
IDE_DCS3#

IDE_DDACK#
1
22_0402
1
100K_0402_NC

+5V_MOD

SATA_RX2-_C
SATA_RX2+_C

2
C889
1U/10V/0603

1 3900P/25V
1 3900P/25V

C888
.1U/10V/0402

C890
.1U/10V/0402

2
2

SATA_RX0-_C
SATA_RX0+_C

1 3900P/25V
1 3900P/25V

+5V_HDD

2
2

C629
C628

<11> SATA_RX2<11> SATA_RX2+

IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15
IDE_DDREQ
IDE_DIOR#

R481
470_0402

Only for Corsica

C627
C626

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

tyco_1909380-1

Pin.47 Cable select


H=Slave,L=Master

10/20 Update FP

Locate caps C626, C627, C628, C629 near HDD Conn.


Length match SATA_C_RX0- & SATA_C_RX0+ within 0 mils.
<11> SATA_RX0<11> SATA_RX0+

1
470_NC

High : Corsica

QT600806-400S-9F

Place close to
connector side

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

<13> IDE_RST_MOD#

1
2
3
4
5
6
7

DFHS22FR012

GND1
RXP
RXN
GND2
TXN
TXP
GND3

51
52

GND1
RXP
RXN
GND2
TXN
TXP
GND3

SATA_RX0-_C
SATA_RX0+_C

23
24
25
26
27
28
29

<11> SATA_TX0+
<11> SATA_TX0-

51
52

CON5

C891
1000P/50V/0402

+5V_MOD
IDE_DD[0..15]

<11> IDE_DD[0..15]

C894
.1U/10V/0402_NC

C893
1U/10V/0603_NC

1
2

C892
10U/10V/0805_NC

C895
1000P/50V/0402_NC

SATA PWR

C295
.1U/10V/0402

C297
1000P/50V/0402

C294
1U/10V/0603

C296
10U/10V/0805

IDE_DDREQ
IDE_DIOW#
IDE_DIOR#
IDE_DIORDY
IDE_DDACK#
IDE_IRQ
IDE_DA1
IDE_DA0
IDE_DCS1#
IDE_DA2
IDE_DCS3#

<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>

+3.3V_RUN

www.kythuatvitinh.com
Only for Corsica

IDE_DDREQ
IDE_DIOW#
IDE_DIOR#
IDE_DIORDY
IDE_DDACK#
IDE_IRQ
IDE_DA1
IDE_DA0
IDE_DCS1#
IDE_DA2
IDE_DCS3#

C298
.1U/10V/0402

Place closed to
MOD connector

ODD PWR

+5V_MOD

<29> MODC_EN

Power Estimate:
SATA drive power consumption estimate at
MobileMark is 1.1W. An additional 150mW
can be saved using Intel's IMST driver.

2
Q55A
2N7002DW_NC

C612
0.1U/25V_NC

Q55B
2N7002DW_NC

R514
100K

R515
100K_NC

Q51B
2N7002DW

17
1

17

17

C608
0.1U/25V

R517
100K_NC

C610
0.01U/25V_NC

6
1

<29> HDDC_EN

Q51A
2N7002DW

17

C613
10U/10V_NC

R494 100K_NC
2
1

+15V_ALW

SATA drive vendors will use only 5V


supply from the system and will derive
3.3V on the drive. If drive power
goals are not achieved, drive vendors
will use both 5V and 3.3V supplies
from the system. Initial power saving
using 3.3V from system is less than 5%.

C618
1U/16V_NC

R490
100K_NC
2

HDD_EN_5V

1
3

2
R476
100K_NC

PR195
100K_0402_NC

R478
100K

PR194
100K_0402

+5V_ALW2
R479
100K

C609
10U/10V

2
0_0805
C

+15V_ALW

8
7
6
5

1
R489

Q56
SI4800BDY_NC
3
2
1
1

17
+3.3V_ALW2

+5V_ALW2

+5V_MOD

2
0_0805_NC

4
1

17

+3.3V_ALW2

+5V_ALW
1
R485

Q52
SI3456BDV
6
5
2
1

+5V_RUN

+5V_RUN

+5V_HDD

+5V_HDD

+5V_ALW

QUANTA
COMPUTER

Title

SATA (HDD&CD_ROM)

Size

Document Number
M-08

Date:

Monday, March 05, 2007


7

Rev
0.1
Sheet

of

23
8

51

+3.3V_WLAN

MiniCard WLAN connector

+3.3V_RUN
1 100K PCIE_MCARD1_DET#
1 100K USB_MCARD1_DET#

22
+3.3V_WLAN +1.5V_RUN

+3.3V_WLAN

4
2

R155 2
R145 2

RP51
4P2R-2.2K
Q75
2N7002W-7-F_NC

3
1

J5
R157 1
2 0
R158 1
2 0
MINI1CLK_REQ#_R

<17> CLK_PCIE_MINI1#
<17> CLK_PCIE_MINI1

40

C649
220P/50V/0402

29

R275 1
R549 1

<28> HOST_DEBUG_RX
<28> 8051_TX

2 0
2 0

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

<12> PCIE_RX2<12> PCIE_RX2+

<12> PCIE_TX2<12> PCIE_TX2+


PCIE_MCARD1_DET#

<13> PCIE_MCARD1_DET#

PCI-Express TX and RX direct to connector

Non-iAMT

RSV_ICH_CL_CLK1
RSV_ICH_CL_DATA1
RSV_ICH_CL_RST1#

T101 PAD
T100 PAD
T96 PAD

DEBUG PINS
JMINI Pin
16

HOST_DEBUG_TX

70

17

HOST_DEBUG_RX

71

GND3
W_DISABLE#
PERST#
3.3VAUX1
GND5
1.5V_2
SMB_CLK
SMB_DATA
GND8
USB_DUSB_D+
GND10
LED_WWAN#
LED_WLAN#
LED_WPAN#
1.5V_3
GND11
3.3V_2

2
4
6
8
10
12
14
16

WLAN_SMBCLK

J8
MOLEX_48099-6701

1
R242
2

R550 1

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

2 0

HOST_DEBUG_TX <28>

R380
1

0_0402
2

R387
1

0_0402_NC
WLAN_RADIO_OFF#
2
SB_WLAN_PCIE_RST#
+3.3V_WLAN

WLAN_SMBDATA

Q74
2N7002W-7-F_NC

<12>

R516
2

USB_MCARD1_DET#
R551 1
2 0

PAD
PAD

2
0_0402_NC

T108
T109
USB_MCARD1_DET# <13>
8051_RX <28>
LED_WLAN_OUT# <37>
LED_WPAN# <37>

ICH_SMBDATA <13,25,26>

0_NC
1

Suport for WoW


WLAN_RADIO_OFF#

WLAN_RADIO_DIS#

40

Place caps close to


connector.

+PWR_SRC

+3.3V_WLAN

Prevent backdrive when


WoW is enabled.

+PWR_SRC

+3.3V_ALW

+3.3V_WLAN
Q10
SI3456DV_NC

www.kythuatvitinh.com
1

R112
100K_NC

+3.3V_RUN

MINI2CLK_REQ#_R
C880
220P/50V/0402

29

USB_MCARD3_DET# <13>

2 0LED_WPAN#

C170
0.1U/10V

C171
0.047U/10V

C158
0.1U/10V

USBP4_DUSBP4_D+
USB_MCARD3_DET#

C151
0.047U/10V

C161
4.7U/10V

LED_WPAN# <37>

Change USBP7 to USBP4

MOLEX_67910-6700

16

L32
USBP4_DUSBP4_D+

1
4

2
3

ICH_USBP4- <12>
ICH_USBP4+ <12>

QUANTA
COMPUTER

DLW21SN900SQ2B_NC

+3.3V_RUN

41

<13>

C164
100P/50V_NC

ICH_SMBCLK <13,25,26>
ICH_SMBDATA <13,25,26>

R552 1

C424
0.1U/10V_NC

PCI-Express TX and RX direct to connector

C150
0.047U/10V

PCIE_MCARD3_DET#

<13> PCIE_MCARD3_DET#

WPAN_RADIO_DIS_MINI#
SB_MCARD3_PCIE_RST# <12>

C159
0.047U/10V

<12> PCIE_TX3<12> PCIE_TX3+

PLTRST1# <12,25,26>

<12> PCIE_RX3<12> PCIE_RX3+

0_0402
2

R99
0_0402_NC
1
2
+3.3V_RUN

R98
1

C157
33P/50V_NC

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

J7
MOLEX_48099-6701

+3.3V_RUN

+1.5V_RUN

GND3
W_DISABLE#
PERST#
3.3VAUX1
GND5
1.5V_2
SMB_CLK
SMB_DATA
GND8
USB_DUSB_D+
GND10
LED_WWAN#
LED_WLAN#
LED_WPAN#
1.5V_3
GND11
3.3V_2

10/22 GG request Place caps close to connector.

UIM_C8
UIM_C4
GND4
PERn0
PERp0
GND6
GND7
PETn0
PETp0
GND9
RESERVED_3
RESERVED_4
RESERVED_5
RESERVED_6
RESERVED_7
RESERVED_8
RESERVED_9
RESERVED_10

2
4
6
8
10
12
14
16

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

3.3V_1
GND0
1.5V_1
UIM_PWR
UIM_DATA
UIM_CLK
UIM_RESET
UIM_VPP

COEX2_WLAN_ACTIVE

WAKE#
RESERVED_1
RESERVED_2
CLKREQ#
GND1
REFCLKREFCLK+
GND2

<17> CLK_PCIE_MINI2#
<17> CLK_PCIE_MINI2

1
3
5
7
9
11
13
15

29

1
2 0
1
2 0
MINI2CLK_REQ#_R

<17> MINI2CLK_REQ#_R

R96
R95

<37> COEX1_BT_ACTIVE_MINI

+1.5V_RUN

J3

<25,26,29> PCIE_WAKE#
<37> COEX2_WLAN_ACTIVE
C

2N7002DW_NC

+3.3V_RUN

1 100K PCIE_MCARD3_DET#
1 100K USB_MCARD3_DET#

R100 2
R104 2

Q12B
2N7002DW_NC

C174
4700P/50V/0603_NC

+3.3V_SUS

R88
100K_NC

R111
200K_NC

<28> AUX_EN_WOWL

MiniCard WPAN connector

R107
470K_0402_NC

Q12A

2
0_0805

WLAN_ENABLE

1
R118

C234
0.1U/10V_NC

C224
0.047U/10V

6
5
2
1

R113
100K_NC

C232
0.047U/10V

C240
330U/6.3V/ESR25_NC

C481
4.7U/10V

+3.3V_RUN

C495
0.047U/10V

C486
0.1U/10V

C479
0.047U/10V

+3.3V_WLAN

C482
0.1U/10V

81

8051_RX

+1.5V_RUN

82

42

8051_TX

19

<29>

D12
SDMK0340L-7-F
2
R152
0_NC

+3.3V_WLAN

ICH_SMBCLK <13,25,26>

0_NC
1

+3.3V_WLAN

PLTRST1# <12,25,26>

WLAN_SMBCLK
WLAN_SMBDATA

1
R520

40

MOLEX_67910-6700

EC Pin

Debug Pin Name

3.3V_1
GND0
1.5V_1
UIM_PWR
UIM_DATA
UIM_CLK
UIM_RESET
UIM_VPP

UIM_C8
UIM_C4
GND4
PERn0
PERp0
GND6
GND7
PETn0
PETp0
GND9
RESERVED_3
RESERVED_4
RESERVED_5
RESERVED_6
RESERVED_7
RESERVED_8
RESERVED_9
RESERVED_10

MINI1CLK_REQ#_R

WAKE#
RESERVED_1
RESERVED_2
CLKREQ#
GND1
REFCLKREFCLK+
GND2

29

1
3
5
7
9
11
13
15

<25,26,29> PCIE_WAKE#
<37> COEX2_WLAN_ACTIVE
<37> COEX1_BT_ACTIVE
<17> MINI1CLK_REQ#_R

R326
1

R325
1

2
2

Layout Note:
R222 and R223
close to choke
as possible to
minimize stubs.
6

Title
MINI-PCI
Size

Document Number
M-08

Date:

Monday, March 05, 2007


7

Rev
0.1
Sheet

of

24
8

51

+3.3V_RUN
R150 2
R153 2

1 100K PCIE_MCARD2_DET#
1 100K USB_MCARD2_DET#

MiniCard WWAN connector


+3.3V_RUN

+3.3V_RUN

+1.5V_RUN

J4
<24,26,29> PCIE_WAKE#
T98 PAD
T99 PAD
<17> MINI3CLK_REQ#_R

1
3
5
7
9
11
13
15

MINI3CLK_REQ#_R

<17> CLK_PCIE_MINI3#
<17> CLK_PCIE_MINI3

WAKE#
RESERVED_1
RESERVED_2
CLKREQ#
GND1
REFCLKREFCLK+
GND2

3.3V_1
GND0
1.5V_1
UIM_PWR
UIM_DATA
UIM_CLK
UIM_RESET
UIM_VPP

2
4
6
8
10
12
14
16

GND3
W_DISABLE#
PERST#
3.3VAUX1
GND5
1.5V_2
SMB_CLK
SMB_DATA
GND8
USB_DUSB_D+
GND10
LED_WWAN#
LED_WLAN#
LED_WPAN#
1.5V_3
GND11
3.3V_2

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

J15
MOLEX_48099-4000
UIM_PWR
C484
UIM_DATA
UIM_CLK
Place
1
2
UIM_RESET
UIM_VPP
100P/50V_NC

C484 close to J4

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ICH_USBP9_DICH_USBP9_D+
USB_MCARD2_DET#

C221
33P/50V/0402

41

1
2

C211
0.047U/10V/0402

C222
0.1U/10V/0402_NC

USB_MCARD2_DET# <13>

T32

27

C230
33P/50V/0402

C226
0.047U/10V/0402

C227
33P/50V/0402

+
C231
0.047U/10V/0402

1
+
C238
330U/6.3V/ESR25

C217
330U/6.3V/ESR25

MLX_67910-0002

+3.3V_RUN

29

C881
220P/50V/0402

Place caps close to connector.

ICH_SMBCLK <13,24,26>
ICH_SMBDATA <13,24,26>

PAD

+3.3V_RUN

+1.5V_RUN

WWAN_RADIO_DIS# <29>
SB_WWAN_PCIE_RST# <12>

MINI3CLK_REQ#_R

PLTRST1# <12,24,26>

PCI-Express TX and RX direct to connector

0_0402_NC
2
+3.3V_RUN

PCIE_MCARD2_DET#

<12> PCIE_MCARD2_DET#

R141
1

<12> PCIE_TX1<12> PCIE_TX1+

0_0402
2

<12> PCIE_RX1<12> PCIE_RX1+

UIM_C8
UIM_C4
GND4
PERn0
PERp0
GND6
GND7
PETn0
PETp0
GND9
RESERVED_3
RESERVED_4
RESERVED_5
RESERVED_6
RESERVED_7
RESERVED_8
RESERVED_9
RESERVED_10

R138
1

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

10/4 EMI agree to change P/N


Place C383, C367 close to JSIM1
ESD1

VPP

UIM_VPP

DATA

UIM_DATA

C383
100P/50V_NC

SUY_254020MA006H555ZL

C485
33P/50V/0402

SRV05-4.TCT

UIM_VPP
UIM_PWR
UIM_DATA

6
5
4

UIM_PWR
L26

C510
100P/50V_NC

2
C367
100P/50V_NC

1
2

CLK

C478
33P/50V/0402

6
5
4

C498
33P/50V/0402

C475
33P/50V/0402

RST

1
2
3

ICH_USBP9_DICH_USBP9_D+

C228
1U/10V/0603

1
4

Note: Place caps on UIMlines close to WWAN connector

9/27 Change PN

2
3

ICH_USBP9- <12>
ICH_USBP9+ <12>

DLW21SN900SQ2B_NC

UIM_CLK

UIM_CLK

UIM_RESET

1
2
3

GND

VCC

UIM_RESET

JSIM1
UIM_PWR

R140
1

0_0402
2

R139
1

0_0402
2

Layout Note:
R139 and R140
close to choke
as possible to
minimize stubs.

Update FP
Place as close as possible to WWAN connector
D

QUANTA
COMPUTER

Title
WWAN

Size

Document Number
VC-08B

Date:

Monday, March 05, 2007


7

Rev
0.1
Sheet

of

25
8

51

EXPRESS+MDC
+3.3V_SUS
CON3

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

ICH_USBP6ICH_USBP6+
CPUSB#

<13,24,25> ICH_SMBCLK
<13,24,25> ICH_SMBDATA
+1.5V_CARD
<24,25,29> PCIE_WAKE#
+3.3V_CARDAUX

CARD_RESET#

+3.3V_CARD
<17> CARD_CLK_REQ#
<29> EXPRCRD_PWREN#
<17> CLK_PCIE_EXPCARD#
<17> CLK_PCIE_EXPCARD
<12> PCIE_RX4<12> PCIE_RX4+
<12> PCIE_TX4<12> PCIE_TX4+

GND0
USBUSB+
CPUSB#
RSV0
RSV1
SMBCLK
SMBDATA
+1.5VCARD0
+1.5VCARD1
WAKE#
+3.3VAUX
PERST#
+3.3VCARD0
+3.3VCARD1
CLKREQ#
CPPE#
REFCLFREFCLK+
GND1
GND2
PERn0
PERp0
GND3
PETn0
PETp0
GND4

IAC_SDATAOUT
RSV2
RSV3
+3.3VMDC
GND5
GND6
IAC_SYNC
GND7
IAC_SDATAIN
GND8
IAC_PESET#
IAC_BITCLK
GND9

MDC I/F

<12> ICH_USBP6<12> ICH_USBP6+

Express card I/F

28
29
30
31
32
33
34
35
36
37
38
39
40

ICH_AZ_MDC_SDOUT

ICH_AZ_MDC_SYNC

<11>

ICH_AZ_MDC_SDIN1

<11>

ICH_AZ_MDC_BITCLK

<11>

ICH_AZ_MDC_RST1#

+1.5V_CARD Max. 650mA, Average 500mA.


+3V_CARD Max. 1300mA, Average 1000mA.

+1.5V_RUN

+3.3V_RUN

+3.3V_SUS

AUXIN
3.3VIN_0
3.3VIN_1
1.5VIN_0
1.5VIN_1

R477 100K
2
1

+3.3V_SUS

R475 0_NC
1
2

<29> EXPRCRD_STDBY#
<12,24,25> PLTRST1#

Update PN

+3.3V_CARDAUX

U33
17
2
4
12
14

Fox_QT100406-5101-9F

<11>

AUXOUT
3.3VOUT_0
3.3VOUT_1
1.5VOUT_0
1.5VOUT_1

+3.3V_CARD

+1.5V_CARD

15
3
5
11
13
+3.3V_SUS

ExpressSwitch
20
1
6

SHDN#
STBY#
SYSRST#

16
7

NC
GND0

PERST#
CPPE#
CPUSB#
OC#

8
10
9
19

RCLKEN

18

CARD_RESET#
EXPRCRD_PWREN#
CPUSB#

R480
R474

2
2

1 100K
1 100K

www.kythuatvitinh.com
R184
1

Please the cap


near pin 2 & 4
(3.3VIN).

Please the cap


near pin 17
(AUXIN).

C606
0.1U/10V

C607
0.1U/10V

+1.5V_CARD

Please the cap


near pin 15
(AUXOUT).

C603
0.1U/10V

Please the cap


near pin 3 & 5
(3.3VOUT).

Please the cap


near pin 12 &
14(1.5VIN).

C605
0.1U/10V

+3.3V_CARD
1

1
2

C604
0.1U/10V

+3.3V_CARDAUX
1

+3.3V_SUS

+3.3V_RUN

+1.5V_RUN
1

R5538D001-TR-F

C602
0.1U/10V

Please the cap


near pin 11 &
13(1.5VOUT).

Q23
BSS138_NL_NC

ICH_AZ_MDC_RST1#

1
2

<11> ICH_AZ_MDC_RST#

+5V_SUS

R185
100K_NC

R188
10K_NC
<34> MDC_RST_DIS#

NOTE : MDC DISABLE


If platform requires MDC disable,populate this circuit.
If MDC disable isn't required, connect ICH_AZ_MDC_RST# directly to
JMDC connector.

QUANTA
COMPUTER

Title

ExpressCard/SmartCard

Size

Document Number
M-08

Date:

Monday, March 05, 2007


7

Rev
0.1
Sheet

of

26
8

51

PJP1

L6

U26

USB_SIDE_PWR

EN1#

OUT1
OC1#

7
8

EN2#

OUT2
OC2#

6
5

R9
1

R8
1

JUSB3
UB1112C-TB212-7F
+
C32
150U/6.3V/ESR45

C31
.1U/10V/0402

ICH_USB_P1ICH_USB_P1+

L8
1
4

<12> ICH_USBP0+
<12> ICH_USBP0-

TPS2062DR

C344
.1U/25V/0603

2
3

ICH_USB_P0+
ICH_USB_P0-

DLW21SN900SQ2B_NC

Each channel is 1A
2

1
2
3
4

A_VCC
A_DATAA_DATA+
A_GND

5
6
7
8

B_VCC
B_DATAB_DATA+
B_GND

USB_OC0_1# <12>
1

C17
10U/10V_NC

USB_SIDE_PWR

GND

DLW21SN900SQ2B_NC

IN

R14
1

R15
1

ICH_USB_P0ICH_USB_P0+

1
C12
.1U/10V/0402

<29> USB_SIDE_EN#

ICH_USB_P1ICH_USB_P1+

+
C352
150U_NC

2
3

1
4

<12> ICH_USBP1<12> ICH_USBP1+

2
FS1
455/5A_NC
2

+5V_ALW

USB_OCP 0/1

C349
.1U/10V/0402

SHIELD1
SHIELD2
SHIELD3
SHIELD4

9
10
11
12

Right Side
2

www.kythuatvitinh.com
L1

OUT1
OC1#

7
8

EN2#

OUT2
OC2#

6
5

C341
10U/10V_NC

TPS2062DR

Each channel is 1A

USB_OC2_3# <12>

C345
.1U/25V/0603

R1
1

R3
1

C339
.1U/10V/0402

ICH_USB_P3ICH_USB_P3+

1
2
3
4

A_VCC
A_DATAA_DATA+
A_GND

5
6
7
8

B_VCC
B_DATAB_DATA+
B_GND

L2

1
4

<12> ICH_USBP2+
<12> ICH_USBP2-

C1
150U/6.3V/ESR45

EN1#

USB_BACK_PWR

2
3

ICH_USB_P2ICH_USB_P2+

DLW21SN900SQ2B_NC
R4
1

R2
1

ICH_USB_P2+
ICH_USB_P2-

C338
150U_NC

GND

JUSB1
UB1112C-TB213-7F

IN

1
2

1
2

USB_BACK_PWR

U25

<29> USB_BACK_EN#

C343
.1U/10V/0402

ICH_USB_P3ICH_USB_P3+

DLW21SN900SQ2B_NC

FS2
455/5A_NC
2

2
3

+5V_ALW

1
4

<12> ICH_USBP3<12> ICH_USBP3+

PJP13

USB_OCP 2/3

C340
.1U/10V/0402

SHIELD1
SHIELD2
SHIELD3
SHIELD4

9
10
11
12

Rear Side

2
2

Gilligan Only

ESD Protect
Place ESD diodes as
close as USB connector.

+5V_ALW
JUSB2

U3
ICH_USB_P1- 1
2
ICH_USB_P1+ 3

I/O I/O
VN VP
I/O I/O

6
5
4

8
7
6
5
4
3
2
1

ICH_USB_P0ICH_USB_P0+

USB_SIDE_PWR

<29> USB_BACK2_EN#
<12> USB_OC8#

SRV05-4

<12> ICH_USBP8+
<12> ICH_USBP8-

Place ESD diodes as


close as USB connector.

USB_BACK2_EN#
USB_OC8#
ICH_USBP8+
ICH_USBP8-

53398-0819-8P-R

U1
ICH_USB_P3- 1
2
ICH_USB_P3+ 3

I/O I/O
VN VP
I/O I/O

6
5
4

ICH_USB_P2ICH_USB_P2+

MLX_ 53398-0871
USB_BACK_PWR

SRV05-4

USB8 for back port


4

Title

QUANTA
COMPUTER
USB & Flash

Size

Document Number
FM1

Date:

Monday, March 05, 2007

Rev
0.1
Sheet
E

27

of

51

NoniAMT

12
+3.3V_ALW

2
4
6
8

+5V_RUN

ALW_PWRGD_3V_5V

CLK_KBD
DAT_KBD
CLK_DOCK
DAT_DOCK

NoniAMT

CLK_PCI_5025

C426
3P/50V

<24> 8051_RX
<24> 8051_TX

CLK_KBD
DAT_KBD
CLK_DOCK
DAT_DOCK
8051_RX
8051_TX

GPIO94/IMCLK
GPIO95/IMDAT
(10)
KCLK
KDAT
GPIOA6/EMCLK
GPIOA7/EMDAT
GPIO20/PS2CLK/8051RX
GPIO21/PS2DAT/8051TX

+3.3V_ALW

R143
100K_0402

ALWON

AB1B_CLK/GPIOA4
AB1B_DATA/GPIOA2
AB1A_CLK
AB1A_DATA

8
7
6
5

LCD_SMBCLK
LCD_SMBDAT
DOCK_SMBCLK
DOCK_SMBDAT

GPIO11/AB2_DATA
GPIO12/AB2_CLK
GPIO13/AB1G_DATA
GPIO14/AB1G_CLK
GPIO87/AB1C_DATA
GPIO86/AB1C_CLK
GPIO85/AB1D_DATA
GPIO84/AB1D_CLK
GPIO93/AB1F_DATA
GPIO92/AB1F_CLK
GPIO91/AB1E_DATA
GPIO90/AB1E_CLK

93
94
95
96
111
112
9
10
97
98
99
100

GPIO82/FAN_TACH3
GPIO16/FAN_TACH2
GPIO15/FAN_TACH1

43
42
41

OUT2/PWM3
OUT9/PWM2
OUT11/PWM1
OUT10/PWM0

48
47
46
45

nEC_SCI/SPDIN2
SGPIO45/MSDATA/SPDOUT2
SGPIO44/MSCLK/SPCLK2
SGPIO46/SPDIN1
SGPIO47/SPDOUT1
SGPIO31/TIN1/SPCLK1

66
55
54
69
68
67

SYSOPT0/SGPIO32/LPC_TX
SYSOPT1/SGPIO33/LPC_RX

70
71

SGPIO40
SGPIO41
SGPIO42
SGPIO43

91
90
89
4

SGPIO35
SGPIO36 (SFPI_EN)
SGPIO37
GPIO96/TOUT1
OUT7/nSMI

1
2
3
52
11

POWER
(6)

C432
0.1U/10V
2
R156
10K_0402

<31,34> POWER_ SW_IN0#

120
119
126
127
128
118

ALWON
POWER_ SW_IN2#/GPIO23
POWER_ SW_IN1#/GPIO22
POWER_ SW_IN0#
ACAV_IN
SWITCH BGPO0/GPIOA5

ALWON <44>
SNIFFER_PWR_SW#

INSTANT_ON_SW#
MAIN_PWR_SW#

MAIN_PWR_SW#

C237
1U/10V/0603

<33>
+RTC_CELL

ACAV_IN <18,34,40>
T18 PAD

SNIFFER_RTC_GPO

GPIO
(36)

R144
100K_0402

LCD_SMBCLK <18>
LCD_SMBDAT <18>
1

INSTANT_ON_SW#
C236
1U/10V/0603

PBAT_SMBDAT <40,41>
PBAT_SMBCLK <40,41>
+5V_ALW

1.5V_RUN_ON <43>
1.25V_RUN_ON <42>
THRM_SMBDAT <34>
THRM_SMBCLK <34>

THRM_SMBDAT
THRM_SMBCLK
R348 2
2.2K_NC

2
R147
10K_0402

<31> INSTANT_POWER_SW#
1.8V_RUN_ON <39>
LCDVCC_TST_EN <18>

AMT_SMBDAT
AMT_SMBCLK
PBAT_SMBDAT
PBAT_SMBCLK
SBAT_DH_SMBDAT
SBAT_DH_SMBCLK

IMVP_PWRGD <13,38,45>
+3.3V_RUN
FAN1_TACH <34>

R338 1
2 0
AUX_EN_WOWL
3.3V_SUS_ON

DOCK_SMBCLK

R374 8.2K_NC
2
1

DOCK_SMBDAT

R393 8.2K_NC
2
1

IMVP_VR_ON <45>
AUX_EN_WOWL <24>
3.3V_SUS_ON <39>
BREATH_LED# <37>

+3.3V_ALW

LCD_SMBCLK

8.2K R373
2
1

LCD_SMBDAT

8.2K R385
2
1

PBAT_SMBDAT

R329 2.2K
2
1

PBAT_SMBCLK

R339 2.2K
2
1

SBAT_DH_SMBDAT

R384 2.2K
2
1

SBAT_DH_SMBCLK

R372 2.2K
2
1

NC

R238

Pin24 of 5025

NC

NC

LOM_LOW_PWR#
LOM_CABLE_DETECT

C474
2

Refer to UMA
ref pg 32.
Refer to UMA
ref pg 32.
Refer to UMA
ref pg 32.

NC

NC

2 10K

+3.3V_ALW

MEC_VCC_PLL

1
MEC5025_XTAL1

1
2

32.768KHZ

D28
CH501H_NC
ALWON 1

104

VCC_PLL

101

VSS_PLL

2 1

R308
10K_NC

R309
10K_NC C423
4.7U/6.3V_NC
2
1

Q33
MMBT3906_NL_NC

C436
22P/50V

113
88
74
51
26

POWER PLANES
(9)

SFPI_EN

T120 PAD
EC_32KHZ <29>
RUNPWROK <18,29,38,45>
RESET_OUT# <38>
T77 PAD

MEC_TEST_PIN

R318
0

Populate
for flash
corruption
issue.

+3.3V_ALW

+3.3V_ALW

Debug Serial Port


Flash Recovery Port.

+3.3V_ALW

R378
1K

Flash Recovery.

RP36
4P2R-4.7K

THRM_SMBCLK
THRM_SMBDAT

R319
100K

Low =
Write Protected.
FWP#

Flash Write
Protect bottom
4K of internal
bootblock flash.

R320
100K_NC

R294
1

0_NC
2

R80
1M

JDEBUG1
VR_CAP

Q31
2N7002W-7-F_NC

2
R295 100K_NC
1
2

VSS
VSS
VSS
VSS
VSS

For MEC5025 Rev.C: C685=22uF and


populate workaround circuit.
For MEC5025 Rev.D: C685=4.7uF and
depopulate workaround circuit.

AGND

VR_CAP

125

R376
1K_NC
C

BAT2_LED# <37>
BAT1_LED# <37>

FWP#
0.9V_DDR_VTT_PWRGD

MEC5025
LQFP128-16X16-4-JM6
Rev 0.01 (11/09/05)

+3.3V_ALW

W2

1
1
C467
22P/50V

C427
0.1U/10V

R303
100K_NC

R364
0

22

MEC_AGND

115
114
84
73
117
49
53
72

2
L33
BLM11A121S

MEC5025_XTAL2

VR_CAP

2
1
L23
BLM11A121S
1
2
L34
BLM11A121S

External Work Around


Circuit.

32KHz Clock.

4.7U/10V
1

LOM_SUPER_IDDQ

R347 1

nPWR_LED
nBAT_LED
nFWP
GPIOA3/WINDMON
GPIO83/32KHZ_OUT
PWRGD
nRESET_OUT/OUT6
TEST_PIN

2
4

NC

Pin37 of 5025

CLOCK
(3)

XTAL1
XTAL2
XOSEL

1
3

Pin25 of 5025

1.05V_1.25V_M_PWRGD

122
124
123

5
4
3
2
1
MLX_53398-0571_NC

SIO_SLP_M#

MEC5025_XTAL1
MEC5025_XTAL2
MEC5025_XOSEL

MISCELLANEOUS
(8)

NC

BC
(3)

+3.3V_ALW

1 = Enabled.
0 = Disabled

Pin24 of 5025

BC_CLK
BC_DAT
BC_INT#

M_ON

87
86
85

<29> BC_CLK
<29> BC_DAT
<29> BC_INT#

11
0.9V_DDR_VTT_ON <42>
SIO_EXT_SMI# <13>

R316
1

R315
10K

0_NC
2

R81
10K
1

NC

SNIFFER_YELLOW#

GPIO80
GPIO81

<13> SIO_PWRBTN#
<33> SNIFFER_YELLOW#

INVERTER_CBL_DET# <33>
AUX_LCD_CBL_DET# <33>
SIO_SPI_CS# <12>
+3.3V_ALW
2
LOM_SMB_ALERT# <13>
0_NC

109
110

10

HOST/8051 SPI
(8)

FLCLK
FLDATAIN
FLDATAOUT

HOST_DEBUG_TX <24>
HOST_DEBUG_RX <24>
+3.3V_ALW

103
106
108

R317 2
1 1M
LCD_CBL_DET
INVERTER_CBL_DET#
AUX_LCD_CBL_DET#
SIO_SPI_CS#
R369 1
2 100K
1
SFPI_EN
R337
DOCK_SMB_ALERT#

<30> EC_FLASH_SPI_CLK
<30> EC_FLASH_SPI_DIN
<30> EC_FLASH_SPI_DO

BEEP
1.25V_GFX_PCIE_ON
DEBUG_ENABLE#

HSTCLK
HSTDATAIN
HSTDATAOUT

SIO_EXT_SCI# <13>
PS_ID <41>
SIO_RCIN# <11>
BEEP <32>

102
105
107

SIO_EXT_SCI#
PS_ID

<12> ICH_EC_SPI_CLK
<12> ICH_EC_SPI_DIN
<12> ICH_EC_SPI_DO

POWER/LPC BUS
(9)

Pin23 of 5025

LRESET#
PCICLK
LFRAME#
LAD0
PCI
LAD1
LAD2
LAD3
CLKRUN#
SER_IRQ

ICH_RSMRST#

57
58
59
60
61
62
63
64
56

CLK_PCI_5025

3.3V_M_PWRGD

Non-AMT
Broadcom
NC

SGPIO34/A20M
OUT5/KBRST

75
76
77
78
79
80
81
82

MEC5025_VCC0

21
44
65
83
116

C434
0.1U/10V

AMT
Intel
Pin15 of 5025

Net & Part

92
50

121

VCC1
VCC1
VCC1
VCC1
VCC1

C469
0.1U/10V

C145
0.1U/10V

1
2

C421
0.1U/10V

<6,12> PLTRST#
<17> CLK_PCI_5025
<11> LPC_LFRAME#
<11> LPC_LAD0
<11> LPC_LAD1
<11> LPC_LAD2
<11> LPC_LAD3
<13,20,35> CLKRUN#
<13,20> IRQ_SERIRQ

Place these caps close to MEC5025.

SNIFFER_GREEN#

POWER PLANES
(6)

ACCESS BUS
(4)

KSI7/GPIO19
KSI6/GPIO17
KSI5/GPIO10
KSI4/GPIO9
KSI3/GPIO8
KSI2/GPIO7/BC_A_INT#
KSI1/GPIO6/BC_A_DAT
KSI0/SGPIO30/BC_A_CLK

VCC0

www.kythuatvitinh.com

C437
10U/6.3V

+3.3V_ALW

<38,39> SUS_ON
<18,38,39> RUN_ON
<41> AC_OFF
T78 PAD
<31> BC_A_INT#
<31> BC_A_DAT
<31> BC_A_CLK

<31> CLK_TP_SIO
<31> DAT_TP_SIO

Place close
to pin 58.

1 2
2

GPIO4/KSO14
KSO13/GPIO18
KSO12/OUT8
KSO11/GPIOC7
KSO10/GPIOC6
KSO9/GPIOC5
KSO8/GPIOC4
KSO7/GPIO3
KEYBOARD/MOUSE
KSO6/GPIO2
(26)
KSO5/GPIO1
KSO4/GPIO0
KSO3/GPIOC3
KSO2/GPIOC2
KSO1/GPIOC1
KSO0/GPIOC0

33
SUS_ON
34
RUN_ON
35
36
RSV_1.05V_1.25V_M_PWRGD 37
38
39
40

<11> SIO_A20GATE
<33> SNIFFER_GREEN#

10

R333
33

10

12
13
14
2 0_NC15
16
EC_CPU_PROCHOT# 17
18
19
20
ICH_RSMRST#
23
RSV_M_ON
24
RSV_SIO_SLP_M#
25
DDR_ON
27
28
ALW_PWRGD_3V_5V 29
30
31
32
AUX_ON

C470
0.1U/10V_NC

+RTC_CELL

R345
2

<32> AUD_AMP_MUTE#
<42> 1.8V_SUS_PWRGD
<3> EC_CPU_PROCHOT#
T106 PAD
<6,13> ICH_CL_PWROK
T86 PAD
<13> ICH_RSMRST#
T87 PAD
T93 PAD
<42> DDR_ON
<31> TP_DET#
<44> ALW_PWRGD_3V_5V
<13> SIO_SLP_S3#
13 <13> SIO_SLP_S5#
<39> 3.3V_RUN_ON

1
3
5
7

RP32
8P4R-4.7K

SIO_S4_STATE#
R371
100K_0402_NC

MEC5025 EC-08
KSO17/GPIOA1/AB1H_DATA
KSO16/GPIOA0/AB1H_CLK
128 PIN VTQFP
GPIO5/KSO15

ATI_Intel
R538 1

12

+RTC_CELL

LCD_CBL_DET

46

Place cap
close to pin
121.

1 10K DOCK_SMB_ALERT#
USIO2

21

1 RUN_ON
100K_NC
R343 2
1AUX_EN_WOWL
0
R507 2
1 ATI_Intel

DDR_ON

R355 2

21

39

2.7K/F

LCD_CBL_DET_L R83 1
2 100K
R82 2
1 200K
<17> CKG_SMBDAT
<17> CKG_SMBCLK

<33> LCD_CBL_DET_L

R379 2

SUS_ON

11

100K

10K_NC SIO_SPI_CS#
+3.3V_ALW
100K TP_DET#
100K INVERTER_CBL_DET#
R386 2
100K AUX_LCD_CBL_DET#

R358 2

1
2
2
2

2.7K/F

2
1
1
1

+3.3V_ALW
R390
BC_DAT
R370
2100K
BC_A_DAT
100K_NC
R322
2
R321

+3.3V_ALW
R126 1
R417 1

8051_RX
8051_TX

Title
DEBUG_ENABLE#

Not Stuff 0 ohm when doing


Flash recovery.
4

DELL CONFIDENTIAL/PROPRIETARY

Ultra I/O Controller MEC5025


Size

Document Number
M-08

Date:

Monday, March 05, 2007


7

Rev
0.1
Sheet

of

28
8

51

Update to 5021
Depopulate R529, R530, R531, R532, R533, R534, R535, R536, R92, R97, C142, C133, C137, C141, C179, C165, C172, L21
Populate R537, C879.

USIO1

+3.3V_ALW

2
4
6
8

<27> USB_BACK2_EN#

SBAT_PRES#
PWRUSB_OC#

1
3
5
7

PWRUSB_OC#

DBAY_MODPRES#

HP_NB_SENSE
DOCK_HP_MUTE#
SPDIF_SHDN

T51 PAD
<32> NB_MUTE#

8P4R-10K

DOCK_SMB_PME#
DOCKED
QBUFEN#
DOCK_PWR_EN

11
R487 2
R116 1

+3.3V_ALW

R349 1
R359 1

1 100K
2 100K

PLATFORM_BID
MODPRES#
DOCKED
PANEL_BKEN

2 100K
2 100K

<40> ADAPT_OC
<40> ADAPT_TRIP_SEL
<3,13> ITP_DBRESET#
<41> PS_ID_DISABLE#

ITP_DBRESET#
PANEL_BKEN

<18> PANEL_BKEN
<37> M_LED_BK#

SW_LED
SUB_SHDN_ON_BATT
TOUCH_PAD_LED#
LOW_LIGHT
CAM_IMG_CAPTURE
MIC_SWITCH
LID_CL_PRES#

R120 100K_0402
1
2 IMVP6_PROCHOT#
+3.3V_RUN
+5V_ALW

2
R548

1
10K

DOCK_SMB_PME#

39

1
2
3
4
5
84
83
6

GPIOE[0]
GPIOE[1]
GPIOE[2]
GPIOE[3]
GPIOE[4]
GPIOE[5]
GPIOE[6]
GPIOE[7]

118
117
116
115
112
111
110
109

GPIOF[0]
GPIOF[1]
GPIOF[2]
GPIOF[3]
GPIOF[4]
GPIOF[5]
GPIOF[6]
GPIOF[7]

127
128
9
10
11
12
13
14

R92 2
R532 1

1 12K/F_0402_NC
2 0_NC

R533 1

2 0_NC

R534 1

2 0_NC

USBDP2/GPIOIK[0]
USBDN2/GPIOIK[1]
USBDN3/GPIOIK[2]
USBDP3/GPIOIK[3]
VDDA33_2/GPIOIK[4]
USBDP4/GPIOIK[5]
USBDN4/GPIOIK[6]
VSS_2/GPIOK[7]

15
16
18
19
20
21
22
23

GPIOs

R535 1

0_NC
0_NC

R536 1

VDD18

R78
0_NC VDDA18PLL
0_NC VDDA33
10K_0402_NC

2 0_NC

ECE5011_CTAL1
C147 33P_NC

+3.3V_ALW
2 1K_0402

Y3
24MHz_NC

R85
1M_NC
ECE5011_CTAL2

C140 33P_NC

+3.3V_ALW

T110 PAD
T111 PAD

VDDA33

VDDA33

T112 PAD Route


T113 PAD USIO2

R167 to
very short

T114 PAD
T115 PAD
T116 PAD
T117 PAD

+3.3V_ALW
L21

T118 PAD
T119 PAD

2 0_NC

VDDA33

C179
C165
C172
.1U/10V/0402_NC .1U/10V/0402_NC .1U/10V/0402_NC

2
BLM11A20_NC

C182
10U/10V/0805

C143
.1U/10V/0402

C209
.1U/10V/0402

+3.3V_ALW

C210
.1U/10V/0402

C439
.1U/10V/0402

VSS_1
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24

CAP_LDO

2 0

GPIOH[0]
GPIOH[1]
GPIOH[4]
GPIOH[5]
GPIOH[6]
GPIOH[7]

Place C879 close


to USIO2.8

.1U/10V/0402

24
25
26
27
32
33

C879

C213
.1U/10V/0402

86

R569
2

<18,28,38,45> RUNPWROK

0_NC

1RUNPWROK_R

PAD T31
<28> EC_32KHz

Reset BID
RUNPWROK_R

PWRGD

35

TEST_PIN

96

32KHz_IN

46

NC

BC
MISCELLANEOUS

C141
.1U_NC

C142
C133
.1U/10V/0402_NC 4.7U/10V/0805_NC

+3.3V_ALW

ECE5021-NU

R129
100K_0402

Update P/N

C137
4.7U/10V/0805_NC

BC_INT#
BC_DAT
BC_CLK

SIO Reset

VDDA18PLL

58
59
60

VSS

GPIOH[2]
GPIOH[3]

106
107

VDD18

<28> BC_INT#
<28> BC_DAT
<28> BC_CLK

OUT65

C435
4.7U/10V/0805

LOM_CABLE_DETECT

105

17
36
37
38
39
40
41
44
45
47
48
49
50
51
52
53
54
55
56
64
72
87
121

<25> WWAN_RADIO_DIS#
Board Revision
SST (X00)
Pre-PT (X01)
PT (X02)
ST (X03)
QT (A00)
RAMP-2 (A01)

VCC1_0/VCC1_1
VCC1_1/VCC1_2
VCC1_2/VCC1_3
VCC1_3/VCC1_4
VCC1_4/VCC1_5
VCC1_5/VCC1_6

CIRRX <31>

VDDA33

IMVP6_PROCHOT#

<18> LCD_TST

BID0
0
1
0
1
0
1

GPIOG[0]
GPIOG[1]
GPIOG[2]
GPIOG[3]
GPIOG[4]
GPIOG[5]
GPIOG[6]
GPIOG[7]

R537 1
34
42
43
57
85
108

1.05V_RUN_ON <43>

<33> WIRELESS_ON/OFF#
<37> BT_RADIO_DIS_DC#
<26> EXPRCRD_PWREN#
<26> EXPRCRD_STDBY#
<45> IMVP6_PROCHOT#
<38> 5V_3V_1.8V_1.25V_RUN_PWRGD

BID1
0
0
1
1
0
0

88
89
90
91
92
93
94
95

LID_CL_SIO#

PLATFORM_BID

VDDA33_0/VCC1_0

61
62
113
114

LID_CL_SIO#

R130
1

10
2

LID_CL#

LID_CL# <31>

R568
0

R67
10K_NC

<11,37> LED_MASK#
<23> PLATFORM_BID
<13> SIO_EXT_WAKE#
<12> ICH_PME#
<13> ICH_PCIE_WAKE#
<24> WLAN_RADIO_DIS#

POWER

GPIOD[1]/CIRTX
GPIOD[2]/CIRRX
CIRTX
CIRRX

50

SC_DET#

CIRCC

BID0
BID1
CHIPSET_ID1
VGA_IDENTIFY

<35> LOM_LOW_PWR#

1
2

R66
10K_0402

R68
10K_0402_NC

1
2
1

GPIOD[0]

RBIAS/GPIOIJ[0]
VSS_25/GPIOIJ[1]
USBDP0/GPIOIJ[2]
USBDN0/GPIOIJ[3]
VSS_0/GPIOIJ[4]
USBDN1/GPIOIJ[5]
USBDP1/GPIOIJ[6]
VDDA33_1/GPIOIJ[7]

USB

BID0
BID1
CHIPSET_ID1
VGA_IDENTIFY
Rsvd_LOM_IDDQ
Rsvd_LOM_TPM_EN#

2
2

R69
R65
10K_0402_NC 10K

R77
R70
10K_0402_NC 10K

BID2
0
0
0
0
0
0

74

R539 1
2
R529 1
2
ECE5011_CTAL2
ECE5011_CTAL1
R530 1
2
R531 1
2
R97 1
2

<34> ATF_INT#

50

VGA
1
1
1
1
1
1

GPIOC[0]
GPIOC[1]
GPIOC[2]
GPIOC[3]
GPIOC[4]
GPIOC[5]
GPIOC[6]
GPIOC[7]

119
120
122
123
124
125
126

www.kythuatvitinh.com
IRMODE

+3.3V_ALW

R76
10K

76
75
67
68
69
70
71
73

VCC1_6/GPIOI[1]
VDD18(CAP)/GPIOI[2]
XTAL2/GPIOI[3]
XTAL1/CLKIN/GPIOI[4]
VDDA18PLL(CAP)/GPIOI[5]
VDDA33PLL(CAP)/GPIOI[6]
ATEST(VCC1)/GPIOI[7]

GPIOB[0]
GPIOB[1]
GPIOB[2]
GPIOB[3]
GPIOB[4]
GPIOB[5]
GPIOB[6]
GPIOB[7]

HDDC_EN <23>
MODC_EN <23>

RP14

65
66
82
81
80
79
78
77

17

<27> USB_SIDE_EN#

MODPRES#
DBAY_MODPRES#

EOL

63
28
29
30
31

<20,35> SYS_PME#
<24,25,26> PCIE_WAKE#
<27> USB_BACK_EN#

GPIOD[3]/VBUS_DET
GPIOD[4]/OCS1_N
GPIOD[5]/OCS2_N
GPIOD[6]/OCS3_N
GPIOD[7]/OCS4_N

8P4R-10K

ECE5021
128 Pin
VTQFP

GPIOA[0]
GPIOA[1]
GPIOA[2]
GPIOA[3]
GPIOA[4]
GPIOA[5]
GPIOA[6]
GPIOA[7]

SBAT_PRES#
CHG_PBATT
CHG_SBATT
PBAT_DSCHG
SYS_PME#
PCIE_WAKE#

97
98
99
100
101
102
103
104

<41> PBAT_PRES#

PCIE_WAKE#
SYS_PME#

1
3
5
7

2
4
6
8

RP15
+3.3V_ALW

C218
0.047U/10V

57

Title

QUANTA
COMPUTER
SIO (GPIO/BC/USB/CIRR)

Size

Document Number
FM1

Date:

Monday, March 05, 2007

Rev
0.1
Sheet
E

29

of

51

16Mbit (2M Byte), SPI

RTC BATTERY
+3.3V_SUS

1
R105
10K

R125
10K

D2 SDMK0340L-7-F
U6

55

C896
22P/50V_NC

WP#

VSS

1
5

RTC_BAT_DET#
+RTC

H-E276X315D126p2-4

H-C276D98p2-4

TH21

TH18
H-C276D126p2-4

H-C276D126p2-4

CPU

TH14

H-TC315BC236D102p2-4

TH15

H-TC315BC236D102p2-4

H-TC315BC236D102p2-4

TH10

TH9

H-TC217BC256D126p2-4

11/28 EMI request change back to PTH

H-TC354BE354X354D126p2-4 1

10/4 EMI request change to NPTH

TH13

H-TC217BC236D126p2-4

TH16
H-TC236BE354X354D126p2-3
1

TH6

TH2

10/18 EMI request

H-C276D98p2-4

H-E354X354D126p2-4 1

TH19
2

H-TC354BE354X354D126p2-4 1

TH20
2

H-TC354BE354X354D126p2-4
1

TH3
2

H-TC354BE354X354D126p2-4 1

TH5

www.kythuatvitinh.com
3

TH12
2

H-TC354BE354X354D126p2-4
1

RTC-BATTERY_NC
MOLEX_53261-0371

SATA BTB Conn. Nut -- Only for Gilligan

TH23
2

TH17

C43
1U/25V

C42
1U/25V

Gfx
3

1
2
3

2
2

2
5

SHDN

MAX1615_NC

TH11

H-E354X354D126p2-4

C50
2.2U/6.3V

<11> RTC_BAT_DET#
2+RTC_1 1
2
R20
1K

TH22

H-TC256BE354X354D126P2-4

J2

2M : AKE28FP0K07

TH4
2

TH1
H-E354X354D126p2-4

GND

IN

D1 SDMK0340L-7-F

SST25VF016B

22P : CH02206JB08

OUT
5/3#

HOLD#

Non-iAMT

C201
0.1U/10V

CE#
SCK
SI
SO

VDD

2 15
2 15
2 15

3
4
1

U14
1
6
5
2

R127 1
R128 1
R101 1

SPI_CS0#
EC_FLASH_SPI_CLK
EC_FLASH_SPI_DO
EC_FLASH_SPI_DIN

+PWR_SRC

+3.3V_RTC_LDO

+RTC_CELL

Layout Note:
Place R471 within 500 mils from SPI flash.
Place R498 & R534 within 500 mils of the
MEC5025.

Non-iAMT

<12>
<28>
<28>
<28>

H-TC315BC236D102p2-4

C634
C630
.1U/10V/0402_NC .1U/25V/0603_NC

+3.3V_RUN

C633
.1U/10V/0402_NC

+3.3V_RUN

C635
.1U/10V/0402_NC

+3.3V_RUN

C636
.1U/10V/0402_NC

+PWR_SRC

C637
.1U/10V/0402_NC

+PWR_SRC

C638
.1U/25V/0603_NC

+1.25V_RUN

C639
.1U/25V/0603_NC

+PWR_SRC

C642
.1U/10V/0402_NC

4
+3.3V_RUN

TH24
h-R36X107DR16X87PB

DSUB
TH8
h-tc217bc256d126p2-4

C388
.1U/25V/0603_NC

+DC_IN_SS

+PWR_SRC

+PWR_SRC

+5V_ALW

+5V_ALW

+5V_ALW

+5V_ALW

+5V_ALW

+5V_ALW

+5V_ALW

+PWR_SRC

+3.3V_RUN

+3.3V_RUN

+PWR_SRC

+PWR_SRC

+PWR_SRC

+PWR_SRC

+PWR_SRC

C358
.1U/25V/0603_NC

C52
C353
.1U/25V/0603_NC .1U/10V/0402_NC

C49
.1U/10V/0402_NC

C40
.1U/25V/0603_NC

C370
.1U/25V/0603_NC

C58
.1U/25V/0603_NC

C396
.1U/25V/0603_NC

+5V_ALW
+1.05V_VCCP

C391
.1U/25V/0603_NC

+1.5V_RUN
+1.05V_VCCP

C420
.1U/10V/0402_NC

TH25
h-R36X107DR16X87PB

C410
.1U/10V/0402_NC

C356
.1U/25V/0603_NC

+5V_ALW

+DC_IN_SS

TH7
h-tc217bc256d126p2-4
2

C632
.1U/25V/0603_NC

+PWR_SRC

C631
.1U/25V/0603_NC

+3.3V_RUN

+PWR_SRC

+PWR_SRC

+DC_IN_SS

+DC_IN_SS

+DC_IN_SS

+5V_ALW

+5V_ALW

+5V_ALW

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

GND

Title

GND
1

GND

PV19
PV17
PV18
PAD195X130 PAD195X130 PAD195X130

GND

PV3
PAD79x130

GND

PV11
PAD79x130

GND

PV10
PAD79x130

GND

PV5
PAD79x130

GND

PV1
PAD79x130

GND

PV6
PAD79x130

GND

PV8
PAD79x130

GND

PV2
PAD79x130

GND

PV7
PAD79x130

GND
1

GND
1

GND
1

GND
1

GND
1

GND

PV12
PV13
PV14
PV16
PV15
PV9
PAD195X130 PAD195X130 PAD195X130 PAD195X130 PAD195X130 PAD79x130

QUANTA
COMPUTER
FLASH, RTC & KC

Size

Document Number
M-08

Date:

Monday, March 05, 2007

Rev
0.1
Sheet
E

30

of

51

+3.3V_ALW

44

1
3

TP

+5V_ALW

+3.3V_ALW

2
4

RP33
4P2R-4.7K

JTP1
1
L28
1
L29

<28> DAT_TP_SIO
<28> CLK_TP_SIO

2
BLM11A601S
2
BLM11A601S

<28> TP_DET#

C248
10P/50V/0402

C247
10P/50V/0402

2
C245
10P/50V/0402

<37> M_LED_BK
<28,34> POWER_ SW_IN0#
<28> INSTANT_POWER_SW#
C244
10P/50V/0402

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

M_LED_BK
POWER_ SW_IN0#
INSTANT_POWER_SW#

www.kythuatvitinh.com
<28> BC_A_DAT

<28> BC_A_CLK
<28> BC_A_INT#
<29> LID_CL#

FOX_HS6115E-M

(Code : 4-1-1)

CIR
+3.3V_ALW
JCIR1
4
3
2
1

CIRRX <29>
1

4
3
2
1

MLX_53398-0471

C335
0.1U/10V/0402

QUANTA
COMPUTER

Title

TOUCH PAD, BULE TOOTH & FIR

Size

Document Number
M-08

Date:

Monday, March 05, 2007


7

Rev
0.1
Sheet

of

31
8

51

U34
NC7SZ08P5X_NL

C324
1U/16V

14
13

PVSS
CPVSS

+5V_SPK_AMP

2
1

+VDDA

C615
1U/10V

C319
0.1U/10V

C617
1U/10V

Layout Note:
Place close
U22.

C323
1U/10V

Layout Note:
Place close U22.

+5V_RUN

Layout Note:
Place close to
pin 18.

+5V_SPK_AMP

C332
1U/10V

Layout Note:
Place close to
pin 8.

C331
10U/10V

C333
0.1U/10V

C315
10U/10V

C310
1U/10V

L30
2
1
BLM21PG600SN1D

For MAX9789A,depop
C619,pop R504.

FB_60ohm+-25%_100MHz
_3A_0.05ohm DC

6dB

10dB

15.6dB

21.6dB

+VDDA

2.2K_NC
R497
0_NC

2
0_0805
1 0_0603
1 0_0603
1 0_0603
1 0_0603

R493
5.1K/F

Layout Note:
Close to U22 Pin 13.

23
24
29

AUD_MIC_IN_L
AUD_MIC_IN_R

PORT_D_L
PORT_D_R

35
36

AUD_LINE_OUT_L
AUD_LINE_OUT_R

PORT_E_L
PORT_E_R
GPIO4/VREFOUT_E

14
15
31

DOCK_HP_MUTE#

PORT_F_L
PORT_F_R
GPIO3/VREFOUT_F

16
17
30

CD_L
CD_GND
CD_R

18
19
20

49

PC_BEEP
MONO_OUT

12
32

AUD_PC_BEEP

27
33

AC97VREFI
CAP2

25
38

AVDD_25
AVDD_38

Depop R203 & pop C321 & C325 for AD1984.

26
42

DVSS
AVSS_26
AVSS_42

VREFFILT
CAP2

1
C322
10U/10V_NC

C299
R187
0.1U/10V
20K
2
1BEEP2 1

AUD_SPDIF_SHDN

C314
10U/10V

BEEP <28>

SPKR <13>

U21
74LVC1G86GW

10_NC
R200

C304
10U/10V

DELL CONFIDENTIAL/PROPRIETARY

C320
0.1U/10V_NC

Title
Azelia CODEC(STAC9205))
Size

Document Number
M-08

Date:

Monday, March 05, 2007

C304 must be 1U & Pop C320 & R200 for AD1984.


2

2 BEEP1

R190
10K

+VDDA

STAC9205

C648
4.7P/50V_NC

R194
10K

AUD_PC_BEEP

C303
1U/10V

1
C302
0.1U/16V

AUD_DMIC_IN0

R196
10K

C300
0.1U/16V
2
1
5

DVDD_CORE_1
DVDD_CORE_9
DVDD_CORE_40
DVDD_IO

+VDDA

C309
0.1U/10V

37
+VDDA

1
9
40
3

C643
1000P/50V

C321
0.1U/10V_NC

NC_43
NC_44
NC_45

Close to U22

C647
4.7P/50V_NC

C325
4.7U/10V_NC

1
2
D

+3.3V_RUN

AUD_DMIC_CLK

43
44
45

1U/10V

R253
100K

<33>

+VDDA

R203
0
1

0.1U/10V

C313

AUD_MIC_SWITCH

Q54
2N7002W-7-F

2
1

C301

10U/10V_NC

C317

PORT_C_L
PORT_C_R
VREFOUT_C

3 2

SPDIF_IN/EAPD#/GPIO0
SPDIF_OUT

47
48

+VDDA

C611
1000P/50V

AUD_EAPD#
SPDIF_OUT

AUD_HP_NB_SENSE 2
Q53
2N7002W-7-F

<19> AUD_SPDIF_OUT

Close to pin 5.
C308
0.1U/10V_NC

R204 0
2

<33> AUD_HP_NB_SENSE
AUD_EXT_MIC_L <33>
AUD_EXT_MIC_R <33>
AUD_VREFOUT_B <33>

+3.3V_RUN

3 2

21
22
28

R492
20K/F

PORT_B_L
PORT_B_R
VREFOUT_B

DMIC_CLK
DMIC0/VOL_UP/GPIO1
DMIC1/VOL_DN/GPIO2

For tuning.
R195
47_NC

AUD_HP_OUT_L
AUD_HP_OUT_R

ICH_AZ_CODEC_SDOUT

39
41
37

46
2
4

49

1
1
CODEC_GPIO_PIN_4

STAC9205 PORT_A_L
PORT_A_R
LQFP 48PIN VREFOUT_A

R491
39.2K/F

0
0

AUD_SENSE_A
AUD_SENSE_B

R555
2
2
R556

SENSE_A
SENSE_B

AUD_DMIC_CLK
AUD_DMIC_IN0

<33> AUD_DMIC_CLK
<33> AUD_DMIC_IN0

R201
100K
13
34

HDA_BITCLK
HDA_SDI_CODEC
HDA_SDO
HDA_SYNC
HDA_RST#

C305
0.1U/10V_NC

10/18 Check package

6
8
5
10
11

U22
ICH_AZ_CODEC_BITCLK
R192 2
1 33 SDIN
ICH_AZ_CODEC_SDOUT

<11> ICH_AZ_CODEC_BITCLK
<11> ICH_AZ_CODEC_SDIN0
<11> ICH_AZ_CODEC_SDOUT
<11> ICH_AZ_CODEC_SYNC
<11> ICH_AZ_CODEC_RST#

AUD_SENSE_A
1

+VDDA

AZALIA (HD) CODEC

Close to pin 6.

EMI Request

C614
0.033U/16V

1
R501
R207 2
R189 2
R198 2
R202 2

R498

SET

GAIN

R199
100K_NC

GAIN2

2
2 1

C316
1U/10V

1
2

1
2
2

1
3

GAIN1

R193
47_NC

C619
0.033U/16V

For MAX9789A,depop
C614,pop R497.

AUD_AMP_GAIN1
AUD_AMP_GAIN2

ICH_AZ_CODEC_BITCLK

2 1

<34>

R499
100K

R197
100K

Q24
2N7002W-7-F

REGEN

2 0

AUDIO_AVDD_ON

C1425/C331 value
need to match with
C326/C290. This
value be chosen in
PT phase.

R504
0_NC

AMP_HP_EN

R496
100K_NC

<29> NB_MUTE#

+5V_SPK_AMP

VDD

+5V_SPK_AMP

Q25
2N7002W-7-F

L35
FB_600ohm+-25%_100MHz
_200mA_0.6ohm DC

+5V_SPK_AMP
+5V_SPK_AMP

www.kythuatvitinh.com

AUD_EAPD#

+VDDA
VDD

AUDIO_AVDD_ON

CODEC_GPIO_PIN_4 1

2
1

AUD_SPK_ENABLE#

28
5
21

TPA6040A4

AUD_HP_NB_SENSE_R

R545 1
R209
100K

GND_28
PGND_5
PGND_21

MLX_ 53398-0671

AUD_HP_NB_SENSE 1

R208
100K

30
8
18

C623
100P/50V_NC

C1P
C1N
CPGND

29

VDD
PVDD_8
PVDD_18

1
R563

10
12
11

VOUT

2
0_0603

1
2
3
4
5
6

SPKR_LINSPKR_RIN-

REGEN
SET

4
1

REGEN
SET

C620
C621
C622
100P/50V_NC 100P/50V_NC 100P/50V_NC

AUD_HP_JACK_L <33>
AUD_HP_JACK_R <33>

HPVDD
CPVDD

16
15

HPR

17
9

AUD_SPK_R1
AUD_SPK_R2

BIAS
SPKR_EN#
HP_EN
MUTE# REG_EN
GAIN1
GAIN2

20
19

+5V_SPK_AMP
U36
NC7SZ08P5X_NL_NC

NB_MUTE#
+5V_SPK_AMP

24
23
22
25
31
32

TPA6040A4 OUTR+
OUTRQFN 32PIN HPL

1
2
3
4
2
1 5
0_0603
6

+5V_SPK_AMP

AUD_AMP_MUTE#

HP_INL
HP_INR

AUD_SPK_L1
AUD_SPK_L2

SPEAKER_DET#

2 1U/16V

C616 1

10/18 De-pop if not necessary

27
26

6
7

R560
<11> SPEAKER_DET#
2
1
R561 2
0_0603
1
0_0603 R562

C318
10U/10V

C328
1U/10V

OUTL+
OUTL-

For MAX9789A,depop
R505,pop R506.
+5V_SPK_AMP

+5V_SPK_AMP

C625
0.1U/10V

SPKR_INL
SPKR_INR

31

R506
100K_NC

3
2

JSPK1
AUD_SPK_L1
AUD_SPK_L2
AUD_SPK_R1
AUD_SPK_R2

C327
47P/50V_NC

C330
47P/50V_NC

10/18 Change 2.2u if necessary

HP_OUT_L
HP_OUT_R
C334 1U/10V
C312
C311
1
2
AUD_SPK_ENABLE#
47P/50V_NC
47P/50V_NC
AMP_HP_EN
AUD_AMP_MUTE#
<28> AUD_AMP_MUTE#
AUD_AMP_GAIN1
AUD_AMP_GAIN2
32

1 1uF/25V/X7R/1206
1 1uF/25V/X7R/1206

SPKR_LIN+
SPKR_RIN+

LINRIN-

C326 2
C329 2

AUD_HP_OUT_L
AUD_HP_OUT_R

2 .033U/25V/X7R/1206
2 .033U/25V/X7R/1206

AUDIO_AVDD_ON 1

52

U23

C306 1
C307 1

R505
0

Update PN

INTERNAL SPEAKER AMP

AUD_LINE_OUT_L
AUD_LINE_OUT_R

Package 1206 for THD+N


performance for Vista Logo
requirements.

Rev
0.1
Sheet

of

32
8

51

Digital Microphone & Camera


Q27
SI2301BDS

+3.3V_RUN

+3.3V_RUN

STEREO MIC
LINE IN

R502
100K

C393
10U/10V/0805

1
2
3
4
5
6
7
8
9
10

53
<32> AUD_HP_NB_SENSE

+3.3V_RUN
+3V_DMIC
1

L9
BLM11A05

48

<13> CCD_VDD_ON

Q26
DTC144EUA

47K

R284
10K_0402

<32> AUD_HP_JACK_R

R564 2

<32> AUD_HP_JACK_L

R566 2

1 0_0603
SNIFFER G_R
1 0_0603
SNIFFER Y_R

C48
10U/10V/0805

To Sniffer

R503
100K

JAUDIO1
2

C403
1U/10V/0603

C385
R557
1U/10V/0603 100K

+5V_CCD

+5V_RUN

Update PN

1 0_0603_NC

SNIFFER2

11
12
13
14
15
16
17
18
19
20

R34

SNIFFER1

AUD_MIC_SWITCH
R565 2

1 0_0603

R567 2

1 0_0603

<32>

AUD_EXT_MIC_R <32>
AUD_EXT_MIC_L <32>
AUD_VREFOUT_B <32>

53

FOX_HT1310F
10/19 Update FP

Place close to Camera connector.

HT1310X-20P-RUV
47K
1

HEADPHONE
LINE OUT

+3.3V_RUN

www.kythuatvitinh.com
<28> INVERTER_CBL_DET#
<28> LCD_CBL_DET_L

49

L10

C379
150U/6.3V/ESR45

<29> WIRELESS_ON/OFF#

ICH_USB_P5ICH_USB_P5+

2
3

R26
1

C624
1U/10V

+RTC_CELL

R335
100K

(Code : 4-1-2)

C51
10U/10V/0805

C45
.1U/10V/0402

C44
.1U/10V/0402

<28> SNIFFER_PWR_SW#

R334
2

10K
1 SNIFFER2

10K
1 SNIFFER1

+3.3V_RUN

DLW21SN900SQ2B_NC
R27
1

R508
2

C55
.1U/10V/0402

MLX_53398-1271

1
4

<12> ICH_USBP5<12> ICH_USBP5+

C56
.1U/10V/0402

<32> AUD_DMIC_IN0

C54
.01U/25V/0402

C651
0.1U/10V_NC

1
2
3
4
5
6
7
8
9
10
11
12

+5V_CCD
+3V_DMIC
ICH_USB_P5+
ICH_USB_P5AUD_DMIC_CLK_R
AUD_DMIC_IN0

2
1

R509
100K

JCAMERA1
<28> AUX_LCD_CBL_DET#

C650
0.1U/10V_NC

AUD_DMIC_IN0

+5V_RUN
AUD_DMIC_CLK_R

Place close to Camera connector.

C431
1U/10V

(Code : 4-1-4)

JCAMERA1
PIN9

Inverter

Camera
PIN1

PIN15

Sniffer LED
GND

+3.3V_SUS

R206

SGPIO41

+3.3V_SUS

10

2
1

1
0

INVERTER_CBL_DET#

PAID

+3.3V_RUN

PIN11

Q58
DDTA114YUA-7-F

47K

PIN20

SNIFFER_YELLOW#

<28>

JCAMERA1

(Code : 4-1-3)

Inverter

<32> AUD_DMIC_CLK

2
R205
10K_NC

LVDS

PIN10

AUD_DMIC_CLK 2
1

<28>

OUT

AUD_DMIC_CLK_R

IN

OE#

VCC

LCD_CBL_DET_L

SNIFFER_GREEN#

10K

10K
U24

Q57
DDTA114YUA-7-F

47K

SNIFFER Y_R

SNIFFER G_R

GND
SN74LVC1G125DBVR_NC

PIN17

DELL CONFIDENTIAL/PROPRIETARY

SGPIO40
PIN3

Title

+5V_ALW

AUDIO CONN

PIN7

Size

Document Number
M-08

Date:

Monday, March 05, 2007


7

Rev
0.1
Sheet

of

33
8

51

+3.3V_RUN

1
2

FAN1_VOUT
FAN1_VOUT_FB

REM_DIODE3_P

Q34
MMST3904

1
C542
2200P/50V

C256
2200P/50V_NC

Q17
MMST3904

C543
2200P/50V

1
2

3
REM_DIODE1_P

C194
2200P/50V_NC

C441
2200P/50V_NC

REM_DIODE4_P

JFAN1

Put C545 close to Guardian.


Put C194 close to Diode

Put C543 close to Guardian.


Put C256 close to Diode

Put C542 close to Guardian.


Put C441 close to Diode

1
2
3

Place under CPU

Place under DIMM ( TOP )

Place under Minicard ( BOT )

MLX_53398-0371
C255
22U/10V

Put C546 close to


Guardian.

U31

Place under DIMM ( BOT )

R420
49.9/F

R434 1

DP3
DN3

41
40

DP2
DN2

DP4
DN4

48
47

REM_DIODE4_P
REM_DIODE4_N

+3VSUS_THRM

35

3V_SUS

DP5
DN5

2
1

REM_DIODE5_P
REM_DIODE5_N

+RTC_CELL

+3.3V_ALW

+3.3V_SUS
2

DP1
DN1

H_THERMDA
H_THERMDC

R435
10K_NC

R439
10K

R440
10K

RTC_PWR3V

23
16

VSUS_PWRGD
3V_PWROK#

THERMATRIP1#
THERMATRIP2#
THERMATRIP3#

17
18
19

THERMTRIP1#
THERMTRIP2#
THERMTRIP3#

THERM_VEST

42
26
34

ATF_INT#
POWER_SW#
ACAVAIL_CLR
THERMTRIP_SIO
SYS_SHDN#

20
3
4
25
24

LDO_SHDN#/ADDR

27

LDO_POK

33

VSET
XEN
VSS

LDO_SET

28

LDO_OUT
LDO_OUT

32
31

LDO_IN
LDO_IN

30
29

21
THERM_PWRGO
+3V_PWROK#

2 1K

C551
0.1U/10V

C571
0.1U/10V

R429 2
R431 2

+3.3V_SUS

1 10K_NC
1 10K_NC

ATF_INT# <29>
POWER_ SW_IN0# <28,31>
ACAV_IN <18,28,40>
THERMTRIP_SIO
THERM_STP# <44>
LDO_SHDN#_ADDR

R432
2

7.5K/F
1

+3.3V_SUS
2.5V_RUN_PWRGD

<38>

THERM_LDO_SET

FAN_OUT_1
FAN_OUT_2

T104 PAD

39

FAN_DAC1

10
13
14
15
22
36

GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6/FAN_DAC2

5V_CAL_SIO1#
5V_CAL_SIO2#

<32> AUDIO_AVDD_ON

VDD_3V

+3.3V_RUN

VDD_5V_1
VDD_5V_2

5
6

+5V_RUN

2
1

1
2
1

THERM_LDO_SET

R430
1K

0603
package.

Q32
2N7002W-7-F

C567
0.1U/10V

R428
1

Layout Note:
Place those capacitors
close to EMC4001.
C562
10U/10V

C566
0.1U/10V

THERM_LDO_IN

+3.3V_RUN

<18> THERMATRIP_VGA#

C540
2200P/50V

R427
31.6K/F_NC

C568
0.1U/10V

<6> THERMTRIP_MCH#

10/18 Check POP or Non-pop

5V_CAL_SIO1#

C570
0.1U/10V

1/2

Q36
MMST3904

Q35
MMST3904

0603
package.

THERM_B32
1

THERMATRIP2#

THERMATRIP3#

10K/F_0603
2

Voltage margining
circuit for LDO
output.For Vmargin
stuff R592 and
R113=30K. R113=1K for
production.

3
2

2
2

R443
2.2K

R312
1

R298
10K
1

R441
8.2K

R438
8.2K

47

VCP2
R442
8.2K

+3.3V_SUS

Thermistor P/N:
TH11-3H103FT

R323
2.2K/F

+3.3V_SUS

+2.5V_RUN

20

C568 needs to be placed


near Guardian IC.
+3.3V_RUN

THERM_B2 2

+3.3V_SUS
2

+5V_SUS

C569
0.1U/10V

Q37
MMST3904

<3> H_THERMTRIP#

R444 2.2K
1
2

THERM_LDO_IN

Placement should be near the WWAN minicard


connector just under the inserted minicard.

THERMATRIP1#

THERM_B1 2

C570 needs to be placed


near Guardian IC.

+2.5V_RUN

EMC4001

1
3

R445 2.2K
1
2

7
8

R437
8.2K

C569 needs to be placed


near Guardian IC.

FAN1_VOUT

+RTC_CELL

+3VSUS_THRM

+3.3V_SUS

+1.05V_VCCP

PWR_MON <45>

45
44

www.kythuatvitinh.com
2

<26> MDC_RST_DIS#
<18> SIO_GFX_PWR

+1.05V_VCCP

REM_DIODE3_P
REM_DIODE3_N

38
37

1
2 1K
2 1K

VCP2

REM_DIODE1_P
REM_DIODE1_N

+RTC_CELL
R436 1
R433 1

<38> SUSPWROK
<38> ICH_PWRGD#

Put C553 close to Guardian.


Put C573 close to Diode

43
46

C573
2200P/50V_NC

REM_DIODE5_P

+3.3V_SUS

VCP1
VCP2

Q38
MMST3904

EMC 4001
QFN PIN48

<3> H_THERMDC

1
1

C553
2200P/50V

C546
470P/50V
REM_DIODE5_N

SMDATA
SMBCLK

11
12

<28> THRM_SMBDAT
<28> THRM_SMBCLK
2

<3> H_THERMDA

Q14
MMST3904

2
R162
0
D13
CHN202UPT_NC

REM_DIODE4_N

1
1

C545
2200P/50V

FAN1_TACH <28>

REM_DIODE3_N
1

REM_DIODE1_N
R163
10K

C565
1U/10V

0/1210
2

+3.3V_RUN

This Value of
R428 can be 0.27
or 0 ohm
and the package
is 1210.

+3.3V_SUS

DELL CONFIDENTIAL/PROPRIETARY

1
C558
0.1U/10V_NC

C556
10U/10V

C561
0.1U/10V

+2.5V_RUN

+5V_RUN

C544
2200P_50V

Note:
VSET = (Tp-70)/21, where
Tp = 70 to 101 degrees C.
Tp set at 88 degrees C.
Guardian temp tolerance =
+-3 degrees C.

1
3

R419
118K/F

C535
0.1U_10V
2

THERM_VEST

R418 332K/F
1
2

C554
10U/4V_NC

Title
FAN & THERMAL
Size

Document Number
M-08

Date:

Monday, March 05, 2007


7

Rev
0.1
Sheet

of

34
8

51

Refer to M07_LOM4401_X06
schematic.

+3.3V_LAN

38

38

38

38

38

38

+1.8V_LOM

38

+3.3V_SUS

1
C26
.1U/10V/0402

C37
47P/50V/0402

C34
47P/50V/0402

C354
47P/50V/0402

C25
47P/50V/0402

C351
C21
1000P/50V/0402 1000P/50V/0402

+3.3V_LAN
1

C27
C13
47P/50V/0402 4.7U/10V/0805
R18

2
0_0805

Place C1284 close to pin65

Close to power pins


0.1U*13 pcs

Refer to M07_LOM4401_X06 schematic.

C16
C645
C41
C350
47P/50V/0402 47P/50V/0402 .1U/10V/0402 .1U/10V/0402

C30
C28
C38
C14
C15
47P/50V/0402 .1U/10V/0402 1000P/50V/0402 .1U/10V/0402 .1U/10V/0402
2

C18
C39
47P/50V/0402 .1U/10V/0402

C646
C35
C36
1000P/50V/0402 4.7U/10V/08054.7U/10V/0805

+3.3V_LAN

38

Refer to M07_LOM4401_X06 schematic.


'+3VLAN should be sourced from
+3VSUS instead of +3VSRC since WOL
is not supported on C/G.

EMI requirement on 0812

These three pin


LINK_LED10#,
LINK_LED100#,
ACT_LED are
open-drain type.
+3.3V_LAN

+1.8V_LOM

91
92

96
97

65

106
79
94

115
125
19
30
40
52
7

112
17
44

Place R219, C640, C347 close to pin69


+3.3V_LAN

LINK_LED10#
LINK_LED100#
ACT_LED#
COL_LED#

75
76
77
78

EPHY_BIAS_AVDD

69

+3.3V_LAN_BIAS_AVDD

LINK_LED10# <36>
LINK_LED100# <36>
ACTLED# <36>

1
2
R219
BK2125LM152

38
1

PCI_RST_L
PCI_CLK
PCI_GNT_L
PCI_REQ_L
PCI_PME_L
PCI_IDSEL
PCI_CLKRUN_L

R222
10K_NC

117
118
119
121
113
5
22

R223
10K_NC

PCI_CBE_L3
PCI_CBE_L2
PCI_CBE_L1
PCI_CBE_L0
PCI_FRAME_L
PCI_IRDY_L
PCI_TRDY_L
PCI_DEVSEL_L
PCI_STOP_L
PCI_PERR_L
PCI_SERR_L
PCI_PAR
PCI_INT_L

R221
10K_NC

VDDCORE
VDDCORE
VDDCORE

4
18
32
43
20
21
23
26
27
28
29
31
116

REGULATOR_VOUT1
REGULATOR_VOUT2

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

XTAL_AVDD

122
123
124
126
127
128
1
3
6
8
9
10
11
14
15
16
33
34
36
37
38
39
41
42
45
48
49
50
51
53
54
55

REGULATOR_AVDD
REGULATOR_AVDD

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

VDDIO
VDDIO
VDDIO

<12,20> PCI_AD[31..0]

VDDIO_PCI
VDDIO_PCI
VDDIO_PCI
VDDIO_PCI
VDDIO_PCI
VDDIO_PCI
VDDIO_PCI

VESD
VESD
VESD

U5

114
25
56

+3.3V_LAN

www.kythuatvitinh.com
71
72
88

EPHY_TDP
EPHY_TDN
EPHY_RDP
EPHY_RDN

62
61
59
60

1.27K/F_0402

C644
47P/50V/0402

1
2

1
2

R220

C23
47P/50V/0402

C22
2.2U/6.3V/0603

R12
49.9/F_0402

Y1

C348
.1U/10V/0402

Delete R630&R631
per 4401 ref
schematic

C19
27P/50V/0402

C24
.1U/10V/0402

+3.3V_LAN

CS
SK
DI
DO

VCC
NC
ORG
GND

8
7
C2
6
5 .1U/10V/0402

C641
47P/50V/0402

Note: BCM4401 requires


16-bit R/W data width

1
2
3
4

SPROM_CS
SPROM_CLK
SPROM_DOUT
SPROM_DIN

U2

T45
T46

1
1K_0402

EXT_POR_L

89

JTAG_TDP
JTAG_TCK
JTAG_TDI
JTAG_TRST_L
JTAG_TMS

83
80
82
73
81

LOM_LOW_PWR# <29>
T47

Note: EXT_POR_L has a internl pull up.

T54

Note: The BCM4401 has weak internal pulldown resistors on


the following signals:
SPROM_CS, SPROM_CLK, SPROM_DOUT, SPROM_DIN.

T57

BCM4401 B0

XO
1

BOOTROM_SCL
BOOTROM_SDA

90
93

T3
T1

Resistors must be rated at least


1/16W. Place termination
resistors close to the ASIC.

1
XTAL_OUT

R10
BCM4401KQLG
800_0402
25MHz
XI 2

66

XTAL_IN

Refer to M07_LOM4401_X06 schematic.


R489 and R490 removed from
schematic because of Bios can
configure the state of CLKRUN#
signal.

C33
6P/50V

67

2
R217

R11
49.9/F_0402
2

R16
49.9/F_0402

XTAL_AVSS
EPHY_BIAS_AVSS
EPHY_AGND
EPHY_PLLGND

PCI_IDSEL
2
100_0402

<13,20,28> CLKRUN#

68
70
58
63

R17
33

Place R17, C33


close to U62.118

<12> PCI_GNT0#
<12> PCI_REQ0#
<20,29> SYS_PME#
PCI_AD16 1
R19

Place L66, C29, C644


close to pin57.

M93C46-WDW6TP

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

<12,20> PCI_RST#
<17> CLK_PCI_LOM

2
L66
BK2125LM152

C29
.1U/10V/0402

1
R13
49.9/F_0402

+3.3V_LAN

87
86
85

98
95
101
99

+1.8V_LOM

Place L7, C22, C23


close to pin64.

104
105
103
108
102
109
110
107

GPIO2/VAUXAVAIL
GPIO1
GPIO0

SPROM_CS
SPROM_CLK
SPROM_DOUT
SPROM_DIN

12
46
111
100
84
2
24
74
13
47
120
35

<12,20> PCI_C_BE3#
<12,20> PCI_C_BE2#
<12,20> PCI_C_BE1#
<12,20> PCI_C_BE0#
<12,20> PCI_FRAME#
<12,20> PCI_IRDY#
<12,20> PCI_TRDY#
<12,20> PCI_DEVSEL#
<12,20> PCI_STOP#
<12,20> PCI_PERR#
<12,20> PCI_SERR#
<12,20> PCI_PAR
<12> PCI_PIRQB#

C346
.1U/10V/0402

LOM_TX+ <36>
LOM_TX- <36>
LOM_RX+ <36>
LOM_RX- <36>

NC
VSS
NC
NC
NC
NC
NC
NC

Place R942
close to U62

+1.8V_LOM

EPHY_VREF
RDAC
EPHY_TESTMODE

L7
BK2125LM152

+1.8V_LOM_PLLVDD

64

57

EPHY_PLLVDD

C640
C347
47P/50V/0402 .1U/10V/0402
2

EPHY_AVDD

+1.8V_LOM_EPHY_AVDD

T2

Title

C20
27P/50V/0402

QUANTA
COMPUTER
LAN (BCM4401)

Size

Document Number
FM1

Date:

Monday, March 05, 2007

Rev
0.1
Sheet
E

35

of

51

2
R225

<35> LINK_LED100#
+3.3V_LAN

1
150_0402

17
15

GREEN
ORANGE

16

COMMON

11
12
10

TRD1+/TX
TRCT1/TX
TRD1-/TX

4
6
5

TRD2+/RX
TRCT2/RX
TRD2-/RX

14

LED2_YP

L67
BK2125LM152
<35> LOM_TX+
<35> LOM_TX<35> LOM_RX+

CON1
TYCO_1368458-1

1
150_0402

<35> LOM_RX-

2
R226

<35> LINK_LED10#

www.kythuatvitinh.com
13

38

C364
.1U/10V/0402

<35> ACTLED#

Place close
to CON1.6 &
CON1.12.

LED2_YN
1
2
3
7
8
9

C366
47P/50V/0402

1
R224

18
19

Place close
to CON1.6.

1
2
3
7
8
9

MGND
MGND

Removed EMI bead(L40-43)


and ESD protect IC(U33)

2
150_0402

QUANTA
COMPUTER

Title
LAN Jack

Size

Document Number
FM1

Date:

Monday, March 05, 2007

Rev
0.1
Sheet
E

36

of

51

+5V_SUS

R46
100K_NC
D3
19-21/BHC-YL1M1RY/3T
1

U7

BREATH_PWRLED

24

R30
1

330
2

RBREATH_PWR_LED

R40
2

<11> SATA_ACT#

Q1
DDTA114YUA-7-F

47K

0
12

10K
BEBL0031Z11

7SH04

LED19-21VGC-TR8

54

10/31 PSL issue

3
Q63
2N7002W-7-F

+5V_SUS

21

R528
100K

<28> BREATH_LED#

+5V_RUN

HDD activity LED.

2
R527
10K

24

+3.3V_ALW

Power & Suspend.

HDD_LED

D4
220
19-21/BHC-YL1M1RY/3T
2RHDD_LED 2
1

R36
1

+5V_RUN
+3.3V_RUN

+3.3V_WLAN
47K

R541
0

47K

220
RBAT2_LED 2

R51
1

+5V_ALW

<24> LED_WLAN_OUT#

BAT2_LED

R542
10K_0402
2
1

24

D6
19-21/BHC-YL1M1RY/3T
Q5
MMBT3906_NL

2
3

R50
1

R553
47K_0402

10K

3
3

BAT1_LED

<28> BAT2_LED#

330
RBAT1_LED 2

10K
Q67
DTC144EUA

54

54

BAT1_LED_R#

BAT1_LED# <28>

BLUE

D5

24

Q3
DDTA114YUA-7-F

47K

R64
330

Q4
DDTA114YUA-7-F

2 1

+3.3V_ALW

WLAN

3 1

+3.3V_ALW

Battery status.

19-22UYOSUBC

9/20 Change FP

Q65
DTC144EUA

47K

47K
47K

www.kythuatvitinh.com
+3.3V_RUN

+5V_RUN

+5V_RUN

Media BD

R522
100K_NC

R523
100K

47K

BT_ACTIVE#

54

<29> M_LED_BK#

M_LED_BK#

Q16
DTA114YUA

2BT_LED_R 2

10K
Q76
2N7002W-7-F

M_LED_BK_L
R159

M_LED_BK <31>

0_0805

D8
19-21/BHC-YL1M1RY/3T

Q62
2N7002W-7-F

47K

R75
330

R525
0_NC

<11,29> LED_MASK#

R546
4.7K_0402_NC

R521
100K_NC

BT_MASK 1

1
2

R524
100K

Q61
2N7002W-7-F

2N7002W-7-F
Q59

BT_LED
3

Q60
SI2301BDS

BT_ACTIVE

+5V_RUN

+3.3V_RUN

10K

LED_WPAN#

<24> LED_WPAN#

24

Q7
DTA114YUA

24

BT

This circuit is only needed if


the platform has the SNIFFER.

R526 2

1 0_NC

+3.3V_RUN

19

BT_ACTIVE

R336 10K
1
2

19

COEX1_BT_ACTIVE_DC

COEX1_BT_ACTIVE_MINI

12/26
Q13
MMBT3906_NL_NC

Bluetooth

LED_MASK#

LED_MASK# <11,29>

<24> COEX1_BT_ACTIVE_MINI

R559 2

COEX1_BT_ACTIVE_DC
USBP7_D-

USBP7_D+
USBP7_D1

R123
10K

C195
100P/50V

1 0_NC

51

16

COEX2_WLAN_ACTIVE <24>

2
R108
10K

1
A

COEX1_BT_ACTIVE <24>

L40

1
C190
0.1U/10V

TYC_1566995-1

2
4
6
8
10

1
4

2
3

ICH_USBP7+ <12>
ICH_USBP7- <12>

DLW21SN900SQ2B_NC
C193
33P/50V

USBP7_D+

GND
Activity LED
3.3V(Logic)
COEX2
Radio Enable/Disable# COEX1
RSVD
USBUSB+
GND

<29> BT_RADIO_DIS_DC#
PAD T28

1
3
5
7
9

COEX1_BT_ACTIVE

7SH32

J1

+3.3V_RUN

25

U35

R512
1

R513
1

Layout Note:
R512 and R513
close to choke
as possible to
minimize stubs.

2
2

Title

QUANTA
COMPUTER
SWITCH & LED

Size

Document Number
FM1

Date:

Monday, March 05, 2007

Rev
0.1
Sheet
E

37

of

51

Non-iAMT

+5V_ALW

2
2
2
2

1
1
1
1

+3.3V_SUS

0
0
0_NC
0_NC

R148
100K

R154
2.2K_NC

9/20 Depop R463

+5V_RUN

R462
R461
R467
R463

+3.3V_RUN

D33
SDMK0340L-7-F

ICH_PWRGD

<6,13>

R472
1

4.7K
2

Q50
MMST3904

U17D

C600
2200P/50V

Q49
MMBT3906_NL

R473
200K

1
2

C601
0.1U/10V

<34>

Q15
2N7002W-7-F

R471 10K
1
2 2

1
1

ICH_PWRGD#
3

1.5V_RUN_PWRGD
1.05V_RUN_PWRGD
2.5V_RUN_PWRGD
GFX_PWRGD

2 0

<43>
<43>
<34>
<18>

R460 1

<42> 1.25V_RUN_PWRGD

<13,28,45> IMVP_PWRGD

12

<28> RESET_OUT#

13

11
74AHC08PW

+1.8V_SUS

+3.3V_SUS
Q47
MMST3904_NC

C212
1
5

+3.3V_ALW

+3.3V_RUN

+3.3V_ALW

R137
20K

9/20 Depop Q47

4.7K_NC
2
2

+3.3V_ALW

+3.3V_ALW

0.1U/10V
2
5

R466
1

C599
2200P/50V_NC

R469
200K_NC

1
2

C598
0.1U/10V_NC

Keep Away from high speed buses


Q45
MMBT3906_NL_NC

R468 10K_NC
1
2 2

D32
SDMK0340L-7-F_NC
2
1

+1.8V_RUN

U18A

U18B
C200
1

Q43
MMBT3906_NL

0.1U/10V
2

C223
0.01U/25V

NC7WZ14P6X_NL

NC7WZ14P6X_NL

R464
1

4.7K
2

Q46
MMST3904

R151
1

<18,28,39> RUN_ON

U17A

74AHC08PW

C589
2200P/50V

1
2

R454
200K

C590
0.1U/10V

www.kythuatvitinh.com
1

1
2

14

R453 10K
1
2 2

D31
SDMK0340L-7-F
2
1

U17B

5V_3V_1.8V_1.25V_RUN_PWRGD

<29>

RUNPWROK

<18,28,29,45>

74AHC08PW

U17C

10

<28,39> SUS_ON

SUSPWROK <34>

74AHC08PW

13
12

+3.3V_ALW

C292
2200P/50V

Q22
MMBT3906_NL
D16
SDMK0340L-7-F
2
1

U20

R182
200K

C293
0.1U/10V
1
2

C291
0.1U/10V
2

R183 10K
1
2 2

D17
SDMK0340L-7-F
2
1

+3.3V_ALW

+3.3V_SUS

NC7SZ14P5X_NL

R181
200K

+5V_ALW

C290
2200P/50V

R179
200K

Q21
MMBT3906_NL
D15
SDMK0340L-7-F
2
1

C289
0.1U/10V
2

QUANTA
COMPUTER

R180
200K
2

R177
200K
2

R178 10K
1
2 2

D14
SDMK0340L-7-F
2
1

+5V_SUS

Title

System Reset Circuit

Size

Document Number
M-08

Date:

Monday, March 05, 2007


7

Rev
0.1
Sheet

of

38
8

51

+3.3V_ALW

+3.3V_SUS
PQ17
SI4800BDY-T1-E3
8
3
7
2
6
1
5
PC62
10U/6.3V/1206

PR60
20K_0402

SUS_3.3V_ENABLE

PC63
4700P/50V/0603

PR62
100K_0402_NC
2

PQ18B
2N7002DW

PQ18A
2N7002DW

4
2

<28> 3.3V_SUS_ON

SUS_ON_3.3V#

PR63
100K_0402

PR61
100K_0402_NC

+15V_ALW

PC180
4700P/50V/0603

PR193
100K_0402
2

4
1

PQ40B
2N7002DW

+5V_ALW2

PR182
20K_0402
1

PQ40A
2N7002DW

6
2

3
RUN_ON_5V# 5

<18,28,38> RUN_ON

+3.3V_ALW2

+5V_RUN
PQ39
SI4800BDY-T1-E3
8
3
7
2
6
1
5
PC179
10U/25V/1206

RUN_ENABLE

PR183
100K_0402
2

PR184
100K_0402_NC

PR189
100K_0402

+5V_ALW

+15V_ALW

+5V_ALW2

+3.3V_ALW2

+15V_ALW

1
PR192
100K_0402

PR88
100K_0402_NC

PR87
100K_0402

PC91
10U/6.3V/1206

PR85
20K_0402
1

3
5
4
<28,38> SUS_ON

PQ26A
2N7002DW

SUS_ON_5V#
PC55
.047U/25V

PR54
0_0402_NC
2

SUS_5V_ENABLE

<28> 1.8V_RUN_ON

PQ14A
2N7002DW_NC

3
B

+5V_SUS
PQ27
SI4800BDY-T1-E3
8
3
7
2
6
1
5
4

PR52
20K_0402_NC

+5V_ALW2

PR53
100K_0402_NC

PR190
PR55
100K_0402_NC 100K_0402_NC

+5V_ALW
+3.3V_ALW2
1

+1.8V_RUN
PQ13
SI4800BDY_NC
8
3
7
2
6
1
5
PC56
10U/6.3V/0603_NC
PD5
CH751H-40HPT_NC
1
2

+1.8V_SUS

+15V_ALW

+5V_ALW2

+3.3V_ALW2

PC92
4700P/50V/0603

PR86
100K_0402_NC

PQ26B
2N7002DW

www.kythuatvitinh.com
PQ14B
2N7002DW_NC

PR57
20K_0402

R172
30/F_0402_NC

+3.3V_SUS

PC57
10U/6.3V/1206

+5V_SUS

R176
1K_0402_NC

R175
1K_0402_NC

Q18
2N7002W-7-F_NC

Q20
2N7002W-7-F_NC

Q19
2N7002W-7-F_NC

6800P/50V/0402

30

3 2

3 2

3 2

SUS_ON_5V# 2

PC58

+1.8V_SUS

PR58
0_0402
PQ16A
2N7002DW

4
2

<28> 3.3V_RUN_ON

PD6
CH751H-40HPT_NC
2

Reserve discharge path

3
6

PR59
100K_0402

+3.3V_RUN
PQ15
PHK12NQ03LT
3
2
1

8
7
6
5

PR56
100K_0402_NC

PR191
100K_0402

+3.3V_ALW

+15V_ALW

+5V_ALW2

+3.3V_ALW2

PQ16B
2N7002DW
Inrush curreunt : 5.4 A

Reserve discharge path


1

3 2

3 2

3 2

R465
1K_0402_NC

Q39
2N7002W-7-F_NC

Q48
2N7002W-7-F_NC

2
Q40
2N7002W-7-F_NC

+1.25V_RUN

R455
1K_0402_NC

3 2
2
Q44
2N7002W-7-F_NC

+0.9V_DDR_VTT

R456
1K_0402_NC

2
Q41
2N7002W-7-F_NC

Q42
2N7002W-7-F_NC

+1.5V_RUN

R470
1K_0402_NC

3 2

R457
10_0402_NC

3 2

R458
1K_0402_NC

RUN_ON_5V#

+1.8V_RUN

+3.3V_RUN

+5V_RUN

Title

QUANTA
COMPUTER
RUN POWER SW

Size

Document Number
M-08

Date:

Monday, March 05, 2007

Rev
0.1
Sheet
5

39

of

51

Id=9.6A@Vgs=10V
PQ32
SI4835BDY-T1-E3

+PWR_SRC

1 4
PC29

PR36
100K_0402
2
1

8
7
6
5

2200P/50V0402

+DC_IN_SS
PR117

PC30

470K_0402

.1U/50V/0603

PR40

FL5
FBMH3225HM202NT
1
2

1
2
3

8
7
6
5

+DC_IN_SS

+DC_IN_SS

1
2
3

CHGR_IN

PR33
.01/F_2512

PQ2
SI4835BDY-T1-E3

CSSP

10K_0402

CSSN

2
PQ5
2N7002W-7-F

+DC_IN_SS

Max Charging current setting


4.7A
2

LDO

PC32
10U/25V/1206

.1U/50V/0603 10U/25V/1206

PC102

27

28

2200P/50V0402

0_0603

PC31

PD11
SDM10K45_NC

25 BST

LDO

21

VCC

26

DHI

24

13

ACOK

<18,28,34> ACAV_IN

PR120
33/F_0603

PC100
.1U/50V/0603
4

RDS(ON)=30m ohm

PR104
1K_0402_NC

PQ3
SI4800BDY-T1-E3

PC109
3300P/50V/0402
1
2

BST

.01U/25V/0402

PR32
PL1
5.8UH 30% 5.5A 24m(SIL104R-5R8PF) .01/F_2512
2
1CHG_CS1

ACIN

LDO

5
6
7
8

PC43 1U/10V/0603
2
1
1

DCIN

CSSN

22

GND

8731_ACIN

PC114

PR119

PR50
10K/F_0402

1U/25V/0805

PC110

CSSP

LDO

PC28

1
PR123
365K/F_0402
PR122
49.9K/F_0402
2
1

+5V_ALW

PD10
SDM10K45

+VCHGR_1

FL6
HI1206T161R-10
1
2

FBSB

16

0_0603

.01U/25V/0402

ADAPT_OC <29>

PR49
100K_0402
3

PU4A
LM393DR2G

3
1

PQ6
2N7002W-7-F

**PR34

1
2

1
2

1
2

3.17

57.6K

13K

105

N/A

90

4.43

51.1K

17.8K

348

33.2K

130

6.43

32.4K

20.5K

100

27.4K

150

7.43

30.9K

24.9K

432

88.7K

200

9.75

19.1K

28K

301

36.5K

230

11.28
(see note3)

32.4K

6.49K

115

N/A

PR43
1K_0402_NC

Note 2: 24.9K at PR34 allows the 65W adaptor seetting to switch


down to 45W.

PC44
.1U/10V/0402_NC

Note 3: PR33 must be 5mOhms instead of 10mOhms for the 230W adaptor.
2

PC51
PC22
100P/50V/0402
100P/50V/0402

2
2

PR39

Note 1: PR34 is popluated if ADAPT_TRIP_SEL is used to program for


the next lower adapter.
ADAPT_TRIP_SET is floating for the higher adaptor,
grounded for the lower adaptor.

PC52
.01U/25V/0402
Title

For GPRS immunity place as close to


the IC as possible

QUANTA
COMPUTER
CHARGER

GNDA_CHG

PR35

65

PR39
348/F_0402

SEE TABLE 1

PR38

2
2

TRIP CURRENT
(A)

PC53

PC50
100P/50V/0402

1
2
8

2
33.2K/F_0402

PR35
17.8K/F_0402

10/4 EMI request

1
PR45
100K_0402

1
2

SEE TABLE 1

SEE TABLE 1

SEE TABLE 1

2200P/50V0402

GNDA_CHG

PR38
51.1K/F_0402

PC25
.01U/25V/0402

PC187

TABLE 1

ADAPTER(W)
PR143

PR41
1M/F_0402

SEE TABLE 1

PC17

PU7

+5V_ALW

1
2

2 2

PC108
220P/50V/0402

+5V_ALW

1
PR34
1
2
0_0402PR188
0_0402PR188

5
6
7
8
1
2
3

100_0402

PC133
.1U/10V/0402

1U/10V/0603

8731REF
PC126

PC20

CSIN

+3.3V_ALW

<29> ADAPT_TRIP_SEL

PC8

CSIP

1+VCHGR

+VCHGR <41>

15

PC101
1000P/50V/0402_NC

PC195

2
1

FBSA

GND

2
1
1
2

REF

PC127
.01U/25V/0402

PC131
.01U/25V/0402

CCS

SI4810BDY-T1-E3

PR137

CCI

CSIN

17

PC89 PC196

10U/25V/1206/X5R

18

PR110
3.8_0805_NC

RDS(ON)=20m
ohm
PQ4

10U/25V/1206/X5R

PC45
.01U/25V/0402

.1U/10V/0402

PR144
8.45K_0402

PC139

PR133
10K_0402

CCV

CSIP

DLO

.1U/50V/0603

IINP

19

Adress :
12H

20

1_0603

1000P/50V/0402

IINP

DLO

PGND

PR121

3300P/50V/0603

GNDA_CHG

SMBUS Address 12

PC115 1U/10V/0603

23 LX

MAX8731AETI+LX

SCL
SDA
BATSEL

DHI

10U/25V/1206/X5R

<28,41> PBAT_SMBCLK
<28,41> PBAT_SMBDAT

.1U/50V/0603
10
9
14

12

PC137

DAC

1 7

PR51
15.8K/F_0402

VDD

1
2
3

www.kythuatvitinh.com
11

+3.3V_ALW

Size

Document Number
FM5

Date:

Monday, March 05, 2007

Rev
0.1
Sheet
E

40

of

51

PD2
DA204U_NC

PD1
DA204U_NC

.1U/50V/0603
2

+3.3V_ALW
3

+VCHGR <40>

1
PR8
10K_0402

JABT1

SMBUS Address 16

1
3

2
4

1
3

2
4

PBAT_SMBCLK <28,40>
PBAT_SMBDAT <28,40>
PBAT_PRES# <29>
PBAT_ALARM#

RP1
4P2R-100

SUY_200185MR009S509ZL

+5V_ALW
+3.3V_ALW
PD9
DA204U

Adress : 16H

RP2
4P2R-100

1
2
3
4
5
6
7
8
9

BATT1+
BATT2+
SMB_CLK
SMB_DAT
BATT_PRES#
SYSPRES#
BAT_ALERT
BATT1BATT2-

PC11
1

PD3
DA204U_NC

2200P/50V0402
2
3

1
1

PD4
DA204U_NC
PC7

+3.3V_ALW

PR92
2.2K_0402
2

PQ28
2N7002W-7-F
PR91
DOCK_PSID

PS_ID <28>

+5V_ALW

+5V_ALW

1
PR90
100K/F_0402
1

100_0402

PD8
DA204U

www.kythuatvitinh.com
PR93
10K_0402

D18

SSM24PT_NC

PR89

PQ29
MMST3904-7-F

PS_ID_DISABLE#

<29>

PR94 100_0402_NC

15K/F_0402

PL11
1
BLM11B102S

DOCK_PSID

Change Value per GG updated


EMI requirement on 0812

1
2

10U/25V/1206

.1U/50V/0603

.1U/50V/0603

PC3
+

PC2
2

.1U/50V/0603

PC95
.47U/25V/0805

PC5

PQ30
IMD2A_NC

<28> AC_OFF

RV1
VZ0603M260AGT_NC
4

RV2
VZ0603M260AGT_NC

PR2
10K/F_0603
2

PC4

1
PR95
240K_0402

.1U/50V/0603

PC1

8
7
6
5

1
2
3

-DCIN_JACK
1

9
8
7
6
5
4

FL2
BLM41PG600SN1L
1
2
1
2
BLM41PG600SN1L
FL1

+DCIN_JACK

PQ1
SI4835BDY-T1-E3 +DC_IN_SS

+DC_IN

JDCIN1
FOXCONN_JPD113D-509-TR
1

PR1
47K_0402

Title

QUANTA
COMPUTER
DCIN,BATT CONNECTOR

Size

Document Number
FM5

Date:

Monday, March 05, 2007

Rev
0.1
Sheet
E

41

of

51

1.8 Volt +/- 5%;f=400kHz


Thermal Design current: 5.61A
Maximum current: 8.015A
OCP: 12.36A

PR161
1

.1U/50V/0603

1
2

2200P/50V/0402

2
1

.1U/50V/0603

1
2

PC71

PC166
.1U/25V/0603

1.25V +/- 5%;f=300kHz


Thermal Design Current: 0.924A
Maximum Current: 1.32A
OCP: 1.67A

PR160
10K_0603

PAD
PAD
PAD

PL8

1.8V_DH

2
5

PJP10
POWER_JP

PQ23B
FDS8984
PL9
6.8uH_SIQ74-6R8_2.1A/45mohm
+1.25V_RUN_P

S1

G1
1.25V_LX

PC65

PQ23A
FDS8984
Rdson=30mOhm

G1
PC189
S1
4700P/50V/0603_NC

Del PC66

.1U/25V/0603_NC

PC176
1U/10V/0603

PR172
PR170
100K/F_0402
100K_0402_NC

PC72
1U/10V/0603

10_0603

PR169
17.4K/F_0603

PC183

PR67

PR168
27.4K/F_0603

+5V_VCC3

3
2
1

+3.3V_ALW

PC181
4700P/50V/0603

10U/25V/1206_NC

1 PR179 2
1_0603

PC67

150U/2V/ESR18

D1

1.25V_DL 2

1.8V_DL

PR177
1_0603
2

D1

PC175
.1U/25V/0603

+5V_ALW

.1U/25V/0603

330U/6.3V/ESR25_NC

330U/2.5V/ESR15

PC164

9
8
7
6
5

PC173
.1U/25V/0603

17
18
19
20
21
22
23
24

35
34
33

3
2
1

1.8V_LX

PQ20
FDS6680AS
Rdson=12.5mOhm

PC64

PC66

D1

www.kythuatvitinh.com
1.0UH_SIL104_11A/6mohm
2
1

+1.8V_SUSP

<28> D1

1.25V_DH 4

PQ19
FDS8878

1.25V_RUN_ON

8
7
6
5
C

+1.25V_RUN
PR174
100K/0603_NC

309K/F_0402
2

PR163
100K/F_0402
1
2
1
2
0_0402PR186
0_0402PR186

32
31
30
29
28
27
26
25

REFIN2
ILIM2
OUT2
SKIP#
MAX8778ETJ+
POK2
EN2
UGATE2
PHASE2
PU9

PR73

<28> DDR_ON

BYP
OUT1
FB1
ILIM1
POK1
EN1
UGATE1
PHASE1
PAD
PAD

+3.3V_ALW

PR162
16.9K_0603

PJP7
POWER_JP
2

9
10
11
12
13
14
15
16
37
36

.1U/25V/0603_NC
PJP8
POWER_JP

LDOREFIN
LDO
VIN
VREF3
EN_LDO
VCC
TON
REF

PC182

BOOT1
LGATE1
PVCC
SECFB
GND
PGND
LGATE2
BOOT2

8
7
6
5
4
3
2
1

+1.8V_SUS

2
PR158
0_0402_NC
1
2

1
PC188

PC70

PR159
0_0402
2

0_0402_NC
2

10U/25V/1206

PR66
0_0402_NC

10U/25V/1206_NC

1
1

PC165
.1U/50V/0603

PC171
+

2
2

PR65
0_0805
+5V_VCC3

2 1

1
2

PR64
0_0805

2200P/50V/0402

2
1

PC168
+

PC76 PC77
.1U/50V/0603

1
2

10U/25V/1206

PC167
+
10U/25V/1206

PC170
+

+DC_PWR_SRC

PJP21
POWER_JP
1
2

+PWR_SRC

<38> Power

1.25V_RUN_PWRGD
1.8V_SUS_PWRGD

<28>

Sequencing, Vcore Regulator

Power Sequencing

SJ5

Jump20X10

+1.8V_SUSP

+5V_ALW

0.9V +/- 5%
Design current 1.05 A
Peak Current 1.5 A

V_DDR_MCH_REF +0.9V_P

PC163
10U/4V_NC

S3 (STBY)

VTTREF

S5 (OFF)

PGND

AGND

TPS51100
PC162
0.1U/25V

POWER_JP

PC160
10U/4V/0603

PC161
10U/4V/0603
1

VDDQSNS

<28> DDR_ON

VTT
VTTSNS

VLDOIN

PAD

<28> 0.9V_DDR_VTT_ON

IN

PC159
2

11

1
PJP20
POWER_JP

.1U/25V/0603

10

+0.9V_DDR_VTT

PJP19

U32

Title

QUANTA
COMPUTER
1.25V,1.05V,1.8V,0.9V

Size

Document Number
FM5

Date:

Monday, March 05, 2007

Rev
0.1
Sheet
1

42

of

51

+1.5V_RUN /+1.05V_VCCP /+3.3V_ALW /+3.3_RTC_LDO


+PWR_SRC
+DC2_PWR_SRC

PJP3
POWER_JP
1

2200P/50V/0402

PC143

.1U/50V/0603

PC144

+ PC145
10U/25V/1206

10U/25V/1206

PC106

PR44
0_0805

PC49
2200P/50V/0402

PR42
0_0805

1
2

PC54
.1U/50V/0603

+ PC141
10U/25V/1206

+ PC146

.1U/50V/0603

5
6
7
8

8
7
6
5
4
3
2
1

PC118
.1U/25V/0603

1.05V_DH 4

PQ12
FDS8878

LDOREFIN
LDO
VIN
VREF3
EN_LDO
VCC
TON
REF

PR118
0_NC

1.5V_DH

S1

PJP4
POWER_JP

PJP5
POWER_JP

1
PC112
1U/10V/0805

PC136
1U/10V/0603

2
1

PC157
10U/6.3V/1206

PC155
330U/2.5V/ESR40_NC

PC156
330U/2.5V/ESR15

PC158
.1U/25V/0603

5
6
7
8
9

PC135
.1U/25V/0603

PC130
0.1U/25V_NC

Notes:
2. For Inspirion +3.3V_ALWP becomes +3.3V_SUSP.
3. For Inspirion +5V_ALW2 becomes +5V_ALW

SJ2
2

1
2
3

PR142
1_0603
2

+5V_ALW

PQ10
FDS6680AS
Rdson=12.5mOhm

1.05V_DL 4

1
2
3

no QCI P/N

Jump20X10

PR136
1

0_0402
2

1.5V_RUN_ON

EN2

PR139
1

0_0402
2

1.05V_RUN_ON

PR132
178K_0402

<28>
<29>

PR140
178K_0402

EN1

+3.3V_SUS

Layout Notes:
Place C7 very near U1-pin19 and PU1-pin20.
Place C8 very near U1-pin3.
Place R19 very near U1-pin21.
Minimize loop including Q4, L2, C11, C12 and R19.
Minimize loop including Q2, L3, C17, C18, C19 and R19.
Route GNDA_DC2 using at least 25 mil trace width.
Minimize GNDA_DC2 trace length.
Place C15 near U1-pin7.
Place C20 near U1-pin5.
Place R7 near U1-pin11.
Place R12 near U1-pin31.
Place R3, C10 near U1-pins 24 and 25.
Place R2, C9 near U1-pins 16 and 17.
Route +1.05V_BOOT, +1.05V_BOOST, +1.5V_BOOT, +1.5V_BOOST
using 25mil trace width and minimize lengths.
Connect large copper fill areas to PQ1, PQ2, PQ3 and Q4
signals for thermal improvement.
Minimize length of +1.5V_RUN_PL and +1.05V_VCCP_PL.
Place C1, C2, C3, C22 very near Q3-pins 5, 6, 7, 8.
Place C4, C5, C6, C23 very near Q1-pins 5, 6, 7, 8.
Route +DC2_PWR_SRC using 50 mil trace width and minimize
length.
Route OUT1 and OUT2 away from inductor and switch-node.
Sense Vout directly at output bulk cap.

MAX8778

PR130 309K/F
1
2
2 PR154 1
0_0402 POK2
EN2

PR141
1_0603
2

+5V_VCC2 PR111
10_0603
1
2

MAX8778

32
31
30
29
28
27
26
25

REFIN2
ILIM2
OUT2
SKIP#
POK2
EN2
UGATE2
PHASE2

35
34
33

PC132
.1U/25V/0603

PC121
0.1U/50V/0603_NC

PU8

BOOT1
LGATE1
PVCC
SECFB
GND
PGND
LGATE2
BOOT2

PR128
0_0402_NC

BYP
OUT1
FB1
ILIM1
POK1
EN1
UGATE1
PHASE1
PAD
PAD

17
18
19
20
21
22
23
24

POK1
EN1

9
10
11
12
13
14
15
16
37
36

PAD
PAD
PAD

S1

PC190
4700P/50V/0603_NC

1
PR131
249K_0402

PL5

1.0UH_SIL104_11A/6mohm
+1.05V_VCCP_P
2
1

1.05V_LX

21.5V_DL

1G

PC142
.1U/25V/0603

D1

Rdson=30mOhm

150U/2V/ESR18

PC154

PQ11A
FDS8984

1.5V_LX

D1

PR127
0_0402_NC

+1.05V_VCCP

www.kythuatvitinh.com

PC147

D1
4

5.2UH_SIL104R_5.5A/22mohm
2
1
PL6

+1.5V_RUN_P

10U/6.3V/1206

PC105
1U/10V/0603

1
PQ11B
FDS8984

1.05V +/- 5%; f=300kHz


Dis. Thermal Design Current: 6.9A
Dis. Maximum Current: 9.8A
Dis. OCP: 12.36A

REF

2
PJP6
POWER_JP

D1

1G

PR124
0_0402
PR125
PR126
93.1K/F_0402_NC 105K_0402_NC
2
1
2

+1.5V_RUN

PR113
0_0402

PR129
0_0402

1.5V +/- 5% ; f=200kHz


Thermal Design Current: 2.3A
Maximum Current: 3.3A
OCP: 4.15A

Note:PC105 use
0.1uFfor Intersil,
Use 1uF for
MAX8778

+3.3V_RTC_LDO

+5V_VCC2

POK2

1.05V_RUN_PWRGD

POK1

1.5V_RUN_PWRGD

<38>
<38>

Title

QUANTA
COMPUTER
1.5V,1.05V

Size

Document Number
FM5

Date:

Monday, March 05, 2007

Rev
1A
Sheet
1

43

of

51

DC/DC +3V_ALW/+5V_ALW/+5V_ALW2 /+15V_ALW


Ton:OUT1/OUT2 Switching Frequency
VDD 200kHz/300kHz
OPEN (REF): 400kHz/300kHz
GND: 400kHz/500kHz

Place these CAPs


close to FETs
No Install PR79 for ISL6236
Install PR79=0Ohm for MAX8778

+DC1_PWR_SRC

Place these CAPs


close to FETs

No Install for ISL6236


Install 10 ohm for MAX8778

PC79

PR72
PR167
0_0402_NC 0_0402

+3.3V_ALW

REFIN2
ILIM2
PU6
OUT2
SKIP#
MAX8778ETJ+
POK2
MAX8778
EN2
UGATE2
PHASE2

32
31
30
29
28
27
26
25

2
POK2

+3.3V_ALWP
C

PC68
PR164
0_0603

1 PR81
2
324K/F_0402

+5V_LX

BYP
OUT1
FB1
ILIM1
POK1
EN1
UGATE1
PHASE1
PAD
PAD

PL7
1.5uH_SIL1055RC-12.5A/7.6mOhm
1
2

+3.3V_LX

PR71
309K/F_0402
1
2

.1U/50V/0603

3
2
1

9
10
11
12
POK1 13
14
15
16
37
36

1
2
3

+5V_ALWP

PL10
2.2uH_SIQH125A-13A/5.5mOhm
1
2

+5V_ALWP

2
1

PR166
100K_0402_NC

POK2
2

2
1

PR82
100K_0402

POK1

BAT54S-7-F

ALW_PWRGD_3V_5V

SJ3
1

+15V_ALWP

1
PC169

PR175
200K/F_0402

PR178
39K/F_0402
2

.1U/50V/0603

Jump20X10

<34> THERM_STP#

LDO = 5V (LDOREFIN = GND) or


LDOREFIN RANGE: 0.3V to 2V
LDO = 2x LDOREFIN

<28> ALWON

PR76
1K/F_0402
2
1

<28>

2
1

+15V_ALW

PR165
0_0402

3
2
1

PC86
BAT54S-7-F
.1U/50V/0603
PD12
1

PD7
SDM10K45

+3.3V_ALWP +3.3V_ALWP

.1U/50V/0603

PC75

Jump20X10

+ PC69
330U/6.3V/ESR25

PR69
0_0603_NC

PC73
.1U/50V/0603_NC

SJ4

PC87
.1U/50V/0603
32
1

Rdson=12.5mOhm

1
2
3

+5V_ALW2

PD13
1

5
6
7
8
9

PC74
.1U/50V/0603

PQ21
FDS6680AS

PR70
1_0603
2

17
18
19
20
21
22
23
24

PR83
1_0603
2

+3.3V_DL4

35
34
33

3
2
1

PR84
0_0402

0_0402
PR187

BOOT1
LGATE1
PVCC
SECFB
GND
PGND
LGATE2
BOOT2

PC90
.1U/50V/0603

4+5V_DL

PAD
PAD
PAD

PQ24
FDS6680AS
Rdson=12.5mOhm

PR80
0_0402_NC
1

2
1

.1U/50V/0603

PR185
240_0805_NC

PC93
330U/6.3V/ESR25

9
8
7
6
5

www.kythuatvitinh.com
PC94

8
7
6
5
4
3
2
1

+5V_DH

PQ22
FDS8878

PQ25
FDS8878

+3.3V_DH 4

.1U/50V/0603_NC
PJP12
POWER_JP

LDOREFIN
LDO
VIN
VREF3
EN_LDO
VCC
TON
REF

8
7
6
5

PC88

PR171
0_0402_NC

+5V_ALW

1
1

PR68
0_0402_NC
5
6
7
8

1
2

PR173
PC80
0_0402_NC
PC78
.1U/10V/0402
1
2

FBMH4532HM681
FL11

PC186
1U/10V/0603

PR79
0_0402_NC

1U/10V/0603

2
1

+3.3V_ALW2

PC81
4.7U/10V/1206

2200P/50V/0402

PC83
2

+5V_VCC1

.1U/50V/0603

2
1

PR176
10_0603
2

FBMH4532HM681
FL12

.1U/50V/0603

PC84

+5V_ALW2

PR181
0_0805

PR180
0_0805

2200P/50V/0402

2
1

PC85

3.3 Volt +/- 5%


Design Current:7.18A
Maximum current:10.25A
OCP: 12.36A

FBMH4532HM681
FL10

5 Volt +/- 5%
Design Current: 7.43 A
Maximum current:10.6A
OCP: 12.96A

PC82
.1U/50V/0603

1
2

PC178
+

10U/25V/1206_NC

PC177
+

10U/25V/1206

1
2

PC174
+

10U/25V/1206

PC172
+

+PWR_SRC

PJP11
POWER_JP
1
2

10U/25V/1206

PR77
200K_0402

PR75
0_0402
2

REFIN2: DYNAMIC 0 to 2V
REFIN2 = RTC: 1.05V Fixed
REFIN2 = VCC: 3.3V Fixed

Title

QUANTA
COMPUTER
3VALW,5V,3V, power on

Size

Document Number
FM5

Date:

Monday, March 05, 2007

Rev
1A
Sheet
1

44

of

51

+PWR_SRC
FL3
FBMH3225HM202NT
1
2

+CPU_PWR_SRC

FL4
FBMH3225HM202NT
1
2

+CPU_PWR_SRC

1
2

2200P/50V0402

.1U/50V/0603

1
2

10U/25V/1206

2
1

10U/25V/1206

2
1

10U/25V/1206

2
1

10U/25V/1206

1
2

2200P/50V0402

1
2

.1U/50V/0603

2
1

220U/2V/ESR7

220U/2V/ESR7

1
2

1
1

.1U/16V/0603

2
2
1

PC38
1

PC193

.1U/50V/0603

PC194

PC37

PC122

1
2

PC134
1.5nF/50V/0603_NC

PC123

2200P/50V0402

BOOT

2
VCC
(VDD)
PWM
FCCM
(SKIP#)
GND
PAD

CSP2

22

PC24
.22U/10V/0603

PC119

10U/25V/1206

DPRSTP#

PU2
ISEN2

PC116

10U/25V/1206

37

+CPU_PWR_SRC

10U/25V/1206

VID6

MAX8786_PWM2

PR134
2.2/F/1206_NC

10U/25V/1206

VID5

34

26

PWM2

PQ34
FDS6298

PR28
0_0603

PC34
1U/10V/0805

2200P/50V0402

33

CPU_VID6

(CSP1)

2
PR107

2200P/50V0402

1
2

.1U/50V/0603

2
1

10U/25V/1206

2
1

10U/25V/1206

2
1

10U/25V/1206

2
1

10U/25V/1206

PR22

1_0402_NC

+ PC150
220U/2V/ESR7_NC

PR98
0_0402

+ PC61
220U/2V/ESR7_NC

VSUM

PC151

PR147
7.68K/F_0805_NC

.1U/16V/0603
2

PC35
.22U/10V/0603
1
2

PR48
2.2/F/1206_NC

2.2K/F_0603
PR150
2

PC98

PC47
1.5nF/50V/0603_NC

PC197

+VCC_CORE

1
2

1
1
2

PQ7
SI7336ADP

PC198

PR153
0_0402

.1U/16V/0603

LG3

PC125

MAX8791GTA+

PC39

PL2
0.45U_ETQP4LR45XFC_25A_20%
2
1

LGTE

PC40

PH3

PC140
1.5nF/50V/0603_NC

PC124

PC26
.22U/10V/0603

PHSE

PC120
2200P/50V0402

1
UG3

PC117
.1U/50V/0603

5
6
7
8
9
1
2
3

1
1

UGTE

3
9

BOOT

PC9
330P/50V/0603_NC
1

.1U/16V/0603

VO

PR105
22.1K/F_0402

VCC
(VDD)
PWM
FCCM
(SKIP#)
GND
PAD

5
6
7
8
9

2
6

PC185

PC184

FCCM

PR138
2.2/F/1206_NC

PR31
1_0402_NC

220U/2V/ESR7

220U/2V/ESR7

1
2

.1U/16V/0603

1 2

5
6
7
8
9
1
2
3

+ PC148

1
PU5

.1U/16V/0603

PQ33
FDS6298

PR37
0_0603

PC104
1U/10V/0805

PR108
0_0402

+ PC60

+5V_ALW

PR25
PC99
6.8K_0402_NC
PR26
.1U/10V/0402
15K/F_0402_NC

PR24
0_0402_NC

PR145
7.68K/F_0805_NC

PR3
0_0402

PC12
1000P/50V/0402_NC
2
1

PC153

+CPU_PWR_SRC

1
2
3

.01U/25V/0402

PC36
.22U/10V/0603
1
2

PWR_MON <34>

1
PC10

PR148
2.2K/F_0603
2

CSN2

PR27
0_0402_NC

CSN2

CSN3

VO

16

(CSN1) VO

PR99
1K/F_0402
2
1

PR112
17.8K/F_0402

VW (TRC)

PR46
2.2/F/1206_NC

PR151
0_0402

PR15
2.43K/F_0402_NC

PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD

1
2
1
2
PC96
PR97
1500P/50V/0402_NC
82.5K/F_0402_NC

2
71.5K/F_0402

41
42
43
44
45
46
47
48
49
50

1
PR9

+VCC_CORE

PC46
1.5nF/50V/0603_NC

VSUM

COMP (REF)

PL3
0.45U_ETQP4LR45XFC_25A_20%
2
1

RDS(ON)=4m ohm

PC19

FB (TIME)

DROOP
15 (CSN3)
DFB
(CSN2)

6.49K/F_0603
PR102
2.2K/F_0402_NC

10
1

PC97
680P/50V/0402_NC

2
2

LG2

PQ8
SI7336ADP

MAX8786GTL+
PR101

14

2
PR5

1
2
PR106
332/F_0402_NC

PH2

VSUM

17

VSUM

(PWR)

VDIFF (VPS)

1
4.53K/F_0402_NC

RTN (GNDS)

11

B=3435

1
2
PC18
1000P/50V/0402
1
10_0603

OCSET
(ILIMPK)

4.99K/F_0402 13
PR103

.033U/16V/0402_NC

VSEN (FBS)

PR16
10K_0603

PC16
1000P/50V/0402

LGTE

UG2

Intersil Note: PR155


change to 13.7K for
60A OCP. We heard
Santa Rosa CPU might
have ~50A peak
current with 10uS
duration

PR100
11.5K/F_0402_NC
1
2

VR_ON (SHDN#)

PC21

35

CLK_EN#

PHSE

CSP3

PR10
226K/F_0402
2
1

38

12

21

(CSP3)

.012U/50V/0603_NC

PAD

ISEN3

UGTE

MAX8791GTA+

PSI#

PWR_MON (PGD_IN)

3
9

MAX8786_ PWM3

25

PC15

PR19
1
0_0402

CLK_ENABLE#

PWM3

DPRSLPVR

PR18
1
0_0402

2
6

FCCM

.33U/16V/0603_NC

36
1
499/F_0402
1
2 PR17
1
0_0402
2
T13

(CSP2)

PR20
1
2
0_0402_NC

PR6
10_0603

1
2
3

2
39

CPU_VID5

PC149
+

RDS(ON)=12.5m ohm

.1U/50V/0603

VID4

PC59
+

+5V_ALW

VID3

32

2 PR29

<3> H_PSI#

<4> VSSSENSE

PR30
0_0402

PC152

CSP1

1
2
3

31

CPU_VID4

MAX8786_PWM1

23

CPU_VID3

27

ISEN1

VID2

PWM1

(DRSKP#)

VID1

FCCM

PC191

VO

SOFT (CCV)

24

PC192

PR152
0_0402

VSUM

FCCM

PC128

+VCC_CORE

PC111
.22U/10V/0603
1
2

PR146
7.68K/F_0805_NC

5
6
7
8
9

3V3
(V3P3)

NTC (THRM)

30

PR149
2.2K/F_0603
1
2

PGOOD
(IMVPOK)

RBIAS (OSC)

VIN
(NC)

VDD
(VCC)

VID0

PC129

PC48
1.5nF/50V/0603_NC

PR47
2.2/F/1206_NC

<13,28,38>

PC42

PL4
0.45U_ETQP4LR45XFC_25A_20%
2
1

40

18

20

19

VSS
(GND)

VR_TT#
(VRHOT#)

29

PC138
1.5nF/50V/0603_NC

PC41

www.kythuatvitinh.com
PR14
<4> VID6
10K_0402_NC

<6,13> DPRSLPVR

28

PC113

1
2

<4> VID5

<4> VID4

<3,6,11> H_DPRSTP#

<4> VCCSENSE

LG1

2
1
<4> VID3

<28> IMVP_VR_ON

PH1

PQ9
SI7336ADP
IMVP_PWRGD

CPU_VID2

<4> VID2

9,38> RUNPWROK

LGTE

PU1
PR114
13K/F_0402

PR12
1
2
0_0402
PR13
143K/F_0402
2
1
PR11
2 PR4
1
2
1
0_0402_NC
100K_0402_NC
470P/50V/0402
1
2
PC13
2
1
CPU_VID0
PC6
<4> VID0
CPU_VID1
2200P/50V/0402_NC
<4> VID1

PC14
1U/10V/0603_NC

PHSE

<29> IMVP6_PROCHOT#

<34> PWR_MON

UG1

PR23
1.91K/F_0603

PR115
0_0603

MAX8791GTA+

PC33
1U/10V/0805

3
9

UGTE

5
6
7
8
9

FCCM

PC23
.22U/10V/0603

BOOT

1
2
6

VCC
(VDD)
PWM
FCCM
(SKIP#)
GND
PAD

PC107

PU3
5

+3.3V_RUN

PC27
.01U/25V/0402_NC

2
1
2
3

PR135
2.2/F/1206_NC

1
PR116
10_0603

PQ35
FDS6298

PR21
0_0603

PC103
1U/10V/0805

2
1

Intersil Note: PIN 39 is


+3.3V_RUN. I would like to
suggest this change to
+3.3V_ALW. It will be the same
as +5V_ALW sequence which is
for ISL6260C and drivers

PR109
10_0603_NC

+5V_ALW

5
6
7
8
9

+5V_ALW

VO
CSN3
4

PHASE 3 populate
Title

QUANTA
COMPUTER
CPU POWER

Size

Document Number
FM5

Date:

Tuesday, March 06, 2007

Rev
1A
Sheet

45
H

of

51

POWER STATES
SLP
S3#

SLP
S4#

SLP
S5#

S4
STATE#

SLP
M#

S0 (Full ON) / M0

HIGH

HIGH

HIGH

HIGH

HIGH

S3 (Suspend to RAM) / M1

LOW

HIGH

HIGH

HIGH

S4 (Suspend to DISK) / M1

LOW

HIGH

HIGH

S5 (SOFT OFF) / M1

LOW

HIGH

LOW

Signal
State

ALWAYS
PLANE

M
PLANE

SUS
PLANE

RUN
PLANE

ON

ON

ON

ON

ON

Right Top

HIGH

ON

ON

ON

OFF

ON

Right Bottom

LOW

HIGH

ON

ON

ON

OFF

ON

Side TOP

LOW

HIGH

ON

ON

ON

OFF

ON

Side Bottom

CLOCKS

DESTINATION

USB PORT#

ICH8-M

S3 (Suspend to RAM) / M-OFF

LOW

HIGH

HIGH

HIGH

LOW

ON

OFF

ON

OFF

OFF

Ext. USB TOP

S4 (Suspend to DISK) / M-OFF

LOW

LOW

HIGH

LOW

LOW

ON

OFF

OFF

OFF

OFF

DIgital Camera

S5 (SOFT OFF) / M-OFF

LOW

LOW

LOW

LOW

LOW

ON

OFF

OFF

OFF

OFF

Express Card

WPAN/Bluetooth

Ext. USB Bottom

WWAN

None

None

None

None

PM TABLE
C

+3.3V_ALW

+1.8V_SUS

+0.9V_DDR_VTT

+3.3V_RTC_LDO

+1.8V_LOM

+1.05V_VCCP

+DC_IN

+2.5V_RUN

+DC_IN_SS

+3.3V_WLAN

+3.3V_LAN

+1.25V_RUN

+5V_MOD

+PWR_SRC

+5V_ALW

+3.3V_SUS

+1.5V_CARD

+5V_RUN

+RTC_CELL

+15V_ALW

+5V_SUS

+1.5V_RUN

+5V_SPK_AMP

+3.3V_CARD

+CPU_PWR_SRC

+3.3V_CARDAUX

+VCC_CORE

+3.3V_R5C832

+VDDA

State

ECE 5011

+3.3V_RUN

ON

ON

ON

ON

ON

ON

OFF

ON

S5 S4/AC

ON

OFF

OFF

ON

S5 S4/AC don't exist

OFF

OFF

OFF

ON

S3

www.kythuatvitinh.com
power
plane

S0

+3.3V_RUN_CARD

PCI EXPRESS

PCI TABLE
PCI DEVICE

IDSEL REQ#/GNT#

PIRQ

BCM4401B

AD16

REQ#0 / GNT#0

PIRQB

R5C833

AD17

REQ#1 / GNT#1 PIRQC: Card reader


PIEQD: 1394

DESTINATION

Lane 1

MINI CARD-1 WWAN

Lane 2

MINI CARD-2 WLAN

Lane 3

MINI CARD-3 WPAN

Lane 4

Express Card

Lane 5

None

Lane 6

None

Title

QUANTA
COMPUTER
Schematic Block Diagram1

Size

Document Number
C & G UMA

Date:

Monday, March 05, 2007

Rev
1A
Sheet
1

46

of

51

+3.3V_SUS

Express Card
7

WLAN
30

WWAN
32

30

32

WPAN
30

+3.3V_RUN

32

+3.3V_RUN

197

DIMM 0

2.2K

2.2K

AJ26 ICH_SMBCLK

AD19 ICH_SMBDATA

AE19

AC17

2N7002
2.2K

ICH8-M

0A0h

195

2.2K

197

MEM_SCLK

MEM_SDATA 195

DIMM 1

0A4h

+3.3V_SUS

10K

10K

AMT_SMBDAT
+3.3V_RUN

+3.3V_ALW

AMT_SMBCLK

+3.3V_RUN

2N7002
2.2K

2.2K

2.2K

13

CKG_SMBCLK

2.2K
B

CLK_SCLK

16

www.kythuatvitinh.com
12

CKG_SMBDAT

CLK GEN

0D2h

GUARDIAN

05Eh

CLK_SDATA 17

+3.3V_ALW

4.7K

4.7K

100 THRM_SMBCLK

12

99

11

THRM_SMBDAT

+3.3V_ALW

SIO
MEC5025

8.2K

8.2K

LCD_SMBCLK

S39

LCD_SMBDAT

S40

Inverter

A9H:Contrast
AAH:Backlight

+3.3V_ALW

+5V_ALW
10

8.2K
8
7

8.2K
100

PBAT_SMBCLK

CHARGER

Primary
BATTERY

016h
Title

Schematic Block Diagram1

100
1

QUANTA
COMPUTER

3
4

PBAT_SMBDAT

012h

Size

Document Number
C & G UMA

Date:

Monday, March 05, 2007


7

Rev
1A
Sheet

47
8

of

51

ECN Number

Item Id

Rev.

Model

Item

Page

Date

Issue Description

Solution Description

C/G

39-45

7/13/2006

DISCRETE

13,29

9/20/2006

S3 resume fail

Move PLTRST_DELAY# from EC to ICH8

11

9/20/2006

2nd SATA HDD can't recognize

Move 2nd SATA from port 1 to port 2

Update PWR schematics

38

9/20/2006

Gfx card timing error

Disconnect GFX_PWRGD to system ( Delete R463 )

38

9/20/2006

Gfx card timing error

Disconnect +1.8V_RUN detect circuit to system ( Delete Q47 )

39-45

9/21/2006

23

9/21/2006

Update PWR schematics


Add +1.8V_RUN for SATA buffer test (CON4.20-21-22-42-43-44)
Update WLAN LED implementation.With the current implementation, there is
a possibility for backdrive from the WLAN LED control signal to +3.3V_RUN
while in S3 / S4 / S5. With the voltage rail being +3.3V_WLAN, there is a
high probability that the LED will be illuminated while in S3 / S4 / S5.

Please change the WLAN LED implementation to advice from Dell.

37

10/2/2006

13

10/2/2006

Intel has advised that the pull-up on LINKALERT# be depopulated and that
the pull-up on GPIO14 be 8.2k. Please update.

Depop R247 & change R227 from 10K ohm to 8.2K ohm

10

28,33

10/11/2006

In order to leverage the M07 implementation, the sniffer LED circuit needs
to be modified. The MEC5025 pins are being changed from active high to
active low.

Change back VC08 design, rename SNIFFER_YELLOW to SNIFFER_YELLOW#,


SNIFFER_GREEN to SNIFFER_GREEN# and remove R507 and R510.

11

28,29

10/11/2006

Move DOCK_SMB_PME from MEC5025 SGPIO37 to ECE5018/5011


GPIOC0.Move DOCK_SMB_ALERT# from ECE5018/5011 GPIOC0 to
MEC5025 SGPIO37

DOCK_SMB_PME# should be pulled up to +3.3V_ALW


DOCK_SMB_ALERT# should be pulled up to +5V_ALW

Remove 3.3V_LAN_PWRGD circuit from page 38


Delete 3.3V_LAN_PWRGD from MEC5025 pin 14
Add a connection from the MEC5025 pin 14 and tie to GND.

www.kythuatvitinh.com
12

28,38

10/11/2006

13

28

10/11/2006

Move ALW_PWRGD_3V_5V from MEC5025 pin 18 to pin 29

14

13

10/11/2006

1) Move SIO_EXT_SCI# from ICH pin AG22 to ICH pin AC19


2) Delete R242 ( delete DOCKED# signal )

15

13

10/11/2006

16

24

10/16/2006

17

23,29

10/18/2006

Add ATI_Intel to MEC5025 pin 14 and tie to GND.This connection


should be labeled ATI_Intel.

Reserve LOM_SMBALERT# (ICH8 AG22) & PU resister


Change WPAN USB port from USBP7 to USBP4

18

12,14

10/18/2006

19

37

20

34

10/23/2006

21

28

10/23/2006

10/23/2006

24

To resolve this issue, please use the HDDC_EN and MODC_EN circuits that are
attached below. These new circuits resemble closely our other load switch
circuits, but require an additional FET and changes the sense of the HDDC_EN
and MODC_EN signals to active high. Please note the use of +5V_ALW2 on these
circuits. The +5V_ALW2 voltage comes directly from the LDO output on the
3V/5V switcher in your M08 design.

WWAN Noise - ICH improvements.


Add one .1 uF cap on each USB OC (over current) trace near the ICH.
Add four .1uF caps in parellel to C813 close to the ICH pins.
Add four .1uF caps in parellel to C825 close to the ICH pins.

Add C871~C878 for USB OC.


Add C867~C870 in parellel to C825.
Add C748,C864~C866 in parellel to C813.

Use LED_MASK# to control BT LED to prevent leakage

Add R336 & change Q13 to BJT

Change pull-up rail on 5V_CAL_SIO1# to +3.3V_SUS.


Feedback from SMSC has indicated that the pull-up rail on 5V_CAL_SIO1#
needs to change from +5V_SUS to +3.3V_SUS.This is necessary because the
GPIO on the EMC4001 is 3V tolerant, not 5V.

Pullup is at reference designator R298.

Due to the power on defaults of the MEC5025, the pull-downs on the KSI
lines of the MEC5025 need to be stronger, to avoid pulses from powering on
certain power rails. Please do the following:
1. Change pull-down on SUS_ON to 2.7k
2. Change pull-down on RUN_ON to 2.7k

22

Modify HDDC_EN and MODC_EN Circuits to Resolve Glitch Issue.


unintentionally for a brief moment.With the current Dawson design, it has
been shown that the +15V_ALW rail comes up before the +3V_ALW rail on
the original HDDC_EN and MODC_EN circuits. This can cause a
momentary glitch at the gate of the power FET, which may cause the FET
to turn on unintentionally for a brief moment.

Change R355,R358 to 2.7K


A

Add SMBus isolation circuitry for WLAN.Add isolation circuitry for SMBus on
WLAN.

10/23/2006

Title

QUANTA
COMPUTER
Change List

Size

Document Number
JM7B

Date:

Monday, March 05, 2007

Rev
1A
Sheet
1

49

of

Model
C/G
DISCRETE

Item

Page

Date

ECN Number

Item Id

Rev.

Issue Description

23

17

10/26/2006

Chipset side spec. Differetial CLK raise/fall slew rate is 2.5~8 V/ns, only
express card and mini card is 0.6~4V/ns. BITCLK rise/fall slew rate in 1-3
V/ns &

24

37

10/26/2006

Change LED control method

25

37

10/26/2006

Add OR gate for BT_ACTIVE

26

13

10/26/2006

M08 GPIO A14 update. Original EC5011 pin66 CCD_VDD_ON move to IC8
pinAD10 GPIO48 and add 100K ohm pull down.

27

25

10/26/2006

For Comm team suggestion ( GG list ), pop C217 for WWAN

28

39 - 45

10/31/2006

PWR team updat schemtics - 10/23

Solution Description
Change serial resistors ( PR4,PR5,PR10,PR12,PR13 ) to meet the CLK SPEC

Move CCD_VDD_ON from EC5011 pin66to IC8


pin AD10 GPIO48 and add 100K ohm pull down.

www.kythuatvitinh.com
B

Title

QUANTA
COMPUTER
Change List

Size

Document Number
JM7B

Date:

Monday, March 05, 2007

Rev
1A
Sheet
1

50

of

Model
F

Item

Page

Date

ECN Number

Item Id

Rev.

Issue Description

C/G

29

24 - 25

11/1/2006

For EMI request, add RC circuit for Mini card clk request

Add R543, C880, R186, C649, R544, C181

DISCRETE

30

39

11/1/2006

For +3.3V_RUN inrush current, it may over OCP ( 12.36 A )

Change PC58 from 470 pF to 6800 pF


Change C306, 307 to 0.033uF/16V/X7R/1206 & C326, C329 to 1uF/16V/X7R/1207
Reserved the AUD_AMP_MUTE# for 'PO' noise

31

32

11/3/2006

For AP - THN+D fail, change C306, 307 to 0.033uF/16V/X7R/1206 & C326, C329
to 1uF/16V/X7R/1206

32

32

11/3/2006

'PO' noise in resume from S3,S4,S5

33

39 - 45

11/09/2006

PWR team updat schemtics - 11/08

34

17

11/09/2006

Change R44 to 2.2K per Intel recommend value.

35

12 - 13

11/21/2006

Due to Intel-ICH8 uses GPIO20 pin AE11 as an Internal Strapping at power up

36

13

11/21/2006

GPIO18 is default as an output at power up, it will drive 1Hz output at


power up. Per Intel this GPIO could not be connected to GND

Add 4.7K series - R547 resistor to separate it

37

32

11/22/2006

There is potential back drive from the codec DVdd back to the AVdd supply
due to an internal ESD diode

add 100kohm resistor (R253) between pin 40 and +3.3V_RUN and a 1000pF cap
(C643 below) from Pin 40 to ground

38

35 - 36

11/28/2006

GG list -- COMM team request

Move PCIE_MCARD2_DET# from GPIO20 to ICH8 GPIO5/PIRQH# pin B3.

1.Change capacitor for U5 pin 79, 94,106 (VDDIO) (C18, C16, C25) to 47pF.
2.Change those three capacitors (C27, C37,C34) to 47pF
3.Add C644 - 47pF capacitor by the pin 57 of U5
4.Change L7 to 0805 package -BK2125LM152. & C23 to 47 pF
5.Add Ferrite Bead BK1608LM152 on 1.8V to EPHY_AVDD pin 57

39
D

28-29

11/28/2006

Move DOCK_SMB_PME from MEC5025 SGPIO37 to ECE5018/5011


GPIOC0.Move DOCK_SMB_ALERT# from ECE5018/5011 GPIOC0 to
MEC5025 SGPIO37

DOCK_SMB_PME# should be pulled up to +5V_ALW


DOCK_SMB_ALERT# should be pulled up to +3.3V_ALW

www.kythuatvitinh.com
40

24

12/01/2006

GG list -- Seperate debug port with MINI-PCI if not necessary

Add 4 0ohm resistors for these pins

41

24 - 25

12/01/2006

GG list -- Delete decoupling cap

Delete C222 & C424

42

39 - 45

12/04/2006

PWR team updat schemtics - 12/04

43

32

12/08/2006

GG List -- Change audio AMP to TI solution

1.Change codec to TPA9040A4

2.Pop R505, C619 & C614; depop R506, R504 & R497

44

31

12/13/2006

GG List -- Change power source for LED of dash board

45

39 - 45

12/19/2006

PWR team updat schemtics - 12/19

Change JTP1.9 from +3.3V_RUN to +5V_ALW

46

28

12/25/2006

GG List -- Remove EC5025 pin15 GPIO4 AUD_AMP_MUTE# circuit.

NC R538

47

34

12/25/2006

GG List -- Add THERMATRIP_VGA# function

Pop R441,442,443 and Q35, C568 for THERMATRIP_VGA# trip.

48

33

12/28/2006

Modify CCD power control soft start function

Change C403 , R284 connect method

Title

QUANTA
COMPUTER

EMI & Screw hole

Size

Document Number
C & G UMA

Date:

Monday, March 05, 2007

Rev
2A
Sheet

50
1

of

51

Date

ECN Number

Item Id

Rev.

Item

Page

C/G

49

22

1/11/2006

XD card detect function error

DISCRETE

50

29

1/11/2006

Base on A16 GPIO : Change net name from BID2 to CHIPSET_ID1

51

37

1/24/2007

Add 0ohm_NC(R571) resistor pad connected from Coex1_BT_Active_MINI to


Coex1_BT_Active

52

32

1/24/2007

Audio solution for pass EMI 225MHz and 451MHz radiation emission test.

Added R560, R561, R562 and R563 on AUD_SPK_L1, AUD_SPK_L2, AUD_SPK_R1,


AUD_SPK_R2 trace

52

33

1/24/2007

Audio solution for pass EMI 225MHz and 451MHz radiation emission test.

Added R564, R565, R566 and R567 on AUD_LINE_OUT,AUD_HP_OUT

53

13

1/24/2007

GG List -- CCD_ON pull down R258 100K NC.

54

37

2/5/2007

Blue LED brightness is too high

Change R30,R50,R75,R64 & R36 from 220 ohm to 330 ohm

55

30

2/12/2007

Prevent SPI CLK overshoot/undershoot issue

Add C896 for RC circuit but not pop it

56

39 - 45

2/12/2007

PWR team updat schemtics - 2/12

57

29

2/12/2007

GG List -- CIR function intermidiate issue

58

44

3/1/2007

PWR team updat schemtics - 3/1

Model
F

Issue Description

ECE5021 pin7 PWRGD need to pull-down to GND with 0 ohm - Add R568 PD resistor
& R569 series resistor ( NC )

www.kythuatvitinh.com
59

17

3/2/2007

Per TDC COMM team request - Change L65 to

Fine tune 14M CLK - Change R57 from 33 to 15 ohm & L65 to BLM18SG260

60

04

3/2/2007

Per reliability issue - Move C98 to C249

De-pop C98 & pop C249

Title

QUANTA
COMPUTER

EMI & Screw hole

Size

Document Number
C & G UMA

Date:

Wednesday, March 07, 2007

Rev
2A
Sheet

51
1

of

51