MITSUBISHI<Dig.Ana.

INTERFACE>

M62352P,FP,GP
8-BIT 12CH D-A CONVERTER WITH BUFFER AMPLIFIERS
DESCRIPTION
The M62352 is an integrated circuit semiconductor of CMOS structure with 12 channels of built-in D-A converters with output buffer operational amplifiers. The 3-wire serial interface method is used for the transfer format mum wiring. It is able to cascading serial use with Do terminal. The output buffer operational amplifier operates in the whole voltage range from power supply to ground for both input/output.

PIN CONFIGURATION (TOP VIEW)

Vss 1 (VrefL) Ao3 2 Ao4 Ao5 Ao6
3 4 5 6 7 8 20 19 18 17 16 15 14 13 12 11

GND Ao2 Ao1 DI CLK LD DO Ao12 Ao11 Vcc

FEATURES
12bit serial data input(3-wire serial data transfer method) Highly stable output buffer operational amplifier allow operation in the all voltage range from power supply to ground.

Ao7 Ao8 Ao9

Ao10 9 VDD 10 (VrefU)

APPLICATION
Adjustment/control of industrial or home-use electronic equipment,such as VTR camera,VTR set,TV,and CRT display.

Outline 20P4B(P) 20P2N-A(FP) 20P2E-A(GP)

BLOCK DIAGRAM
GND Ao2 Ao1 DI CLK LD Do Ao12 Ao11 Vcc

20

19
8-BIT R-2R D-A
Ch2 1

18
-

17

16

15

14

13
-

12
D-A
11

11

12-BIT SHIFT REGISTER D-A

D0 1 2 3 4 5 6 D7 D8 9 10 D11

D-A
12

8-BIT LATCH ..... (12)

L (8) (12) ADDRESS DECODER .....

(12)

8-BIT LATCH
Ch3 4

L
5

L
6

L
7

L
8

L
9

L
10

L D-A -

8-BIT R-2R D-A BUFFER OP AMP -

D-A -

D-A -

D-A -

D-A -

D-A -

D-A -

1
Vss (VrefL)

2
Ao3

3
Ao4

4
Ao5

5
Ao6

6
Ao7

7
Ao8

8
Ao9

9
Ao10

10
VDD (VrefU)

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MITSUBISHI<Dig.Ana.INTERFACE>

M62352P,FP,GP
8-BIT 12CH D-A CONVERTER WITH BUFFER AMPLIFIERS
EXPLANATION OF TERMINALS
Pin No. 17 14 16 15 18 19 2 3 4 5 6 7 8 9 12 13 11 20 10 1 Symbol DI DO CLK LD Ao1 Ao2 Ao3 Ao4 Ao5 Ao6 Ao7 Ao8 Ao9 Ao10 Ao11 Ao12 Vcc GND VDD Vss Function Serial data input terminal Serial data output terminal Serial clock input terminal LD terminal input high level than latch circuit data load

8-bit D-A converter output terminal

Power supply terminal Digital and analog common GND D-A converter upper reference voltage input terminal D-A converter lower reference voltage input terminal

BLOCK DIAGRAM FOR EXPLANATION OF TERMINALS

Vcc GND

11
DI

20
12-BIT SHIFT REGISTER

17 14
D7 D8 D9 D10 D11 D0 D0 D1 D2 D3 D4 D5 D6

CLK 18

ADDRESS DECODER 8 12 ............... 1 2 3 4 12

15

LD

D0

............ 8-BIT LATCH 8-BIT R-2R D-A -

D7 ..............................................12 ..............................................

D0

............ 8-BIT LATCH 8-BIT R-2R D-A -

D7

...................................................................................................

10
VDD (VrefU)

18
Ao10

13
Ao12

1
VSS
(VrefL)

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M62352P,FP,GP
8-BIT 12CH D-A CONVERTER WITH BUFFER AMPLIFIERS
DIGITAL DATA FORMAT
LAST LSB D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 FIRST MSB D11

DAC DATA

DAC SELECT DATA

D0 0 1 0 1 0 1 D8 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

D1 0 0 1 1 1 1 D9 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

D2 0 0 0 0 1 1 D10 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

D3 0 0 0 0 1 1 D11 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

D4 0 0 0 0 1 1

D5 0 0 0 0 1 1

D6 0 0 0 0 1 1

D7 0 0 0 0 1 1

D-A output (VrefU-VrefL)/256X1+VrefL (VrefU-VrefL)/256X2+VrefL (VrefU-VrefL)/256X3+VrefL (VrefU-VrefL)/256X4+VrefL (VrefU-VrefL)/256X255+VrefL VrefU *VrefU=VDD VrefL=Vss

DAC selection Dont care Ao1 selection Ao2 Ao3 Ao4 Ao5 Ao6 Ao7 Ao8 Ao9 Ao10 Ao11 Ao12 Dont care Dont care Dont care

TIMING CHART (MODEL)

MSB DI D11 D10 D9 D8 D2 D1

LSB D0

CLK

LD

D-A OUTPUT

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M62352P,FP,GP
8-BIT 12CH D-A CONVERTER WITH BUFFER AMPLIFIERS
ABSOLUTE MAXIMUM RATINGS
Symbol Vcc VDD VIN Vo Pd Topr Tstg Parameter Supply voltage D-A converter upper reference voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature Conditions Ratings -0.3~7.0 -0.3~7.0 -0.3~Vcc+0.3 -0.3~Vcc+0.3 350(P)/350(FP)/150(GP) -20~+85 -55~+125 Unit V V V V mV C C

ELECTRICAL CHARACTERISTICS Digital part(Vcc,VrefU=+5V10%,VccVrefU,GND,VrefL=0V,Ta=-20C~+85C, unless otherwise noted)

Symbol Vcc Icc IILK VIL VIH VOL VOH Parameter Supply voltage Circuit current Input leak current Input low voltage Input high voltage Output low voltage Output high voltage CLK=1MHz operation IOA=0A VIN=0~Vcc -10 0.8Vcc IOL=2.5mA IOH=-400A Vcc-0.4 0.4 Test conditions Min. 4.5 Limits Typ. 5.0 1.6 Max. 5.5 3.2 10 0.2Vcc Unit V mA A V V V V

Analog part(Vcc,VrefU=+5V10%,VccVrefU,Ta=-20C~+85C, unless otherwise noted)

Symbol Parameter Current dissipation D-A converter upper reference voltage range D-A converter lower reference voltage range Buffer amplifier output voltage range Buffer amplifier output drive range Differential nonlinearity error Nonlinearity error Zero code error Full scale error Output capacitive load Buffer amplifier output impedance 5 Test conditions VrefU=5V,VrefL=0V Data condition;at maximum current The output dose not necessarily be the value within the reference voltage setting range. The output value is determined by the buffer amplifier output voltage range(VAO) IOA=100A IOA=500A Upper side saturation voltage=0.3V Lower side saturation voltage=0.2V VrefU=4.79V VrefL=0.95V Vcc=5.5V(15mV/LSB) Without load(IOA=0) 3.5 Min. Limits Typ. 1.4 Max. 2.5 Unit mA

IDD

VDD

Vcc

V V V mA LSB LSB LSB LSB F

Vss VAO IAO SDL SL SZERO SFULL CO RO

GND 0.1 0.2 -1 -1.0 -1.5 -2 -2

Vcc-3.5 Vcc-0.1 Vcc-0.2 1 1.0 1.5 2 2 0.1

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M62352P,FP,GP
8-BIT 12CH D-A CONVERTER WITH BUFFER AMPLIFIERS
AC CHARACTERISTICS(Vcc,VrefU=+5V10%,VccVrefU,GND,VrefL=0V,Ta=-20~+85C, unless otherwise noted)
Symbol tCLK tCKH tCR tCF tDCH tCHD tCHL tLDC tLDH tDO tLDD Parameter Clock "L"pulse width Clock "H"pulse width Clock rise time Clock fall time Data setup time Data hold time LD setup time LD hold time LD "H" pulse width Data output delay time D-A output setting time CL100pF CL100pF VAQ:0.5 4.5V The time until the output becomes the final value of 1/2 LSB Test conditions Min 200 200 Limits Typ Max Unit ns ns ns ns ns ns ns ns ns ns s

200 200 30 60 200 100 100 70

350 300

TIMING CHART
tCR tCKH tCF

CLK tCKL

DI tDCH tCHD tLDH tCHL LD tLDC

tLDD D-A OUTPUT

tDO DO OUTPUT

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M62352P,FP,GP
8-BIT 12CH D-A CONVERTER WITH BUFFER AMPLIFIERS
TYPICAL CHARACTERISTICS
UPPER SIDE SATURATION VOLTAGE VS. OUTPUT SOURCE CURRENT LOWER SIDE SATURATION VOLTAGE VS. OUTPUT SINK CURRENT

150

150

100

100

50

50

0 0 200 400 600 800 1000

OUTPUT SOURCE CURRENT IAOD(A)

0 0 200 400 600 800 1000

OUTPUT SINK CURRENT IAOD(A)

SATURATION VOLTAGE VS.OUTPUT CURRENT

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