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Compal Confidential
2

PEW76/86/96 M/B Schematics Document


AMD Danube Only UMA
AMD Champlain Processor with RS880M/SB820M

2010-07-20
LA6552P REV: 1.0

2010/04/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/10/12

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Cover Page
Document Number

PEW/76/86/96 LA-6552P
Sheet

Thursday, July 22, 2010


E

of

45

Rev
B

Danube

Compal Confidential

AMD S1G4 Processor

PCB

Model Name : PEW96


File Name : LA-6552P
P/N : DA60000IM10

ZZZ

LA-6552P MB Rev0: DA60000IM00


LA-6552P MB Rev1: DA60000IM10
LA-6552P MB Rev1: DAZ0FQ00200

LA-6552P RE1 M/B

Memory BUS(DDR3)

uPGA-638 Package
Champlain page 6,7,8,9

204pin DDRIII-SO-DIMM X2

Dual Channel

BANK 0, 1, 2, 3

page 10,11

1.5V DDRIII 1066~1333MHz


1

Hyper Transport Link


16 x 16

LVDS
page 15

Thermal Sensor
ADM1032

ATI RS880M

page 8

CRT

uFCBGA-528

page 17
page 12,13,14

HDMI Conn.

page 27

USB
conn
X3

A link Express2
Gen1

page 16

page 15

CMOS
Camera

ATI SB820M
MINI Card 1

Broadcom
BCM57780

WLAN
page 26

GPP1

3.3V 48MHz

S-ATA

page 18,19,20,21,22

page 26

Bluetooth
Conn

Mini
card
(WL)X1

Card
Reader
RTS5137

USB port 7

USB port 8

USB port 6
2

USB

3.3V 24.576MHz/48Mhz

uFCBGA-605

LAN(GbE)

page 26

<Option>

USB port 0,1,2 USB port 5


2

page 27

HD Audio

Gen2

page 24

HDA Codec
ALC272X
page 30

GPP0

RJ45
LPC BUS

page 25

SATA HDD
Conn. page 23

SATA ODD
FFC Conn.
page 23

port 0

port 1

Audio AMP
page 31

LED
3

ENE KB926

Fan Control

page 29

page 28

page 32

Phone Jack x2
page 31

RTC CKT.
page 18

LID SW / MEDIA/B
page 28

Int.KBD

Touch Pad

Extend Card/B

page 29

page 29

1. USB X2

EC I/O Buffer

BIOS

page 29

2. ODD X1

page 29

Power On/Off CKT.


page 32

DC/DC Interface CKT.


4

page 33

Power Circuit
2010/04/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

page 34,35,36,37,38
39,40,41,42

2010/10/12

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Block Diagrams
Document Number

PEW/76/86/96 LA-6552P
Sheet

Thursday, July 22, 2010


E

of

45

Rev
B

32.768K Hz

RTC

MEM_MA_CLK1_P/N
MEM_MA_CLK7_P/N

A_SODIMM

MEM_MB_CLK1_P/N
MEM_MB_CLK7_P/N

B_SODIMM

S1G4
CPU SOCKET

1066MHz

SATA

ATI
SB
SB820M

CPU_CLKP/N
200MHz

CLK_SBLINK_BCLK
100MHz

AMD

AMD

1066MHz

25MHz

AMD

CLK_NBHT

Internal CLK GEN.

ATI
NB
RS880M

100MHz

CLK_48M_SD
48MHz
CLK_PCIE_WWAN
100MHz

CLK_PCIE_MINI1
100MHz
CLK_PCIE_LAN

100MHz

CardReader
RTS5137

WWAN
Mini PCI Socket

WLAN
Mini PCI Socket

GbE LAN
BCM
57780

Compal Secret Data

Security Classification
2010/04/12

Issued Date

2010/10/12

Deciphered Date

Title

CLOCK DISTRIBUTION

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom PEW/76/86/96
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Rev
B

LA-6552P
Sheet

Thursday, July 22, 2010


1

of

45

SIGNAL

STATE

Voltage Rails

SLP_S1# SLP_S3# SLP_S4# SLP_S5#

+VALW

+V

+VS

Clock

HIGH

HIGH

HIGH

HIGH

ON

ON

ON

ON

Power Plane

Description

S1

S3

S5

S1(Power On Suspend)

LOW

HIGH

HIGH

HIGH

ON

ON

ON

LOW

VIN

Adapter power supply (19V)

N/A

N/A

N/A

S3 (Suspend to RAM)

LOW

LOW

HIGH

HIGH

ON

ON

OFF

OFF

B+

AC or battery power rail for power circuit.

N/A

N/A

N/A

+CPU_CORE

Core voltage for CPU (1.375-1.5V)

ON

OFF

OFF

S4 (Suspend to Disk)

LOW

LOW

LOW

HIGH

ON

OFF

OFF

OFF

+CPU_CORE_NB

Voltage for On-die Northbridge of CPU(0.8-1.1V)ON

OFF

OFF

S5 (Soft OFF)

LOW

LOW

LOW

LOW

ON

OFF

OFF

OFF

Full ON

+CPU_VDDR

1.05V switched power rail

ON

OFF

OFF

+0.75V

0.75V switched power rail for DDR terminator

ON

ON

OFF

+1.1VS

1.1V switched power rail for NB VDDC & VGA

ON

OFF

OFF

+1.5V

1.5V power rail for CPU VDDIO and DDR

ON

ON

OFF

Vcc
Ra/Rc/Re

Board ID / SKU ID Table for AD channel

+1.5VS

1.5V power rail for MINI Card

ON

OFF

OFF

Board ID

+1.8VS

1.8V switched power rail

ON

OFF

OFF

+2.5VS

2.5V for CPU_VDDA

ON

OFF

OFF

+3VALW

3.3V always on power rail

ON

ON

ON*

+3VS

3.3V switched power rail

ON

OFF

OFF

+3V_LAN

3.3V power rail for LAN

ON

ON

ON

+5VALW

5V always on power rail

ON

ON

ON*

+5VS

5V switched power rail

ON

OFF

OFF

+VSB

VSB always on power rail

ON

ON

ON*

0
1
2
3
4
5
6
7

+RTCVCC

RTC power

ON

ON

ON

3.3V +/- 5%
100K +/- 5%
Rb / Rd / Rf
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC

V AD_BID min
0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V

V AD_BID typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V

V AD_BID max
0 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V

BOARD ID Table

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Board ID
0
1
2
3
4
5
6
7

External PCI Devices


Device

IDSEL#

REQ#/GNT#

EC SM Bus1 address

Interrupts

Address

HEX

Smart Battery

0001 011X b

16H

Device
ADI ADM1032 (CPU)

Address

HEX

1001 100X b

98H

SB-Temp Sensor

SB820
SM Bus 0 address
Address

HEX

Clock Generator
(SILEGO SLG8SP626)

1101 001Xb

D2

DDR DIMM1

1001 000Xb

90

DDR DIMM2

1001 010Xb

94

Device

EVT / PVT stage (w/ pach code)

Board ID
0
1
2
3
4
5
6
7

98H

SB820
SM Bus 1 address

Device

BTO Item

PCB Revision

BOM Structure

Bluetooth
Vari-Bright
No Vari-Bright
HDMI

BT@
VB@
UNVB@
HDMI@

Project ID Table

EC SM Bus2 address

Device

BTO Option Table

PCB Revision
PEW76/86/96

Address

Mini card
4

2010/04/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/10/12

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Notes List
Document Number

PEW/76/86/96 LA-6552P
Sheet

Thursday, July 22, 2010


E

of

45

Rev
B

AMD CPU S1G4


+CPU_CORE
BATTERY
12.6V

BATT+

PU5
CHARGER
ISL6261AHAZ-T

PU15
ISL6265IRZ-T

PU16
APL5508-25DC
AC ADAPTOR
19V 90W

+CPU_CORE

0.7~1.3V

VDD CORE 36A

+CPU_CORE_NB

0.8~1.2V

VDDNB 4A

2.5V

VDDA 250mA

1.5V

VDDIO 3A

1.05V

VDDR 1.5A

1.1V

VLDT 1.5A

+CPU_CORE_NB

+2.5VS

+1.05VS
+1.05VS

PU12
APL5915

VIN

+1.1VS

RAM DDRIII SODIMMX2


+1.5V

PU7
RT8209BGQW

B+

+1.5V

1.5V

VDD_MEM 4A

0.75V

VTT_MEM 0.5A

+0.75VS
PU10
APL5913

NorthBridge AMD RS880M

PU8
RT8209BGQW

PU6
RT8209BGQW

1.0~1.1V

VDDC 1.0V-1.1V 7.6A

1.1V_S0

VDDHTRX+HT 0.68A
VDDPCIE 1.1A
VDDHTTX 0.68A
PLLs 0.23A

1.8V_S0

VDDA18 0.64A
VDDG18 0.005A
VDDLT18 0.22A
PLLs 0.1A

3.3V_S0

VDDG33 0.06A
AVDD 0.125A
VDDLT33 0A

No Use

VDD18_MEM 1.8V 0.005A


VDD_MEM 1.8V 0.23A

+NB_CORE
+1.1VS

+1.1VALW

+1.1VALW
U36
SI4800BDY
+1.1VS
+1.5V

+1.5VS

PU19
TSP51117RGYR

U35
SI4800BDY

VGA ATI Madison / Park


PU17
APW7138NITRL

+GPU_CORE

+VDDCI
0.85~1.1V
+1VSG
PU10
APL5913

+1.8VS
PU14
APL5913

PU11
MP2121DQ

+1.8VSP2

1.0V

PCIE_VDDC 2 A
DP[F:A]_VDD10 230 mA
DPLL_VDDC 125 mA
SPV10 100 mA

1.5V

VDDR1 TBD A

1.8V

PCIE_PVDD 40 mA
PCIE_VDDR 400 mA
TSVDD 5 mA
VDDR4 TBD mA
VDD_CT 17 mA
DP[F:A]_PVDD 20 mA
DP[F:A]_VDD18 330 mA
AVDD 70 mA
VDD1DI 45 mA
A2VDDQ 1.5 mA
VDD2DI 50 mA
DPLL_PVDD 75 mA
MPV18 150 mA
SPV18 50 mA

3.3V

VDDR3 60 mA
A2VDD 130 mA

+1.8VSP1

PU4
SN0806081 RHBR
+5VALW

U37
SI1800BDY

+3VS

LCD panel
15.6"

Delay

+3VS_DELAY

U34
SI4800BDY +5VS

B+ 300mA

VRAM 1GB
64Mx16 (K4B1G1646E) * 8

+1.5VS

+3VALW
+INVPWR_B+

VDDC 29 A
VDDCI 4 A

+3.3 350mA

1.5V

2.4 A

SouthBridge AMD SB820M

1.1V_S0
+1.1VALW

FAN Control
APL5607

1.1V_S5

+5VS 500mA
3.3V_S0

+3VALW

U25/U40
TPS2061DRG4 +USB_VCCA

3.3V_S5

+USB_VCCB

Audio AMP
TPA6017A2

USB X3
+5V
Dual+1
2.5A

+5V 25mA

SATA

Audio Codec
ALC272X

+5V 3A

+5V 45mA

+3.3V

+3.3VS 25mA

Realtek
RTS5137

EC
ENE KB926

+3.3VS 300mA

+3.3VALW 30mA
+3.3VS 3mA

LAN
BCM57780

ICS9LPRS488B

+3.3VALW 750mA

+3.3V 400mA

Mini Card

No Use

RTC
Bettary

+1.5VS 500mA
+3.3VS 1A
+3.3VALW 330mA

+1.1V

VDDCR_11_S 113mA
VDDAN_11_USB_S 200mA
VDDCR_11_USB_S 197mA
VDDPL_11_SYS_S
VDDIO_33_PCIGP 0.020A
VDDPL_33_PCIE 0.030A
VDDPL_33_SATA 0.020A
VDDPL_33_SYS
VDDIO_33_S
VDDPL_33_USB_S
VDDAN_33_USB_S 0.2A
VDDAN_33_S
VDDXL_33_S
VDDIO_AZ_S
VDDCR_11_GBE_S
VDDRF_GBE_S
VDDIO_33_GBE_S
VDDIO_GBE_S
VDDIO_18_FC

VDDBT_RTC_G

2010/04/12

Deciphered Date

2010/10/12

Title

POWER DELIVERY CHART

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom PEW/76/86/96
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Secret Data

Security Classification
Issued Date

2.5~3.6V
BAT

VDDCR_11 1.1V 0.5A


VDDAN_11_PCIE 1A
VDDAN_11_SATA 0.8A
VDDAN_11_CLK 0.4A

Rev
B

LA-6552P
Sheet

Thursday, July 22, 2010


1

of

45

VLDT CAP.

+1.1VS

250 mil
2
<12> H_CADIP[0..15]
<12> H_CADIN[0..15]

H_CADIP[0..15]

H_CADOP[0..15]

H_CADIN[0..15]

H_CADOP[0..15]

H_CADON[0..15]

H_CADON[0..15]

<12>
1

<12>

C1
10U_0805_10V4Z

C2
10U_0805_10V4Z

C3
0.22U_0603_16V4Z

C4
0.22U_0603_16V4Z

C5
180P_0402_50V8J

C6
180P_0402_50V8J

Near CPU Socket


+1.1VS

+1.1VS
JCPU1A

TBD

H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2
H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7
H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15

C7

HT LINK

D1
D2
D3
D4

VLDT_A0
VLDT_A1
VLDT_A2
VLDT_A3

E3
E2
E1
F1
G3
G2
G1
H1
J1
K1
L3
L2
L1
M1
N3
N2
E5
F5
F3
F4
G5
H5
H3
H4
K3
K4
L5
M5
M3
M4
N5
P5

L0_CADIN_H0
L0_CADIN_L0
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H15
L0_CADIN_L15

VLDT_B0
VLDT_B1
VLDT_B2
VLDT_B3

AE2
AE3
AE4
AE5

L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H15
L0_CADOUT_L15

AD1
AC1
AC2
AC3
AB1
AA1
AA2
AA3
W2
W3
V1
U1
U2
U3
T1
R1
AD4
AD3
AD5
AC5
AB4
AB3
AB5
AA5
Y5
W5
V4
V3
V5
U5
T4
T3

10U_0805_10V4Z
H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15

<12>
<12>
<12>
<12>

H_CLKIP0
H_CLKIN0
H_CLKIP1
H_CLKIN1

J3
J2
J5
K5

L0_CLKIN_H0
L0_CLKIN_L0
L0_CLKIN_H1
L0_CLKIN_L1

L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1

Y1
W1
Y4
Y3

H_CLKOP0
H_CLKON0
H_CLKOP1
H_CLKON1

<12>
<12>
<12>
<12>

<12>
<12>
<12>
<12>

H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1

N1
P1
P3
P4

L0_CTLIN_H0
L0_CTLIN_L0
L0_CTLIN_H1
L0_CTLIN_L1

L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1

R2
R3
T5
R5

H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1

<12>
<12>
<12>
<12>

FOX_PZ63823-284S-41F_Champlian

2010/04/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/10/12

Deciphered Date

Title

AMD CPU S1G4 HT I/F

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

PEW/76/86/96 LA-6552P
Sheet

Thursday, July 22, 2010


E

of

45

Rev
B

Processor DDR3 Memory Interface


JCPU1C
<11> DDRB_SDQ[63..0]
1

MEM:DATA

+1.5V

R1
1K_0402_1%

C8
1000P_0402_50V7K

C9
0.01U_0402_25V7K

MEM_VREF
1

R2
1K_0402_1%

+CPU_VDDR

+CPU_VDDR
JCPU1B

AMD suggest
2

Place them
close to CPU
within 1"

+1.5V

R4
1
1
R5

R410 0_0603_5%
2
1
1
C95
@
10U_0805_10V4Z

<10> MEM_MA_RST#
<10> DDRA_ODT0
<10> DDRA_ODT1

<10> DDRA_SCS0#
<10> DDRA_SCS1#

<10> DDRA_CKE0
<10> DDRA_CKE1
<10> DDRA_CLK0
<10> DDRA_CLK0#

<10> DDRA_CLK1
<10> DDRA_CLK1#
<10> DDRA_SMA[15..0]

<10> DDRA_SBS0#
<10> DDRA_SBS1#
<10> DDRA_SBS2#
<10> DDRA_SRAS#
<10> DDRA_SCAS#
<10> DDRA_SWE#

1.5A

D10
C10
B10
AD10

39.2_0402_1%
MEMZP AF10
2
MEMZN AE10
2
39.2_0402_1%
MEM_MA_RST#
H16
DDRA_ODT0
DDRA_ODT1

DDRA_SCS0#
DDRA_SCS1#

DDRA_CKE0
DDRA_CKE1
DDRA_CLK0
DDRA_CLK0#

VDDR: DDR3 under 1033MHz


set to 0.9V to save power

VDDR1 MEM:CMD/CTRL/CLK
VDDR5
VDDR2
VDDR6
VDDR3
VDDR7
VDDR4
VDDR8
VDDR9
MEMZP
MEMZN
VDDR_SENSE

W10
AC10
AB10
AA10
A10

MA_RESET_L

W17

MEM_VREF

MB_RESET_L

B18

MEM_MB_RST#

MB0_ODT0
MB0_ODT1
MB1_ODT0

W26
W23
Y26

DDRB_ODT0
DDRB_ODT1

MB0_CS_L0
MB0_CS_L1
MB1_CS_L0

V26
W25
U22

DDRB_SCS0#
DDRB_SCS1#

MB_CKE0
MB_CKE1

J25
H26

DDRB_CKE0
DDRB_CKE1
DDRB_CLK0
DDRB_CLK0#

T19
V22
U21
V19

MA0_ODT0
MA0_ODT1
MA1_ODT0
MA1_ODT1

T20
U19
U20
V20

MA0_CS_L0
MA0_CS_L1
MA1_CS_L0
MA1_CS_L1

J22
J20

MA_CKE0
MA_CKE1

MEMVREF

Y10

VTT_SENSE

N19
N20
E16
F16
Y16
AA16
P19
P20

MA_CLK_H5
MA_CLK_L5
MA_CLK_H1
MA_CLK_L1
MA_CLK_H7
MA_CLK_L7
MA_CLK_H4
MA_CLK_L4

MB_CLK_H5
MB_CLK_L5
MB_CLK_H1
MB_CLK_L1
MB_CLK_H7
MB_CLK_L7
MB_CLK_H4
MB_CLK_L4

P22
R22
A17
A18
AF18
AF17
R26
R25

DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3
DDRA_SMA4
DDRA_SMA5
DDRA_SMA6
DDRA_SMA7
DDRA_SMA8
DDRA_SMA9
DDRA_SMA10
DDRA_SMA11
DDRA_SMA12
DDRA_SMA13
DDRA_SMA14
DDRA_SMA15

N21
M20
N22
M19
M22
L20
M24
L21
L19
K22
R21
L22
K20
V24
K24
K19

MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15

MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15

P24
N24
P26
N23
N26
L23
N25
L24
M26
K26
T26
L26
L25
W24
J23
J24

DDRB_SMA0
DDRB_SMA1
DDRB_SMA2
DDRB_SMA3
DDRB_SMA4
DDRB_SMA5
DDRB_SMA6
DDRB_SMA7
DDRB_SMA8
DDRB_SMA9
DDRB_SMA10
DDRB_SMA11
DDRB_SMA12
DDRB_SMA13
DDRB_SMA14
DDRB_SMA15

DDRA_SBS0#
DDRA_SBS1#
DDRA_SBS2#

R20
R23
J21

MA_BANK0
MA_BANK1
MA_BANK2

MB_BANK0
MB_BANK1
MB_BANK2

R24
U26
J26

DDRB_SBS0#
DDRB_SBS1#
DDRB_SBS2#

DDRA_SRAS#
DDRA_SCAS#
DDRA_SWE#

R19
T22
T24

MA_RAS_L
MA_CAS_L
MA_WE_L

MB_RAS_L
MB_CAS_L
MB_WE_L

U25
U24
U23

DDRB_SRAS#
DDRB_SCAS#
DDRB_SWE#

DDRA_CLK1
DDRA_CLK1#

DDRB_CLK1
DDRB_CLK1#

PAD

T1

MEM_MB_RST# <11>
DDRB_ODT0 <11>
DDRB_ODT1 <11>
DDRB_SCS0# <11>
DDRB_SCS1# <11>
DDRB_CKE0 <11>
DDRB_CKE1 <11>
DDRB_CLK0 <11>
DDRB_CLK0# <11>

DDRB_CLK1 <11>
DDRB_CLK1# <11> <11> DDRB_SDM[7..0]
DDRB_SMA[15..0] <11>

DDRB_SBS0# <11>
DDRB_SBS1# <11>
DDRB_SBS2# <11>
DDRB_SRAS# <11>
DDRB_SCAS# <11>
DDRB_SWE# <11>

<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>

DDRB_SDQS0
DDRB_SDQS0#
DDRB_SDQS1
DDRB_SDQS1#
DDRB_SDQS2
DDRB_SDQS2#
DDRB_SDQS3
DDRB_SDQS3#
DDRB_SDQS4
DDRB_SDQS4#
DDRB_SDQS5
DDRB_SDQS5#
DDRB_SDQS6
DDRB_SDQS6#
DDRB_SDQS7
DDRB_SDQS7#

FOX_PZ63823-284S-41F_Champlian

DDRB_SDQ0
DDRB_SDQ1
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ4
DDRB_SDQ5
DDRB_SDQ6
DDRB_SDQ7
DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDQ26
DDRB_SDQ27
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQ30
DDRB_SDQ31
DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDQ58
DDRB_SDQ59
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQ62
DDRB_SDQ63

C11
A11
A14
B14
G11
E11
D12
A13
A15
A16
A19
A20
C14
D14
C18
D18
D20
A21
D24
C25
B20
C20
B24
C24
E23
E24
G25
G26
C26
D26
G23
G24
AA24
AA23
AD24
AE24
AA26
AA25
AD26
AE25
AC22
AD22
AE20
AF20
AF24
AF23
AC20
AD20
AD18
AE18
AC14
AD14
AF19
AC18
AF16
AF15
AF13
AC12
AB11
Y11
AE14
AF14
AF11
AD11

MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63

DDRB_SDM0
DDRB_SDM1
DDRB_SDM2
DDRB_SDM3
DDRB_SDM4
DDRB_SDM5
DDRB_SDM6
DDRB_SDM7

A12
B16
A22
E25
AB26
AE22
AC16
AD12

MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7

DDRB_SDQS0
DDRB_SDQS0#
DDRB_SDQS1
DDRB_SDQS1#
DDRB_SDQS2
DDRB_SDQS2#
DDRB_SDQS3
DDRB_SDQS3#
DDRB_SDQS4
DDRB_SDQS4#
DDRB_SDQS5
DDRB_SDQS5#
DDRB_SDQS6
DDRB_SDQS6#
DDRB_SDQS7
DDRB_SDQS7#

C12
B12
D16
C16
A24
A23
F26
E26
AC25
AC26
AF21
AF22
AE16
AD16
AF12
AE12

MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7

MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63

G12
F12
H14
G14
H11
H12
C13
E13
H15
E15
E17
H17
E14
F14
C17
G17
G18
C19
D22
E20
E18
F18
B22
C23
F20
F22
H24
J19
E21
E22
H20
H22
Y24
AB24
AB22
AA21
W22
W21
Y22
AA22
Y20
AA20
AA18
AB18
AB21
AD21
AD19
Y18
AD17
W16
W14
Y14
Y17
AB17
AB15
AD15
AB13
AD13
Y12
W11
AB14
AA14
AB12
AA12

DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ31
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ62
DDRA_SDQ63

MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7

E12
C15
E19
F24
AC24
Y19
AB16
Y13

DDRA_SDM0
DDRA_SDM1
DDRA_SDM2
DDRA_SDM3
DDRA_SDM4
DDRA_SDM5
DDRA_SDM6
DDRA_SDM7

MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7

G13
H13
G16
G15
C22
C21
G22
G21
AD23
AC23
AB19
AB20
Y15
W15
W12
W13

DDRA_SDQS0
DDRA_SDQS0#
DDRA_SDQS1
DDRA_SDQS1#
DDRA_SDQS2
DDRA_SDQS2#
DDRA_SDQS3
DDRA_SDQS3#
DDRA_SDQS4
DDRA_SDQS4#
DDRA_SDQS5
DDRA_SDQS5#
DDRA_SDQS6
DDRA_SDQS6#
DDRA_SDQS7
DDRA_SDQS7#

DDRA_SDQ[63..0]

<10>
1

DDRA_SDM[7..0]

DDRA_SDQS0
DDRA_SDQS0#
DDRA_SDQS1
DDRA_SDQS1#
DDRA_SDQS2
DDRA_SDQS2#
DDRA_SDQS3
DDRA_SDQS3#
DDRA_SDQS4
DDRA_SDQS4#
DDRA_SDQS5
DDRA_SDQS5#
DDRA_SDQS6
DDRA_SDQS6#
DDRA_SDQS7
DDRA_SDQS7#

<10>

<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>

FOX_PZ63823-284S-41F_Champlian

2010/04/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/10/12

Deciphered Date

Title

AMD CPU S1G4 DDRIII I/F

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

PEW/76/86/96 LA-6552P
Sheet

Thursday, July 22, 2010


E

of

45

Rev
B

FBMA-L11-201209-221LMA30T_0805 1

C11

VDDA=0.25A

3300P_0402_50V7K

4.7U_0805_10V4Z

1
C12

220U_6.3V_M

LDT_RES# / MEMHOT#
no support in S1g4

1
C13

+1.5V

C14
0.22U_0603_16V4Z

R6
10K_0402_5%
<BOM Structure>

+2.5VS

Champlain: C1E
C1E: LDT_REQ# no connect
CLMC: LDT_REQ# connect to NB

+2.5VDDA
L1

R7
1K_0402_5%
1

JCPU1D

2 2

LDT_RST#
H_PWRGD
LDT_STOP#

R10
169_0402_1%
<18> CLK_CPU_BCLK#

C15

2
3900P_0402_50V7K

T2
+1.5V
+1.5V

+1.5VS

R12
R14

2
1

LDT_RST#

C17
0.01U_0402_25V4Z
@

1
2
1

R21
300_0402_5%

PAD

CPU_SIC
CPU_SID

AF4
AF5
AE6

2 44.2_0402_1% CPU_HTREF0
2 44.2_0402_1% CPU_HTREF1

SVC
SVD

RESET_L
PWROK
LDTSTOP_L
LDTREQ_L

THERMTRIP_L
PROCHOT_L
MEMHOT_L
THERMDC
THERMDA

HT_REF0
HT_REF1

CPU_SVC <42>
CPU_SVD <42>

PAD

W7
W8

THERMDC_CPU
THERMDA_CPU

T3

VDD0_FB_H
VDD0_FB_L

VDDIO_FB_H
VDDIO_FB_L

W9
Y9

CPU_VDD1_FB_H
Y6
CPU_VDD1_FB_L AB6

VDD1_FB_H
VDD1_FB_L

VDDNB_FB_H
VDDNB_FB_L

H6
G6

CPU_VDDNB_FB_H
CPU_VDDNB_FB_L

DBREQ_L

E10

CPU_DBREQ#

TDO

AE9

CPU_TDO

G10
AA9
AC9
AD9
AF9
CPU_TEST23

AD7

CPU_TEST18
CPU_TEST19

H10
G9

CPU_TEST25H
CPU_TEST25L

C18
0.01U_0402_25V4Z
@

H_PWRGD
C19
0.01U_0402_25V4Z
@

1
R24

+3VS

E9
E8

DBRDY
TMS
TCK
TRST_L
TDI

TEST28_H
TEST28_L

TEST18
TEST19
TEST25_H
TEST25_L

AB8
AF7
AE7
AE8
AC8
AF8

TEST21
TEST20
TEST24
TEST22
TEST12
TEST27

2
0_0402_5%

C2
AA6

TEST9
TEST6

A3
A5
B3
B5
C1

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5

H_THERMTRIP# <19>

1
R9

2
0_0402_5%

1
R11

MAINPWON <35,36>

2
300_0402_5%

PAD
PAD

H_PROCHOT#

1
R13

2
0_0402_5%

H_PROCHOT_R# <18>

PROCHOT:
Input: For HTC Function
Output: Over Temperature Condition

T4
T11
CPU_VDDNB_FB_H <42>
CPU_VDDNB_FB_L <42>

+1.5V

TEST23

CPU_TEST21
CPU_TEST20
CPU_TEST24
CPU_TEST22
CPU_TEST12
CPU_TEST27

2
0_0402_5%

CPU_THERMTRIP#_R
H_PROCHOT#

AF6
AC7
AA8

<42> CPU_VDD1_FB_H
<42> CPU_VDD1_FB_L

CPU_DBRDY
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI

1
R8

MMBT3904_NL_SOT23-3
CPU_SVC
CPU_SVD

+1.5V

SIC
SID
ALERT_L

R6
P6

A6
A4

F6
E6

LDT_STOP#

B7
A7
F10
C6

VSS
RSVD11

<42> CPU_VDD0_FB_H
<42> CPU_VDD0_FB_L

R18
300_0402_5%

+1.5VS <13,18> LDT_STOP#

CLKIN_H
CLKIN_L

CPU_VDD0_FB_H
CPU_VDD0_FB_L

+1.5VS

<18> H_PWRGD

1
1

2
2 1K_0402_5%
1K_0402_5%

R15
R16

+1.1VS
R17
300_0402_5%

<18> LDT_RST#

1
1

VDDA1
VDDA2

A9
A8

C16

CPU_CLKIN_SC_P
CPU_CLKIN_SC_N

2 3900P_0402_50V7K

CPU_THERMTRIP#_R

M11
W18

Q1
1

<18> CLK_CPU_BCLK

F8
F9

TEST17
TEST16
TEST15
TEST14

D7
E7
F7
C7

TEST7
TEST10

C3
K8

TEST8

C4

TEST29_H
TEST29_L

C9
C8

RSVD10
RSVD9
RSVD8
RSVD7
RSVD6

J7
H8

CPU_SVC
CPU_TEST17
CPU_TEST16
CPU_TEST15
CPU_TEST14

PAD
PAD
PAD
PAD

T5
T6
T7
T8

1
R19
1
R20

CPU_SVD

2
1K_0402_5%
2
1K_0402_5%
+1.5V

CPU_TEST29_H_FBCLKOUT_P
CPU_TEST29_L_FBCLKOUT_N

2
R25

CPU_TEST25H

1
R22
1
R23

CPU_TEST25L

1
R26
1
R27

1
80.6_0402_1%

H18
H19
AA7
D5
C5

2
510_0402_5%
2
510_0402_5%

+1.5V

2
510_0402_5%
2
510_0402_5%

0.1U_0402_16V4Z

+1.5V

FOX_PZ63823-284S-41F_Champlian
@
C20

CPU_TEST27
@
U1

C21

VDD

THERMDA_CPU

D+

THERMDC_CPU

D-

2
100P_0402_50V8J

THERM#

EC_SMB_CK2

SDATA

EC_SMB_DA2

ALERT#

CPU_TEST12

GND

CPU_TEST18

SCLK

CPU_TEST19
+1.5V

CPU_TEST20

Address 1001 100X b

31.6K_0402_1%

30K_0402_5%

For PVT

CPU_SID 3

1.607V for Gate


1

CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO

EC_SMB_DA2

1
3
5
7
9
11
13
15
17
19
21
23

Q2

2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%

2
4
6
8
10
12
14
16
18
20
22
24
26

R43
@

2
0_0402_5%

+3VS
5

CPU_TEST23

1
R29
1
R30
1
R31
1
R32
1
R33
1
R34
1
R35
1
R265

JP2

U2
HDT_RST#

FDV301N_NL_SOT23-3

Y
@

LDT_RST#
SB_PWRGD <13,19,28>

NC7SZ08P5X_NL_SC70-5

CONN@ SAMTEC_ASP-68200-07

+3VS

0.1U_0402_16V4Z

R42
1

BSH111, the Vgs is:


min = 0.4V
Typ = 1.0V
Max = 1.3V

CPU_TEST24

C22
R41
2

FDV301N, the Vgs is:


min = 0.65V
Typ = 0.85V
Max = 1.5V

CPU_TEST22

2
1
220_0402_5% R36
2
1
220_0402_5% R37
2
1
220_0402_5% R38
2
1
300_0402_5% R39
1
2
300_0402_5% R40

CPU_TEST21

CPU internal thermal sensor


2

2
1K_0402_5%

For SCAN connect use

EC_SMB_DA2 <28>

ADM1032ARMZ_MSOP8

1
R28

EC_SMB_CK2 <28>

CPU_SIC 3

EC_SMB_CK2

2010/04/12

Issued Date

FDV301N_NL_SOT23-3

Compal Electronics, Inc.

Compal Secret Data

Security Classification

S
Q3

2010/10/12

Deciphered Date

Title

AMD CPU S1G4 CTRL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

PEW/76/86/96 LA-6552P
Sheet

Thursday, July 22, 2010


E

of

45

Rev
B

JCPU1F

VDD(+CPU_CORE) decoupling.

JCPU1E

+CPU_CORE

+CPU_CORE

C23

C24

C25

+ C27
@
330U_D2_2V_Y
2

C26

330U_D2_2V_Y
2

330U_D2_2V_Y
2

330U_D2_2V_Y
2

330U_D2_2V_Y
2

Near CPU Socket

Change as SGA19331D10 (ESR9 ohm) for PVT

+CPU_CORE

+CPU_CORE
+CPU_CORE_NB

C28
22U_0805_6.3V6M

C29
22U_0805_6.3V6M

C30
22U_0805_6.3V6M

C35
22U_0805_6.3V6M

C31
22U_0805_6.3V6M

+CPU_CORE

C32
22U_0805_6.3V6M

C33
22U_0805_6.3V6M

4A
C34
22U_0805_6.3V6M

+1.5V

+CPU_CORE

C36
0.22U_0603_16V4Z

C37
0.01U_0402_25V4Z

C38
180P_0402_50V8J

C39
0.22U_0603_16V4Z

C40
0.01U_0402_25V4Z

C41
180P_0402_50V8J

Under CPU Socket


2

G4
H2
J9
J11
J13
J15
K6
K10
K12
K14
L4
L7
L9
L11
L13
L15
M2
M6
M8
M10
N7
N9
N11

VDD0_1
VDD0_2
VDD0_3
VDD0_4
VDD0_5
VDD0_6
VDD0_7
VDD0_8
VDD0_9
VDD0_10
VDD0_11
VDD0_12
VDD0_13
VDD0_14
VDD0_15
VDD0_16
VDD0_17
VDD0_18
VDD0_19
VDD0_20
VDD0_21
VDD0_22
VDD0_23

K16
M16
P16
T16
V16

VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5

H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17

VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12

AA4
AA11
AA13
AA15
AA17
AA19
AB2
AB7
AB9
AB23
AB25
AC11
AC13
AC15
AC17
AC19
AC21
AD6
AD8
AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23
B4
B6
B8
B9
B11
B13
B15
B17
B19
B21
B23
B25
D6
D8
D9
D11
D13
D15
D17
D19
D21
D23
D25
E4
F2
F11
F13
F15
F17
F19
F21
F23
F25
H7
H9
H21
H23
J4

+CPU_CORE
VDD1_1
VDD1_2
VDD1_3
VDD1_4
VDD1_5
VDD1_6
VDD1_7
VDD1_8
VDD1_9
VDD1_10
VDD1_11
VDD1_12
VDD1_13
VDD1_14
VDD1_15
VDD1_16
VDD1_17
VDD1_18
VDD1_19
VDD1_20
VDD1_21
VDD1_22
VDD1_23
VDD1_24
VDD1_25
VDD1_26

P8
P10
R4
R7
R9
R11
T2
T6
T8
T10
T12
T14
U7
U9
U11
U13
U15
V6
V8
V10
V12
V14
W4
Y2
AC4
AD2

VDDIO27
VDDIO26
VDDIO25
VDDIO24
VDDIO23
VDDIO22
VDDIO21
VDDIO20
VDDIO19
VDDIO18
VDDIO17
VDDIO16
VDDIO15
VDDIO14
VDDIO13

Y25
V25
V23
V21
V18
U17
T25
T23
T21
T18
R17
P25
P23
P21
P18

36A

+1.5V

TBD

FOX_PZ63823-284S-41F_Champlian
Athlon 64 S1
Processor Socket

VDDIO decoupling.
+CPU_CORE_NB

decoupling.

+1.5V
+CPU_CORE_NB
1

C44
22U_0805_6.3V6M

C45
22U_0805_6.3V6M

C46

0.22U_0603_16V4Z
2

C47

0.22U_0603_16V4Z
2

C48

C50

180P_0402_50V8J 180P_0402_50V8J
2
2

C42
22U_0805_6.3V6M

C43
22U_0805_6.3V6M

C49
22U_0805_6.3V6M

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65

J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
AC6
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6

VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129

FOX_PZ63823-284S-41F_Champlian

Under CPU Socket

Athlon 64 S1
Processor Socket

+1.5V

C355
0.22U_0603_16V4Z

C354
0.22U_0603_16V4Z

C56 +

220U_6.3V_M

C55
22U_0805_6.3V6M

2
2

+1.5V

+1.5V

C64
0.01U_0402_25V4Z

C65
0.01U_0402_25V4Z

180PF Qt'y follow the distance between


CPU socket and DIMM0. <2.5inch>
2

C66
0.1U_0402_16V7K

C67
0.1U_0402_16V7K

C68
180P_0402_50V8J

+CPU_VDDR

Reserve for EMI

C69
1
180P_0402_50V8J C57
4.7U_0805_10V4Z
2

C58
4.7U_0805_10V4Z

+1.5V

0.1U_0402_16V7K

C54
0.22U_0603_16V4Z

C96

C101 0.1U_0402_16V7K

C53
0.22U_0603_16V4Z

0.1U_0402_16V7K

C52
0.22U_0603_16V4Z

0.1U_0402_16V7K

C51
0.22U_0603_16V4Z

0.1U_0402_16V7K

Near Power Supply

C100 0.1U_0402_16V7K

+CPU_VDDR

VDDR decoupling.

C99

+1.5V
3

C98

C97

Between CPU Socket and DIMM

C59
0.22U_0603_16V4Z

C60
0.22U_0603_16V4Z

C61
1000P_0402_50V7K

C62
1000P_0402_50V7K

C63
180P_0402_50V8J

C70
180P_0402_50V8J

Near CPU Socket Right side.


Change as SGA19331D10 (ESR9 ohm) for PVT

+CPU_VDDR

1
1

1
C71
4.7U_0805_10V4Z

1
C72
4.7U_0805_10V4Z

1
C73
4.7U_0805_10V4Z

+
C74
4.7U_0805_10V4Z

C75
330U_D2_2V_Y

C76
4.7U_0805_10V4Z

C77
4.7U_0805_10V4Z

C78
0.22U_0603_16V4Z

C79
0.22U_0603_16V4Z

C80
1000P_0402_50V7K

C81
1000P_0402_50V7K

C82
180P_0402_50V8J

C83
180P_0402_50V8J

Near CPU Socket Left side.

2010/04/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/10/12

Deciphered Date

Title

AMD CPU S1G4 PWR & GND

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

PEW/76/86/96 LA-6552P
Sheet

Thursday, July 22, 2010


E

of

45

Rev
B

+VREF_DQ

+1.5V

+1.5V
JDIMM1

DDRA_SDQS2#
DDRA_SDQS2

<7> DDRA_SDQS2#
<7> DDRA_SDQS2

DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDM3
DDRA_SDQ26
DDRA_SDQ27

DDRA_SDQ[0..63]

<7>

DDRA_SDM[0..7]

<7>

DDRA_SMA[0..15]

<7>

DDRA_SDQ12
DDRA_SDQ13
DDRA_SMA[0..15]
DDRA_SDM1
MEM_MA_RST#

MEM_MA_RST# <7>

DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDM2
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQS3#
DDRA_SDQS3

+VREF_CA
+VREF_DQ

DDRA_SDQ30
DDRA_SDQ31

DDRA_SMA3
DDRA_SMA1
<7> DDRA_CLK0
<7> DDRA_CLK0#
<7> DDRA_SBS0#
<7> DDRA_SWE#
<7> DDRA_SCAS#

<7> DDRA_SCS1#

DDRA_CLK0
DDRA_CLK0#
DDRA_SMA10
DDRA_SBS0#
DDRA_SWE#
DDRA_SCAS#
DDRA_SMA13
DDRA_SCS1#

DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQS4#
DDRA_SDQS4

<7> DDRA_SDQS4#
<7> DDRA_SDQS4

DDRA_SDQ34
DDRA_SDQ35

DDRA_SDQ40
DDRA_SDQ41
DDRA_SDM5
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQS6#
DDRA_SDQS6

<7> DDRA_SDQS6#
<7> DDRA_SDQS6

DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDM7
DDRA_SDQ58
DDRA_SDQ59
R50
10K_0402_5%
1
2

+3VS

R51

+3VS
2

10K_0402_5%

C90

2
2.2U_0805_10V6K

C91

206

DDRA_CKE1 <7>

DDRA_SMA15
DDRA_SMA14
DDRA_SMA11
DDRA_SMA7
DDRA_SMA6
DDRA_SMA4

C84
@

C85

G2

DDRA_CKE1

C10

R49
1K_0402_1%

C235
@

2
C351
1

C680

R315
1K_0402_1%

DDRA_SMA2
DDRA_SMA0
DDRA_CLK1
DDRA_CLK1#
DDRA_SBS1#
DDRA_SRAS#
DDRA_SCS0#
DDRA_ODT0
DDRA_ODT1

DDRA_CLK1 <7>
DDRA_CLK1# <7>
DDRA_SBS1# <7>
DDRA_SRAS# <7>
DDRA_SCS0# <7>
DDRA_ODT0 <7>
DDRA_ODT1 <7>
+1.5V

+VREF_CA
DDRA_SDQ36
DDRA_SDQ37

DDRA_SDM4
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQS5#
DDRA_SDQS5

0.1U_0402_16V4Z
2

C87

0.1U_0402_16V4Z
2

C643

1
0.1U_0402_16V4Z

C88

0.1U_0402_16V4Z
2

C644

1
0.1U_0402_16V4Z

C640

C645

1
0.1U_0402_16V4Z

0.1U_0402_16V4Z
2
C641

1
0.1U_0402_16V4Z

C646
1

0.1U_0402_16V4Z
2
C642

1
0.1U_0402_16V4Z

C647
1
3

DDRA_SDQS5# <7>
DDRA_SDQS5 <7>

+0.75VS

DDRA_SDQ46
DDRA_SDQ47

0.1U_0402_16V4Z
2

DDRA_SDQ52
DDRA_SDQ53

C665
1
0.1U_0402_16V4Z

DDRA_SDM6

C664
1

1
C961

2
4.7U_0805_10V4Z

Place near DIMM1

DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQS7#
DDRA_SDQS7

DDRA_SDQS7# <7>
DDRA_SDQS7 <7>

+1.5V

DDRA_SDQ62
DDRA_SDQ63
+1.5V
PAD

C690

T9

SB_SMDAT0 <11,19,26>
SB_SMCLK0 <11,19,26>

+0.75VS

+0.75VS

2
C691

2
C692

2
C693

0.1U_0402_16V4Z

0.01U_0402_16V7K
4

0.01U_0402_16V7K

FOX_AS0A626-U8SN-7F
CONN@

0.01U_0402_16V7K

0.1U_0402_16V4Z
2

DIMM_A STD H:8mm

2010/04/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

<Address: 00>

2010/10/12

Deciphered Date

Title

DDRIII SO-DIMM 1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

G1

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

1000P_0402_50V7K

205

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

0.01U_0402_25V7K

DDRA_SMA8
DDRA_SMA5

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

4.7U_0805_10V4Z

DDRA_SMA12
DDRA_SMA9

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

C89
1000P_0402_50V7K

<7> DDRA_SBS2#

DDRA_SBS2#

+VREF_CA
0.01U_0402_25V7K

DDRA_CKE0

<7> DDRA_CKE0

R310
1K_0402_1%

R48
1K_0402_1%
+VREF_DQ

+1.5V

+1.5V

DDRA_SDQS3# <7>
DDRA_SDQS3 <7>

DDRA_SDQ16
DDRA_SDQ17

DDRA_SDQ[0..63]
DDRA_SDM[0..7]

DDRA_SDQ10
DDRA_SDQ11

DDRA_SDQS0# <7>
DDRA_SDQS0 <7>

DDRA_SDQ6
DDRA_SDQ7

DDRA_SDQS1#
DDRA_SDQS1

<7> DDRA_SDQS1#
<7> DDRA_SDQS1

DDRA_SDQS0#
DDRA_SDQS0

DDRA_SDQ8
DDRA_SDQ9

DDRA_SDQ4
DDRA_SDQ5

1000P_0402_50V7K

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

4.7U_0805_10V4Z

DDRA_SDQ2
DDRA_SDQ3

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

DDRA_SDM0

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

DDRA_SDQ0
DDRA_SDQ1

PEW/76/86/96 LA-6552P
Sheet

Thursday, July 22, 2010


E

10

of

45

Rev
B

+VREF_DQ

+1.5V

+1.5V
JDIMM2

<7> DDRB_SDQS1#
<7> DDRB_SDQS1

DDRB_SDQS1#
DDRB_SDQS1
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ16
DDRB_SDQ17

<7> DDRB_SDQS2#
<7> DDRB_SDQS2

DDRB_SDQS2#
DDRB_SDQS2
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDM3
DDRB_SDQ26
DDRB_SDQ27

<7> DDRB_CKE0
2

<7> DDRB_SBS2#

DDRB_CKE0
DDRB_SBS2#
DDRB_SMA12
DDRB_SMA9
DDRB_SMA8
DDRB_SMA5
DDRB_SMA3
DDRB_SMA1

<7> DDRB_SWE#
<7> DDRB_SCAS#

<7> DDRB_SCS1#

DDRB_SWE#
DDRB_SCAS#
DDRB_SMA13
DDRB_SCS1#

DDRB_SDQ32
DDRB_SDQ33
<7> DDRB_SDQS4#
<7> DDRB_SDQS4

DDRB_SDQS4#
DDRB_SDQS4
DDRB_SDQ34
DDRB_SDQ35

DDRB_SDQ40
DDRB_SDQ41
DDRB_SDM5
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ48
DDRB_SDQ49
<7> DDRB_SDQS6#
<7> DDRB_SDQS6

DDRB_SDQS6#
DDRB_SDQS6
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDM7
DDRB_SDQ58
DDRB_SDQ59
R52
10K_0402_5%
1
2

+3VS

R53

205

10K_0402_5%

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

G2

206

G1

DDRB_SDQS0# <7>
DDRB_SDQS0 <7>

DDRB_SDQ[0..63]

DDRB_SDQ6
DDRB_SDQ7

DDRB_SDQ[0..63]

DDRB_SDM[0..7]

DDRB_SDM[0..7]

<7>
<7>
1

DDRB_SDQ12
DDRB_SDQ13
DDRB_SMA[0..15]
DDRB_SDM1
MEM_MB_RST#

DDRB_SMA[0..15]

<7>

MEM_MB_RST# <7>

DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDM2
DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQS3#
DDRB_SDQS3

DDRB_SDQS3# <7>
DDRB_SDQS3 <7>

DDRB_SDQ30
DDRB_SDQ31

DDRB_CKE1

DDRB_CKE1 <7>

DDRB_SMA15
DDRB_SMA14

DDRB_SMA11
DDRB_SMA7
+VREF_DQ

DDRB_SMA6
DDRB_SMA4

+VREF_CA

DDRB_SMA2
DDRB_SMA0
DDRB_CLK1
DDRB_CLK1#
DDRB_SBS1#
DDRB_SRAS#
DDRB_SCS0#
DDRB_ODT0
DDRB_ODT1

+VREF_DQ

DDRB_CLK1 <7>
DDRB_CLK1# <7>
DDRB_SBS1# <7>
DDRB_SRAS# <7>
DDRB_SCS0# <7>
DDRB_ODT0 <7>

C92

C93

+VREF_CA

C682

C352

0.1U_0402_16V4Z

<7> DDRB_SBS0#

DDRB_SMA10
DDRB_SBS0#

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

DDRB_SDQS0#
DDRB_SDQS0

0.1U_0402_16V4Z

<7> DDRB_CLK0
<7> DDRB_CLK0#

DDRB_CLK0
DDRB_CLK0#

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

DDRB_SDQ4
DDRB_SDQ5

C353

1000P_0402_50V7K

DDRB_SDQ8
DDRB_SDQ9

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

4.7U_0805_10V4Z

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

1000P_0402_50V7K

DDRB_SDQ2
DDRB_SDQ3

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

4.7U_0805_10V4Z

DDRB_SDM0

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

C683

DDRB_ODT1 <7>
+VREF_CA

DDRB_SDQ36
DDRB_SDQ37

DDRB_SDM4
DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQS5#
DDRB_SDQS5

DDRB_SDQS5# <7>
DDRB_SDQS5 <7>

+1.5V

DDRB_SDQ46
DDRB_SDQ47

0.1U_0402_16V4Z
2

DDRB_SDQ52
DDRB_SDQ53

C677

0.1U_0402_16V4Z
2

C670

1
0.1U_0402_16V4Z

DDRB_SDM6

C666

C671

1
0.1U_0402_16V4Z

0.1U_0402_16V4Z
2
C667

1
0.1U_0402_16V4Z

C672
1

0.1U_0402_16V4Z
2
C668

C673

1
0.1U_0402_16V4Z

0.1U_0402_16V4Z
2
C669

C674

1
0.1U_0402_16V4Z

DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQS7#
DDRB_SDQS7

+1.5V
+0.75VS
DDRB_SDQS7# <7>
DDRB_SDQS7 <7>

DDRB_SDQ62
DDRB_SDQ63
PAD

0.1U_0402_16V4Z
2
C676

1
0.1U_0402_16V4Z

T10

C675
1

1
+

C925

2
4.7U_0603_6.3V6K

SB_SMDAT0 <10,19,26>
SB_SMCLK0 <10,19,26>

C86
330U_X_2VM_R6M

Place near DIMM2

+0.75VS
4

FOX_AS0A626-U4SN-7F
CONN@

DIMM_B STD H:4mm


<Address: 01>

2010/04/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/10/12

Deciphered Date

Title

DDRIII SO-DIMM 2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

C94
1000P_0402_50V7K

DDRB_SDQ0
DDRB_SDQ1

PEW/76/86/96 LA-6552P
Sheet

Thursday, July 22, 2010


E

11

of

45

Rev
B

U3B

<24>
<24>
<26>
<26>

PCIE_PTX_C_IRX_P0
PCIE_PTX_C_IRX_N0
PCIE_PTX_C_IRX_P1
PCIE_PTX_C_IRX_N1

<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>

SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N

AE3
AD4
AE2
AD3
AD1
AD2
V5
W6
U5
U6
U8
U7

GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
GPP_RX4P
GPP_RX4N
GPP_RX5P
GPP_RX5N

AA8
Y8
AA7
Y7
AA5
AA6
W5
Y5

SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N

GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N

A5
B5
A4
B4
C3
B2
D1
D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2

GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N

AC1
AC2
AB4
AB3
AA2
AA1
Y1
Y2
Y4
Y3
V1
V2

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

AD7
AE7
AE6
AD6
AB6
AC6
AD5
AE5

PCE_CALRP(PCE_BCALRP)
PCE_CALRN(PCE_BCALRN)

AC8
AB8

PART 2 OF 6

PCIE I/F GPP

PCIE I/F SB

GMCH_HDMI_TXD2+ <16>
GMCH_HDMI_TXD2- <16>
GMCH_HDMI_TXD1+ <16>
GMCH_HDMI_TXD1- <16>
GMCH_HDMI_TXD0+ <16>
GMCH_HDMI_TXD0- <16>
GMCH_HDMI_TXC+ <16>
GMCH_HDMI_TXC- <16>

PCIE_ITX_PRX_P0
PCIE_ITX_PRX_N0
PCIE_ITX_PRX_P1
PCIE_ITX_PRX_N1

C127 1
C128
1
C129 1
C130
1

2
2
2
2

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_ITX_C_PRX_P0
PCIE_ITX_C_PRX_N0
PCIE_ITX_C_PRX_P1
PCIE_ITX_C_PRX_N1

<24>
<24>GLAN
<26>
<26>WLAN

<6> H_CADOP[0..15]
<6> H_CADON[0..15]
SB_TX0P_C
SB_TX0N_C
SB_TX1P_C
SB_TX1N_C
SB_TX2P_C
SB_TX2N_C
SB_TX3P_C
SB_TX3N_C
R59
R58

C133
C134
C135
C136
C137
C138
C139
C140

1
1
1
1
1
1
1
1

1
1

2
2

2
2
2
2
2
2
2
2

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

1.27K_0402_1%
2K_0402_1%

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>

H_CADIP[0..15]
H_CADIN[0..15]

+1.1VS

RS880 A11(SA000032710)

<6>
<6>
<6>
<6>

H_CLKOP0
H_CLKON0
H_CLKOP1
H_CLKON1

<6>
<6>
<6>
<6>

H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1
1

R60

H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7

Y25
Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25

H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15

AC24
AC25
AB25
AB24
AA24
AA25
Y22
Y23
W21
W20
V21
V20
U20
U21
U19
U18

HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N

T22
T23
AB23
AA22

HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N

M22
M23
R21
R20

H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1
2

HT_RXCALP
HT_RXCALN

301_0402_1%~D

C23
A24

<6>

HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N

D24
D25
E24
E25
F24
F25
F23
F22
H23
H22
J25
J24
K24
K25
K23
K22

H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2
H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7

HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N

F21
G21
G20
H21
J20
J21
J18
K17
L19
J19
M19
L18
M21
P21
P18
M18

H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15

HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N

H24
H25
L21
L20

HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N

HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N

M24
M25
P19
R18

H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1

HT_RXCALP
HT_RXCALN

HT_TXCALP
HT_TXCALN

B24
B25

HT_TXCALP
HT_TXCALN

HT_RXCAD0P
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N

PART 1 OF 6

<6>
<6>
<6>
<6>

H_CTLIP0
H_CTLIN0
H_CTLIP1
H_CTLIN1

<6>
<6>
<6>
<6>

R61

301_0402_1%~D

Compal Electronics, Inc.

Compal Secret Data


2010/10/12

Deciphered Date

Title

RS880-HT/PCIE

Date:

H_CLKIP0
H_CLKIN0
H_CLKIP1
H_CLKIN1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

0718 Place within 1"


layout 1:2

RS880 A11(SA000032710)

2010/04/12

<6>

RS780M_FCBGA528

0718 Place within 1"


layout 1:2

Security Classification

H_CADIP[0..15]
H_CADIN[0..15]

U3A

RS780M_FCBGA528

Issued Date

H_CADOP[0..15]
H_CADON[0..15]

HYPER TRANSPORT CPU I/F

GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N

PCIE I/F GFX

D4
C4
A3
B3
C2
C1
E5
F5
G5
G6
H5
H6
J6
J5
J7
J8
L5
L6
M8
L8
P7
M7
P5
M5
R8
P8
R6
R5
P4
P3
T4
T3

PEW/76/86/96 LA-6552P
Sheet

Thursday, July 22, 2010


E

12

of

45

Rev
B

FBMA-L11-160808-221LMT 0603

C143
1

2.2U_0603_6.3V4Z
2
2
2
1U_0402_6.3V4Z

+1.8VS

C147
1U_0402_6.3V4Z

20mA

L7
1

4mA

+AVDDQ

FBMA-L11-160808-221LMT 0603
C148
2.2U_0603_6.3V4Z

C149
1U_0402_6.3V4Z

FBMA-L11-160808-221LMT 0603
C150
2.2U_0603_6.3V4Z

C151
1U_0402_6.3V4Z

2
1

20mA
+VDDA18HTPLL

+1.8VS

R68

1
1

R80

2 4.7K_0402_5%

DAC_HSYNC(PWM_GPIO4)
DAC_VSYNC(PWM_GPIO6)
DAC_SCL(PCE_RCALRN)
DAC_SDA(PCE_TCALRN)

2 4.7K_0402_5% GMCH_CRT_DATA

H17

PLLVDD(NC)
PLLVDD18(NC)
PLLVSS(NC)
VDDA18HTPLL

HT_REFCLKP
HT_REFCLKN

<18> NB_DISP_CLKP
<18> NB_DISP_CLKN

E11
F11

REFCLK_P/OSCIN(OSCIN)
REFCLK_N(PWM_GPIO3)

4.7K_0402_5%
2 CLK_NBGFX
2 CLK_NBGFX#
4.7K_0402_5%

GMCH_LCD_CLK
GMCH_LCD_DATA
GMCH_HDMI_DATA
GMCH_HDMI_CLK

<15> GMCH_LCD_CLK
<15> GMCH_LCD_DATA
<16> GMCH_HDMI_DATA
<16> GMCH_HDMI_CLK

GMCH_CRT_CLK

<39> POWER_SEL

1
2
R82
2K_0402_5%
POWER_SEL

T2
T1

GFX_REFCLKP
GFX_REFCLKN

U1
U2

GPP_REFCLKP
GPP_REFCLKN

V4
V3

GPPSB_REFCLKP(SB_REFCLKP)
GPPSB_REFCLKN(SB_REFCLKN)

B9
A9
B8
A8
B7
A7

I2C_CLK
I2C_DATA
DDC_DATA0/AUX0N(NC)
DDC_CLK0/AUX0P(NC)
DDC_CLK1/AUX1P(NC)
DDC_DATA1/AUX1N(NC)

B10
G11

1
R85

5
P

4NB_PWRGD_R

@
1

2
0_0402_5%

2
150_0402_1%

C8

A22
B22
A21
B21
B20
A20
A19
B19

TXOUT_U0P(NC)
TXOUT_U0N(NC)
TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)
TXOUT_U2P(NC)
TXOUT_U2N(NC)
TXOUT_U3P(PCIE_RESET_GPIO5)
TXOUT_U3N(NC)

B18
A18
A17
B17
D20
D21
D18
D19

TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)
TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)

B16
A16
D16
D17

VDDLTP18(NC)
VSSLTP18(NC)

A13
B13

VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)

A15
B15
A14
B14

VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)

C14
D15
C16
C18
C20
E20
C22

LVDS_DIGON(PCE_TCALRP)
LVDS_BLON(PCE_RCALRP)
LVDS_ENA_BL(PWM_GPIO2)

E9
F7
G12

DAC_RSET(PWM_GPIO1)

C25
C24

<18> CLK_SBLINK_BCLK
<18> CLK_SBLINK_BCLK#

GMCH_LCD_CLK

2 4.7K_0402_5% GMCH_LCD_DATA
@

A11
B11
F8
E8

<18> CLK_NBHT
<18> CLK_NBHT#

+3VS

R79

RED(DFT_GPIO0)
REDb(NC)
GREEN(DFT_GPIO1)
GREENb(NC)
BLUE(DFT_GPIO3)
BLUEb(NC)

SYSRESETb
POWERGOOD
LDTSTOPb
ALLOW_LDTSTOP

NB_PWRGD_R
NB_LDTSTOP#
NB_ALLOW_LDTSTOP

close NB

R78

G18
G17
E18
F18
E19
F19

D8
A10
C10
C12

R106 1
R83 1

2 4.7K_0402_5%

C_Pr(DFT_GPIO5)
Y(DFT_GPIO2)
COMP_Pb(DFT_GPIO4)

VDDA18PCIEPLL1
VDDA18PCIEPLL2

1
300_0402_5%

U4
NC7SZ08P5X_NL_SC70-5

NC7SZ08P5X_NL_SC70-5

TXOUT_L0P(NC)
TXOUT_L0N(NC)
TXOUT_L1P(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)
TXOUT_L2N(DBG_GPIO0)
TXOUT_L3P(NC)
TXOUT_L3N(DBG_GPIO2)

PART 3 OF 6

D7
E7

<14,18,28> A_RST#
1
2
R67
0_0402_5%

<19> NB_PWRGD

E17
F17
F15

120mA

+VDDA18PCIEPLL

R77

AVDD1(NC)
AVDD2(NC)
AVDDDI(NC)
AVSSDI(NC)
AVDDQ(NC)
AVSSQ(NC)

+NB_PLLVDD
+NB_HTPVDD

C155
1U_0402_6.3V4Z

U3C
F12
E12
F14
G15
H15
H14

DAC_RSET
G14
2
715_0402_1%
65mA
+NB_PLLVDD
A12
+NB_HTPVDD 20mA
D14
B12

1
R65

GMCH_CRT_HSYNC
GMCH_CRT_VSYNC
GMCH_CRT_CLK
GMCH_CRT_DATA

<14,17> GMCH_CRT_HSYNC
<14,17> GMCH_CRT_VSYNC
<17> GMCH_CRT_CLK
<17> GMCH_CRT_DATA

L9
1

GMCH_CRT_B

<17> GMCH_CRT_B

+VDDA18PCIEPLL

FBMA-L11-160808-221LMT 0603
C154
2.2U_0603_6.3V4Z

GMCH_CRT_G

<17> GMCH_CRT_G

+1.8VS

GMCH_CRT_R

<17> GMCH_CRT_R

<8,19,28> SB_PWRGD

AMD suggest

+1.8VS

+VDDA18HTPLL

NB_LDTSTOP#

4
U8

+AVDDDI

L6

+1.8VS

NB_PWRGD

TXOUT0+ <15>
TXOUT0- <15>
TXOUT1+ <15>
TXOUT1- <15>
TXOUT2+ <15>
TXOUT2- <15>

L8
+VDDLTP18
1
C152
1U_0402_6.3V4Z

15mA

STRP_DATA
RSVD
AUX_CAL(NC)

TMDS_HPD(NC)
HPD(NC)

D9
D10

SUS_STAT#(PWM_GPIO5)

D12

THERMALDIODE_P
THERMALDIODE_N

AE8
AD8

TESTMODE

D13

+VDDLT18
1

C156
0.1U_0402_16V4Z

+VDDLT18

+1.8VS

L10
1
2
BLM18AG601SN1D_2P

+1.8VS

C157
4.7U_0805_10V4Z

GMCH_ENVDD <15>
VARY_ENBKL

R73

MIS.

FBMA-L11-160808-221LMT 0603
C153
2.2U_0603_6.3V4Z
2

+VDDLTP18

300mA

1
1

TXCLK+ <15>
TXCLK- <15>

R74

2
1
4.7K_0402_5%

R64

125mA

2
1
4.7K_0402_5%

FBMA-L11-160808-221LMT 0603
C145
0.1U_0402_16V4Z

FBMA-L11-160808-221LMT 0603
C146
2.2U_0603_6.3V4Z

L4

+NB_HTPVDD
L5
1

2
1
4.7K_0402_5%

+1.8VS

<8,18> LDT_STOP#

C144
1

CRT/TVOUT

4.7U_0603_6.3V6K

PLL PWR
LVTM

4.7U_0603_6.3V6K
L3

C142
1U_0402_6.3V4Z

+1.8VS
R63
2.2K_0402_5%

+3VS

PM

C684

+AVDD1

FBMA-L11-160808-221LMT 0603
C141
2.2U_0603_6.3V4Z

C679

C696
2

+1.8VS

+NB_PLLVDD
L2
1

CLOCKs

+1.1VS

R417
@
300_0402_5%

+1.8VS

0.1U_0402_16V4Z
1
2
5

+1.8VS

R71 1 UNVB@ 2 0_0402_5%

ENBKL <28>

R72 1 VB@

2 0_0402_5%

GMCH_INVT_PWM <15>

R76 1 VB@

2 0_0402_5%
3

If support VB, pop VB@ and reserve R71

R75
GMCH_HDMI_DET <16>
@

1
R81

2
0_0402_5%

SUS_STAT# <19>

To SB

SUS_STAT_R# <14>Strap

pin

1
2
R84
1.8K_0402_5%

RS780M_FCBGA528
RS880
HIGH
LOW

POWER_SEL

RS880 A11(SA000032710)

0.95V
1.1V
1
R87
1
R88
1
R89

GMCH_CRT_R
2
140_0402_1%
GMCH_CRT_G
2
150_0402_1%
GMCH_CRT_B
2
150_0402_1%

+1.8VS

R90
1K_0402_5%
2

<18> ALLOW_LDTSTOP

R91
1

2010/04/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

0_0402_5%
NB_ALLOW_LDTSTOP
2

2010/10/12

Deciphered Date

Title

RS880 VEDIO/CLK GEN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

PEW/76/86/96 LA-6552P
Sheet

Thursday, July 22, 2010


E

13

of

45

Rev
B

0.1U_0402_16V4Z

+VDDHT

L14
2

+1.1VS

C261
@
10U_0805_10V4Z

C174

1
C175

4.7U_0603_6.3V6K

C178

C202

2
2
2
2
0.1U_0402_16V4Z 1U_0402_6.3V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z 0.1U_0402_16V4Z +VDDA18PCIE


1

C179
2

C177

1
C192

1
C185

1
C190

2
2
0.1U_0402_16V4Z

AE25
AD24
AC23
AB22
AA21
Y20
W19
V18
U17
T17
R17
P17
M17

700mA

J10
P10
K10
M10
L10
W9
H9
T10
R10
Y9
AA9
AB9
AD9
AE9
U10

1
C186
2
0.1U_0402_16V4Z

4.7U_0603_6.3V6K

10mA

F9
G9
AE11
AD11

+1.8VS

C197
1U_0402_6.3V4Z

5mA

VDDHTTX_1
VDDHTTX_2
VDDHTTX_3
VDDHTTX_4
VDDHTTX_5
VDDHTTX_6
VDDHTTX_7
VDDHTTX_8
VDDHTTX_9
VDDHTTX_10
VDDHTTX_11
VDDHTTX_12
VDDHTTX_13
VDDA18PCIE_1
VDDA18PCIE_2
VDDA18PCIE_3
VDDA18PCIE_4
VDDA18PCIE_5
VDDA18PCIE_6
VDDA18PCIE_7
VDDA18PCIE_8
VDDA18PCIE_9
VDDA18PCIE_10
VDDA18PCIE_11
VDDA18PCIE_12
VDDA18PCIE_13
VDDA18PCIE_14
VDDA18PCIE_15
VDD18_1
VDD18_2
VDD18_MEM1(NC)
VDD18_MEM2(NC)

K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22

AE10
AA11
Y11
AD10
AB10
AC10

VDD_MEM1(NC)
VDD_MEM2(NC)
VDD_MEM3(NC)
VDD_MEM4(NC)
VDD_MEM5(NC)
VDD_MEM6(NC)

H11
H12

VDD33_1(NC)
VDD33_2(NC)

2
2 0.1U_0402_16V4Z
0.1U_0402_16V4Z

+NB_CORE

10A

23mA

1
+
2

220U_C6_6.3V_M_R15

C181

1
1

C172
C173

C189

L15
2
1
FBMA-L11-201209-221LMA30T_0805
1

1
C176

4.7U_0603_6.3V6K

+1.8VS

680mA

0.1U_0402_16V4Z 0.1U_0402_16V4Z +VDDHTTX

FBMA-L11-201209-221LMA30T_0805

2 1U_0402_6.3V4Z
2 1U_0402_6.3V4Z

C196

2
0.1U_0402_16V4Z

VDDHTRX_1
VDDHTRX_2
VDDHTRX_3
VDDHTRX_4
VDDHTRX_5
VDDHTRX_6
VDDHTRX_7

C184

2
2
2
2
4.7U_0805_10V4Z 0.1U_0402_16V4Z

H18
G19
F20
E21
D22
B23
A23

2 4.7U_0805_10V4Z

1
1

10U_0805_10V4Z

700mA

C201

C168
C171

C195

C161

C163

10U_0805_10V4Z

2 10U_0805_10V4Z
2 10U_0805_10V4Z

C183

C170

1
1

0.1U_0402_16V4Z

C169

+VDDHTRX
1

C160
C162

C188

C164

+VDDA11PCIE

0.1U_0402_16V4Z

2.5A

C180

0.1U_0402_16V4Z

FBMA-L11-201209-221LMA30T_0805

A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9

VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8
VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17

0.1U_0402_16V4Z

1U_0402_6.3V4Z

PART 5/6

C194

L13

VDDHT_1
VDDHT_2
VDDHT_3
VDDHT_4
VDDHT_5
VDDHT_6
VDDHT_7

0.1U_0402_16V4Z

U3E
J17
K16
L16
M16
P16
R16
T16

C193

2
0.1U_0402_16V4Z

+1.1VS

0.1U_0402_16V4Z

2
2
2
0.1U_0402_16V4Z

1
2
FBMA-L11-201209-221LMA30T_0805

C187

C200

0.1U_0402_16V4Z

C167

L12

C182

2
4.7U_0805_10V4Z

U3F

0.1U_0402_16V4Z

C159

C191

C166

0.1U_0402_16V4Z

C165

600mA

0.1U_0402_16V4Z

FBMA-L11-201209-221LMA30T_0805

1U_0402_6.3V4Z

POWER

A25
D23
E22
G22
G24
G25
H19
J22
L17
L22
L24
L25
M20
N22
P20
R19
R22
R24
R25
H20
U22
V19
W22
W24
W25
Y21
AD25

VSSAHT1
VSSAHT2
VSSAHT3
VSSAHT4
VSSAHT5
VSSAHT6
VSSAHT7
VSSAHT8
VSSAHT9
VSSAHT10
VSSAHT11
VSSAHT12
VSSAHT13
VSSAHT14
VSSAHT15
VSSAHT16
VSSAHT17
VSSAHT18
VSSAHT19
VSSAHT20
VSSAHT21
VSSAHT22
VSSAHT23
VSSAHT24
VSSAHT25
VSSAHT26
VSSAHT27

L12
M14
N13
P12
P15
R11
R14
T12
U14
U11
U15
V12
W11
W15
AC12
AA14
Y18
AB11
AB15
AB17
AB19
AE20
AB21
K11

VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34

60mA

RS880 A11(SA000032710)

C198
0.1U_0402_16V4Z

VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8
VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30
VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10

A2
B1
D3
D5
E4
G1
G2
G4
H7
J4
R7
L1
L2
L4
L7
M6
N4
P6
R1
R2
R4
V7
U4
V8
V6
W1
W2
W4
W7
W8
Y6
AA4
AB5
AB1
AB7
AC3
AC4
AE1
AE4
AB2

AE14
D11
G8
E14
E15
J15
J12
K14
M11
L15

RS780M_FCBGA528

+3VS
1

RS780M_FCBGA528

PART 6/6

GROUND

L11

1.3A
+1.1VS

RS880 A11(SA000032710)

1
C199

0.1U_0402_16V4Z

U3D

DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb

Debug Mode
2
R92
2
R93

1
3K_0402_5%
1
3K_0402_5%

Enables the Test Debug Bus using GPIO. (VSYNC)


1 : Disable
0 : Enable

+3VS

DFT_GPIO1: LOAD_EEPROM_STRAPS

Load EEPROM Strap


D1 @
CH751H-40_SC76
2
1

<13> SUS_STAT_R#

2
R264 @

Selects Loading of STRAPS from EPROM


1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use
default values if not connected

A_RST# <13,18,28>

1
3K_0402_5%

Enable Side Port Memory

Enable Side Port Memory


4

<13,17> GMCH_CRT_HSYNC

2
R94
2
R95

1
3K_0402_5%
1
3K_0402_5%

RS880: HSYNC#
0:
Enable
1 : Disable

+3VS

MEM_A0(NC)
MEM_A1(NC)
MEM_A2(NC)
MEM_A3(NC)
MEM_A4(NC)
MEM_A5(NC)
MEM_A6(NC)
MEM_A7(NC)
MEM_A8(NC)
MEM_A9(NC)
MEM_A10(NC)
MEM_A11(NC)
MEM_A12(NC)
MEM_A13(NC)

AD16
AE17
AD17

MEM_BA0(NC)
MEM_BA1(NC)
MEM_BA2(NC)

W12
Y12
AD18
AB13
AB18
V14

MEM_RASb(NC)
MEM_CASb(NC)
MEM_WEb(NC)
MEM_CSb(NC)
MEM_CKE(NC)
MEM_ODT(NC)

V15
W14

MEM_CKP(NC)
MEM_CKN(NC)

AE12
AD12

Register Readback of strap:


NB_CLKCFG:CLK_TOP_SPARE_D[1]

MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)
MEM_DQ2/DVO_DE(NC)
MEM_DQ3/DVO_D0(NC)
MEM_DQ4(NC)
MEM_DQ5/DVO_D1(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)
MEM_DQ9/DVO_D5(NC)
MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)
MEM_DQ12(NC)
MEM_DQ13/DVO_D9(NC)
MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)

AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21

MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)
MEM_DQS1P(NC)
MEM_DQS1N(NC)

Y17
W18
AD20
AE21

MEM_DM0(NC)
MEM_DM1/DVO_D8(NC)

W17
AE19

IOPLLVDD18(NC)
IOPLLVDD(NC)

AE23
AE24

IOPLLVSS(NC)

AD23

MEM_VREF(NC)

AE18

MEM_COMPP(NC)
MEM_COMPN(NC)

+1.8VS
+1.1VS

Compal Electronics, Inc.

Compal Secret Data


2010/04/12

2010/10/12

Deciphered Date

Title

RS880 PWR/GND

Date:

26mA

RS880 A11(SA000032710)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

15mA

RS780M_FCBGA528

Security Classification
Issued Date

SBD_MEM/DVO_I/F

Side port and Strap setting


<13,17> GMCH_CRT_VSYNC

PAR 4 OF 6
AB12
AE16
V11
AE15
AA12
AB16
AB14
AD14
AD13
AD15
AC16
AE13
AC14
Y14

PEW/76/86/96 LA-6552P
Sheet

Thursday, July 22, 2010


E

14

of

45

Rev
B

LCD POWER CIRCUIT

JLVDS1

+LCDVDD
1

W=60mils
1

R250
300_0603_5%

41
42
43
44
45
46

+3VS

+3VALW

R251
100K_0402_5%

C538

G1
G2
G3
G4
G5
G6

4.7U_0805_10V4Z

1
1K_0402_5%
1
C539

1
GMCH_ENVDD

Q23

<13> GMCH_ENVDD

S
2N7002_SOT23

2N7002_SOT23

+LCDVDD

W=60mils

0.047U_0402_16V7K
2

2
G

1 R507
2
100K_0402_5%

AO3413_SOT23-3
Q13

2
R252

2
G

Q11

2
D

C540

4.7U_0805_10V4Z
2

<NCQD0 use>
C541
0.1U_0402_16V4Z

+3VS
+LCDVDD
B+
1

+INVPWR_B+

W=40mils

L59 2
1
FBMA-L11-201209-221LMA30T_0805
C544

BKOFF#

<28> BKOFF#

C545

680P_0402_50V7K 68P_0402_50V8J
2
2

D9
CH751H-40PT_SOD323-2
@
1
2

R121
@
4.7K_0402_5%
2

L58 2
1
FBMA-L11-201209-221LMA30T_0805

R172 1

2 0_0402_5%

R171 1

2 10K_0402_5%

C546

C547

DISPOFF#
2

10U_0805_10V4Z

INVT_PWM
DISPOFF#

INVT_PWM
DISPOFF#
GMCH_LCD_CLK
GMCH_LCD_DATA
TXOUT0TXOUT0+
TXOUT1TXOUT1+
TXOUT2TXOUT2+
TXCLKTXCLK+

DMIC_DATA_R
DMIC_CLK_R
+3VS_DMIC

@
2
+LCDVDD R841

1
0_0603_5%

+LCDVDD

W=60mils

+3VS

GMCH_LCD_CLK <13>
GMCH_LCD_DATA <13>
DAC_BRIG <28>

TXOUT0- <13>
TXOUT0+ <13>
TXOUT1- <13>
TXOUT1+ <13>
TXOUT2- <13>
TXOUT2+ <13>
TXCLK- <13>
TXCLK+ <13>

R842
R885
R886
R843
R887

@
@
@
@
@

2
2
2
2
2

1
1
1
1
1

0_0402_5%
0_0603_5%
0_0603_5%
0_0402_5%
0_0402_5%

DMIC_DATA
DMIC_CLK

LOCAL_DIM <28>
DMIC_DATA <30>
DMIC_CLK <30>
COLOY_ENG_EN <28>

+3VS

+3VS
USB20_N5 <19>
USB20_P5 <19>

INVT_PWM

@
1
2
C1024 @
1
2
C1025 @
1
2
C542
1
2
C543
1
2
C548

+3VS

220P_0402_50V7K

CH3

Vp

CH2

Vn

CH1

USB20_N5

220P_0402_50V7K
USB20_P5
220P_0402_50V7K

CH4

CM1293-04SO_SOT23-6
220P_0402_50V7K
220P_0402_50V7K

VB@ 2
1
R262
0_0402_5%

+LCDVDD_L

R319
10K_0402_5%
@
2

<13> GMCH_INVT_PWM

GMCH_INVT_PWM

+INVPWR_B+

DAC_BRIG

1 UNVB@ 2
R260
0_0402_5%

W=60mils

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

D14 @

DMIC_CLK_R

EC_INVT_PWM

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

IPEX_20143-040E-20F
CONN@

0.1U_0402_16V4Z

DMIC_DATA_R

<28> EC_INVT_PWM

LCD/LED PANEL Conn.

2010/04/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/10/12

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

LVDS Connector
Document Number

PEW/76/86/96 LA-6552P
Sheet

Thursday, July 22, 2010


1

15

of

45

Rev
B

+3VS

+3VS

+HDMI_5V_OUT

W=40mils
2
1

1.1A_6VDC_FUSE
HDMI@

C549
0.1U_0402_16V4Z
HDMI@
JHDMI1

HDMI_SCLK

HDMI_HPD
+HDMI_5V_OUT

Q16
BSH111 1N_SOT23-3

HDMI_SDATA
HDMI_SCLK
HDMI_SDATA

1
D

S
@

1
D

<5V tolerant>
<13> GMCH_HDMI_DATA

3
S

<13> GMCH_HDMI_CLK

F1
1+HDMI_5V_OUT_1 1

RB491D_SC59-3
HDMI@

R277
4.7K_0402_5%
HDMI@
2

1
2

@
D

4.7K_0402_5%

R276
HDMI@

10K_0402_5%

R275
1

2
R274
1

+5VS

10K_0402_5%

+HDMI_5V_OUT
D3

HDMI_R_CK-

Q17
BSH111 1N_SOT23-3

HDMI_R_CK+
HDMI_R_D0-

2 HDMI@ 1
R278
0_0402_5%

HDMI_R_D0+
HDMI_R_D1-

2 HDMI@ 1
R279
0_0402_5%

HDMI_R_D1+
HDMI_R_D2-

Check 5V tolerant

HDMI_R_D2+

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

Place closed to JHDMI1

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+

20
21
22
23

SUYIN_100042MR019S153ZL
CONN@

<NAV70 use>

+3VS

HDMI@
R280
0_0402_5%

+HDMI_5V_OUT
C

GMCH_HDMI_DET

GMCH_HDMI_DET

<13> GMCH_HDMI_DET

U40
@

HDMI@
HDMI_HPD
2
1
2
B
R281
150K_0402_5%
E HDMI@
Q18
MMBT3904_NL_SOT23-3
R283
365K_0402_1%
HDMI@
1

1 1

R284
10K_0402_5%
HDMI@

R411
100K_0402_5%
@

+3VS

4.7K_0402_5%

2
0.1U_0402_16V7K

P
OE#

5
1

C687
0.1U_0402_16V7K
@

@
1 R304

C681

HDMI_HPD

SN74AHCT1G125GW_SOT353-5

Reserve

HDMI@
HDMI_C_CLK-

UMA 715 ohm


<12> GMCH_HDMI_TXD2<12> GMCH_HDMI_TXD2+

1 0.1U_0402_16V7K
1 0.1U_0402_16V7K

HDMI_C_TX2HDMI_C_TX2+

<12> GMCH_HDMI_TXD1<12> GMCH_HDMI_TXD1+

C552 HDMI@2
C553 HDMI@2

1 0.1U_0402_16V7K
1 0.1U_0402_16V7K

<12> GMCH_HDMI_TXD0<12> GMCH_HDMI_TXD0+

C554 HDMI@2
C555 HDMI@2

<12> GMCH_HDMI_TXC<12> GMCH_HDMI_TXC+

C556 HDMI@2
C557 HDMI@2

R286 1 HDMI@ 2
R287 1 HDMI@ 2

715_0402_1%
715_0402_1%

HDMI_C_TX1HDMI_C_TX1+

R289 1 HDMI@ 2
R290 1 HDMI@ 2

715_0402_1%
715_0402_1%

1 0.1U_0402_16V7K
1 0.1U_0402_16V7K

HDMI_C_TX0HDMI_C_TX0+

R292 1 HDMI@ 2
R293 1 HDMI@ 2

715_0402_1%
715_0402_1%

1 0.1U_0402_16V7K
1 0.1U_0402_16V7K

HDMI_C_CLKHDMI_C_CLK+

R294 1 HDMI@ 2
R295 1 HDMI@ 2

715_0402_1%
715_0402_1%

1
R298

HDMI_C_TX0-

10mil

2
G

2N7002_SOT23
Q19
HDMI@

HDMI_C_TX1-

10mil

HDMI_C_TX1+

100K_0402_5%

HDMI_C_TX2-

3
HDMI_R_CK+

R291 1 HDMI@ 2

0_0402_5%

HDMI_R_D0-

HDMI@

R296 1

3
HDMI@

R297 1 HDMI@ 2

R299
R300

L63
WCM-2012-900T_0805
@
4
HDMI_C_TX2+

HDMI_R_CK-

0_0402_5%

Place closed to JHDMI1

1
L62
WCM-2012-900T_0805
@
4

HDMI@

0_0402_5%

R288 1

1
L61
WCM-2012-900T_0805
@
4

10mil

HDMI_C_TX0+

0_0402_5%
2
HDMI@

HDMI_C_CLK+

R302 1

+HDMI_5V_OUT

L60
WCM-2012-900T_0805
@
4

C550 HDMI@2
C551 HDMI@2

R285 1

2
3
0_0402_5%

HDMI_R_D0+

0_0402_5%

HDMI_R_D1-

2
3

0_0402_5%

HDMI_R_D1+

1 HDMI@ 2

0_0402_5%

HDMI_R_D2-

HDMI@

R301 1

3
HDMI@

2
3
0_0402_5%

HDMI_R_D2+

2010/04/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/10/12

Deciphered Date

Title

HDMI Connector

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

PEW/76/86/96 LA-6552P
Sheet

Thursday, July 22, 2010


1

16

of

45

Rev
B

CRT Connector

W=40mils
+R_CRT_VCC

+5VS
D7
2

RB491D_SC59-3
D5
PJDLC05C_SOT23-3
@

W=40mils

2
1.1A_6VDC_FUSE
1

C558
0.1U_0402_16V4Z

D4
PJDLC05C_SOT23-3
@

+CRT_VCC

F2

CRT_R_1

GMCH_CRT_G

2
R408

1
0_0402_5%

CRT_G_1

L65 1

2 FCM2012CF-800T06_2P

CRT_G_2

GMCH_CRT_B

2
R409

1
0_0402_5%

CRT_B_1

L66 1

2 FCM2012CF-800T06_2P

CRT_B_2

<13> GMCH_CRT_B

1
0_0402_5%

R305

L64 1

R307

R308

C559

C560

2
10P_0402_50V8J

150_0402_1%
140_0402_1%

2 FCM2012CF-800T06_2P

CRT_R_2

JCRT1
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

<13> GMCH_CRT_G

2
R407

GMCH_CRT_R

<13> GMCH_CRT_R

150_0402_1%

C561

C562

2
10P_0402_50V8J

C563

2
10P_0402_50V8J

C564

2
10P_0402_50V8J
10P_0402_50V8J

10P_0402_50V8J

C565

<NAL00 use>
16
17

G
G

C-H_13-12201513CP
CONN@

100P_0402_50V8J

+CRT_VCC

A
3

CRT_HSYNC_1

C566
10P_0402_50V8J

CRT_VSYNC_2
1

C567
10P_0402_50V8J

74AHCT1G125GW_SOT353-5

R311
100K_0402_5%
@

C568 2
68P_0402_50V8J 1

+CRT_VCC
2

C570
68P_0402_50V8J

+CRT_VCC

P
2

1
OE#

GMCH_CRT_VSYNC

U19
Y

CRT_VSYNC_1

<13,14> GMCH_CRT_VSYNC

DSUB_15

2 0.1U_0402_16V4Z
5

C571 1

DSUB_12

L68 1
2
FCM2012CF-800T06_2P

U18

CRT_DET# <19>

CRT_HSYNC_2

P
GMCH_CRT_HSYNC

L67 1
2
FCM2012CF-800T06_2P

1 10K_0402_5%

<13,14> GMCH_CRT_HSYNC

R312 2
5

2 0.1U_0402_16V4Z

OE#

C569 1

74AHCT1G125GW_SOT353-5

Change as SA411250110

Close to Conn side


+CRT_VCC
+3VS
1

2
G

R318
4.7K_0402_5%
2

R317
4.7K_0402_5%

@
D

GMCH_CRT_DATA

3
S

DSUB_12

GMCH_CRT_DATA <13>

2
G

Q53
BSH111 1N_SOT23-3
1

@
DSUB_15

GMCH_CRT_CLK

GMCH_CRT_CLK <13>

Q65
BSH111 1N_SOT23-3
2
R321

1
0_0402_5%

2
R323

1
0_0402_5%

Check 5V tolerant for DISO state

2010/04/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/10/12

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

CRT Connector
Document Number

PEW/76/86/96 LA-6552P
Sheet

Thursday, July 22, 2010


E

17

of

45

Rev
B

R370

level shift to ISL6265


<13> CLK_SBLINK_BCLK
<13> CLK_SBLINK_BCLK#
<13> NB_DISP_CLKP
<13> NB_DISP_CLKN

ISL6265 PWROK input, TTL level: 0.8V~2.0V


When this pin is high, the SVI interface is
active and I2C protocol is running. While this
pin is low, the SVC, SVD, and VFIXEN input
states determine the pre-PWROK metal VID or
VFIX mode voltage. This pin must be low prior
to the ISL6265 PGOOD output going high

<13> CLK_NBHT
<13> CLK_NBHT#

NB HT
CPU

LAN

MINI

<8> CLK_CPU_BCLK
<8> CLK_CPU_BCLK#

<24> CLK_PCIE_LAN
<24> CLK_PCIE_LAN#

<26> CLK_PCIE_MINI1
<26> CLK_PCIE_MINI1#

25M_CLK_X1

PCIE_RCLKP/NB_LNK_CLKP
PCIE_RCLKN/NB_LNK_CLKN

U29
U28

NB_DISP_CLKP
NB_DISP_CLKN

T26
T27

NB_HT_CLKP
NB_HT_CLKN

V21
T21

CPU_HT_CLKP
CPU_HT_CLKN

V23
T23

SLT_GFX_CLKP
SLT_GFX_CLKN

L29
L28

GPP_CLK0P
GPP_CLK0N

N29
N28

GPP_CLK1P
GPP_CLK1N

M29
M28

GPP_CLK2P
GPP_CLK2N

T25
V25

GPP_CLK3P
GPP_CLK3N

L24
L23

GPP_CLK4P
GPP_CLK4N

P25
M25

GPP_CLK5P
GPP_CLK5N

P29
P28

GPP_CLK6P
GPP_CLK6N

N26
N27

GPP_CLK7P
GPP_CLK7N

T29
T28

GPP_CLK8P
GPP_CLK8N

L25

14M_25M_48M_OSC

1
2
C689
27P_0402_50V8J

M23
P23

Y6

R426
1M_0603_5%

25MHZ_20PF_7A25000012
25M_CLK_X2

1
2
C688
27P_0402_50V8J

AMD suggest add Crystal for Internal CLK GEN


<26> CLK_SD_48M

INTE#/GPIO32
INTF#/GPIO33
INTG#/GPIO34
INTH#/GPIO35

CLOCK GENERATOR

NB A LINK

LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
LDRQ1#/CLK_REQ6#/GPIO49
SERIRQ/GPIO48

ALLOW_LDTSTP/DMA_ACTIVE#
PROCHOT#
LDT_PG
LDT_STP#
LDT_RST#

@ R332 20M_0402_5%
@R332
1
2

L27

PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29

H24
H25
J27
J26
H29
H28
G28
J25
AA18
AB19

LPCCLK0

<22>
<20,22>
<22>
<22>
<22>
<22>
<22>

PCI_AD24 : VDDR Voltage SW

+RTCBATT

LPC_CLK0_EC
2
22_0402_5%

1
R330

G21
H21
K19
G22
J24

ALLOW_LDTSTOP <13>
H_PROCHOT_R# <8>
H_PWRGD <8>
LDT_STOP# <8,13>
LDT_RST# <8>

32K_X2

C2

SB_32KHO

RTCCLK
INTRUDER_ALERT#
VDDBT_RTC_G

D2
B2
B1

R331
1K_0402_5%

EC_CLK <28>
+RTCVCC

OSC

NC

Close to SB

1 C585

2
510_0402_5%

W=20mils

R334

C583

@
0_0603_5%

for Clear CMOS

2010/04/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

18P_0402_50V8J

2010/10/12

Deciphered Date

Title

SB820-PCIE/PCI/ACPI/LPC/RTC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

+CHGRTC

DAN202UT106_SC70-3

32.768KHZ_12.5PF_Q13MC14610002
SB_32KHO

D8
2

C584 1

NC

SUYIN_060003HA002G202ZL

SERIRQ <28>

0.1U_0402_16V4Z

C586

OSC

CONN@
PBJ1

LPC_CLK0_EC <22,28>
LPC_CLK1 <22>

LPC_AD0 <28>
LPC_AD1 <28>
LPC_AD2 <28>
LPC_AD3 <28>
LPC_FRAME# <28>

Y3
1

PLT_RST# <24,26>

NC7SZ08P5X_NL_SC70-5

CLKRUN# <28>

SB_32KHI

R335
20M_0603_5%

PLT_RST#

SB820M_FCBGA605

18P_0402_50V8J

PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29

1
R333

AJ6
AG6
AG4
AJ4

C582
1

U21
Y

SB_32KHI

25M_X1

25M_X2

+RTCBATT

RTC

25M_CLK_X2

L26

R328
8.2K_0402_5%
@

C1

32K_X1
25M_CLK_X1

0.1U_0402_16V4Z

H_PWRGD_L <42>

0.1U_0402_16V4Z

1
FDV301N_NL_SOT23-3

A_RST#

3
Q21

2
@ 0_0402_5%
2
0_0402_5%

GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N

1
R427
1
R425

AA22
Y21
AA25
AA24
W23
V24
W24
W25

AMD suggest add GPIO control gate


<19> SB_GPIO_A_RST#

1U_0402_6.3V4Z

H_PWRGD

R329
4.7K_0402_5%

C581
1
2

GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N

AA28
AA29
Y29
Y28
Y26
Y27
W28
W29

+3VALW

+3VS
+1.5VS

PCIE_CALRP
PCIE_CALRN

AA1
AA4
AA3
AB1
AA5
AB2
AB6
AB5
AA6
AC2
AC3
AC4
AC1
AD1
AD2
AC6
AE2
AE1
AF8
AE3
AF1
AG1
AF2
AE9
AD9
AC11
AF6
AF4
AF3
AH2
AG2
AH3
AA8
AD5
AD8
AA10
AE8
AB9
AJ3
AE7
AC5
AF5
AE6
AE4
AE11
AH5
AH4
AC12
AD12
AJ5
AH6
AB12
AB11
AD7

T26

590_0402_1% AD29
2K_0402_1% AD28

AD0/GPIO0
AD1/GPIO1
AD2/GPIO2
AD3/GPIO3
AD4/GPIO4
AD5/GPIO5
AD6/GPIO6
AD7/GPIO7
AD8/GPIO8
AD9/GPIO9
AD10/GPIO10
AD11/GPIO11
AD12/GPIO12
AD13/GPIO13
AD14/GPIO14
AD15/GPIO15
AD16/GPIO16
AD17/GPIO17
AD18/GPIO18
AD19/GPIO19
AD20/GPIO20
AD21/GPIO21
AD22/GPIO22
AD23/GPIO23
AD24/GPIO24
AD25/GPIO25
AD26/GPIO26
AD27/GPIO27
AD28/GPIO28
AD29/GPIO29
AD30/GPIO30
AD31/GPIO31
CBE0#
CBE1#
CBE2#
CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
PAR
STOP#
PERR#
SERR#
REQ0#
REQ1#/GPIO40
REQ2#/CLK_REQ8#/GPIO41
REQ3#/CLK_REQ5#/GPIO42
GNT0#
GNT1#/GPO44
GNT2#/GPO45
GNT3#/CLK_REQ7#/GPIO46
CLKRUN#
LOCK#

PAD

A_RX0P
A_RX0N
A_RX1P
A_RX1N
A_RX2P
A_RX2N
A_RX3P
A_RX3N

V2

<22>
<22>
<22>
<22>

AE24
AE23
AD25
AD24
AC24
AC25
AB25
AB24

PCIRST#

PCI_CLK1
PCI_CLK2
PCI_CLK3
PCI_CLK4

1
1

A_TX0P
A_TX0N
A_TX1P
A_TX1N
A_TX2P
A_TX2N
A_TX3P
A_TX3N

+1.1VS_PCIE

2
2

AD26
AD27
AC28
AC29
AB29
AB28
AB26
AB27

W2
W1
W3
W4
Y1

R326
R327

SB_RX0P_C
SB_RX0N_C
SB_RX1P_C
SB_RX1N_C
SB_RX2P_C
SB_RX2N_C
SB_RX3P_C
SB_RX3N_C

PCICLK0
PCICLK1/GPO36
PCICLK2/GPO37
PCICLK3/GPO38
PCICLK4/14M_OSC/GPO39

2
2
2
2
2
2
2
2

Part 1 of 5

PCI INTERFACE

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

1
1
1
1
1
1
1
1

SB800
PCIE_RST#
A_RST#

LPC

<12>
<12>
<12>
<12>
<12>
<12>
<12>
<12>

C579
C573
C574
C575
C576
C580
C577
C578

U20A
33_0402_5%
P1
1
1 33_0402_5%L1

CPU

SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N

@
2
2
R325
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

PCI CLKS

A_RST#

<13,14,28> A_RST#
<12>
<12>
<12>
<12>
<12>
<12>
<12>
<12>

2 150P_0402_50V8J

PCI EXPRESS INTERFACES

C572 1

PEW/76/86/96 LA-6552P
Sheet

Thursday, July 22, 2010


E

18

of

45

Rev
B

<24,26> SB_PCIE_WAKE#

+3VS

R340 1

R341 1
R415 1

2 2.2K_0402_5%

<8> H_THERMTRIP#
<13> NB_PWRGD

SKU ID: 1-> VGA


0-> UMA

SKU_ID

2 2.2K_0402_5%

R416 1

2 100K_0402_5%

R418 1 VB@

2 2.2K_0402_5%

EC_RSMRST#

<28> EC_RSMRST#

2 100K_0402_5%

ACF_EN
PX_FN

PX Function: 1-> PX Enable


0-> PX Disable *

VB_EN

VB Function: 1-> VB Enable


0-> VB Disable *

Mini Card

<26> MINI1_CLKREQ#
<18> SB_GPIO_A_RST#

<30> SB_SPKR
<10,11,26> SB_SMCLK0
<10,11,26> SB_SMDAT0

R588 1 UNVB@ 2 100K_0402_5%

Cinfigure to output or Internal PU/PD


Check SW:
R402 1
2

2 2.2K_0402_5%

1 100K_0402_5%

R846 1

2 2.2K_0402_5%

R406

R847

LAY_SEL: 1-> 6L*


0-> 8L

ACF_EN

MUXLESS_SEL

LAN

SB_GPIO_A_RST#
SKU_ID
MUXLESS_SEL
PX_FN
SB_SMCLK0
SB_SMDAT0
SB_SMCLK1
SB_SMDAT1
VB_EN

<24> LAN_CLKREQ#

MUXLESS SEL: 1->PX with Muxless


0->PX with Mux

100K_0402_5%

<28> EC_LID_OUT#

EC_LID_OUT#
T27

<27> USB_OC#2
<27> USB_OC#1
<27> USB_OC#0
<30>
<22>
<30>
<30>

HDA_BITCLK_AUDIO
HDA_SDOUT
HDA_SDOUT_AUDIO
HDA_SDIN0

<30> HDA_SYNC_AUDIO
<30> HDA_RST_AUDIO#

PAD

USB_OC#2
USB_OC#1
USB_OC#0

R345 1

2 33_0402_5%

R346 1

2 33_0402_5%

HDA_BITCLK
HDA_SDOUT
HDA_SDIN0
HDA_SDIN1

R347 1
R348 1

2 33_0402_5%
2 33_0402_5%

HDA_SYNC
HDA_RST#
GBE_COL
GBE_CRS

GBE_MDIO

+3VS
GBE_RXERR
@

1
R349
@
1
R350
@
1
R351

HDA_BITCLK

2
10K_0402_5%
HDA_SDIN0
2
10K_0402_5%
HDA_SDIN1
2
10K_0402_5%

R342 1

2 2.2K_0402_5% SB_SMCLK0

R343 1

2 2.2K_0402_5% SB_SMDAT0

R344 1

2 4.7K_0402_5%

SUS_STAT#
GBE_PHY_INTR
T28
T29

+3VALW
+3VALW
R352 1

1
R355
@
1
R357
1
R359
1
R360
1
R361
1
R362
1
R363

SB_PCIE_WAKE#
2
10K_0402_5%
EC_LID_OUT#
2
100K_0402_5%
SB_SIC
2
2.2K_0402_5%
SB_SID
2
2.2K_0402_5%
H_THERMTRIP#
2
10K_0402_5%
SB_SMCLK1
2
2.2K_0402_5%
SB_SMDAT1
2
2.2K_0402_5%

2 10K_0402_5%

R420 1

2 10K_0402_5%

R3531

2 10K_0402_5%

R428 1
R354 1

2 10K_0402_5%

USB 1.1 USB MISC

H9
J8

CLK_REQ4#/SATA_IS0#/GPIO64
CLK_REQ3#/SATA_IS1#/GPIO63
SMARTVOLT1/SATA_IS2#/GPIO50
CLK_REQ0#/SATA_IS3#/GPIO60
SATA_IS4#/FANOUT3/GPIO55
SATA_IS5#/FANIN3/GPIO59
SPKR/GPIO66
SCL0/GPIO43
SDA0/GPIO47
SCL1/GPIO227
SDA1/GPIO228
CLK_REQ2#/FANIN4/GPIO62
CLK_REQ1#/FANOUT4/GPIO61
IR_LED#/LLB#/GPIO184
SMARTVOLT2/SHUTDOWN#/GPIO51
DDR3_RST#/GEVENT7#
GBE_LED0/GPIO183
GBE_LED1/GEVENT9#
GBE_LED2/GEVENT10#
GBE_STAT0/GEVENT11#
CLK_REQG#/GPIO65/OSCIN
BLINK/USB_OC7#/GEVENT18#
USB_OC6#/IR_TX1/GEVENT6#
USB_OC5#/IR_TX0/GEVENT17#
USB_OC4#/IR_RX0/GEVENT16#
USB_OC3#/AC_PRES/TDO/GEVENT15#
USB_OC2#/TCK/GEVENT14#
USB_OC1#/TDI/GEVENT13#
USB_OC0#/TRST#/GEVENT12#

M3
N1
L2
M2
M1
M4
N2
P2

AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO167
AZ_SDIN1/GPIO168
AZ_SDIN2/GPIO169
AZ_SDIN3/GPIO170
AZ_SYNC
AZ_RST#
GBE_COL
GBE_CRS
GBE_MDCK
GBE_MDIO
GBE_RXCLK
GBE_RXD3
GBE_RXD2
GBE_RXD1
GBE_RXD0
GBE_RXCTL/RXDV
GBE_RXERR
GBE_TXCLK
GBE_TXD3
GBE_TXD2
GBE_TXD1
GBE_TXD0
GBE_TXCTL/TXEN
GBE_PHY_PD
GBE_PHY_RST#
GBE_PHY_INTR

E23
E24
F21
G29

PS2_DAT/SDA4/GPIO187
PS2_CLK/SCL4/GPIO188
SPI_CS2#/GBE_STAT2/GPIO166
FC_RST#/GPO160

D27
F28
F29
E27

PS2KB_DAT/GPIO189
PS2KB_CLK/GPIO190
PS2M_DAT/GPIO191
PS2M_CLK/GPIO192
SB820M_FCBGA605

2
R338

OHCI4

USB_HSD13P
USB_HSD13N

B12
A12

USB_HSD12P
USB_HSD12N

F11
E11

USB_HSD11P
USB_HSD11N

E14
E12

USB_HSD10P
USB_HSD10N

J12
J14

USB_HSD9P
USB_HSD9N

A13
B13

USB_HSD8P
USB_HSD8N

D13
C13

USB20_P8
USB20_N8

USB_HSD7P
USB_HSD7N

G12
G14

USB20_P7
USB20_N7

USB_HSD6P
USB_HSD6N

G16
G18

USB20_P6
USB20_N6

USB_HSD5P
USB_HSD5N

D16
C16

USB20_P5
USB20_N5

USB_HSD4P
USB_HSD4N

B14
A14

USB_HSD3P
USB_HSD3N

E18
E16

USB_HSD2P
USB_HSD2N

J16
J18

USB20_P2
USB20_N2

USB_HSD1P
USB_HSD1N

B17
A17

USB20_P1
USB20_N1

USB_HSD0P
USB_HSD0N

A16
B16

USB20_P0
USB20_N0

SCL2/GPIO193
SDA2/GPIO194
SCL3_LV/GPIO195
SDA3_LV/GPIO196
EC_PWM0/EC_TIMER0/GPIO197
EC_PWM1/EC_TIMER1/GPIO198
EC_PWM2/EC_TIMER2/GPIO199
EC_PWM3/EC_TIMER3/GPIO200

D25
F23
B26
E26
F25
E22
F22
E21

KSI_0/GPIO201
KSI_1/GPIO202
KSI_2/GPIO203
KSI_3/GPIO204
KSI_4/GPIO205
KSI_5/GPIO206
KSI_6/GPIO207
KSI_7/GPIO208

G24
G25
E28
E29
D29
D28
C29
C28

KSO_0/GPIO209
KSO_1/GPIO210
KSO_2/GPIO211
KSO_3/GPIO212
KSO_4/GPIO213
KSO_5/GPIO214
KSO_6/GPIO215
KSO_7/GPIO216
KSO_8/GPIO217
KSO_9/GPIO218
KSO_10/GPIO219
KSO_11/GPIO220
KSO_12/GPIO221
KSO_13/GPIO222
KSO_14/GPIO223
KSO_15/GPIO224
KSO_16/GPIO225
KSO_17/GPIO226

B28
A27
B27
D26
A26
C26
A24
B25
A25
D24
B24
C24
B23
A23
D22
C22
A22
B22

EHCI13 / OHCI3

USB20_P8 <26>
USB20_N8 <26>

Mini1-WLAN

USB20_P7 <27>
USB20_N7 <27>

BT

USB20_P6 <26>
USB20_N6 <26>

CardReader

USB20_P5 <15>
USB20_N5 <15>

Camera

USB20_P2 <27>
USB20_N2 <27>

Ext USB3

USB20_P1 <27>
USB20_N1 <27>

Ext USB2

USB20_P0 <27>
USB20_N0 <27>

Ext USB1

EHCI1 / OHCI1
<Wake Up support>

Check SW:
Cinfigure to output or Internal PU/PD
SB_SIC
SB_SID

GPIO199 <22>
GPIO200 <22>

STRAP PIN

GBE_CRS

2 10K_0402_5%
2 10K_0402_5%

R358 1

2 10K_0402_5%
@

2 10K_0402_5%

GBE_RXERR

2010/04/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
GBE_PHY_INTR

2010/10/12

Deciphered Date

Title

SB820 USB/HD audio

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

EHCI2 / OHCI2

2 10K_0402_5%
@

R430 1

R431 1

GBE_COL

USB_FSD0P/GPIO185
USB_FSD0N

RSMRST#

H3
D1
E4
D4
E8
F7
E7
F8

T1
T4
L6
L5
T9
U1
U3
T2
U2
T5
V5
P5
M5
P9
T7
P7
M7
P4
M9
V7

J10
H11

USB_RCOMP 1
11.8K_0402_1%

2 10K_0402_5%

R429 1
R356 1

GBE_MDIO

PAD
PAD

G1
AD19
AA16
AB21
AC18
AF20
AE19
AF19
AD22
AE22
F5
F4
AH21
AB18
E1
AJ21
H4
D5
D7
G5
K3
AA20

USB_FSD1P/GPIO186
USB_FSD1N

USB 2.0

EC_RSMRST#
2
2.2K_0402_5%

ACPI / WAKE UP EVENTS

<28> EC_GA20
<28> EC_KBRST#
<28> EC_SCI#
<28> EC_SMI#

SB800

G19

GPIO

2N7002_SOT23

A10

USB_RCOMP

USB OC

PM_SLP_S3#
PM_SLP_S5#
PBTN_OUT#
SB_PWRGD
SUS_STAT#

USBCLK/14M_25M_48M_OSC

EMBEDDED CTRL

3
1
R339

<28>
<28>
<28>
<8,13,28>
<13>

PCI_PME#/GEVENT4#
RI#/GEVENT22#
SPI_CS3#/GBE_STAT1/GEVENT21#
SLP_S3#
SLP_S5#
PWR_BTN#
PWR_GOOD
SUS_STAT#
Part 4 of 5
TEST0
TEST1/TMS
TEST2
GA20IN/GEVENT0#
KBRST#/GEVENT1#
LPC_PME#/GEVENT3#
LPC_SMI#/GEVENT23#
GEVENT5#
SYS_RESET#/GEVENT19#
WAKE#/GEVENT8#
IR_RX1/GEVENT20#
THRMTRIP#/SMBALERT#/GEVENT2#
NB_PWRGD

EMBEDDED CTRL

D
@
Q22

J2
K1
D3
F1
H1
F2
H5
SUS_STAT#
G6
B3
T24
PAD
C4
T22
PAD
F6
T23
PAD
AD21
AE21
K2
J29
H2
J1
H6
F3
H_THERMTRIP#
J6
NB_PWRGD
AC19
CRT_DET

2
G

<17> CRT_DET#

U20D
<28> EC_SWI#

CRT_DET

HD AUDIO

@
R336
100K_0402_5%

GBE LAN

+3VALW

PEW/76/86/96 LA-6552P
Sheet

Thursday, July 22, 2010


E

19

of

45

Rev
B

U20B

<23> SATA_DTX_C_SRX_N0
<23> SATA_DTX_C_SRX_P0

AJ8
AH8

SATA_RX0N
SATA_RX0P

AH10
AJ10

SATA_TX1P
SATA_TX1N

AG10
AF10

SATA_RX1N
SATA_RX1P

AG12
AF12

SATA_TX2P
SATA_TX2N

AJ12
AH12

SATA_RX2N
SATA_RX2P

AH14
AJ14

SATA_TX3P
SATA_TX3N

AG14
AF14

SATA_RX3N
SATA_RX3P

AG17
AF17

SATA_TX4P
SATA_TX4N

AJ17
AH17

SATA_RX4N
SATA_RX4P

AJ18
AH18

SATA_TX5P
SATA_TX5N

AH19
AJ19

SATA_RX5N
SATA_RX5P

<23> SATA_STX_DRX_P1
<23> SATA_STX_DRX_N1

ODD

<23> SATA_DTX_C_SRX_N1
<23> SATA_DTX_C_SRX_P1

+1.1VS_SATA

R364
2
2
R365

1K_0402_1%
SATA_CALRP
1
SATA_CALRN
1
931_0402_1%

<29> SATA_LED#
+3VS

R367 1

SATA_X2

SATA_ACT#/GPIO67

AC16

FC_OE#/GPIOD145
FC_AVD#/GPIOD146
FC_WE#/GPIOD148
FC_CE1#/GPIOD149
FC_CE2#/GPIOD150
FC_INT1/GPIOD144
FC_INT2/GPIOD147

AF28
AG29
AG26
AF27
AE29
AF29
AH27

FC_ADQ0/GPIOD128
FC_ADQ1/GPIOD129
FC_ADQ2/GPIOD130
FC_ADQ3/GPIOD131
FC_ADQ4/GPIOD132
FC_ADQ5/GPIOD133
FC_ADQ6/GPIOD134
FC_ADQ7/GPIOD135
FC_ADQ8/GPIOD136
FC_ADQ9/GPIOD137
FC_ADQ10/GPIOD138
FC_ADQ11/GPIOD139
FC_ADQ12/GPIOD140
FC_ADQ13/GPIOD141
FC_ADQ14/GPIOD142
FC_ADQ15/GPIOD143

AJ27
AJ26
AH25
AH24
AG23
AH23
AJ22
AG21
AF21
AH22
AJ23
AF23
AJ24
AJ25
AG25
AH26

SATA_X1

SATA_X2

SPI_DI/GPIO164
SPI_DO/GPIO163
SPI_CLK/GPIO162
SPI_CS1#/GPIO165
ROM_RST#/GPIO161

FANOUT0/GPIO52
FANOUT1/GPIO53
FANOUT2/GPIO54

W5
W6
Y9

FANIN0/GPIO56
FANIN1/GPIO57
FANIN2/GPIO58

W7
V9
W8

TEMPIN0/GPIO171
TEMPIN1/GPIO172
TEMPIN2/GPIO173
TEMPIN3/TALERT#/GPIO174
TEMP_COMM

B6
A6
A5
B5
C7

VIN0/GPIO175
VIN1/GPIO176
VIN2/GPIO177
VIN3/GPIO178
VIN4/GPIO179
VIN5/GPIO180
VIN6/GBE_STAT3/GPIO181
VIN7/GBE_LED3/GPIO182

A3
B4
A4
C5
A7
B7
B8
A8

NC1
NC2

@R366
@
R366
1
2
0_0402_5%

EC_THERM# <28>
Check SW:
Cinfigure to output or Internal PU/PD

MEM_1V5

G27
Y2

SB820 A12(SA00003IW10)
SB820 A13(SA00003IW10)

AD11

AD16

AH28
AG28
AF26

SB820M_FCBGA605

@
Y4
R368
25MHZ_20PF_7A25000012 10M_0402_5%
1
2
C589
27P_0402_50V8J

SATA_CALRP
SATA_CALRN

J5
E2
K4
K9
G2

SATA_X1
1

1
2
C588
27P_0402_50V8J

AB14
AA14

2 10K_0402_5%
SATA_X1

FC_CLK
FC_FBCLKOUT
FC_FBCLKIN

Part 2 of 5

FLASH

SATA_TX0P
SATA_TX0N

SERIAL ATA

AH9
AJ9

HW MONITOR

HDD

SB800

<23> SATA_STX_DRX_P0
<23> SATA_STX_DRX_N0

SPI ROM

SATA_X2

MEM_1V5 is for gating the


glitch on PCI_AD24
+3VS

C685
2

Y
A

1 @
R423

PCI_AD24
1 : VDDR=1.05V
0 : VDDR=0.9V

U22

<18,22> PCI_AD24

0.1U_0402_16V4Z

@
1
2 MEM_1V5
R890
10K_0402_5%
1
2
R422
0_0402_5%

For Pre-MP 0702

1
R424

2
33_0402_5%

VDDR_SW <39>
2

NC7SZ08P5X_NL_SC70-5

2
0_0402_5%

C686
150P_0402_50V8J

For VDDR Voltage Switch, AMD suggest


4

2010/04/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/10/12

Deciphered Date

Title

SB820 SATA/IDE/SPI

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

PEW/76/86/96 LA-6552P
Sheet

Thursday, July 22, 2010


E

20

of

45

Rev
B

U20E

+1.1VS_VDDC

510mA

1
R369

U20C

71mA

AF22
AE25
AF24
AC22

2
0_0402_5%

VDDIO_18_FC_1
VDDIO_18_FC_2
VDDIO_18_FC_3
VDDIO_18_FC_4

POWER
43mA

AE28

+VDDPL_3V_PCIE
+1.1VS_PCIE
L70
2
1
FBMA-L11-201209-221LMA30T_0805

+1.1VS

C604
C605
C606
C607

1
1
1
1

2
2
2
2

600mA

22U_0805_6.3V6M
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

+VDDPL_3V_SATA

+1.1VS

1
1
1
1
1

2
2
2
2
2

VDDAN_11_PCIE_1
VDDAN_11_PCIE_2
VDDAN_11_PCIE_3
VDDAN_11_PCIE_4
VDDAN_11_PCIE_5
VDDAN_11_PCIE_6
VDDAN_11_PCIE_7
VDDAN_11_PCIE_8

22U_0805_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

AD14

VDDPL_33_SATA

AJ20
AF18
AH20
AG19
AE18
AD18
AE16

VDDAN_11_SATA_1
VDDAN_11_SATA_4
VDDAN_11_SATA_2
VDDAN_11_SATA_3
VDDAN_11_SATA_5
VDDAN_11_SATA_6
VDDAN_11_SATA_7

+1.1V_USB
L74
2
1
FBMA-L11-160808-221LMT 0603

+1.1VALW

CORE S0

658mA

A18
A19
A20
B18
B19
B20
C18
C20
D18
D19
D20
E19

10U_0805_10V4Z
10U_0805_10V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z

C625 2
C626 2

VDDAN_33_USB_S_1
VDDAN_33_USB_S_2
VDDAN_33_USB_S_3
VDDAN_33_USB_S_4
VDDAN_33_USB_S_5
VDDAN_33_USB_S_6
VDDAN_33_USB_S_7
VDDAN_33_USB_S_8
VDDAN_33_USB_S_9
VDDAN_33_USB_S_10
VDDAN_33_USB_S_11
VDDAN_33_USB_S_12

200mA

C11
D11

1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
R372
1
R373

M10

C590

1
1
1
1

C596
C594
C597
C598

L69
2
1
FBMA-L11-201209-221LMA30T_0805

22U_0805_6.3V6M

V1

L7
L9

1
R374

M6
P8

VDDAN_11_USB_S_1
VDDAN_11_USB_S_2

VDDIO_33_S_1
VDDIO_33_S_2
VDDIO_33_S_3
VDDIO_33_S_4
VDDIO_33_S_5
VDDIO_33_S_6
VDDIO_33_S_7
VDDIO_33_S_8

A21
D21
B21
K10
L10
J9
T6
T8

VDDCR_11_S_1
VDDCR_11_S_2

F26
G26

VDDIO_AZ_S
VDDCR_11_USB_S_1
VDDCR_11_USB_S_2

M8
A11
B11

VDDPL_33_SYS

M21

VDDPL_11_SYS_S

L22

VDDPL_33_USB_S

F19

VDDAN_33_HWM_S
VDDXL_33_S

1 2.2U_0603_6.3V4Z
1 0.1U_0402_16V4Z

+1.1VS_CKVDD

400mA

2
2
2
2

1
2
2
2
2

+1.1VS

C595

External Clock, connect to +1.1VS


directly, no need thick trace

1
1
1
1

C600
C601
C602
C603

check can be removed?

2
0_0402_5%
2
0_0402_5%

+3VALW
@
U85

+VDDCR_USB
VDDCR_11_GBE_S_1
VDDCR_11_GBE_S_2

CORE S5

2
2
2
2
2

1
R375

@
L107
5
2
1
FBMA-L11-160808-221LMT 0603

2
0_0402_5%

2
0_0402_5%

VIN

1U_0402_6.3V6K
2
1
2

VOUT
GND
FB

C989
@

EN

APL5317

USB I/O

1
1
1
1
1

10U_0805_10V4Z

+1.1VS

+3VALW

PLL

+AVDD_USB
L72
2
1
FBMA-L11-201209-221LMA30T_0805
C617
C618
C619
C620
C621

K28
K29
J28
K26
J21
J20
K21
J22

VDDIO_GBE_S_1
VDDIO_GBE_S_2

check 220ohm bead

+3VALW

VDDAN_11_CLK_1
VDDAN_11_CLK_2
VDDAN_11_CLK_3
VDDAN_11_CLK_4
VDDAN_11_CLK_5
VDDAN_11_CLK_6
VDDAN_11_CLK_7
VDDAN_11_CLK_8

2
0_0805_5%

1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

93mA

+1.1VS_SATA
L71
2
1
FBMA-L11-201209-221LMA30T_0805
567mA
C610
C611
C612
C613
C614

N13
R15
N17
U13
U17
V12
V18
W12
W18

VDDIO_33_GBE_S

VDDPL_33_PCIE

U26
V22
V26
V27
V28
V29
W22
W26

VDDCR_11_1
VDDCR_11_2
VDDCR_11_3
VDDCR_11_4
VDDCR_11_5
VDDCR_11_6
VDDCR_11_7
VDDCR_11_8
VDDCR_11_9

VDDRF_GBE_S

3.3V_S5 I/O

1
R371

PCI/GPIO I/O

22U_0805_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

CLKGEN I/O

2
2
2

FLASH I/O

1
1
1

GBE LAN

VDDIO_33_PCIGP_1
VDDIO_33_PCIGP_2
VDDIO_33_PCIGP_3
VDDIO_33_PCIGP_4
VDDIO_33_PCIGP_5
VDDIO_33_PCIGP_6
VDDIO_33_PCIGP_7
VDDIO_33_PCIGP_8
VDDIO_33_PCIGP_9
VDDIO_33_PCIGP_10
VDDIO_33_PCIGP_11
VDDIO_33_PCIGP_12

SERIAL ATA

C591
C592
C593
C599

Part 3 of 5

SB800

AH1
V6
Y19
AE5
AC21
AA2
AB4
AC8
AA7
AA9
AF7
AA19

PCI EXPRESS

131mA
+3VS

D6
L20

32mA
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z

1
1

2
2

C608
C609
+1.1VALW

C615 2
C616 2

113mA

1 1U_0402_6.3V4Z
1 1U_0402_6.3V4Z

TBD
+VDDIO_AZ

2
1
L73 FBMA-L11-160808-221LMT 0603
C622
1
2 10U_0805_10V4Z

47mA
62mA
17mA

+VDDPL_3V

C623
C624

+VDDPL_11V

2
2

1 0.1U_0402_16V4Z
1 0.1U_0402_16V4Z

+VDDPL_3V_USB

5mA
197mA

+3V_HWM

A9
B10
K11
B9
D10
D12
D14
D17
E9
F9
F12
F14
F16
C9
G11
F18
D9
H12
H14
H16
H18
J11
J19
K12
K14
K16
K18
H19

SB800
VSSIO_SATA_1
VSSIO_SATA_2
VSSIO_SATA_3
VSSIO_SATA_4
VSSIO_SATA_5
VSSIO_SATA_6
VSSIO_SATA_7
VSSIO_SATA_8
VSSIO_SATA_9
VSSIO_SATA_10
VSSIO_SATA_11
VSSIO_SATA_12
VSSIO_SATA_13
VSSIO_SATA_14
VSSIO_SATA_15
VSSIO_SATA_16
VSSIO_SATA_17
VSSIO_SATA_18
VSSIO_SATA_19
VSSIO_USB_1
VSSIO_USB_2
VSSIO_USB_3
VSSIO_USB_4
VSSIO_USB_5
VSSIO_USB_6
VSSIO_USB_7
VSSIO_USB_8
VSSIO_USB_9
VSSIO_USB_10
VSSIO_USB_11
VSSIO_USB_12
VSSIO_USB_13
VSSIO_USB_14
VSSIO_USB_15
VSSIO_USB_16
VSSIO_USB_17
VSSIO_USB_18
VSSIO_USB_19
VSSIO_USB_20
VSSIO_USB_21
VSSIO_USB_22
VSSIO_USB_23
VSSIO_USB_24
VSSIO_USB_25
VSSIO_USB_26
VSSIO_USB_27
VSSIO_USB_28

Y4

EFUSE

D8

VSSAN_HWM

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52

M19

VSSXL

P21
P20
M22
M24
M26
P22
P24
P26
T20
T22
T24
V20
J23

VSSIO_PCIECLK_1
VSSIO_PCIECLK_2
VSSIO_PCIECLK_3
VSSIO_PCIECLK_4
VSSIO_PCIECLK_5
VSSIO_PCIECLK_6
VSSIO_PCIECLK_7
VSSIO_PCIECLK_8
VSSIO_PCIECLK_9
VSSIO_PCIECLK_10
VSSIO_PCIECLK_11
VSSIO_PCIECLK_12
VSSIO_PCIECLK_13

VSSPL_SYS

AJ2
A28
A2
E5
D23
E25
E6
F24
N15
R13
R17
T10
P10
V11
U15
M18
V19
M11
L12
L18
J7
P3
V4
AD6
AD4
AB7
AC9
V8
W9
W10
AJ28
B29
U4
Y18
Y10
Y12
Y11
AA11
AA12
G4
J4
G8
G9
M12
AF25
H7
AH29
V10
P6
N4
L4
L8

M20

+1.1VALW
+VDDCR_USB

197mA

Y14
Y16
AB16
AC14
AE12
AE14
AF9
AF11
AF13
AF16
AG8
AH7
AH11
AH13
AH16
AJ7
AJ11
AJ13
AJ16

GROUND

+3VALW
+VDDLX_3V
2
1
L75 FBMA-L11-160808-221LMT 0603
C627 1
2 2.2U_0603_6.3V4Z

SB820M_FCBGA605

VSSIO_PCIECLK_14
VSSIO_PCIECLK_15
VSSIO_PCIECLK_16
VSSIO_PCIECLK_17
VSSIO_PCIECLK_18
VSSIO_PCIECLK_19
VSSIO_PCIECLK_20
VSSIO_PCIECLK_21
VSSIO_PCIECLK_22
VSSIO_PCIECLK_23
VSSIO_PCIECLK_24
VSSIO_PCIECLK_25
VSSIO_PCIECLK_26
VSSIO_PCIECLK_27

H23
H26
AA21
AA23
AB23
AD23
AA26
AC26
Y20
W21
W20
AE26
L21
K20

Part 5 of 5
SB820M_FCBGA605

+VDDPL_11V
+VDDPL_3V_PCIE

+3VS

+VDDPL_3V

+VDDPL_3V_USB

L76
2
1
FBMA-L11-160808-221LMT 0603

L80

2
1
FBMA-L11-160808-221LMT 0603

+1.1VALW

0.1U_0402_16V4Z

2
1
FBMA-L11-160808-221LMT 0603

1
C634
2.2U_0603_6.3V4Z

+VDDPL_3V_SATA

+3VS

+3V_HWM

+3VALW

R414 0_0603_5%
2
1

1
C628

+3VALW

+3VS

L79

C635
2.2U_0603_6.3V4Z

+VDDIO_AZ

C630
C629
2.2U_0603_6.3V4Z

0.1U_0402_16V4Z

AMD

L78
2
1
FBMA-L11-160808-221LMT 0603
C632

C631
2.2U_0603_6.3V4Z

0.1U_0402_16V4Z

C633
2.2U_0603_6.3V4Z

+3VALW

L81
4

2
1
FBMA-L11-160808-221LMT 0603
C636
0.1U_0402_16V4Z

1
R376

0_0402_5%

1
C637
2.2U_0603_6.3V4Z

C638
2.2U_0603_6.3V4Z

For 3V AZ device

2010/04/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/10/12

Deciphered Date

Title

SB820 power/GND

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

PEW/76/86/96 LA-6552P
Sheet

Thursday, July 22, 2010


E

21

of

45

Rev
B

REQUIRED STRAPS

USE
DEBUG
STRAP

Performance
MODE

PULL
LOW

FORCE PCIE
GEN1

DEFAULT

IGNORE
DEBUG
STRAP

Inter CLK
Gen Mode

+3VS

+3VS

R380
10K_0402_5%
2
1

+3VS

R379
10K_0402_5%
2
1

+3VS

R378
10K_0402_5%
2
1

DEFAULT

GPIO200

CLOCKGEN
ENABLE

GPIO199

H,H = Reserved

EC
DISABLE

L,H = LPC ROM (Default L,NC)

CLOCKGEN
DISABLE

L,L = FWH ROM

Disable

DEFAULT

LCP_CLK1

EC
ENABLE

H,L = SPI ROM

Inter CLK
Gen Mode

DEFAULT

LPC_CLK0

Enable

DEFAULT

R377
10K_0402_5%
2
1

+VDDIO_AZ

WATCHDOG
TIMER
DISABLE

PCI_CLK4

DEFAULT

+3VALW

DEFAULT

+3VALW

+3VALW

+3VALW

R385
2.2K_0402_5%
2
1

PCI_CLK3

R384
10K_0402_5%
2
1

PCI_CLK2

LOW POWER ALLOW PCIE WATCHDOG


MODE
GEN2
TIMER
ENABLE

R383
10K_0402_5%
2
1

PCI_CLK1

Check Internal PU/PD

R382
10K_0402_5%
2
1

AZ_SDOUT
PULL
HIGH

R381
10K_0402_5%
2
1

<19> HDA_SDOUT
<18> PCI_CLK1
<18> PCI_CLK2
<18> PCI_CLK3
<18> PCI_CLK4
<18,28> LPC_CLK0_EC
<18> LPC_CLK1
<19> GPIO200
<19> GPIO199

USE PCI
PLL

DISABLE ILA
AUTORUN

USE FC PLL

USE DEFAULT
PCIE STRAPS

DISABLE PCI
MEM BOOT

DEFAULT

PULL
LOW

BYPASS
PCI PLL

Check AD29,AD28 strap function

PCI_AD23

DEFAULT

DEFAULT

DEFAULT

DEFAULT

ENABLE ILA
AUTORUN

BYPASS
FC PLL

USE EEPROM
PCIE STRAPS

ENABLE PCI
MEM BOOT

<18>
<18>
<18>
<18>
<18>
<18,20>
<18>

PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23

check default

R401
2.2K_0402_5%
2
1

PCI_AD24

R400
2.2K_0402_5%
2
1

PCI_AD25

R399
2.2K_0402_5%
2
1

PCI_AD26

R398
2.2K_0402_5%
2
1

PULL
HIGH

PCI_AD27

+3VS

R397
2.2K_0402_5%
2
1

R396
10K_0402_5%
2
1

R395
10K_0402_5%
2
1

DEBUG STRAPS

R394
2.2K_0402_5%
2
1

+3VS

SB800 HAS 15K INTERNAL PU FOR PCI_AD[27:23]

R393
2.2K_0402_5%
2
1

R392
10K_0402_5%
2
1

R391
10K_0402_5%
2
1

R390
10K_0402_5%
2
1

R389
10K_0402_5%
2
1

R388
10K_0402_5%
2
1

R387
10K_0402_5%
2
1

R386
10K_0402_5%
2
1

2010/04/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/10/12

Deciphered Date

Title

SB820 STRAPS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

PEW/76/86/96 LA-6552P
Sheet

Thursday, July 22, 2010


E

22

of

45

Rev
B

SATA HDD Conn.

JHDD1

<20> SATA_STX_DRX_P0
<20> SATA_STX_DRX_N0
<20> SATA_DTX_C_SRX_N0
<20> SATA_DTX_C_SRX_P0

C656 1
C658 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_STX_C_DRX_P0
SATA_STX_C_DRX_N0

C657 1
C659 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_DTX_SRX_N0
SATA_DTX_SRX_P0

1
2
3
4
5
6
7

GND
A+
AGND
BB+
GND

+3VS
1

+5VS

R405 1

+3VS
C639
0.1U_0402_16V4Z

+5VS_HDD

2 0_0805_5%
10U_0805_10V4Z
C660

C661

0.1U_0402_16V4Z
1

C662

C663

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

GND
GND

24
23

SANTA_192301-1
CONN@

1U_0402_6.3V4Z

V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12

1000P_0402_50V7K

<NAV70 use>

SATA ODD FFC Conn.


JODD1
<20> SATA_STX_DRX_P1
<20> SATA_STX_DRX_N1

C648 1
C649 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_STX_C_DRX_P1
SATA_STX_C_DRX_N1

<20> SATA_DTX_C_SRX_N1
<20> SATA_DTX_C_SRX_P1

C650 1
C651 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_DTX_SRX_N1
SATA_DTX_SRX_P1

R403 1

2 1K_0402_1%

+5VS

80mils

1
2
3
4
5
6
7
8
9
10
11
12

1
2
3
4
5
6
7
8
9
10
11
12

GND
GND

13
14

ACES_85201-1205N
CONN@

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/04/12

2010/10/12

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

HDD & ODD Connector


Document Number

PEW/76/86/96 LA-6552P

Date:

Thursday, July 22, 2010


G

Sheet

23
H

of

45

Rev
B

+3V_LAN
+3VALW

R800

60mil

0_1206_5%
2

C902

C901
4.7U_0805_10V4Z
U70
+3V_LAN

2
0.1U_0402_16V4Z

+LAN_BIASVDDH

42

VDDC

BIASVDDH

25

6
15
41

VDDC
VDDC
VDDC

XTALVDDH

14

AVDDH

30

AVDDH

36

TRD3_N

37

LAN_MIDI3-

TRD3_P

38

LAN_MIDI3+

TRD2_N

35

LAN_MIDI2-

TRD2_P

34

LAN_MIDI2+

TRD1_N

31

LAN_MIDI1-

TRD1_P

32

LAN_MIDI1+

TRD0_N

29

LAN_MIDI0-

TRD0_P

28

LAN_MIDI0+

LINKLED#

48

SPD100LED#

47

2
0.1U_0402_16V4Z
+LAN_AVDDL

+LAN_GPHYPLLVDDL

24

AVDDL
AVDDL
AVDDL

LAN_MIDI3- <25>
LAN_MIDI3+ <25>
LAN_MIDI2- <25>

SPROM_CLK
(EECLK)

SPROM_DOUT
(EEDATA)

On chip

AT24C02

+3V_LAN

LAN_MIDI2+ <25>

C906 1

GPHY_PLLVDDL

18

PCIE_PLLVDDL

21

PCIE_PLLVDDL

LAN_MIDI1- <25>

LAN_MIDI0- <25>
LAN_MIDI0+ <25>

C9071
C9081

PCIE_PTX_C_IRX_P0
PCIE_PTX_C_IRX_N0
PCIE_ITX_C_PRX_P0
PCIE_ITX_C_PRX_N0

<19,26> SB_PCIE_WAKE#
<28> EC_PME#
+3V_LAN

R806 1
R807 1
R808 1

2 0.1U_0402_16V7K PCIE_PTX_IRX_P0 17
2 0.1U_0402_16V7K PCIE_PTX_IRX_N0 16
22
23
LAN_PME#
4
LAN_RESET# 2
20
@
2 0_0402_5%
19
2 0_0402_5%
2 4.7K_0402_5%

R809 1

<18,26> PLT_RST#

PCIE_TXD_P
PCIE_TXD_N
PCIE_RXD_P
PCIE_RXD_N
WAKE#
REST#
PCIE_REFCLK_P
PCIE_REFCLK_N

SPD1000LED#

46

TRAFFICLED#

45

2
R805
0_0402_5%

U71 @
8
7
6
5

R812
1K_0402_1%
@

LAN_ACTIVITY# <25>

20mil
+LAN_XTALVDDH 1
C909

+3VS

R810 1

2 1K_0402_5%

40

R813 1

2 10K_0402_5%

SPROM_DOUT

EECLK

44

SPROM_CLK

VMAIN_PRSINT

SR_LX
T12 PAD
T13 PAD

LAN_XTALO_R
LAN_XTALI

13

XTALO

12

XTALI

SR_VFB

11

+1.2V_LAN_OUT
1
2
4.7UH_PG031B-4R7MS_1.1A_20%

+1.2V_LAN
C913

0.1U_0402_16V4Z

26

RDAC
SR_VDDP

1.24K_0402_1%

0.1U_0402_16V4Z
2

NC

0.1U_0402_16V4Z

20mil
+LAN_GPHYPLLVDDL
1
2
C919
0.1U_0402_16V4Z

49

BCM57780A0KMLG_QFN48_7X7

L104
1
2
BLM18AG601SN1D_2P

+1.2V_LAN

C916
4.7U_0805_10V4Z

C918

2
2
4.7U_0603_6.3V6K 0.1U_0402_16V4Z

CLKREQ#

0.1U_0402_16V4Z

+LAN_PCIEPLLVDD
1
C915

PAD

<19> LAN_CLKREQ#

C917

20mil

+3V_LAN
1

L102
1
2
BLM18AG601SN1D_2P

C914
10U_0805_10V4Z

10

SR_VDD

0.1U_0402_16V4Z

+LAN_AVDDH
1
1
C911
C912

R814
LAN_RDAC

20mil

LOW_PWR

+3V_LAN

L101
1
2
BLM18AG601SN1D_2P

+LAN_BIASVDDH 1
C910

L103

L100
1
2
BLM18AG601SN1D_2P
0.1U_0402_16V4Z

20mil
43

1
2
3
4

AT24C02_SO8

R811
1K_0402_1%

<18> CLK_PCIE_LAN
<18> CLK_PCIE_LAN#

EEDATA

A0
A1
NC
GND

LAN_LINK# <25>

2 0_0402_5%
MODE

VCC
WP
SCL
SDA

<12>
<12>
<12>
<12>

2
R801
0_0402_5%

R803
1K_0402_1%

SPROM_CLK
SPROM_DOUT

2 0.1U_0402_16V4Z
@

R802
1K_0402_1%
@

LAN_MIDI1+ <25>

+LAN_PCIEPLLVDD

27
33
39

+LAN_AVDDH

2
2
0.1U_0402_16V4Z

+LAN_XTALVDDH

C903

0.1U_0402_16V4Z
1
1
C904
C905

4.7U_0805_10V4Z

C900

+1.2V_LAN

20mil
+LAN_AVDDL
1
C921

LAN_XTALI

0.1U_0402_16V4Z

L105
1
2
BLM18AG601SN1D_2P

+1.2V_LAN

C920
4.7U_0805_10V4Z

L106
1
2
BLM18AG601SN1D_2P

+1.2V_LAN

C922
4.7U_0805_10V4Z

LAN_XTALO_R
R815
200_0402_1%
Y5

C923
33P_0402_50V8K

2 LAN_XTALO

25MHZ_20PF_7A25000012

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

C924
33P_0402_50V8K

2010/04/12

Deciphered Date

2010/10/12

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

BROADCOM 57780
PEW/76/86/96 LA-6552P

Thursday, July 22, 2010

Sheet
D

24

of

45

Rev
B

LAN Connector

BH GS5009-D <SP050006B00>

JRJ45
T25

<24> LAN_ACTIVITY#

<24> LAN_MIDI0+
<24> LAN_MIDI0-

LAN_MIDI0+
LAN_MIDI0-

1
2
3

TCT1
TD1+
TD1-

MCT1
MX1+
MX1-

24
23
22

RJ45_MIDI0+
RJ45_MIDI0-

<24> LAN_MIDI1+
<24> LAN_MIDI1-

LAN_MIDI1+
LAN_MIDI1-

4
5
6

TCT2
TD2+
TD2-

MCT2
MX2+
MX2-

21
20
19

RJ45_MIDI1+
RJ45_MIDI1-

<24> LAN_MIDI2+
<24> LAN_MIDI2-

LAN_MIDI2+
LAN_MIDI2-

7
8
9

TCT3
TD3+
TD3-

MCT3
MX3+
MX3-

18
17
16

RJ45_MIDI2+
RJ45_MIDI2-

<24> LAN_MIDI3+
<24> LAN_MIDI3-

LAN_MIDI3+
LAN_MIDI3-

10
11
12

TCT4
TD4+
TD4-

MCT4
MX4+
MX4-

15
14
13

RJ45_MIDI3+
RJ45_MIDI3-

2
R823
1
C938

+3V_LAN

1
1K_0402_5%
2
220P_0402_50V7K

12

Yellow LED-

11

Yellow LED+

RJ45_MIDI3-

PR4-

RJ45_MIDI3+

PR4+

RJ45_MIDI1-

PR2-

RJ45_MIDI2-

PR3-

RJ45_MIDI2+

PR3+

RJ45_MIDI1+

PR2+

RJ45_MIDI0-

PR1-

RJ45_MIDI0+

0.1U_0402_16V4Z
2
2

R819
75_0402_1%

C931

0.1U_0402_16V4Z
2

R821
75_0402_1%

0.1U_0402_16V4Z

2
R824
1
C942

+3V_LAN

1
1K_0402_5%
2
220P_0402_50V7K

Green LED-

R412
0_0805_5%
@

Green LED+
SANTA_130451-K
CONN@

R822
75_0402_1%
RJ45_GND

RJ45_GND

Place close to TCT pin

2
R820
75_0402_1%

0.1U_0402_16V4Z

C930

C929

C928

PR1+

10

<24> LAN_LINK#

@
0_0805_5%
1

350UH_IH-037-2

R413
2

13
14

SHLD2
SHLD1

LANGND
2

C940
1000P_1206_2KV7K

40mil

1
C941

0.1U_0402_16V4Z

LAN_ACTIVITY#
LAN_LINK#

40mil

C939
4.7U_0805_10V4Z

D40
PJDLC05_SOT23-3
@

LAN_ACTIVITY#

1
C943

2
220P_0402_50V7K

LAN_LINK#

1
C944

2
220P_0402_50V7K
B

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/04/12

Issued Date

Deciphered Date

2010/10/12

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

LAN Magnetic & RJ45


Document Number

PEW/76/86/96 LA-6552P
Thursday, July 22, 2010

Sheet
1

25

of

45

Rev
B

Mini-Express Card for WLAN


+3VS

+1.5VS

C705
4.7U_0805_10V4Z

C706
0.1U_0402_16V4Z

C707
0.1U_0402_16V4Z

C708
4.7U_0805_10V4Z

C709
0.1U_0402_16V4Z

C710
0.1U_0402_16V4Z

JMINI1
R440 1

2 0_0402_5%

<19> MINI1_CLKREQ#
<18> CLK_PCIE_MINI1#
<18> CLK_PCIE_MINI1

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

<12> PCIE_PTX_C_IRX_N1
<12> PCIE_PTX_C_IRX_P1
<12> PCIE_ITX_C_PRX_N1
<12> PCIE_ITX_C_PRX_P1
+3VS

0_0402_5%
R445 1
2

<28> E51TXD_P80DATA
<28> E51RXD_P80CLK

1
3
5
7
9
11
13
15

E51TXD_P80DATA_R
E51RXD_P80CLK

2
4
6
8
10
12
14
16

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

+3VS
+1.5VS

53
54
55
56

WL_OFF#
PLT_RST#
+3V_WLAN

1
R441 1
R442
@
MINI1_SMBCLK
@
1
MINI1_SMBDAT R443
@
1
R444

2
2 0_0603_5%
0_0603_5%
2
0_0603_5%
2
0_0603_5%

WL_OFF# <28>
PLT_RST# <18,24>
+3VS
+3VALW

Normal

Peak

Normal

+3VS

1000

750

+3V

330

250

250 (wake enable)

+1.5VS

500

375

5 (Not wake enable)

SB_SMDAT0 <10,11,19>
SB_SMCLK0 <10,11,19>

USB20_N8 <19>
USB20_P8 <19>

(MINI1_LED#)

WIMAX_LED#
WLAN_LED#_L

+3VS

R835 1

+3VS
ACES_88910-5204
CONN@

WIMAX_LED#
@
1
R836

<NAV70 use>

Auxiliary Power (mA)

Primary Power (mA)

0_0402_5%
2

R848
100K_0402_5%

2
R492
100K_0402_5%

Mini Card Power Rating


Power

G1
G2
G3
G3

1
3
5
7
9
11
13
15

SB_PCIE_WAKE#

<19,24> SB_PCIE_WAKE#

2
10K_0402_5%

WLAN_LED#_L

2
1

MINI1_LED# <28>

(9~16mA)

CHP202UPT_SOT323-3
D44 @
1
2
R837
0_0402_5%

Height : 4mm

Card Reader RTS5138 / RTS5137


(only SD+MMC function)

Card Reader Connector

+3VS_CR

2 0_0805_5%

30mil

1
10mil
100P_0402_50V8J
RREF
2
6.2K_0603_1%
USB20_N6
<19> USB20_N6
USB20_P6
<19> USB20_P6
2
C981
R855 1

1
C983
4.7U_0805_10V4Z

30mil
C984

1
0.1U_0402_16V4Z

+3VS_CR
+CARDPWR
VREG

10mil

C985
1U_0402_6.3V6K
XDDRY_SDWP_MSCLK

REFE

2
3

DM
DP

4
5
6

3V3_IN
CARD_3V3
V18

XD_CD#

8
9
10
11
12

SP1
SP2
SP3
SP4
SP5

GPIO0

17

CLK_IN

24

XD_D7

23

SP14
SP13
SP12
SP11
SP10
SP9
SP8
SP7
SP6

22
21
20
19
18
16
15
14
13

5IN1_LED# <29>

C982 1
@
1
2
2 10P_0402_50V8J
@
R856
10_0402_5%
CLK_SD_48M_R
2
1
CLK_SD_48M <18>
R857
22_0402_5%

JCR1
XDD4_SDD3_MSD1
XDD2_SDCMD

1
2
3
4
5
6

XDD0_SDCLK_MSD2
XDD5_SDD2_MS_D5
XDD4_SDD3_MSD1

+CARDPWR

XDD2_SDCMD

1
R858

XDD0_SDCLK_MSD2
XDWE#_SDCD#

RTS5138-GR_QFN24_4X4

XDCLE_SDD0
XDCE#_SDD1
XDD5_SDD2_MS_D5
XDDRY_SDWP_MSCLK
XDWE#_SDCD#

+SDPWR_MMCPWR

30mil

2
0_0805_5%

30mil

R859
100K_0402_5%

C986
0.1U_0402_16V4Z

C987
0.1U_0402_16V4Z

25

XDCE#_SDD1
XDCLE_SDD0

+SDPWR_MMCPWR
5IN1_LED#

U84
1

D3
CMD
VSS1
VDD
CLK
VSS2

7
8
9
10
11

D0
D1
D2
WP
CD

12
13

GND1
GND2

R854

EPAD

+3VS

C988
0.1U_0402_16V4Z

C987, C988 close to connector

Change to RTS5137 (SA000043500)


4

TAITW_PSDBTC09GLBS1N14N0
CONN@

2010/04/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/10/12

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

MINI CARD / CardReader RTS5137


Document Number

PEW/76/86/96 LA-6552P
Sheet

Thursday, July 22, 2010


E

26

of

45

Rev
B

+3VALW
+USB_VCCA

C713

8
7
6
5

+USB_VCCA
R446
100K_0402_5%

80mil

C711

C712
R447 1

2 10K_0402_5%

USB_OC#0 <19>

GND VOUT
VIN VOUT
VIN VOUT
EN
FLG

U24
1
2
3
4

+USB_VCCA

SVPE, 4.4m, 17mohm


+5VALW

220U_6.3V_M

2
470P_0402_50V7K

RT9715BGS_SO8
C714
0.1U_0402_16V4Z

<33> SYSON#

R448

+3VALW

C715

1
2
3
4

GND VOUT
VIN VOUT
VIN VOUT
EN
FLG

8
7
6
5

80mil

0_0402_5%

R449 @
0_0402_5%
1
2

USB20_N0

R450
100K_0402_5%

USB20_P0

<19> USB20_P0

JUSB1

USB_OC#2 <19>

1
2
3
4
5
6
7
8

USB20_N0_R
USB20_P0_R

WCM2012F2S-900T04_0805

U25

+USB_VCCB

L83
<19> USB20_N0

+5VALW

W=80mils

4.7U_0805_10V4Z
2

1
2
R452
10K_0402_5%

RT9715BGS_SO8
4.7U_0805_10V4Z
2

USB_OC#1 <19>
1

R451

1
2
3
4
GND
GND
GND
GND

<NAL00 use>

SUYIN_020133MB004S580ZL-C
CONN@

0_0402_5%

C716
0.1U_0402_16V4Z

SYSON#
D10
USB20_N0_R

+USB_VCCA

To USB/B Connector

USB20_P0_R

1
PJUSB208_SOT23-6

ESD Change P/N SC300000B00 For DVT


+USB_VCCB

(Port 1,2)
JUSB2

USB20_N2
USB20_P2

USB20_N1 <19>
USB20_P1 <19>
USB20_N2 <19>
USB20_P2 <19>

ACES_85201-1205N
CONN@
3

+3VALW

Bluetooth Conn.

<NAL00 use>

+3VS
3

C718
3

BT@
C719
1U_0402_6.3V4Z

C720

AO3413_SOT23-3

W=40mils

BT@
0.1U_0402_16V4Z

+BT_VCC
C721

+BT_VCC

BT@
Q24

BT@ 2
1
R453
10K_0402_5%

<28> BT_ON#

BT@
0.1U_0402_16V4Z

BT@

C722

BT@

GND 8
7
6
5
4
3
2
GND 1

BT@
R454
300_0603_5%

4.7U_0805_10V4Z
2
0.1U_0402_16V4Z
2

JBT1
10

USB20_N1
USB20_P1

8
7
6
5
4
3
2
1

USB20_P7 <19>
USB20_N7 <19>

GND
GND

1
2
3
4
5
6
7
8
9
10
11
12

13
14

1
2
3
4
5
6
7
8
9
10
11
12

BT@
Q25
2N7002_SOT23

2
G

ACES_87213-0800G
CONN@
4

<NAL00 use>

2010/04/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/10/12

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

BlueTooth / Int USB x2 /eSATA


Document Number

PEW/76/86/96 LA-6552P
Sheet

Thursday, July 22, 2010


E

27

of

45

Rev
B

+3VALW

C726
KSO[0..17] <29>

KSI[0..7]

2
2
0.1U_0402_16V4Z

2
2
0.1U_0402_16V4Z

C728
1000P_0402_50V7K
1
1

C729
1000P_0402_50V7K

KSI[0..7] <29>

Place on MiniCard door

JP7

1
2
3
4

1
2
3
4

E51RXD_P80CLK
E51TXD_P80DATA

ACES_85205-0400
@

65W/90W#

R458
VR_ON

R459

<18> CLKRUN#

+5VS

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

TP_CLK
2
4.7K_0402_5%
TP_DATA
2
4.7K_0402_5%

1
R465
1
R466

R489
4.7K_0402_5%

+3VALW +3VS

For PVT 0602


@
R852
0_0402_5%

R851
0_0402_5%

EC_SMB_CK2
2
2.2K_0402_5%
EC_SMB_DA2
2
2.2K_0402_5%

1
R467
1
R468
+3VALW

1
R471
1
R472
1
R473
1
R474
2
R475
1
R476
2
R497

EC_SMB_CK1
2
2.2K_0402_5%
EC_SMB_DA1
2
2.2K_0402_5%
KSO1
2
47K_0402_5%
KSO2
2
47K_0402_5%
LID_SW#
1
100K_0402_5%
EC_PME#
2
10K_0402_5%
PBTN_OUT#
1
100K_0402_5%

<35>
<35>
<8>
<8>

<19> PM_SLP_S3#
<19> PM_SLP_S5#
<19> EC_SMI#
<15> LOCAL_DIM
<26> MINI1_LED#

For LED INV_PWM freq to 1K


ENBKL
1
100K_0402_5%
LOCAL_DIM
1
100K_0402_5%
COLOY_ENG_EN
1
100K_0402_5%

2
R488
2
R844
2
R845

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

<15> COLOY_ENG_EN
<15> EC_INVT_PWM
<32> FAN_SPEED1
<27> BT_ON#
<32> ON/OFF
<29> PWR_SUSP_LED
<29> WLAN_LED#

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

77
78
79
80

PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
LOCAL_DIM
MINI1_LED#

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

COLOY_ENG_EN
EC_INVT_PWM
FAN_SPEED1
BT_ON#
E51TXD_P80DATA
E51RXD_P80CLK
ON/OFF
PWR_SUSP_LED
WLAN_LED#

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

EC_CRY1
EC_CRY2

2
0_0402_5%

122
123

DAC_BRIG
EN_DFAN1
IREF
CALIBRATE#

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F

83
84
85
86
87
88

EC_MUTE#

PS2 Interface

97
98
99
109

3S/4S#
65W/90W#
VLDT_EN
LID_SW#

SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0

SPI Flash ROM

X1

C740
15P_0402_50V8J

Project_ID : 0-> NEW75/85/95


1-> PEW76/86/96
2-> PEW56(BA51)

100K_0402_5%
AD_PID0

TP_CLK
TP_DATA

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

3S/4S# <37>
65W/90W# <37>
VLDT_EN <33,39>
LID_SW# <29>

119
120
126
128

PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

110
112
114
115
116
117
118

VGATE
ENBKL
EAPD
EC_THERM#
SUSP#
PBTN_OUT#
EC_PME#

V18R

124

69

11
24
35
94
113

20mil
ECAGND 2

L85

BLM18AG601SN1D_2P

Analog Board ID definition


+3VALW

10_0402_5%

EC_SPICLK <29>

FSTCHG <37>
BATT_BLUE_LED# <29>

BATT_BLUE_LED#
BATT_AMB_LED#
PWR_LED
SYSON
VR_ON
ACIN

Ra

Board_ID : 0-> w/ pach code


1-> wo/ pach code

@
R469
100K_0402_5%
AD_BID0

R470

Rb

8.2K_0402_5%

BATT_AMB_LED# <29>
PWR_LED <29>
Reserve
SYSON <33,38>
VR_ON <39,42>
ACIN <33,37>

C735
0.1U_0402_16V4Z

for EMI, close to EC


B

+3VS

EC_RSMRST# <19>
EC_LID_OUT# <19>
EC_ON <32,36>
EC_SWI# <19>

EC_REV

2
R838
@
2
R839

BKOFF# <15>
WL_OFF# <26>
VGA_ON <33,41>

KB926QFB1_LQFP128_14X14

0.1U_0402_16V4Z

R419

C783
33P_0402_50V8K
@

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11

XCLK1
XCLK0

For Pre-MP 07/05

EC_SI_SPI_SO <29>
EC_SO_SPI_SI <29>
1
EC_SPICS#/FSEL# <29>

EC_RSMRST#
EC_LID_OUT#
EC_ON
EC_SWI#
EC_PWROK
BKOFF#
WL_OFF#
EC_REV

GPI

C734
C

TP_CLK <29>
TP_DATA <29>

100
101
102
103
104
105
106
107
108

GPIO
SM Bus

SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#

R464

Rb

8.2K_0402_5%

73
74
89
90
91
92
93
95
121
127

OSC

OSC

NC

NC

C739

EC_REV : 1-> D3
1
0-> E0
100K_0402_5%
1
100K_0402_5%

Delay SUSP# 10ms

VGATE <42>
ENBKL <13>
EAPD <30>
EC_THERM# <20>
SUSP# <33>
PBTN_OUT# <19>
EC_PME# <24>

EC_PWROK 1
R254

2
0_0402_5%

SB_PWRGD <8,13,19>

C736
4.7U_0805_10V4Z

KB926 Rev:D3(SA00001J580)
KB926 Rev:E0(SA00001J5A0)

BATT_TEMP

C737
2

100P_0402_50V8J
1

ACIN

C741
2

100P_0402_50V8J
1

<BOM Structure>

Compal Electronics, Inc.

Compal Secret Data

Security Classification

32.768KHZ_12.5PF_Q13MC14610002

2010/04/12

Issued Date

15P_0402_50V8J

R889
100K_0402_5%
@

2
1

2
A

For PVT 0602

EC_CRY2

Ra

EC_MUTE# <31>

CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59

EC_CRY1

+3VALW

DAC_BRIG <15>
EN_DFAN1 <32>
IREF <37>
CALIBRATE# <37>

SPI Device Interface

GND
GND
GND
GND
GND

Analog Project ID definition

ADP_I <37>

68
70
71
72

AGND

EC_CLK 1
R888

BATT_TEMP <35>

ADP_I
AD_BID0
AD_PID0
MB_SL

DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F

For Low PWR panel use


<18> EC_CLK

ECAGND
2
1
C731 0.01U_0402_16V7K

R463

DA Output
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

ACOFF <37,40>

BATT_TEMP

EC_SCI#

<19> EC_SCI#
1
2
@
R99
0_0402_5%

PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

ACOFF

2
1
R462
47K_0402_5%
2
1
C733
0.1U_0402_16V4Z

+3VALW

AD

BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43

63
64
65
66
75
76

BEEP# <30>

<13,14,18> A_RST#

12
13
37
20
38

PWM Output

BEEP#

LPC_CLK0_EC

<18,22> LPC_CLK0_EC

21
23
26
27

1
33_0402_5%

INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13

2
R461

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC

R460

1
2
3
4
5
7
8
10

1
100K_0402_5%
1
100K_0402_5%
2
4.7K_0402_5%

C732
@ 22P_0402_50V8J
2
1

<19> EC_GA20
<19> EC_KBRST#
<18> SERIRQ
<18> LPC_FRAME#
<18> LPC_AD3
<18> LPC_AD2
<18> LPC_AD1
<18> LPC_AD0

+3VALW

4.7K_0402_5%

3S/4S#
EC_GA20
EC_KBRST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

E51RXD_P80CLK <26>
E51TXD_P80DATA <26>

R491

AVCC

VCC
VCC
VCC
VCC
VCC
VCC

U26

0.1U_0402_16V4Z

67

9
22
33
96
111
125

MB_SL

+3VALW
R109
0_0402_5%
@

C730
ECAGND

KSO[0..17]

C727

1
2+EC_VCCA
BLM18AG601SN1D_2P
1

0.1U_0402_16V4Z
1
2

0.1U_0402_16V4Z
1 C725
1

C724

For EC Tools

+3VS
L84

Deciphered Date

2010/10/12

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

EC ENE KB926
Document Number

PEW/76/86/96 LA-6552P
Thursday, July 22, 2010

Sheet
1

28

of

45

Rev
B

To TP/B Conn.

+5VS

JTP1
2 0.1U_0402_16V4Z

+SPI_VCC
U27
1
3
7
4

CS#
WP#
HOLD#
GND

VCC
SCLK
SI
SO

8
6
5
2

EC_SPICLK_R

R481 1

2 0_0402_5%
EC_SO_SPI_SI <28>
EC_SI_SPI_SO <28>

+5VS

TP_CLK <28>
TP_DATA <28>

LEFT_BTN#
RIGHT_BTN#

C745
0.1U_0402_16V4Z

ACES_85201-0605N
CONN@

EC_SPICLK <28>

RIGHT_BTN#

MX25L1605DM2I-12G SOP 8P
SA00002TO00
LEFT_BTN#

SW1
SMT1-05-A_4P
3
1

RIGHT_BTN#

TP_CLK

LEFT_BTN#

TP_DATA

D11

5
6

SW2
SMT1-05-A_4P
3
1

EC_SPICS#/FSEL#
2 4.7K_0402_5% SPI_WP#
2 4.7K_0402_5% SPI_HOLD#

R480 1
R482 1

1
2
3
4
5
6

<28> EC_SPICS#/FSEL#
+3VALW

7
8

1
2
3
4
5
6
GND
GND

C742 1

2
0_0603_5%

1
R479

5
6

+3VALW

D13

PJDLC05C_SOT23-3

PJDLC05C_SOT23-3

JLED1

INT_KBD Conn.

C751 1

KSO13

C753 1

KSO12

C755 1

KSI0

C757 1

KSO11

C759 1

KSO10

C761 1

KSI1

C763 1

KSI2

C765 1

KSO9

C767 1

KSI3

C769 1
C771 1

@
@
@
@
@
@
@
@
@
@
@

R486

C748 1
C750 1

100P_0402_50V8J

KSO6

C752 1

100P_0402_50V8J

KSO5

C754 1

100P_0402_50V8J

KSO4

C756 1

100P_0402_50V8J

KSO3

C758 1

100P_0402_50V8J

KSI4

C760 1

100P_0402_50V8J

KSO2

C762 1

100P_0402_50V8J

KSO1

C764 1

100P_0402_50V8J

KSO0

100P_0402_50V8J

KSI5

C768 1

100P_0402_50V8J

KSI6

C770 1

KSI7

C766 1

C772 1

@
@
@
@
@
@
@
@
@
@
@
@
@
@

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

5IN1_LED# <26>

SATA_LED# <20>

NC7SZ08P5X_NL_SC70-5

PWR_LED#

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

5
C747 1

KSO17
KSO7

For PVT 0608 Unpop Cap.

KSO16

100P_0402_50V8J

100P_0402_50V8J

100K_0402_5%
U29
2

MEDIA_LED#

Pop R486 for RTS5137

+3VS

LED1
HT-191NB5_BLUE
DMN66D0LDW-7_SOT363-6
Q26A

<28> PWR_LED
R487
100K_0402_5%

+3VS

1
R477

2
2
750_0402_1%

+3VALW

1
R478

2
2
3.01K_0402_1%

+3VALW

1
R499

2
2
750_0402_1%

+3VALW

1
R498

2
2
3.3K_0402_5%

PWR_LED#

LED2
HT-191UD5_AMBER

PWR_SUSP_LED#

LED3
HT-191NB5_BLUE
PWR_SUSP_LED#

R490
100K_0402_5%

100P_0402_50V8J

2010/04/12

BATT_BLUE_LED#

BATT_BLUE_LED# <28>

BATT_AMB_LED#

BATT_AMB_LED# <28>

For PEW76/86/96 LED light,


R477, R499 change as 750 ohm
R478 change as 3.01k ohm
R498 change as 3.3k ohm

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

LED4
HT-191UD5_AMBER

DMN66D0LDW-7_SOT363-6
Q26B

<28> PWR_SUSP_LED

KSO8

+3VS

KSO14

ON/OFFBTN# <32>

KSO[0..17] <28>

C749 1

+3VS

KSO15

PWR_LED#
ON/OFFBTN#

+3VALW
LID_SW# <28>
WLAN_LED# <28>

ACES_85201-08051
CONN@

KSI[0..7] <28>

KSO[0..17]

ACES_88747-2601
CONN@

KSI[0..7]

LID_SW#
WLAN_LED#
MEDIA_LED#

KSO0
G2
KSO1
G1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

28
27

26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

1
2
3
4
5
6
7
8
9
10

JKB1
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

1
2
3
4
5
6
7
8
GND
GND

Deciphered Date

2010/10/12

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

BIOS, I/O Port & K/B Connector


Document Number

PEW/76/86/96 LA-6552P
Thursday, July 22, 2010

Sheet

29

of

45

Rev
B

+3VS

1
R784

+VDDA

2
0_0805_5%

+5VAMP

FBMA-L11-201209-221LMA30T_0805
MONO_IN

1
R786

2
1

HD Audio Codec

C
2

2.4K_0402_1%
Q72

2
B

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C936
1
1U_0402_6.3V4Z

22U_0805_6.3V6M

C952 1
1U_0402_6.3V4Z

<28> BEEP#

R787

FBMA-L11-201209-221LMA30T_0805
L88 1
2

C947

CH751H-40PT_SOD323-2
1

U81

60mil

2
C899

R789
10K_0402_5%

C678

D38

L87

+5VS

R783
20K_0402_1%

IN

GND

SHDN

40mil
OUT

BYP

4.75V

+VDDA

1
2
C949
0.01U_0402_25V7K

@ G9191-475T1U_SOT23-5

(output = 300 mA)

560_0402_5%

2SC2411KT146_SOT23-3

<19> SB_SPKR

R788

560_0402_5%

C946 1
1U_0402_6.3V4Z

D37
CH751H-40PT_SOD323-2
L82
BLM18AG601SN1D_2P
1
2

1
+AVDD_HDA

C794
INT_MIC

2
R523

4.7U_0805_10V4Z
MIC2_C_L
2

1INT_MIC_2
1K_0402_1%
C797

+3VS

MIC2_VREFO

C926
10U_0805_10V4Z

R585
2.2K_0402_5%
2

C945

MIC2_C_R
2
4.7U_0805_10V4Z

35

AMP_LEFT

LINE2_R

LOUT_R

36

AMP_RIGHT

MIC2_L

LOUT2_L

39

MIC2_R

LOUT2_R

41

LINE1_L

SPDIFO2

45

24

LINE1_R

DMIC_CLK1/2

46

18

LINE1_VREFO

NC

43

20

LINE2_VREFO

DMIC_CLK3/4

19

MIC2_VREFO

LINE2_L

15
16
17

AMP_LEFT <31>

DMIC_CLK

1
220P_0402_50V7K

DMIC_CLK <15>

PCBEEP_IN

11

RESET#

10

<19> HDA_SYNC_AUDIO

<19> HDA_SDOUT_AUDIO
DMIC_DATA

<15> DMIC_DATA
<31> MIC_PLUG#
<31> HP_PLUG#

R794 2
R795 2

1 20K_0402_1%
1 5.11K_0402_1%
1
R796

<28> EAPD

SENSE_A
SENSE_B
2
0_0402_5%

MONO_OUT

37

CBP

29

CPVEE

31

MIC1_VREFO

28

HPOUT_R

32

SYNC
SDATA_OUT

2
3
13
34

GPIO0/DMIC_DATA1/2
GPIO1/DMIC_DATA3/4
SENSE A
SENSE B

47

EAPD

48
4
7

SPDIFO1

CBN

30

VREF

27

JDREF

40

HPOUT_L

33

AVSS1
AVSS2

26
42

DVSS1
DVSS2

1
R793

C951

2
33_0402_5%

SENSE A
4

SENSE B

Codec Signals

HP_RIGHT

CODEC_VREF

HP_RIGHT

C954
2.2U_0805_10V6K

39.2K

PORT-A (PIN 39, 41)

LOUT2

PORT-B (PIN 21, 22)

MIC1

10K

PORT-C (PIN 23, 24)

LINE1

5.1K

PORT-D (PIN 35, 36)

LOUT1

39.2K

PORT-E (PIN 14, 15)

LINE2

20K

PORT-F (PIN 16, 17)

MIC2

PORT-I (PIN 32, 33)

HP

HP_LEFT <31>

10mil
1

HP_LEFT

J4

J1
1

AGND

JUMP_43X39 @
J6
1 1
2 2

JUMP_43X39

GNDA

Title

HD Audio Codec ALC272X


Document Number

PEW/76/86/96 LA-6552P

Date:

GNDA

Compal Electronics, Inc.


2010/10/12

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

GND

Compal Secret Data


2010/04/12

JUMP_43X39 @
J3
1
2 2

GND

Issued Date

JUMP_43X39 @
J5
1 1
2 2

JUMP_43X39

Security Classification

JUMP_43X39 @
J2
1 1
2 2

10K
5.1K

HP_RIGHT <31>

HP_LEFT

Function

20K

D27 @
PJDLC05C_SOT23-3

2
MIC1_VREFO

ALC272X
Impedance

G1
G2

ACES_88266-02001
CONN@

2.2U_0805_10V6K
2

10mil

ALC272-VA2-GR_LQFP48_7X7

Sense Pin

3
4

<19>

HDA_SDIN0 <19>

Change to ALC272X
DGND

C980
2

1
2

12

SDATA_IN

C937

MIC1_R

0.1U_0402_16V4Z

<19> HDA_RST_AUDIO#

MIC1_L

22

10U_0805_10V4Z

C932

MIC1_C_R
2
4.7U_0805_10V4Z
MONO_IN

C979
2

JMIC2
1
2

For EMI

HDA_BITCLK_AUDIO

C927

BITCLK

2 C948
22P_0402_50V8J

2
1
0_0402_5%

MIC1_R

21

1
R792

R797

<31> MIC1_R

C934 1

44
6

20K_0402_1%

<31> MIC1_L

MIC1_L

4.7U_0805_10V4Z
MIC1_C_L
2

0_0603_5% R849
1
2
1
2
0_0603_5% R850
1
220P_0402_50V7K

INT_MIC

15mil

MIC2_VREFO

C808
220P_0402_50V7K

AMP_RIGHT <31>

23

LOUT1_L

14

Close to Conn

INT_MIC

U82

DVDD

2
0.1U_0402_16V4Z

DVDD_IO

C953

0.1U_0402_16V4Z

38

25

C950
10U_0805_10V4Z

AVDD1

1
2
BLM18AG601SN1D_2P

+VDDA

40mil

AVDD2

0.1U_0402_16V4Z
1
1
C935

C933

L86

+3VS_DVDD

0.1U_0402_16V4Z

10mil

Thursday, July 22, 2010


G

Sheet

30
H

of

45

Rev
B

GAIN0 GAIN1 AV(inv)


0
6dB
0
1
10dB
0
1
0
15.6dB
1
1
21.6dB

Ri
90k
70k
45k
25k

+5VAMP
0.1U_0402_16V4Z

1
C959
10U_0805_10V4Z

Int. Speaker Conn.

1
C960

2
+5VAMP

16
15
6

C955 1

<30> AMP_LEFT

2
0.47U_0603_10V7K

1
R828

2 0.47U_0603_10V7K

AMP_C_LEFT
2
0_0603_5%

EC_MUTE#

19

18

SPKR+

ROUT-

14

SPKR-

LOUT+

SPKL+

LOUT-

SPKL-

@ R825
100K_0402_5%

G1
G2

Left

ACES_88266-02001
CONN@

R826
100K_0402_5%

JSPK1
SPKR+
SPKR-

R831 1
R832 1

2 0_0603_5%
2 0_0603_5%

20mil

LIN+

LIN-

3
4

ROUT+

GAIN1
1

2
GAIN1

1
RIN-

1
2

SPK_R+
SPK_R-

1
2

1
2

D41

3
4

G1
G2

PJDLC05C_SOT23-3

Right

ACES_88266-02001
CONN@

C971

AMP_C_RIGHT 17
2
0_0603_5%

GAIN0

GAIN0

1
2

1
R830

PJDLC05C_SOT23-3

2
0.47U_0603_10V7K

RIN+

D39

C957

SPK_L+
SPK_L-

1
<30> AMP_RIGHT

2 0.47U_0603_10V7K

2 0_0603_5%
2 0_0603_5%

@ R829
100K_0402_5%

C958 1

R834 1
R833 1

20mil

R827
100K_0402_5%

VDD
PVDD1
PVDD2

U83

JSPK2
SPKL+
SPKL-

10 dB

12
10

SHUTDOWN

Keep 10 mil width


2

GND5
GND1
GND2
GND3
GND4

<28> EC_MUTE#

NC
BYPASS

C956
0.47U_0603_10V7K

21
20
13
11
1

TPA6017A2_TSSOP20

C779
330P_0402_50V7K

<30> HP_LEFT

R686 1

2 56.2_0603_1%

HPOUT_L_1

<30> HP_RIGHT

R685 1

2 56.2_0603_1%

HPOUT_R_1

1
L94
1
L93

C774

Headphone Out

330P_0402_50V7K
1

JHP1
1
2

HPOUT_L_2
2
FBMA-L11-160808-700LMT_2P
HPOUT_R_2
2
FBMA-L11-160808-700LMT_2P

3
4

<30> HP_PLUG#

HP_PLUG#

6
SINGA_2SJ-0960-C01
CONN@

MIC_PLUG#

<NAL00 use>

1 1
2

MIC1_R_R
1

C780
220P_0402_50V7K

1
2

MIC1_L_R

R695 1

JMIC1

4.7K_0402_5%

L89 1
2
FBMA-L11-160808-700LMT_2P
L90 1
2
FBMA-L11-160808-700LMT_2P

<30> MIC1_R

MIC1_L_1
2
1K_0603_1%
MIC1_R_1
2
1K_0603_1%

MIC JACK

R693
2

R692
4.7K_0402_5%
R694 1

@
D24
PJDLC05C_SOT23-3

D42
CH751H-40PT_SOD323-2
1 1

D43
CH751H-40PT_SOD323-2

<30> MIC1_L

HP_PLUG#
MIC1_VREFO MIC1_VREFO

C781
220P_0402_50V7K

@
D29
<30> MIC_PLUG#

4
MIC_PLUG#

PJDLC05C_SOT23-3
6

SINGA_2SJ-A960-C01
CONN@

<NAL00 use>

2010/04/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/10/12

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Amplifier & Audio Jack


Document Number

PEW/76/86/96 LA-6552P
Sheet

Thursday, July 22, 2010


E

31

of

45

Rev
B

ON/OFF switch

FAN1 Conn

R494

2
@ 10K_0603_5%

R495
100K_0402_5%

Bottom Side

U35
8
7
6
5

C823
10U_0805_10V4Z
1
2

APL5607KI-TRG_SO8
+3VS

ON/OFF <28>

Change to SC600000B00

<28> FAN_SPEED1
1

C825
1000P_0402_50V7K

1
2
3

G1
G2

EC_ON

<28,36> EC_ON

S 2N7002_SOT23

Q27

R496

4
5

2
G

JFAN1
1
2
3

1000P_0402_50V7K
1

10K_0402_5%

CONN@
ACES_85204-03001

+VCC_FAN1

C773

ON/OFFBTN# <29>

R568
10K_0402_5%

40mil

51ON# <34>

DAN202UT106_SC70-3

C824
1000P_0402_50V7K
1
2

1
2

2010/04/12

H23
H_4P2

H17
H_3P0X3P5N

H22
H_4P2

H21
H_4P2

H13
H_3P0N

FD4

FD3

FIDUCIAL_C40M80

FIDUCIAL_C40M80

FIDUCIAL_C40M80

FIDUCIAL_C40M80

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

FD2

H20
H_4P2

H10
H_3P0

FD1

H8
H_3P0

H18
H_3P4

H7
H_3P0

H24
H_3P0

H19
H_3P0

H11
H_3P0

H5
H_3P0

H4
H_3P0

0.01U_0402_25V4Z

ON/OFFBTN#

3
2

C822

@
2

GND
GND
GND
GND

2
0_0402_5% 1

EN
VIN
VOUT
VSET

D12

6
5

1
2
3
4

@ SW3
SMT1-05-A_4P
1
3

@ D26 BAS16_SOT23-3
1
2

D25
1SS355_SOD323-2

+VCC_FAN1
1
R567

2
@ 10K_0603_5%

10U_0805_10V4Z
2

R493

R566
0_0603_5%
@

<28> EN_DFAN1

+3VALW

TOP Side
+5VS

+5VS
C821
1

Power Button

Deciphered Date

2010/10/12

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

FAN & Screw Hole & PBTN


Document Number

PEW/76/86/96 LA-6552P
Thursday, July 22, 2010

Sheet

32

of

45

Rev
B

+5VALW TO +5VS

+5VALW

+1.1VALW TO +1.1VS

+5VS

+1.1VALW

+5VALW

+1.1VS

R570
100K_0402_5%

U36

@
D

ACIN 2
G

<28,37> ACIN

+3VALW

0.1U_0603_25V7K

Q48
@
2N7002_SOT23

1
1
2
3
4

C832

SI4800BDY_SO8
10U_0805_10V4Z

2
10U_0805_10V4Z

2
G
Q34
S
2N7002_SOT23
1

C848
0.22U_0603_16V4Z2

R583
100K_0402_5%

ACIN 2
G

2 VGA_ON#
G
Q32
2N7002_SOT23

VLDT_EN#

<28,39> VLDT_EN
1

C835

Q40
2N7002_SOT23

2
G

R584
10K_0402_5%

0.1U_0603_25V7K

2
1
R503 47K_0402_5%

470_0603_5%

VGA_ON#

+5VALW
R572

1.5VSG_GATE
2
100K_0402_5%

1
R575

+VSB

C833

0.1U_0603_25V7K

C843

10U_0805_10V4Z
2
2
1U_0402_6.3V4Z

S
S
S
G

D
D
D
D

C831

8
7
6
5

R596

Q35
2N7002_SOT23

U37
2 SUSP
G
Q36
2N7002_SOT23
C830

2
G

R580
10K_0402_5%

+1.5VS

+1.5V

SUSP

2
Q38G
2N7002_SOT23

SUSP

<40> SUSP

+1.5V to +1.5VS

R579
470_0603_5%

3VS_GATE

1
200K_0402_5%
1

2
R582

510K_0402_5%

10U_0805_10V4Z
2
2
10U_0805_10V4Z

+VSB

C836
10U_0805_10V4Z
2
2
1U_0402_6.3V4Z

R576
100K_0402_5%

2
C842

SI4800BDY_SO8

C841

1
2
3
4

S
S
S
G

+5VALW

<28> SUSP#

1 1

C840

D
D
D
D

C844

U39
8
7
6
5

Q30
2N7002_SOT23

R573
100K_0402_5%

2 VLDT_EN#
G
Q37
2N7002_SOT23

2
G

VLDT_EN# 2
Q39G
2N7002_SOT23

<28,38> SYSON

R595

510K_0402_5%

0.1U_0603_25V7K

+3VALW TO +3VS
+3VS

1.1VS_GATE

2
47K_0402_5%

1 2

1
R581

+VSB

SYSON#

<27> SYSON#

470_0603_5%

C834
1

2
10U_0805_10V4Z

2 SUSP
G
Q31
2N7002_SOT23

R578

1
SUSP
2
Q33G
2N7002_SOT23

5VS_GATE

2
100K_0402_5%

1
R574

C839
10U_0805_10V4Z
2
2
1U_0402_6.3V4Z

C838

SI4800BDY_SO8

R577
C837
1K_0402_5%

R571
470_0603_5%

10U_0805_10V4Z
2
2
10U_0805_10V4Z

1
2
3
4

S
S
S
G

C829
10U_0805_10V4Z
2
2
1U_0402_6.3V4Z

D
D
D
D

2
C827

SI4800BDY_SO8

+VSB

8
7
6
5

U38

1
2
3
4

S
S
S
G

C828

D
D
D
D

C826

8
7
6
5

Q49
@
2N7002_SOT23

+5VALW

R587
100K_0402_5%

+CPU_VDDR

+NB_CORE

+1.8VS

1
1
+0.75VS

Q42
2N7002_SOT23

2
G

R586
10K_0402_5%

+1.5V
2

2
S

+5VS

1
1

1
S

R605
470_0603_5%

D
VGA_ON#
2
G
Q46
2N7002_SOT23

D
2 VLDT_EN#
G
Q69
2N7002_SOT23

R592
470_0603_5%

D
2 VLDT_EN#
G
Q56
2N7002_SOT23

D
2 SUSP
G
2N7002_SOT23
Q45

R610
470_0603_5%

1
1

R604
470_0603_5%

D
2 SUSP
G
Q44
2N7002_SOT23

R591
470_0603_5%

R590
470_0603_5%

+2.5VS

VGA_ON#

<28,41> VGA_ON

2 SYSON#
G
Q57
2N7002_SOT23

C972

C973

C974

C975

C976

C977

C978

0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
2
2 0.1U_0402_16V4Z
2
2 0.1U_0402_16V4Z
2
2 0.1U_0402_16V4Z

2010/04/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/10/12

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

DC Interface
Document Number

PEW/76/86/96 LA-6552P
Sheet

Thursday, July 22, 2010


E

33

of

45

Rev
B

DC-IN cable: DC301009W00 (Yellow)

VIN

SP02000GC00
ACES_50305-00441-001

PC4
100P_0402_50V8J

1
PC5
100P_0402_50V8J

1
PC3
1000P_0402_50V7K

PJP1

PL1
SMB3025500YA_2P
1
2

DC_IN_S1

1
2
3
4
5
6

1
2
3
4
GND
GND

PC6
1000P_0402_50V7K

PJ1
1

+3VALWP

PJ22
2

+3VALW

+1.8VSP

JUMP_43X118

(3.9A,160mils ,Via NO.= 8)

VIN
2
PD2
RLS4148_LL34-2

<32> 51ON#

+1.1VALW

(7A,280mils ,Via NO.=14)

PJ11
2

+VSB

+0.75VSP

+0.75VS
3

JUMP_43X118

(3A,120mils ,Via NO.=6)

(5A,200mils ,Via NO.= 10)

PJ8

VS

+NB_COREP

+1.5VP
2

+NB_CORE

+1.5V

JUMP_43X118

JUMP_43X118
PJ19
PC14
0.1U_0603_25V7K

JUMP_43X118

PR14
22K_0402_1%
1
2

PC13
0.22U_0603_25V7K

+1.1VALWP

PJ6

PR13
100K_0402_1%

+5VALW

(120mA,40mils ,Via NO.= 2)

PJ26
2

JUMP_43X39

PR11
68_1206_5%

+1.8VS

JUMP_43X118

+VSBP

JUMP_43X118

1
1

BATT+

PQ1
TP0610K-T1-E3_SOT23-3
N1

(3A,120mils ,Via NO.=6)

PJ5

PR10
68_1206_5%
PD3
RLS4148_LL34-2

PJ3
1

+5VALWP

JUMP_43X118

(7.09A,300mils ,Via NO.=16)

(8.1A,320mils ,Via NO.=17)


PJ9

+2.5VSP

+2.5VS

+CPU_VDDR

JUMP_43X39

+3VLP
PJ21

+CHGRTC

+CPU_VDDRP

PR16
0_0603_5%
2
1

JUMP_43X39

(1.5A,40mils ,Via NO.= 3)

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/04/12

Deciphered Date

2010/10/12

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

DCIN & DETECTOR


Rev
B

PEW96 LA-6552P

Thursday, July 22, 2010

Sheet
D

34

of

45

PH1 under CPU botten side : Not SPEC, reference only!


CPU thermal protection at 92 degree C
Recovery at 56 degree C

VL
1

PR32
100_0402_1%

OT1 TMSNS2

OT2 RHYST2

1
7

@PR169
@
PR169
47K_0402_1%
1
2

G718TM1U_SOT23-8

PR261
1K_0402_5%

MAINPWON <8,36>
1

PR24
6.49K_0402_1%
2
1

+3VALWP

2
2

100K_0402_1%_NCP15WF104F03RC
2

PR33
1K_0402_1%

PC26
0.1U_0402_10V7K

PH1

1
2

EC_SMB_CK1 <28>
PC19
0.01U_0402_25V7K

2
8

GND RHYST1

4
PC20
1000P_0402_50V7K

VCC TMSNS1

@PR21
@
PR21
100K_0402_1%

PR30
9.53K_0402_1%
1
2

PH2 @

100K_0402_1%_NCP15WF104F03RC
2

<40,41>
BATT+

PL2
SMB3025500YA_2P
1
2

BATT_S1

EC_SMB_DA1 <28>

PC22
1U_0402_6.3V6K
2
1

CONN@

PU3

PJP2
SUYIN_200275GR008G13GZR

PR28
21K_0402_1%

PR27
10K_0402_1%

<40,41>
VMB

PC21
0.1U_0402_10V7K

PR29
100_0402_1%

EC_SMCA
TH
PI

VL
EC_SMDA

10
9
8
7
6
5
4
3
2
1

GND
GND
8
7
6
5
4
3
2
1

BATT_TEMP <28>

VL
1

+VSBP

PC25
0.1U_0603_25V7K
<BOM Structure>

PR34
100K_0402_1%

B+

PC24
0.22U_0603_25V7K

PQ3
TP0610K-T1-E3_SOT23-3
3

PR36
22K_0402_1%

PR39
1K_0402_5%
2

PQ4
2N7002W-T/R7_SOT323-3

2
G

<BOM
PC27Structure>
1U_0402_6.3V6K

<36,38> SPOK

PR38
100K_0402_1%

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/04/12

Deciphered Date

2010/10/12

Title

BATTERY CONN / OTP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Rev
B

PEW96 LA-6552P

Thursday, July 22, 2010

Sheet
D

35

of

45

Note:
Use TPS51125 IC can remove RTC refernece LDO
Use TPS51427 IC must keep RTC refernece LDO

PC344
1U_0603_10V6K

2VREF_8205

RT8205_B+
PL36
FBMA-L11-322513-151LMA50T_1210

PR265
30.9K_0402_1%
1
2

PR266
20K_0402_1%
1
2

PR267
20K_0402_1%
1
2

20

LX_5V

LGATE2

LGATE1

19

LG_5V

1
2
1

PQ62
AO4712_SO8

3
2
1
PC359
1U_0603_10V6K
2
1

RT8205_B+

2VREF_8205

PC360
4.7U_0805_10V6K

1
2

1
2

VL

Typ: 175mA

PR273
4.7_1206_5%

5
6
7
8

RT8205EGQW_WQFN24_4X4

+5VALWP

1
PC356
220U_6.3V_M

PC358
680P_0402_50V7K

NC

PL35
10UH_MSCDRI-104A-100M-E_4.6A_20%
1
2

18

VIN

VREG5
17

3
2
1

PHASE1

16

5
6
7
8

PC350
2200P_0402_50V7K
2
1

PC349
10U_1206_25V6M
2
1

ENTRIP1
1
ENTRIP1

2
FB1

REF

UG_5V

PHASE2

2
1
PC361
0.1U_0603_25V7K

1
3

PC23
1U_0402_6.3V6K

1
2

PC363
2.2U_0603_10V7K
2
1

2
G

PQ63B
DMN66D0LDW-7_SOT363-6

PQ64
PDTC115EU_SOT323

PR288
200K_0402_1%
1
2
1

<37> ACPRN

5
G

+
2

RT8205
TONSEL=VREF (1)SMPS1=300KHZ (+5VALWP)
(2)SMPS2=375KHZ(+3VALWP)

TPS51125A
TONSEL=VREF (1)SMPS1=245KHZ (+5VALWP)
(2)SMPS2=305KHZ(+3VALWP)
3.3VALWP Delta I = 1.902A (Freq=305KHz)
Iocp = 6.1232A ~ 8.3291A
5VALWP Delta I = 3.199A (Freq=245KHz)
Iocp = 8.74A ~ 10.16A

PR276
100K_0402_1%

PR277
100K_0402_1%

2
1
PR278
40.2K_0402_1%

TONSEL

22
21

EN
3

<8,35> MAINPWON

ENTRIP2

BOOT1

13

PC357
680P_0402_50V7K
2
1

1
2
3

ENTRIP2

PQ60
AO4466_SO8
4

SPOK <35,38>

B+

23

UGATE1

PR274
499K_0402_1%
1
2

PR279
0_0402_5%
1
2

PGOOD

VFB=2.0V

VL

VO1

24

UGATE2

BOOT2

ENTRIP1

PQ63A
DMN66D0LDW-7_SOT363-6

RT8205_B+
PR269
154K_0402_1%
1
2

PR271 PC354
2.2_0603_5% 0.1U_0603_25V7K
BST_5V 1
2 1
2

GND

12

VREG3

15

8
7
6
5

LG_3V
PQ61
AO4468_SO8

+
2

VO2

1
2 1
2 BST_3V 9
2.2_0603_5%
UG_3V 10
PC353
0.1U_0603_25V7K
LX_3V
11

PR275
100K_0402_1%

1
PC355
220U_6.3V_M

SKIPSEL

1
2
3

PR270

1
PR272
4.7_1206_5%
2
1

P PAD

14

25

PL34
4.7UH_SIL104R-4R7PF_5.7A_30%

+3VALWP

ENTRIP2

PC352
4.7U_0805_10V6K

PU19

PC347
10U_1206_25V6M
2
1

8
7
6
5
PQ59
AO4466_SO8
4

PR268
137K_0402_1%
1
2

FB2

+3VLP

VS

PR264
13K_0402_1%
1
2

Typ: 175mA

2
PC348
2200P_0402_50V7K
2
1

1
PC351
1000P_0402_50V7K
2
1

PC362
0.1U_0402_25V6
2
1

B+

+3.3VALWP Ipeak=5.629A ; Imax=3.940A


Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)
Vlimit=(10E-06 * 133K)/10=133mV
Ilimit=133mV/(22m*1.2) ~ 133mV/(17.4m*1.2)
=6.157A ~ 7.389A
Iocp=Ilimit+Delta I/2
=6.931A ~ 8.162A
Delta I=1.547A (Freq=375KHz)

+5VALWP Ipeak=5.875A ; Imax=4.113A


Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)
Vlimit=(10E-06 * 154K)/10=154mV
Ilimit=154mV/(18m*1.2) ~ 154mV/(15m*1.2)
=7.14A ~ 8.56A
Iocp=Ilimit+Delta I/2
=8.44A ~ 9.86A
Delta I=2.613A (Freq=300KHz)

PQ65
2N7002W-T/R7_SOT323-3

<28,32> EC_ON

2
PQ66
PDTC115EU_SOT323

2010/04/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2010/10/12

Title

+5VALWP/+3VALWP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Rev
B

PEW96 LA-6552P

Thursday, July 22, 2010

Sheet
1

36

of

45

Iada=0~3.42A(65W/19V=3.421A)

1
CSIN

20

CSIP

19

S
PC55
0.01U_0402_25V7K

PR77
100_0402_1%
1
2

PHASE

18

VCOMP

ICM

CHLIM

BOOT

16

10

ACLIM

VDDP

15

11

VADJ

LGATE

14

12

GND

PGND

13

4
2

PQ54
2N7002W-T/R7_SOT323-3
2
65W/90W#
G

26251VDD

DL_CHG

PQ57
AO4468_SO8

PD12
RB751V-40TE17_SOD323-2

12.1K_0402_1%

<40,41>

PC59
0.1U_0603_25V7K
BST_CHGA 2
1

6251VDDP

1
1
2

DH_CHG
PR82
2.2_0603_5%
BST_CHG 1
2

PQ24
2N7002W-T/R7_SOT323-3

BATT+

17

ACPRN 2
G

PL5
PR78
10UH_PCMB104T-100MS_6A_20%
0.02_1206_1%
CHG1
1
2
4

4
1

UGATE

6251aclim
PR87
20K_0402_1%

<28>

VREF

PR84

2 PACIN
G
@ PQ23
2N7002W-T/R7_SOT323-3

3
2
1

0.1U_0402_16V7K
6251VREF 1

ACOFF

PR83
100K_0402_1%

6251VREF

PC58
1
2

PR85
2.55K_0402_1%

<28,40> ACOFF

<28> IREF

PR81
80.6K_0402_1%
2
1

2
1
PC60
0.01U_0402_25V7K
2
1

PQ53
PDTC115EU_SOT323

PR79
47K_0402_5%
PACIN 1
2

<28> ADP_I

PR86
4.7_0603_5%
PC64
4.7U_0805_6.3V6K

PC63
10U_1206_25V6M
2
1

ICOMP

PQ55
AO4466_SO8

CSOP

@PR67
@
PR67
200K_0402_1%
1
2
VIN

PC68
10U_1206_25V6M
2
1

21

PC52
0.1U_0603_25V7K
2
1

CSOP

PR283
VIN1 100K_0402_1%
1
2

CELLS

CSON

PC53
0.047U_0603_16V7K
1
2
PR73
20_0402_5%
2
1
PR74
PC129
20_0402_5%
0.1U_0603_25V7K
1
2
PR76
2_0402_5%
LX_CHG

PC54
6800P_0402_25V7K
1
2
PR75
10K_0402_1%
1
2

1 1

2
22

2
CSON

5
6
7
8

EN

PR72
20_0402_5%
1
2

PR80
4.7_1206_5%

1
1

ACPRN

PQ68B
DMN66D0LDW-7_SOT363-6

23

PC127
0.1U_0603_25V7K
DCIN
2
1

PC128
680P_0402_50V7K

5
G

ACSET ACPRN

PR282
14.3K_0402_1%

3
2
1

PQ68A
DMN66D0LDW-7_SOT363-6
2
G

@ PD17
BAS40CW_SOT323-3
3 ACOFF
2 1
2

5
6
7
8

<28> 3S/4S#

24

VIN

PR65
10K_0402_1%

PC57
2200P_0402_50V7K
2
1

2
1 1

6251_EN

DCIN

PQ35
PDTC115EU_SOT323

VDD

PC364
1000P_0402_50V7K

PR63
47K_0402_1%
1
2

PQ20
PDTC115EU_SOT323

PR69
150K_0402_1%

2
1
PR71
100K_0402_1%

6251VDD

8
7
6
5

ACSETIN

PR281
10_1206_5%
PU5

PR70 47K_0402_5%
2

PR280
191K_0402_1%

PD16
RB751V-40_SOD323-2

ACSETIN

PR68
0_0402_5%
2
1

<28> FSTCHG
PQ21
PDTC115EU_SOT323

PreCHG

PC61
2200P_0402_50V7K
2
1

VIN

PC48
0.1U_0603_25V7K
2
1

CSIP

47K

1
2
3

CSIN

PR94
200K_0402_1%

PQ16
AO4435L_SO8

PC51
10U_1206_25V6M
2
1

PC49
2.2U_0603_6.3V6K
2
1

1
3

CHG_B+

PL37
FBMA-L11-322513-151LMA50T_1210

6251VDD

VIN1

PQ19
PDTA144EU_SOT323-3

47K
2

PC62
0.1U_0603_25V7K
2
1

1
PR62
200K_0402_1%

PC50
10U_1206_25V6M
2
1

8
7
6
5

1
2
3

B+

PR61
0.02_2512_1%

P3

PQ15
AO4407A_SO8

1
2
3

8
7
6
5

B+

P2

PQ14
AO4435L_SO8

VIN

CP = 85%*Iada ; CP = 2.91A
CP = 85%*Iada ; CP = 4.07A

ADP_I = 19.9*Iadapter*Rsense

PC56
5600P_0402_25V7K
1
2

Iada=0~4.74A(90W/19V=4.736A)

ISL6251AHAZ-T_QSOP24

CP= 85%*Iada; CP=2.91A

<28> CALIBRATE#

6251VDD
PR90
31.6K_0402_1%

CP mode
Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05)
where Vaclm=1.464V (90W), Iinput=4.03A
PR84=12.1K;PR87=20K
where Vaclm=0.391(65W), Iinput=2.91A
PR84=12.1K;PR85=2.55K

PR284
10K_0402_1%
1
2

Iada=0~3.42A(65W)

PR88
15.4K_0402_1%
1
2
2

CP= 85%*Iada; CP=4.03A

Iada=0~4.74A(90W)

ACIN <28,33>

PR286
10K_0402_1%
2

PR285
47K_0402_1%

PACIN

PR287
14.3K_0402_1%

CC=0.6~4.48A

2
PQ67
PDTC115EU_SOT323

IREF=1.016*Icharge

<36> ACPRN

IREF=0.43V~3.24V
4

BATT Type

Charging Voltage
(0x15)

CV mode

12600mV

12.60V

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Normal 3S LI-ON Cells

2010/04/12

Deciphered Date

2010/10/12

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

CHARGER
Rev
B

Thursday, July 22, 2010

Sheet
D

37

of

45

PR96
255K_0402_1%
1
2

DCR= 7.5 mohm


14

11

VDDP

LX_1.1VALW
2
PR102
7.32K_0402_1%

10

LGATE

DL_1.1VALW

+ PC76
330U_6.3V_M

S IC G5603RU1U TQFN 14P PWM

PC80
4.7U_0805_10V6K

2
PC78
680P_0603_50V7K

PR103
4.7K_0402_1%
2
1

Cout ESR=15m ohm Rdson(max)=5.6 mohm Rdson(typ)=4.5 mohm.


Ipeak=7.42A, Imax=5.2A, Iocp=8.9A
Delta I=((19-1.1)*(1.1/19))/(L*Fsw)=2.06A
=>1/2Delta I=1.03A
Vtripmax=Iocp*Rdson=8.9*5.6*1.3=0.065V
Rcs=Vtrip/9uA=0.065V/9uA=7.2K
choose Rcs=7.32K
Iocpmax=((7.32K*11uA)/0.0045)+1.03A=19A
Iocpmin=((7.32K*9uA)/(0.0056*1.3))+1.03A=10A
Iocp=10A~19A

PR104
8.45K_0402_1%

PL32
FBMA-L11-322513-151LMA50T_1210

1
2

B+

PC83
2200P_0402_50V7K

1
2

5
6
7
8

PQ27
AO4466_SO8

VDDP

10

2
PR112
18.2K_0402_1%

FB

DL_1.5V

LGATE

+5VALW

S IC G5603RU1U TQFN 14P PWM

Cout ESR=17 mohm Rdson(max)=18 mohm Rdson(typ)=15 mohm


Ipeak=7A, Imax=8.4A, Iocp=13.2A
Delta I=((19-1.5)*(1.5/19))/(L*Fsw)=3.9A
=>1/2Delta I=1.95A
Vtripmax=Iocp*Rdson=16.2*5.6*1.3=0.118V
Rcs=Vtrip/9uA=0.118V/9uA=13.1K
choose Rcs=13K
Iocpmax=((13K*11uA)/0.0045)+1.95A=32A
Iocpmin=((13K*9uA)/(0.0056*1.3))+1.95A=18A
Iocp=9.94A~13.2A

1
+ PC86
330U_6.3V_M

PC88
680P_0603_50V7K

PC90
4.7U_0805_10V6K

PR113
10K_0402_1%
2
1

PR114
10K_0402_1%
2

<Vo=1.5V> VFB=0.75V
Vo=0.75*(1+10K/10K)=1.5V
Fsw=335KHz

PQ28
AO4712_SO8

PGND
8

PGOOD

GND

PC87
4.7U_0603_6.3V6K

+1.5VP

11

14

12

CS

PHASE

PR110
4.7_1206_5%

VDD

LX_1.5V

VOUT

DH_1.5V
5
6
7
8

13

UGATE

PL7
1.8UH_1164AY-1R8N=P3_9.5A_30%
1
2

3
2
1

+5VALW

TON

PC84
0.1U_0603_25V7K
BST_1.5V-1
1
2

BOOT

2
PR111
100_0603_1%
1
2

15

PU7

NC

@PC85
@PC85
0.1U_0402_16V7K

@PR109
@
PR109
30K_0402_5%

EN/DEM

3
2
1

PR108
2.2_0603_5%
BST_1.5V 1
2

PR105 0_0402_5%
1
2

PC82
10U_1206_25V6M

1.5V_B+

PR106
226K_0402_1%
1
2

<28,33> SYSON

PQ26
AO4456_SO8

PGND

<Vo=1.1V> VFB=0.75V
V=0.75*(1+4.7K/10K)=1.1V
Fsw=280KHz

PGOOD

GND

6
2

PC77
4.7U_0603_6.3V6K

PR100
4.7_1206_5%

+5VALW

+1.1VALWP

NC

FB

12

CS

PHASE

VDD

0.1U_0603_25V7K

VOUT

DH_1.1VALW

13

UGATE

5
6
7
8

TON

3
2
1

PL6
1.0UH_PCMC104T-1R0MN_20A_20%
1
2

PC75
BST_1.1VALW-11
2

BOOT

EN/DEM

PU6

PR101
100_0603_1%
1
2

15

1
@ PC74
@PC74
0.1U_0402_16V7K

@ PR99
30K_0402_5%

+5VALW

PQ25
AO4466_SO8

PR98
2.2_0603_5%
BST_1.1VALW
1
2

<35,36> SPOK

B+

3
2
1

PR97
0_0402_5%
1
2

PL31
FBMA-L11-322513-151LMA50T_1210
2
1

PC72
10U_1206_25V6M

5
6
7
8

PC139
2200P_0402_50V7K

1.1VALW_B+

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/04/12

Deciphered Date

2010/10/12

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

1.1VALWP/1.5VP
Rev
B

PEW96 LA-6552P
Sheet

Thursday, July 22, 2010


D

38

of

45

PL33
FBMA-L11-322513-151LMA50T_1210
2
1

PR115
255K_0402_1%
1
2

14

12

CS

11

VDDP

10

2
PR121
7.5K_0402_1%

DL_NB_CORE

Cout ESR=15m ohm Rdson(max)=18m Rdson(typ)=15m


Ipeak=7.6A, Imax=5.4A, Iocp=9.2A
Delta I=((19-1.1)*(1.1/19))/(L*Fsw)=2.06A
=>1/2Delta I=1.03A
Vtripmax=Iocp*Rdson=9.2*5.6*1.3=0.067V
Rcs=Vtrip/9uA=0.067V/9uA=7.44K
choose Rcs=7.5K
Iocpmax=((7.5K*11uA)/0.0045)+1.03A=19.36A
Iocpmin=((7.5K*9uA)/(0.018*1.3))+1.03A=10.3A
Iocp=10.3A~19.36A

PC218
100U_25V_M

1
2

PC125
0.1U_0402_25V6

PQ43
PR157
2N7002W-T/R7_SOT323-3 0_0402_5%
2
2
1
G

POWER_SEL <13>

1.1V

PC126
0.01U_0402_25V7K

PJ24
@ JUMP_43X79

0.95V

LOW

PR159
10K_0402_5%
2
1

POWER_SEL
HIGH

PC115
1U_0402_6.3V6K

1
VIN

PC118
0.01U_0402_25V7K

GND

PR154
31.6K_0402_1%

APL5915KAI-TRL_SO8

VDDR_SW

OUT

1.05V

PC114
1U_0402_6.3V6K

0.9V

PQ58
2N7002W-T/R7_SOT323-3
S

@ PR153
@PR153
150_1206_5%
4

+2.5VSP

2
1

LOW

2
G

GND

1
2

<20> VDDR_SW

IN

PC113
4.7U_0805_6.3V6K

HIGH

@ PR152
@PR152
10K_0402_1%

+3VS

PR156
249K_0402_1%

PR161
165K_0402_1%

PU16
APL5508-25DC-TRL_SOT89-3

+5VALW

+CPU_VDDRP

FB

PR188 @
47K_0402_5%

EN

VOUT

PC116
4.7U_0805_6.3V6K

@PR155
@
PR155
10K_0402_1%
1
2

VIN
VOUT

PC119
22U_0805_6.3V6M

POK

PU12
7

VCNTL

10K_0402_1%
1
2

2
1
2
G

PR123
8.87K_0402_1%

+5VALW
3

PC121
0.1U_0402_16V7K

PC99
4.7U_0805_10V6K

PR131
10K_0402_1%
1

PR158
11.8K_0402_1%

+1.5V

VLDT_EN

PC97
680P_0603_50V7K
2

S IC G5603RU1U TQFN 14P PWM

+5VALW

<28,42> VR_ON

PR122
2.37K_0402_1%
1
2

PQ44
2N7002W-T/R7_SOT323-3

PR162

+ PC95
330U_6.3V_M

4
1

LGATE

PQ30
AO4456_SO8

PGOOD

GND

PC96
4.7U_0603_6.3V6K

<Vo=1.1V> VFB=0.75V
V=0.75*(1+4.7K/10K)=1.1V
Fsw=280KHz

PGND

FB

PR119
4.7_1206_5%

+5VALW

+NB_COREP

BOOT

EN/DEM

PHASE

LX_NB_CORE

VDD

DH_NB_CORE 0.1U_0603_25V7K
5
6
7
8

VOUT

NC

13

UGATE

FB1_NB_COREP

TON

PL8
1.0UH_PCMC104T-1R0MN_20A_20%
1
2

PC93
BST_NB_CORE-1
1
2

3
2
1

PR120
100_0603_1%
1
2

15

1
2

PU8

PC94
0.1U_0402_16V7K
2

+
2

DCR= 7.5 mohm

@PR118
@
PR118
30K_0402_5%

+5VALW

PQ29
AO4466_SO8

<28,33> VLDT_EN

PR117
2.2_0603_5%
BST_NB_CORE
1
2

B+

3
2
1

PR116
100K_0402_5%
1
2

PC91
10U_1206_25V6M

5
6
7
8

PC140
2200P_0402_50V7K

NB_CORE_B+

PR160
10K_0402_1%

2010/04/12

Deciphered Date

2010/10/12

Title

NB_CORE/2.5VS/CPU_VDDRP

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Rev
B

PEW96 LA-6552P
Sheet

Thursday, July 22, 2010


D

39

of

45

PreCHG
+1.5V

VREF VCNTL

VOUT

NC

TP

+3VALW
PC101
1U_0603_6.3V6M

PR128
100K_0402_5%

PR130
1K_0402_1%

PR127
1K_1206_5%
1
2

PR129
100K_0402_5%

S
2N7002W-T/R7_SOT323-3

1
PR132
100K_0402_5%

+0.75VSP

PQ33
DTC115EUA_SC70-3

PD18
PC103
22U_0805_6.3V6M

<28,37> ACOFF

+5VALWP

2
1

PQ34
DTC115EUA_SC70-3

3
BAS40CW_SOT323-3
2

PR134
1K_0402_1%

PC102
0.1U_0402_16V7K
2
1

PC104
0.22U_0402_10V4Z

PQ32
2
G

PR133
300K_0402_5%
1
2

<33> SUSP

UP7711U8 PSOP 8P

1 2

NC

B+
1

LL4148_LL34-2

NC

GND

VIN

2
2

PR126
1K_1206_5%
1
2

PU9

PC100
4.7U_0805_6.3V6K

PD13
1

1
PJ17
JUMP_43X79
D

PQ31
TP0610K-T1-E3_SOT23-3

PR125
1K_1206_5%
1
2

VIN

PR124
1K_1206_5%
1
2

Change 300K / 0.22u delay


Ipeak=1A, Imax=0.7A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/04/12

Issued Date

Deciphered Date

2010/10/12

Title

Precharge/+0.75VSP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Thursday, July 22, 2010

Rev
B

PEW96 LA-6552P
Sheet
1

40

of

45

FB=0.6V

Note:Iload(max)=3.5A
D

1
1
2

SY8033BDBC_DFN10_3X3

1
2

PR145
4.99K_0402_1%
2

PC155
680P_0603_50V7K

1
2

PC1026
0.1U_0402_10V7K

1
2

PC156
0.22U_0603_25V7K

PC124
22U_0805_6.3VAM

NC

NC

TP

FB_1.8V

1.8V_EN

PR147
10K_0402_1%

FB

+1.8VSP
PC117
22U_0805_6.3VAM

PL9
2.2UH_MSCDRI-74A-2R2M-E_6.5A_20%
1
2
PC1022
68P_0402_50V8J
2
1

LX

LX_1.8V

EN

SVIN

LX

PG

PVIN

PR144
200K_0402_1%
1
2

11

VGA_ON

PVIN

PR143
4.7_1206_5%

<28,33> VGA_ON

10

PC157
22U_0805_6.3VAM

PU11

+3VALW

2010/04/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2010/10/12

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

+1.8VSP
Rev
B

PEW96 LA-6552P

Thursday, July 22, 2010

Sheet
1

41

of

45

5
6
7
8

1 2
2

PHASE1
UGATE1

25

BOOT1

1 2

+CPU_CORE_0
Design Current: 25A
Max current: 35A
OCP_min:42A

PHASE1
PL18
0.36UH_PCMC104T-R36MN1R17_30A_20%
1
2
5

1
1 2

4
@ PQ52
AON6704L_DFN8-5

PC208
680P_0603_50V7K

3
2
1

3
2
1

VSEN1

DIFF_1

PR247
16.2K_0402_1%
PR248
4.7_1206_5%

PQ49
AON6704L_DFN8-5
4

PR251
10_0402_5%
1

+CPU_CORE

PR243
2.2_0603_5%
BOOT1 1
2 1
PC207
0.1U_0603_25V7K

PC198
2200P_0402_50V7K
2
1
1

UGATE1

@ PR252 1K_0402_1%
2
1

+CPU_CORE

PC197
0.01U_0402_25V7K
2
1

3
2
1
5
5

49

24
ISN1

ISP1
23
ISP1

VW1
22

FB1

21

20

19

14

CPU_B+

PQ51
AON6428L 1N DFN-8

RTN1
PR246 10K_0402_1%
2
1

<8> CPU_VDD1_FB_H

PC201
1
2
0.1U_0402_16V7K

LGATE0

TP

26

BOOT1
ISN1

UGATE1

VW0

COMP1

COMP0

12

VDIFF1

11

PC202
1U_0603_16V6K

1 PR235 2
4.02K_0402_1%

ISP0

27

@ PQ47
AON6704L_DFN8-5

PC200
680P_0603_50V7K

PC206
2200P_0402_50V7K
2
1

28

PHASE1

10_0402_5%
1

PC205
0.01U_0402_25V7K
2
1

LGATE1

29

PGND1

FB0

0_0402_5%
PR240
2

+5VALW

10

PR233
4.7_1206_5%

LGATE0

LGATE1

+CPU_CORE

PR232
16.2K_0402_1%

PQ48
AON6704L_DFN8-5

PC204
4.7U_0805_25V6-K
2
1

ISL6265IRZ-T_QFN48_6X6~D

PC199
0.1U_0603_25V7K

3
2
1

VDIFF0

PL17
0.36UH_PCMC104T-R36MN1R17_30A_20%
1
2

OCSET

PR229
2.2_0603_5%
BOOT0 1
2 1

3
2
1

30

PC223
4.7U_0805_25V6-K
2
1

5
PVCC

3
2
1

LGATE0

31

RBIAS

UGATE0

32

ENABLE

PQ46
AON6428L 1N DFN-8

1
PGND0

<8>

38

37

PHASE_NB

LGATE_NB

UGATE_NB

40

39

41

PGND_NB

OCSET_NB

42
RTN_NB

SVC

RTN0

VW0

44

+1.5VS

DIFF_0

43

33

<8> CPU_VDD0_FB_L
PR245
2

FSET_NB

PHASE0

PR241
2
1
10_0402_5%

<8> CPU_VDD1_FB_L

VSEN_NB

46

SVD

VSEN0
+CPU_CORE

45

13
<8> CPU_VDD0_FB_H

FB_NB

PHASE0

ISP0
ISN0

COMP_NB

47
VCC

48
VIN

PR239
1
95.3K_0402_1%

UGATE0

ISP0

BOOT0

34

VSEN1

1
0_0402_5%

35

UGATE0

RTN1

2
PR236

BOOT0

PWROK

RTN0

<8> CPU_SVC

PGOOD

VSEN0

1
0_0402_5%

BOOT_NB

15
PR242 0_0402_5%
16
2
1
0_0402_5%
17
2 PR244 1
0_0402_5%
18
2 PR250 1

2
PR234

36

+VDDNB
Design Current: 2.8A
Max current: 4A
OCP_min:5A

PHASE0

BOOT_NB

OFS/VFIXEN

ISN0

<8> CPU_SVD

<28,39> VR_ON
PR238
2
1
21.5K_0402_1%

CPU_VDDNB_FB_L

1
2

PR237 0_0402_5%
1
2
1
2
PR231 0_0402_5% @

<18> H_PWRGD_L

PR226
10_0402_5%

PC192
220U_D2_4VM

CPU_B+

PC196
4.7U_0805_25V6-K
2
1

1
<28> VGATE

LGATE_NB

PR224
0_0402_5%

PU15

UGATE_NB

PR228
@ 105K_0402_1%

PR227
105K_0402_1%

<8>

PC193
680P_0603_50V7K

PHASE_NB

2
PR225
@ 10K_0402_1%

PHASE_NB

PR223
@ 105K_0402_1%

+CPU_CORE_NB

PR217
4.7_1206_5%

3
2
1

CPU_VDDNB_FB_H

PR221
13.7K_0402_1%
2
1
PR220
0_0402_5%

PC194
0.1U_0603_16V7K

PR222
0_0402_5%

LGATE_NB

PR219
2_0603_5%

+3VS

+CPU_CORE_NB

+5VS

PL16
3.3UH_SIQB74B-3R3PF_5.9A_20%
1
2

PQ70
AO4712_SO8

PR218
10_0402_5%
1
2

+3VS

+
2

PC191
0.1U_0603_25V7K

PR216
22K_0402_1%
2
1

2
CPU_B+

PHASE_NB

B+

PC189
1000P_0402_50V7K
2
1

PC190
0.1U_0603_16V7K

UGATE_NB
PR230
2.2_0603_5%
BOOT_NB 1
2 1

PC195
4.7U_0805_25V6-K
2
1

PR215
2_0603_5%
1
2

+5VALW

PC184
1200P_0402_50V7K

PC219
2200P_0402_50V7K
2
1

PC188
220U_25V_M

PR214
44.2K_0402_1%

PC203
4.7U_0805_25V6-K
2
1

3
2
1

PL15
FBMA-L18-453215-900LMA90T_1812
2
1

PC187
2200P_0402_50V7K
2
1

PQ69
AO4466_SO8

PC186
0.01U_0402_25V7K
2
1

5
6
7
8

PC185
10U_1206_25V6M
2
1

CPU_B+
PC183
33P_0402_50V8K
2
1

PC222
0.01U_0402_25V7K
2
1

PC221
0.01U_0402_25V7K
2
1

PC220
2200P_0402_50V7K
2
1

ISN0

1 PR249 2
4.02K_0402_1%
PC209
1
2
0.1U_0402_16V7K

VW1

COMP0

PC211
180P_0402_50V8J
PR255
1K_0402_5%
2
1

PR256
2

PC216
2
1

PC212
1000P_0402_50V7K
PR257
6.81K_0402_1%
2
1

COMP1

PC214
180P_0402_50V8J
PR258
1K_0402_5%
2
1

PR259
2

PC217
2
1

PC215
1000P_0402_50V7K
PR260
6.81K_0402_1%
2
1

54.9K_0402_1% 1200P_0402_50V7K

54.9K_0402_1% 1200P_0402_50V7K

ISN1

PR254
PC213
255_0402_1% 4700P_0402_25V7K
FB_1
2
1 2
1

ISP1

LGATE1
PR253
PC210
255_0402_1% 4700P_0402_25V7K
FB_0
2
1 2
1

PR263 @
1K_0402_5%

PR262 @
1K_0402_5%
4

2010/04/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2010/10/12

Title

+CPU_CORE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Document Number

Rev
B

NAV71
Thursday, July 22, 2010

Sheet

42
H

of

45

Version change list (P.I.R. List)


Item

Fixed Issue

Reason for change

Rev.

PG#

Modify List

Page 1 of 2
for PWR

Date

Phase

Add PR279,PR288,PC57
Change PR285 100K to 47K
Change PR287 20K to 14.3K
Change PQ67 2N7002 to PDTC115
Change PR62 47K to 200K
Change PR79 22K to47K
Change PR283 0 to 100K

2010
0528

PVT

Change PJ30 to PL36, PJ23 to PL37


Add PC361,PC362

2010
0602

PVT

Change PR265 from 30K to 30.9K

2010
0604

PVT

Modify Pre-charger

Meet common rule

HDMI test fail

5V voltage too low at test termial

ESD test fail

ESD solution

Add PC22, PC23

2010
0608

PVT

EMI test fail

EMI solution

Enable 3V,5V,1.1V,1.5V,NB_CORE,CPU snubber

2010
0608

PVT

36

Power sequence tune

Costdown

41

Costdown

38

8
9
10

For DDR voltage default/HW YC


Aprove 200MHz~220MHz/EMI Chris

Change PR144 from 22K to 200K


Change PC156 from 0.47u to 0.22u
Change PQ28 from AO4456 to AO4712
Change PR112 from 13K to 18.2K
Change PL7 from 1.0uH to 1.8uH
Change PQ61 from AO4712 to AO4468
PR268 from 133K to 137K
PQ57 from AO4466 to AO4468

2010
0609

PVT

2010
0617

PVT

DDR 2 need 0.9V, DDR 3 need 1.05V


But DDR2 voltage is critical then DDR 3

39

Disable PR152
Enable PR160

2010
0705

Pre MP

EMI solution

37

Enable PR80, PC128


Change PR82 from 0 to 2.2

2010
0705

Pre MP

Add PC26 near PC22

2010
0705

11

Add a bypass path/ESD Chris

ESD solution

35

Pre MP

12
13
14
15
A

16

2010/04/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2010/10/12

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

PIR (PWR)
Rev
B

PEW96 LA-6552P

Thursday, July 22, 2010

Sheet
1

43

of

45

Version change list (P.I.R. List)


Item

Fixed Issue

Reason for change

Rev.

PG#

Modify List

Page 2 of 2
for PWR

Date

Phase

3
4
5
C

8
9
10
B

11
12
13
14
15
A

16

2010/04/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2010/10/12

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

PIR (PWR)
Rev
B

PEW96 LA-6552P

Thursday, July 22, 2010

Sheet
1

44

of

45

05/10 First release


1. Change Cardreader chip (RTS5137/RTS5138)
2. ODD used to ODD sub/b
3. RTC Battery change (w/o charge)
D

06/11 PVT
1. P.28 Reserve R889 For EC_CLK, pop R851, unpop R852 For EC_SMBus leakage
2. P.26 Remove R853
3. P.28 project ID-->1 Board ID -->1, unstuff KSI, KSO Cap.
4. P.8 Change R41 as 31.6k ohm and R42 as 30k ohm for TSI

07/05 Pre-MP
1. P.19 Reserve R890 For MEM_1V5
2. P.28 Change R419 as 10 ohm For EMI

07/20
1. P.29 Change R477, R499 as 750 ohm; change R478 as 3.01k ohm; change R498 as 3.3k ohm for LED light
C

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/04/12

Deciphered Date

2010/10/12

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

HW PIR
Document Number

Rev
B

PEW/76/86/96 LA-6552P
Thursday, July 22, 2010

Sheet
1

45

of

45

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