LPC 2138 Tutorials

Features:
Counter or Timer operation Up to four 32-bit capture channels per timer, that can take a snapshot of the timer value when inputs signal transitions. A capture event may also optionally generate an interrupt Four 32-bit match registers that allow: o Continuous operation with optional interrupt generation on match. o Stop timer on match with optional interrupt generation. o Reset timer on match with optional interrupt generation. Up to four external outputs corresponding to match registers, with the following capabilities o Set low on match. o Set high on match. o Toggle on match.

Register Description:
Timer Interrupt Register (T0IR and T1IR): It has 4 bit for both match interrupt and capture interrupt .When interrupt occurs the corresponding bit will be one. By writing one to the bit will clear the interrupt.

CR3

CR2

CR1

CR0

MR3

MR2

MR1

MR0

Timer Control Register (T0CR and T1CR): This register is used to start and reset the timer/counter.

7 -

6 -

5 -

4 -

3 -

2 -

1 Counter Reset

0 Counter Enable

Counter Enable: 1 on this bit enable Timer counter and Prescalar counter for counting and 0 will disable Timer/Counter. Counter Reset: 1 on this bit will reset Timer counter/Prescalar counter. After resetting this bit has to loaded with 0.

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Timer Count Controller Register (T0CTCR and T1CTCR): This register is used to select timer or counter operation and if counter operation is selected the capture input.

LPC 2138 Tutorials

7 -

6 -

5 -

4 -

Count Input Select

Counter/Timer Mode

Counter/Timer Mode: These bits are used to select timer or counter mode. Value 0 0 1 1 0 1 0 1 Function Timer Mode Counter Mode/TC Increment For every rising edge Counter Mode/TC Increment For every falling edge Counter Mode/TC Increment on both edge

Count Input Select: These bits are used to select capture input pin. Value 0 0 1 1 0 1 0 1 Function CAPn.0(CAP0.0 and CAP1.0) CAPn.1(CAP0.1 and CAP1.1) CAPn.2(CAP0.2 and CAP1.2) CAPn.3(CAP0.3 and CAP1.3)

Timer Counter Register (T0TC and T1TC): This is 32 bit register which increment based on Prescalar register and if this register is not reset it will count till 0xFFFFFFFF and roll over to 0x00000000 causing overflow, but this doesnt cause interrupt. This can be used by match register. Timer Prescale Register (T0PR and T1PR): This is 32 bit register used to hold the maximum value for Prescale Counter Register. Timer Prescale Counter Register (T0PCR and T1PCR):
The 32-bit Prescale Counter controls division of PCLK by some constant value before it is applied to the Timer Counter. The Prescale Counter is incremented on every PCLK. When it reaches the value stored in the Prescale Register, the Timer Counter is incremented

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and the Prescale Counter is reset on the next PCLK. This causes the TC to increment on every PCLK when PR=0, every 2 PCLKs when PR=1.

LPC 2138 Tutorials

Match Register (MR0-MR3):

The Match register values are continuously compared to the Timer Counter value. When the two values are equal, actions can be triggered automatically. The action possibilities are to generate an interrupt, reset the Timer Counter, or stop the timer. Actions are controlled by the settings in the MCR register. Timer Match Control Register (T0MCR and T1MCR):

This register the controls the function if the Timer counter value is equal with any of the four match register (i.e. whether to enable interrupt, to reset, to stop) 15 7 MR2R 14 6 MR2I 13 5 MR1S 12 4 MR1R 11 MR3S 3 MR1I 10 MR3R 2 MR0S 9 MR3I 1 MR0R 8 MR2S 0 MR0I

MR0I: 1on tis bit enable interrupt when MR0 match occurs and 0 on this bit will disable interrupt. MR0R: 1 on this bit will reset TC on MR0 match and 0 on this bit will not reset TC. MR0S: 1 on this bit will stop TC on MR0 match and 0 on this bit will not stop TC. MR1I: 1on tis bit enable interrupt when MR1 match occurs and 0 on this bit will disable interrupt. MR1R: 1 on this bit will reset TC on MR1 match and 0 on this bit will not reset TC. MR1S: 1 on this bit will stop TC on MR1 match and 0 on this bit will not stop TC. MR2I: 1on tis bit enable interrupt when MR2 match occurs and 0 on this bit will disable interrupt. MR2R: 1 on this bit will reset TC on MR2 match and 0 on this bit will not reset TC. MR2S: 1 on this bit will stop TC on MR2 match and 0 on this bit will not stop TC. MR3I: 1on tis bit enable interrupt when MR3 match occurs and 0 on this bit will disable interrupt. MR3R: 1 on this bit will reset TC on MR3 match and 0 on this bit will not reset TC. MR3S: 1 on this bit will stop TC on MR3 match and 0 on this bit will not stop TC.

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Capture Register (CAP0-CAP3):

LPC 2138 Tutorials

Each Capture register is associated with a device pin and may be loaded with the Timer Counter value when a specified event occurs on that pin. The settings in the Capture Control Register determine whether the capture function is enabled, and whether a capture event happens on the rising edge of the associated pin, the falling edge, or on both edges.

Timer Capture Control Register (T0CCR and T1CCR):

The Capture Control Register is used to control whether one of the four Capture Registers is loaded with the value in the Timer Counter when the capture event occurs, and whether an interrupt is generated by the capture event. Setting both the rising and falling bits at the same time is a valid configuration, resulting in a capture event for both edges.

15 7 CAP2FE

14 6 CAP2RE

13 5 CAP1I

12 4 CAP1FE

11 CAP3I 3 CAP1RE

10 CAP3FE 2 CAP0I

9 CAP3RE 1 CAP0FE

8 CAP2I 0 CAP0RE

CAP0RE: 1 on this bit will cause CR0 to be loaded with the contents of TC when a sequence of 0 then 1 on CAPn.0 and 0 will disable feature. CAP0FE: 1 on this bit will cause CR0 to be loaded with the contents of TC when a sequence of 1 then 0 on CAPn.0 and 0 will disable feature. CAP0I: 1on this bit will enable interrupt when a CR0 load occurs due to a CAPn.0 event. CAP1RE: 1 on this bit will cause CR1 to be loaded with the contents of TC when a sequence of 0 then 1 on CAPn.1 and 0 will disable feature. CAP1FE: 1 on this bit will cause CR1 to be loaded with the contents of TC when a sequence of 1 then 0 on CAPn.1 and 0 will disable feature. CAP1I: 1on this bit will enable interrupt when a CR1 load occurs due to a CAPn.1 event. CAP2RE: 1 on this bit will cause CR2 to be loaded with the contents of TC when a sequence of 0 then 1 on CAPn.2 and 0 will disable feature. CAP2FE: 1 on this bit will cause CR2 to be loaded with the contents of TC when a sequence of 1 then 0 on CAPn.2 and 0 will disable feature. CAP2I: 1on this bit will enable interrupt when a CR2 load occurs due to a CAPn.0 event. CAP3RE: 1 on this bit will cause CR3 to be loaded with the contents of TC when a sequence of 0 then 1 on CAPn.3 and 0 will disable feature.

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CAP0FE: 1 on this bit will cause CR3 to be loaded with the contents of TC when a sequence of 1 then 0 on CAPn.3 and 0 will disable feature. CAP0I: 1on this bit will enable interrupt when a CR3 load occurs due to a CAPn.0 event. External Match Register (T0EMR and T1EMR): The External Match Register provides both control and status of the external match pins MAT0-MAT3.

LPC 2138 Tutorials

15 7 EMC1

14 6

13 5 EMC0

12 4

11 EMC3 3 EM3

10 2 EM2

9 EMC2 1 EM1

8 0 EM0

EM0: This bit reflects the state of output MAT0.0/MAT1.0, whether or not this output is connected to
its pin. When a match occurs between the TC and MR0, this output of the timer can toggle, go low, go high, or do nothing. Bits EMR [5:4] control the functionality of this output. EM1: This bit reflects the state of output MAT0.1/MAT1.1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this output of the timer can toggle, go low, go high, or do nothing. Bits EMR [7:6] control the functionality of this output. EM2: This bit reflects the state of output MAT0.2/MAT1.2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this output of the timer can toggle, go low, go high, or do nothing. Bits EMR [9:8] control the functionality of this output. EM3: This bit reflects the state of output MAT0.3/MAT1.3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this output of the timer can toggle, go low, go high, or do nothing. Bits EMR [11:10] control the functionality of this output. EMC0-EMC3: The Functionality of the bit EMR4-11 is given in the below table

Value 0 0 1 1 0 1 0 1

Function Nothing Clear the external match pin Set the external match pin Toggles on the external match pin

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