----------------------------------------------------------------------------------- Company: -- Engineer: --- Create Date: 17:05:08 05/07/2013 -- Design Name: -- Module Name: maq - Behavioral -- Project

Name: -- Target Devices: -- Tool versions: -- Description: --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: ----------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code.

--library UNISIM; --use UNISIM.VComponents.all;

entity maq is Port ( clk : in STD_LOGIC; rst : in STD_LOGIC; a : in STD_LOGIC; b : in STD_LOGIC; z : out STD_LOGIC); end maq;

architecture Behavioral of maq is type estados is (s0,s1); signal ep,es: estados; begin process(clk,rst) begin if(rst='1')then ep<=s0; elsif(rising_edge(clk))then ep<=es; end if; end process;

process(a,b,ep) begin

case ep is when s0 => if a='1' then es<=s1; else es<=s0; end if; when s1 => if b='1' then es<=s0; else es<=s1; end if; end case; end process;

process(ep) begin case ep is when s0 => z<='0'; when s1 => z<='1'; end case; end process;

end Behavioral;