PA in ADS For Radars

Agilent EEsof EDA
Presentation on Amplifier Design in ADS for Radar Applications
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Aerospace and Defense Symposium 2005
Amplifier Design in ADS for Radar Applications

Presented by: HeeSoo LEE
Objectives
Overview of a systematic medium power amplifier design flow in ADS Overview of available tools and utilities in ADS for amplifier design Demonstrate ADS co-simulation capability Demonstrate ADS layout for amplifier design
Page 2
Typical Block Diagram of a Radar System

Transmitter
Pulse Generator
TIMING SYNC
PA
Local Oscillator
RECEIVER PROTECTOR
To Display
ADC and Signal Processor
SYNCHRONOUS I/Q DETECTOR
LNA
Receiver
Page 3
Power Amplifier in Radar System

In this presentation, design
3 Watts medium output power two stage power amplifier 20+dB gain at 1.95GHz frequency Overall, good input and output match Two separate amplifiers without interstage matching
14.8 dBm
12 dB
26.8 dBm
34.8 dBm
8 dB
NE651R479A
NE6510179A
Page 4
Power Stage Amplifier

Deliver 3 Watts
14.8 dBm
12 dB
26.8 dBm
34.8 dBm
8 dB
NE651R479A
NE6510179A
Page 5
3 Watts HJ-FET NE6510179A

NEC L&S band medium power HJ-FET Good for power stage transistor because of
Typical 35dBm output power @5V Typical 10dB Gain at 1.9GHz
Also ADS design kit is available with nonlinear models

http://www.cel.com/prod/prod_ads_update.asp
Source: NEC
Page 6
Graphical Method of Determining Ropt*

Ropt, the load impedance at drain terminal that gives the maximum output power for devices* in Ids Class A operation Imax (VBias-VKnee)2 Ropt = 2 x POut Easy to calculate Reasonably accurate
*
VKnee
VBias
Vmax
Vds
2.67 Ropt with NE6510179A at 5V, 1.2A bias point

: Steve C. Cripps, RF Power Amplifier for Wireless communications Artech House Publishers
Page 7
Modeling of FET Ground Pad Inductance

Substrate on RT Duroid 5870, 31mil thick and oz Model ground pad in preparation for determining the optimal load impedance from a load-pull simulation Momentum EM Simulation to get S-parameters Calculation of Leff from Z-parameters: 0.163nH at 2GHz
Substrate
oz 31 mil AIR RT Duroid 5870 GND
Recommended PCB Layout
Leff =
ADS Layout for ground
Imaginary (Z11)
Page 8
DesignGuides in ADS Bridging the Gap

DesignGuides
Passive RF System Filter Linearization Bluetooth Mixer Amplifier Oscillator PLL
Simulation Technology
Applications
Amplifier, Filters Mixers, Oscillator Passives, System Mod/Demods Packaging Others
Linear, Nonlinear Circuit Envelope Time Domain Agilent Ptolemy Electromagnetic Others
Page 9
What and Where to use DesignGuides
UWB
Page 10
Determine Optimum Load Impedance Load-Pull*

Use Amplifier DesignGuides Load-Pull
Pre-configured simulation setup Pre-configured data post-processing
Simply replace it with your own device!
Menu
1-Tone Nonlinear Simulations / Load-Pull PAE, Output Power Contours

Complex Load Impedance
Ground pad is attached to the device!
*Also available in load-pull application guides Amplifier Design in ADS for Radar Applications Page 11
Load-Pull Simulation Result

Simulation maps complex load impedances to power and PAE contours Pre-configured data display for gain compression, PAE, harmonics and more Load reflection coefficient that gives maximum power is at 0.924/-169.396
36dBm 35.5dBm
Load impedances is mapped to Power and PAE contours
Page 12
Comparison of Graphical and Load-Pull Methods

Graphical Method DC only calculation 2.67 Load-Pull Method Complete non-linear AC/RF simulation Ropt = 0.924/-169.396
A: 2.67 B: 2.0 + j4.65
ZRopt = 2.0 + j*4.65 Reasonable agreement but slightly different due to Where to look into the impedance
Graphical method, at A plane: Drain terminal of intrinsic transistor Load-Pull method, at B plane: Drain terminal of extrinsic or packaged transistor
Package parasitic
Page 13
Determine Optimum Source Impedance Linear method

No information on output power but small signal gain Choice 1 : Conjugate match
Good for maximum gain Good for Input match Output match is question
Optimum transistor output match for maximum power Mapped input gain circle for transistors output impedance
Choice 2: Mismatched input for optimum output match

Better output match with a little loss of gain As an example, 0.936/-156.351 gives 1.4dB mismatch loss but better match for output
Max Gain = 9.978dB at 1.95GHz Amplifier Design in ADS for Radar Applications Page 14
Determine Optimum Source Impedance Source-Pull

Use Amplifier DesignGuides Source-Pull

Menu 1-Tone Nonlinear Simulations /
Pre-configured simulation setup Source-Pull PAE, Output Power Contours Pre-configured data post-processing Brute-force solution for finding optimum source impedance Full understanding on output power with varying source impedance
0.778/-159.090
Page 15
Stability
NE6510179A is stable at 1.95GHz design frequency with the addition of pad ground inductance Mu factor is over 1
Output Stability Circle
Input Stability Circle
Page 16
Matching Network Design
?
?
Page 17
Smith Chart Utility

User interactive matching network design View frequency response View matching network topology Define Q of the circuit Build ADS schematic Easy to use
Source and Load Terminations Series Components Shunt Components Transmission Line and Transformers
Amplifier Design in ADS for Radar Applications Page 18
Matching Utility
Available network topologies
Lowpass Highpass Bandpass
Source/Load impedance can be defined over wide frequency range Matching element transformation utility
Page 19
Output Matching Network Design

Design with Smith Chart Utility Design for reflection coefficient from load-pull, Ropt 0.924/-169.396 Ideal lumped passive and transmission line elements Display of Smith
Chart Utility
Ropt 0.924/-169.396
0.627 pF 59.85 deg 50 Ohm
Reflection Trajectory
5.6 pF
Enter conjugate of Ropt for load termination Q circle
Page 20
Input Matching Network Design

Design with Smith Chart Utility Design for reflection coefficient from source-pull, IN opt 0.778/-159.090 Ideal lumped passive and transmission line elements
IN opt 0.778/-159.090
1.37 pF
46 deg 50 Ohm
3.3 pF
Conjugate of INopt for load termination
Input Match
Page 21
Impedance Loci with Different Width and Length of Transmission Line

Discrete SMT capacitance value limits flexibility of design Parameter sweep simulation capability allows designers to understand
Impedance loci of network with varying physical dimension
Input matching
Output matching
Consider bandwidth of network with each combination
Output matching with different capacitance Blue: 0.5pF, Red: 1.0pF
Page 22
Realization of Input and Output Networks

Replace ideal capacitors with discrete vendor SMT capacitors SMT capacitors from Taiyo-Yuden ADS model library is available (Download from Web)
http://66.40.41.39//simtools/index.cfm
1.37 pF
46 deg 50 Ohm 3.3 pF
59.85 deg 50 Ohm
0.627 pF
5.6 pF
1.2pF
1 pF
Physical Realization
Page 23
Linear Simulation With ADS Models

Transmission lines in input and output matching networks were chosen to be close to 50 lines 7.81 dB small signal gain at 1.95GHz Excellent match for input and reasonable match for output
Page 24
Non-Linear Simulation with ADS Models

Use Amplifier DesignGuides pre-configured power simulation setup Gain compression at 37.07dBm 38.24% PAE 7.81 dB small signal gain
Menu
1-Tone Nonlinear Simulations / Spectrum,Gain,Harmonic Distortion vs Power (w/PAE)
Page 25
Linear Simulation with Momentum Component

Layout look alike Momentum Component for physical layout Nested EM simulation for physical layout Accurate simulation for layout parasitics Overcome limitation of valid model range for circuit models Frequency response is shifted
Comparison with ADS model simulation
Shifted Momentum Component
Solid = Layout Simulation Faint Solid = ADS Models
Page 26
Detuned Matching Network

Input and output impedances are detuned from desired impedances due to physical layout parasitics Sprobe Component Very convenient SProbe simulation component
IN opt
0.778/-159.090
Ropt
0.924/-169.396
Page 27
Advanced Model Composer (AMC)
component : tee_s : symmetrical tee model is function of :

W12 W3
Momentum calculates S-data

W3 freq W12
single frequency single W12, W3
substrate frequency range layout parameters W12 & W3
W3 freq W12
continuous frequency single W12, W3
ADS Model Composer builds parameterized models for passive components continuous frequency range & discrete and/or continuously varying layout parameters
W3 freq W12
continuous frequency discrete W12 discrete W3
W3 freq W12
continuous frequency discrete W12 continuous W3
W3 freq W12
continuous frequency continuous W12 continuous W3
Page 28
AMC Model for In/Output Matching Network

Two perturbed parameters
Line width and length
Line Width Line Length
Once the model is developed, AMC provides very fast simulation speed without a Parameter Sweep loss of accuracy Simulation with AMC Input
Matching Network Model
Parameter Sweep Simulation with AMC Output Matching Network Model
Page 29
Tuned Matching Network

Input and output matching networks are tuned for desired impedances Linear and Non-linear simulations are performed Swept input power 20 to 30dBm
Gain Compression 36dBm, 4W
Page 30
Bias Circuit Design

Transistor Bias Utility for biasing circuit for transistors
Unregulated bias network for BJT and FET OPAMP based active biasing network up to 4 devices OPAMP based regulated biasing network up to 4 devices
LineCalc Utility for synthesizing transmission lines

50 Ohm - 91 mil 31 mil RT Duroid 5870
Resistive bias network Opamp based active bias Opamp based regulated bias
Amplifier Design in ADS for Radar Applications Page 31
Linear Simulation with Bias Lines

Bias lines for source and drain terminals are attached 8.179dB small signal gain at 1.95GHz Very good input and output return loss
Due to /4 lines
Page 32
Final Non-Linear Simulation

8.179dB gain at small signal 35.48dBm 1dB gain compression 35% PAE at 35.5dBm Pout
Page 33
Driver Stage Amplifier

Deliver 480 mW
14.8 dBm
12 dB
26.8 dBm
34.8 dBm
8 dB
NE651R479A
NE6510179A
Page 34
1 Watt HJ-FET NE651R479A

NEC L&S band medium power HJ-FET Good for driver stage transistor because of
Typical 29.5dBm output power Typical 12dB Gain at 1.95GHz
ADS design kit is available with nonlinear models

http://www.cel.com/prod/prod_ads_update.asp
Source: NEC
Page 35
Load and Source Matching Network

HJ-FET NE651R479A is biased at 5V, 250mA Optimum source and load impedances were extracted from Load-Pull and Source-Pull Simulation
IN opt 0.846/-153.444
Ropt 0.707/-169.644
Page 36
Linear Performance of Driver Amplifier

13.1dB small signal gain at 1.95GHz Good input and output return loss characteristic
Due to /4 bias lines
Page 37
Non-Linear Performance
1dB gain compression at 30.57dBm 41% PAE at 30.56dBm Pout 13.1 dB small signal gain
Page 38
Final Integration and Layout

Deliver 3 Watts
14.8 dBm
12 dB
26.8 dBm
34.8 dBm
8 dB
NE651R479A
NE6510179A
Page 39
Linear Performance of Two Stage Amplifier

Total 21.37dB small signal gain Good match for input and reasonable match for output Hierarchical design is employed with a sub-network
Page 40
Non-Linear Power Simulation Setup

Use Amplifier DesignGuides pre-configured power simulation setup Hierarchical design is employed with a sub-network
Page 41
Non-Linear Performance (1)
Pre-configured data presentation from Amplifier DesignGuides
Gain Compression at 35.33 dBm
Page 42
Non-Linear Performance (2) - PAE

Overall 39.55% PAE
Page 43
Non-Linear Performance (3) - AM-to-PM

Page 44
ADS Layout for Two Stage Amplifier
Page 45
Co-Simulation of Power Amplifier in Radar System
Page 46
Power of Co-Simulation in ADS
Concept Block Diagram
Top Level Radar System Using ADS Ptolemy
Transmitter System Using ADS Circuit Envelope

Baseband Float/Fixed Point HDL(Verilog & VHDL), MatLab C++.System-C
Power Amp Circuit Using ADS EM-Circuit Co-simulation

Behavior RF/Analog Subsystem, Circuit, Transistor Level Models
Connected Solution
Physical, EM Models, Circuit Models
Page 47
Transmitter Response with 2-Stage Power AMP

70 dB System Gain Double Conversion Simulated with Circuit Envelope
Page 48
Top Level Radar System Performance with 2-Stage Power AMP

Target Distance & RCS
Top Level Radar System Design Using ADS Ptolemy
Page 49
Co-Simulation Result
LFM Chirp Source Spectrum Transmitter Output Spectrum Output to Dynamic VSA Software
Click the graph to animate in slide show mode
Page 50
Summary
ADS provides an integrated and seamless design environment for designing medium power amplifier ADS DesignGuides and Application Guides bridge the gap between complex simulation technologies and advanced applications ADS Momentum and Momentum Component provide both accuracy and convenience for taking into account physical layout parasitics ADS Co-Simulation capability allows single click simulation for multiple simulation technologies and various abstract level models
Page 51
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Revised: March 27, 2008
Product specications and descriptions in this document subject to change without notice. Agilent Technologies, Inc. 2008 Printed in USA, August 01, 2005 5989-9465EN

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Agilent EEsof EDA

Presentation on Amplifier Design in ADS for Radar Applications

Aerospace and Defense Symposium 2005

Amplifier Design in ADS for Radar Applications

Aerospace and Defense Symposium 2005

Amplifier Design in ADS for Radar Applications

Aerospace and Defense Symposium 2005

Typical Block Diagram of a Radar System

ADC and Signal Processor

SYNCHRONOUS I/Q DETECTOR

Amplifier Design in ADS for Radar Applications

Aerospace and Defense Symposium 2005

Power Amplifier in Radar System

Amplifier Design in ADS for Radar Applications

Aerospace and Defense Symposium 2005

Power Stage Amplifier

Amplifier Design in ADS for Radar Applications

Aerospace and Defense Symposium 2005

3 Watts HJ-FET NE6510179A

Also ADS design kit is available with nonlinear models

Amplifier Design in ADS for Radar Applications

Aerospace and Defense Symposium 2005

Graphical Method of Determining Ropt*

2.67 Ropt with NE6510179A at 5V, 1.2A bias point

Amplifier Design in ADS for Radar Applications

Aerospace and Defense Symposium 2005

Modeling of FET Ground Pad Inductance

Recommended PCB Layout

Amplifier Design in ADS for Radar Applications

Aerospace and Defense Symposium 2005

DesignGuides in ADS Bridging the Gap

Amplifier Design in ADS for Radar Applications

Aerospace and Defense Symposium 2005

What and Where to use DesignGuides

Amplifier Design in ADS for Radar Applications

Aerospace and Defense Symposium 2005

Determine Optimum Load Impedance Load-Pull*

1-Tone Nonlinear Simulations / Load-Pull PAE, Output Power Contours

Ground pad is attached to the device!

Aerospace and Defense Symposium 2005

Load-Pull Simulation Result

Load impedances is mapped to Power and PAE contours

Amplifier Design in ADS for Radar Applications

Aerospace and Defense Symposium 2005

Comparison of Graphical and Load-Pull Methods

Amplifier Design in ADS for Radar Applications

Aerospace and Defense Symposium 2005

Determine Optimum Source Impedance Linear method

Choice 2: Mismatched input for optimum output match

Aerospace and Defense Symposium 2005

Determine Optimum Source Impedance Source-Pull

Amplifier Design in ADS for Radar Applications

Aerospace and Defense Symposium 2005

Input Stability Circle

Amplifier Design in ADS for Radar Applications

Aerospace and Defense Symposium 2005

Matching Network Design

Aerospace and Defense Symposium 2005

Smith Chart Utility

Aerospace and Defense Symposium 2005

Amplifier Design in ADS for Radar Applications

Aerospace and Defense Symposium 2005

Output Matching Network Design