VHDL

INTEGRATED CIRCUITS
INTEGRAED CIRCUITES (IC) MEANING THAT ALL THE COMPONENTS IN THIS CIRCUITS ARE FABRICATED ON THE SAME CHIP.

ICs HAVE BECOME A VITAL PART OF MODERN ELECTRONICS CIRCUITS DESIGN . THEY ARE USED IN THE COMPUTER INDUDTRY ,AUTOMOBILE INDUSTRY, HOME APPLIANCES, COMMUNICATION AND CONTROL SYSTEMS.
ICs ARE OF TWO BASIC TYPES :

MOORES LAW
MOORE WHO IS KNOWN AS FATHER OF PRINTER. IN 1970 MOORE GAVE THE LAW WHICH IS KNOWN AS MOORES LAW. ITS STATE THAT AFTER EACH 18\24 MONTHS THE NUMBER OF COMPONETS IS DOUBLEED IN IC . FOR EXAMPLE INTEL PROCESSOR P4 AFTER TWO YEARS LATER COMES CORE 2 DUAL ,BUT PROCSSOR DUAL CORE COMES IN JUST SIXTH MONTHS LATER SO THE AVERAGE IS 18 MONTHS.

NOTE: IN VHDL COMBINATION CIRCUITS IS USED INSTEAD OF SEQUENTIAL CIRCUITS (ALSO KNOWN AS FSM ).

INTEL MICROPROCESSORS
PROCESSOR YEAR OF INTRODUCTION NUMBER OF TRANSISTORS INITIAL CLOCK SPEED

4004
8008 8080 8085 8086 8088 80286 80386 80486

1971
1972 1974 1976 1978 1979 1982 1985 1989

2300
3500 6000 6500 29000 29000 134000 275000 1.2M

108KHz
200KHz 2MHz 5MHz 5MHz 5MHz 8MHz 16MHz 25MHz

PENTIUM
PENTIUM II PENTIUM III

1993
1997 1999

3.1M
8.8M 9.5M

150MHz
233MHz 650MHz

PENTIUM 4
DUAL CORE

2000

42M

1.4GHz

GENERATION OF INTEGRATED CIRCUITS

TECHNOLOGY
INVENTON OF TRANSISTOR DISCREATE COMPONENTS SMALL SCALE INTEGRATION MEDIUM SCALE INTEGRATION LARGE SCALE INTEGRATION VERY LARGE SCALE INTEGRATION NO. OF TRANSISTER PER CHIP 1 1 10 100-1000 1000-20,000 20,000-1,00,000 YEAR 1947 1950 1961 1966 1971 1980

ULTRA LARGE SCALE INTEGRATION GIANT SCALE INTEGRATION

1,00,000-10,00,000 >10,00,000

1990 2000

VLSI DESIGN
VLSI

Front end designing (coding) (vhdl and verilog hdl)

Backend designing (tanner tool) (fabrication/physic

al implementation of
porogramming)

VLSI AN INTRODUCTION
VLSI IS A PROCESS OF INTEGRATION OF MILLIONS OF TRANSISTOR IN A SINGLE CHIP .VLSI DESIGN INVOLVES ALL ASPECTS OF CREATING AN IC. VLSI DESIGN PROCESS IS CLASSIFIED INTO TWO CATEGORIES . FRONT END AND BACK END . IN FRONT END VLSI DESIGN PROCESS A DESIGN ENGINEER PERFORMS ALL ASPECTS OF DESIGN BEFORE HANDLING THE DESIGN. IN BACK END VLSI DESIGN PROCESS TASKS PERFORMED BY DESIGN ENGINEERS ARE(a) MASK GENERATION (d)TESTING (b)WAFER PROCESSING (e)DELIVERY OF SAMPLES (c)PACKAGING (f)FINAL MASS PRODUCTION

THE VHDL LANGUAGE

VHDL IS ONE OF THE MOST ACCEPTED AND WIDELY USED LANGUAGE FOR DESCRIBING DIGITAL SYSTEM . VHDL HAS BEEN APPROVED BY IEEE AS A STANDARD LANGUAGE FOR DESIGING HARDWARE. VHDL IS A LARGE AND VERBOSE LANGUAGE WITH MANY COMPLEX CONSTRUCTS AND IT IS INITIALLY DIFFICULT TO UNDERSTAND. HOWEVER IT IS POSSIBLE TO QUICKLY UNDERSTAND A SUB SET OF VHDL WHICH IS BOTH SIMPLE AND EASY TO USE. VHDL IS ABBRIVATION FOR VHSIC HARDWARE DESCRIPTION LANGUAGE.

HISTORY OF VHDL
In 1981: IN EARLY 80s DEPARTMENT OF DEFENSE (DOD) OF USA WAS INVOLVED WITH VARIOUS VENDORS TO PURCHASE VHSIC CHIPS AND ALL THOSE VENDORS WERE USING DIFFERENT HARDWARE DESCRIPTION LANGUAGES TO DESCRIBE THEIR PRODUCTS . DUE TO THIS DOD WAS FACING PROBLEM OF TESTING AND VERIFICATION AT THAT TIME THE NEED OF A STANDARD HARDWARE LANGUAGE WHICH IS CAPABLE OF DESIGN , DOCUMENTATION AND VERIFICATION OF DIGITAL SYSTEM WAS GENERATED. In 1983: DOD GAVE CONTRACT TO IBM ,TEXAS, INSTRUMENTS AND INTERMETRICS TO DEVELOP A LANGUAGE WHICH CAN DESCRIBE A HARDWARE OR A UNIVERSAL LANGUAGE . In 1985: VHDL VERSION 7.2 MADE AVILABLE.

HISTORY OF VHDL
In 1987: STANDARD VERSION OF VHDL IEEE Std 1076-1987 WAS LAUNCHED FOR INDUSTRIAL USE In 1993: REVISED IEEE Std-1076-1993 STANDARD WAS RELEASED, VHDL-93. In 2001: REVISED IEEE Std-1076-2001 STANDARD WAS RELEASED, VHDL-2001. In 2002: WORK ON VHDL -200X STARTED.

VHDL DESIGN CYCLE

DESIGN IDEA VHDL MODLE SIMULATION SIMULATED WAVEFORMS SYNTHESIZER CIRCUIT GENERATED

CIRCUITED IMPLEMENTED

PROGRAM STRUCTURE
LIBRARY/PACKAGE ENTITY ARCHITECTURE

BASIC TERMINOLOGY/ DESIGN UNITS

(A) ENTITY DECLARATION (B) ARCHITECTURE BODY (C) CONFIGURATION DECLARATION (D) PACKAGE DECLARATION (E) PACKAGE BODY

ENTITY:
AN ENTITY IS THE MOST BASIC BUILDING BLOCK IN A DESIGN. A HARDWARE DESCRIPTION OF A DIGITAL SYSTEM IS CALLED AN ENTITY. AN ENTITY SPECIFIES THE EXTERNAL VIEW AND ONE OR MORE INTERNAL VIEWS.

ARCHITECTURE BODY:
THE ARCHITECTURE BODY CONTAINS THE INTERNAL DESCRIPTION OF THE ENTITY. THE ARCHTECTURE DESCRIBES THE FUNCTIONALITY & BEHAVIOUR OF THE ENTITY. AN ARCHITECTURE IS ALWAYS RELATED TO AN ENTITY.

CONFIGURATION:
IT SPECIFIES THE BINDING OF ONE ARCHITECTURE BODY FROM THE MANY ARCHITECTURE BODIES. CONFIGURATION DECLARATION IS USED TO BIND ONE OF MANY ARCHITECTURE BODIES TO AN ENTITY. IT IS ALSO USED TO BIND COMPONENTS USED IN STRUCTURAL MODEL TO OTHER ENTITY ARCHITECTURE PAIR. AN ENTITY MAY HAVE ANY NUMBER OF DIFFERENT CONFIGURATION.

PACKAGE:
A PACKAGE IS A COLLECTION OF COMMONLY USED DATA TYPES AND SUB PROGRAMS USED IN A DESIGN.

PACKAGE DECLARATION:
A PACKAGE DECLARATION ENCAPSULATES A SET OF RELATED DECLARATIONS SUCH AS DATA TYPES, COMPONENTS, SUB PROGRAM (PROCEDURE AND FUNCTIONS). THE DECLARATION INSIDE A PACKAGE CAN BE SHARED BY OTHER DESIGN UNITS BY USING A USE CLAUSE.

PACKKAGE BODY:
A PACKAGE BODY CONTAIN THE DEFINITIONS OF SUBPROGRAMS DECLARED IN A PACKAGE DECLARATION. NAME OF PACKAGE BODY SHOULD BE SAME AS PACKAGE DECLARATION. NOTE: A HADRWARE DESCRIPTION OF DIGITAL SYSTEM i.e. AN ENTITY MUST HAVE AN ENTITY DECLARATION AND AT LEAST ONE ARECHITECTURE BODY.

ENTITY DECLARATION :
ENTITY DECLARATION DESCRIBES HOW AN ENTITY IS CONNECTED TO OUTSIDE WORLD. IT DESCRIBES THE EXTERNAL VIEW OF THE ENTITY. ENTITY DECLARATION SPECIFIES THE NAME OF ENTITY. IT ALSO SPECIFIES THE INPUT AND OUTPUT PORTS THROUGH WHICH ENTITY COMMUNICATES WITH THE EXTERNAL WORLD. SYNTEX OF ENTITY DECLARATION : ENTITY entity-name IS PORT (port1: port1-type: port2: port2-type); END entity-name;

Ex.1 WRITE THE ENTITY DECLARATION FOR A 2 INPUT AND GATE. entity AND2 is port (a, b: in bit ; c : out bit); end AND2;

DESCRIPTION OF EXAMPLE:
KEYWORD ENTITY SHOWS THAT THE THIS IS THE START OF THE ENTITY STATEMENT. ALL THE KEYWORD ARE CAPITAL WORD SHOWS THAT STANDARD PACKAGE i.e. ENTITY, IS, PORT, IN, OUT. THE STANDARD DATA TYPE BIT, WHICH IS A PREDEFINED TYPE IN VHDL. NAME OF USER CREATED OBJECTS SUCH AS MUX IN LOWER CASE.

Ex. 2 WRITE THE ENTITY DECLARATION FOR A FULL ADDER. entity FullAdder is port (X, Y, Cin: in bit; -- Inputs Cout, Sum: out bit); -- Outputs end FullAdder;

FullAdde r

ARCHITECTURE :
IT SHOWS THE INSIDE VIEW OR WHAT ARE THE FUNCTIONS OPERATION ARE DONE AND WHICH TYPE OF THAT . AN ARCHITECTURE IS ALWAYS RELATED TO AN ENTITY & DESCRIBES THE BEHAVIOUR OF THE ENTITY. INTERNAL DETAILS OF AN ENTITY ARE SPECIFIED BY AN ARCHITECTURE BODY BY USING ANY ONE OF THE FOLLOWING MODEL: SYNTEX OF ARCHITECTURE: ARCHITECTURE arcitecture-name OF entityname IS .declare some signals here BEGIN .put some concurrent statement here END architecture-name;

AREHITECTURE BODY
ARECHITECTURE

DATAFLOW STYLE

BEHAVIORAL STYLE

STRUCTURAL STYLE

BEHAVIORAL MODEL:
THE BEHAVIORAL STYLE OF MODELING SPECIFIES THE BEHAVIORAL OF AN ENTITY AS A STATEMENTS THAT ARE EXECUTED SEQUENTIALLY IN THE SPECIFIED ORDER. ALL STATEMENTS WHICH ARE SPECIFIED INSIDE A PROCESS STATEMENT, DO NOT CLEARLY SPECIFIES THE STRUTURE OF THE ENTITY BUT MERELY ITS FUNCTIONALITY. A PROCESS STATEMENT IS A CONCURRENT STATEMENT THAT CAN APPEAR WITH IN AN ARCHITECTURE BODY.

EX.1 WRITE THE BEHAVIORAL MODEL DESCRIPTION OF AND GATE .

architecture AND-2-BEHAVIOR of AND-2 is begin process (A,B) begin C<=A and B; end process; end AND-2 BEHAVIOR;

EX.2 WRITE THE BEHAVIORAL MODEL DESCRIPTION OF EX-OR GATE .

architecture EX-OR-2-BEHAVIOR of EX-OR-2 is begin process (X,Y) begin Z<=X and Y; end process; end EX-OR-2 BEHAVIOR;

STRUCTURE ARCHITECTURE:
IN THE STRUCTRE STYLE OF MODELING AN ENTITY IS DESCRIBED IN TERMS OF ITS COMPONENTS AND THEIR INTERCONNECTIONS. A STRUCTURE MODEL DOES NOT TELL ABOUT THE FUNCTIONALITY OF THE ENTITY. A STRUCTURE DESCRIPTION IS EASIEST TO BE SYNTHESIZED. THE ARCHITECTURE BODY IS COMPOSED OF TWO PARTS: 1. THE DECLARATION PART (BEFORE THE KEYWORD BEGIN) 2. THE STATEMENT PART (AFTER THE KEYWORD BEGIN). HALF ADDER IS SUCH TYPE OF STRUCTURE ARCHITECTURE.

EX.1 STRUCTURAL DESCRIPTION OF HALF ADDER.

architecture HALF-ADDER-STRUCTURE of HALF-ADDER is component AND2 port(IN1,IN2: in bit ; OUT1: out bit); end component; component XOR2 port(IN3,IN4: in bit ; OUT2 : out bit); end component; begin A1:AND2 port map (A,B, Sum); X1:XOR2 port map (A,B,Carry); end HALF-ADDER-STRUTURE;

DESCRIPTION:
(A) DECLARATION PART (COMPONENTS DECLARATION )
COMPONENTS DECLARATION SPECIFIES THE NAME OF COMPONENT, NAME OF INTERFACING PORTS ,THEIR MODE (IN, ,OUT,INOUT) AND TYPE OF PORTS. HERE TWO COMPONETS ARE AND2 & XOR2, INTERFACING PORTS OF AND2 ARE IN1, IN2 (BOTH ARE INPUT PORTS) , OUT1 (OUTPUT PORTS), INTERFACING PORTS OF XOR2 ARE IN3, IN4 ( BOTH ARE INPUT PORTS ), OUT2 ( OUTPUT PORT ). .

(B)STATEMENT PART
A1 IS COMPONENT LABEL OF AND2 COMPONENT INSTANTIATION STATEMENT. INPUT PORTS A & B OF HALF ADDER ARE CONNECTED TO THE INPUT PORTS IN1 AND IN2 OF AND2 COMPONENT . OUTPUT PORT CARRY OF HALF ADDER IS CONNECTED TO THE OUTPUT PORT OUTPUT1 OF AND2 COMPONENT. X1 IS COMPONENT LABEL OF XOR2 COMPONENT INSTANTIATION STATEMENT. INPUT PORTS A & B OF HALF ADDER ARE CONNECTED TO THE INPUT PORTS IN3 AND IN4 OF XOR2 COMPONENT. OUTPUT PORT SUM OF HALF ADDER IS CONNECTED TO THE OUTPUT PORT OUTPUT2 OF XOR2 COMPONENT.

DATAFLOW ARCHITECTURE:
IN THE DATAFLOW STYLE OF MODELING AN ENTITY IS DESCRIBED IN TERMS OF DATA FLOW BY USING CONCURRENT SIGNAL ASSIGNMENT STATEMENTS. A DATAFLOW MODEL DOES NOT TELL ABOUT THE STRUCTURE OF THE ENTITY.

EX.1 DATAFLOW DESCRIPTION OF HALF ADDER. architecture HALF-ADDER-DATATFLOW of HALF-ADDER is begin SUM<=A xor B; CARRY<=A and B; end HALF-ADDER-DATAFLOW;

VHDL Description: AND gate

entity AND2 is port (a, b: in bit ; c : out bit); end AND2;

architecture beh of AND2 is begin c <= a and b; end beh;

VHDL Description: MUX

entity MUX_4 is port (IN1, IN2, IN3, IN4, S1, S0 : in BIT; ZOUT : out BIT); end MUX_4; architecture BEH of MUX_4 is begin process(IN1, IN2, IN3, IN4, S0, S1) begin if (S1 = '0' and S0 = '0') then ZOUT <= IN1; elsif (S1 = '0' and S0 = '1') then ZOUT <= IN2;

elsif (S1 = '1' and S0 = '0') then ZOUT <= IN3; else ZOUT <= IN4; end if end process; end BEH;

VHDL SOFTWARE USED

1.XILINX ISE 8.1 I 2.ALTERA 3.QUARTUS

OUTPUT WAVE FORM

OUTPUT WAVE FORM

OUTPUT WAVE FORM