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  • Pcieclock

    Hochgeladen von

    Leah Wells
    9 Ansichten2 Seiten
    This document shows a circuit diagram with various components connected to provide reference clocks to FPGA transceivers. It includes capacitors, resistors and an oscillator connected to differential clock input pins on the FPGA. The document also provides information on reference clock requirements for FPGA transceivers, noting the common mode voltage, required voltage swing range and that AC coupling is needed between the oscillator and clock inputs.

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    Originaltitel

    pcieclock

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    This document shows a circuit diagram with various components connected to provide reference clocks to FPGA transceivers. It includes capacitors, resistors and an oscillator connected to differential clock input pins on the FPGA. The document also provides information on reference clock requirements for FPGA transceivers, noting the common mode voltage, required voltage swing range and that AC coupling is needed between the oscillator and clock inputs.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Als DOCX, PDF, TXT herunterladen oder online auf Scribd lesen
    Markieren Sie unangemessene Inhalte
    9 Ansichten2 Seiten

    Pcieclock

    Hochgeladen von

    Leah Wells
    This document shows a circuit diagram with various components connected to provide reference clocks to FPGA transceivers. It includes capacitors, resistors and an oscillator connected to differential clock input pins on the FPGA. The document also provides information on reference clock requirements for FPGA transceivers, noting the common mode voltage, required voltage swing range and that AC coupling is needed between the oscillator and clock inputs.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Als DOCX, PDF, TXT herunterladen oder online auf Scribd lesen
    Markieren Sie unangemessene Inhalte
    von 2

    VCC_3.

    VCC_3.3_CLK
    VDDA_3.3V

    FB39

    C1122
    0.1UF/16V/0402

    0.1UF/16V/0402

    C155

    VCC_3.3

    1UF/X5R/10V/0402

    0E/0603

    0.1UF/16V/0402 C161

    C1152
    10uF/10V/0805

    R89
    0.1UF/16V/0402 C160

    FERRITE

    0.1UF/16V/0402 C159

    2
    0.1UF/16V/0402 C158

    C1123

    VCC_3.3

    VCC_3.3_CLK
    Y4
    1
    C162

    R92
    4.7K/0603/1%

    25MHZ
    22pF/50V/0402

    C163
    22pF/50V/0402

    R895

    240E

    0E/0402
    CLK_25M_B

    R868
    TP91
    1
    1

    SEL2

    PCIE4
    PCIEN4
    OE_6
    OE_5
    PCIE3
    PCIEN3
    PCIE2
    PCIEN2
    OE_4

    R109
    R108
    31
    31

    R93
    4.7K/0603/1%

    U13

    I2C2_SDA
    I2C2_SCL
    0E/0402
    0E/0402

    1
    2
    3
    4
    5
    6
    7
    8
    9
    10
    11
    12
    13
    14
    15
    16
    17
    18
    19
    20
    21
    22
    23
    24

    XIN/CLKIN DIF_STOP
    X2
    VSPREAD
    VDD1
    SEL_14M_25M
    GND1
    VOE_3
    REFOUT
    DIF_3
    VFS2
    DIF_3
    VOE_7
    VDD5
    DIF_7
    DIF_2
    DIF_7
    DIF_2
    VDD2
    OE_2
    DIF_6
    GND3
    DIF_6
    VDD6
    OE_6
    OE_1
    VDD3
    DIF_1
    GND2
    DIF_1
    OE_5
    VDD7
    DIF_5
    DIF_0
    DIF_5
    DIF_0
    VDD4
    VOE_O
    DIF_4
    VFS1
    DIF_4
    VFS0
    VOE_4
    IREF
    SDATA
    GNDA
    SCLK
    VDDA6

    25
    26
    27
    28
    29
    30
    31
    32
    33
    34
    35
    36
    37
    38
    39
    40
    41
    42
    43
    44
    45
    46
    47
    48

    R94
    OE_3
    PCIEN1
    PCIE1

    33E/0402/1%

    10K/0603/1%

    R96 33E/0402/1%
    R97 33E/0402/1%
    OE_2
    OE_1
    R102 33E/0402/1%
    R104 33E/0402/1%
    R106 33E/0402/1%
    R107 33E/0402/1%
    OE_0
    SEL1
    SEL0
    R110 475E/0603/1%

    PCIE1 R95
    33E/0402/1%
    PCIEN1 R99

    11

    PCIe_FPGA_REFCLK1-

    11

    R98
    R101
    78.7E/0603/1%

    R103
    78.7E/0603/1%

    PPC_SD2_REFCLK- 36
    PPC_SD2_REFCLK+ 36
    PPC_SD1_REFCLK- 35
    PPC_SD1_REFCLK+ 35

    PCIe_FPGA_REFCLK1+
    100E

    PCIe_TSI384_REFCLK- 15
    PCIe_TSI384_REFCLK+ 15

    VDDA_3.3V

    PCIE4

    33E/0402/1%
    R111

    PCIe_FPGA_REFCLK4+

    9FG108EGILF

    100E
    PCIEN4

    33E/0402/1%
    R113

    R112
    PCIe_FPGA_REFCLK4R114
    78.7E/0603/1%

    11

    R115
    78.7E/0603/1%

    VCC_3.3

    33E/0402/1%
    PCIE3

    R116

    PCIEN3

    33E/0402/1%
    R125

    R117
    R118
    R119
    R120
    R121
    R122
    R123
    4.7K/0603/1%
    4.7K/0603/1%
    4.7K/0603/1%
    4.7K/0603/1%
    4.7K/0603/1%
    4.7K/0603/1%
    4.7K/0603/1%

    PCIe_FPGA_REFCLK3+

    11

    PCIe_FPGA_REFCLK3-

    11

    100E
    R124

    OE_0
    R126
    78.7E/0603/1%

    OE_1

    R127
    78.7E/0603/1%

    OE_2
    OE_3
    OE_4
    OE_5
    OE_6

    SEL2
    SEL1
    SEL0

    33E/0402/1%
    PCIE2

    R128

    PCIe_FPGA_REFCLK2+

    11

    PCIe_FPGA_REFCLK2-

    11

    100E

    3,11

    R131

    R133

    PCIe_FPGA_REFCLK1+

    10K/0603/1%

    R129
    R134
    78.7E/0603/1%

    R135
    78.7E/0603/1%

    0.1UF/16V/0402
    C530

    PCIe_FPGA_REFCLK1R321

    3,11

    R130

    10K/0603/1%

    10K/0603/1%

    PCIEN2

    33E/0402/1%
    R132

    FPGA PCie Clock

    100E
    0.1UF/16V/0402
    C531

    11

    Reference Clock
    The common mode voltage of this differential reference clock input pair is 2/3
    MGTAVCC, or nominal 0.8V.

    GTP Reference Clock Checklist


    The following criteria must be met when choosing an oscillator for a design with GTP transceivers:
    Provide AC coupling between the oscillator output pins and the dedicated GTPA1_DUAL
    clock input pins.
    Ensure that the differential voltage swing of the reference clock is the range as specified in
    the Spartan-6 FPGA Data Sheet (the nominal range is 200 mV 2000 mV, and the nominal
    typical value is 1200 mV).

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