SYSTEM DESIGN LAB INCHARGE: Ms.

Komal Swami

INDEX
S.No. DATE TITLE SIGN REMARK

Experiment -1

Objective: Design a RTL Inverter circuit using H SPICE Simulation tool. The designing parameter the
given below (Vdd=3V; L=1um; Vin= 1V ; Vtn=1V; R1=1K; W=90.9um; kn=22um; gamma=2)

Tool:

H SPICE A-2008.0 3(32 BIT)

Theory:

Netlist:

***RTL inverter ciruit*** vdd 3 0 dc 5 vin 1 0 dc .1 R1 3 2 1k M 2 1 0 0 nmod w=90.9u l=1u .model nmod nmos (vto=1 kn=22u gamma=0.2) .dc vm 0 5 .1 .plot dc v(2) .probe .option post .end

Simulation Results:

Experiment -2
Objective: Design a RTL Inverter circuit using H SPICE Simulation tool. The designing parameter the
given below (Vdd=5V; L=1um; Vin= 1V ; Vtp= -1V; R1=1K; W=90.9um; kn=22um; gamma=0.2)

Tool:

H SPICE A-2008.0 3(32 BIT)

Theory:

Netlist:

***RTL inverter ciruit*** vdd 3 0 dc 5 vin 1 0 dc .1 R1 3 2 1k M 2 1 0 2 pmod w=90.9u l=1u .model pmod pmos (vto= -1 kp=22u gamma=0.2) .dc vm 0 5 .1 .plot dc v(2) .probe .option post .end

Simulation Results:

Experiment -3
Objective: Design a CMOS Inverter circuit using H SPICE Simulation tool. The designing parameter
the given below (Vdd=5V; Vtn=1V; gamma=0.2) Vin= 1V ; Vtp=-1V L=1um; kn=22um; W=90.9um; kn=22um;

Tool:

H SPICE A-2008.0 3(32 BIT)

Theory:

Netlist:
***cmos inverter ciruit*** vdd 3 0 dc 5 vin 1 0 dc .1 M1 2 1 0 0 nmod w=90.9u l=1u M2 3 1 2 3 pmod w=90.9u l=1u .model nmod nmos (vtn=1 kn=22u gamma=0.2) .model pmod pmos (vtp=-1 kp=22u gamma=0.2) .dc vin 0 5 .1 .plot dc v(2) .probe .option post .end

Simulation Results: