library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity keyboard is
port(clock :in std_logic;
--??????
R_line : in std_logic_vector(3 downto 0); --????
R_row : out std_logic_vector(3 downto 0);
--????
num : out integer range 0 to 16 );
--?????????
end entity;
architecture behav of Keyboard is
----------------------------------------------------------component div is
port(clkin:in std_logic;
clk_div:out std_logic);
end component;
-----------------------------------------------------------component xiaod is
--????
port(CLK_XD:in std_logic;
--???????
KEY_IN:in integer range 0 to 16;
--????
KEY_OUT:out integer range 0 to 16); --?????????
end component xiaod;
------------------------------------------------------------signal counter: integer range 0 to 3;
--????????
signal counterB: integer range 0 to 3;
--????
signal Decode: std_logic_vector(0 to 7);
signal out_num: integer range 0 to 16;
signal Scan:std_logic_vector(3 downto 0);
signal clk_in:std_logic;
begin
u1: xiaod port map(CLK_XD=>clock,KEY_IN=>out_num,KEY_OUT=>num);
u2: div port map (clkin=>clock,clk_div=>clk_in);
process(clk_in)
begin
if rising_edge(clk_in) then
if counter=3 then
--????????
counter<=0;
else
counter<=counter+1;
end if;
case counter is
--????
when 0=> Scan<="1000";
when 1=> Scan<="0100";
when 2=> Scan<="0010";
when 3=> Scan<="0001";
end case;
end if;
end process;
process(clk_in)
begin
if falling_edge (clk_in) then
if R_line="0000" then
--????????????????
if counterB=3 then
counterB<=0;
out_num<=16;
else counterB<=counterB+1;
end if;
else counterB<=0;
case Decode is
--??
when "10000001" => out_num<=0;
when "10000010" => out_num<=1;

when "10000100" => out_num<=2;

when "10001000" => out_num<=3;
when "01000001" => out_num<=4;
when "01000010" => out_num<=5;
when "01000100" => out_num<=6;
when "01001000" => out_num<=7;
when "00100001" => out_num<=8;
when "00100010" => out_num<=9;
when "00100100" => out_num<=10;
when "00101000" => out_num<=11;
when "00010001" => out_num<=12;
when "00010010" => out_num<=13;
when "00010100" => out_num<=14;
when "00011000" => out_num<=15;
when others => out_num<=out_num;
end case;
end if;
end if;
end process;
Decode<=Scan&R_line;
R_row<=Scan;
end architecture

--????

-- ??