Cycle stealing is used to describe the "stealing" of a single CPU cycle, for exa mple, to allow a DMA controller

to perform a DMA operation. This is opposed to b lock operation where a DMA controller would request a bus, hold it for a complet e transaction (typically 16-32 bytes but could last much longer) before releasin g to a CPU. Cycle stealing generally occurs when the entire DMA transfer of data is finished , the DMA controller interrupts the CPU. A CPU design technique that periodically "grabs" machine cycles from the main pr ocessor usually by some peripheral control unit, such as a DMA (direct memory ac cess) device. In this way, processing and peripheral operations can be performed concurrently or with some degree of overlap