Computer Arithmetic

COMPUTER ARITHMETIC

Arithmetic with Signed-2's Complement Numbers Multiplication and Division Floating-Point Arithmetic Operations Decimal Arithmetic Unit Decimal Arithmetic Operations

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Addition and Subtraction

SIGNED MAGNITUDEADDITION AND SUBTRACTION

Addition: A + B ; A: Augend; B: Addend Subtraction: A - B: A: Minuend; B: Subtrahend
Operation (+A) + (+B) (+A) + (- B) (- A) + (+B) (- A) + (- B) (+A) - (+B) (+A) - (- B) (- A) - (+B) (- A) - (- B) Add Magnitude +(A + B) +(A - B) - (A - B) - (A + B) +(A - B) +(A + B) - (A + B) - (A - B) +(B - A) +(A - B) - (B - A) +(A - B) - (B - A) +(B - A) +(A - B) +(A - B) Subtract Magnitude When A>B When A<B When A=B

Hardware Implementation

Bs

B Register

AVF E Output Carry

Complementer Parallel Adder S As A Register

M(Mode Control) Input Carry Load Sum Computer Architectures Lab

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Addition and Subtraction

SIGNED 2S COMPLEMENT ADDITION AND SUBTRACTION

Hardware
B Register

V Overflow

Complementer and Parallel Adder

AC

Algorithm
Subtract Add

Minuend in AC Subtrahend in B

Augend in AC Addend in B AC AC + B V overflow END Computer Architectures Lab

AC AC + B+ 1 V overflow END Computer Organization

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Multiplication

MULTIPLICATION
Multiplication: B * A; B: Multiplicand; A: Multiplier; P: Partial Product Multiplication of Unsigned Positive Numbers A = An-1An-2 ... A0 B = Bn-1Bn-2 ... B0

P=B*A n-1 = B * ( 2i * Ai )
i=0

= An-1 * (B2n-1) + An-2 * (B2n-2) + ... + A0 * (B20)

B shifted left n-1 bits B shifted left n-2 bits B shifted left 0 bits = A

Or
B shifted (n-1) bits to the left

P = An-1*(B2n-1 * 20) + An-2*(B2n-1 * 2-1) + ... + A0*(B2n-1 * 2-(n-1))

B2n-1 B2n-1 shifted right 1 bit B2n-1 shifted right (n-1) bits Computer Architectures Lab

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Multiplication

EXAMPLE

Multiplicand B=10111

SC

Multiplier in Q Q0 = 1; add B First partial product Shift right EAQ Q0 = 1; add B Second Partial Product Shift right EAQ Q0 = 0; shift right EAQ Q0 = 0; shift right EAQ Q0 = 1; add B Fifth partial product Shift right EAQ Final Product in AQ = 0110110101

0 0 0 1 0 0 0 0 0

00000 10111 10111 01011 10111 00010 10001 01000 00100 10111 11011 01101

10011 11001 01100 10110 01011 10101

101 100 011 010 001 000

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Multiplication

SIGNED MAGNITUDE MULTIPLICATION

Hardware
Bs B Register Complementer and Parallel Adder As 0 E AC Qs Q Register Qn Sequence Counter

EAQ
B <- Multiplicand B Q <- MultiplierA

Algorithm
As,Qs <- Qs Bs A <- 0, E <- 0 SC <- n-1 = 0 Q =1 0 EA <- A + B shr EAQ SC <- SC+1

END Product in AQ

=0 =0 SC

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BOOTH MULTIPLICATION ALGORITHM FOR SIGNED 2S COMPLEMENT

Multiplier Strings of 0s: No addition; Simply shifts Strings of 1s: String of 1s from mp to mq: Example 001110 (14) -> p = 3, q = 1 001110 = 23+1 - 21 M * 14 = M24 - M21 Algorithm [1] Subtract multiplicand for the first least significant 1 in a string of 1s in the multiplier [2] Add multiplicand for the first 0 after the string of 1s in the multiplier [3] Partial Product does not change when the multiplier bit is identical to the previous bit 110010 = -24 + 22 - 21 = -16 + 4 - 2 = -14 2p+1 - 2q

Multiplication

subtract 24

Add 22

subtract 21 Computer Architectures Lab

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Multiplication

BOOTH ALGORITHM FOR SIGNED 2S COMPLEMENT

B <- Multiplicand B Q <- Multiplier A AC <- 0 Q-1 <- 0 SC <- n 10 Q0Q-1 ? 11 00 AC<-AC+B+1 AC <- AC + B 01

Q-1 : shifted out bit on shr of Q

ashr(AC&Q) SC <- SC + 1 0

SC ? =0 END

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Multiplication

EXAMPLE OF BOOTH MULTIPLIER

Q0Q-1 10 11 01

B = 10111 B+1=01001 Initial Subtract B ashr ashr Add B ashr ashr Subtract B ashr

00 10

AC 00000 01001 01001 00100 00010 10111 11001 11100 11110 01001 00111 00011

Q 10011 11001 01100 10110 01011 10101

Q-1 0 1 1 0 0 1

SC 101 100 011 010 001 000

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Multiplication

ARRAY MULTIPLIER
A = a1a0: Multiplier B = b1b0: Multiplicand C = B * A = c3c2c1c0 c3 a1b1 c2 b1 b0 a1 a0 a0b1 a0b0 a1b0 c1 c0 b1 b0

a0
b1 b0

a1

HA C S

HA C S

c3
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c2

c1 c0
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Multiplication

ARRAY MULTIPLIER 4-BIT X 3-BIT

a0 a1 b3 b2 b1 b0 0
Addend Augend

b3

b2

b1

b0

4-bit Adder
Sum and Carry Outputs

a2 b3 b2 b1 b0

Addend

Augend

4-bit Adder
Sum and Carry Outputs

c6
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c5

c4

c3

c2

c1

c0
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Division

DIVISION
A/B=Q+R A: Dividend; B: Divisor; Q: Quotient; R: Remainder
Divisor B = 10001, B+ 1 = 01111 E A Q 01110 00000 Dividend: 0 11100 00000 shl EAQ 01111 add B+1 1 01011 E=1 1 01011 00001 Set Q0=1 0 10110 00010 shl EAQ 01111 Add B+1 1 00101 E=1 1 00101 00011 Set Q0=1 0 01010 00110 shl EAQ 01111 add B+1 0 11001 00110 E=0; Q0=0 10001 add B 1 01010 restore remainder 0 10100 01100 shl EAQ 01111 add B+1 1 00011 E=1 1 00011 01101 Set Q0=1 0 00110 11010 shl EAQ 01111 add B+1 0 10101 11010 E=0; Q0=0 10001 add B 1 00110 11010 restore remainder neglect E 00110 remainder in A 11010 quotient in Q Computer Organization SC 5

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Division

FLOWCHART OF DIVIDE OPERATION

Dividend in AQ Divisor in B

Qs As Bs SC<- n - 1 EA A + B+1 1 E 0

shl EAQ E EA A+B+1 E 1 0(A<B) A B Q0 1 A A+B+1

A B
EA A+B DVF 1

A<B
EA A+B DVF 0

EA A+B

SC SC-1 0 END (Divide overflow) END (Quotient in Q Remainder in R) Computer Organization Computer Architectures Lab 0

SC

Computer Arithmetic

Floating Point Arithmetic

FLOATING POINT ARITHMETIC OPERATIONS

F = m x re where m: Mantissa r: Radix e: Exponent

Registers for Floating Point Arithmetic

Bs

b Parallel Adder and Comparator

BR

Parallel Adder

As A1

AC

Qs

QR

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Floating Point Arithmetic

FLOATING POINT ADD AND AUBTRACT

C H E C K F O R 0 0 EA<-A+B+1 A<-A+1 As<-As 0 0 A1 shl A a<-a+1 END Computer Organization Computer Architectures Lab E 1 A =0 Normalization AC<-0 E shr A A1<-E a<-a+1 EA<-A+B =0 BR 0 AC =0 AC<-BR add op sub As<-As 0 a<b shr A a <- a+1 sub op a:b a>b shr B b <- b+1 add Align Mantissa

As Bs

As Bs 0

+ or - of mantissa

Computer Arithmetic

Floating Point Arithmetic

FLOATING POINT MULTIPLICATION

BR <- Multiplicand QR <- Multiplier =0 BR 0 QR

=0

0
AC <- 0

a <- q a <- a+b a <- a-bias

Multiply mantissa (finxed point multiplication) shl AQ a <- a-1 0 A1 1 END (Product is in AC)

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Floating Point Arithmetic

FLOATING POINT DIVISION

BR<-Divisor AC<-Dividend =0 =0 BR 0 AC 0

QR <- 0 divide by 0

Qs <- As + Bs Q<-0 SC<-n-1 EA <- A+B+1 1 A>=B A <- A+B shr A a <- a+1 a <- a+b+1 a <- a+bias q <- a Divide Magnitude of mantissa as in fixed point numbers E 0 A<B A <- A+B

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BCD Arithmetic

BCD ADD
BCD digit < 10 BCD digit + BCD digit + carry =< 19
K 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 Binary Sum Z8 Z4 Z2 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 1 Z1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 C 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 BCD Sum S8 S4 S2 S1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Computer Architectures Lab

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BCD Arithmetic

BCD ADDER
If we can convert Binary Sums to BCD Sum , we can use a binary adder to add two BCD numbers SUM =< 9 BCD Sum = Binary Sum BCD Carry = Binary Carry
4-bit Binary Add 1 K 0

19 >= SUM > 9 BCD Sum = Binary Sum + 0110 BCD Carry = Carry(Binary Sum + 0110)

Take next higher digit

Z8 1

1 1 BCD Sum<-Sum + 0110 BCD C<-Carry(BCD Sum)

Z4 0 Z2 0

done ? END BCD Sum = Sum BCD C<-Carry(Sum)

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BCD Arithmetic

BCD ADDER HARDWARE

Addend Augend

Carry Out

4-bit Binary Addr Z8 Z4 Z2 Z1

Carry In

BCD Carry

0 0110 4-bit Binary Adder

S8 S4 S2 S1 Computer Organization Computer Architectures Lab

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Decimal Arithmetic

DECIMAL ARITHMETIC OPERATIONS

Addition - Identical to the BCD addition - 9s complement and 10s complement are identical to 1s complement and 10s complement, respectively

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